X86ISelLowering.cpp revision e80aa7c783ab27711505b540597d83e038fc6900
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// Forward declarations. 57static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 58 SDValue V2); 59 60/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 61/// sets things up to match to an AVX VEXTRACTF128 instruction or a 62/// simple subregister reference. Idx is an index in the 128 bits we 63/// want. It need not be aligned to a 128-bit bounday. That makes 64/// lowering EXTRACT_VECTOR_ELT operations easier. 65static SDValue Extract128BitVector(SDValue Vec, 66 SDValue Idx, 67 SelectionDAG &DAG, 68 DebugLoc dl) { 69 EVT VT = Vec.getValueType(); 70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 71 EVT ElVT = VT.getVectorElementType(); 72 int Factor = VT.getSizeInBits()/128; 73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 74 VT.getVectorNumElements()/Factor); 75 76 // Extract from UNDEF is UNDEF. 77 if (Vec.getOpcode() == ISD::UNDEF) 78 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 79 80 if (isa<ConstantSDNode>(Idx)) { 81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 82 83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 84 // we can match to VEXTRACTF128. 85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 86 87 // This is the index of the first element of the 128-bit chunk 88 // we want. 89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 90 * ElemsPerChunk); 91 92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 94 VecIdx); 95 96 return Result; 97 } 98 99 return SDValue(); 100} 101 102/// Generate a DAG to put 128-bits into a vector > 128 bits. This 103/// sets things up to match to an AVX VINSERTF128 instruction or a 104/// simple superregister reference. Idx is an index in the 128 bits 105/// we want. It need not be aligned to a 128-bit bounday. That makes 106/// lowering INSERT_VECTOR_ELT operations easier. 107static SDValue Insert128BitVector(SDValue Result, 108 SDValue Vec, 109 SDValue Idx, 110 SelectionDAG &DAG, 111 DebugLoc dl) { 112 if (isa<ConstantSDNode>(Idx)) { 113 EVT VT = Vec.getValueType(); 114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 115 116 EVT ElVT = VT.getVectorElementType(); 117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 118 EVT ResultVT = Result.getValueType(); 119 120 // Insert the relevant 128 bits. 121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 122 123 // This is the index of the first element of the 128-bit chunk 124 // we want. 125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 126 * ElemsPerChunk); 127 128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 130 VecIdx); 131 return Result; 132 } 133 134 return SDValue(); 135} 136 137static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 139 bool is64Bit = Subtarget->is64Bit(); 140 141 if (Subtarget->isTargetEnvMacho()) { 142 if (is64Bit) 143 return new X8664_MachoTargetObjectFile(); 144 return new TargetLoweringObjectFileMachO(); 145 } 146 147 if (Subtarget->isTargetELF()) 148 return new TargetLoweringObjectFileELF(); 149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 150 return new TargetLoweringObjectFileCOFF(); 151 llvm_unreachable("unknown subtarget type"); 152} 153 154X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 155 : TargetLowering(TM, createTLOF(TM)) { 156 Subtarget = &TM.getSubtarget<X86Subtarget>(); 157 X86ScalarSSEf64 = Subtarget->hasSSE2(); 158 X86ScalarSSEf32 = Subtarget->hasSSE1(); 159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 160 161 RegInfo = TM.getRegisterInfo(); 162 TD = getTargetData(); 163 164 // Set up the TargetLowering object. 165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 166 167 // X86 is weird, it always uses i8 for shift amounts and setcc results. 168 setBooleanContents(ZeroOrOneBooleanContent); 169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 171 172 // For 64-bit since we have so many registers use the ILP scheduler, for 173 // 32-bit code use the register pressure specific scheduling. 174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling. 175 if (Subtarget->is64Bit()) 176 setSchedulingPreference(Sched::ILP); 177 else if (Subtarget->isAtom()) 178 setSchedulingPreference(Sched::Hybrid); 179 else 180 setSchedulingPreference(Sched::RegPressure); 181 setStackPointerRegisterToSaveRestore(X86StackPtr); 182 183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 184 // Setup Windows compiler runtime calls. 185 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 187 setLibcallName(RTLIB::SREM_I64, "_allrem"); 188 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 189 setLibcallName(RTLIB::MUL_I64, "_allmul"); 190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 195 196 // The _ftol2 runtime function has an unusual calling conv, which 197 // is modeled by a special pseudo-instruction. 198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 202 } 203 204 if (Subtarget->isTargetDarwin()) { 205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 206 setUseUnderscoreSetJmp(false); 207 setUseUnderscoreLongJmp(false); 208 } else if (Subtarget->isTargetMingw()) { 209 // MS runtime is weird: it exports _setjmp, but longjmp! 210 setUseUnderscoreSetJmp(true); 211 setUseUnderscoreLongJmp(false); 212 } else { 213 setUseUnderscoreSetJmp(true); 214 setUseUnderscoreLongJmp(true); 215 } 216 217 // Set up the register classes. 218 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 219 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 220 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 221 if (Subtarget->is64Bit()) 222 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 223 224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 225 226 // We don't accept any truncstore of integer registers. 227 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 228 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 230 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 232 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 233 234 // SETOEQ and SETUNE require checking two conditions. 235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 241 242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 243 // operation. 244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 247 248 if (Subtarget->is64Bit()) { 249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 251 } else if (!TM.Options.UseSoftFloat) { 252 // We have an algorithm for SSE2->double, and we turn this into a 253 // 64-bit FILD followed by conditional FADD for other targets. 254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 255 // We have an algorithm for SSE2, and we turn this into a 64-bit 256 // FILD for other targets. 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 258 } 259 260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 261 // this operation. 262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 264 265 if (!TM.Options.UseSoftFloat) { 266 // SSE has no i16 to fp conversion, only i32 267 if (X86ScalarSSEf32) { 268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 269 // f32 and f64 cases are Legal, f80 case is not 270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 271 } else { 272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 274 } 275 } else { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 278 } 279 280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 281 // are Legal, f80 is custom lowered. 282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 284 285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 286 // this operation. 287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 289 290 if (X86ScalarSSEf32) { 291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 292 // f32 and f64 cases are Legal, f80 case is not 293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 294 } else { 295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 297 } 298 299 // Handle FP_TO_UINT by promoting the destination to a larger signed 300 // conversion. 301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 304 305 if (Subtarget->is64Bit()) { 306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 308 } else if (!TM.Options.UseSoftFloat) { 309 // Since AVX is a superset of SSE3, only check for SSE here. 310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 311 // Expand FP_TO_UINT into a select. 312 // FIXME: We would like to use a Custom expander here eventually to do 313 // the optimal thing for SSE vs. the default expansion in the legalizer. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 315 else 316 // With SSE3 we can use fisttpll to convert to a signed i64; without 317 // SSE, we're stuck with a fistpll. 318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 319 } 320 321 if (isTargetFTOL()) { 322 // Use the _ftol2 runtime function, which has a pseudo-instruction 323 // to handle its weird calling convention. 324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 325 } 326 327 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 328 if (!X86ScalarSSEf64) { 329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 331 if (Subtarget->is64Bit()) { 332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 333 // Without SSE, i64->f64 goes through memory. 334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 335 } 336 } 337 338 // Scalar integer divide and remainder are lowered to use operations that 339 // produce two results, to match the available instructions. This exposes 340 // the two-result form to trivial CSE, which is able to combine x/y and x%y 341 // into a single instruction. 342 // 343 // Scalar integer multiply-high is also lowered to use two-result 344 // operations, to match the available instructions. However, plain multiply 345 // (low) operations are left as Legal, as there are single-result 346 // instructions for this in x86. Using the two-result multiply instructions 347 // when both high and low results are needed must be arranged by dagcombine. 348 for (unsigned i = 0, e = 4; i != e; ++i) { 349 MVT VT = IntVTs[i]; 350 setOperationAction(ISD::MULHS, VT, Expand); 351 setOperationAction(ISD::MULHU, VT, Expand); 352 setOperationAction(ISD::SDIV, VT, Expand); 353 setOperationAction(ISD::UDIV, VT, Expand); 354 setOperationAction(ISD::SREM, VT, Expand); 355 setOperationAction(ISD::UREM, VT, Expand); 356 357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 358 setOperationAction(ISD::ADDC, VT, Custom); 359 setOperationAction(ISD::ADDE, VT, Custom); 360 setOperationAction(ISD::SUBC, VT, Custom); 361 setOperationAction(ISD::SUBE, VT, Custom); 362 } 363 364 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 365 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 366 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 368 if (Subtarget->is64Bit()) 369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 374 setOperationAction(ISD::FREM , MVT::f32 , Expand); 375 setOperationAction(ISD::FREM , MVT::f64 , Expand); 376 setOperationAction(ISD::FREM , MVT::f80 , Expand); 377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 378 379 // Promote the i8 variants and force them on up to i32 which has a shorter 380 // encoding. 381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 385 if (Subtarget->hasBMI()) { 386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 388 if (Subtarget->is64Bit()) 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 390 } else { 391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 393 if (Subtarget->is64Bit()) 394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 395 } 396 397 if (Subtarget->hasLZCNT()) { 398 // When promoting the i8 variants, force them to i32 for a shorter 399 // encoding. 400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 406 if (Subtarget->is64Bit()) 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 408 } else { 409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 415 if (Subtarget->is64Bit()) { 416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 418 } 419 } 420 421 if (Subtarget->hasPOPCNT()) { 422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 423 } else { 424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 427 if (Subtarget->is64Bit()) 428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 429 } 430 431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 433 434 // These should be promoted to a larger select which is supported. 435 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 436 // X86 wants to expand cmov itself. 437 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 438 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 439 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 440 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 441 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 442 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 443 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 444 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 446 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 447 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 448 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 449 if (Subtarget->is64Bit()) { 450 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 451 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 452 } 453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 454 455 // Darwin ABI issue. 456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 460 if (Subtarget->is64Bit()) 461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 464 if (Subtarget->is64Bit()) { 465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 470 } 471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 475 if (Subtarget->is64Bit()) { 476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 479 } 480 481 if (Subtarget->hasSSE1()) 482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 483 484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 486 487 // On X86 and X86-64, atomic operations are lowered to locked instructions. 488 // Locked instructions, in turn, have implicit fence semantics (all memory 489 // operations are flushed before issuing the locked instruction, and they 490 // are not buffered), so we can fold away the common pattern of 491 // fence-atomic-fence. 492 setShouldFoldAtomicFences(true); 493 494 // Expand certain atomics 495 for (unsigned i = 0, e = 4; i != e; ++i) { 496 MVT VT = IntVTs[i]; 497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 500 } 501 502 if (!Subtarget->is64Bit()) { 503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 511 } 512 513 if (Subtarget->hasCmpxchg16b()) { 514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 515 } 516 517 // FIXME - use subtarget debug flags 518 if (!Subtarget->isTargetDarwin() && 519 !Subtarget->isTargetELF() && 520 !Subtarget->isTargetCygMing()) { 521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 522 } 523 524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 528 if (Subtarget->is64Bit()) { 529 setExceptionPointerRegister(X86::RAX); 530 setExceptionSelectorRegister(X86::RDX); 531 } else { 532 setExceptionPointerRegister(X86::EAX); 533 setExceptionSelectorRegister(X86::EDX); 534 } 535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 537 538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 540 541 setOperationAction(ISD::TRAP, MVT::Other, Legal); 542 543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 544 setOperationAction(ISD::VASTART , MVT::Other, Custom); 545 setOperationAction(ISD::VAEND , MVT::Other, Expand); 546 if (Subtarget->is64Bit()) { 547 setOperationAction(ISD::VAARG , MVT::Other, Custom); 548 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 549 } else { 550 setOperationAction(ISD::VAARG , MVT::Other, Expand); 551 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 552 } 553 554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 556 557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 559 MVT::i64 : MVT::i32, Custom); 560 else if (TM.Options.EnableSegmentedStacks) 561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 562 MVT::i64 : MVT::i32, Custom); 563 else 564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 565 MVT::i64 : MVT::i32, Expand); 566 567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 568 // f32 and f64 use SSE. 569 // Set up the FP register classes. 570 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 571 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 572 573 // Use ANDPD to simulate FABS. 574 setOperationAction(ISD::FABS , MVT::f64, Custom); 575 setOperationAction(ISD::FABS , MVT::f32, Custom); 576 577 // Use XORP to simulate FNEG. 578 setOperationAction(ISD::FNEG , MVT::f64, Custom); 579 setOperationAction(ISD::FNEG , MVT::f32, Custom); 580 581 // Use ANDPD and ORPD to simulate FCOPYSIGN. 582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 584 585 // Lower this to FGETSIGNx86 plus an AND. 586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 588 589 // We don't support sin/cos/fmod 590 setOperationAction(ISD::FSIN , MVT::f64, Expand); 591 setOperationAction(ISD::FCOS , MVT::f64, Expand); 592 setOperationAction(ISD::FSIN , MVT::f32, Expand); 593 setOperationAction(ISD::FCOS , MVT::f32, Expand); 594 595 // Expand FP immediates into loads from the stack, except for the special 596 // cases we handle. 597 addLegalFPImmediate(APFloat(+0.0)); // xorpd 598 addLegalFPImmediate(APFloat(+0.0f)); // xorps 599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 600 // Use SSE for f32, x87 for f64. 601 // Set up the FP register classes. 602 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 604 605 // Use ANDPS to simulate FABS. 606 setOperationAction(ISD::FABS , MVT::f32, Custom); 607 608 // Use XORP to simulate FNEG. 609 setOperationAction(ISD::FNEG , MVT::f32, Custom); 610 611 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 612 613 // Use ANDPS and ORPS to simulate FCOPYSIGN. 614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 616 617 // We don't support sin/cos/fmod 618 setOperationAction(ISD::FSIN , MVT::f32, Expand); 619 setOperationAction(ISD::FCOS , MVT::f32, Expand); 620 621 // Special cases we handle for FP constants. 622 addLegalFPImmediate(APFloat(+0.0f)); // xorps 623 addLegalFPImmediate(APFloat(+0.0)); // FLD0 624 addLegalFPImmediate(APFloat(+1.0)); // FLD1 625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 627 628 if (!TM.Options.UnsafeFPMath) { 629 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 630 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 631 } 632 } else if (!TM.Options.UseSoftFloat) { 633 // f32 and f64 in x87. 634 // Set up the FP register classes. 635 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 636 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 637 638 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 639 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 642 643 if (!TM.Options.UnsafeFPMath) { 644 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 645 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 646 } 647 addLegalFPImmediate(APFloat(+0.0)); // FLD0 648 addLegalFPImmediate(APFloat(+1.0)); // FLD1 649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 655 } 656 657 // We don't support FMA. 658 setOperationAction(ISD::FMA, MVT::f64, Expand); 659 setOperationAction(ISD::FMA, MVT::f32, Expand); 660 661 // Long double always uses X87. 662 if (!TM.Options.UseSoftFloat) { 663 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 664 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 666 { 667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 668 addLegalFPImmediate(TmpFlt); // FLD0 669 TmpFlt.changeSign(); 670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 671 672 bool ignored; 673 APFloat TmpFlt2(+1.0); 674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 675 &ignored); 676 addLegalFPImmediate(TmpFlt2); // FLD1 677 TmpFlt2.changeSign(); 678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 679 } 680 681 if (!TM.Options.UnsafeFPMath) { 682 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 683 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 684 } 685 686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 687 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 689 setOperationAction(ISD::FRINT, MVT::f80, Expand); 690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 691 setOperationAction(ISD::FMA, MVT::f80, Expand); 692 } 693 694 // Always use a library call for pow. 695 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 696 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 697 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 698 699 setOperationAction(ISD::FLOG, MVT::f80, Expand); 700 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 701 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 702 setOperationAction(ISD::FEXP, MVT::f80, Expand); 703 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 704 705 // First set operation action for all vector types to either promote 706 // (for widening) or expand (for scalarization). Then we will selectively 707 // turn on ones that can be effectively codegen'd. 708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 769 setTruncStoreAction((MVT::SimpleValueType)VT, 770 (MVT::SimpleValueType)InnerVT, Expand); 771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 774 } 775 776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 777 // with -msoft-float, disable use of MMX as well. 778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 779 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 780 // No operations on x86mmx supported, everything uses intrinsics. 781 } 782 783 // MMX-sized vectors (other than x86mmx) are expected to be expanded 784 // into smaller operations. 785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 789 setOperationAction(ISD::AND, MVT::v8i8, Expand); 790 setOperationAction(ISD::AND, MVT::v4i16, Expand); 791 setOperationAction(ISD::AND, MVT::v2i32, Expand); 792 setOperationAction(ISD::AND, MVT::v1i64, Expand); 793 setOperationAction(ISD::OR, MVT::v8i8, Expand); 794 setOperationAction(ISD::OR, MVT::v4i16, Expand); 795 setOperationAction(ISD::OR, MVT::v2i32, Expand); 796 setOperationAction(ISD::OR, MVT::v1i64, Expand); 797 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 798 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 799 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 800 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 814 815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 816 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 817 818 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 830 } 831 832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 833 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 834 835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 836 // registers cannot be used even for integer operations. 837 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 838 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 839 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 840 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 841 842 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 843 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 844 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 845 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 846 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 847 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 848 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 849 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 850 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 851 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 852 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 858 859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 863 864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 869 870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 875 876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 878 EVT VT = (MVT::SimpleValueType)i; 879 // Do not attempt to custom lower non-power-of-2 vectors 880 if (!isPowerOf2_32(VT.getVectorNumElements())) 881 continue; 882 // Do not attempt to custom lower non-128-bit vectors 883 if (!VT.is128BitVector()) 884 continue; 885 setOperationAction(ISD::BUILD_VECTOR, 886 VT.getSimpleVT().SimpleTy, Custom); 887 setOperationAction(ISD::VECTOR_SHUFFLE, 888 VT.getSimpleVT().SimpleTy, Custom); 889 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 890 VT.getSimpleVT().SimpleTy, Custom); 891 } 892 893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 899 900 if (Subtarget->is64Bit()) { 901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 903 } 904 905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 908 EVT VT = SVT; 909 910 // Do not attempt to promote non-128-bit vectors 911 if (!VT.is128BitVector()) 912 continue; 913 914 setOperationAction(ISD::AND, SVT, Promote); 915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 916 setOperationAction(ISD::OR, SVT, Promote); 917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 918 setOperationAction(ISD::XOR, SVT, Promote); 919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 920 setOperationAction(ISD::LOAD, SVT, Promote); 921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 922 setOperationAction(ISD::SELECT, SVT, Promote); 923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 924 } 925 926 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 927 928 // Custom lower v2i64 and v2f64 selects. 929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 933 934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 936 } 937 938 if (Subtarget->hasSSE41()) { 939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 940 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 942 setOperationAction(ISD::FRINT, MVT::f32, Legal); 943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 945 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 947 setOperationAction(ISD::FRINT, MVT::f64, Legal); 948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 949 950 // FIXME: Do we need to handle scalar-to-vector here? 951 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 952 953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 958 959 // i8 and i16 vectors are custom , because the source register and source 960 // source memory operand types are not the same width. f32 vectors are 961 // custom since the immediate controlling the insert encodes additional 962 // information. 963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 967 968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 972 973 // FIXME: these should be Legal but thats only for the case where 974 // the index is constant. For now custom expand to deal with that. 975 if (Subtarget->is64Bit()) { 976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 978 } 979 } 980 981 if (Subtarget->hasSSE2()) { 982 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 983 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 984 985 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 986 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 987 988 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 989 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 990 991 if (Subtarget->hasAVX2()) { 992 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 993 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 994 995 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 996 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 997 998 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 999 } else { 1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1002 1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1005 1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1007 } 1008 } 1009 1010 if (Subtarget->hasSSE42()) 1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1012 1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1014 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1015 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1016 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1017 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1018 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1019 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1020 1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1024 1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1031 1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1038 1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1042 1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1049 1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1052 1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1055 1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1058 1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1063 1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1067 1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1072 1073 if (Subtarget->hasAVX2()) { 1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1078 1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1083 1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1087 // Don't lower v32i8 because there is no 128-bit byte mul 1088 1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1090 1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1093 1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1096 1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1098 } else { 1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1103 1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1108 1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1112 // Don't lower v32i8 because there is no 128-bit byte mul 1113 1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1116 1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1119 1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1121 } 1122 1123 // Custom lower several nodes for 256-bit types. 1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1127 EVT VT = SVT; 1128 1129 // Extract subvector is special because the value type 1130 // (result) is 128-bit but the source is 256-bit wide. 1131 if (VT.is128BitVector()) 1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1133 1134 // Do not attempt to custom lower other non-256-bit vectors 1135 if (!VT.is256BitVector()) 1136 continue; 1137 1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1144 } 1145 1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1149 EVT VT = SVT; 1150 1151 // Do not attempt to promote non-256-bit vectors 1152 if (!VT.is256BitVector()) 1153 continue; 1154 1155 setOperationAction(ISD::AND, SVT, Promote); 1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1157 setOperationAction(ISD::OR, SVT, Promote); 1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1159 setOperationAction(ISD::XOR, SVT, Promote); 1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1161 setOperationAction(ISD::LOAD, SVT, Promote); 1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1163 setOperationAction(ISD::SELECT, SVT, Promote); 1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1165 } 1166 } 1167 1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1169 // of this type with custom code. 1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1173 Custom); 1174 } 1175 1176 // We want to custom lower some of our intrinsics. 1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1178 1179 1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1181 // handle type legalization for these operations here. 1182 // 1183 // FIXME: We really should do custom legalization for addition and 1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1185 // than generic legalization for 64-bit multiplication-with-overflow, though. 1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1187 // Add/Sub/Mul with overflow operations are custom lowered. 1188 MVT VT = IntVTs[i]; 1189 setOperationAction(ISD::SADDO, VT, Custom); 1190 setOperationAction(ISD::UADDO, VT, Custom); 1191 setOperationAction(ISD::SSUBO, VT, Custom); 1192 setOperationAction(ISD::USUBO, VT, Custom); 1193 setOperationAction(ISD::SMULO, VT, Custom); 1194 setOperationAction(ISD::UMULO, VT, Custom); 1195 } 1196 1197 // There are no 8-bit 3-address imul/mul instructions 1198 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1199 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1200 1201 if (!Subtarget->is64Bit()) { 1202 // These libcalls are not available in 32-bit. 1203 setLibcallName(RTLIB::SHL_I128, 0); 1204 setLibcallName(RTLIB::SRL_I128, 0); 1205 setLibcallName(RTLIB::SRA_I128, 0); 1206 } 1207 1208 // We have target-specific dag combine patterns for the following nodes: 1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1211 setTargetDAGCombine(ISD::VSELECT); 1212 setTargetDAGCombine(ISD::SELECT); 1213 setTargetDAGCombine(ISD::SHL); 1214 setTargetDAGCombine(ISD::SRA); 1215 setTargetDAGCombine(ISD::SRL); 1216 setTargetDAGCombine(ISD::OR); 1217 setTargetDAGCombine(ISD::AND); 1218 setTargetDAGCombine(ISD::ADD); 1219 setTargetDAGCombine(ISD::FADD); 1220 setTargetDAGCombine(ISD::FSUB); 1221 setTargetDAGCombine(ISD::SUB); 1222 setTargetDAGCombine(ISD::LOAD); 1223 setTargetDAGCombine(ISD::STORE); 1224 setTargetDAGCombine(ISD::ZERO_EXTEND); 1225 setTargetDAGCombine(ISD::SIGN_EXTEND); 1226 setTargetDAGCombine(ISD::TRUNCATE); 1227 setTargetDAGCombine(ISD::SINT_TO_FP); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279 return; 1280} 1281 1282/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1283/// function arguments in the caller parameter area. For X86, aggregates 1284/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1285/// are at 4-byte boundaries. 1286unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1287 if (Subtarget->is64Bit()) { 1288 // Max of 8 and alignment of type. 1289 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1290 if (TyAlign > 8) 1291 return TyAlign; 1292 return 8; 1293 } 1294 1295 unsigned Align = 4; 1296 if (Subtarget->hasSSE1()) 1297 getMaxByValAlign(Ty, Align); 1298 return Align; 1299} 1300 1301/// getOptimalMemOpType - Returns the target specific optimal type for load 1302/// and store operations as a result of memset, memcpy, and memmove 1303/// lowering. If DstAlign is zero that means it's safe to destination 1304/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1305/// means there isn't a need to check it against alignment requirement, 1306/// probably because the source does not need to be loaded. If 1307/// 'IsZeroVal' is true, that means it's safe to return a 1308/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1309/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1310/// constant so it does not need to be loaded. 1311/// It returns EVT::Other if the type should be determined using generic 1312/// target-independent logic. 1313EVT 1314X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1315 unsigned DstAlign, unsigned SrcAlign, 1316 bool IsZeroVal, 1317 bool MemcpyStrSrc, 1318 MachineFunction &MF) const { 1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1320 // linux. This is because the stack realignment code can't handle certain 1321 // cases like PR2962. This should be removed when PR2962 is fixed. 1322 const Function *F = MF.getFunction(); 1323 if (IsZeroVal && 1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1325 if (Size >= 16 && 1326 (Subtarget->isUnalignedMemAccessFast() || 1327 ((DstAlign == 0 || DstAlign >= 16) && 1328 (SrcAlign == 0 || SrcAlign >= 16))) && 1329 Subtarget->getStackAlignment() >= 16) { 1330 if (Subtarget->getStackAlignment() >= 32) { 1331 if (Subtarget->hasAVX2()) 1332 return MVT::v8i32; 1333 if (Subtarget->hasAVX()) 1334 return MVT::v8f32; 1335 } 1336 if (Subtarget->hasSSE2()) 1337 return MVT::v4i32; 1338 if (Subtarget->hasSSE1()) 1339 return MVT::v4f32; 1340 } else if (!MemcpyStrSrc && Size >= 8 && 1341 !Subtarget->is64Bit() && 1342 Subtarget->getStackAlignment() >= 8 && 1343 Subtarget->hasSSE2()) { 1344 // Do not use f64 to lower memcpy if source is string constant. It's 1345 // better to use i32 to avoid the loads. 1346 return MVT::f64; 1347 } 1348 } 1349 if (Subtarget->is64Bit() && Size >= 8) 1350 return MVT::i64; 1351 return MVT::i32; 1352} 1353 1354/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1355/// current function. The returned value is a member of the 1356/// MachineJumpTableInfo::JTEntryKind enum. 1357unsigned X86TargetLowering::getJumpTableEncoding() const { 1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1359 // symbol. 1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1361 Subtarget->isPICStyleGOT()) 1362 return MachineJumpTableInfo::EK_Custom32; 1363 1364 // Otherwise, use the normal jump table encoding heuristics. 1365 return TargetLowering::getJumpTableEncoding(); 1366} 1367 1368const MCExpr * 1369X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1370 const MachineBasicBlock *MBB, 1371 unsigned uid,MCContext &Ctx) const{ 1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1373 Subtarget->isPICStyleGOT()); 1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1375 // entries. 1376 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1377 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1378} 1379 1380/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1381/// jumptable. 1382SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1383 SelectionDAG &DAG) const { 1384 if (!Subtarget->is64Bit()) 1385 // This doesn't have DebugLoc associated with it, but is not really the 1386 // same as a Register. 1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1388 return Table; 1389} 1390 1391/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1392/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1393/// MCExpr. 1394const MCExpr *X86TargetLowering:: 1395getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1396 MCContext &Ctx) const { 1397 // X86-64 uses RIP relative addressing based on the jump table label. 1398 if (Subtarget->isPICStyleRIPRel()) 1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1400 1401 // Otherwise, the reference is relative to the PIC base. 1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1403} 1404 1405// FIXME: Why this routine is here? Move to RegInfo! 1406std::pair<const TargetRegisterClass*, uint8_t> 1407X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1408 const TargetRegisterClass *RRC = 0; 1409 uint8_t Cost = 1; 1410 switch (VT.getSimpleVT().SimpleTy) { 1411 default: 1412 return TargetLowering::findRepresentativeClass(VT); 1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1414 RRC = (Subtarget->is64Bit() 1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1416 break; 1417 case MVT::x86mmx: 1418 RRC = X86::VR64RegisterClass; 1419 break; 1420 case MVT::f32: case MVT::f64: 1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1422 case MVT::v4f32: case MVT::v2f64: 1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1424 case MVT::v4f64: 1425 RRC = X86::VR128RegisterClass; 1426 break; 1427 } 1428 return std::make_pair(RRC, Cost); 1429} 1430 1431bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1432 unsigned &Offset) const { 1433 if (!Subtarget->isTargetLinux()) 1434 return false; 1435 1436 if (Subtarget->is64Bit()) { 1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1438 Offset = 0x28; 1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1440 AddressSpace = 256; 1441 else 1442 AddressSpace = 257; 1443 } else { 1444 // %gs:0x14 on i386 1445 Offset = 0x14; 1446 AddressSpace = 256; 1447 } 1448 return true; 1449} 1450 1451 1452//===----------------------------------------------------------------------===// 1453// Return Value Calling Convention Implementation 1454//===----------------------------------------------------------------------===// 1455 1456#include "X86GenCallingConv.inc" 1457 1458bool 1459X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1460 MachineFunction &MF, bool isVarArg, 1461 const SmallVectorImpl<ISD::OutputArg> &Outs, 1462 LLVMContext &Context) const { 1463 SmallVector<CCValAssign, 16> RVLocs; 1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1465 RVLocs, Context); 1466 return CCInfo.CheckReturn(Outs, RetCC_X86); 1467} 1468 1469SDValue 1470X86TargetLowering::LowerReturn(SDValue Chain, 1471 CallingConv::ID CallConv, bool isVarArg, 1472 const SmallVectorImpl<ISD::OutputArg> &Outs, 1473 const SmallVectorImpl<SDValue> &OutVals, 1474 DebugLoc dl, SelectionDAG &DAG) const { 1475 MachineFunction &MF = DAG.getMachineFunction(); 1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1477 1478 SmallVector<CCValAssign, 16> RVLocs; 1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1480 RVLocs, *DAG.getContext()); 1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1482 1483 // Add the regs to the liveout set for the function. 1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1485 for (unsigned i = 0; i != RVLocs.size(); ++i) 1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1487 MRI.addLiveOut(RVLocs[i].getLocReg()); 1488 1489 SDValue Flag; 1490 1491 SmallVector<SDValue, 6> RetOps; 1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1493 // Operand #1 = Bytes To Pop 1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1495 MVT::i16)); 1496 1497 // Copy the result values into the output registers. 1498 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1499 CCValAssign &VA = RVLocs[i]; 1500 assert(VA.isRegLoc() && "Can only return in registers!"); 1501 SDValue ValToCopy = OutVals[i]; 1502 EVT ValVT = ValToCopy.getValueType(); 1503 1504 // If this is x86-64, and we disabled SSE, we can't return FP values, 1505 // or SSE or MMX vectors. 1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1509 report_fatal_error("SSE register return with SSE disabled"); 1510 } 1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1512 // llvm-gcc has never done it right and no one has noticed, so this 1513 // should be OK for now. 1514 if (ValVT == MVT::f64 && 1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1516 report_fatal_error("SSE2 register return with SSE2 disabled"); 1517 1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1519 // the RET instruction and handled by the FP Stackifier. 1520 if (VA.getLocReg() == X86::ST0 || 1521 VA.getLocReg() == X86::ST1) { 1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1523 // change the value to the FP stack register class. 1524 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1526 RetOps.push_back(ValToCopy); 1527 // Don't emit a copytoreg. 1528 continue; 1529 } 1530 1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1532 // which is returned in RAX / RDX. 1533 if (Subtarget->is64Bit()) { 1534 if (ValVT == MVT::x86mmx) { 1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1538 ValToCopy); 1539 // If we don't have SSE2 available, convert to v4f32 so the generated 1540 // register is legal. 1541 if (!Subtarget->hasSSE2()) 1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1543 } 1544 } 1545 } 1546 1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1548 Flag = Chain.getValue(1); 1549 } 1550 1551 // The x86-64 ABI for returning structs by value requires that we copy 1552 // the sret argument into %rax for the return. We saved the argument into 1553 // a virtual register in the entry block, so now we copy the value out 1554 // and into %rax. 1555 if (Subtarget->is64Bit() && 1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1557 MachineFunction &MF = DAG.getMachineFunction(); 1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1559 unsigned Reg = FuncInfo->getSRetReturnReg(); 1560 assert(Reg && 1561 "SRetReturnReg should have been set in LowerFormalArguments()."); 1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1563 1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1565 Flag = Chain.getValue(1); 1566 1567 // RAX now acts like a return value. 1568 MRI.addLiveOut(X86::RAX); 1569 } 1570 1571 RetOps[0] = Chain; // Update chain. 1572 1573 // Add the flag if we have it. 1574 if (Flag.getNode()) 1575 RetOps.push_back(Flag); 1576 1577 return DAG.getNode(X86ISD::RET_FLAG, dl, 1578 MVT::Other, &RetOps[0], RetOps.size()); 1579} 1580 1581bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1582 if (N->getNumValues() != 1) 1583 return false; 1584 if (!N->hasNUsesOfValue(1, 0)) 1585 return false; 1586 1587 SDNode *Copy = *N->use_begin(); 1588 if (Copy->getOpcode() == ISD::CopyToReg) { 1589 // If the copy has a glue operand, we conservatively assume it isn't safe to 1590 // perform a tail call. 1591 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1592 return false; 1593 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1594 return false; 1595 1596 bool HasRet = false; 1597 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1598 UI != UE; ++UI) { 1599 if (UI->getOpcode() != X86ISD::RET_FLAG) 1600 return false; 1601 HasRet = true; 1602 } 1603 1604 return HasRet; 1605} 1606 1607EVT 1608X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1609 ISD::NodeType ExtendKind) const { 1610 MVT ReturnMVT; 1611 // TODO: Is this also valid on 32-bit? 1612 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1613 ReturnMVT = MVT::i8; 1614 else 1615 ReturnMVT = MVT::i32; 1616 1617 EVT MinVT = getRegisterType(Context, ReturnMVT); 1618 return VT.bitsLT(MinVT) ? MinVT : VT; 1619} 1620 1621/// LowerCallResult - Lower the result values of a call into the 1622/// appropriate copies out of appropriate physical registers. 1623/// 1624SDValue 1625X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1626 CallingConv::ID CallConv, bool isVarArg, 1627 const SmallVectorImpl<ISD::InputArg> &Ins, 1628 DebugLoc dl, SelectionDAG &DAG, 1629 SmallVectorImpl<SDValue> &InVals) const { 1630 1631 // Assign locations to each value returned by this call. 1632 SmallVector<CCValAssign, 16> RVLocs; 1633 bool Is64Bit = Subtarget->is64Bit(); 1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1635 getTargetMachine(), RVLocs, *DAG.getContext()); 1636 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1637 1638 // Copy all of the result registers out of their specified physreg. 1639 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1640 CCValAssign &VA = RVLocs[i]; 1641 EVT CopyVT = VA.getValVT(); 1642 1643 // If this is x86-64, and we disabled SSE, we can't return FP values 1644 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1645 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1646 report_fatal_error("SSE register return with SSE disabled"); 1647 } 1648 1649 SDValue Val; 1650 1651 // If this is a call to a function that returns an fp value on the floating 1652 // point stack, we must guarantee the the value is popped from the stack, so 1653 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1654 // if the return value is not used. We use the FpPOP_RETVAL instruction 1655 // instead. 1656 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1657 // If we prefer to use the value in xmm registers, copy it out as f80 and 1658 // use a truncate to move it from fp stack reg to xmm reg. 1659 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1660 SDValue Ops[] = { Chain, InFlag }; 1661 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1662 MVT::Other, MVT::Glue, Ops, 2), 1); 1663 Val = Chain.getValue(0); 1664 1665 // Round the f80 to the right size, which also moves it to the appropriate 1666 // xmm register. 1667 if (CopyVT != VA.getValVT()) 1668 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1669 // This truncation won't change the value. 1670 DAG.getIntPtrConstant(1)); 1671 } else { 1672 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1673 CopyVT, InFlag).getValue(1); 1674 Val = Chain.getValue(0); 1675 } 1676 InFlag = Chain.getValue(2); 1677 InVals.push_back(Val); 1678 } 1679 1680 return Chain; 1681} 1682 1683 1684//===----------------------------------------------------------------------===// 1685// C & StdCall & Fast Calling Convention implementation 1686//===----------------------------------------------------------------------===// 1687// StdCall calling convention seems to be standard for many Windows' API 1688// routines and around. It differs from C calling convention just a little: 1689// callee should clean up the stack, not caller. Symbols should be also 1690// decorated in some fancy way :) It doesn't support any vector arguments. 1691// For info on fast calling convention see Fast Calling Convention (tail call) 1692// implementation LowerX86_32FastCCCallTo. 1693 1694/// CallIsStructReturn - Determines whether a call uses struct return 1695/// semantics. 1696static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1697 if (Outs.empty()) 1698 return false; 1699 1700 return Outs[0].Flags.isSRet(); 1701} 1702 1703/// ArgsAreStructReturn - Determines whether a function uses struct 1704/// return semantics. 1705static bool 1706ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1707 if (Ins.empty()) 1708 return false; 1709 1710 return Ins[0].Flags.isSRet(); 1711} 1712 1713/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1714/// by "Src" to address "Dst" with size and alignment information specified by 1715/// the specific parameter attribute. The copy will be passed as a byval 1716/// function parameter. 1717static SDValue 1718CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1719 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1720 DebugLoc dl) { 1721 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1722 1723 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1724 /*isVolatile*/false, /*AlwaysInline=*/true, 1725 MachinePointerInfo(), MachinePointerInfo()); 1726} 1727 1728/// IsTailCallConvention - Return true if the calling convention is one that 1729/// supports tail call optimization. 1730static bool IsTailCallConvention(CallingConv::ID CC) { 1731 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1732} 1733 1734bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1735 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1736 return false; 1737 1738 CallSite CS(CI); 1739 CallingConv::ID CalleeCC = CS.getCallingConv(); 1740 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1741 return false; 1742 1743 return true; 1744} 1745 1746/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1747/// a tailcall target by changing its ABI. 1748static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1749 bool GuaranteedTailCallOpt) { 1750 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1751} 1752 1753SDValue 1754X86TargetLowering::LowerMemArgument(SDValue Chain, 1755 CallingConv::ID CallConv, 1756 const SmallVectorImpl<ISD::InputArg> &Ins, 1757 DebugLoc dl, SelectionDAG &DAG, 1758 const CCValAssign &VA, 1759 MachineFrameInfo *MFI, 1760 unsigned i) const { 1761 // Create the nodes corresponding to a load from this parameter slot. 1762 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1763 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1764 getTargetMachine().Options.GuaranteedTailCallOpt); 1765 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1766 EVT ValVT; 1767 1768 // If value is passed by pointer we have address passed instead of the value 1769 // itself. 1770 if (VA.getLocInfo() == CCValAssign::Indirect) 1771 ValVT = VA.getLocVT(); 1772 else 1773 ValVT = VA.getValVT(); 1774 1775 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1776 // changed with more analysis. 1777 // In case of tail call optimization mark all arguments mutable. Since they 1778 // could be overwritten by lowering of arguments in case of a tail call. 1779 if (Flags.isByVal()) { 1780 unsigned Bytes = Flags.getByValSize(); 1781 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1782 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1783 return DAG.getFrameIndex(FI, getPointerTy()); 1784 } else { 1785 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1786 VA.getLocMemOffset(), isImmutable); 1787 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1788 return DAG.getLoad(ValVT, dl, Chain, FIN, 1789 MachinePointerInfo::getFixedStack(FI), 1790 false, false, false, 0); 1791 } 1792} 1793 1794SDValue 1795X86TargetLowering::LowerFormalArguments(SDValue Chain, 1796 CallingConv::ID CallConv, 1797 bool isVarArg, 1798 const SmallVectorImpl<ISD::InputArg> &Ins, 1799 DebugLoc dl, 1800 SelectionDAG &DAG, 1801 SmallVectorImpl<SDValue> &InVals) 1802 const { 1803 MachineFunction &MF = DAG.getMachineFunction(); 1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1805 1806 const Function* Fn = MF.getFunction(); 1807 if (Fn->hasExternalLinkage() && 1808 Subtarget->isTargetCygMing() && 1809 Fn->getName() == "main") 1810 FuncInfo->setForceFramePointer(true); 1811 1812 MachineFrameInfo *MFI = MF.getFrameInfo(); 1813 bool Is64Bit = Subtarget->is64Bit(); 1814 bool IsWindows = Subtarget->isTargetWindows(); 1815 bool IsWin64 = Subtarget->isTargetWin64(); 1816 1817 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1818 "Var args not supported with calling convention fastcc or ghc"); 1819 1820 // Assign locations to all of the incoming arguments. 1821 SmallVector<CCValAssign, 16> ArgLocs; 1822 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1823 ArgLocs, *DAG.getContext()); 1824 1825 // Allocate shadow area for Win64 1826 if (IsWin64) { 1827 CCInfo.AllocateStack(32, 8); 1828 } 1829 1830 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1831 1832 unsigned LastVal = ~0U; 1833 SDValue ArgValue; 1834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1835 CCValAssign &VA = ArgLocs[i]; 1836 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1837 // places. 1838 assert(VA.getValNo() != LastVal && 1839 "Don't support value assigned to multiple locs yet"); 1840 (void)LastVal; 1841 LastVal = VA.getValNo(); 1842 1843 if (VA.isRegLoc()) { 1844 EVT RegVT = VA.getLocVT(); 1845 const TargetRegisterClass *RC; 1846 if (RegVT == MVT::i32) 1847 RC = X86::GR32RegisterClass; 1848 else if (Is64Bit && RegVT == MVT::i64) 1849 RC = X86::GR64RegisterClass; 1850 else if (RegVT == MVT::f32) 1851 RC = X86::FR32RegisterClass; 1852 else if (RegVT == MVT::f64) 1853 RC = X86::FR64RegisterClass; 1854 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1855 RC = X86::VR256RegisterClass; 1856 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1857 RC = X86::VR128RegisterClass; 1858 else if (RegVT == MVT::x86mmx) 1859 RC = X86::VR64RegisterClass; 1860 else 1861 llvm_unreachable("Unknown argument type!"); 1862 1863 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1864 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1865 1866 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1867 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1868 // right size. 1869 if (VA.getLocInfo() == CCValAssign::SExt) 1870 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1871 DAG.getValueType(VA.getValVT())); 1872 else if (VA.getLocInfo() == CCValAssign::ZExt) 1873 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1874 DAG.getValueType(VA.getValVT())); 1875 else if (VA.getLocInfo() == CCValAssign::BCvt) 1876 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1877 1878 if (VA.isExtInLoc()) { 1879 // Handle MMX values passed in XMM regs. 1880 if (RegVT.isVector()) { 1881 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1882 ArgValue); 1883 } else 1884 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1885 } 1886 } else { 1887 assert(VA.isMemLoc()); 1888 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1889 } 1890 1891 // If value is passed via pointer - do a load. 1892 if (VA.getLocInfo() == CCValAssign::Indirect) 1893 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1894 MachinePointerInfo(), false, false, false, 0); 1895 1896 InVals.push_back(ArgValue); 1897 } 1898 1899 // The x86-64 ABI for returning structs by value requires that we copy 1900 // the sret argument into %rax for the return. Save the argument into 1901 // a virtual register so that we can access it from the return points. 1902 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1903 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1904 unsigned Reg = FuncInfo->getSRetReturnReg(); 1905 if (!Reg) { 1906 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1907 FuncInfo->setSRetReturnReg(Reg); 1908 } 1909 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1911 } 1912 1913 unsigned StackSize = CCInfo.getNextStackOffset(); 1914 // Align stack specially for tail calls. 1915 if (FuncIsMadeTailCallSafe(CallConv, 1916 MF.getTarget().Options.GuaranteedTailCallOpt)) 1917 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1918 1919 // If the function takes variable number of arguments, make a frame index for 1920 // the start of the first vararg value... for expansion of llvm.va_start. 1921 if (isVarArg) { 1922 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1923 CallConv != CallingConv::X86_ThisCall)) { 1924 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1925 } 1926 if (Is64Bit) { 1927 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1928 1929 // FIXME: We should really autogenerate these arrays 1930 static const uint16_t GPR64ArgRegsWin64[] = { 1931 X86::RCX, X86::RDX, X86::R8, X86::R9 1932 }; 1933 static const uint16_t GPR64ArgRegs64Bit[] = { 1934 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1935 }; 1936 static const uint16_t XMMArgRegs64Bit[] = { 1937 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1938 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1939 }; 1940 const uint16_t *GPR64ArgRegs; 1941 unsigned NumXMMRegs = 0; 1942 1943 if (IsWin64) { 1944 // The XMM registers which might contain var arg parameters are shadowed 1945 // in their paired GPR. So we only need to save the GPR to their home 1946 // slots. 1947 TotalNumIntRegs = 4; 1948 GPR64ArgRegs = GPR64ArgRegsWin64; 1949 } else { 1950 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1951 GPR64ArgRegs = GPR64ArgRegs64Bit; 1952 1953 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1954 TotalNumXMMRegs); 1955 } 1956 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1957 TotalNumIntRegs); 1958 1959 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1960 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1961 "SSE register cannot be used when SSE is disabled!"); 1962 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1963 NoImplicitFloatOps) && 1964 "SSE register cannot be used when SSE is disabled!"); 1965 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1966 !Subtarget->hasSSE1()) 1967 // Kernel mode asks for SSE to be disabled, so don't push them 1968 // on the stack. 1969 TotalNumXMMRegs = 0; 1970 1971 if (IsWin64) { 1972 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1973 // Get to the caller-allocated home save location. Add 8 to account 1974 // for the return address. 1975 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1976 FuncInfo->setRegSaveFrameIndex( 1977 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1978 // Fixup to set vararg frame on shadow area (4 x i64). 1979 if (NumIntRegs < 4) 1980 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1981 } else { 1982 // For X86-64, if there are vararg parameters that are passed via 1983 // registers, then we must store them to their spots on the stack so 1984 // they may be loaded by deferencing the result of va_next. 1985 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1986 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1987 FuncInfo->setRegSaveFrameIndex( 1988 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1989 false)); 1990 } 1991 1992 // Store the integer parameter registers. 1993 SmallVector<SDValue, 8> MemOps; 1994 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1995 getPointerTy()); 1996 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1997 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1998 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1999 DAG.getIntPtrConstant(Offset)); 2000 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2001 X86::GR64RegisterClass); 2002 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2003 SDValue Store = 2004 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2005 MachinePointerInfo::getFixedStack( 2006 FuncInfo->getRegSaveFrameIndex(), Offset), 2007 false, false, 0); 2008 MemOps.push_back(Store); 2009 Offset += 8; 2010 } 2011 2012 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2013 // Now store the XMM (fp + vector) parameter registers. 2014 SmallVector<SDValue, 11> SaveXMMOps; 2015 SaveXMMOps.push_back(Chain); 2016 2017 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2018 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2019 SaveXMMOps.push_back(ALVal); 2020 2021 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2022 FuncInfo->getRegSaveFrameIndex())); 2023 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2024 FuncInfo->getVarArgsFPOffset())); 2025 2026 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2027 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2028 X86::VR128RegisterClass); 2029 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2030 SaveXMMOps.push_back(Val); 2031 } 2032 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2033 MVT::Other, 2034 &SaveXMMOps[0], SaveXMMOps.size())); 2035 } 2036 2037 if (!MemOps.empty()) 2038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2039 &MemOps[0], MemOps.size()); 2040 } 2041 } 2042 2043 // Some CCs need callee pop. 2044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2045 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2046 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2047 } else { 2048 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2049 // If this is an sret function, the return should pop the hidden pointer. 2050 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2051 ArgsAreStructReturn(Ins)) 2052 FuncInfo->setBytesToPopOnReturn(4); 2053 } 2054 2055 if (!Is64Bit) { 2056 // RegSaveFrameIndex is X86-64 only. 2057 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2058 if (CallConv == CallingConv::X86_FastCall || 2059 CallConv == CallingConv::X86_ThisCall) 2060 // fastcc functions can't have varargs. 2061 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2062 } 2063 2064 FuncInfo->setArgumentStackSize(StackSize); 2065 2066 return Chain; 2067} 2068 2069SDValue 2070X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2071 SDValue StackPtr, SDValue Arg, 2072 DebugLoc dl, SelectionDAG &DAG, 2073 const CCValAssign &VA, 2074 ISD::ArgFlagsTy Flags) const { 2075 unsigned LocMemOffset = VA.getLocMemOffset(); 2076 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2077 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2078 if (Flags.isByVal()) 2079 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2080 2081 return DAG.getStore(Chain, dl, Arg, PtrOff, 2082 MachinePointerInfo::getStack(LocMemOffset), 2083 false, false, 0); 2084} 2085 2086/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2087/// optimization is performed and it is required. 2088SDValue 2089X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2090 SDValue &OutRetAddr, SDValue Chain, 2091 bool IsTailCall, bool Is64Bit, 2092 int FPDiff, DebugLoc dl) const { 2093 // Adjust the Return address stack slot. 2094 EVT VT = getPointerTy(); 2095 OutRetAddr = getReturnAddressFrameIndex(DAG); 2096 2097 // Load the "old" Return address. 2098 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2099 false, false, false, 0); 2100 return SDValue(OutRetAddr.getNode(), 1); 2101} 2102 2103/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2104/// optimization is performed and it is required (FPDiff!=0). 2105static SDValue 2106EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2107 SDValue Chain, SDValue RetAddrFrIdx, 2108 bool Is64Bit, int FPDiff, DebugLoc dl) { 2109 // Store the return address to the appropriate stack slot. 2110 if (!FPDiff) return Chain; 2111 // Calculate the new stack slot for the return address. 2112 int SlotSize = Is64Bit ? 8 : 4; 2113 int NewReturnAddrFI = 2114 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2115 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2116 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2117 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2118 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2119 false, false, 0); 2120 return Chain; 2121} 2122 2123SDValue 2124X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2125 CallingConv::ID CallConv, bool isVarArg, 2126 bool doesNotRet, bool &isTailCall, 2127 const SmallVectorImpl<ISD::OutputArg> &Outs, 2128 const SmallVectorImpl<SDValue> &OutVals, 2129 const SmallVectorImpl<ISD::InputArg> &Ins, 2130 DebugLoc dl, SelectionDAG &DAG, 2131 SmallVectorImpl<SDValue> &InVals) const { 2132 MachineFunction &MF = DAG.getMachineFunction(); 2133 bool Is64Bit = Subtarget->is64Bit(); 2134 bool IsWin64 = Subtarget->isTargetWin64(); 2135 bool IsWindows = Subtarget->isTargetWindows(); 2136 bool IsStructRet = CallIsStructReturn(Outs); 2137 bool IsSibcall = false; 2138 2139 if (MF.getTarget().Options.DisableTailCalls) 2140 isTailCall = false; 2141 2142 if (isTailCall) { 2143 // Check if it's really possible to do a tail call. 2144 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2145 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2146 Outs, OutVals, Ins, DAG); 2147 2148 // Sibcalls are automatically detected tailcalls which do not require 2149 // ABI changes. 2150 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2151 IsSibcall = true; 2152 2153 if (isTailCall) 2154 ++NumTailCalls; 2155 } 2156 2157 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2158 "Var args not supported with calling convention fastcc or ghc"); 2159 2160 // Analyze operands of the call, assigning locations to each operand. 2161 SmallVector<CCValAssign, 16> ArgLocs; 2162 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2163 ArgLocs, *DAG.getContext()); 2164 2165 // Allocate shadow area for Win64 2166 if (IsWin64) { 2167 CCInfo.AllocateStack(32, 8); 2168 } 2169 2170 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2171 2172 // Get a count of how many bytes are to be pushed on the stack. 2173 unsigned NumBytes = CCInfo.getNextStackOffset(); 2174 if (IsSibcall) 2175 // This is a sibcall. The memory operands are available in caller's 2176 // own caller's stack. 2177 NumBytes = 0; 2178 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2179 IsTailCallConvention(CallConv)) 2180 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2181 2182 int FPDiff = 0; 2183 if (isTailCall && !IsSibcall) { 2184 // Lower arguments at fp - stackoffset + fpdiff. 2185 unsigned NumBytesCallerPushed = 2186 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2187 FPDiff = NumBytesCallerPushed - NumBytes; 2188 2189 // Set the delta of movement of the returnaddr stackslot. 2190 // But only set if delta is greater than previous delta. 2191 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2192 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2193 } 2194 2195 if (!IsSibcall) 2196 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2197 2198 SDValue RetAddrFrIdx; 2199 // Load return address for tail calls. 2200 if (isTailCall && FPDiff) 2201 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2202 Is64Bit, FPDiff, dl); 2203 2204 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2205 SmallVector<SDValue, 8> MemOpChains; 2206 SDValue StackPtr; 2207 2208 // Walk the register/memloc assignments, inserting copies/loads. In the case 2209 // of tail call optimization arguments are handle later. 2210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2211 CCValAssign &VA = ArgLocs[i]; 2212 EVT RegVT = VA.getLocVT(); 2213 SDValue Arg = OutVals[i]; 2214 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2215 bool isByVal = Flags.isByVal(); 2216 2217 // Promote the value if needed. 2218 switch (VA.getLocInfo()) { 2219 default: llvm_unreachable("Unknown loc info!"); 2220 case CCValAssign::Full: break; 2221 case CCValAssign::SExt: 2222 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2223 break; 2224 case CCValAssign::ZExt: 2225 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2226 break; 2227 case CCValAssign::AExt: 2228 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2229 // Special case: passing MMX values in XMM registers. 2230 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2231 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2232 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2233 } else 2234 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2235 break; 2236 case CCValAssign::BCvt: 2237 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2238 break; 2239 case CCValAssign::Indirect: { 2240 // Store the argument. 2241 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2242 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2243 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2244 MachinePointerInfo::getFixedStack(FI), 2245 false, false, 0); 2246 Arg = SpillSlot; 2247 break; 2248 } 2249 } 2250 2251 if (VA.isRegLoc()) { 2252 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2253 if (isVarArg && IsWin64) { 2254 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2255 // shadow reg if callee is a varargs function. 2256 unsigned ShadowReg = 0; 2257 switch (VA.getLocReg()) { 2258 case X86::XMM0: ShadowReg = X86::RCX; break; 2259 case X86::XMM1: ShadowReg = X86::RDX; break; 2260 case X86::XMM2: ShadowReg = X86::R8; break; 2261 case X86::XMM3: ShadowReg = X86::R9; break; 2262 } 2263 if (ShadowReg) 2264 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2265 } 2266 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2267 assert(VA.isMemLoc()); 2268 if (StackPtr.getNode() == 0) 2269 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2270 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2271 dl, DAG, VA, Flags)); 2272 } 2273 } 2274 2275 if (!MemOpChains.empty()) 2276 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2277 &MemOpChains[0], MemOpChains.size()); 2278 2279 // Build a sequence of copy-to-reg nodes chained together with token chain 2280 // and flag operands which copy the outgoing args into registers. 2281 SDValue InFlag; 2282 // Tail call byval lowering might overwrite argument registers so in case of 2283 // tail call optimization the copies to registers are lowered later. 2284 if (!isTailCall) 2285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2287 RegsToPass[i].second, InFlag); 2288 InFlag = Chain.getValue(1); 2289 } 2290 2291 if (Subtarget->isPICStyleGOT()) { 2292 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2293 // GOT pointer. 2294 if (!isTailCall) { 2295 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2296 DAG.getNode(X86ISD::GlobalBaseReg, 2297 DebugLoc(), getPointerTy()), 2298 InFlag); 2299 InFlag = Chain.getValue(1); 2300 } else { 2301 // If we are tail calling and generating PIC/GOT style code load the 2302 // address of the callee into ECX. The value in ecx is used as target of 2303 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2304 // for tail calls on PIC/GOT architectures. Normally we would just put the 2305 // address of GOT into ebx and then call target@PLT. But for tail calls 2306 // ebx would be restored (since ebx is callee saved) before jumping to the 2307 // target@PLT. 2308 2309 // Note: The actual moving to ECX is done further down. 2310 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2311 if (G && !G->getGlobal()->hasHiddenVisibility() && 2312 !G->getGlobal()->hasProtectedVisibility()) 2313 Callee = LowerGlobalAddress(Callee, DAG); 2314 else if (isa<ExternalSymbolSDNode>(Callee)) 2315 Callee = LowerExternalSymbol(Callee, DAG); 2316 } 2317 } 2318 2319 if (Is64Bit && isVarArg && !IsWin64) { 2320 // From AMD64 ABI document: 2321 // For calls that may call functions that use varargs or stdargs 2322 // (prototype-less calls or calls to functions containing ellipsis (...) in 2323 // the declaration) %al is used as hidden argument to specify the number 2324 // of SSE registers used. The contents of %al do not need to match exactly 2325 // the number of registers, but must be an ubound on the number of SSE 2326 // registers used and is in the range 0 - 8 inclusive. 2327 2328 // Count the number of XMM registers allocated. 2329 static const uint16_t XMMArgRegs[] = { 2330 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2331 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2332 }; 2333 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2334 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2335 && "SSE registers cannot be used when SSE is disabled"); 2336 2337 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2338 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2339 InFlag = Chain.getValue(1); 2340 } 2341 2342 2343 // For tail calls lower the arguments to the 'real' stack slot. 2344 if (isTailCall) { 2345 // Force all the incoming stack arguments to be loaded from the stack 2346 // before any new outgoing arguments are stored to the stack, because the 2347 // outgoing stack slots may alias the incoming argument stack slots, and 2348 // the alias isn't otherwise explicit. This is slightly more conservative 2349 // than necessary, because it means that each store effectively depends 2350 // on every argument instead of just those arguments it would clobber. 2351 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2352 2353 SmallVector<SDValue, 8> MemOpChains2; 2354 SDValue FIN; 2355 int FI = 0; 2356 // Do not flag preceding copytoreg stuff together with the following stuff. 2357 InFlag = SDValue(); 2358 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2360 CCValAssign &VA = ArgLocs[i]; 2361 if (VA.isRegLoc()) 2362 continue; 2363 assert(VA.isMemLoc()); 2364 SDValue Arg = OutVals[i]; 2365 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2366 // Create frame index. 2367 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2368 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2369 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2370 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2371 2372 if (Flags.isByVal()) { 2373 // Copy relative to framepointer. 2374 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2375 if (StackPtr.getNode() == 0) 2376 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2377 getPointerTy()); 2378 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2379 2380 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2381 ArgChain, 2382 Flags, DAG, dl)); 2383 } else { 2384 // Store relative to framepointer. 2385 MemOpChains2.push_back( 2386 DAG.getStore(ArgChain, dl, Arg, FIN, 2387 MachinePointerInfo::getFixedStack(FI), 2388 false, false, 0)); 2389 } 2390 } 2391 } 2392 2393 if (!MemOpChains2.empty()) 2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2395 &MemOpChains2[0], MemOpChains2.size()); 2396 2397 // Copy arguments to their registers. 2398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2399 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2400 RegsToPass[i].second, InFlag); 2401 InFlag = Chain.getValue(1); 2402 } 2403 InFlag =SDValue(); 2404 2405 // Store the return address to the appropriate stack slot. 2406 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2407 FPDiff, dl); 2408 } 2409 2410 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2411 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2412 // In the 64-bit large code model, we have to make all calls 2413 // through a register, since the call instruction's 32-bit 2414 // pc-relative offset may not be large enough to hold the whole 2415 // address. 2416 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2417 // If the callee is a GlobalAddress node (quite common, every direct call 2418 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2419 // it. 2420 2421 // We should use extra load for direct calls to dllimported functions in 2422 // non-JIT mode. 2423 const GlobalValue *GV = G->getGlobal(); 2424 if (!GV->hasDLLImportLinkage()) { 2425 unsigned char OpFlags = 0; 2426 bool ExtraLoad = false; 2427 unsigned WrapperKind = ISD::DELETED_NODE; 2428 2429 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2430 // external symbols most go through the PLT in PIC mode. If the symbol 2431 // has hidden or protected visibility, or if it is static or local, then 2432 // we don't need to use the PLT - we can directly call it. 2433 if (Subtarget->isTargetELF() && 2434 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2435 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2436 OpFlags = X86II::MO_PLT; 2437 } else if (Subtarget->isPICStyleStubAny() && 2438 (GV->isDeclaration() || GV->isWeakForLinker()) && 2439 (!Subtarget->getTargetTriple().isMacOSX() || 2440 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2441 // PC-relative references to external symbols should go through $stub, 2442 // unless we're building with the leopard linker or later, which 2443 // automatically synthesizes these stubs. 2444 OpFlags = X86II::MO_DARWIN_STUB; 2445 } else if (Subtarget->isPICStyleRIPRel() && 2446 isa<Function>(GV) && 2447 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2448 // If the function is marked as non-lazy, generate an indirect call 2449 // which loads from the GOT directly. This avoids runtime overhead 2450 // at the cost of eager binding (and one extra byte of encoding). 2451 OpFlags = X86II::MO_GOTPCREL; 2452 WrapperKind = X86ISD::WrapperRIP; 2453 ExtraLoad = true; 2454 } 2455 2456 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2457 G->getOffset(), OpFlags); 2458 2459 // Add a wrapper if needed. 2460 if (WrapperKind != ISD::DELETED_NODE) 2461 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2462 // Add extra indirection if needed. 2463 if (ExtraLoad) 2464 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2465 MachinePointerInfo::getGOT(), 2466 false, false, false, 0); 2467 } 2468 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2469 unsigned char OpFlags = 0; 2470 2471 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2472 // external symbols should go through the PLT. 2473 if (Subtarget->isTargetELF() && 2474 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2475 OpFlags = X86II::MO_PLT; 2476 } else if (Subtarget->isPICStyleStubAny() && 2477 (!Subtarget->getTargetTriple().isMacOSX() || 2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2479 // PC-relative references to external symbols should go through $stub, 2480 // unless we're building with the leopard linker or later, which 2481 // automatically synthesizes these stubs. 2482 OpFlags = X86II::MO_DARWIN_STUB; 2483 } 2484 2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2486 OpFlags); 2487 } 2488 2489 // Returns a chain & a flag for retval copy to use. 2490 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2491 SmallVector<SDValue, 8> Ops; 2492 2493 if (!IsSibcall && isTailCall) { 2494 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2495 DAG.getIntPtrConstant(0, true), InFlag); 2496 InFlag = Chain.getValue(1); 2497 } 2498 2499 Ops.push_back(Chain); 2500 Ops.push_back(Callee); 2501 2502 if (isTailCall) 2503 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2504 2505 // Add argument registers to the end of the list so that they are known live 2506 // into the call. 2507 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2508 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2509 RegsToPass[i].second.getValueType())); 2510 2511 // Add an implicit use GOT pointer in EBX. 2512 if (!isTailCall && Subtarget->isPICStyleGOT()) 2513 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2514 2515 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2516 if (Is64Bit && isVarArg && !IsWin64) 2517 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2518 2519 // Add a register mask operand representing the call-preserved registers. 2520 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2521 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2522 assert(Mask && "Missing call preserved mask for calling convention"); 2523 Ops.push_back(DAG.getRegisterMask(Mask)); 2524 2525 if (InFlag.getNode()) 2526 Ops.push_back(InFlag); 2527 2528 if (isTailCall) { 2529 // We used to do: 2530 //// If this is the first return lowered for this function, add the regs 2531 //// to the liveout set for the function. 2532 // This isn't right, although it's probably harmless on x86; liveouts 2533 // should be computed from returns not tail calls. Consider a void 2534 // function making a tail call to a function returning int. 2535 return DAG.getNode(X86ISD::TC_RETURN, dl, 2536 NodeTys, &Ops[0], Ops.size()); 2537 } 2538 2539 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2540 InFlag = Chain.getValue(1); 2541 2542 // Create the CALLSEQ_END node. 2543 unsigned NumBytesForCalleeToPush; 2544 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2545 getTargetMachine().Options.GuaranteedTailCallOpt)) 2546 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2547 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2548 IsStructRet) 2549 // If this is a call to a struct-return function, the callee 2550 // pops the hidden struct pointer, so we have to push it back. 2551 // This is common for Darwin/X86, Linux & Mingw32 targets. 2552 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2553 NumBytesForCalleeToPush = 4; 2554 else 2555 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2556 2557 // Returns a flag for retval copy to use. 2558 if (!IsSibcall) { 2559 Chain = DAG.getCALLSEQ_END(Chain, 2560 DAG.getIntPtrConstant(NumBytes, true), 2561 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2562 true), 2563 InFlag); 2564 InFlag = Chain.getValue(1); 2565 } 2566 2567 // Handle result values, copying them out of physregs into vregs that we 2568 // return. 2569 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2570 Ins, dl, DAG, InVals); 2571} 2572 2573 2574//===----------------------------------------------------------------------===// 2575// Fast Calling Convention (tail call) implementation 2576//===----------------------------------------------------------------------===// 2577 2578// Like std call, callee cleans arguments, convention except that ECX is 2579// reserved for storing the tail called function address. Only 2 registers are 2580// free for argument passing (inreg). Tail call optimization is performed 2581// provided: 2582// * tailcallopt is enabled 2583// * caller/callee are fastcc 2584// On X86_64 architecture with GOT-style position independent code only local 2585// (within module) calls are supported at the moment. 2586// To keep the stack aligned according to platform abi the function 2587// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2588// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2589// If a tail called function callee has more arguments than the caller the 2590// caller needs to make sure that there is room to move the RETADDR to. This is 2591// achieved by reserving an area the size of the argument delta right after the 2592// original REtADDR, but before the saved framepointer or the spilled registers 2593// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2594// stack layout: 2595// arg1 2596// arg2 2597// RETADDR 2598// [ new RETADDR 2599// move area ] 2600// (possible EBP) 2601// ESI 2602// EDI 2603// local1 .. 2604 2605/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2606/// for a 16 byte align requirement. 2607unsigned 2608X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2609 SelectionDAG& DAG) const { 2610 MachineFunction &MF = DAG.getMachineFunction(); 2611 const TargetMachine &TM = MF.getTarget(); 2612 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2613 unsigned StackAlignment = TFI.getStackAlignment(); 2614 uint64_t AlignMask = StackAlignment - 1; 2615 int64_t Offset = StackSize; 2616 uint64_t SlotSize = TD->getPointerSize(); 2617 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2618 // Number smaller than 12 so just add the difference. 2619 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2620 } else { 2621 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2622 Offset = ((~AlignMask) & Offset) + StackAlignment + 2623 (StackAlignment-SlotSize); 2624 } 2625 return Offset; 2626} 2627 2628/// MatchingStackOffset - Return true if the given stack call argument is 2629/// already available in the same position (relatively) of the caller's 2630/// incoming argument stack. 2631static 2632bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2633 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2634 const X86InstrInfo *TII) { 2635 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2636 int FI = INT_MAX; 2637 if (Arg.getOpcode() == ISD::CopyFromReg) { 2638 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2639 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2640 return false; 2641 MachineInstr *Def = MRI->getVRegDef(VR); 2642 if (!Def) 2643 return false; 2644 if (!Flags.isByVal()) { 2645 if (!TII->isLoadFromStackSlot(Def, FI)) 2646 return false; 2647 } else { 2648 unsigned Opcode = Def->getOpcode(); 2649 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2650 Def->getOperand(1).isFI()) { 2651 FI = Def->getOperand(1).getIndex(); 2652 Bytes = Flags.getByValSize(); 2653 } else 2654 return false; 2655 } 2656 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2657 if (Flags.isByVal()) 2658 // ByVal argument is passed in as a pointer but it's now being 2659 // dereferenced. e.g. 2660 // define @foo(%struct.X* %A) { 2661 // tail call @bar(%struct.X* byval %A) 2662 // } 2663 return false; 2664 SDValue Ptr = Ld->getBasePtr(); 2665 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2666 if (!FINode) 2667 return false; 2668 FI = FINode->getIndex(); 2669 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2670 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2671 FI = FINode->getIndex(); 2672 Bytes = Flags.getByValSize(); 2673 } else 2674 return false; 2675 2676 assert(FI != INT_MAX); 2677 if (!MFI->isFixedObjectIndex(FI)) 2678 return false; 2679 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2680} 2681 2682/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2683/// for tail call optimization. Targets which want to do tail call 2684/// optimization should implement this function. 2685bool 2686X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2687 CallingConv::ID CalleeCC, 2688 bool isVarArg, 2689 bool isCalleeStructRet, 2690 bool isCallerStructRet, 2691 const SmallVectorImpl<ISD::OutputArg> &Outs, 2692 const SmallVectorImpl<SDValue> &OutVals, 2693 const SmallVectorImpl<ISD::InputArg> &Ins, 2694 SelectionDAG& DAG) const { 2695 if (!IsTailCallConvention(CalleeCC) && 2696 CalleeCC != CallingConv::C) 2697 return false; 2698 2699 // If -tailcallopt is specified, make fastcc functions tail-callable. 2700 const MachineFunction &MF = DAG.getMachineFunction(); 2701 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2702 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2703 bool CCMatch = CallerCC == CalleeCC; 2704 2705 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2706 if (IsTailCallConvention(CalleeCC) && CCMatch) 2707 return true; 2708 return false; 2709 } 2710 2711 // Look for obvious safe cases to perform tail call optimization that do not 2712 // require ABI changes. This is what gcc calls sibcall. 2713 2714 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2715 // emit a special epilogue. 2716 if (RegInfo->needsStackRealignment(MF)) 2717 return false; 2718 2719 // Also avoid sibcall optimization if either caller or callee uses struct 2720 // return semantics. 2721 if (isCalleeStructRet || isCallerStructRet) 2722 return false; 2723 2724 // An stdcall caller is expected to clean up its arguments; the callee 2725 // isn't going to do that. 2726 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2727 return false; 2728 2729 // Do not sibcall optimize vararg calls unless all arguments are passed via 2730 // registers. 2731 if (isVarArg && !Outs.empty()) { 2732 2733 // Optimizing for varargs on Win64 is unlikely to be safe without 2734 // additional testing. 2735 if (Subtarget->isTargetWin64()) 2736 return false; 2737 2738 SmallVector<CCValAssign, 16> ArgLocs; 2739 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2740 getTargetMachine(), ArgLocs, *DAG.getContext()); 2741 2742 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2743 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2744 if (!ArgLocs[i].isRegLoc()) 2745 return false; 2746 } 2747 2748 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2749 // stack. Therefore, if it's not used by the call it is not safe to optimize 2750 // this into a sibcall. 2751 bool Unused = false; 2752 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2753 if (!Ins[i].Used) { 2754 Unused = true; 2755 break; 2756 } 2757 } 2758 if (Unused) { 2759 SmallVector<CCValAssign, 16> RVLocs; 2760 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2761 getTargetMachine(), RVLocs, *DAG.getContext()); 2762 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2763 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2764 CCValAssign &VA = RVLocs[i]; 2765 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2766 return false; 2767 } 2768 } 2769 2770 // If the calling conventions do not match, then we'd better make sure the 2771 // results are returned in the same way as what the caller expects. 2772 if (!CCMatch) { 2773 SmallVector<CCValAssign, 16> RVLocs1; 2774 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2775 getTargetMachine(), RVLocs1, *DAG.getContext()); 2776 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2777 2778 SmallVector<CCValAssign, 16> RVLocs2; 2779 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2780 getTargetMachine(), RVLocs2, *DAG.getContext()); 2781 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2782 2783 if (RVLocs1.size() != RVLocs2.size()) 2784 return false; 2785 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2786 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2787 return false; 2788 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2789 return false; 2790 if (RVLocs1[i].isRegLoc()) { 2791 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2792 return false; 2793 } else { 2794 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2795 return false; 2796 } 2797 } 2798 } 2799 2800 // If the callee takes no arguments then go on to check the results of the 2801 // call. 2802 if (!Outs.empty()) { 2803 // Check if stack adjustment is needed. For now, do not do this if any 2804 // argument is passed on the stack. 2805 SmallVector<CCValAssign, 16> ArgLocs; 2806 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2807 getTargetMachine(), ArgLocs, *DAG.getContext()); 2808 2809 // Allocate shadow area for Win64 2810 if (Subtarget->isTargetWin64()) { 2811 CCInfo.AllocateStack(32, 8); 2812 } 2813 2814 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2815 if (CCInfo.getNextStackOffset()) { 2816 MachineFunction &MF = DAG.getMachineFunction(); 2817 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2818 return false; 2819 2820 // Check if the arguments are already laid out in the right way as 2821 // the caller's fixed stack objects. 2822 MachineFrameInfo *MFI = MF.getFrameInfo(); 2823 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2824 const X86InstrInfo *TII = 2825 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2826 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2827 CCValAssign &VA = ArgLocs[i]; 2828 SDValue Arg = OutVals[i]; 2829 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2830 if (VA.getLocInfo() == CCValAssign::Indirect) 2831 return false; 2832 if (!VA.isRegLoc()) { 2833 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2834 MFI, MRI, TII)) 2835 return false; 2836 } 2837 } 2838 } 2839 2840 // If the tailcall address may be in a register, then make sure it's 2841 // possible to register allocate for it. In 32-bit, the call address can 2842 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2843 // callee-saved registers are restored. These happen to be the same 2844 // registers used to pass 'inreg' arguments so watch out for those. 2845 if (!Subtarget->is64Bit() && 2846 !isa<GlobalAddressSDNode>(Callee) && 2847 !isa<ExternalSymbolSDNode>(Callee)) { 2848 unsigned NumInRegs = 0; 2849 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2850 CCValAssign &VA = ArgLocs[i]; 2851 if (!VA.isRegLoc()) 2852 continue; 2853 unsigned Reg = VA.getLocReg(); 2854 switch (Reg) { 2855 default: break; 2856 case X86::EAX: case X86::EDX: case X86::ECX: 2857 if (++NumInRegs == 3) 2858 return false; 2859 break; 2860 } 2861 } 2862 } 2863 } 2864 2865 return true; 2866} 2867 2868FastISel * 2869X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2870 return X86::createFastISel(funcInfo); 2871} 2872 2873 2874//===----------------------------------------------------------------------===// 2875// Other Lowering Hooks 2876//===----------------------------------------------------------------------===// 2877 2878static bool MayFoldLoad(SDValue Op) { 2879 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2880} 2881 2882static bool MayFoldIntoStore(SDValue Op) { 2883 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2884} 2885 2886static bool isTargetShuffle(unsigned Opcode) { 2887 switch(Opcode) { 2888 default: return false; 2889 case X86ISD::PSHUFD: 2890 case X86ISD::PSHUFHW: 2891 case X86ISD::PSHUFLW: 2892 case X86ISD::SHUFP: 2893 case X86ISD::PALIGN: 2894 case X86ISD::MOVLHPS: 2895 case X86ISD::MOVLHPD: 2896 case X86ISD::MOVHLPS: 2897 case X86ISD::MOVLPS: 2898 case X86ISD::MOVLPD: 2899 case X86ISD::MOVSHDUP: 2900 case X86ISD::MOVSLDUP: 2901 case X86ISD::MOVDDUP: 2902 case X86ISD::MOVSS: 2903 case X86ISD::MOVSD: 2904 case X86ISD::UNPCKL: 2905 case X86ISD::UNPCKH: 2906 case X86ISD::VPERMILP: 2907 case X86ISD::VPERM2X128: 2908 return true; 2909 } 2910} 2911 2912static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2913 SDValue V1, SelectionDAG &DAG) { 2914 switch(Opc) { 2915 default: llvm_unreachable("Unknown x86 shuffle node"); 2916 case X86ISD::MOVSHDUP: 2917 case X86ISD::MOVSLDUP: 2918 case X86ISD::MOVDDUP: 2919 return DAG.getNode(Opc, dl, VT, V1); 2920 } 2921} 2922 2923static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2924 SDValue V1, unsigned TargetMask, 2925 SelectionDAG &DAG) { 2926 switch(Opc) { 2927 default: llvm_unreachable("Unknown x86 shuffle node"); 2928 case X86ISD::PSHUFD: 2929 case X86ISD::PSHUFHW: 2930 case X86ISD::PSHUFLW: 2931 case X86ISD::VPERMILP: 2932 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2933 } 2934} 2935 2936static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2937 SDValue V1, SDValue V2, unsigned TargetMask, 2938 SelectionDAG &DAG) { 2939 switch(Opc) { 2940 default: llvm_unreachable("Unknown x86 shuffle node"); 2941 case X86ISD::PALIGN: 2942 case X86ISD::SHUFP: 2943 case X86ISD::VPERM2X128: 2944 return DAG.getNode(Opc, dl, VT, V1, V2, 2945 DAG.getConstant(TargetMask, MVT::i8)); 2946 } 2947} 2948 2949static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2950 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2951 switch(Opc) { 2952 default: llvm_unreachable("Unknown x86 shuffle node"); 2953 case X86ISD::MOVLHPS: 2954 case X86ISD::MOVLHPD: 2955 case X86ISD::MOVHLPS: 2956 case X86ISD::MOVLPS: 2957 case X86ISD::MOVLPD: 2958 case X86ISD::MOVSS: 2959 case X86ISD::MOVSD: 2960 case X86ISD::UNPCKL: 2961 case X86ISD::UNPCKH: 2962 return DAG.getNode(Opc, dl, VT, V1, V2); 2963 } 2964} 2965 2966SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2967 MachineFunction &MF = DAG.getMachineFunction(); 2968 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2969 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2970 2971 if (ReturnAddrIndex == 0) { 2972 // Set up a frame object for the return address. 2973 uint64_t SlotSize = TD->getPointerSize(); 2974 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2975 false); 2976 FuncInfo->setRAIndex(ReturnAddrIndex); 2977 } 2978 2979 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2980} 2981 2982 2983bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2984 bool hasSymbolicDisplacement) { 2985 // Offset should fit into 32 bit immediate field. 2986 if (!isInt<32>(Offset)) 2987 return false; 2988 2989 // If we don't have a symbolic displacement - we don't have any extra 2990 // restrictions. 2991 if (!hasSymbolicDisplacement) 2992 return true; 2993 2994 // FIXME: Some tweaks might be needed for medium code model. 2995 if (M != CodeModel::Small && M != CodeModel::Kernel) 2996 return false; 2997 2998 // For small code model we assume that latest object is 16MB before end of 31 2999 // bits boundary. We may also accept pretty large negative constants knowing 3000 // that all objects are in the positive half of address space. 3001 if (M == CodeModel::Small && Offset < 16*1024*1024) 3002 return true; 3003 3004 // For kernel code model we know that all object resist in the negative half 3005 // of 32bits address space. We may not accept negative offsets, since they may 3006 // be just off and we may accept pretty large positive ones. 3007 if (M == CodeModel::Kernel && Offset > 0) 3008 return true; 3009 3010 return false; 3011} 3012 3013/// isCalleePop - Determines whether the callee is required to pop its 3014/// own arguments. Callee pop is necessary to support tail calls. 3015bool X86::isCalleePop(CallingConv::ID CallingConv, 3016 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3017 if (IsVarArg) 3018 return false; 3019 3020 switch (CallingConv) { 3021 default: 3022 return false; 3023 case CallingConv::X86_StdCall: 3024 return !is64Bit; 3025 case CallingConv::X86_FastCall: 3026 return !is64Bit; 3027 case CallingConv::X86_ThisCall: 3028 return !is64Bit; 3029 case CallingConv::Fast: 3030 return TailCallOpt; 3031 case CallingConv::GHC: 3032 return TailCallOpt; 3033 } 3034} 3035 3036/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3037/// specific condition code, returning the condition code and the LHS/RHS of the 3038/// comparison to make. 3039static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3040 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3041 if (!isFP) { 3042 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3043 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3044 // X > -1 -> X == 0, jump !sign. 3045 RHS = DAG.getConstant(0, RHS.getValueType()); 3046 return X86::COND_NS; 3047 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3048 // X < 0 -> X == 0, jump on sign. 3049 return X86::COND_S; 3050 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3051 // X < 1 -> X <= 0 3052 RHS = DAG.getConstant(0, RHS.getValueType()); 3053 return X86::COND_LE; 3054 } 3055 } 3056 3057 switch (SetCCOpcode) { 3058 default: llvm_unreachable("Invalid integer condition!"); 3059 case ISD::SETEQ: return X86::COND_E; 3060 case ISD::SETGT: return X86::COND_G; 3061 case ISD::SETGE: return X86::COND_GE; 3062 case ISD::SETLT: return X86::COND_L; 3063 case ISD::SETLE: return X86::COND_LE; 3064 case ISD::SETNE: return X86::COND_NE; 3065 case ISD::SETULT: return X86::COND_B; 3066 case ISD::SETUGT: return X86::COND_A; 3067 case ISD::SETULE: return X86::COND_BE; 3068 case ISD::SETUGE: return X86::COND_AE; 3069 } 3070 } 3071 3072 // First determine if it is required or is profitable to flip the operands. 3073 3074 // If LHS is a foldable load, but RHS is not, flip the condition. 3075 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3076 !ISD::isNON_EXTLoad(RHS.getNode())) { 3077 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3078 std::swap(LHS, RHS); 3079 } 3080 3081 switch (SetCCOpcode) { 3082 default: break; 3083 case ISD::SETOLT: 3084 case ISD::SETOLE: 3085 case ISD::SETUGT: 3086 case ISD::SETUGE: 3087 std::swap(LHS, RHS); 3088 break; 3089 } 3090 3091 // On a floating point condition, the flags are set as follows: 3092 // ZF PF CF op 3093 // 0 | 0 | 0 | X > Y 3094 // 0 | 0 | 1 | X < Y 3095 // 1 | 0 | 0 | X == Y 3096 // 1 | 1 | 1 | unordered 3097 switch (SetCCOpcode) { 3098 default: llvm_unreachable("Condcode should be pre-legalized away"); 3099 case ISD::SETUEQ: 3100 case ISD::SETEQ: return X86::COND_E; 3101 case ISD::SETOLT: // flipped 3102 case ISD::SETOGT: 3103 case ISD::SETGT: return X86::COND_A; 3104 case ISD::SETOLE: // flipped 3105 case ISD::SETOGE: 3106 case ISD::SETGE: return X86::COND_AE; 3107 case ISD::SETUGT: // flipped 3108 case ISD::SETULT: 3109 case ISD::SETLT: return X86::COND_B; 3110 case ISD::SETUGE: // flipped 3111 case ISD::SETULE: 3112 case ISD::SETLE: return X86::COND_BE; 3113 case ISD::SETONE: 3114 case ISD::SETNE: return X86::COND_NE; 3115 case ISD::SETUO: return X86::COND_P; 3116 case ISD::SETO: return X86::COND_NP; 3117 case ISD::SETOEQ: 3118 case ISD::SETUNE: return X86::COND_INVALID; 3119 } 3120} 3121 3122/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3123/// code. Current x86 isa includes the following FP cmov instructions: 3124/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3125static bool hasFPCMov(unsigned X86CC) { 3126 switch (X86CC) { 3127 default: 3128 return false; 3129 case X86::COND_B: 3130 case X86::COND_BE: 3131 case X86::COND_E: 3132 case X86::COND_P: 3133 case X86::COND_A: 3134 case X86::COND_AE: 3135 case X86::COND_NE: 3136 case X86::COND_NP: 3137 return true; 3138 } 3139} 3140 3141/// isFPImmLegal - Returns true if the target can instruction select the 3142/// specified FP immediate natively. If false, the legalizer will 3143/// materialize the FP immediate as a load from a constant pool. 3144bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3145 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3146 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3147 return true; 3148 } 3149 return false; 3150} 3151 3152/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3153/// the specified range (L, H]. 3154static bool isUndefOrInRange(int Val, int Low, int Hi) { 3155 return (Val < 0) || (Val >= Low && Val < Hi); 3156} 3157 3158/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3159/// specified value. 3160static bool isUndefOrEqual(int Val, int CmpVal) { 3161 if (Val < 0 || Val == CmpVal) 3162 return true; 3163 return false; 3164} 3165 3166/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3167/// from position Pos and ending in Pos+Size, falls within the specified 3168/// sequential range (L, L+Pos]. or is undef. 3169static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3170 int Pos, int Size, int Low) { 3171 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3172 if (!isUndefOrEqual(Mask[i], Low)) 3173 return false; 3174 return true; 3175} 3176 3177/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3178/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3179/// the second operand. 3180static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3181 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3182 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3183 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3184 return (Mask[0] < 2 && Mask[1] < 2); 3185 return false; 3186} 3187 3188/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3189/// is suitable for input to PSHUFHW. 3190static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3191 if (VT != MVT::v8i16) 3192 return false; 3193 3194 // Lower quadword copied in order or undef. 3195 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3196 return false; 3197 3198 // Upper quadword shuffled. 3199 for (unsigned i = 4; i != 8; ++i) 3200 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3201 return false; 3202 3203 return true; 3204} 3205 3206/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3207/// is suitable for input to PSHUFLW. 3208static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3209 if (VT != MVT::v8i16) 3210 return false; 3211 3212 // Upper quadword copied in order. 3213 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3214 return false; 3215 3216 // Lower quadword shuffled. 3217 for (unsigned i = 0; i != 4; ++i) 3218 if (Mask[i] >= 4) 3219 return false; 3220 3221 return true; 3222} 3223 3224/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3225/// is suitable for input to PALIGNR. 3226static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3227 const X86Subtarget *Subtarget) { 3228 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3229 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3230 return false; 3231 3232 unsigned NumElts = VT.getVectorNumElements(); 3233 unsigned NumLanes = VT.getSizeInBits()/128; 3234 unsigned NumLaneElts = NumElts/NumLanes; 3235 3236 // Do not handle 64-bit element shuffles with palignr. 3237 if (NumLaneElts == 2) 3238 return false; 3239 3240 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3241 unsigned i; 3242 for (i = 0; i != NumLaneElts; ++i) { 3243 if (Mask[i+l] >= 0) 3244 break; 3245 } 3246 3247 // Lane is all undef, go to next lane 3248 if (i == NumLaneElts) 3249 continue; 3250 3251 int Start = Mask[i+l]; 3252 3253 // Make sure its in this lane in one of the sources 3254 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3255 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3256 return false; 3257 3258 // If not lane 0, then we must match lane 0 3259 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3260 return false; 3261 3262 // Correct second source to be contiguous with first source 3263 if (Start >= (int)NumElts) 3264 Start -= NumElts - NumLaneElts; 3265 3266 // Make sure we're shifting in the right direction. 3267 if (Start <= (int)(i+l)) 3268 return false; 3269 3270 Start -= i; 3271 3272 // Check the rest of the elements to see if they are consecutive. 3273 for (++i; i != NumLaneElts; ++i) { 3274 int Idx = Mask[i+l]; 3275 3276 // Make sure its in this lane 3277 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3278 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3279 return false; 3280 3281 // If not lane 0, then we must match lane 0 3282 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3283 return false; 3284 3285 if (Idx >= (int)NumElts) 3286 Idx -= NumElts - NumLaneElts; 3287 3288 if (!isUndefOrEqual(Idx, Start+i)) 3289 return false; 3290 3291 } 3292 } 3293 3294 return true; 3295} 3296 3297/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3298/// the two vector operands have swapped position. 3299static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3300 unsigned NumElems) { 3301 for (unsigned i = 0; i != NumElems; ++i) { 3302 int idx = Mask[i]; 3303 if (idx < 0) 3304 continue; 3305 else if (idx < (int)NumElems) 3306 Mask[i] = idx + NumElems; 3307 else 3308 Mask[i] = idx - NumElems; 3309 } 3310} 3311 3312/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3313/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3314/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3315/// reverse of what x86 shuffles want. 3316static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3317 bool Commuted = false) { 3318 if (!HasAVX && VT.getSizeInBits() == 256) 3319 return false; 3320 3321 unsigned NumElems = VT.getVectorNumElements(); 3322 unsigned NumLanes = VT.getSizeInBits()/128; 3323 unsigned NumLaneElems = NumElems/NumLanes; 3324 3325 if (NumLaneElems != 2 && NumLaneElems != 4) 3326 return false; 3327 3328 // VSHUFPSY divides the resulting vector into 4 chunks. 3329 // The sources are also splitted into 4 chunks, and each destination 3330 // chunk must come from a different source chunk. 3331 // 3332 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3333 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3334 // 3335 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3336 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3337 // 3338 // VSHUFPDY divides the resulting vector into 4 chunks. 3339 // The sources are also splitted into 4 chunks, and each destination 3340 // chunk must come from a different source chunk. 3341 // 3342 // SRC1 => X3 X2 X1 X0 3343 // SRC2 => Y3 Y2 Y1 Y0 3344 // 3345 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3346 // 3347 unsigned HalfLaneElems = NumLaneElems/2; 3348 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3349 for (unsigned i = 0; i != NumLaneElems; ++i) { 3350 int Idx = Mask[i+l]; 3351 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3352 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3353 return false; 3354 // For VSHUFPSY, the mask of the second half must be the same as the 3355 // first but with the appropriate offsets. This works in the same way as 3356 // VPERMILPS works with masks. 3357 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3358 continue; 3359 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3360 return false; 3361 } 3362 } 3363 3364 return true; 3365} 3366 3367/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3368/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3369static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3370 unsigned NumElems = VT.getVectorNumElements(); 3371 3372 if (VT.getSizeInBits() != 128) 3373 return false; 3374 3375 if (NumElems != 4) 3376 return false; 3377 3378 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3379 return isUndefOrEqual(Mask[0], 6) && 3380 isUndefOrEqual(Mask[1], 7) && 3381 isUndefOrEqual(Mask[2], 2) && 3382 isUndefOrEqual(Mask[3], 3); 3383} 3384 3385/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3386/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3387/// <2, 3, 2, 3> 3388static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3389 unsigned NumElems = VT.getVectorNumElements(); 3390 3391 if (VT.getSizeInBits() != 128) 3392 return false; 3393 3394 if (NumElems != 4) 3395 return false; 3396 3397 return isUndefOrEqual(Mask[0], 2) && 3398 isUndefOrEqual(Mask[1], 3) && 3399 isUndefOrEqual(Mask[2], 2) && 3400 isUndefOrEqual(Mask[3], 3); 3401} 3402 3403/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3404/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3405static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3406 if (VT.getSizeInBits() != 128) 3407 return false; 3408 3409 unsigned NumElems = VT.getVectorNumElements(); 3410 3411 if (NumElems != 2 && NumElems != 4) 3412 return false; 3413 3414 for (unsigned i = 0; i != NumElems/2; ++i) 3415 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3416 return false; 3417 3418 for (unsigned i = NumElems/2; i != NumElems; ++i) 3419 if (!isUndefOrEqual(Mask[i], i)) 3420 return false; 3421 3422 return true; 3423} 3424 3425/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3426/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3427static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3428 unsigned NumElems = VT.getVectorNumElements(); 3429 3430 if ((NumElems != 2 && NumElems != 4) 3431 || VT.getSizeInBits() > 128) 3432 return false; 3433 3434 for (unsigned i = 0; i != NumElems/2; ++i) 3435 if (!isUndefOrEqual(Mask[i], i)) 3436 return false; 3437 3438 for (unsigned i = 0; i != NumElems/2; ++i) 3439 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems)) 3440 return false; 3441 3442 return true; 3443} 3444 3445/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3446/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3447static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3448 bool HasAVX2, bool V2IsSplat = false) { 3449 unsigned NumElts = VT.getVectorNumElements(); 3450 3451 assert((VT.is128BitVector() || VT.is256BitVector()) && 3452 "Unsupported vector type for unpckh"); 3453 3454 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3455 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3456 return false; 3457 3458 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3459 // independently on 128-bit lanes. 3460 unsigned NumLanes = VT.getSizeInBits()/128; 3461 unsigned NumLaneElts = NumElts/NumLanes; 3462 3463 for (unsigned l = 0; l != NumLanes; ++l) { 3464 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3465 i != (l+1)*NumLaneElts; 3466 i += 2, ++j) { 3467 int BitI = Mask[i]; 3468 int BitI1 = Mask[i+1]; 3469 if (!isUndefOrEqual(BitI, j)) 3470 return false; 3471 if (V2IsSplat) { 3472 if (!isUndefOrEqual(BitI1, NumElts)) 3473 return false; 3474 } else { 3475 if (!isUndefOrEqual(BitI1, j + NumElts)) 3476 return false; 3477 } 3478 } 3479 } 3480 3481 return true; 3482} 3483 3484/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3485/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3486static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3487 bool HasAVX2, bool V2IsSplat = false) { 3488 unsigned NumElts = VT.getVectorNumElements(); 3489 3490 assert((VT.is128BitVector() || VT.is256BitVector()) && 3491 "Unsupported vector type for unpckh"); 3492 3493 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3494 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3495 return false; 3496 3497 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3498 // independently on 128-bit lanes. 3499 unsigned NumLanes = VT.getSizeInBits()/128; 3500 unsigned NumLaneElts = NumElts/NumLanes; 3501 3502 for (unsigned l = 0; l != NumLanes; ++l) { 3503 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3504 i != (l+1)*NumLaneElts; i += 2, ++j) { 3505 int BitI = Mask[i]; 3506 int BitI1 = Mask[i+1]; 3507 if (!isUndefOrEqual(BitI, j)) 3508 return false; 3509 if (V2IsSplat) { 3510 if (isUndefOrEqual(BitI1, NumElts)) 3511 return false; 3512 } else { 3513 if (!isUndefOrEqual(BitI1, j+NumElts)) 3514 return false; 3515 } 3516 } 3517 } 3518 return true; 3519} 3520 3521/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3522/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3523/// <0, 0, 1, 1> 3524static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3525 bool HasAVX2) { 3526 unsigned NumElts = VT.getVectorNumElements(); 3527 3528 assert((VT.is128BitVector() || VT.is256BitVector()) && 3529 "Unsupported vector type for unpckh"); 3530 3531 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3532 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3533 return false; 3534 3535 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3536 // FIXME: Need a better way to get rid of this, there's no latency difference 3537 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3538 // the former later. We should also remove the "_undef" special mask. 3539 if (NumElts == 4 && VT.getSizeInBits() == 256) 3540 return false; 3541 3542 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3543 // independently on 128-bit lanes. 3544 unsigned NumLanes = VT.getSizeInBits()/128; 3545 unsigned NumLaneElts = NumElts/NumLanes; 3546 3547 for (unsigned l = 0; l != NumLanes; ++l) { 3548 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3549 i != (l+1)*NumLaneElts; 3550 i += 2, ++j) { 3551 int BitI = Mask[i]; 3552 int BitI1 = Mask[i+1]; 3553 3554 if (!isUndefOrEqual(BitI, j)) 3555 return false; 3556 if (!isUndefOrEqual(BitI1, j)) 3557 return false; 3558 } 3559 } 3560 3561 return true; 3562} 3563 3564/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3565/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3566/// <2, 2, 3, 3> 3567static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3568 unsigned NumElts = VT.getVectorNumElements(); 3569 3570 assert((VT.is128BitVector() || VT.is256BitVector()) && 3571 "Unsupported vector type for unpckh"); 3572 3573 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3574 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3575 return false; 3576 3577 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3578 // independently on 128-bit lanes. 3579 unsigned NumLanes = VT.getSizeInBits()/128; 3580 unsigned NumLaneElts = NumElts/NumLanes; 3581 3582 for (unsigned l = 0; l != NumLanes; ++l) { 3583 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3584 i != (l+1)*NumLaneElts; i += 2, ++j) { 3585 int BitI = Mask[i]; 3586 int BitI1 = Mask[i+1]; 3587 if (!isUndefOrEqual(BitI, j)) 3588 return false; 3589 if (!isUndefOrEqual(BitI1, j)) 3590 return false; 3591 } 3592 } 3593 return true; 3594} 3595 3596/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3597/// specifies a shuffle of elements that is suitable for input to MOVSS, 3598/// MOVSD, and MOVD, i.e. setting the lowest element. 3599static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3600 if (VT.getVectorElementType().getSizeInBits() < 32) 3601 return false; 3602 if (VT.getSizeInBits() == 256) 3603 return false; 3604 3605 unsigned NumElts = VT.getVectorNumElements(); 3606 3607 if (!isUndefOrEqual(Mask[0], NumElts)) 3608 return false; 3609 3610 for (unsigned i = 1; i != NumElts; ++i) 3611 if (!isUndefOrEqual(Mask[i], i)) 3612 return false; 3613 3614 return true; 3615} 3616 3617/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3618/// as permutations between 128-bit chunks or halves. As an example: this 3619/// shuffle bellow: 3620/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3621/// The first half comes from the second half of V1 and the second half from the 3622/// the second half of V2. 3623static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3624 if (!HasAVX || VT.getSizeInBits() != 256) 3625 return false; 3626 3627 // The shuffle result is divided into half A and half B. In total the two 3628 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3629 // B must come from C, D, E or F. 3630 unsigned HalfSize = VT.getVectorNumElements()/2; 3631 bool MatchA = false, MatchB = false; 3632 3633 // Check if A comes from one of C, D, E, F. 3634 for (unsigned Half = 0; Half != 4; ++Half) { 3635 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3636 MatchA = true; 3637 break; 3638 } 3639 } 3640 3641 // Check if B comes from one of C, D, E, F. 3642 for (unsigned Half = 0; Half != 4; ++Half) { 3643 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3644 MatchB = true; 3645 break; 3646 } 3647 } 3648 3649 return MatchA && MatchB; 3650} 3651 3652/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3653/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3654static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3655 EVT VT = SVOp->getValueType(0); 3656 3657 unsigned HalfSize = VT.getVectorNumElements()/2; 3658 3659 unsigned FstHalf = 0, SndHalf = 0; 3660 for (unsigned i = 0; i < HalfSize; ++i) { 3661 if (SVOp->getMaskElt(i) > 0) { 3662 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3663 break; 3664 } 3665 } 3666 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3667 if (SVOp->getMaskElt(i) > 0) { 3668 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3669 break; 3670 } 3671 } 3672 3673 return (FstHalf | (SndHalf << 4)); 3674} 3675 3676/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3677/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3678/// Note that VPERMIL mask matching is different depending whether theunderlying 3679/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3680/// to the same elements of the low, but to the higher half of the source. 3681/// In VPERMILPD the two lanes could be shuffled independently of each other 3682/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3683static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3684 if (!HasAVX) 3685 return false; 3686 3687 unsigned NumElts = VT.getVectorNumElements(); 3688 // Only match 256-bit with 32/64-bit types 3689 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3690 return false; 3691 3692 unsigned NumLanes = VT.getSizeInBits()/128; 3693 unsigned LaneSize = NumElts/NumLanes; 3694 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3695 for (unsigned i = 0; i != LaneSize; ++i) { 3696 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3697 return false; 3698 if (NumElts != 8 || l == 0) 3699 continue; 3700 // VPERMILPS handling 3701 if (Mask[i] < 0) 3702 continue; 3703 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3704 return false; 3705 } 3706 } 3707 3708 return true; 3709} 3710 3711/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3712/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3713/// element of vector 2 and the other elements to come from vector 1 in order. 3714static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3715 bool V2IsSplat = false, bool V2IsUndef = false) { 3716 unsigned NumOps = VT.getVectorNumElements(); 3717 if (VT.getSizeInBits() == 256) 3718 return false; 3719 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3720 return false; 3721 3722 if (!isUndefOrEqual(Mask[0], 0)) 3723 return false; 3724 3725 for (unsigned i = 1; i != NumOps; ++i) 3726 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3727 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3728 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3729 return false; 3730 3731 return true; 3732} 3733 3734/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3735/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3736/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3737static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3738 const X86Subtarget *Subtarget) { 3739 if (!Subtarget->hasSSE3()) 3740 return false; 3741 3742 unsigned NumElems = VT.getVectorNumElements(); 3743 3744 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3745 (VT.getSizeInBits() == 256 && NumElems != 8)) 3746 return false; 3747 3748 // "i+1" is the value the indexed mask element must have 3749 for (unsigned i = 0; i != NumElems; i += 2) 3750 if (!isUndefOrEqual(Mask[i], i+1) || 3751 !isUndefOrEqual(Mask[i+1], i+1)) 3752 return false; 3753 3754 return true; 3755} 3756 3757/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3758/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3759/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3760static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3761 const X86Subtarget *Subtarget) { 3762 if (!Subtarget->hasSSE3()) 3763 return false; 3764 3765 unsigned NumElems = VT.getVectorNumElements(); 3766 3767 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3768 (VT.getSizeInBits() == 256 && NumElems != 8)) 3769 return false; 3770 3771 // "i" is the value the indexed mask element must have 3772 for (unsigned i = 0; i != NumElems; i += 2) 3773 if (!isUndefOrEqual(Mask[i], i) || 3774 !isUndefOrEqual(Mask[i+1], i)) 3775 return false; 3776 3777 return true; 3778} 3779 3780/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3781/// specifies a shuffle of elements that is suitable for input to 256-bit 3782/// version of MOVDDUP. 3783static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3784 unsigned NumElts = VT.getVectorNumElements(); 3785 3786 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3787 return false; 3788 3789 for (unsigned i = 0; i != NumElts/2; ++i) 3790 if (!isUndefOrEqual(Mask[i], 0)) 3791 return false; 3792 for (unsigned i = NumElts/2; i != NumElts; ++i) 3793 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3794 return false; 3795 return true; 3796} 3797 3798/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3799/// specifies a shuffle of elements that is suitable for input to 128-bit 3800/// version of MOVDDUP. 3801static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3802 if (VT.getSizeInBits() != 128) 3803 return false; 3804 3805 unsigned e = VT.getVectorNumElements() / 2; 3806 for (unsigned i = 0; i != e; ++i) 3807 if (!isUndefOrEqual(Mask[i], i)) 3808 return false; 3809 for (unsigned i = 0; i != e; ++i) 3810 if (!isUndefOrEqual(Mask[e+i], i)) 3811 return false; 3812 return true; 3813} 3814 3815/// isVEXTRACTF128Index - Return true if the specified 3816/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3817/// suitable for input to VEXTRACTF128. 3818bool X86::isVEXTRACTF128Index(SDNode *N) { 3819 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3820 return false; 3821 3822 // The index should be aligned on a 128-bit boundary. 3823 uint64_t Index = 3824 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3825 3826 unsigned VL = N->getValueType(0).getVectorNumElements(); 3827 unsigned VBits = N->getValueType(0).getSizeInBits(); 3828 unsigned ElSize = VBits / VL; 3829 bool Result = (Index * ElSize) % 128 == 0; 3830 3831 return Result; 3832} 3833 3834/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3835/// operand specifies a subvector insert that is suitable for input to 3836/// VINSERTF128. 3837bool X86::isVINSERTF128Index(SDNode *N) { 3838 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3839 return false; 3840 3841 // The index should be aligned on a 128-bit boundary. 3842 uint64_t Index = 3843 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3844 3845 unsigned VL = N->getValueType(0).getVectorNumElements(); 3846 unsigned VBits = N->getValueType(0).getSizeInBits(); 3847 unsigned ElSize = VBits / VL; 3848 bool Result = (Index * ElSize) % 128 == 0; 3849 3850 return Result; 3851} 3852 3853/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3854/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3855/// Handles 128-bit and 256-bit. 3856static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3857 EVT VT = N->getValueType(0); 3858 3859 assert((VT.is128BitVector() || VT.is256BitVector()) && 3860 "Unsupported vector type for PSHUF/SHUFP"); 3861 3862 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3863 // independently on 128-bit lanes. 3864 unsigned NumElts = VT.getVectorNumElements(); 3865 unsigned NumLanes = VT.getSizeInBits()/128; 3866 unsigned NumLaneElts = NumElts/NumLanes; 3867 3868 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3869 "Only supports 2 or 4 elements per lane"); 3870 3871 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3872 unsigned Mask = 0; 3873 for (unsigned i = 0; i != NumElts; ++i) { 3874 int Elt = N->getMaskElt(i); 3875 if (Elt < 0) continue; 3876 Elt %= NumLaneElts; 3877 unsigned ShAmt = i << Shift; 3878 if (ShAmt >= 8) ShAmt -= 8; 3879 Mask |= Elt << ShAmt; 3880 } 3881 3882 return Mask; 3883} 3884 3885/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3886/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3887static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 3888 unsigned Mask = 0; 3889 // 8 nodes, but we only care about the last 4. 3890 for (unsigned i = 7; i >= 4; --i) { 3891 int Val = N->getMaskElt(i); 3892 if (Val >= 0) 3893 Mask |= (Val - 4); 3894 if (i != 4) 3895 Mask <<= 2; 3896 } 3897 return Mask; 3898} 3899 3900/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3901/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3902static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 3903 unsigned Mask = 0; 3904 // 8 nodes, but we only care about the first 4. 3905 for (int i = 3; i >= 0; --i) { 3906 int Val = N->getMaskElt(i); 3907 if (Val >= 0) 3908 Mask |= Val; 3909 if (i != 0) 3910 Mask <<= 2; 3911 } 3912 return Mask; 3913} 3914 3915/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3916/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3917static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3918 EVT VT = SVOp->getValueType(0); 3919 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3920 3921 unsigned NumElts = VT.getVectorNumElements(); 3922 unsigned NumLanes = VT.getSizeInBits()/128; 3923 unsigned NumLaneElts = NumElts/NumLanes; 3924 3925 int Val = 0; 3926 unsigned i; 3927 for (i = 0; i != NumElts; ++i) { 3928 Val = SVOp->getMaskElt(i); 3929 if (Val >= 0) 3930 break; 3931 } 3932 if (Val >= (int)NumElts) 3933 Val -= NumElts - NumLaneElts; 3934 3935 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3936 return (Val - i) * EltSize; 3937} 3938 3939/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3940/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3941/// instructions. 3942unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3943 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3944 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3945 3946 uint64_t Index = 3947 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3948 3949 EVT VecVT = N->getOperand(0).getValueType(); 3950 EVT ElVT = VecVT.getVectorElementType(); 3951 3952 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3953 return Index / NumElemsPerChunk; 3954} 3955 3956/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3957/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3958/// instructions. 3959unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3960 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3961 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3962 3963 uint64_t Index = 3964 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3965 3966 EVT VecVT = N->getValueType(0); 3967 EVT ElVT = VecVT.getVectorElementType(); 3968 3969 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3970 return Index / NumElemsPerChunk; 3971} 3972 3973/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3974/// constant +0.0. 3975bool X86::isZeroNode(SDValue Elt) { 3976 return ((isa<ConstantSDNode>(Elt) && 3977 cast<ConstantSDNode>(Elt)->isNullValue()) || 3978 (isa<ConstantFPSDNode>(Elt) && 3979 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3980} 3981 3982/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3983/// their permute mask. 3984static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3985 SelectionDAG &DAG) { 3986 EVT VT = SVOp->getValueType(0); 3987 unsigned NumElems = VT.getVectorNumElements(); 3988 SmallVector<int, 8> MaskVec; 3989 3990 for (unsigned i = 0; i != NumElems; ++i) { 3991 int idx = SVOp->getMaskElt(i); 3992 if (idx < 0) 3993 MaskVec.push_back(idx); 3994 else if (idx < (int)NumElems) 3995 MaskVec.push_back(idx + NumElems); 3996 else 3997 MaskVec.push_back(idx - NumElems); 3998 } 3999 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4000 SVOp->getOperand(0), &MaskVec[0]); 4001} 4002 4003/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4004/// match movhlps. The lower half elements should come from upper half of 4005/// V1 (and in order), and the upper half elements should come from the upper 4006/// half of V2 (and in order). 4007static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4008 if (VT.getSizeInBits() != 128) 4009 return false; 4010 if (VT.getVectorNumElements() != 4) 4011 return false; 4012 for (unsigned i = 0, e = 2; i != e; ++i) 4013 if (!isUndefOrEqual(Mask[i], i+2)) 4014 return false; 4015 for (unsigned i = 2; i != 4; ++i) 4016 if (!isUndefOrEqual(Mask[i], i+4)) 4017 return false; 4018 return true; 4019} 4020 4021/// isScalarLoadToVector - Returns true if the node is a scalar load that 4022/// is promoted to a vector. It also returns the LoadSDNode by reference if 4023/// required. 4024static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4025 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4026 return false; 4027 N = N->getOperand(0).getNode(); 4028 if (!ISD::isNON_EXTLoad(N)) 4029 return false; 4030 if (LD) 4031 *LD = cast<LoadSDNode>(N); 4032 return true; 4033} 4034 4035// Test whether the given value is a vector value which will be legalized 4036// into a load. 4037static bool WillBeConstantPoolLoad(SDNode *N) { 4038 if (N->getOpcode() != ISD::BUILD_VECTOR) 4039 return false; 4040 4041 // Check for any non-constant elements. 4042 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4043 switch (N->getOperand(i).getNode()->getOpcode()) { 4044 case ISD::UNDEF: 4045 case ISD::ConstantFP: 4046 case ISD::Constant: 4047 break; 4048 default: 4049 return false; 4050 } 4051 4052 // Vectors of all-zeros and all-ones are materialized with special 4053 // instructions rather than being loaded. 4054 return !ISD::isBuildVectorAllZeros(N) && 4055 !ISD::isBuildVectorAllOnes(N); 4056} 4057 4058/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4059/// match movlp{s|d}. The lower half elements should come from lower half of 4060/// V1 (and in order), and the upper half elements should come from the upper 4061/// half of V2 (and in order). And since V1 will become the source of the 4062/// MOVLP, it must be either a vector load or a scalar load to vector. 4063static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4064 ArrayRef<int> Mask, EVT VT) { 4065 if (VT.getSizeInBits() != 128) 4066 return false; 4067 4068 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4069 return false; 4070 // Is V2 is a vector load, don't do this transformation. We will try to use 4071 // load folding shufps op. 4072 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4073 return false; 4074 4075 unsigned NumElems = VT.getVectorNumElements(); 4076 4077 if (NumElems != 2 && NumElems != 4) 4078 return false; 4079 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4080 if (!isUndefOrEqual(Mask[i], i)) 4081 return false; 4082 for (unsigned i = NumElems/2; i != NumElems; ++i) 4083 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4084 return false; 4085 return true; 4086} 4087 4088/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4089/// all the same. 4090static bool isSplatVector(SDNode *N) { 4091 if (N->getOpcode() != ISD::BUILD_VECTOR) 4092 return false; 4093 4094 SDValue SplatValue = N->getOperand(0); 4095 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4096 if (N->getOperand(i) != SplatValue) 4097 return false; 4098 return true; 4099} 4100 4101/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4102/// to an zero vector. 4103/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4104static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4105 SDValue V1 = N->getOperand(0); 4106 SDValue V2 = N->getOperand(1); 4107 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4108 for (unsigned i = 0; i != NumElems; ++i) { 4109 int Idx = N->getMaskElt(i); 4110 if (Idx >= (int)NumElems) { 4111 unsigned Opc = V2.getOpcode(); 4112 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4113 continue; 4114 if (Opc != ISD::BUILD_VECTOR || 4115 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4116 return false; 4117 } else if (Idx >= 0) { 4118 unsigned Opc = V1.getOpcode(); 4119 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4120 continue; 4121 if (Opc != ISD::BUILD_VECTOR || 4122 !X86::isZeroNode(V1.getOperand(Idx))) 4123 return false; 4124 } 4125 } 4126 return true; 4127} 4128 4129/// getZeroVector - Returns a vector of specified type with all zero elements. 4130/// 4131static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4132 SelectionDAG &DAG, DebugLoc dl) { 4133 assert(VT.isVector() && "Expected a vector type"); 4134 4135 // Always build SSE zero vectors as <4 x i32> bitcasted 4136 // to their dest type. This ensures they get CSE'd. 4137 SDValue Vec; 4138 if (VT.getSizeInBits() == 128) { // SSE 4139 if (Subtarget->hasSSE2()) { // SSE2 4140 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4141 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4142 } else { // SSE1 4143 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4144 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4145 } 4146 } else if (VT.getSizeInBits() == 256) { // AVX 4147 if (Subtarget->hasAVX2()) { // AVX2 4148 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4149 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4150 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4151 } else { 4152 // 256-bit logic and arithmetic instructions in AVX are all 4153 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4154 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4155 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4157 } 4158 } 4159 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4160} 4161 4162/// getOnesVector - Returns a vector of specified type with all bits set. 4163/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4164/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4165/// Then bitcast to their original type, ensuring they get CSE'd. 4166static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4167 DebugLoc dl) { 4168 assert(VT.isVector() && "Expected a vector type"); 4169 assert((VT.is128BitVector() || VT.is256BitVector()) 4170 && "Expected a 128-bit or 256-bit vector type"); 4171 4172 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4173 SDValue Vec; 4174 if (VT.getSizeInBits() == 256) { 4175 if (HasAVX2) { // AVX2 4176 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4177 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4178 } else { // AVX 4179 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4180 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4181 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4182 Vec = Insert128BitVector(InsV, Vec, 4183 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4184 } 4185 } else { 4186 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4187 } 4188 4189 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4190} 4191 4192/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4193/// that point to V2 points to its first element. 4194static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4195 for (unsigned i = 0; i != NumElems; ++i) { 4196 if (Mask[i] > (int)NumElems) { 4197 Mask[i] = NumElems; 4198 } 4199 } 4200} 4201 4202/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4203/// operation of specified width. 4204static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4205 SDValue V2) { 4206 unsigned NumElems = VT.getVectorNumElements(); 4207 SmallVector<int, 8> Mask; 4208 Mask.push_back(NumElems); 4209 for (unsigned i = 1; i != NumElems; ++i) 4210 Mask.push_back(i); 4211 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4212} 4213 4214/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4215static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4216 SDValue V2) { 4217 unsigned NumElems = VT.getVectorNumElements(); 4218 SmallVector<int, 8> Mask; 4219 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4220 Mask.push_back(i); 4221 Mask.push_back(i + NumElems); 4222 } 4223 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4224} 4225 4226/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4227static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4228 SDValue V2) { 4229 unsigned NumElems = VT.getVectorNumElements(); 4230 unsigned Half = NumElems/2; 4231 SmallVector<int, 8> Mask; 4232 for (unsigned i = 0; i != Half; ++i) { 4233 Mask.push_back(i + Half); 4234 Mask.push_back(i + NumElems + Half); 4235 } 4236 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4237} 4238 4239// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4240// a generic shuffle instruction because the target has no such instructions. 4241// Generate shuffles which repeat i16 and i8 several times until they can be 4242// represented by v4f32 and then be manipulated by target suported shuffles. 4243static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4244 EVT VT = V.getValueType(); 4245 int NumElems = VT.getVectorNumElements(); 4246 DebugLoc dl = V.getDebugLoc(); 4247 4248 while (NumElems > 4) { 4249 if (EltNo < NumElems/2) { 4250 V = getUnpackl(DAG, dl, VT, V, V); 4251 } else { 4252 V = getUnpackh(DAG, dl, VT, V, V); 4253 EltNo -= NumElems/2; 4254 } 4255 NumElems >>= 1; 4256 } 4257 return V; 4258} 4259 4260/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4261static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4262 EVT VT = V.getValueType(); 4263 DebugLoc dl = V.getDebugLoc(); 4264 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4265 && "Vector size not supported"); 4266 4267 if (VT.getSizeInBits() == 128) { 4268 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4269 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4270 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4271 &SplatMask[0]); 4272 } else { 4273 // To use VPERMILPS to splat scalars, the second half of indicies must 4274 // refer to the higher part, which is a duplication of the lower one, 4275 // because VPERMILPS can only handle in-lane permutations. 4276 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4277 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4278 4279 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4280 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4281 &SplatMask[0]); 4282 } 4283 4284 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4285} 4286 4287/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4288static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4289 EVT SrcVT = SV->getValueType(0); 4290 SDValue V1 = SV->getOperand(0); 4291 DebugLoc dl = SV->getDebugLoc(); 4292 4293 int EltNo = SV->getSplatIndex(); 4294 int NumElems = SrcVT.getVectorNumElements(); 4295 unsigned Size = SrcVT.getSizeInBits(); 4296 4297 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4298 "Unknown how to promote splat for type"); 4299 4300 // Extract the 128-bit part containing the splat element and update 4301 // the splat element index when it refers to the higher register. 4302 if (Size == 256) { 4303 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4304 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4305 if (Idx > 0) 4306 EltNo -= NumElems/2; 4307 } 4308 4309 // All i16 and i8 vector types can't be used directly by a generic shuffle 4310 // instruction because the target has no such instruction. Generate shuffles 4311 // which repeat i16 and i8 several times until they fit in i32, and then can 4312 // be manipulated by target suported shuffles. 4313 EVT EltVT = SrcVT.getVectorElementType(); 4314 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4315 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4316 4317 // Recreate the 256-bit vector and place the same 128-bit vector 4318 // into the low and high part. This is necessary because we want 4319 // to use VPERM* to shuffle the vectors 4320 if (Size == 256) { 4321 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4322 DAG.getConstant(0, MVT::i32), DAG, dl); 4323 V1 = Insert128BitVector(InsV, V1, 4324 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4325 } 4326 4327 return getLegalSplat(DAG, V1, EltNo); 4328} 4329 4330/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4331/// vector of zero or undef vector. This produces a shuffle where the low 4332/// element of V2 is swizzled into the zero/undef vector, landing at element 4333/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4334static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4335 bool IsZero, 4336 const X86Subtarget *Subtarget, 4337 SelectionDAG &DAG) { 4338 EVT VT = V2.getValueType(); 4339 SDValue V1 = IsZero 4340 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4341 unsigned NumElems = VT.getVectorNumElements(); 4342 SmallVector<int, 16> MaskVec; 4343 for (unsigned i = 0; i != NumElems; ++i) 4344 // If this is the insertion idx, put the low elt of V2 here. 4345 MaskVec.push_back(i == Idx ? NumElems : i); 4346 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4347} 4348 4349/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4350/// target specific opcode. Returns true if the Mask could be calculated. 4351/// Sets IsUnary to true if only uses one source. 4352static bool getTargetShuffleMask(SDNode *N, EVT VT, 4353 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4354 unsigned NumElems = VT.getVectorNumElements(); 4355 SDValue ImmN; 4356 4357 IsUnary = false; 4358 switch(N->getOpcode()) { 4359 case X86ISD::SHUFP: 4360 ImmN = N->getOperand(N->getNumOperands()-1); 4361 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4362 break; 4363 case X86ISD::UNPCKH: 4364 DecodeUNPCKHMask(VT, Mask); 4365 break; 4366 case X86ISD::UNPCKL: 4367 DecodeUNPCKLMask(VT, Mask); 4368 break; 4369 case X86ISD::MOVHLPS: 4370 DecodeMOVHLPSMask(NumElems, Mask); 4371 break; 4372 case X86ISD::MOVLHPS: 4373 DecodeMOVLHPSMask(NumElems, Mask); 4374 break; 4375 case X86ISD::PSHUFD: 4376 case X86ISD::VPERMILP: 4377 ImmN = N->getOperand(N->getNumOperands()-1); 4378 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4379 IsUnary = true; 4380 break; 4381 case X86ISD::PSHUFHW: 4382 ImmN = N->getOperand(N->getNumOperands()-1); 4383 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4384 IsUnary = true; 4385 break; 4386 case X86ISD::PSHUFLW: 4387 ImmN = N->getOperand(N->getNumOperands()-1); 4388 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4389 IsUnary = true; 4390 break; 4391 case X86ISD::MOVSS: 4392 case X86ISD::MOVSD: { 4393 // The index 0 always comes from the first element of the second source, 4394 // this is why MOVSS and MOVSD are used in the first place. The other 4395 // elements come from the other positions of the first source vector 4396 Mask.push_back(NumElems); 4397 for (unsigned i = 1; i != NumElems; ++i) { 4398 Mask.push_back(i); 4399 } 4400 break; 4401 } 4402 case X86ISD::VPERM2X128: 4403 ImmN = N->getOperand(N->getNumOperands()-1); 4404 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4405 break; 4406 case X86ISD::MOVDDUP: 4407 case X86ISD::MOVLHPD: 4408 case X86ISD::MOVLPD: 4409 case X86ISD::MOVLPS: 4410 case X86ISD::MOVSHDUP: 4411 case X86ISD::MOVSLDUP: 4412 case X86ISD::PALIGN: 4413 // Not yet implemented 4414 return false; 4415 default: llvm_unreachable("unknown target shuffle node"); 4416 } 4417 4418 return true; 4419} 4420 4421/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4422/// element of the result of the vector shuffle. 4423static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4424 unsigned Depth) { 4425 if (Depth == 6) 4426 return SDValue(); // Limit search depth. 4427 4428 SDValue V = SDValue(N, 0); 4429 EVT VT = V.getValueType(); 4430 unsigned Opcode = V.getOpcode(); 4431 4432 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4433 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4434 int Elt = SV->getMaskElt(Index); 4435 4436 if (Elt < 0) 4437 return DAG.getUNDEF(VT.getVectorElementType()); 4438 4439 unsigned NumElems = VT.getVectorNumElements(); 4440 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4441 : SV->getOperand(1); 4442 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4443 } 4444 4445 // Recurse into target specific vector shuffles to find scalars. 4446 if (isTargetShuffle(Opcode)) { 4447 unsigned NumElems = VT.getVectorNumElements(); 4448 SmallVector<int, 16> ShuffleMask; 4449 SDValue ImmN; 4450 bool IsUnary; 4451 4452 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary)) 4453 return SDValue(); 4454 4455 int Elt = ShuffleMask[Index]; 4456 if (Elt < 0) 4457 return DAG.getUNDEF(VT.getVectorElementType()); 4458 4459 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4460 : N->getOperand(1); 4461 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4462 Depth+1); 4463 } 4464 4465 // Actual nodes that may contain scalar elements 4466 if (Opcode == ISD::BITCAST) { 4467 V = V.getOperand(0); 4468 EVT SrcVT = V.getValueType(); 4469 unsigned NumElems = VT.getVectorNumElements(); 4470 4471 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4472 return SDValue(); 4473 } 4474 4475 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4476 return (Index == 0) ? V.getOperand(0) 4477 : DAG.getUNDEF(VT.getVectorElementType()); 4478 4479 if (V.getOpcode() == ISD::BUILD_VECTOR) 4480 return V.getOperand(Index); 4481 4482 return SDValue(); 4483} 4484 4485/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4486/// shuffle operation which come from a consecutively from a zero. The 4487/// search can start in two different directions, from left or right. 4488static 4489unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4490 bool ZerosFromLeft, SelectionDAG &DAG) { 4491 unsigned i; 4492 for (i = 0; i != NumElems; ++i) { 4493 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4494 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4495 if (!(Elt.getNode() && 4496 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4497 break; 4498 } 4499 4500 return i; 4501} 4502 4503/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4504/// correspond consecutively to elements from one of the vector operands, 4505/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4506static 4507bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4508 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4509 unsigned NumElems, unsigned &OpNum) { 4510 bool SeenV1 = false; 4511 bool SeenV2 = false; 4512 4513 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4514 int Idx = SVOp->getMaskElt(i); 4515 // Ignore undef indicies 4516 if (Idx < 0) 4517 continue; 4518 4519 if (Idx < (int)NumElems) 4520 SeenV1 = true; 4521 else 4522 SeenV2 = true; 4523 4524 // Only accept consecutive elements from the same vector 4525 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4526 return false; 4527 } 4528 4529 OpNum = SeenV1 ? 0 : 1; 4530 return true; 4531} 4532 4533/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4534/// logical left shift of a vector. 4535static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4536 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4537 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4538 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4539 false /* check zeros from right */, DAG); 4540 unsigned OpSrc; 4541 4542 if (!NumZeros) 4543 return false; 4544 4545 // Considering the elements in the mask that are not consecutive zeros, 4546 // check if they consecutively come from only one of the source vectors. 4547 // 4548 // V1 = {X, A, B, C} 0 4549 // \ \ \ / 4550 // vector_shuffle V1, V2 <1, 2, 3, X> 4551 // 4552 if (!isShuffleMaskConsecutive(SVOp, 4553 0, // Mask Start Index 4554 NumElems-NumZeros, // Mask End Index(exclusive) 4555 NumZeros, // Where to start looking in the src vector 4556 NumElems, // Number of elements in vector 4557 OpSrc)) // Which source operand ? 4558 return false; 4559 4560 isLeft = false; 4561 ShAmt = NumZeros; 4562 ShVal = SVOp->getOperand(OpSrc); 4563 return true; 4564} 4565 4566/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4567/// logical left shift of a vector. 4568static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4569 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4570 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4571 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4572 true /* check zeros from left */, DAG); 4573 unsigned OpSrc; 4574 4575 if (!NumZeros) 4576 return false; 4577 4578 // Considering the elements in the mask that are not consecutive zeros, 4579 // check if they consecutively come from only one of the source vectors. 4580 // 4581 // 0 { A, B, X, X } = V2 4582 // / \ / / 4583 // vector_shuffle V1, V2 <X, X, 4, 5> 4584 // 4585 if (!isShuffleMaskConsecutive(SVOp, 4586 NumZeros, // Mask Start Index 4587 NumElems, // Mask End Index(exclusive) 4588 0, // Where to start looking in the src vector 4589 NumElems, // Number of elements in vector 4590 OpSrc)) // Which source operand ? 4591 return false; 4592 4593 isLeft = true; 4594 ShAmt = NumZeros; 4595 ShVal = SVOp->getOperand(OpSrc); 4596 return true; 4597} 4598 4599/// isVectorShift - Returns true if the shuffle can be implemented as a 4600/// logical left or right shift of a vector. 4601static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4602 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4603 // Although the logic below support any bitwidth size, there are no 4604 // shift instructions which handle more than 128-bit vectors. 4605 if (SVOp->getValueType(0).getSizeInBits() > 128) 4606 return false; 4607 4608 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4609 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4610 return true; 4611 4612 return false; 4613} 4614 4615/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4616/// 4617static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4618 unsigned NumNonZero, unsigned NumZero, 4619 SelectionDAG &DAG, 4620 const X86Subtarget* Subtarget, 4621 const TargetLowering &TLI) { 4622 if (NumNonZero > 8) 4623 return SDValue(); 4624 4625 DebugLoc dl = Op.getDebugLoc(); 4626 SDValue V(0, 0); 4627 bool First = true; 4628 for (unsigned i = 0; i < 16; ++i) { 4629 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4630 if (ThisIsNonZero && First) { 4631 if (NumZero) 4632 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4633 else 4634 V = DAG.getUNDEF(MVT::v8i16); 4635 First = false; 4636 } 4637 4638 if ((i & 1) != 0) { 4639 SDValue ThisElt(0, 0), LastElt(0, 0); 4640 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4641 if (LastIsNonZero) { 4642 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4643 MVT::i16, Op.getOperand(i-1)); 4644 } 4645 if (ThisIsNonZero) { 4646 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4647 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4648 ThisElt, DAG.getConstant(8, MVT::i8)); 4649 if (LastIsNonZero) 4650 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4651 } else 4652 ThisElt = LastElt; 4653 4654 if (ThisElt.getNode()) 4655 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4656 DAG.getIntPtrConstant(i/2)); 4657 } 4658 } 4659 4660 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4661} 4662 4663/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4664/// 4665static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4666 unsigned NumNonZero, unsigned NumZero, 4667 SelectionDAG &DAG, 4668 const X86Subtarget* Subtarget, 4669 const TargetLowering &TLI) { 4670 if (NumNonZero > 4) 4671 return SDValue(); 4672 4673 DebugLoc dl = Op.getDebugLoc(); 4674 SDValue V(0, 0); 4675 bool First = true; 4676 for (unsigned i = 0; i < 8; ++i) { 4677 bool isNonZero = (NonZeros & (1 << i)) != 0; 4678 if (isNonZero) { 4679 if (First) { 4680 if (NumZero) 4681 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4682 else 4683 V = DAG.getUNDEF(MVT::v8i16); 4684 First = false; 4685 } 4686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4687 MVT::v8i16, V, Op.getOperand(i), 4688 DAG.getIntPtrConstant(i)); 4689 } 4690 } 4691 4692 return V; 4693} 4694 4695/// getVShift - Return a vector logical shift node. 4696/// 4697static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4698 unsigned NumBits, SelectionDAG &DAG, 4699 const TargetLowering &TLI, DebugLoc dl) { 4700 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4701 EVT ShVT = MVT::v2i64; 4702 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4703 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4704 return DAG.getNode(ISD::BITCAST, dl, VT, 4705 DAG.getNode(Opc, dl, ShVT, SrcOp, 4706 DAG.getConstant(NumBits, 4707 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4708} 4709 4710SDValue 4711X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4712 SelectionDAG &DAG) const { 4713 4714 // Check if the scalar load can be widened into a vector load. And if 4715 // the address is "base + cst" see if the cst can be "absorbed" into 4716 // the shuffle mask. 4717 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4718 SDValue Ptr = LD->getBasePtr(); 4719 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4720 return SDValue(); 4721 EVT PVT = LD->getValueType(0); 4722 if (PVT != MVT::i32 && PVT != MVT::f32) 4723 return SDValue(); 4724 4725 int FI = -1; 4726 int64_t Offset = 0; 4727 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4728 FI = FINode->getIndex(); 4729 Offset = 0; 4730 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4731 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4732 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4733 Offset = Ptr.getConstantOperandVal(1); 4734 Ptr = Ptr.getOperand(0); 4735 } else { 4736 return SDValue(); 4737 } 4738 4739 // FIXME: 256-bit vector instructions don't require a strict alignment, 4740 // improve this code to support it better. 4741 unsigned RequiredAlign = VT.getSizeInBits()/8; 4742 SDValue Chain = LD->getChain(); 4743 // Make sure the stack object alignment is at least 16 or 32. 4744 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4745 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4746 if (MFI->isFixedObjectIndex(FI)) { 4747 // Can't change the alignment. FIXME: It's possible to compute 4748 // the exact stack offset and reference FI + adjust offset instead. 4749 // If someone *really* cares about this. That's the way to implement it. 4750 return SDValue(); 4751 } else { 4752 MFI->setObjectAlignment(FI, RequiredAlign); 4753 } 4754 } 4755 4756 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4757 // Ptr + (Offset & ~15). 4758 if (Offset < 0) 4759 return SDValue(); 4760 if ((Offset % RequiredAlign) & 3) 4761 return SDValue(); 4762 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4763 if (StartOffset) 4764 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4765 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4766 4767 int EltNo = (Offset - StartOffset) >> 2; 4768 int NumElems = VT.getVectorNumElements(); 4769 4770 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4771 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4772 LD->getPointerInfo().getWithOffset(StartOffset), 4773 false, false, false, 0); 4774 4775 SmallVector<int, 8> Mask; 4776 for (int i = 0; i < NumElems; ++i) 4777 Mask.push_back(EltNo); 4778 4779 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4780 } 4781 4782 return SDValue(); 4783} 4784 4785/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4786/// vector of type 'VT', see if the elements can be replaced by a single large 4787/// load which has the same value as a build_vector whose operands are 'elts'. 4788/// 4789/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4790/// 4791/// FIXME: we'd also like to handle the case where the last elements are zero 4792/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4793/// There's even a handy isZeroNode for that purpose. 4794static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4795 DebugLoc &DL, SelectionDAG &DAG) { 4796 EVT EltVT = VT.getVectorElementType(); 4797 unsigned NumElems = Elts.size(); 4798 4799 LoadSDNode *LDBase = NULL; 4800 unsigned LastLoadedElt = -1U; 4801 4802 // For each element in the initializer, see if we've found a load or an undef. 4803 // If we don't find an initial load element, or later load elements are 4804 // non-consecutive, bail out. 4805 for (unsigned i = 0; i < NumElems; ++i) { 4806 SDValue Elt = Elts[i]; 4807 4808 if (!Elt.getNode() || 4809 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4810 return SDValue(); 4811 if (!LDBase) { 4812 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4813 return SDValue(); 4814 LDBase = cast<LoadSDNode>(Elt.getNode()); 4815 LastLoadedElt = i; 4816 continue; 4817 } 4818 if (Elt.getOpcode() == ISD::UNDEF) 4819 continue; 4820 4821 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4822 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4823 return SDValue(); 4824 LastLoadedElt = i; 4825 } 4826 4827 // If we have found an entire vector of loads and undefs, then return a large 4828 // load of the entire vector width starting at the base pointer. If we found 4829 // consecutive loads for the low half, generate a vzext_load node. 4830 if (LastLoadedElt == NumElems - 1) { 4831 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4832 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4833 LDBase->getPointerInfo(), 4834 LDBase->isVolatile(), LDBase->isNonTemporal(), 4835 LDBase->isInvariant(), 0); 4836 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4837 LDBase->getPointerInfo(), 4838 LDBase->isVolatile(), LDBase->isNonTemporal(), 4839 LDBase->isInvariant(), LDBase->getAlignment()); 4840 } else if (NumElems == 4 && LastLoadedElt == 1 && 4841 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4842 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4843 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4844 SDValue ResNode = 4845 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4846 LDBase->getPointerInfo(), 4847 LDBase->getAlignment(), 4848 false/*isVolatile*/, true/*ReadMem*/, 4849 false/*WriteMem*/); 4850 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4851 } 4852 return SDValue(); 4853} 4854 4855/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 4856/// to generate a splat value for the following cases: 4857/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 4858/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4859/// a scalar load, or a constant. 4860/// The VBROADCAST node is returned when a pattern is found, 4861/// or SDValue() otherwise. 4862SDValue 4863X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { 4864 if (!Subtarget->hasAVX()) 4865 return SDValue(); 4866 4867 EVT VT = Op.getValueType(); 4868 DebugLoc dl = Op.getDebugLoc(); 4869 4870 SDValue Ld; 4871 bool ConstSplatVal; 4872 4873 switch (Op.getOpcode()) { 4874 default: 4875 // Unknown pattern found. 4876 return SDValue(); 4877 4878 case ISD::BUILD_VECTOR: { 4879 // The BUILD_VECTOR node must be a splat. 4880 if (!isSplatVector(Op.getNode())) 4881 return SDValue(); 4882 4883 Ld = Op.getOperand(0); 4884 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4885 Ld.getOpcode() == ISD::ConstantFP); 4886 4887 // The suspected load node has several users. Make sure that all 4888 // of its users are from the BUILD_VECTOR node. 4889 // Constants may have multiple users. 4890 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4891 return SDValue(); 4892 break; 4893 } 4894 4895 case ISD::VECTOR_SHUFFLE: { 4896 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4897 4898 // Shuffles must have a splat mask where the first element is 4899 // broadcasted. 4900 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4901 return SDValue(); 4902 4903 SDValue Sc = Op.getOperand(0); 4904 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4905 return SDValue(); 4906 4907 Ld = Sc.getOperand(0); 4908 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4909 Ld.getOpcode() == ISD::ConstantFP); 4910 4911 // The scalar_to_vector node and the suspected 4912 // load node must have exactly one user. 4913 // Constants may have multiple users. 4914 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 4915 return SDValue(); 4916 break; 4917 } 4918 } 4919 4920 bool Is256 = VT.getSizeInBits() == 256; 4921 bool Is128 = VT.getSizeInBits() == 128; 4922 4923 // Handle the broadcasting a single constant scalar from the constant pool 4924 // into a vector. On Sandybridge it is still better to load a constant vector 4925 // from the constant pool and not to broadcast it from a scalar. 4926 if (ConstSplatVal && Subtarget->hasAVX2()) { 4927 EVT CVT = Ld.getValueType(); 4928 assert(!CVT.isVector() && "Must not broadcast a vector type"); 4929 unsigned ScalarSize = CVT.getSizeInBits(); 4930 4931 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) || 4932 (Is128 && (ScalarSize == 32))) { 4933 4934 const Constant *C = 0; 4935 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 4936 C = CI->getConstantIntValue(); 4937 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 4938 C = CF->getConstantFPValue(); 4939 4940 assert(C && "Invalid constant type"); 4941 4942 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 4943 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 4944 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 4945 MachinePointerInfo::getConstantPool(), 4946 false, false, false, Alignment); 4947 4948 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4949 } 4950 } 4951 4952 // The scalar source must be a normal load. 4953 if (!ISD::isNormalLoad(Ld.getNode())) 4954 return SDValue(); 4955 4956 // Reject loads that have uses of the chain result 4957 if (Ld->hasAnyUseOfValue(1)) 4958 return SDValue(); 4959 4960 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 4961 4962 // VBroadcast to YMM 4963 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 4964 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4965 4966 // VBroadcast to XMM 4967 if (Is128 && (ScalarSize == 32)) 4968 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4969 4970 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 4971 // double since there is vbroadcastsd xmm 4972 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 4973 // VBroadcast to YMM 4974 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 4975 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4976 4977 // VBroadcast to XMM 4978 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 4979 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4980 } 4981 4982 // Unsupported broadcast. 4983 return SDValue(); 4984} 4985 4986SDValue 4987X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4988 DebugLoc dl = Op.getDebugLoc(); 4989 4990 EVT VT = Op.getValueType(); 4991 EVT ExtVT = VT.getVectorElementType(); 4992 unsigned NumElems = Op.getNumOperands(); 4993 4994 // Vectors containing all zeros can be matched by pxor and xorps later 4995 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 4996 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 4997 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 4998 if (VT == MVT::v4i32 || VT == MVT::v8i32) 4999 return Op; 5000 5001 return getZeroVector(VT, Subtarget, DAG, dl); 5002 } 5003 5004 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5005 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5006 // vpcmpeqd on 256-bit vectors. 5007 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5008 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5009 return Op; 5010 5011 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5012 } 5013 5014 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5015 if (Broadcast.getNode()) 5016 return Broadcast; 5017 5018 unsigned EVTBits = ExtVT.getSizeInBits(); 5019 5020 unsigned NumZero = 0; 5021 unsigned NumNonZero = 0; 5022 unsigned NonZeros = 0; 5023 bool IsAllConstants = true; 5024 SmallSet<SDValue, 8> Values; 5025 for (unsigned i = 0; i < NumElems; ++i) { 5026 SDValue Elt = Op.getOperand(i); 5027 if (Elt.getOpcode() == ISD::UNDEF) 5028 continue; 5029 Values.insert(Elt); 5030 if (Elt.getOpcode() != ISD::Constant && 5031 Elt.getOpcode() != ISD::ConstantFP) 5032 IsAllConstants = false; 5033 if (X86::isZeroNode(Elt)) 5034 NumZero++; 5035 else { 5036 NonZeros |= (1 << i); 5037 NumNonZero++; 5038 } 5039 } 5040 5041 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5042 if (NumNonZero == 0) 5043 return DAG.getUNDEF(VT); 5044 5045 // Special case for single non-zero, non-undef, element. 5046 if (NumNonZero == 1) { 5047 unsigned Idx = CountTrailingZeros_32(NonZeros); 5048 SDValue Item = Op.getOperand(Idx); 5049 5050 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5051 // the value are obviously zero, truncate the value to i32 and do the 5052 // insertion that way. Only do this if the value is non-constant or if the 5053 // value is a constant being inserted into element 0. It is cheaper to do 5054 // a constant pool load than it is to do a movd + shuffle. 5055 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5056 (!IsAllConstants || Idx == 0)) { 5057 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5058 // Handle SSE only. 5059 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5060 EVT VecVT = MVT::v4i32; 5061 unsigned VecElts = 4; 5062 5063 // Truncate the value (which may itself be a constant) to i32, and 5064 // convert it to a vector with movd (S2V+shuffle to zero extend). 5065 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5066 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5067 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5068 5069 // Now we have our 32-bit value zero extended in the low element of 5070 // a vector. If Idx != 0, swizzle it into place. 5071 if (Idx != 0) { 5072 SmallVector<int, 4> Mask; 5073 Mask.push_back(Idx); 5074 for (unsigned i = 1; i != VecElts; ++i) 5075 Mask.push_back(i); 5076 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5077 DAG.getUNDEF(Item.getValueType()), 5078 &Mask[0]); 5079 } 5080 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5081 } 5082 } 5083 5084 // If we have a constant or non-constant insertion into the low element of 5085 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5086 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5087 // depending on what the source datatype is. 5088 if (Idx == 0) { 5089 if (NumZero == 0) 5090 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5091 5092 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5093 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5094 if (VT.getSizeInBits() == 256) { 5095 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5096 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5097 Item, DAG.getIntPtrConstant(0)); 5098 } 5099 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5100 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5101 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5102 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5103 } 5104 5105 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5106 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5107 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5108 if (VT.getSizeInBits() == 256) { 5109 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5110 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5111 DAG, dl); 5112 } else { 5113 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5114 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5115 } 5116 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5117 } 5118 } 5119 5120 // Is it a vector logical left shift? 5121 if (NumElems == 2 && Idx == 1 && 5122 X86::isZeroNode(Op.getOperand(0)) && 5123 !X86::isZeroNode(Op.getOperand(1))) { 5124 unsigned NumBits = VT.getSizeInBits(); 5125 return getVShift(true, VT, 5126 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5127 VT, Op.getOperand(1)), 5128 NumBits/2, DAG, *this, dl); 5129 } 5130 5131 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5132 return SDValue(); 5133 5134 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5135 // is a non-constant being inserted into an element other than the low one, 5136 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5137 // movd/movss) to move this into the low element, then shuffle it into 5138 // place. 5139 if (EVTBits == 32) { 5140 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5141 5142 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5143 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5144 SmallVector<int, 8> MaskVec; 5145 for (unsigned i = 0; i < NumElems; i++) 5146 MaskVec.push_back(i == Idx ? 0 : 1); 5147 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5148 } 5149 } 5150 5151 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5152 if (Values.size() == 1) { 5153 if (EVTBits == 32) { 5154 // Instead of a shuffle like this: 5155 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5156 // Check if it's possible to issue this instead. 5157 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5158 unsigned Idx = CountTrailingZeros_32(NonZeros); 5159 SDValue Item = Op.getOperand(Idx); 5160 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5161 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5162 } 5163 return SDValue(); 5164 } 5165 5166 // A vector full of immediates; various special cases are already 5167 // handled, so this is best done with a single constant-pool load. 5168 if (IsAllConstants) 5169 return SDValue(); 5170 5171 // For AVX-length vectors, build the individual 128-bit pieces and use 5172 // shuffles to put them in place. 5173 if (VT.getSizeInBits() == 256) { 5174 SmallVector<SDValue, 32> V; 5175 for (unsigned i = 0; i != NumElems; ++i) 5176 V.push_back(Op.getOperand(i)); 5177 5178 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5179 5180 // Build both the lower and upper subvector. 5181 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5182 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5183 NumElems/2); 5184 5185 // Recreate the wider vector with the lower and upper part. 5186 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5187 DAG.getConstant(0, MVT::i32), DAG, dl); 5188 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5189 DAG, dl); 5190 } 5191 5192 // Let legalizer expand 2-wide build_vectors. 5193 if (EVTBits == 64) { 5194 if (NumNonZero == 1) { 5195 // One half is zero or undef. 5196 unsigned Idx = CountTrailingZeros_32(NonZeros); 5197 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5198 Op.getOperand(Idx)); 5199 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5200 } 5201 return SDValue(); 5202 } 5203 5204 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5205 if (EVTBits == 8 && NumElems == 16) { 5206 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5207 Subtarget, *this); 5208 if (V.getNode()) return V; 5209 } 5210 5211 if (EVTBits == 16 && NumElems == 8) { 5212 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5213 Subtarget, *this); 5214 if (V.getNode()) return V; 5215 } 5216 5217 // If element VT is == 32 bits, turn it into a number of shuffles. 5218 SmallVector<SDValue, 8> V(NumElems); 5219 if (NumElems == 4 && NumZero > 0) { 5220 for (unsigned i = 0; i < 4; ++i) { 5221 bool isZero = !(NonZeros & (1 << i)); 5222 if (isZero) 5223 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5224 else 5225 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5226 } 5227 5228 for (unsigned i = 0; i < 2; ++i) { 5229 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5230 default: break; 5231 case 0: 5232 V[i] = V[i*2]; // Must be a zero vector. 5233 break; 5234 case 1: 5235 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5236 break; 5237 case 2: 5238 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5239 break; 5240 case 3: 5241 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5242 break; 5243 } 5244 } 5245 5246 bool Reverse1 = (NonZeros & 0x3) == 2; 5247 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5248 int MaskVec[] = { 5249 Reverse1 ? 1 : 0, 5250 Reverse1 ? 0 : 1, 5251 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5252 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5253 }; 5254 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5255 } 5256 5257 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5258 // Check for a build vector of consecutive loads. 5259 for (unsigned i = 0; i < NumElems; ++i) 5260 V[i] = Op.getOperand(i); 5261 5262 // Check for elements which are consecutive loads. 5263 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5264 if (LD.getNode()) 5265 return LD; 5266 5267 // For SSE 4.1, use insertps to put the high elements into the low element. 5268 if (getSubtarget()->hasSSE41()) { 5269 SDValue Result; 5270 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5271 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5272 else 5273 Result = DAG.getUNDEF(VT); 5274 5275 for (unsigned i = 1; i < NumElems; ++i) { 5276 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5277 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5278 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5279 } 5280 return Result; 5281 } 5282 5283 // Otherwise, expand into a number of unpckl*, start by extending each of 5284 // our (non-undef) elements to the full vector width with the element in the 5285 // bottom slot of the vector (which generates no code for SSE). 5286 for (unsigned i = 0; i < NumElems; ++i) { 5287 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5288 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5289 else 5290 V[i] = DAG.getUNDEF(VT); 5291 } 5292 5293 // Next, we iteratively mix elements, e.g. for v4f32: 5294 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5295 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5296 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5297 unsigned EltStride = NumElems >> 1; 5298 while (EltStride != 0) { 5299 for (unsigned i = 0; i < EltStride; ++i) { 5300 // If V[i+EltStride] is undef and this is the first round of mixing, 5301 // then it is safe to just drop this shuffle: V[i] is already in the 5302 // right place, the one element (since it's the first round) being 5303 // inserted as undef can be dropped. This isn't safe for successive 5304 // rounds because they will permute elements within both vectors. 5305 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5306 EltStride == NumElems/2) 5307 continue; 5308 5309 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5310 } 5311 EltStride >>= 1; 5312 } 5313 return V[0]; 5314 } 5315 return SDValue(); 5316} 5317 5318// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5319// them in a MMX register. This is better than doing a stack convert. 5320static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5321 DebugLoc dl = Op.getDebugLoc(); 5322 EVT ResVT = Op.getValueType(); 5323 5324 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5325 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5326 int Mask[2]; 5327 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5328 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5329 InVec = Op.getOperand(1); 5330 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5331 unsigned NumElts = ResVT.getVectorNumElements(); 5332 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5333 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5334 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5335 } else { 5336 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5337 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5338 Mask[0] = 0; Mask[1] = 2; 5339 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5340 } 5341 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5342} 5343 5344// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5345// to create 256-bit vectors from two other 128-bit ones. 5346static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5347 DebugLoc dl = Op.getDebugLoc(); 5348 EVT ResVT = Op.getValueType(); 5349 5350 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5351 5352 SDValue V1 = Op.getOperand(0); 5353 SDValue V2 = Op.getOperand(1); 5354 unsigned NumElems = ResVT.getVectorNumElements(); 5355 5356 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5357 DAG.getConstant(0, MVT::i32), DAG, dl); 5358 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5359 DAG, dl); 5360} 5361 5362SDValue 5363X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5364 EVT ResVT = Op.getValueType(); 5365 5366 assert(Op.getNumOperands() == 2); 5367 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5368 "Unsupported CONCAT_VECTORS for value type"); 5369 5370 // We support concatenate two MMX registers and place them in a MMX register. 5371 // This is better than doing a stack convert. 5372 if (ResVT.is128BitVector()) 5373 return LowerMMXCONCAT_VECTORS(Op, DAG); 5374 5375 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5376 // from two other 128-bit ones. 5377 return LowerAVXCONCAT_VECTORS(Op, DAG); 5378} 5379 5380// Try to lower a shuffle node into a simple blend instruction. 5381static SDValue LowerVECTOR_SHUFFLEtoBlend(SDValue Op, 5382 const X86Subtarget *Subtarget, 5383 SelectionDAG &DAG, EVT PtrTy) { 5384 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5385 SDValue V1 = SVOp->getOperand(0); 5386 SDValue V2 = SVOp->getOperand(1); 5387 DebugLoc dl = SVOp->getDebugLoc(); 5388 LLVMContext *Context = DAG.getContext(); 5389 EVT VT = Op.getValueType(); 5390 EVT InVT = V1.getValueType(); 5391 EVT EltVT = VT.getVectorElementType(); 5392 unsigned EltSize = EltVT.getSizeInBits(); 5393 int MaskSize = VT.getVectorNumElements(); 5394 int InSize = InVT.getVectorNumElements(); 5395 5396 // TODO: At the moment we only use AVX blends. We could also use SSE4 blends. 5397 if (!Subtarget->hasAVX()) 5398 return SDValue(); 5399 5400 if (MaskSize != InSize) 5401 return SDValue(); 5402 5403 SmallVector<Constant*,2> MaskVals; 5404 ConstantInt *Zero = ConstantInt::get(*Context, APInt(EltSize, 0)); 5405 ConstantInt *NegOne = ConstantInt::get(*Context, APInt(EltSize, -1)); 5406 5407 for (int i = 0; i < MaskSize; ++i) { 5408 int EltIdx = SVOp->getMaskElt(i); 5409 if (EltIdx == i || EltIdx == -1) 5410 MaskVals.push_back(NegOne); 5411 else if (EltIdx == (i + MaskSize)) 5412 MaskVals.push_back(Zero); 5413 else return SDValue(); 5414 } 5415 5416 Constant *MaskC = ConstantVector::get(MaskVals); 5417 EVT MaskTy = EVT::getEVT(MaskC->getType()); 5418 assert(MaskTy.getSizeInBits() == VT.getSizeInBits() && "Invalid mask size"); 5419 SDValue MaskIdx = DAG.getConstantPool(MaskC, PtrTy); 5420 unsigned Alignment = cast<ConstantPoolSDNode>(MaskIdx)->getAlignment(); 5421 SDValue Mask = DAG.getLoad(MaskTy, dl, DAG.getEntryNode(), MaskIdx, 5422 MachinePointerInfo::getConstantPool(), 5423 false, false, false, Alignment); 5424 5425 if (Subtarget->hasAVX2() && MaskTy == MVT::v32i8) 5426 return DAG.getNode(ISD::VSELECT, dl, VT, Mask, V1, V2); 5427 5428 if (Subtarget->hasAVX()) { 5429 switch (MaskTy.getSimpleVT().SimpleTy) { 5430 default: return SDValue(); 5431 case MVT::v16i8: 5432 case MVT::v4i32: 5433 case MVT::v2i64: 5434 case MVT::v8i32: 5435 case MVT::v4i64: 5436 return DAG.getNode(ISD::VSELECT, dl, VT, Mask, V1, V2); 5437 } 5438 } 5439 5440 return SDValue(); 5441} 5442 5443// v8i16 shuffles - Prefer shuffles in the following order: 5444// 1. [all] pshuflw, pshufhw, optional move 5445// 2. [ssse3] 1 x pshufb 5446// 3. [ssse3] 2 x pshufb + 1 x por 5447// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5448SDValue 5449X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5450 SelectionDAG &DAG) const { 5451 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5452 SDValue V1 = SVOp->getOperand(0); 5453 SDValue V2 = SVOp->getOperand(1); 5454 DebugLoc dl = SVOp->getDebugLoc(); 5455 SmallVector<int, 8> MaskVals; 5456 5457 // Determine if more than 1 of the words in each of the low and high quadwords 5458 // of the result come from the same quadword of one of the two inputs. Undef 5459 // mask values count as coming from any quadword, for better codegen. 5460 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5461 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5462 std::bitset<4> InputQuads; 5463 for (unsigned i = 0; i < 8; ++i) { 5464 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5465 int EltIdx = SVOp->getMaskElt(i); 5466 MaskVals.push_back(EltIdx); 5467 if (EltIdx < 0) { 5468 ++Quad[0]; 5469 ++Quad[1]; 5470 ++Quad[2]; 5471 ++Quad[3]; 5472 continue; 5473 } 5474 ++Quad[EltIdx / 4]; 5475 InputQuads.set(EltIdx / 4); 5476 } 5477 5478 int BestLoQuad = -1; 5479 unsigned MaxQuad = 1; 5480 for (unsigned i = 0; i < 4; ++i) { 5481 if (LoQuad[i] > MaxQuad) { 5482 BestLoQuad = i; 5483 MaxQuad = LoQuad[i]; 5484 } 5485 } 5486 5487 int BestHiQuad = -1; 5488 MaxQuad = 1; 5489 for (unsigned i = 0; i < 4; ++i) { 5490 if (HiQuad[i] > MaxQuad) { 5491 BestHiQuad = i; 5492 MaxQuad = HiQuad[i]; 5493 } 5494 } 5495 5496 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5497 // of the two input vectors, shuffle them into one input vector so only a 5498 // single pshufb instruction is necessary. If There are more than 2 input 5499 // quads, disable the next transformation since it does not help SSSE3. 5500 bool V1Used = InputQuads[0] || InputQuads[1]; 5501 bool V2Used = InputQuads[2] || InputQuads[3]; 5502 if (Subtarget->hasSSSE3()) { 5503 if (InputQuads.count() == 2 && V1Used && V2Used) { 5504 BestLoQuad = InputQuads[0] ? 0 : 1; 5505 BestHiQuad = InputQuads[2] ? 2 : 3; 5506 } 5507 if (InputQuads.count() > 2) { 5508 BestLoQuad = -1; 5509 BestHiQuad = -1; 5510 } 5511 } 5512 5513 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5514 // the shuffle mask. If a quad is scored as -1, that means that it contains 5515 // words from all 4 input quadwords. 5516 SDValue NewV; 5517 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5518 int MaskV[] = { 5519 BestLoQuad < 0 ? 0 : BestLoQuad, 5520 BestHiQuad < 0 ? 1 : BestHiQuad 5521 }; 5522 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5523 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5524 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5525 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5526 5527 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5528 // source words for the shuffle, to aid later transformations. 5529 bool AllWordsInNewV = true; 5530 bool InOrder[2] = { true, true }; 5531 for (unsigned i = 0; i != 8; ++i) { 5532 int idx = MaskVals[i]; 5533 if (idx != (int)i) 5534 InOrder[i/4] = false; 5535 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5536 continue; 5537 AllWordsInNewV = false; 5538 break; 5539 } 5540 5541 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5542 if (AllWordsInNewV) { 5543 for (int i = 0; i != 8; ++i) { 5544 int idx = MaskVals[i]; 5545 if (idx < 0) 5546 continue; 5547 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5548 if ((idx != i) && idx < 4) 5549 pshufhw = false; 5550 if ((idx != i) && idx > 3) 5551 pshuflw = false; 5552 } 5553 V1 = NewV; 5554 V2Used = false; 5555 BestLoQuad = 0; 5556 BestHiQuad = 1; 5557 } 5558 5559 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5560 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5561 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5562 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5563 unsigned TargetMask = 0; 5564 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5565 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5566 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5567 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5568 getShufflePSHUFLWImmediate(SVOp); 5569 V1 = NewV.getOperand(0); 5570 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5571 } 5572 } 5573 5574 // If we have SSSE3, and all words of the result are from 1 input vector, 5575 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5576 // is present, fall back to case 4. 5577 if (Subtarget->hasSSSE3()) { 5578 SmallVector<SDValue,16> pshufbMask; 5579 5580 // If we have elements from both input vectors, set the high bit of the 5581 // shuffle mask element to zero out elements that come from V2 in the V1 5582 // mask, and elements that come from V1 in the V2 mask, so that the two 5583 // results can be OR'd together. 5584 bool TwoInputs = V1Used && V2Used; 5585 for (unsigned i = 0; i != 8; ++i) { 5586 int EltIdx = MaskVals[i] * 2; 5587 if (TwoInputs && (EltIdx >= 16)) { 5588 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5589 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5590 continue; 5591 } 5592 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5593 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5594 } 5595 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5596 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5597 DAG.getNode(ISD::BUILD_VECTOR, dl, 5598 MVT::v16i8, &pshufbMask[0], 16)); 5599 if (!TwoInputs) 5600 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5601 5602 // Calculate the shuffle mask for the second input, shuffle it, and 5603 // OR it with the first shuffled input. 5604 pshufbMask.clear(); 5605 for (unsigned i = 0; i != 8; ++i) { 5606 int EltIdx = MaskVals[i] * 2; 5607 if (EltIdx < 16) { 5608 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5609 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5610 continue; 5611 } 5612 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5613 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5614 } 5615 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5616 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5617 DAG.getNode(ISD::BUILD_VECTOR, dl, 5618 MVT::v16i8, &pshufbMask[0], 16)); 5619 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5620 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5621 } 5622 5623 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5624 // and update MaskVals with new element order. 5625 std::bitset<8> InOrder; 5626 if (BestLoQuad >= 0) { 5627 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5628 for (int i = 0; i != 4; ++i) { 5629 int idx = MaskVals[i]; 5630 if (idx < 0) { 5631 InOrder.set(i); 5632 } else if ((idx / 4) == BestLoQuad) { 5633 MaskV[i] = idx & 3; 5634 InOrder.set(i); 5635 } 5636 } 5637 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5638 &MaskV[0]); 5639 5640 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5641 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5642 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5643 NewV.getOperand(0), 5644 getShufflePSHUFLWImmediate(SVOp), DAG); 5645 } 5646 } 5647 5648 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5649 // and update MaskVals with the new element order. 5650 if (BestHiQuad >= 0) { 5651 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5652 for (unsigned i = 4; i != 8; ++i) { 5653 int idx = MaskVals[i]; 5654 if (idx < 0) { 5655 InOrder.set(i); 5656 } else if ((idx / 4) == BestHiQuad) { 5657 MaskV[i] = (idx & 3) + 4; 5658 InOrder.set(i); 5659 } 5660 } 5661 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5662 &MaskV[0]); 5663 5664 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5665 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5666 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5667 NewV.getOperand(0), 5668 getShufflePSHUFHWImmediate(SVOp), DAG); 5669 } 5670 } 5671 5672 // In case BestHi & BestLo were both -1, which means each quadword has a word 5673 // from each of the four input quadwords, calculate the InOrder bitvector now 5674 // before falling through to the insert/extract cleanup. 5675 if (BestLoQuad == -1 && BestHiQuad == -1) { 5676 NewV = V1; 5677 for (int i = 0; i != 8; ++i) 5678 if (MaskVals[i] < 0 || MaskVals[i] == i) 5679 InOrder.set(i); 5680 } 5681 5682 // The other elements are put in the right place using pextrw and pinsrw. 5683 for (unsigned i = 0; i != 8; ++i) { 5684 if (InOrder[i]) 5685 continue; 5686 int EltIdx = MaskVals[i]; 5687 if (EltIdx < 0) 5688 continue; 5689 SDValue ExtOp = (EltIdx < 8) 5690 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5691 DAG.getIntPtrConstant(EltIdx)) 5692 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5693 DAG.getIntPtrConstant(EltIdx - 8)); 5694 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5695 DAG.getIntPtrConstant(i)); 5696 } 5697 return NewV; 5698} 5699 5700// v16i8 shuffles - Prefer shuffles in the following order: 5701// 1. [ssse3] 1 x pshufb 5702// 2. [ssse3] 2 x pshufb + 1 x por 5703// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5704static 5705SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5706 SelectionDAG &DAG, 5707 const X86TargetLowering &TLI) { 5708 SDValue V1 = SVOp->getOperand(0); 5709 SDValue V2 = SVOp->getOperand(1); 5710 DebugLoc dl = SVOp->getDebugLoc(); 5711 ArrayRef<int> MaskVals = SVOp->getMask(); 5712 5713 // If we have SSSE3, case 1 is generated when all result bytes come from 5714 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5715 // present, fall back to case 3. 5716 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5717 bool V1Only = true; 5718 bool V2Only = true; 5719 for (unsigned i = 0; i < 16; ++i) { 5720 int EltIdx = MaskVals[i]; 5721 if (EltIdx < 0) 5722 continue; 5723 if (EltIdx < 16) 5724 V2Only = false; 5725 else 5726 V1Only = false; 5727 } 5728 5729 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5730 if (TLI.getSubtarget()->hasSSSE3()) { 5731 SmallVector<SDValue,16> pshufbMask; 5732 5733 // If all result elements are from one input vector, then only translate 5734 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5735 // 5736 // Otherwise, we have elements from both input vectors, and must zero out 5737 // elements that come from V2 in the first mask, and V1 in the second mask 5738 // so that we can OR them together. 5739 bool TwoInputs = !(V1Only || V2Only); 5740 for (unsigned i = 0; i != 16; ++i) { 5741 int EltIdx = MaskVals[i]; 5742 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5743 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5744 continue; 5745 } 5746 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5747 } 5748 // If all the elements are from V2, assign it to V1 and return after 5749 // building the first pshufb. 5750 if (V2Only) 5751 V1 = V2; 5752 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5753 DAG.getNode(ISD::BUILD_VECTOR, dl, 5754 MVT::v16i8, &pshufbMask[0], 16)); 5755 if (!TwoInputs) 5756 return V1; 5757 5758 // Calculate the shuffle mask for the second input, shuffle it, and 5759 // OR it with the first shuffled input. 5760 pshufbMask.clear(); 5761 for (unsigned i = 0; i != 16; ++i) { 5762 int EltIdx = MaskVals[i]; 5763 if (EltIdx < 16) { 5764 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5765 continue; 5766 } 5767 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5768 } 5769 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5770 DAG.getNode(ISD::BUILD_VECTOR, dl, 5771 MVT::v16i8, &pshufbMask[0], 16)); 5772 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5773 } 5774 5775 // No SSSE3 - Calculate in place words and then fix all out of place words 5776 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5777 // the 16 different words that comprise the two doublequadword input vectors. 5778 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5779 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5780 SDValue NewV = V2Only ? V2 : V1; 5781 for (int i = 0; i != 8; ++i) { 5782 int Elt0 = MaskVals[i*2]; 5783 int Elt1 = MaskVals[i*2+1]; 5784 5785 // This word of the result is all undef, skip it. 5786 if (Elt0 < 0 && Elt1 < 0) 5787 continue; 5788 5789 // This word of the result is already in the correct place, skip it. 5790 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5791 continue; 5792 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5793 continue; 5794 5795 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5796 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5797 SDValue InsElt; 5798 5799 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5800 // using a single extract together, load it and store it. 5801 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5802 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5803 DAG.getIntPtrConstant(Elt1 / 2)); 5804 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5805 DAG.getIntPtrConstant(i)); 5806 continue; 5807 } 5808 5809 // If Elt1 is defined, extract it from the appropriate source. If the 5810 // source byte is not also odd, shift the extracted word left 8 bits 5811 // otherwise clear the bottom 8 bits if we need to do an or. 5812 if (Elt1 >= 0) { 5813 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5814 DAG.getIntPtrConstant(Elt1 / 2)); 5815 if ((Elt1 & 1) == 0) 5816 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5817 DAG.getConstant(8, 5818 TLI.getShiftAmountTy(InsElt.getValueType()))); 5819 else if (Elt0 >= 0) 5820 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5821 DAG.getConstant(0xFF00, MVT::i16)); 5822 } 5823 // If Elt0 is defined, extract it from the appropriate source. If the 5824 // source byte is not also even, shift the extracted word right 8 bits. If 5825 // Elt1 was also defined, OR the extracted values together before 5826 // inserting them in the result. 5827 if (Elt0 >= 0) { 5828 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5829 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5830 if ((Elt0 & 1) != 0) 5831 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5832 DAG.getConstant(8, 5833 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5834 else if (Elt1 >= 0) 5835 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5836 DAG.getConstant(0x00FF, MVT::i16)); 5837 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5838 : InsElt0; 5839 } 5840 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5841 DAG.getIntPtrConstant(i)); 5842 } 5843 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5844} 5845 5846/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5847/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5848/// done when every pair / quad of shuffle mask elements point to elements in 5849/// the right sequence. e.g. 5850/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5851static 5852SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5853 SelectionDAG &DAG, DebugLoc dl) { 5854 EVT VT = SVOp->getValueType(0); 5855 SDValue V1 = SVOp->getOperand(0); 5856 SDValue V2 = SVOp->getOperand(1); 5857 unsigned NumElems = VT.getVectorNumElements(); 5858 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5859 EVT NewVT; 5860 switch (VT.getSimpleVT().SimpleTy) { 5861 default: llvm_unreachable("Unexpected!"); 5862 case MVT::v4f32: NewVT = MVT::v2f64; break; 5863 case MVT::v4i32: NewVT = MVT::v2i64; break; 5864 case MVT::v8i16: NewVT = MVT::v4i32; break; 5865 case MVT::v16i8: NewVT = MVT::v4i32; break; 5866 } 5867 5868 int Scale = NumElems / NewWidth; 5869 SmallVector<int, 8> MaskVec; 5870 for (unsigned i = 0; i < NumElems; i += Scale) { 5871 int StartIdx = -1; 5872 for (int j = 0; j < Scale; ++j) { 5873 int EltIdx = SVOp->getMaskElt(i+j); 5874 if (EltIdx < 0) 5875 continue; 5876 if (StartIdx == -1) 5877 StartIdx = EltIdx - (EltIdx % Scale); 5878 if (EltIdx != StartIdx + j) 5879 return SDValue(); 5880 } 5881 if (StartIdx == -1) 5882 MaskVec.push_back(-1); 5883 else 5884 MaskVec.push_back(StartIdx / Scale); 5885 } 5886 5887 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5888 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5889 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5890} 5891 5892/// getVZextMovL - Return a zero-extending vector move low node. 5893/// 5894static SDValue getVZextMovL(EVT VT, EVT OpVT, 5895 SDValue SrcOp, SelectionDAG &DAG, 5896 const X86Subtarget *Subtarget, DebugLoc dl) { 5897 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5898 LoadSDNode *LD = NULL; 5899 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5900 LD = dyn_cast<LoadSDNode>(SrcOp); 5901 if (!LD) { 5902 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5903 // instead. 5904 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5905 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5906 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5907 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5908 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5909 // PR2108 5910 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5911 return DAG.getNode(ISD::BITCAST, dl, VT, 5912 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5913 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5914 OpVT, 5915 SrcOp.getOperand(0) 5916 .getOperand(0)))); 5917 } 5918 } 5919 } 5920 5921 return DAG.getNode(ISD::BITCAST, dl, VT, 5922 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5923 DAG.getNode(ISD::BITCAST, dl, 5924 OpVT, SrcOp))); 5925} 5926 5927/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5928/// which could not be matched by any known target speficic shuffle 5929static SDValue 5930LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5931 EVT VT = SVOp->getValueType(0); 5932 5933 unsigned NumElems = VT.getVectorNumElements(); 5934 unsigned NumLaneElems = NumElems / 2; 5935 5936 DebugLoc dl = SVOp->getDebugLoc(); 5937 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5938 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 5939 SDValue Shufs[2]; 5940 5941 SmallVector<int, 16> Mask; 5942 for (unsigned l = 0; l < 2; ++l) { 5943 // Build a shuffle mask for the output, discovering on the fly which 5944 // input vectors to use as shuffle operands (recorded in InputUsed). 5945 // If building a suitable shuffle vector proves too hard, then bail 5946 // out with useBuildVector set. 5947 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 5948 unsigned LaneStart = l * NumLaneElems; 5949 for (unsigned i = 0; i != NumLaneElems; ++i) { 5950 // The mask element. This indexes into the input. 5951 int Idx = SVOp->getMaskElt(i+LaneStart); 5952 if (Idx < 0) { 5953 // the mask element does not index into any input vector. 5954 Mask.push_back(-1); 5955 continue; 5956 } 5957 5958 // The input vector this mask element indexes into. 5959 int Input = Idx / NumLaneElems; 5960 5961 // Turn the index into an offset from the start of the input vector. 5962 Idx -= Input * NumLaneElems; 5963 5964 // Find or create a shuffle vector operand to hold this input. 5965 unsigned OpNo; 5966 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 5967 if (InputUsed[OpNo] == Input) 5968 // This input vector is already an operand. 5969 break; 5970 if (InputUsed[OpNo] < 0) { 5971 // Create a new operand for this input vector. 5972 InputUsed[OpNo] = Input; 5973 break; 5974 } 5975 } 5976 5977 if (OpNo >= array_lengthof(InputUsed)) { 5978 // More than two input vectors used! Give up. 5979 return SDValue(); 5980 } 5981 5982 // Add the mask index for the new shuffle vector. 5983 Mask.push_back(Idx + OpNo * NumLaneElems); 5984 } 5985 5986 if (InputUsed[0] < 0) { 5987 // No input vectors were used! The result is undefined. 5988 Shufs[l] = DAG.getUNDEF(NVT); 5989 } else { 5990 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 5991 DAG.getConstant((InputUsed[0] % 2) * NumLaneElems, MVT::i32), 5992 DAG, dl); 5993 // If only one input was used, use an undefined vector for the other. 5994 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 5995 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 5996 DAG.getConstant((InputUsed[1] % 2) * NumLaneElems, MVT::i32), 5997 DAG, dl); 5998 // At least one input vector was used. Create a new shuffle vector. 5999 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6000 } 6001 6002 Mask.clear(); 6003 } 6004 6005 // Concatenate the result back 6006 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shufs[0], 6007 DAG.getConstant(0, MVT::i32), DAG, dl); 6008 return Insert128BitVector(V, Shufs[1],DAG.getConstant(NumLaneElems, MVT::i32), 6009 DAG, dl); 6010} 6011 6012/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6013/// 4 elements, and match them with several different shuffle types. 6014static SDValue 6015LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6016 SDValue V1 = SVOp->getOperand(0); 6017 SDValue V2 = SVOp->getOperand(1); 6018 DebugLoc dl = SVOp->getDebugLoc(); 6019 EVT VT = SVOp->getValueType(0); 6020 6021 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6022 6023 std::pair<int, int> Locs[4]; 6024 int Mask1[] = { -1, -1, -1, -1 }; 6025 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6026 6027 unsigned NumHi = 0; 6028 unsigned NumLo = 0; 6029 for (unsigned i = 0; i != 4; ++i) { 6030 int Idx = PermMask[i]; 6031 if (Idx < 0) { 6032 Locs[i] = std::make_pair(-1, -1); 6033 } else { 6034 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6035 if (Idx < 4) { 6036 Locs[i] = std::make_pair(0, NumLo); 6037 Mask1[NumLo] = Idx; 6038 NumLo++; 6039 } else { 6040 Locs[i] = std::make_pair(1, NumHi); 6041 if (2+NumHi < 4) 6042 Mask1[2+NumHi] = Idx; 6043 NumHi++; 6044 } 6045 } 6046 } 6047 6048 if (NumLo <= 2 && NumHi <= 2) { 6049 // If no more than two elements come from either vector. This can be 6050 // implemented with two shuffles. First shuffle gather the elements. 6051 // The second shuffle, which takes the first shuffle as both of its 6052 // vector operands, put the elements into the right order. 6053 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6054 6055 int Mask2[] = { -1, -1, -1, -1 }; 6056 6057 for (unsigned i = 0; i != 4; ++i) 6058 if (Locs[i].first != -1) { 6059 unsigned Idx = (i < 2) ? 0 : 4; 6060 Idx += Locs[i].first * 2 + Locs[i].second; 6061 Mask2[i] = Idx; 6062 } 6063 6064 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6065 } else if (NumLo == 3 || NumHi == 3) { 6066 // Otherwise, we must have three elements from one vector, call it X, and 6067 // one element from the other, call it Y. First, use a shufps to build an 6068 // intermediate vector with the one element from Y and the element from X 6069 // that will be in the same half in the final destination (the indexes don't 6070 // matter). Then, use a shufps to build the final vector, taking the half 6071 // containing the element from Y from the intermediate, and the other half 6072 // from X. 6073 if (NumHi == 3) { 6074 // Normalize it so the 3 elements come from V1. 6075 CommuteVectorShuffleMask(PermMask, 4); 6076 std::swap(V1, V2); 6077 } 6078 6079 // Find the element from V2. 6080 unsigned HiIndex; 6081 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6082 int Val = PermMask[HiIndex]; 6083 if (Val < 0) 6084 continue; 6085 if (Val >= 4) 6086 break; 6087 } 6088 6089 Mask1[0] = PermMask[HiIndex]; 6090 Mask1[1] = -1; 6091 Mask1[2] = PermMask[HiIndex^1]; 6092 Mask1[3] = -1; 6093 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6094 6095 if (HiIndex >= 2) { 6096 Mask1[0] = PermMask[0]; 6097 Mask1[1] = PermMask[1]; 6098 Mask1[2] = HiIndex & 1 ? 6 : 4; 6099 Mask1[3] = HiIndex & 1 ? 4 : 6; 6100 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6101 } else { 6102 Mask1[0] = HiIndex & 1 ? 2 : 0; 6103 Mask1[1] = HiIndex & 1 ? 0 : 2; 6104 Mask1[2] = PermMask[2]; 6105 Mask1[3] = PermMask[3]; 6106 if (Mask1[2] >= 0) 6107 Mask1[2] += 4; 6108 if (Mask1[3] >= 0) 6109 Mask1[3] += 4; 6110 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6111 } 6112 } 6113 6114 // Break it into (shuffle shuffle_hi, shuffle_lo). 6115 int LoMask[] = { -1, -1, -1, -1 }; 6116 int HiMask[] = { -1, -1, -1, -1 }; 6117 6118 int *MaskPtr = LoMask; 6119 unsigned MaskIdx = 0; 6120 unsigned LoIdx = 0; 6121 unsigned HiIdx = 2; 6122 for (unsigned i = 0; i != 4; ++i) { 6123 if (i == 2) { 6124 MaskPtr = HiMask; 6125 MaskIdx = 1; 6126 LoIdx = 0; 6127 HiIdx = 2; 6128 } 6129 int Idx = PermMask[i]; 6130 if (Idx < 0) { 6131 Locs[i] = std::make_pair(-1, -1); 6132 } else if (Idx < 4) { 6133 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6134 MaskPtr[LoIdx] = Idx; 6135 LoIdx++; 6136 } else { 6137 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6138 MaskPtr[HiIdx] = Idx; 6139 HiIdx++; 6140 } 6141 } 6142 6143 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6144 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6145 int MaskOps[] = { -1, -1, -1, -1 }; 6146 for (unsigned i = 0; i != 4; ++i) 6147 if (Locs[i].first != -1) 6148 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6149 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6150} 6151 6152static bool MayFoldVectorLoad(SDValue V) { 6153 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6154 V = V.getOperand(0); 6155 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6156 V = V.getOperand(0); 6157 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6158 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6159 // BUILD_VECTOR (load), undef 6160 V = V.getOperand(0); 6161 if (MayFoldLoad(V)) 6162 return true; 6163 return false; 6164} 6165 6166// FIXME: the version above should always be used. Since there's 6167// a bug where several vector shuffles can't be folded because the 6168// DAG is not updated during lowering and a node claims to have two 6169// uses while it only has one, use this version, and let isel match 6170// another instruction if the load really happens to have more than 6171// one use. Remove this version after this bug get fixed. 6172// rdar://8434668, PR8156 6173static bool RelaxedMayFoldVectorLoad(SDValue V) { 6174 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6175 V = V.getOperand(0); 6176 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6177 V = V.getOperand(0); 6178 if (ISD::isNormalLoad(V.getNode())) 6179 return true; 6180 return false; 6181} 6182 6183static 6184SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6185 EVT VT = Op.getValueType(); 6186 6187 // Canonizalize to v2f64. 6188 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6189 return DAG.getNode(ISD::BITCAST, dl, VT, 6190 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6191 V1, DAG)); 6192} 6193 6194static 6195SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6196 bool HasSSE2) { 6197 SDValue V1 = Op.getOperand(0); 6198 SDValue V2 = Op.getOperand(1); 6199 EVT VT = Op.getValueType(); 6200 6201 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6202 6203 if (HasSSE2 && VT == MVT::v2f64) 6204 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6205 6206 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6207 return DAG.getNode(ISD::BITCAST, dl, VT, 6208 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6209 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6210 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6211} 6212 6213static 6214SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6215 SDValue V1 = Op.getOperand(0); 6216 SDValue V2 = Op.getOperand(1); 6217 EVT VT = Op.getValueType(); 6218 6219 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6220 "unsupported shuffle type"); 6221 6222 if (V2.getOpcode() == ISD::UNDEF) 6223 V2 = V1; 6224 6225 // v4i32 or v4f32 6226 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6227} 6228 6229static 6230SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6231 SDValue V1 = Op.getOperand(0); 6232 SDValue V2 = Op.getOperand(1); 6233 EVT VT = Op.getValueType(); 6234 unsigned NumElems = VT.getVectorNumElements(); 6235 6236 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6237 // operand of these instructions is only memory, so check if there's a 6238 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6239 // same masks. 6240 bool CanFoldLoad = false; 6241 6242 // Trivial case, when V2 comes from a load. 6243 if (MayFoldVectorLoad(V2)) 6244 CanFoldLoad = true; 6245 6246 // When V1 is a load, it can be folded later into a store in isel, example: 6247 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6248 // turns into: 6249 // (MOVLPSmr addr:$src1, VR128:$src2) 6250 // So, recognize this potential and also use MOVLPS or MOVLPD 6251 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6252 CanFoldLoad = true; 6253 6254 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6255 if (CanFoldLoad) { 6256 if (HasSSE2 && NumElems == 2) 6257 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6258 6259 if (NumElems == 4) 6260 // If we don't care about the second element, procede to use movss. 6261 if (SVOp->getMaskElt(1) != -1) 6262 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6263 } 6264 6265 // movl and movlp will both match v2i64, but v2i64 is never matched by 6266 // movl earlier because we make it strict to avoid messing with the movlp load 6267 // folding logic (see the code above getMOVLP call). Match it here then, 6268 // this is horrible, but will stay like this until we move all shuffle 6269 // matching to x86 specific nodes. Note that for the 1st condition all 6270 // types are matched with movsd. 6271 if (HasSSE2) { 6272 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6273 // as to remove this logic from here, as much as possible 6274 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6275 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6276 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6277 } 6278 6279 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6280 6281 // Invert the operand order and use SHUFPS to match it. 6282 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6283 getShuffleSHUFImmediate(SVOp), DAG); 6284} 6285 6286SDValue 6287X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6288 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6289 EVT VT = Op.getValueType(); 6290 DebugLoc dl = Op.getDebugLoc(); 6291 SDValue V1 = Op.getOperand(0); 6292 SDValue V2 = Op.getOperand(1); 6293 6294 if (isZeroShuffle(SVOp)) 6295 return getZeroVector(VT, Subtarget, DAG, dl); 6296 6297 // Handle splat operations 6298 if (SVOp->isSplat()) { 6299 unsigned NumElem = VT.getVectorNumElements(); 6300 int Size = VT.getSizeInBits(); 6301 6302 // Use vbroadcast whenever the splat comes from a foldable load 6303 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6304 if (Broadcast.getNode()) 6305 return Broadcast; 6306 6307 // Handle splats by matching through known shuffle masks 6308 if ((Size == 128 && NumElem <= 4) || 6309 (Size == 256 && NumElem < 8)) 6310 return SDValue(); 6311 6312 // All remaning splats are promoted to target supported vector shuffles. 6313 return PromoteSplat(SVOp, DAG); 6314 } 6315 6316 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6317 // do it! 6318 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6319 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6320 if (NewOp.getNode()) 6321 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6322 } else if ((VT == MVT::v4i32 || 6323 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6324 // FIXME: Figure out a cleaner way to do this. 6325 // Try to make use of movq to zero out the top part. 6326 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6327 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6328 if (NewOp.getNode()) { 6329 EVT NewVT = NewOp.getValueType(); 6330 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6331 NewVT, true, false)) 6332 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6333 DAG, Subtarget, dl); 6334 } 6335 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6336 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6337 if (NewOp.getNode()) { 6338 EVT NewVT = NewOp.getValueType(); 6339 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6340 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6341 DAG, Subtarget, dl); 6342 } 6343 } 6344 } 6345 return SDValue(); 6346} 6347 6348SDValue 6349X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6350 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6351 SDValue V1 = Op.getOperand(0); 6352 SDValue V2 = Op.getOperand(1); 6353 EVT VT = Op.getValueType(); 6354 DebugLoc dl = Op.getDebugLoc(); 6355 unsigned NumElems = VT.getVectorNumElements(); 6356 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6357 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6358 bool V1IsSplat = false; 6359 bool V2IsSplat = false; 6360 bool HasSSE2 = Subtarget->hasSSE2(); 6361 bool HasAVX = Subtarget->hasAVX(); 6362 bool HasAVX2 = Subtarget->hasAVX2(); 6363 MachineFunction &MF = DAG.getMachineFunction(); 6364 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6365 6366 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6367 6368 if (V1IsUndef && V2IsUndef) 6369 return DAG.getUNDEF(VT); 6370 6371 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6372 6373 // Vector shuffle lowering takes 3 steps: 6374 // 6375 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6376 // narrowing and commutation of operands should be handled. 6377 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6378 // shuffle nodes. 6379 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6380 // so the shuffle can be broken into other shuffles and the legalizer can 6381 // try the lowering again. 6382 // 6383 // The general idea is that no vector_shuffle operation should be left to 6384 // be matched during isel, all of them must be converted to a target specific 6385 // node here. 6386 6387 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6388 // narrowing and commutation of operands should be handled. The actual code 6389 // doesn't include all of those, work in progress... 6390 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6391 if (NewOp.getNode()) 6392 return NewOp; 6393 6394 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6395 6396 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6397 // unpckh_undef). Only use pshufd if speed is more important than size. 6398 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6399 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6400 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6401 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6402 6403 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6404 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6405 return getMOVDDup(Op, dl, V1, DAG); 6406 6407 if (isMOVHLPS_v_undef_Mask(M, VT)) 6408 return getMOVHighToLow(Op, dl, DAG); 6409 6410 // Use to match splats 6411 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6412 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6413 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6414 6415 if (isPSHUFDMask(M, VT)) { 6416 // The actual implementation will match the mask in the if above and then 6417 // during isel it can match several different instructions, not only pshufd 6418 // as its name says, sad but true, emulate the behavior for now... 6419 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6420 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6421 6422 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6423 6424 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6425 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6426 6427 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6428 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6429 6430 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6431 TargetMask, DAG); 6432 } 6433 6434 // Check if this can be converted into a logical shift. 6435 bool isLeft = false; 6436 unsigned ShAmt = 0; 6437 SDValue ShVal; 6438 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6439 if (isShift && ShVal.hasOneUse()) { 6440 // If the shifted value has multiple uses, it may be cheaper to use 6441 // v_set0 + movlhps or movhlps, etc. 6442 EVT EltVT = VT.getVectorElementType(); 6443 ShAmt *= EltVT.getSizeInBits(); 6444 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6445 } 6446 6447 if (isMOVLMask(M, VT)) { 6448 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6449 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6450 if (!isMOVLPMask(M, VT)) { 6451 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6452 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6453 6454 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6455 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6456 } 6457 } 6458 6459 // FIXME: fold these into legal mask. 6460 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6461 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6462 6463 if (isMOVHLPSMask(M, VT)) 6464 return getMOVHighToLow(Op, dl, DAG); 6465 6466 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6467 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6468 6469 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6470 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6471 6472 if (isMOVLPMask(M, VT)) 6473 return getMOVLP(Op, dl, DAG, HasSSE2); 6474 6475 if (ShouldXformToMOVHLPS(M, VT) || 6476 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6477 return CommuteVectorShuffle(SVOp, DAG); 6478 6479 if (isShift) { 6480 // No better options. Use a vshldq / vsrldq. 6481 EVT EltVT = VT.getVectorElementType(); 6482 ShAmt *= EltVT.getSizeInBits(); 6483 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6484 } 6485 6486 bool Commuted = false; 6487 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6488 // 1,1,1,1 -> v8i16 though. 6489 V1IsSplat = isSplatVector(V1.getNode()); 6490 V2IsSplat = isSplatVector(V2.getNode()); 6491 6492 // Canonicalize the splat or undef, if present, to be on the RHS. 6493 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6494 CommuteVectorShuffleMask(M, NumElems); 6495 std::swap(V1, V2); 6496 std::swap(V1IsSplat, V2IsSplat); 6497 Commuted = true; 6498 } 6499 6500 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6501 // Shuffling low element of v1 into undef, just return v1. 6502 if (V2IsUndef) 6503 return V1; 6504 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6505 // the instruction selector will not match, so get a canonical MOVL with 6506 // swapped operands to undo the commute. 6507 return getMOVL(DAG, dl, VT, V2, V1); 6508 } 6509 6510 if (isUNPCKLMask(M, VT, HasAVX2)) 6511 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6512 6513 if (isUNPCKHMask(M, VT, HasAVX2)) 6514 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6515 6516 if (V2IsSplat) { 6517 // Normalize mask so all entries that point to V2 points to its first 6518 // element then try to match unpck{h|l} again. If match, return a 6519 // new vector_shuffle with the corrected mask.p 6520 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6521 NormalizeMask(NewMask, NumElems); 6522 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) { 6523 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6524 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) { 6525 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6526 } 6527 } 6528 6529 if (Commuted) { 6530 // Commute is back and try unpck* again. 6531 // FIXME: this seems wrong. 6532 CommuteVectorShuffleMask(M, NumElems); 6533 std::swap(V1, V2); 6534 std::swap(V1IsSplat, V2IsSplat); 6535 Commuted = false; 6536 6537 if (isUNPCKLMask(M, VT, HasAVX2)) 6538 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6539 6540 if (isUNPCKHMask(M, VT, HasAVX2)) 6541 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6542 } 6543 6544 // Normalize the node to match x86 shuffle ops if needed 6545 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6546 return CommuteVectorShuffle(SVOp, DAG); 6547 6548 // The checks below are all present in isShuffleMaskLegal, but they are 6549 // inlined here right now to enable us to directly emit target specific 6550 // nodes, and remove one by one until they don't return Op anymore. 6551 6552 if (isPALIGNRMask(M, VT, Subtarget)) 6553 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6554 getShufflePALIGNRImmediate(SVOp), 6555 DAG); 6556 6557 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6558 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6559 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6560 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6561 } 6562 6563 if (isPSHUFHWMask(M, VT)) 6564 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6565 getShufflePSHUFHWImmediate(SVOp), 6566 DAG); 6567 6568 if (isPSHUFLWMask(M, VT)) 6569 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6570 getShufflePSHUFLWImmediate(SVOp), 6571 DAG); 6572 6573 if (isSHUFPMask(M, VT, HasAVX)) 6574 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6575 getShuffleSHUFImmediate(SVOp), DAG); 6576 6577 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6578 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6579 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6580 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6581 6582 //===--------------------------------------------------------------------===// 6583 // Generate target specific nodes for 128 or 256-bit shuffles only 6584 // supported in the AVX instruction set. 6585 // 6586 6587 // Handle VMOVDDUPY permutations 6588 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6589 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6590 6591 // Handle VPERMILPS/D* permutations 6592 if (isVPERMILPMask(M, VT, HasAVX)) { 6593 if (HasAVX2 && VT == MVT::v8i32) 6594 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6595 getShuffleSHUFImmediate(SVOp), DAG); 6596 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6597 getShuffleSHUFImmediate(SVOp), DAG); 6598 } 6599 6600 // Handle VPERM2F128/VPERM2I128 permutations 6601 if (isVPERM2X128Mask(M, VT, HasAVX)) 6602 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6603 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6604 6605 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG, getPointerTy()); 6606 if (BlendOp.getNode()) 6607 return BlendOp; 6608 6609 //===--------------------------------------------------------------------===// 6610 // Since no target specific shuffle was selected for this generic one, 6611 // lower it into other known shuffles. FIXME: this isn't true yet, but 6612 // this is the plan. 6613 // 6614 6615 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6616 if (VT == MVT::v8i16) { 6617 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6618 if (NewOp.getNode()) 6619 return NewOp; 6620 } 6621 6622 if (VT == MVT::v16i8) { 6623 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6624 if (NewOp.getNode()) 6625 return NewOp; 6626 } 6627 6628 // Handle all 128-bit wide vectors with 4 elements, and match them with 6629 // several different shuffle types. 6630 if (NumElems == 4 && VT.getSizeInBits() == 128) 6631 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6632 6633 // Handle general 256-bit shuffles 6634 if (VT.is256BitVector()) 6635 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6636 6637 return SDValue(); 6638} 6639 6640SDValue 6641X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6642 SelectionDAG &DAG) const { 6643 EVT VT = Op.getValueType(); 6644 DebugLoc dl = Op.getDebugLoc(); 6645 6646 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6647 return SDValue(); 6648 6649 if (VT.getSizeInBits() == 8) { 6650 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6651 Op.getOperand(0), Op.getOperand(1)); 6652 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6653 DAG.getValueType(VT)); 6654 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6655 } else if (VT.getSizeInBits() == 16) { 6656 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6657 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6658 if (Idx == 0) 6659 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6660 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6661 DAG.getNode(ISD::BITCAST, dl, 6662 MVT::v4i32, 6663 Op.getOperand(0)), 6664 Op.getOperand(1))); 6665 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6666 Op.getOperand(0), Op.getOperand(1)); 6667 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6668 DAG.getValueType(VT)); 6669 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6670 } else if (VT == MVT::f32) { 6671 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6672 // the result back to FR32 register. It's only worth matching if the 6673 // result has a single use which is a store or a bitcast to i32. And in 6674 // the case of a store, it's not worth it if the index is a constant 0, 6675 // because a MOVSSmr can be used instead, which is smaller and faster. 6676 if (!Op.hasOneUse()) 6677 return SDValue(); 6678 SDNode *User = *Op.getNode()->use_begin(); 6679 if ((User->getOpcode() != ISD::STORE || 6680 (isa<ConstantSDNode>(Op.getOperand(1)) && 6681 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6682 (User->getOpcode() != ISD::BITCAST || 6683 User->getValueType(0) != MVT::i32)) 6684 return SDValue(); 6685 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6686 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6687 Op.getOperand(0)), 6688 Op.getOperand(1)); 6689 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6690 } else if (VT == MVT::i32 || VT == MVT::i64) { 6691 // ExtractPS/pextrq works with constant index. 6692 if (isa<ConstantSDNode>(Op.getOperand(1))) 6693 return Op; 6694 } 6695 return SDValue(); 6696} 6697 6698 6699SDValue 6700X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6701 SelectionDAG &DAG) const { 6702 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6703 return SDValue(); 6704 6705 SDValue Vec = Op.getOperand(0); 6706 EVT VecVT = Vec.getValueType(); 6707 6708 // If this is a 256-bit vector result, first extract the 128-bit vector and 6709 // then extract the element from the 128-bit vector. 6710 if (VecVT.getSizeInBits() == 256) { 6711 DebugLoc dl = Op.getNode()->getDebugLoc(); 6712 unsigned NumElems = VecVT.getVectorNumElements(); 6713 SDValue Idx = Op.getOperand(1); 6714 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6715 6716 // Get the 128-bit vector. 6717 bool Upper = IdxVal >= NumElems/2; 6718 Vec = Extract128BitVector(Vec, 6719 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6720 6721 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6722 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6723 } 6724 6725 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6726 6727 if (Subtarget->hasSSE41()) { 6728 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6729 if (Res.getNode()) 6730 return Res; 6731 } 6732 6733 EVT VT = Op.getValueType(); 6734 DebugLoc dl = Op.getDebugLoc(); 6735 // TODO: handle v16i8. 6736 if (VT.getSizeInBits() == 16) { 6737 SDValue Vec = Op.getOperand(0); 6738 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6739 if (Idx == 0) 6740 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6741 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6742 DAG.getNode(ISD::BITCAST, dl, 6743 MVT::v4i32, Vec), 6744 Op.getOperand(1))); 6745 // Transform it so it match pextrw which produces a 32-bit result. 6746 EVT EltVT = MVT::i32; 6747 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6748 Op.getOperand(0), Op.getOperand(1)); 6749 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6750 DAG.getValueType(VT)); 6751 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6752 } else if (VT.getSizeInBits() == 32) { 6753 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6754 if (Idx == 0) 6755 return Op; 6756 6757 // SHUFPS the element to the lowest double word, then movss. 6758 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6759 EVT VVT = Op.getOperand(0).getValueType(); 6760 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6761 DAG.getUNDEF(VVT), Mask); 6762 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6763 DAG.getIntPtrConstant(0)); 6764 } else if (VT.getSizeInBits() == 64) { 6765 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6766 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6767 // to match extract_elt for f64. 6768 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6769 if (Idx == 0) 6770 return Op; 6771 6772 // UNPCKHPD the element to the lowest double word, then movsd. 6773 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6774 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6775 int Mask[2] = { 1, -1 }; 6776 EVT VVT = Op.getOperand(0).getValueType(); 6777 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6778 DAG.getUNDEF(VVT), Mask); 6779 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6780 DAG.getIntPtrConstant(0)); 6781 } 6782 6783 return SDValue(); 6784} 6785 6786SDValue 6787X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6788 SelectionDAG &DAG) const { 6789 EVT VT = Op.getValueType(); 6790 EVT EltVT = VT.getVectorElementType(); 6791 DebugLoc dl = Op.getDebugLoc(); 6792 6793 SDValue N0 = Op.getOperand(0); 6794 SDValue N1 = Op.getOperand(1); 6795 SDValue N2 = Op.getOperand(2); 6796 6797 if (VT.getSizeInBits() == 256) 6798 return SDValue(); 6799 6800 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6801 isa<ConstantSDNode>(N2)) { 6802 unsigned Opc; 6803 if (VT == MVT::v8i16) 6804 Opc = X86ISD::PINSRW; 6805 else if (VT == MVT::v16i8) 6806 Opc = X86ISD::PINSRB; 6807 else 6808 Opc = X86ISD::PINSRB; 6809 6810 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6811 // argument. 6812 if (N1.getValueType() != MVT::i32) 6813 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6814 if (N2.getValueType() != MVT::i32) 6815 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6816 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6817 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6818 // Bits [7:6] of the constant are the source select. This will always be 6819 // zero here. The DAG Combiner may combine an extract_elt index into these 6820 // bits. For example (insert (extract, 3), 2) could be matched by putting 6821 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6822 // Bits [5:4] of the constant are the destination select. This is the 6823 // value of the incoming immediate. 6824 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6825 // combine either bitwise AND or insert of float 0.0 to set these bits. 6826 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6827 // Create this as a scalar to vector.. 6828 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6829 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6830 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6831 isa<ConstantSDNode>(N2)) { 6832 // PINSR* works with constant index. 6833 return Op; 6834 } 6835 return SDValue(); 6836} 6837 6838SDValue 6839X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6840 EVT VT = Op.getValueType(); 6841 EVT EltVT = VT.getVectorElementType(); 6842 6843 DebugLoc dl = Op.getDebugLoc(); 6844 SDValue N0 = Op.getOperand(0); 6845 SDValue N1 = Op.getOperand(1); 6846 SDValue N2 = Op.getOperand(2); 6847 6848 // If this is a 256-bit vector result, first extract the 128-bit vector, 6849 // insert the element into the extracted half and then place it back. 6850 if (VT.getSizeInBits() == 256) { 6851 if (!isa<ConstantSDNode>(N2)) 6852 return SDValue(); 6853 6854 // Get the desired 128-bit vector half. 6855 unsigned NumElems = VT.getVectorNumElements(); 6856 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6857 bool Upper = IdxVal >= NumElems/2; 6858 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6859 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6860 6861 // Insert the element into the desired half. 6862 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6863 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6864 6865 // Insert the changed part back to the 256-bit vector 6866 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6867 } 6868 6869 if (Subtarget->hasSSE41()) 6870 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6871 6872 if (EltVT == MVT::i8) 6873 return SDValue(); 6874 6875 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6876 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6877 // as its second argument. 6878 if (N1.getValueType() != MVT::i32) 6879 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6880 if (N2.getValueType() != MVT::i32) 6881 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6882 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6883 } 6884 return SDValue(); 6885} 6886 6887SDValue 6888X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6889 LLVMContext *Context = DAG.getContext(); 6890 DebugLoc dl = Op.getDebugLoc(); 6891 EVT OpVT = Op.getValueType(); 6892 6893 // If this is a 256-bit vector result, first insert into a 128-bit 6894 // vector and then insert into the 256-bit vector. 6895 if (OpVT.getSizeInBits() > 128) { 6896 // Insert into a 128-bit vector. 6897 EVT VT128 = EVT::getVectorVT(*Context, 6898 OpVT.getVectorElementType(), 6899 OpVT.getVectorNumElements() / 2); 6900 6901 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6902 6903 // Insert the 128-bit vector. 6904 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6905 DAG.getConstant(0, MVT::i32), 6906 DAG, dl); 6907 } 6908 6909 if (Op.getValueType() == MVT::v1i64 && 6910 Op.getOperand(0).getValueType() == MVT::i64) 6911 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6912 6913 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6914 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6915 "Expected an SSE type!"); 6916 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6917 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6918} 6919 6920// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6921// a simple subregister reference or explicit instructions to grab 6922// upper bits of a vector. 6923SDValue 6924X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6925 if (Subtarget->hasAVX()) { 6926 DebugLoc dl = Op.getNode()->getDebugLoc(); 6927 SDValue Vec = Op.getNode()->getOperand(0); 6928 SDValue Idx = Op.getNode()->getOperand(1); 6929 6930 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6931 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6932 return Extract128BitVector(Vec, Idx, DAG, dl); 6933 } 6934 } 6935 return SDValue(); 6936} 6937 6938// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6939// simple superregister reference or explicit instructions to insert 6940// the upper bits of a vector. 6941SDValue 6942X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6943 if (Subtarget->hasAVX()) { 6944 DebugLoc dl = Op.getNode()->getDebugLoc(); 6945 SDValue Vec = Op.getNode()->getOperand(0); 6946 SDValue SubVec = Op.getNode()->getOperand(1); 6947 SDValue Idx = Op.getNode()->getOperand(2); 6948 6949 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 6950 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 6951 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 6952 } 6953 } 6954 return SDValue(); 6955} 6956 6957// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 6958// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 6959// one of the above mentioned nodes. It has to be wrapped because otherwise 6960// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 6961// be used to form addressing mode. These wrapped nodes will be selected 6962// into MOV32ri. 6963SDValue 6964X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 6965 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 6966 6967 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6968 // global base reg. 6969 unsigned char OpFlag = 0; 6970 unsigned WrapperKind = X86ISD::Wrapper; 6971 CodeModel::Model M = getTargetMachine().getCodeModel(); 6972 6973 if (Subtarget->isPICStyleRIPRel() && 6974 (M == CodeModel::Small || M == CodeModel::Kernel)) 6975 WrapperKind = X86ISD::WrapperRIP; 6976 else if (Subtarget->isPICStyleGOT()) 6977 OpFlag = X86II::MO_GOTOFF; 6978 else if (Subtarget->isPICStyleStubPIC()) 6979 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6980 6981 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 6982 CP->getAlignment(), 6983 CP->getOffset(), OpFlag); 6984 DebugLoc DL = CP->getDebugLoc(); 6985 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6986 // With PIC, the address is actually $g + Offset. 6987 if (OpFlag) { 6988 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6989 DAG.getNode(X86ISD::GlobalBaseReg, 6990 DebugLoc(), getPointerTy()), 6991 Result); 6992 } 6993 6994 return Result; 6995} 6996 6997SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 6998 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 6999 7000 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7001 // global base reg. 7002 unsigned char OpFlag = 0; 7003 unsigned WrapperKind = X86ISD::Wrapper; 7004 CodeModel::Model M = getTargetMachine().getCodeModel(); 7005 7006 if (Subtarget->isPICStyleRIPRel() && 7007 (M == CodeModel::Small || M == CodeModel::Kernel)) 7008 WrapperKind = X86ISD::WrapperRIP; 7009 else if (Subtarget->isPICStyleGOT()) 7010 OpFlag = X86II::MO_GOTOFF; 7011 else if (Subtarget->isPICStyleStubPIC()) 7012 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7013 7014 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7015 OpFlag); 7016 DebugLoc DL = JT->getDebugLoc(); 7017 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7018 7019 // With PIC, the address is actually $g + Offset. 7020 if (OpFlag) 7021 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7022 DAG.getNode(X86ISD::GlobalBaseReg, 7023 DebugLoc(), getPointerTy()), 7024 Result); 7025 7026 return Result; 7027} 7028 7029SDValue 7030X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7031 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7032 7033 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7034 // global base reg. 7035 unsigned char OpFlag = 0; 7036 unsigned WrapperKind = X86ISD::Wrapper; 7037 CodeModel::Model M = getTargetMachine().getCodeModel(); 7038 7039 if (Subtarget->isPICStyleRIPRel() && 7040 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7041 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7042 OpFlag = X86II::MO_GOTPCREL; 7043 WrapperKind = X86ISD::WrapperRIP; 7044 } else if (Subtarget->isPICStyleGOT()) { 7045 OpFlag = X86II::MO_GOT; 7046 } else if (Subtarget->isPICStyleStubPIC()) { 7047 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7048 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7049 OpFlag = X86II::MO_DARWIN_NONLAZY; 7050 } 7051 7052 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7053 7054 DebugLoc DL = Op.getDebugLoc(); 7055 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7056 7057 7058 // With PIC, the address is actually $g + Offset. 7059 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7060 !Subtarget->is64Bit()) { 7061 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7062 DAG.getNode(X86ISD::GlobalBaseReg, 7063 DebugLoc(), getPointerTy()), 7064 Result); 7065 } 7066 7067 // For symbols that require a load from a stub to get the address, emit the 7068 // load. 7069 if (isGlobalStubReference(OpFlag)) 7070 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7071 MachinePointerInfo::getGOT(), false, false, false, 0); 7072 7073 return Result; 7074} 7075 7076SDValue 7077X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7078 // Create the TargetBlockAddressAddress node. 7079 unsigned char OpFlags = 7080 Subtarget->ClassifyBlockAddressReference(); 7081 CodeModel::Model M = getTargetMachine().getCodeModel(); 7082 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7083 DebugLoc dl = Op.getDebugLoc(); 7084 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7085 /*isTarget=*/true, OpFlags); 7086 7087 if (Subtarget->isPICStyleRIPRel() && 7088 (M == CodeModel::Small || M == CodeModel::Kernel)) 7089 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7090 else 7091 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7092 7093 // With PIC, the address is actually $g + Offset. 7094 if (isGlobalRelativeToPICBase(OpFlags)) { 7095 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7096 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7097 Result); 7098 } 7099 7100 return Result; 7101} 7102 7103SDValue 7104X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7105 int64_t Offset, 7106 SelectionDAG &DAG) const { 7107 // Create the TargetGlobalAddress node, folding in the constant 7108 // offset if it is legal. 7109 unsigned char OpFlags = 7110 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7111 CodeModel::Model M = getTargetMachine().getCodeModel(); 7112 SDValue Result; 7113 if (OpFlags == X86II::MO_NO_FLAG && 7114 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7115 // A direct static reference to a global. 7116 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7117 Offset = 0; 7118 } else { 7119 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7120 } 7121 7122 if (Subtarget->isPICStyleRIPRel() && 7123 (M == CodeModel::Small || M == CodeModel::Kernel)) 7124 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7125 else 7126 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7127 7128 // With PIC, the address is actually $g + Offset. 7129 if (isGlobalRelativeToPICBase(OpFlags)) { 7130 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7131 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7132 Result); 7133 } 7134 7135 // For globals that require a load from a stub to get the address, emit the 7136 // load. 7137 if (isGlobalStubReference(OpFlags)) 7138 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7139 MachinePointerInfo::getGOT(), false, false, false, 0); 7140 7141 // If there was a non-zero offset that we didn't fold, create an explicit 7142 // addition for it. 7143 if (Offset != 0) 7144 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7145 DAG.getConstant(Offset, getPointerTy())); 7146 7147 return Result; 7148} 7149 7150SDValue 7151X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7152 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7153 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7154 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7155} 7156 7157static SDValue 7158GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7159 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7160 unsigned char OperandFlags) { 7161 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7162 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7163 DebugLoc dl = GA->getDebugLoc(); 7164 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7165 GA->getValueType(0), 7166 GA->getOffset(), 7167 OperandFlags); 7168 if (InFlag) { 7169 SDValue Ops[] = { Chain, TGA, *InFlag }; 7170 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7171 } else { 7172 SDValue Ops[] = { Chain, TGA }; 7173 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7174 } 7175 7176 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7177 MFI->setAdjustsStack(true); 7178 7179 SDValue Flag = Chain.getValue(1); 7180 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7181} 7182 7183// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7184static SDValue 7185LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7186 const EVT PtrVT) { 7187 SDValue InFlag; 7188 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7189 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7190 DAG.getNode(X86ISD::GlobalBaseReg, 7191 DebugLoc(), PtrVT), InFlag); 7192 InFlag = Chain.getValue(1); 7193 7194 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7195} 7196 7197// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7198static SDValue 7199LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7200 const EVT PtrVT) { 7201 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7202 X86::RAX, X86II::MO_TLSGD); 7203} 7204 7205// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7206// "local exec" model. 7207static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7208 const EVT PtrVT, TLSModel::Model model, 7209 bool is64Bit) { 7210 DebugLoc dl = GA->getDebugLoc(); 7211 7212 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7213 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7214 is64Bit ? 257 : 256)); 7215 7216 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7217 DAG.getIntPtrConstant(0), 7218 MachinePointerInfo(Ptr), 7219 false, false, false, 0); 7220 7221 unsigned char OperandFlags = 0; 7222 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7223 // initialexec. 7224 unsigned WrapperKind = X86ISD::Wrapper; 7225 if (model == TLSModel::LocalExec) { 7226 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7227 } else if (is64Bit) { 7228 assert(model == TLSModel::InitialExec); 7229 OperandFlags = X86II::MO_GOTTPOFF; 7230 WrapperKind = X86ISD::WrapperRIP; 7231 } else { 7232 assert(model == TLSModel::InitialExec); 7233 OperandFlags = X86II::MO_INDNTPOFF; 7234 } 7235 7236 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7237 // exec) 7238 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7239 GA->getValueType(0), 7240 GA->getOffset(), OperandFlags); 7241 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7242 7243 if (model == TLSModel::InitialExec) 7244 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7245 MachinePointerInfo::getGOT(), false, false, false, 0); 7246 7247 // The address of the thread local variable is the add of the thread 7248 // pointer with the offset of the variable. 7249 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7250} 7251 7252SDValue 7253X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7254 7255 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7256 const GlobalValue *GV = GA->getGlobal(); 7257 7258 if (Subtarget->isTargetELF()) { 7259 // TODO: implement the "local dynamic" model 7260 // TODO: implement the "initial exec"model for pic executables 7261 7262 // If GV is an alias then use the aliasee for determining 7263 // thread-localness. 7264 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7265 GV = GA->resolveAliasedGlobal(false); 7266 7267 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7268 7269 switch (model) { 7270 case TLSModel::GeneralDynamic: 7271 case TLSModel::LocalDynamic: // not implemented 7272 if (Subtarget->is64Bit()) 7273 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7274 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7275 7276 case TLSModel::InitialExec: 7277 case TLSModel::LocalExec: 7278 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7279 Subtarget->is64Bit()); 7280 } 7281 } else if (Subtarget->isTargetDarwin()) { 7282 // Darwin only has one model of TLS. Lower to that. 7283 unsigned char OpFlag = 0; 7284 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7285 X86ISD::WrapperRIP : X86ISD::Wrapper; 7286 7287 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7288 // global base reg. 7289 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7290 !Subtarget->is64Bit(); 7291 if (PIC32) 7292 OpFlag = X86II::MO_TLVP_PIC_BASE; 7293 else 7294 OpFlag = X86II::MO_TLVP; 7295 DebugLoc DL = Op.getDebugLoc(); 7296 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7297 GA->getValueType(0), 7298 GA->getOffset(), OpFlag); 7299 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7300 7301 // With PIC32, the address is actually $g + Offset. 7302 if (PIC32) 7303 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7304 DAG.getNode(X86ISD::GlobalBaseReg, 7305 DebugLoc(), getPointerTy()), 7306 Offset); 7307 7308 // Lowering the machine isd will make sure everything is in the right 7309 // location. 7310 SDValue Chain = DAG.getEntryNode(); 7311 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7312 SDValue Args[] = { Chain, Offset }; 7313 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7314 7315 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7316 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7317 MFI->setAdjustsStack(true); 7318 7319 // And our return value (tls address) is in the standard call return value 7320 // location. 7321 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7322 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7323 Chain.getValue(1)); 7324 } else if (Subtarget->isTargetWindows()) { 7325 // Just use the implicit TLS architecture 7326 // Need to generate someting similar to: 7327 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7328 // ; from TEB 7329 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7330 // mov rcx, qword [rdx+rcx*8] 7331 // mov eax, .tls$:tlsvar 7332 // [rax+rcx] contains the address 7333 // Windows 64bit: gs:0x58 7334 // Windows 32bit: fs:__tls_array 7335 7336 // If GV is an alias then use the aliasee for determining 7337 // thread-localness. 7338 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7339 GV = GA->resolveAliasedGlobal(false); 7340 DebugLoc dl = GA->getDebugLoc(); 7341 SDValue Chain = DAG.getEntryNode(); 7342 7343 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7344 // %gs:0x58 (64-bit). 7345 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7346 ? Type::getInt8PtrTy(*DAG.getContext(), 7347 256) 7348 : Type::getInt32PtrTy(*DAG.getContext(), 7349 257)); 7350 7351 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7352 Subtarget->is64Bit() 7353 ? DAG.getIntPtrConstant(0x58) 7354 : DAG.getExternalSymbol("_tls_array", 7355 getPointerTy()), 7356 MachinePointerInfo(Ptr), 7357 false, false, false, 0); 7358 7359 // Load the _tls_index variable 7360 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7361 if (Subtarget->is64Bit()) 7362 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7363 IDX, MachinePointerInfo(), MVT::i32, 7364 false, false, 0); 7365 else 7366 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7367 false, false, false, 0); 7368 7369 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7370 getPointerTy()); 7371 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7372 7373 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7374 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7375 false, false, false, 0); 7376 7377 // Get the offset of start of .tls section 7378 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7379 GA->getValueType(0), 7380 GA->getOffset(), X86II::MO_SECREL); 7381 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7382 7383 // The address of the thread local variable is the add of the thread 7384 // pointer with the offset of the variable. 7385 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7386 } 7387 7388 llvm_unreachable("TLS not implemented for this target."); 7389} 7390 7391 7392/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7393/// and take a 2 x i32 value to shift plus a shift amount. 7394SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7395 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7396 EVT VT = Op.getValueType(); 7397 unsigned VTBits = VT.getSizeInBits(); 7398 DebugLoc dl = Op.getDebugLoc(); 7399 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7400 SDValue ShOpLo = Op.getOperand(0); 7401 SDValue ShOpHi = Op.getOperand(1); 7402 SDValue ShAmt = Op.getOperand(2); 7403 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7404 DAG.getConstant(VTBits - 1, MVT::i8)) 7405 : DAG.getConstant(0, VT); 7406 7407 SDValue Tmp2, Tmp3; 7408 if (Op.getOpcode() == ISD::SHL_PARTS) { 7409 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7410 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7411 } else { 7412 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7413 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7414 } 7415 7416 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7417 DAG.getConstant(VTBits, MVT::i8)); 7418 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7419 AndNode, DAG.getConstant(0, MVT::i8)); 7420 7421 SDValue Hi, Lo; 7422 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7423 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7424 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7425 7426 if (Op.getOpcode() == ISD::SHL_PARTS) { 7427 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7428 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7429 } else { 7430 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7431 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7432 } 7433 7434 SDValue Ops[2] = { Lo, Hi }; 7435 return DAG.getMergeValues(Ops, 2, dl); 7436} 7437 7438SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7439 SelectionDAG &DAG) const { 7440 EVT SrcVT = Op.getOperand(0).getValueType(); 7441 7442 if (SrcVT.isVector()) 7443 return SDValue(); 7444 7445 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7446 "Unknown SINT_TO_FP to lower!"); 7447 7448 // These are really Legal; return the operand so the caller accepts it as 7449 // Legal. 7450 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7451 return Op; 7452 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7453 Subtarget->is64Bit()) { 7454 return Op; 7455 } 7456 7457 DebugLoc dl = Op.getDebugLoc(); 7458 unsigned Size = SrcVT.getSizeInBits()/8; 7459 MachineFunction &MF = DAG.getMachineFunction(); 7460 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7461 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7462 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7463 StackSlot, 7464 MachinePointerInfo::getFixedStack(SSFI), 7465 false, false, 0); 7466 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7467} 7468 7469SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7470 SDValue StackSlot, 7471 SelectionDAG &DAG) const { 7472 // Build the FILD 7473 DebugLoc DL = Op.getDebugLoc(); 7474 SDVTList Tys; 7475 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7476 if (useSSE) 7477 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7478 else 7479 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7480 7481 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7482 7483 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7484 MachineMemOperand *MMO; 7485 if (FI) { 7486 int SSFI = FI->getIndex(); 7487 MMO = 7488 DAG.getMachineFunction() 7489 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7490 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7491 } else { 7492 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7493 StackSlot = StackSlot.getOperand(1); 7494 } 7495 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7496 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7497 X86ISD::FILD, DL, 7498 Tys, Ops, array_lengthof(Ops), 7499 SrcVT, MMO); 7500 7501 if (useSSE) { 7502 Chain = Result.getValue(1); 7503 SDValue InFlag = Result.getValue(2); 7504 7505 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7506 // shouldn't be necessary except that RFP cannot be live across 7507 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7508 MachineFunction &MF = DAG.getMachineFunction(); 7509 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7510 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7511 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7512 Tys = DAG.getVTList(MVT::Other); 7513 SDValue Ops[] = { 7514 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7515 }; 7516 MachineMemOperand *MMO = 7517 DAG.getMachineFunction() 7518 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7519 MachineMemOperand::MOStore, SSFISize, SSFISize); 7520 7521 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7522 Ops, array_lengthof(Ops), 7523 Op.getValueType(), MMO); 7524 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7525 MachinePointerInfo::getFixedStack(SSFI), 7526 false, false, false, 0); 7527 } 7528 7529 return Result; 7530} 7531 7532// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7533SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7534 SelectionDAG &DAG) const { 7535 // This algorithm is not obvious. Here it is what we're trying to output: 7536 /* 7537 movq %rax, %xmm0 7538 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7539 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7540 #ifdef __SSE3__ 7541 haddpd %xmm0, %xmm0 7542 #else 7543 pshufd $0x4e, %xmm0, %xmm1 7544 addpd %xmm1, %xmm0 7545 #endif 7546 */ 7547 7548 DebugLoc dl = Op.getDebugLoc(); 7549 LLVMContext *Context = DAG.getContext(); 7550 7551 // Build some magic constants. 7552 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7553 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7554 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7555 7556 SmallVector<Constant*,2> CV1; 7557 CV1.push_back( 7558 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7559 CV1.push_back( 7560 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7561 Constant *C1 = ConstantVector::get(CV1); 7562 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7563 7564 // Load the 64-bit value into an XMM register. 7565 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7566 Op.getOperand(0)); 7567 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7568 MachinePointerInfo::getConstantPool(), 7569 false, false, false, 16); 7570 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7571 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7572 CLod0); 7573 7574 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7575 MachinePointerInfo::getConstantPool(), 7576 false, false, false, 16); 7577 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7578 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7579 SDValue Result; 7580 7581 if (Subtarget->hasSSE3()) { 7582 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7583 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7584 } else { 7585 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7586 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7587 S2F, 0x4E, DAG); 7588 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7589 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7590 Sub); 7591 } 7592 7593 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7594 DAG.getIntPtrConstant(0)); 7595} 7596 7597// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7598SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7599 SelectionDAG &DAG) const { 7600 DebugLoc dl = Op.getDebugLoc(); 7601 // FP constant to bias correct the final result. 7602 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7603 MVT::f64); 7604 7605 // Load the 32-bit value into an XMM register. 7606 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7607 Op.getOperand(0)); 7608 7609 // Zero out the upper parts of the register. 7610 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7611 7612 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7613 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7614 DAG.getIntPtrConstant(0)); 7615 7616 // Or the load with the bias. 7617 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7618 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7619 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7620 MVT::v2f64, Load)), 7621 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7622 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7623 MVT::v2f64, Bias))); 7624 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7625 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7626 DAG.getIntPtrConstant(0)); 7627 7628 // Subtract the bias. 7629 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7630 7631 // Handle final rounding. 7632 EVT DestVT = Op.getValueType(); 7633 7634 if (DestVT.bitsLT(MVT::f64)) { 7635 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7636 DAG.getIntPtrConstant(0)); 7637 } else if (DestVT.bitsGT(MVT::f64)) { 7638 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7639 } 7640 7641 // Handle final rounding. 7642 return Sub; 7643} 7644 7645SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7646 SelectionDAG &DAG) const { 7647 SDValue N0 = Op.getOperand(0); 7648 DebugLoc dl = Op.getDebugLoc(); 7649 7650 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7651 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7652 // the optimization here. 7653 if (DAG.SignBitIsZero(N0)) 7654 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7655 7656 EVT SrcVT = N0.getValueType(); 7657 EVT DstVT = Op.getValueType(); 7658 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7659 return LowerUINT_TO_FP_i64(Op, DAG); 7660 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7661 return LowerUINT_TO_FP_i32(Op, DAG); 7662 else if (Subtarget->is64Bit() && 7663 SrcVT == MVT::i64 && DstVT == MVT::f32) 7664 return SDValue(); 7665 7666 // Make a 64-bit buffer, and use it to build an FILD. 7667 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7668 if (SrcVT == MVT::i32) { 7669 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7670 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7671 getPointerTy(), StackSlot, WordOff); 7672 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7673 StackSlot, MachinePointerInfo(), 7674 false, false, 0); 7675 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7676 OffsetSlot, MachinePointerInfo(), 7677 false, false, 0); 7678 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7679 return Fild; 7680 } 7681 7682 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7683 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7684 StackSlot, MachinePointerInfo(), 7685 false, false, 0); 7686 // For i64 source, we need to add the appropriate power of 2 if the input 7687 // was negative. This is the same as the optimization in 7688 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7689 // we must be careful to do the computation in x87 extended precision, not 7690 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7691 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7692 MachineMemOperand *MMO = 7693 DAG.getMachineFunction() 7694 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7695 MachineMemOperand::MOLoad, 8, 8); 7696 7697 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7698 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7699 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7700 MVT::i64, MMO); 7701 7702 APInt FF(32, 0x5F800000ULL); 7703 7704 // Check whether the sign bit is set. 7705 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7706 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7707 ISD::SETLT); 7708 7709 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7710 SDValue FudgePtr = DAG.getConstantPool( 7711 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7712 getPointerTy()); 7713 7714 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7715 SDValue Zero = DAG.getIntPtrConstant(0); 7716 SDValue Four = DAG.getIntPtrConstant(4); 7717 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7718 Zero, Four); 7719 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7720 7721 // Load the value out, extending it from f32 to f80. 7722 // FIXME: Avoid the extend by constructing the right constant pool? 7723 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7724 FudgePtr, MachinePointerInfo::getConstantPool(), 7725 MVT::f32, false, false, 4); 7726 // Extend everything to 80 bits to force it to be done on x87. 7727 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7728 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7729} 7730 7731std::pair<SDValue,SDValue> X86TargetLowering:: 7732FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 7733 DebugLoc DL = Op.getDebugLoc(); 7734 7735 EVT DstTy = Op.getValueType(); 7736 7737 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 7738 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7739 DstTy = MVT::i64; 7740 } 7741 7742 assert(DstTy.getSimpleVT() <= MVT::i64 && 7743 DstTy.getSimpleVT() >= MVT::i16 && 7744 "Unknown FP_TO_INT to lower!"); 7745 7746 // These are really Legal. 7747 if (DstTy == MVT::i32 && 7748 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7749 return std::make_pair(SDValue(), SDValue()); 7750 if (Subtarget->is64Bit() && 7751 DstTy == MVT::i64 && 7752 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7753 return std::make_pair(SDValue(), SDValue()); 7754 7755 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 7756 // stack slot, or into the FTOL runtime function. 7757 MachineFunction &MF = DAG.getMachineFunction(); 7758 unsigned MemSize = DstTy.getSizeInBits()/8; 7759 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7760 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7761 7762 unsigned Opc; 7763 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 7764 Opc = X86ISD::WIN_FTOL; 7765 else 7766 switch (DstTy.getSimpleVT().SimpleTy) { 7767 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7768 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7769 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7770 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7771 } 7772 7773 SDValue Chain = DAG.getEntryNode(); 7774 SDValue Value = Op.getOperand(0); 7775 EVT TheVT = Op.getOperand(0).getValueType(); 7776 // FIXME This causes a redundant load/store if the SSE-class value is already 7777 // in memory, such as if it is on the callstack. 7778 if (isScalarFPTypeInSSEReg(TheVT)) { 7779 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7780 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7781 MachinePointerInfo::getFixedStack(SSFI), 7782 false, false, 0); 7783 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7784 SDValue Ops[] = { 7785 Chain, StackSlot, DAG.getValueType(TheVT) 7786 }; 7787 7788 MachineMemOperand *MMO = 7789 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7790 MachineMemOperand::MOLoad, MemSize, MemSize); 7791 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7792 DstTy, MMO); 7793 Chain = Value.getValue(1); 7794 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7795 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7796 } 7797 7798 MachineMemOperand *MMO = 7799 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7800 MachineMemOperand::MOStore, MemSize, MemSize); 7801 7802 if (Opc != X86ISD::WIN_FTOL) { 7803 // Build the FP_TO_INT*_IN_MEM 7804 SDValue Ops[] = { Chain, Value, StackSlot }; 7805 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7806 Ops, 3, DstTy, MMO); 7807 return std::make_pair(FIST, StackSlot); 7808 } else { 7809 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 7810 DAG.getVTList(MVT::Other, MVT::Glue), 7811 Chain, Value); 7812 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 7813 MVT::i32, ftol.getValue(1)); 7814 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 7815 MVT::i32, eax.getValue(2)); 7816 SDValue Ops[] = { eax, edx }; 7817 SDValue pair = IsReplace 7818 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 7819 : DAG.getMergeValues(Ops, 2, DL); 7820 return std::make_pair(pair, SDValue()); 7821 } 7822} 7823 7824SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7825 SelectionDAG &DAG) const { 7826 if (Op.getValueType().isVector()) 7827 return SDValue(); 7828 7829 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7830 /*IsSigned=*/ true, /*IsReplace=*/ false); 7831 SDValue FIST = Vals.first, StackSlot = Vals.second; 7832 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7833 if (FIST.getNode() == 0) return Op; 7834 7835 if (StackSlot.getNode()) 7836 // Load the result. 7837 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7838 FIST, StackSlot, MachinePointerInfo(), 7839 false, false, false, 0); 7840 else 7841 // The node is the result. 7842 return FIST; 7843} 7844 7845SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7846 SelectionDAG &DAG) const { 7847 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7848 /*IsSigned=*/ false, /*IsReplace=*/ false); 7849 SDValue FIST = Vals.first, StackSlot = Vals.second; 7850 assert(FIST.getNode() && "Unexpected failure"); 7851 7852 if (StackSlot.getNode()) 7853 // Load the result. 7854 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7855 FIST, StackSlot, MachinePointerInfo(), 7856 false, false, false, 0); 7857 else 7858 // The node is the result. 7859 return FIST; 7860} 7861 7862SDValue X86TargetLowering::LowerFABS(SDValue Op, 7863 SelectionDAG &DAG) const { 7864 LLVMContext *Context = DAG.getContext(); 7865 DebugLoc dl = Op.getDebugLoc(); 7866 EVT VT = Op.getValueType(); 7867 EVT EltVT = VT; 7868 if (VT.isVector()) 7869 EltVT = VT.getVectorElementType(); 7870 Constant *C; 7871 if (EltVT == MVT::f64) { 7872 C = ConstantVector::getSplat(2, 7873 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7874 } else { 7875 C = ConstantVector::getSplat(4, 7876 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7877 } 7878 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7879 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7880 MachinePointerInfo::getConstantPool(), 7881 false, false, false, 16); 7882 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7883} 7884 7885SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7886 LLVMContext *Context = DAG.getContext(); 7887 DebugLoc dl = Op.getDebugLoc(); 7888 EVT VT = Op.getValueType(); 7889 EVT EltVT = VT; 7890 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7891 if (VT.isVector()) { 7892 EltVT = VT.getVectorElementType(); 7893 NumElts = VT.getVectorNumElements(); 7894 } 7895 Constant *C; 7896 if (EltVT == MVT::f64) 7897 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7898 else 7899 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7900 C = ConstantVector::getSplat(NumElts, C); 7901 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7902 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7903 MachinePointerInfo::getConstantPool(), 7904 false, false, false, 16); 7905 if (VT.isVector()) { 7906 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7907 return DAG.getNode(ISD::BITCAST, dl, VT, 7908 DAG.getNode(ISD::XOR, dl, XORVT, 7909 DAG.getNode(ISD::BITCAST, dl, XORVT, 7910 Op.getOperand(0)), 7911 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7912 } else { 7913 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7914 } 7915} 7916 7917SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7918 LLVMContext *Context = DAG.getContext(); 7919 SDValue Op0 = Op.getOperand(0); 7920 SDValue Op1 = Op.getOperand(1); 7921 DebugLoc dl = Op.getDebugLoc(); 7922 EVT VT = Op.getValueType(); 7923 EVT SrcVT = Op1.getValueType(); 7924 7925 // If second operand is smaller, extend it first. 7926 if (SrcVT.bitsLT(VT)) { 7927 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7928 SrcVT = VT; 7929 } 7930 // And if it is bigger, shrink it first. 7931 if (SrcVT.bitsGT(VT)) { 7932 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7933 SrcVT = VT; 7934 } 7935 7936 // At this point the operands and the result should have the same 7937 // type, and that won't be f80 since that is not custom lowered. 7938 7939 // First get the sign bit of second operand. 7940 SmallVector<Constant*,4> CV; 7941 if (SrcVT == MVT::f64) { 7942 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7943 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7944 } else { 7945 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7946 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7947 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7948 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7949 } 7950 Constant *C = ConstantVector::get(CV); 7951 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7952 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7953 MachinePointerInfo::getConstantPool(), 7954 false, false, false, 16); 7955 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7956 7957 // Shift sign bit right or left if the two operands have different types. 7958 if (SrcVT.bitsGT(VT)) { 7959 // Op0 is MVT::f32, Op1 is MVT::f64. 7960 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7961 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7962 DAG.getConstant(32, MVT::i32)); 7963 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7964 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7965 DAG.getIntPtrConstant(0)); 7966 } 7967 7968 // Clear first operand sign bit. 7969 CV.clear(); 7970 if (VT == MVT::f64) { 7971 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7972 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7973 } else { 7974 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7975 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7976 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7977 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7978 } 7979 C = ConstantVector::get(CV); 7980 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7981 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7982 MachinePointerInfo::getConstantPool(), 7983 false, false, false, 16); 7984 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 7985 7986 // Or the value with the sign bit. 7987 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 7988} 7989 7990SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 7991 SDValue N0 = Op.getOperand(0); 7992 DebugLoc dl = Op.getDebugLoc(); 7993 EVT VT = Op.getValueType(); 7994 7995 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 7996 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 7997 DAG.getConstant(1, VT)); 7998 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 7999} 8000 8001/// Emit nodes that will be selected as "test Op0,Op0", or something 8002/// equivalent. 8003SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8004 SelectionDAG &DAG) const { 8005 DebugLoc dl = Op.getDebugLoc(); 8006 8007 // CF and OF aren't always set the way we want. Determine which 8008 // of these we need. 8009 bool NeedCF = false; 8010 bool NeedOF = false; 8011 switch (X86CC) { 8012 default: break; 8013 case X86::COND_A: case X86::COND_AE: 8014 case X86::COND_B: case X86::COND_BE: 8015 NeedCF = true; 8016 break; 8017 case X86::COND_G: case X86::COND_GE: 8018 case X86::COND_L: case X86::COND_LE: 8019 case X86::COND_O: case X86::COND_NO: 8020 NeedOF = true; 8021 break; 8022 } 8023 8024 // See if we can use the EFLAGS value from the operand instead of 8025 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8026 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8027 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8028 // Emit a CMP with 0, which is the TEST pattern. 8029 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8030 DAG.getConstant(0, Op.getValueType())); 8031 8032 unsigned Opcode = 0; 8033 unsigned NumOperands = 0; 8034 switch (Op.getNode()->getOpcode()) { 8035 case ISD::ADD: 8036 // Due to an isel shortcoming, be conservative if this add is likely to be 8037 // selected as part of a load-modify-store instruction. When the root node 8038 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8039 // uses of other nodes in the match, such as the ADD in this case. This 8040 // leads to the ADD being left around and reselected, with the result being 8041 // two adds in the output. Alas, even if none our users are stores, that 8042 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8043 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8044 // climbing the DAG back to the root, and it doesn't seem to be worth the 8045 // effort. 8046 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8047 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8048 if (UI->getOpcode() != ISD::CopyToReg && 8049 UI->getOpcode() != ISD::SETCC && 8050 UI->getOpcode() != ISD::STORE) 8051 goto default_case; 8052 8053 if (ConstantSDNode *C = 8054 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8055 // An add of one will be selected as an INC. 8056 if (C->getAPIntValue() == 1) { 8057 Opcode = X86ISD::INC; 8058 NumOperands = 1; 8059 break; 8060 } 8061 8062 // An add of negative one (subtract of one) will be selected as a DEC. 8063 if (C->getAPIntValue().isAllOnesValue()) { 8064 Opcode = X86ISD::DEC; 8065 NumOperands = 1; 8066 break; 8067 } 8068 } 8069 8070 // Otherwise use a regular EFLAGS-setting add. 8071 Opcode = X86ISD::ADD; 8072 NumOperands = 2; 8073 break; 8074 case ISD::AND: { 8075 // If the primary and result isn't used, don't bother using X86ISD::AND, 8076 // because a TEST instruction will be better. 8077 bool NonFlagUse = false; 8078 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8079 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8080 SDNode *User = *UI; 8081 unsigned UOpNo = UI.getOperandNo(); 8082 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8083 // Look pass truncate. 8084 UOpNo = User->use_begin().getOperandNo(); 8085 User = *User->use_begin(); 8086 } 8087 8088 if (User->getOpcode() != ISD::BRCOND && 8089 User->getOpcode() != ISD::SETCC && 8090 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8091 NonFlagUse = true; 8092 break; 8093 } 8094 } 8095 8096 if (!NonFlagUse) 8097 break; 8098 } 8099 // FALL THROUGH 8100 case ISD::SUB: 8101 case ISD::OR: 8102 case ISD::XOR: 8103 // Due to the ISEL shortcoming noted above, be conservative if this op is 8104 // likely to be selected as part of a load-modify-store instruction. 8105 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8106 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8107 if (UI->getOpcode() == ISD::STORE) 8108 goto default_case; 8109 8110 // Otherwise use a regular EFLAGS-setting instruction. 8111 switch (Op.getNode()->getOpcode()) { 8112 default: llvm_unreachable("unexpected operator!"); 8113 case ISD::SUB: Opcode = X86ISD::SUB; break; 8114 case ISD::OR: Opcode = X86ISD::OR; break; 8115 case ISD::XOR: Opcode = X86ISD::XOR; break; 8116 case ISD::AND: Opcode = X86ISD::AND; break; 8117 } 8118 8119 NumOperands = 2; 8120 break; 8121 case X86ISD::ADD: 8122 case X86ISD::SUB: 8123 case X86ISD::INC: 8124 case X86ISD::DEC: 8125 case X86ISD::OR: 8126 case X86ISD::XOR: 8127 case X86ISD::AND: 8128 return SDValue(Op.getNode(), 1); 8129 default: 8130 default_case: 8131 break; 8132 } 8133 8134 if (Opcode == 0) 8135 // Emit a CMP with 0, which is the TEST pattern. 8136 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8137 DAG.getConstant(0, Op.getValueType())); 8138 8139 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8140 SmallVector<SDValue, 4> Ops; 8141 for (unsigned i = 0; i != NumOperands; ++i) 8142 Ops.push_back(Op.getOperand(i)); 8143 8144 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8145 DAG.ReplaceAllUsesWith(Op, New); 8146 return SDValue(New.getNode(), 1); 8147} 8148 8149/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8150/// equivalent. 8151SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8152 SelectionDAG &DAG) const { 8153 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8154 if (C->getAPIntValue() == 0) 8155 return EmitTest(Op0, X86CC, DAG); 8156 8157 DebugLoc dl = Op0.getDebugLoc(); 8158 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8159} 8160 8161/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8162/// if it's possible. 8163SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8164 DebugLoc dl, SelectionDAG &DAG) const { 8165 SDValue Op0 = And.getOperand(0); 8166 SDValue Op1 = And.getOperand(1); 8167 if (Op0.getOpcode() == ISD::TRUNCATE) 8168 Op0 = Op0.getOperand(0); 8169 if (Op1.getOpcode() == ISD::TRUNCATE) 8170 Op1 = Op1.getOperand(0); 8171 8172 SDValue LHS, RHS; 8173 if (Op1.getOpcode() == ISD::SHL) 8174 std::swap(Op0, Op1); 8175 if (Op0.getOpcode() == ISD::SHL) { 8176 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8177 if (And00C->getZExtValue() == 1) { 8178 // If we looked past a truncate, check that it's only truncating away 8179 // known zeros. 8180 unsigned BitWidth = Op0.getValueSizeInBits(); 8181 unsigned AndBitWidth = And.getValueSizeInBits(); 8182 if (BitWidth > AndBitWidth) { 8183 APInt Zeros, Ones; 8184 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 8185 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8186 return SDValue(); 8187 } 8188 LHS = Op1; 8189 RHS = Op0.getOperand(1); 8190 } 8191 } else if (Op1.getOpcode() == ISD::Constant) { 8192 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8193 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8194 SDValue AndLHS = Op0; 8195 8196 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8197 LHS = AndLHS.getOperand(0); 8198 RHS = AndLHS.getOperand(1); 8199 } 8200 8201 // Use BT if the immediate can't be encoded in a TEST instruction. 8202 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8203 LHS = AndLHS; 8204 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8205 } 8206 } 8207 8208 if (LHS.getNode()) { 8209 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8210 // instruction. Since the shift amount is in-range-or-undefined, we know 8211 // that doing a bittest on the i32 value is ok. We extend to i32 because 8212 // the encoding for the i16 version is larger than the i32 version. 8213 // Also promote i16 to i32 for performance / code size reason. 8214 if (LHS.getValueType() == MVT::i8 || 8215 LHS.getValueType() == MVT::i16) 8216 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8217 8218 // If the operand types disagree, extend the shift amount to match. Since 8219 // BT ignores high bits (like shifts) we can use anyextend. 8220 if (LHS.getValueType() != RHS.getValueType()) 8221 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8222 8223 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8224 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8225 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8226 DAG.getConstant(Cond, MVT::i8), BT); 8227 } 8228 8229 return SDValue(); 8230} 8231 8232SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8233 8234 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8235 8236 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8237 SDValue Op0 = Op.getOperand(0); 8238 SDValue Op1 = Op.getOperand(1); 8239 DebugLoc dl = Op.getDebugLoc(); 8240 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8241 8242 // Optimize to BT if possible. 8243 // Lower (X & (1 << N)) == 0 to BT(X, N). 8244 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8245 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8246 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8247 Op1.getOpcode() == ISD::Constant && 8248 cast<ConstantSDNode>(Op1)->isNullValue() && 8249 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8250 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8251 if (NewSetCC.getNode()) 8252 return NewSetCC; 8253 } 8254 8255 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8256 // these. 8257 if (Op1.getOpcode() == ISD::Constant && 8258 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8259 cast<ConstantSDNode>(Op1)->isNullValue()) && 8260 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8261 8262 // If the input is a setcc, then reuse the input setcc or use a new one with 8263 // the inverted condition. 8264 if (Op0.getOpcode() == X86ISD::SETCC) { 8265 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8266 bool Invert = (CC == ISD::SETNE) ^ 8267 cast<ConstantSDNode>(Op1)->isNullValue(); 8268 if (!Invert) return Op0; 8269 8270 CCode = X86::GetOppositeBranchCondition(CCode); 8271 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8272 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8273 } 8274 } 8275 8276 bool isFP = Op1.getValueType().isFloatingPoint(); 8277 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8278 if (X86CC == X86::COND_INVALID) 8279 return SDValue(); 8280 8281 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8282 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8283 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8284} 8285 8286// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8287// ones, and then concatenate the result back. 8288static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8289 EVT VT = Op.getValueType(); 8290 8291 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8292 "Unsupported value type for operation"); 8293 8294 int NumElems = VT.getVectorNumElements(); 8295 DebugLoc dl = Op.getDebugLoc(); 8296 SDValue CC = Op.getOperand(2); 8297 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8298 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8299 8300 // Extract the LHS vectors 8301 SDValue LHS = Op.getOperand(0); 8302 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8303 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8304 8305 // Extract the RHS vectors 8306 SDValue RHS = Op.getOperand(1); 8307 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8308 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8309 8310 // Issue the operation on the smaller types and concatenate the result back 8311 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8312 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8313 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8314 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8315 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8316} 8317 8318 8319SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8320 SDValue Cond; 8321 SDValue Op0 = Op.getOperand(0); 8322 SDValue Op1 = Op.getOperand(1); 8323 SDValue CC = Op.getOperand(2); 8324 EVT VT = Op.getValueType(); 8325 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8326 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8327 DebugLoc dl = Op.getDebugLoc(); 8328 8329 if (isFP) { 8330 unsigned SSECC = 8; 8331 EVT EltVT = Op0.getValueType().getVectorElementType(); 8332 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8333 8334 bool Swap = false; 8335 8336 // SSE Condition code mapping: 8337 // 0 - EQ 8338 // 1 - LT 8339 // 2 - LE 8340 // 3 - UNORD 8341 // 4 - NEQ 8342 // 5 - NLT 8343 // 6 - NLE 8344 // 7 - ORD 8345 switch (SetCCOpcode) { 8346 default: break; 8347 case ISD::SETOEQ: 8348 case ISD::SETEQ: SSECC = 0; break; 8349 case ISD::SETOGT: 8350 case ISD::SETGT: Swap = true; // Fallthrough 8351 case ISD::SETLT: 8352 case ISD::SETOLT: SSECC = 1; break; 8353 case ISD::SETOGE: 8354 case ISD::SETGE: Swap = true; // Fallthrough 8355 case ISD::SETLE: 8356 case ISD::SETOLE: SSECC = 2; break; 8357 case ISD::SETUO: SSECC = 3; break; 8358 case ISD::SETUNE: 8359 case ISD::SETNE: SSECC = 4; break; 8360 case ISD::SETULE: Swap = true; 8361 case ISD::SETUGE: SSECC = 5; break; 8362 case ISD::SETULT: Swap = true; 8363 case ISD::SETUGT: SSECC = 6; break; 8364 case ISD::SETO: SSECC = 7; break; 8365 } 8366 if (Swap) 8367 std::swap(Op0, Op1); 8368 8369 // In the two special cases we can't handle, emit two comparisons. 8370 if (SSECC == 8) { 8371 if (SetCCOpcode == ISD::SETUEQ) { 8372 SDValue UNORD, EQ; 8373 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8374 DAG.getConstant(3, MVT::i8)); 8375 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8376 DAG.getConstant(0, MVT::i8)); 8377 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8378 } else if (SetCCOpcode == ISD::SETONE) { 8379 SDValue ORD, NEQ; 8380 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8381 DAG.getConstant(7, MVT::i8)); 8382 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8383 DAG.getConstant(4, MVT::i8)); 8384 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8385 } 8386 llvm_unreachable("Illegal FP comparison"); 8387 } 8388 // Handle all other FP comparisons here. 8389 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8390 DAG.getConstant(SSECC, MVT::i8)); 8391 } 8392 8393 // Break 256-bit integer vector compare into smaller ones. 8394 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8395 return Lower256IntVSETCC(Op, DAG); 8396 8397 // We are handling one of the integer comparisons here. Since SSE only has 8398 // GT and EQ comparisons for integer, swapping operands and multiple 8399 // operations may be required for some comparisons. 8400 unsigned Opc = 0; 8401 bool Swap = false, Invert = false, FlipSigns = false; 8402 8403 switch (SetCCOpcode) { 8404 default: break; 8405 case ISD::SETNE: Invert = true; 8406 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8407 case ISD::SETLT: Swap = true; 8408 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8409 case ISD::SETGE: Swap = true; 8410 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8411 case ISD::SETULT: Swap = true; 8412 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8413 case ISD::SETUGE: Swap = true; 8414 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8415 } 8416 if (Swap) 8417 std::swap(Op0, Op1); 8418 8419 // Check that the operation in question is available (most are plain SSE2, 8420 // but PCMPGTQ and PCMPEQQ have different requirements). 8421 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8422 return SDValue(); 8423 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8424 return SDValue(); 8425 8426 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8427 // bits of the inputs before performing those operations. 8428 if (FlipSigns) { 8429 EVT EltVT = VT.getVectorElementType(); 8430 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8431 EltVT); 8432 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8433 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8434 SignBits.size()); 8435 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8436 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8437 } 8438 8439 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8440 8441 // If the logical-not of the result is required, perform that now. 8442 if (Invert) 8443 Result = DAG.getNOT(dl, Result, VT); 8444 8445 return Result; 8446} 8447 8448// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8449static bool isX86LogicalCmp(SDValue Op) { 8450 unsigned Opc = Op.getNode()->getOpcode(); 8451 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8452 return true; 8453 if (Op.getResNo() == 1 && 8454 (Opc == X86ISD::ADD || 8455 Opc == X86ISD::SUB || 8456 Opc == X86ISD::ADC || 8457 Opc == X86ISD::SBB || 8458 Opc == X86ISD::SMUL || 8459 Opc == X86ISD::UMUL || 8460 Opc == X86ISD::INC || 8461 Opc == X86ISD::DEC || 8462 Opc == X86ISD::OR || 8463 Opc == X86ISD::XOR || 8464 Opc == X86ISD::AND)) 8465 return true; 8466 8467 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8468 return true; 8469 8470 return false; 8471} 8472 8473static bool isZero(SDValue V) { 8474 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8475 return C && C->isNullValue(); 8476} 8477 8478static bool isAllOnes(SDValue V) { 8479 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8480 return C && C->isAllOnesValue(); 8481} 8482 8483SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8484 bool addTest = true; 8485 SDValue Cond = Op.getOperand(0); 8486 SDValue Op1 = Op.getOperand(1); 8487 SDValue Op2 = Op.getOperand(2); 8488 DebugLoc DL = Op.getDebugLoc(); 8489 SDValue CC; 8490 8491 if (Cond.getOpcode() == ISD::SETCC) { 8492 SDValue NewCond = LowerSETCC(Cond, DAG); 8493 if (NewCond.getNode()) 8494 Cond = NewCond; 8495 } 8496 8497 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8498 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8499 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8500 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8501 if (Cond.getOpcode() == X86ISD::SETCC && 8502 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8503 isZero(Cond.getOperand(1).getOperand(1))) { 8504 SDValue Cmp = Cond.getOperand(1); 8505 8506 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8507 8508 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8509 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8510 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8511 8512 SDValue CmpOp0 = Cmp.getOperand(0); 8513 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8514 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8515 8516 SDValue Res = // Res = 0 or -1. 8517 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8518 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8519 8520 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8521 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8522 8523 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8524 if (N2C == 0 || !N2C->isNullValue()) 8525 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8526 return Res; 8527 } 8528 } 8529 8530 // Look past (and (setcc_carry (cmp ...)), 1). 8531 if (Cond.getOpcode() == ISD::AND && 8532 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8533 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8534 if (C && C->getAPIntValue() == 1) 8535 Cond = Cond.getOperand(0); 8536 } 8537 8538 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8539 // setting operand in place of the X86ISD::SETCC. 8540 unsigned CondOpcode = Cond.getOpcode(); 8541 if (CondOpcode == X86ISD::SETCC || 8542 CondOpcode == X86ISD::SETCC_CARRY) { 8543 CC = Cond.getOperand(0); 8544 8545 SDValue Cmp = Cond.getOperand(1); 8546 unsigned Opc = Cmp.getOpcode(); 8547 EVT VT = Op.getValueType(); 8548 8549 bool IllegalFPCMov = false; 8550 if (VT.isFloatingPoint() && !VT.isVector() && 8551 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8552 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8553 8554 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8555 Opc == X86ISD::BT) { // FIXME 8556 Cond = Cmp; 8557 addTest = false; 8558 } 8559 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8560 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8561 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8562 Cond.getOperand(0).getValueType() != MVT::i8)) { 8563 SDValue LHS = Cond.getOperand(0); 8564 SDValue RHS = Cond.getOperand(1); 8565 unsigned X86Opcode; 8566 unsigned X86Cond; 8567 SDVTList VTs; 8568 switch (CondOpcode) { 8569 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8570 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8571 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8572 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8573 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8574 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8575 default: llvm_unreachable("unexpected overflowing operator"); 8576 } 8577 if (CondOpcode == ISD::UMULO) 8578 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8579 MVT::i32); 8580 else 8581 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8582 8583 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8584 8585 if (CondOpcode == ISD::UMULO) 8586 Cond = X86Op.getValue(2); 8587 else 8588 Cond = X86Op.getValue(1); 8589 8590 CC = DAG.getConstant(X86Cond, MVT::i8); 8591 addTest = false; 8592 } 8593 8594 if (addTest) { 8595 // Look pass the truncate. 8596 if (Cond.getOpcode() == ISD::TRUNCATE) 8597 Cond = Cond.getOperand(0); 8598 8599 // We know the result of AND is compared against zero. Try to match 8600 // it to BT. 8601 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8602 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8603 if (NewSetCC.getNode()) { 8604 CC = NewSetCC.getOperand(0); 8605 Cond = NewSetCC.getOperand(1); 8606 addTest = false; 8607 } 8608 } 8609 } 8610 8611 if (addTest) { 8612 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8613 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8614 } 8615 8616 // a < b ? -1 : 0 -> RES = ~setcc_carry 8617 // a < b ? 0 : -1 -> RES = setcc_carry 8618 // a >= b ? -1 : 0 -> RES = setcc_carry 8619 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8620 if (Cond.getOpcode() == X86ISD::CMP) { 8621 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8622 8623 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8624 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8625 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8626 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8627 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8628 return DAG.getNOT(DL, Res, Res.getValueType()); 8629 return Res; 8630 } 8631 } 8632 8633 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8634 // condition is true. 8635 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8636 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8637 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8638} 8639 8640// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8641// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8642// from the AND / OR. 8643static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8644 Opc = Op.getOpcode(); 8645 if (Opc != ISD::OR && Opc != ISD::AND) 8646 return false; 8647 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8648 Op.getOperand(0).hasOneUse() && 8649 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8650 Op.getOperand(1).hasOneUse()); 8651} 8652 8653// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8654// 1 and that the SETCC node has a single use. 8655static bool isXor1OfSetCC(SDValue Op) { 8656 if (Op.getOpcode() != ISD::XOR) 8657 return false; 8658 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8659 if (N1C && N1C->getAPIntValue() == 1) { 8660 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8661 Op.getOperand(0).hasOneUse(); 8662 } 8663 return false; 8664} 8665 8666SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8667 bool addTest = true; 8668 SDValue Chain = Op.getOperand(0); 8669 SDValue Cond = Op.getOperand(1); 8670 SDValue Dest = Op.getOperand(2); 8671 DebugLoc dl = Op.getDebugLoc(); 8672 SDValue CC; 8673 bool Inverted = false; 8674 8675 if (Cond.getOpcode() == ISD::SETCC) { 8676 // Check for setcc([su]{add,sub,mul}o == 0). 8677 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8678 isa<ConstantSDNode>(Cond.getOperand(1)) && 8679 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8680 Cond.getOperand(0).getResNo() == 1 && 8681 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8682 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8683 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8684 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8685 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8686 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8687 Inverted = true; 8688 Cond = Cond.getOperand(0); 8689 } else { 8690 SDValue NewCond = LowerSETCC(Cond, DAG); 8691 if (NewCond.getNode()) 8692 Cond = NewCond; 8693 } 8694 } 8695#if 0 8696 // FIXME: LowerXALUO doesn't handle these!! 8697 else if (Cond.getOpcode() == X86ISD::ADD || 8698 Cond.getOpcode() == X86ISD::SUB || 8699 Cond.getOpcode() == X86ISD::SMUL || 8700 Cond.getOpcode() == X86ISD::UMUL) 8701 Cond = LowerXALUO(Cond, DAG); 8702#endif 8703 8704 // Look pass (and (setcc_carry (cmp ...)), 1). 8705 if (Cond.getOpcode() == ISD::AND && 8706 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8708 if (C && C->getAPIntValue() == 1) 8709 Cond = Cond.getOperand(0); 8710 } 8711 8712 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8713 // setting operand in place of the X86ISD::SETCC. 8714 unsigned CondOpcode = Cond.getOpcode(); 8715 if (CondOpcode == X86ISD::SETCC || 8716 CondOpcode == X86ISD::SETCC_CARRY) { 8717 CC = Cond.getOperand(0); 8718 8719 SDValue Cmp = Cond.getOperand(1); 8720 unsigned Opc = Cmp.getOpcode(); 8721 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8722 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8723 Cond = Cmp; 8724 addTest = false; 8725 } else { 8726 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8727 default: break; 8728 case X86::COND_O: 8729 case X86::COND_B: 8730 // These can only come from an arithmetic instruction with overflow, 8731 // e.g. SADDO, UADDO. 8732 Cond = Cond.getNode()->getOperand(1); 8733 addTest = false; 8734 break; 8735 } 8736 } 8737 } 8738 CondOpcode = Cond.getOpcode(); 8739 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8740 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8741 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8742 Cond.getOperand(0).getValueType() != MVT::i8)) { 8743 SDValue LHS = Cond.getOperand(0); 8744 SDValue RHS = Cond.getOperand(1); 8745 unsigned X86Opcode; 8746 unsigned X86Cond; 8747 SDVTList VTs; 8748 switch (CondOpcode) { 8749 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8750 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8751 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8752 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8753 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8754 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8755 default: llvm_unreachable("unexpected overflowing operator"); 8756 } 8757 if (Inverted) 8758 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8759 if (CondOpcode == ISD::UMULO) 8760 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8761 MVT::i32); 8762 else 8763 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8764 8765 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8766 8767 if (CondOpcode == ISD::UMULO) 8768 Cond = X86Op.getValue(2); 8769 else 8770 Cond = X86Op.getValue(1); 8771 8772 CC = DAG.getConstant(X86Cond, MVT::i8); 8773 addTest = false; 8774 } else { 8775 unsigned CondOpc; 8776 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8777 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8778 if (CondOpc == ISD::OR) { 8779 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8780 // two branches instead of an explicit OR instruction with a 8781 // separate test. 8782 if (Cmp == Cond.getOperand(1).getOperand(1) && 8783 isX86LogicalCmp(Cmp)) { 8784 CC = Cond.getOperand(0).getOperand(0); 8785 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8786 Chain, Dest, CC, Cmp); 8787 CC = Cond.getOperand(1).getOperand(0); 8788 Cond = Cmp; 8789 addTest = false; 8790 } 8791 } else { // ISD::AND 8792 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8793 // two branches instead of an explicit AND instruction with a 8794 // separate test. However, we only do this if this block doesn't 8795 // have a fall-through edge, because this requires an explicit 8796 // jmp when the condition is false. 8797 if (Cmp == Cond.getOperand(1).getOperand(1) && 8798 isX86LogicalCmp(Cmp) && 8799 Op.getNode()->hasOneUse()) { 8800 X86::CondCode CCode = 8801 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8802 CCode = X86::GetOppositeBranchCondition(CCode); 8803 CC = DAG.getConstant(CCode, MVT::i8); 8804 SDNode *User = *Op.getNode()->use_begin(); 8805 // Look for an unconditional branch following this conditional branch. 8806 // We need this because we need to reverse the successors in order 8807 // to implement FCMP_OEQ. 8808 if (User->getOpcode() == ISD::BR) { 8809 SDValue FalseBB = User->getOperand(1); 8810 SDNode *NewBR = 8811 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8812 assert(NewBR == User); 8813 (void)NewBR; 8814 Dest = FalseBB; 8815 8816 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8817 Chain, Dest, CC, Cmp); 8818 X86::CondCode CCode = 8819 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8820 CCode = X86::GetOppositeBranchCondition(CCode); 8821 CC = DAG.getConstant(CCode, MVT::i8); 8822 Cond = Cmp; 8823 addTest = false; 8824 } 8825 } 8826 } 8827 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8828 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8829 // It should be transformed during dag combiner except when the condition 8830 // is set by a arithmetics with overflow node. 8831 X86::CondCode CCode = 8832 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8833 CCode = X86::GetOppositeBranchCondition(CCode); 8834 CC = DAG.getConstant(CCode, MVT::i8); 8835 Cond = Cond.getOperand(0).getOperand(1); 8836 addTest = false; 8837 } else if (Cond.getOpcode() == ISD::SETCC && 8838 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8839 // For FCMP_OEQ, we can emit 8840 // two branches instead of an explicit AND instruction with a 8841 // separate test. However, we only do this if this block doesn't 8842 // have a fall-through edge, because this requires an explicit 8843 // jmp when the condition is false. 8844 if (Op.getNode()->hasOneUse()) { 8845 SDNode *User = *Op.getNode()->use_begin(); 8846 // Look for an unconditional branch following this conditional branch. 8847 // We need this because we need to reverse the successors in order 8848 // to implement FCMP_OEQ. 8849 if (User->getOpcode() == ISD::BR) { 8850 SDValue FalseBB = User->getOperand(1); 8851 SDNode *NewBR = 8852 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8853 assert(NewBR == User); 8854 (void)NewBR; 8855 Dest = FalseBB; 8856 8857 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8858 Cond.getOperand(0), Cond.getOperand(1)); 8859 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8860 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8861 Chain, Dest, CC, Cmp); 8862 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8863 Cond = Cmp; 8864 addTest = false; 8865 } 8866 } 8867 } else if (Cond.getOpcode() == ISD::SETCC && 8868 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8869 // For FCMP_UNE, we can emit 8870 // two branches instead of an explicit AND instruction with a 8871 // separate test. However, we only do this if this block doesn't 8872 // have a fall-through edge, because this requires an explicit 8873 // jmp when the condition is false. 8874 if (Op.getNode()->hasOneUse()) { 8875 SDNode *User = *Op.getNode()->use_begin(); 8876 // Look for an unconditional branch following this conditional branch. 8877 // We need this because we need to reverse the successors in order 8878 // to implement FCMP_UNE. 8879 if (User->getOpcode() == ISD::BR) { 8880 SDValue FalseBB = User->getOperand(1); 8881 SDNode *NewBR = 8882 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8883 assert(NewBR == User); 8884 (void)NewBR; 8885 8886 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8887 Cond.getOperand(0), Cond.getOperand(1)); 8888 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8889 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8890 Chain, Dest, CC, Cmp); 8891 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8892 Cond = Cmp; 8893 addTest = false; 8894 Dest = FalseBB; 8895 } 8896 } 8897 } 8898 } 8899 8900 if (addTest) { 8901 // Look pass the truncate. 8902 if (Cond.getOpcode() == ISD::TRUNCATE) 8903 Cond = Cond.getOperand(0); 8904 8905 // We know the result of AND is compared against zero. Try to match 8906 // it to BT. 8907 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8908 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8909 if (NewSetCC.getNode()) { 8910 CC = NewSetCC.getOperand(0); 8911 Cond = NewSetCC.getOperand(1); 8912 addTest = false; 8913 } 8914 } 8915 } 8916 8917 if (addTest) { 8918 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8919 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8920 } 8921 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8922 Chain, Dest, CC, Cond); 8923} 8924 8925 8926// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8927// Calls to _alloca is needed to probe the stack when allocating more than 4k 8928// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8929// that the guard pages used by the OS virtual memory manager are allocated in 8930// correct sequence. 8931SDValue 8932X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8933 SelectionDAG &DAG) const { 8934 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8935 getTargetMachine().Options.EnableSegmentedStacks) && 8936 "This should be used only on Windows targets or when segmented stacks " 8937 "are being used"); 8938 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8939 DebugLoc dl = Op.getDebugLoc(); 8940 8941 // Get the inputs. 8942 SDValue Chain = Op.getOperand(0); 8943 SDValue Size = Op.getOperand(1); 8944 // FIXME: Ensure alignment here 8945 8946 bool Is64Bit = Subtarget->is64Bit(); 8947 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8948 8949 if (getTargetMachine().Options.EnableSegmentedStacks) { 8950 MachineFunction &MF = DAG.getMachineFunction(); 8951 MachineRegisterInfo &MRI = MF.getRegInfo(); 8952 8953 if (Is64Bit) { 8954 // The 64 bit implementation of segmented stacks needs to clobber both r10 8955 // r11. This makes it impossible to use it along with nested parameters. 8956 const Function *F = MF.getFunction(); 8957 8958 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8959 I != E; I++) 8960 if (I->hasNestAttr()) 8961 report_fatal_error("Cannot use segmented stacks with functions that " 8962 "have nested arguments."); 8963 } 8964 8965 const TargetRegisterClass *AddrRegClass = 8966 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8967 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8968 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8969 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8970 DAG.getRegister(Vreg, SPTy)); 8971 SDValue Ops1[2] = { Value, Chain }; 8972 return DAG.getMergeValues(Ops1, 2, dl); 8973 } else { 8974 SDValue Flag; 8975 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8976 8977 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8978 Flag = Chain.getValue(1); 8979 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8980 8981 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8982 Flag = Chain.getValue(1); 8983 8984 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8985 8986 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8987 return DAG.getMergeValues(Ops1, 2, dl); 8988 } 8989} 8990 8991SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8992 MachineFunction &MF = DAG.getMachineFunction(); 8993 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8994 8995 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8996 DebugLoc DL = Op.getDebugLoc(); 8997 8998 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8999 // vastart just stores the address of the VarArgsFrameIndex slot into the 9000 // memory location argument. 9001 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9002 getPointerTy()); 9003 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9004 MachinePointerInfo(SV), false, false, 0); 9005 } 9006 9007 // __va_list_tag: 9008 // gp_offset (0 - 6 * 8) 9009 // fp_offset (48 - 48 + 8 * 16) 9010 // overflow_arg_area (point to parameters coming in memory). 9011 // reg_save_area 9012 SmallVector<SDValue, 8> MemOps; 9013 SDValue FIN = Op.getOperand(1); 9014 // Store gp_offset 9015 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9016 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9017 MVT::i32), 9018 FIN, MachinePointerInfo(SV), false, false, 0); 9019 MemOps.push_back(Store); 9020 9021 // Store fp_offset 9022 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9023 FIN, DAG.getIntPtrConstant(4)); 9024 Store = DAG.getStore(Op.getOperand(0), DL, 9025 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9026 MVT::i32), 9027 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9028 MemOps.push_back(Store); 9029 9030 // Store ptr to overflow_arg_area 9031 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9032 FIN, DAG.getIntPtrConstant(4)); 9033 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9034 getPointerTy()); 9035 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9036 MachinePointerInfo(SV, 8), 9037 false, false, 0); 9038 MemOps.push_back(Store); 9039 9040 // Store ptr to reg_save_area. 9041 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9042 FIN, DAG.getIntPtrConstant(8)); 9043 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9044 getPointerTy()); 9045 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9046 MachinePointerInfo(SV, 16), false, false, 0); 9047 MemOps.push_back(Store); 9048 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9049 &MemOps[0], MemOps.size()); 9050} 9051 9052SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9053 assert(Subtarget->is64Bit() && 9054 "LowerVAARG only handles 64-bit va_arg!"); 9055 assert((Subtarget->isTargetLinux() || 9056 Subtarget->isTargetDarwin()) && 9057 "Unhandled target in LowerVAARG"); 9058 assert(Op.getNode()->getNumOperands() == 4); 9059 SDValue Chain = Op.getOperand(0); 9060 SDValue SrcPtr = Op.getOperand(1); 9061 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9062 unsigned Align = Op.getConstantOperandVal(3); 9063 DebugLoc dl = Op.getDebugLoc(); 9064 9065 EVT ArgVT = Op.getNode()->getValueType(0); 9066 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9067 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9068 uint8_t ArgMode; 9069 9070 // Decide which area this value should be read from. 9071 // TODO: Implement the AMD64 ABI in its entirety. This simple 9072 // selection mechanism works only for the basic types. 9073 if (ArgVT == MVT::f80) { 9074 llvm_unreachable("va_arg for f80 not yet implemented"); 9075 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9076 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9077 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9078 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9079 } else { 9080 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9081 } 9082 9083 if (ArgMode == 2) { 9084 // Sanity Check: Make sure using fp_offset makes sense. 9085 assert(!getTargetMachine().Options.UseSoftFloat && 9086 !(DAG.getMachineFunction() 9087 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9088 Subtarget->hasSSE1()); 9089 } 9090 9091 // Insert VAARG_64 node into the DAG 9092 // VAARG_64 returns two values: Variable Argument Address, Chain 9093 SmallVector<SDValue, 11> InstOps; 9094 InstOps.push_back(Chain); 9095 InstOps.push_back(SrcPtr); 9096 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9097 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9098 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9099 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9100 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9101 VTs, &InstOps[0], InstOps.size(), 9102 MVT::i64, 9103 MachinePointerInfo(SV), 9104 /*Align=*/0, 9105 /*Volatile=*/false, 9106 /*ReadMem=*/true, 9107 /*WriteMem=*/true); 9108 Chain = VAARG.getValue(1); 9109 9110 // Load the next argument and return it 9111 return DAG.getLoad(ArgVT, dl, 9112 Chain, 9113 VAARG, 9114 MachinePointerInfo(), 9115 false, false, false, 0); 9116} 9117 9118SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9119 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9120 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9121 SDValue Chain = Op.getOperand(0); 9122 SDValue DstPtr = Op.getOperand(1); 9123 SDValue SrcPtr = Op.getOperand(2); 9124 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9125 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9126 DebugLoc DL = Op.getDebugLoc(); 9127 9128 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9129 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9130 false, 9131 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9132} 9133 9134// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9135// may or may not be a constant. Takes immediate version of shift as input. 9136static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9137 SDValue SrcOp, SDValue ShAmt, 9138 SelectionDAG &DAG) { 9139 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9140 9141 if (isa<ConstantSDNode>(ShAmt)) { 9142 switch (Opc) { 9143 default: llvm_unreachable("Unknown target vector shift node"); 9144 case X86ISD::VSHLI: 9145 case X86ISD::VSRLI: 9146 case X86ISD::VSRAI: 9147 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9148 } 9149 } 9150 9151 // Change opcode to non-immediate version 9152 switch (Opc) { 9153 default: llvm_unreachable("Unknown target vector shift node"); 9154 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9155 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9156 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9157 } 9158 9159 // Need to build a vector containing shift amount 9160 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9161 SDValue ShOps[4]; 9162 ShOps[0] = ShAmt; 9163 ShOps[1] = DAG.getConstant(0, MVT::i32); 9164 ShOps[2] = DAG.getUNDEF(MVT::i32); 9165 ShOps[3] = DAG.getUNDEF(MVT::i32); 9166 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9167 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9168 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9169} 9170 9171SDValue 9172X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9173 DebugLoc dl = Op.getDebugLoc(); 9174 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9175 switch (IntNo) { 9176 default: return SDValue(); // Don't custom lower most intrinsics. 9177 // Comparison intrinsics. 9178 case Intrinsic::x86_sse_comieq_ss: 9179 case Intrinsic::x86_sse_comilt_ss: 9180 case Intrinsic::x86_sse_comile_ss: 9181 case Intrinsic::x86_sse_comigt_ss: 9182 case Intrinsic::x86_sse_comige_ss: 9183 case Intrinsic::x86_sse_comineq_ss: 9184 case Intrinsic::x86_sse_ucomieq_ss: 9185 case Intrinsic::x86_sse_ucomilt_ss: 9186 case Intrinsic::x86_sse_ucomile_ss: 9187 case Intrinsic::x86_sse_ucomigt_ss: 9188 case Intrinsic::x86_sse_ucomige_ss: 9189 case Intrinsic::x86_sse_ucomineq_ss: 9190 case Intrinsic::x86_sse2_comieq_sd: 9191 case Intrinsic::x86_sse2_comilt_sd: 9192 case Intrinsic::x86_sse2_comile_sd: 9193 case Intrinsic::x86_sse2_comigt_sd: 9194 case Intrinsic::x86_sse2_comige_sd: 9195 case Intrinsic::x86_sse2_comineq_sd: 9196 case Intrinsic::x86_sse2_ucomieq_sd: 9197 case Intrinsic::x86_sse2_ucomilt_sd: 9198 case Intrinsic::x86_sse2_ucomile_sd: 9199 case Intrinsic::x86_sse2_ucomigt_sd: 9200 case Intrinsic::x86_sse2_ucomige_sd: 9201 case Intrinsic::x86_sse2_ucomineq_sd: { 9202 unsigned Opc = 0; 9203 ISD::CondCode CC = ISD::SETCC_INVALID; 9204 switch (IntNo) { 9205 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9206 case Intrinsic::x86_sse_comieq_ss: 9207 case Intrinsic::x86_sse2_comieq_sd: 9208 Opc = X86ISD::COMI; 9209 CC = ISD::SETEQ; 9210 break; 9211 case Intrinsic::x86_sse_comilt_ss: 9212 case Intrinsic::x86_sse2_comilt_sd: 9213 Opc = X86ISD::COMI; 9214 CC = ISD::SETLT; 9215 break; 9216 case Intrinsic::x86_sse_comile_ss: 9217 case Intrinsic::x86_sse2_comile_sd: 9218 Opc = X86ISD::COMI; 9219 CC = ISD::SETLE; 9220 break; 9221 case Intrinsic::x86_sse_comigt_ss: 9222 case Intrinsic::x86_sse2_comigt_sd: 9223 Opc = X86ISD::COMI; 9224 CC = ISD::SETGT; 9225 break; 9226 case Intrinsic::x86_sse_comige_ss: 9227 case Intrinsic::x86_sse2_comige_sd: 9228 Opc = X86ISD::COMI; 9229 CC = ISD::SETGE; 9230 break; 9231 case Intrinsic::x86_sse_comineq_ss: 9232 case Intrinsic::x86_sse2_comineq_sd: 9233 Opc = X86ISD::COMI; 9234 CC = ISD::SETNE; 9235 break; 9236 case Intrinsic::x86_sse_ucomieq_ss: 9237 case Intrinsic::x86_sse2_ucomieq_sd: 9238 Opc = X86ISD::UCOMI; 9239 CC = ISD::SETEQ; 9240 break; 9241 case Intrinsic::x86_sse_ucomilt_ss: 9242 case Intrinsic::x86_sse2_ucomilt_sd: 9243 Opc = X86ISD::UCOMI; 9244 CC = ISD::SETLT; 9245 break; 9246 case Intrinsic::x86_sse_ucomile_ss: 9247 case Intrinsic::x86_sse2_ucomile_sd: 9248 Opc = X86ISD::UCOMI; 9249 CC = ISD::SETLE; 9250 break; 9251 case Intrinsic::x86_sse_ucomigt_ss: 9252 case Intrinsic::x86_sse2_ucomigt_sd: 9253 Opc = X86ISD::UCOMI; 9254 CC = ISD::SETGT; 9255 break; 9256 case Intrinsic::x86_sse_ucomige_ss: 9257 case Intrinsic::x86_sse2_ucomige_sd: 9258 Opc = X86ISD::UCOMI; 9259 CC = ISD::SETGE; 9260 break; 9261 case Intrinsic::x86_sse_ucomineq_ss: 9262 case Intrinsic::x86_sse2_ucomineq_sd: 9263 Opc = X86ISD::UCOMI; 9264 CC = ISD::SETNE; 9265 break; 9266 } 9267 9268 SDValue LHS = Op.getOperand(1); 9269 SDValue RHS = Op.getOperand(2); 9270 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9271 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9272 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9273 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9274 DAG.getConstant(X86CC, MVT::i8), Cond); 9275 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9276 } 9277 // XOP comparison intrinsics 9278 case Intrinsic::x86_xop_vpcomltb: 9279 case Intrinsic::x86_xop_vpcomltw: 9280 case Intrinsic::x86_xop_vpcomltd: 9281 case Intrinsic::x86_xop_vpcomltq: 9282 case Intrinsic::x86_xop_vpcomltub: 9283 case Intrinsic::x86_xop_vpcomltuw: 9284 case Intrinsic::x86_xop_vpcomltud: 9285 case Intrinsic::x86_xop_vpcomltuq: 9286 case Intrinsic::x86_xop_vpcomleb: 9287 case Intrinsic::x86_xop_vpcomlew: 9288 case Intrinsic::x86_xop_vpcomled: 9289 case Intrinsic::x86_xop_vpcomleq: 9290 case Intrinsic::x86_xop_vpcomleub: 9291 case Intrinsic::x86_xop_vpcomleuw: 9292 case Intrinsic::x86_xop_vpcomleud: 9293 case Intrinsic::x86_xop_vpcomleuq: 9294 case Intrinsic::x86_xop_vpcomgtb: 9295 case Intrinsic::x86_xop_vpcomgtw: 9296 case Intrinsic::x86_xop_vpcomgtd: 9297 case Intrinsic::x86_xop_vpcomgtq: 9298 case Intrinsic::x86_xop_vpcomgtub: 9299 case Intrinsic::x86_xop_vpcomgtuw: 9300 case Intrinsic::x86_xop_vpcomgtud: 9301 case Intrinsic::x86_xop_vpcomgtuq: 9302 case Intrinsic::x86_xop_vpcomgeb: 9303 case Intrinsic::x86_xop_vpcomgew: 9304 case Intrinsic::x86_xop_vpcomged: 9305 case Intrinsic::x86_xop_vpcomgeq: 9306 case Intrinsic::x86_xop_vpcomgeub: 9307 case Intrinsic::x86_xop_vpcomgeuw: 9308 case Intrinsic::x86_xop_vpcomgeud: 9309 case Intrinsic::x86_xop_vpcomgeuq: 9310 case Intrinsic::x86_xop_vpcomeqb: 9311 case Intrinsic::x86_xop_vpcomeqw: 9312 case Intrinsic::x86_xop_vpcomeqd: 9313 case Intrinsic::x86_xop_vpcomeqq: 9314 case Intrinsic::x86_xop_vpcomequb: 9315 case Intrinsic::x86_xop_vpcomequw: 9316 case Intrinsic::x86_xop_vpcomequd: 9317 case Intrinsic::x86_xop_vpcomequq: 9318 case Intrinsic::x86_xop_vpcomneb: 9319 case Intrinsic::x86_xop_vpcomnew: 9320 case Intrinsic::x86_xop_vpcomned: 9321 case Intrinsic::x86_xop_vpcomneq: 9322 case Intrinsic::x86_xop_vpcomneub: 9323 case Intrinsic::x86_xop_vpcomneuw: 9324 case Intrinsic::x86_xop_vpcomneud: 9325 case Intrinsic::x86_xop_vpcomneuq: 9326 case Intrinsic::x86_xop_vpcomfalseb: 9327 case Intrinsic::x86_xop_vpcomfalsew: 9328 case Intrinsic::x86_xop_vpcomfalsed: 9329 case Intrinsic::x86_xop_vpcomfalseq: 9330 case Intrinsic::x86_xop_vpcomfalseub: 9331 case Intrinsic::x86_xop_vpcomfalseuw: 9332 case Intrinsic::x86_xop_vpcomfalseud: 9333 case Intrinsic::x86_xop_vpcomfalseuq: 9334 case Intrinsic::x86_xop_vpcomtrueb: 9335 case Intrinsic::x86_xop_vpcomtruew: 9336 case Intrinsic::x86_xop_vpcomtrued: 9337 case Intrinsic::x86_xop_vpcomtrueq: 9338 case Intrinsic::x86_xop_vpcomtrueub: 9339 case Intrinsic::x86_xop_vpcomtrueuw: 9340 case Intrinsic::x86_xop_vpcomtrueud: 9341 case Intrinsic::x86_xop_vpcomtrueuq: { 9342 unsigned CC = 0; 9343 unsigned Opc = 0; 9344 9345 switch (IntNo) { 9346 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9347 case Intrinsic::x86_xop_vpcomltb: 9348 case Intrinsic::x86_xop_vpcomltw: 9349 case Intrinsic::x86_xop_vpcomltd: 9350 case Intrinsic::x86_xop_vpcomltq: 9351 CC = 0; 9352 Opc = X86ISD::VPCOM; 9353 break; 9354 case Intrinsic::x86_xop_vpcomltub: 9355 case Intrinsic::x86_xop_vpcomltuw: 9356 case Intrinsic::x86_xop_vpcomltud: 9357 case Intrinsic::x86_xop_vpcomltuq: 9358 CC = 0; 9359 Opc = X86ISD::VPCOMU; 9360 break; 9361 case Intrinsic::x86_xop_vpcomleb: 9362 case Intrinsic::x86_xop_vpcomlew: 9363 case Intrinsic::x86_xop_vpcomled: 9364 case Intrinsic::x86_xop_vpcomleq: 9365 CC = 1; 9366 Opc = X86ISD::VPCOM; 9367 break; 9368 case Intrinsic::x86_xop_vpcomleub: 9369 case Intrinsic::x86_xop_vpcomleuw: 9370 case Intrinsic::x86_xop_vpcomleud: 9371 case Intrinsic::x86_xop_vpcomleuq: 9372 CC = 1; 9373 Opc = X86ISD::VPCOMU; 9374 break; 9375 case Intrinsic::x86_xop_vpcomgtb: 9376 case Intrinsic::x86_xop_vpcomgtw: 9377 case Intrinsic::x86_xop_vpcomgtd: 9378 case Intrinsic::x86_xop_vpcomgtq: 9379 CC = 2; 9380 Opc = X86ISD::VPCOM; 9381 break; 9382 case Intrinsic::x86_xop_vpcomgtub: 9383 case Intrinsic::x86_xop_vpcomgtuw: 9384 case Intrinsic::x86_xop_vpcomgtud: 9385 case Intrinsic::x86_xop_vpcomgtuq: 9386 CC = 2; 9387 Opc = X86ISD::VPCOMU; 9388 break; 9389 case Intrinsic::x86_xop_vpcomgeb: 9390 case Intrinsic::x86_xop_vpcomgew: 9391 case Intrinsic::x86_xop_vpcomged: 9392 case Intrinsic::x86_xop_vpcomgeq: 9393 CC = 3; 9394 Opc = X86ISD::VPCOM; 9395 break; 9396 case Intrinsic::x86_xop_vpcomgeub: 9397 case Intrinsic::x86_xop_vpcomgeuw: 9398 case Intrinsic::x86_xop_vpcomgeud: 9399 case Intrinsic::x86_xop_vpcomgeuq: 9400 CC = 3; 9401 Opc = X86ISD::VPCOMU; 9402 break; 9403 case Intrinsic::x86_xop_vpcomeqb: 9404 case Intrinsic::x86_xop_vpcomeqw: 9405 case Intrinsic::x86_xop_vpcomeqd: 9406 case Intrinsic::x86_xop_vpcomeqq: 9407 CC = 4; 9408 Opc = X86ISD::VPCOM; 9409 break; 9410 case Intrinsic::x86_xop_vpcomequb: 9411 case Intrinsic::x86_xop_vpcomequw: 9412 case Intrinsic::x86_xop_vpcomequd: 9413 case Intrinsic::x86_xop_vpcomequq: 9414 CC = 4; 9415 Opc = X86ISD::VPCOMU; 9416 break; 9417 case Intrinsic::x86_xop_vpcomneb: 9418 case Intrinsic::x86_xop_vpcomnew: 9419 case Intrinsic::x86_xop_vpcomned: 9420 case Intrinsic::x86_xop_vpcomneq: 9421 CC = 5; 9422 Opc = X86ISD::VPCOM; 9423 break; 9424 case Intrinsic::x86_xop_vpcomneub: 9425 case Intrinsic::x86_xop_vpcomneuw: 9426 case Intrinsic::x86_xop_vpcomneud: 9427 case Intrinsic::x86_xop_vpcomneuq: 9428 CC = 5; 9429 Opc = X86ISD::VPCOMU; 9430 break; 9431 case Intrinsic::x86_xop_vpcomfalseb: 9432 case Intrinsic::x86_xop_vpcomfalsew: 9433 case Intrinsic::x86_xop_vpcomfalsed: 9434 case Intrinsic::x86_xop_vpcomfalseq: 9435 CC = 6; 9436 Opc = X86ISD::VPCOM; 9437 break; 9438 case Intrinsic::x86_xop_vpcomfalseub: 9439 case Intrinsic::x86_xop_vpcomfalseuw: 9440 case Intrinsic::x86_xop_vpcomfalseud: 9441 case Intrinsic::x86_xop_vpcomfalseuq: 9442 CC = 6; 9443 Opc = X86ISD::VPCOMU; 9444 break; 9445 case Intrinsic::x86_xop_vpcomtrueb: 9446 case Intrinsic::x86_xop_vpcomtruew: 9447 case Intrinsic::x86_xop_vpcomtrued: 9448 case Intrinsic::x86_xop_vpcomtrueq: 9449 CC = 7; 9450 Opc = X86ISD::VPCOM; 9451 break; 9452 case Intrinsic::x86_xop_vpcomtrueub: 9453 case Intrinsic::x86_xop_vpcomtrueuw: 9454 case Intrinsic::x86_xop_vpcomtrueud: 9455 case Intrinsic::x86_xop_vpcomtrueuq: 9456 CC = 7; 9457 Opc = X86ISD::VPCOMU; 9458 break; 9459 } 9460 9461 SDValue LHS = Op.getOperand(1); 9462 SDValue RHS = Op.getOperand(2); 9463 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9464 DAG.getConstant(CC, MVT::i8)); 9465 } 9466 9467 // Arithmetic intrinsics. 9468 case Intrinsic::x86_sse2_pmulu_dq: 9469 case Intrinsic::x86_avx2_pmulu_dq: 9470 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9471 Op.getOperand(1), Op.getOperand(2)); 9472 case Intrinsic::x86_sse3_hadd_ps: 9473 case Intrinsic::x86_sse3_hadd_pd: 9474 case Intrinsic::x86_avx_hadd_ps_256: 9475 case Intrinsic::x86_avx_hadd_pd_256: 9476 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9477 Op.getOperand(1), Op.getOperand(2)); 9478 case Intrinsic::x86_sse3_hsub_ps: 9479 case Intrinsic::x86_sse3_hsub_pd: 9480 case Intrinsic::x86_avx_hsub_ps_256: 9481 case Intrinsic::x86_avx_hsub_pd_256: 9482 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9483 Op.getOperand(1), Op.getOperand(2)); 9484 case Intrinsic::x86_ssse3_phadd_w_128: 9485 case Intrinsic::x86_ssse3_phadd_d_128: 9486 case Intrinsic::x86_avx2_phadd_w: 9487 case Intrinsic::x86_avx2_phadd_d: 9488 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9489 Op.getOperand(1), Op.getOperand(2)); 9490 case Intrinsic::x86_ssse3_phsub_w_128: 9491 case Intrinsic::x86_ssse3_phsub_d_128: 9492 case Intrinsic::x86_avx2_phsub_w: 9493 case Intrinsic::x86_avx2_phsub_d: 9494 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9495 Op.getOperand(1), Op.getOperand(2)); 9496 case Intrinsic::x86_avx2_psllv_d: 9497 case Intrinsic::x86_avx2_psllv_q: 9498 case Intrinsic::x86_avx2_psllv_d_256: 9499 case Intrinsic::x86_avx2_psllv_q_256: 9500 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9501 Op.getOperand(1), Op.getOperand(2)); 9502 case Intrinsic::x86_avx2_psrlv_d: 9503 case Intrinsic::x86_avx2_psrlv_q: 9504 case Intrinsic::x86_avx2_psrlv_d_256: 9505 case Intrinsic::x86_avx2_psrlv_q_256: 9506 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9507 Op.getOperand(1), Op.getOperand(2)); 9508 case Intrinsic::x86_avx2_psrav_d: 9509 case Intrinsic::x86_avx2_psrav_d_256: 9510 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9511 Op.getOperand(1), Op.getOperand(2)); 9512 case Intrinsic::x86_ssse3_pshuf_b_128: 9513 case Intrinsic::x86_avx2_pshuf_b: 9514 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9515 Op.getOperand(1), Op.getOperand(2)); 9516 case Intrinsic::x86_ssse3_psign_b_128: 9517 case Intrinsic::x86_ssse3_psign_w_128: 9518 case Intrinsic::x86_ssse3_psign_d_128: 9519 case Intrinsic::x86_avx2_psign_b: 9520 case Intrinsic::x86_avx2_psign_w: 9521 case Intrinsic::x86_avx2_psign_d: 9522 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9523 Op.getOperand(1), Op.getOperand(2)); 9524 case Intrinsic::x86_sse41_insertps: 9525 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9526 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9527 case Intrinsic::x86_avx_vperm2f128_ps_256: 9528 case Intrinsic::x86_avx_vperm2f128_pd_256: 9529 case Intrinsic::x86_avx_vperm2f128_si_256: 9530 case Intrinsic::x86_avx2_vperm2i128: 9531 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9532 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9533 case Intrinsic::x86_avx_vpermil_ps: 9534 case Intrinsic::x86_avx_vpermil_pd: 9535 case Intrinsic::x86_avx_vpermil_ps_256: 9536 case Intrinsic::x86_avx_vpermil_pd_256: 9537 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(), 9538 Op.getOperand(1), Op.getOperand(2)); 9539 9540 // ptest and testp intrinsics. The intrinsic these come from are designed to 9541 // return an integer value, not just an instruction so lower it to the ptest 9542 // or testp pattern and a setcc for the result. 9543 case Intrinsic::x86_sse41_ptestz: 9544 case Intrinsic::x86_sse41_ptestc: 9545 case Intrinsic::x86_sse41_ptestnzc: 9546 case Intrinsic::x86_avx_ptestz_256: 9547 case Intrinsic::x86_avx_ptestc_256: 9548 case Intrinsic::x86_avx_ptestnzc_256: 9549 case Intrinsic::x86_avx_vtestz_ps: 9550 case Intrinsic::x86_avx_vtestc_ps: 9551 case Intrinsic::x86_avx_vtestnzc_ps: 9552 case Intrinsic::x86_avx_vtestz_pd: 9553 case Intrinsic::x86_avx_vtestc_pd: 9554 case Intrinsic::x86_avx_vtestnzc_pd: 9555 case Intrinsic::x86_avx_vtestz_ps_256: 9556 case Intrinsic::x86_avx_vtestc_ps_256: 9557 case Intrinsic::x86_avx_vtestnzc_ps_256: 9558 case Intrinsic::x86_avx_vtestz_pd_256: 9559 case Intrinsic::x86_avx_vtestc_pd_256: 9560 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9561 bool IsTestPacked = false; 9562 unsigned X86CC = 0; 9563 switch (IntNo) { 9564 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9565 case Intrinsic::x86_avx_vtestz_ps: 9566 case Intrinsic::x86_avx_vtestz_pd: 9567 case Intrinsic::x86_avx_vtestz_ps_256: 9568 case Intrinsic::x86_avx_vtestz_pd_256: 9569 IsTestPacked = true; // Fallthrough 9570 case Intrinsic::x86_sse41_ptestz: 9571 case Intrinsic::x86_avx_ptestz_256: 9572 // ZF = 1 9573 X86CC = X86::COND_E; 9574 break; 9575 case Intrinsic::x86_avx_vtestc_ps: 9576 case Intrinsic::x86_avx_vtestc_pd: 9577 case Intrinsic::x86_avx_vtestc_ps_256: 9578 case Intrinsic::x86_avx_vtestc_pd_256: 9579 IsTestPacked = true; // Fallthrough 9580 case Intrinsic::x86_sse41_ptestc: 9581 case Intrinsic::x86_avx_ptestc_256: 9582 // CF = 1 9583 X86CC = X86::COND_B; 9584 break; 9585 case Intrinsic::x86_avx_vtestnzc_ps: 9586 case Intrinsic::x86_avx_vtestnzc_pd: 9587 case Intrinsic::x86_avx_vtestnzc_ps_256: 9588 case Intrinsic::x86_avx_vtestnzc_pd_256: 9589 IsTestPacked = true; // Fallthrough 9590 case Intrinsic::x86_sse41_ptestnzc: 9591 case Intrinsic::x86_avx_ptestnzc_256: 9592 // ZF and CF = 0 9593 X86CC = X86::COND_A; 9594 break; 9595 } 9596 9597 SDValue LHS = Op.getOperand(1); 9598 SDValue RHS = Op.getOperand(2); 9599 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9600 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9601 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9602 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9603 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9604 } 9605 9606 // SSE/AVX shift intrinsics 9607 case Intrinsic::x86_sse2_psll_w: 9608 case Intrinsic::x86_sse2_psll_d: 9609 case Intrinsic::x86_sse2_psll_q: 9610 case Intrinsic::x86_avx2_psll_w: 9611 case Intrinsic::x86_avx2_psll_d: 9612 case Intrinsic::x86_avx2_psll_q: 9613 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9614 Op.getOperand(1), Op.getOperand(2)); 9615 case Intrinsic::x86_sse2_psrl_w: 9616 case Intrinsic::x86_sse2_psrl_d: 9617 case Intrinsic::x86_sse2_psrl_q: 9618 case Intrinsic::x86_avx2_psrl_w: 9619 case Intrinsic::x86_avx2_psrl_d: 9620 case Intrinsic::x86_avx2_psrl_q: 9621 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9622 Op.getOperand(1), Op.getOperand(2)); 9623 case Intrinsic::x86_sse2_psra_w: 9624 case Intrinsic::x86_sse2_psra_d: 9625 case Intrinsic::x86_avx2_psra_w: 9626 case Intrinsic::x86_avx2_psra_d: 9627 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9628 Op.getOperand(1), Op.getOperand(2)); 9629 case Intrinsic::x86_sse2_pslli_w: 9630 case Intrinsic::x86_sse2_pslli_d: 9631 case Intrinsic::x86_sse2_pslli_q: 9632 case Intrinsic::x86_avx2_pslli_w: 9633 case Intrinsic::x86_avx2_pslli_d: 9634 case Intrinsic::x86_avx2_pslli_q: 9635 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9636 Op.getOperand(1), Op.getOperand(2), DAG); 9637 case Intrinsic::x86_sse2_psrli_w: 9638 case Intrinsic::x86_sse2_psrli_d: 9639 case Intrinsic::x86_sse2_psrli_q: 9640 case Intrinsic::x86_avx2_psrli_w: 9641 case Intrinsic::x86_avx2_psrli_d: 9642 case Intrinsic::x86_avx2_psrli_q: 9643 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9644 Op.getOperand(1), Op.getOperand(2), DAG); 9645 case Intrinsic::x86_sse2_psrai_w: 9646 case Intrinsic::x86_sse2_psrai_d: 9647 case Intrinsic::x86_avx2_psrai_w: 9648 case Intrinsic::x86_avx2_psrai_d: 9649 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9650 Op.getOperand(1), Op.getOperand(2), DAG); 9651 // Fix vector shift instructions where the last operand is a non-immediate 9652 // i32 value. 9653 case Intrinsic::x86_mmx_pslli_w: 9654 case Intrinsic::x86_mmx_pslli_d: 9655 case Intrinsic::x86_mmx_pslli_q: 9656 case Intrinsic::x86_mmx_psrli_w: 9657 case Intrinsic::x86_mmx_psrli_d: 9658 case Intrinsic::x86_mmx_psrli_q: 9659 case Intrinsic::x86_mmx_psrai_w: 9660 case Intrinsic::x86_mmx_psrai_d: { 9661 SDValue ShAmt = Op.getOperand(2); 9662 if (isa<ConstantSDNode>(ShAmt)) 9663 return SDValue(); 9664 9665 unsigned NewIntNo = 0; 9666 switch (IntNo) { 9667 case Intrinsic::x86_mmx_pslli_w: 9668 NewIntNo = Intrinsic::x86_mmx_psll_w; 9669 break; 9670 case Intrinsic::x86_mmx_pslli_d: 9671 NewIntNo = Intrinsic::x86_mmx_psll_d; 9672 break; 9673 case Intrinsic::x86_mmx_pslli_q: 9674 NewIntNo = Intrinsic::x86_mmx_psll_q; 9675 break; 9676 case Intrinsic::x86_mmx_psrli_w: 9677 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9678 break; 9679 case Intrinsic::x86_mmx_psrli_d: 9680 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9681 break; 9682 case Intrinsic::x86_mmx_psrli_q: 9683 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9684 break; 9685 case Intrinsic::x86_mmx_psrai_w: 9686 NewIntNo = Intrinsic::x86_mmx_psra_w; 9687 break; 9688 case Intrinsic::x86_mmx_psrai_d: 9689 NewIntNo = Intrinsic::x86_mmx_psra_d; 9690 break; 9691 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9692 } 9693 9694 // The vector shift intrinsics with scalars uses 32b shift amounts but 9695 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9696 // to be zero. 9697 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9698 DAG.getConstant(0, MVT::i32)); 9699// FIXME this must be lowered to get rid of the invalid type. 9700 9701 EVT VT = Op.getValueType(); 9702 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9703 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9704 DAG.getConstant(NewIntNo, MVT::i32), 9705 Op.getOperand(1), ShAmt); 9706 } 9707 } 9708} 9709 9710SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9711 SelectionDAG &DAG) const { 9712 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9713 MFI->setReturnAddressIsTaken(true); 9714 9715 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9716 DebugLoc dl = Op.getDebugLoc(); 9717 9718 if (Depth > 0) { 9719 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9720 SDValue Offset = 9721 DAG.getConstant(TD->getPointerSize(), 9722 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9723 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9724 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9725 FrameAddr, Offset), 9726 MachinePointerInfo(), false, false, false, 0); 9727 } 9728 9729 // Just load the return address. 9730 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9731 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9732 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9733} 9734 9735SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9736 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9737 MFI->setFrameAddressIsTaken(true); 9738 9739 EVT VT = Op.getValueType(); 9740 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9741 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9742 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9743 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9744 while (Depth--) 9745 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9746 MachinePointerInfo(), 9747 false, false, false, 0); 9748 return FrameAddr; 9749} 9750 9751SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9752 SelectionDAG &DAG) const { 9753 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9754} 9755 9756SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9757 MachineFunction &MF = DAG.getMachineFunction(); 9758 SDValue Chain = Op.getOperand(0); 9759 SDValue Offset = Op.getOperand(1); 9760 SDValue Handler = Op.getOperand(2); 9761 DebugLoc dl = Op.getDebugLoc(); 9762 9763 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9764 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9765 getPointerTy()); 9766 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9767 9768 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9769 DAG.getIntPtrConstant(TD->getPointerSize())); 9770 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9771 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9772 false, false, 0); 9773 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9774 MF.getRegInfo().addLiveOut(StoreAddrReg); 9775 9776 return DAG.getNode(X86ISD::EH_RETURN, dl, 9777 MVT::Other, 9778 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9779} 9780 9781SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9782 SelectionDAG &DAG) const { 9783 return Op.getOperand(0); 9784} 9785 9786SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9787 SelectionDAG &DAG) const { 9788 SDValue Root = Op.getOperand(0); 9789 SDValue Trmp = Op.getOperand(1); // trampoline 9790 SDValue FPtr = Op.getOperand(2); // nested function 9791 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9792 DebugLoc dl = Op.getDebugLoc(); 9793 9794 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9795 9796 if (Subtarget->is64Bit()) { 9797 SDValue OutChains[6]; 9798 9799 // Large code-model. 9800 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9801 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9802 9803 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9804 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9805 9806 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9807 9808 // Load the pointer to the nested function into R11. 9809 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9810 SDValue Addr = Trmp; 9811 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9812 Addr, MachinePointerInfo(TrmpAddr), 9813 false, false, 0); 9814 9815 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9816 DAG.getConstant(2, MVT::i64)); 9817 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9818 MachinePointerInfo(TrmpAddr, 2), 9819 false, false, 2); 9820 9821 // Load the 'nest' parameter value into R10. 9822 // R10 is specified in X86CallingConv.td 9823 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9824 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9825 DAG.getConstant(10, MVT::i64)); 9826 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9827 Addr, MachinePointerInfo(TrmpAddr, 10), 9828 false, false, 0); 9829 9830 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9831 DAG.getConstant(12, MVT::i64)); 9832 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9833 MachinePointerInfo(TrmpAddr, 12), 9834 false, false, 2); 9835 9836 // Jump to the nested function. 9837 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9838 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9839 DAG.getConstant(20, MVT::i64)); 9840 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9841 Addr, MachinePointerInfo(TrmpAddr, 20), 9842 false, false, 0); 9843 9844 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9845 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9846 DAG.getConstant(22, MVT::i64)); 9847 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9848 MachinePointerInfo(TrmpAddr, 22), 9849 false, false, 0); 9850 9851 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9852 } else { 9853 const Function *Func = 9854 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9855 CallingConv::ID CC = Func->getCallingConv(); 9856 unsigned NestReg; 9857 9858 switch (CC) { 9859 default: 9860 llvm_unreachable("Unsupported calling convention"); 9861 case CallingConv::C: 9862 case CallingConv::X86_StdCall: { 9863 // Pass 'nest' parameter in ECX. 9864 // Must be kept in sync with X86CallingConv.td 9865 NestReg = X86::ECX; 9866 9867 // Check that ECX wasn't needed by an 'inreg' parameter. 9868 FunctionType *FTy = Func->getFunctionType(); 9869 const AttrListPtr &Attrs = Func->getAttributes(); 9870 9871 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9872 unsigned InRegCount = 0; 9873 unsigned Idx = 1; 9874 9875 for (FunctionType::param_iterator I = FTy->param_begin(), 9876 E = FTy->param_end(); I != E; ++I, ++Idx) 9877 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9878 // FIXME: should only count parameters that are lowered to integers. 9879 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9880 9881 if (InRegCount > 2) { 9882 report_fatal_error("Nest register in use - reduce number of inreg" 9883 " parameters!"); 9884 } 9885 } 9886 break; 9887 } 9888 case CallingConv::X86_FastCall: 9889 case CallingConv::X86_ThisCall: 9890 case CallingConv::Fast: 9891 // Pass 'nest' parameter in EAX. 9892 // Must be kept in sync with X86CallingConv.td 9893 NestReg = X86::EAX; 9894 break; 9895 } 9896 9897 SDValue OutChains[4]; 9898 SDValue Addr, Disp; 9899 9900 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9901 DAG.getConstant(10, MVT::i32)); 9902 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9903 9904 // This is storing the opcode for MOV32ri. 9905 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9906 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9907 OutChains[0] = DAG.getStore(Root, dl, 9908 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9909 Trmp, MachinePointerInfo(TrmpAddr), 9910 false, false, 0); 9911 9912 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9913 DAG.getConstant(1, MVT::i32)); 9914 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9915 MachinePointerInfo(TrmpAddr, 1), 9916 false, false, 1); 9917 9918 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9919 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9920 DAG.getConstant(5, MVT::i32)); 9921 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9922 MachinePointerInfo(TrmpAddr, 5), 9923 false, false, 1); 9924 9925 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9926 DAG.getConstant(6, MVT::i32)); 9927 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9928 MachinePointerInfo(TrmpAddr, 6), 9929 false, false, 1); 9930 9931 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9932 } 9933} 9934 9935SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9936 SelectionDAG &DAG) const { 9937 /* 9938 The rounding mode is in bits 11:10 of FPSR, and has the following 9939 settings: 9940 00 Round to nearest 9941 01 Round to -inf 9942 10 Round to +inf 9943 11 Round to 0 9944 9945 FLT_ROUNDS, on the other hand, expects the following: 9946 -1 Undefined 9947 0 Round to 0 9948 1 Round to nearest 9949 2 Round to +inf 9950 3 Round to -inf 9951 9952 To perform the conversion, we do: 9953 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9954 */ 9955 9956 MachineFunction &MF = DAG.getMachineFunction(); 9957 const TargetMachine &TM = MF.getTarget(); 9958 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9959 unsigned StackAlignment = TFI.getStackAlignment(); 9960 EVT VT = Op.getValueType(); 9961 DebugLoc DL = Op.getDebugLoc(); 9962 9963 // Save FP Control Word to stack slot 9964 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9965 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9966 9967 9968 MachineMemOperand *MMO = 9969 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9970 MachineMemOperand::MOStore, 2, 2); 9971 9972 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9973 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9974 DAG.getVTList(MVT::Other), 9975 Ops, 2, MVT::i16, MMO); 9976 9977 // Load FP Control Word from stack slot 9978 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9979 MachinePointerInfo(), false, false, false, 0); 9980 9981 // Transform as necessary 9982 SDValue CWD1 = 9983 DAG.getNode(ISD::SRL, DL, MVT::i16, 9984 DAG.getNode(ISD::AND, DL, MVT::i16, 9985 CWD, DAG.getConstant(0x800, MVT::i16)), 9986 DAG.getConstant(11, MVT::i8)); 9987 SDValue CWD2 = 9988 DAG.getNode(ISD::SRL, DL, MVT::i16, 9989 DAG.getNode(ISD::AND, DL, MVT::i16, 9990 CWD, DAG.getConstant(0x400, MVT::i16)), 9991 DAG.getConstant(9, MVT::i8)); 9992 9993 SDValue RetVal = 9994 DAG.getNode(ISD::AND, DL, MVT::i16, 9995 DAG.getNode(ISD::ADD, DL, MVT::i16, 9996 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9997 DAG.getConstant(1, MVT::i16)), 9998 DAG.getConstant(3, MVT::i16)); 9999 10000 10001 return DAG.getNode((VT.getSizeInBits() < 16 ? 10002 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10003} 10004 10005SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 10006 EVT VT = Op.getValueType(); 10007 EVT OpVT = VT; 10008 unsigned NumBits = VT.getSizeInBits(); 10009 DebugLoc dl = Op.getDebugLoc(); 10010 10011 Op = Op.getOperand(0); 10012 if (VT == MVT::i8) { 10013 // Zero extend to i32 since there is not an i8 bsr. 10014 OpVT = MVT::i32; 10015 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10016 } 10017 10018 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10019 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10020 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10021 10022 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10023 SDValue Ops[] = { 10024 Op, 10025 DAG.getConstant(NumBits+NumBits-1, OpVT), 10026 DAG.getConstant(X86::COND_E, MVT::i8), 10027 Op.getValue(1) 10028 }; 10029 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10030 10031 // Finally xor with NumBits-1. 10032 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10033 10034 if (VT == MVT::i8) 10035 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10036 return Op; 10037} 10038 10039SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 10040 SelectionDAG &DAG) const { 10041 EVT VT = Op.getValueType(); 10042 EVT OpVT = VT; 10043 unsigned NumBits = VT.getSizeInBits(); 10044 DebugLoc dl = Op.getDebugLoc(); 10045 10046 Op = Op.getOperand(0); 10047 if (VT == MVT::i8) { 10048 // Zero extend to i32 since there is not an i8 bsr. 10049 OpVT = MVT::i32; 10050 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10051 } 10052 10053 // Issue a bsr (scan bits in reverse). 10054 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10055 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10056 10057 // And xor with NumBits-1. 10058 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10059 10060 if (VT == MVT::i8) 10061 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10062 return Op; 10063} 10064 10065SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10066 EVT VT = Op.getValueType(); 10067 unsigned NumBits = VT.getSizeInBits(); 10068 DebugLoc dl = Op.getDebugLoc(); 10069 Op = Op.getOperand(0); 10070 10071 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10072 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10073 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10074 10075 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10076 SDValue Ops[] = { 10077 Op, 10078 DAG.getConstant(NumBits, VT), 10079 DAG.getConstant(X86::COND_E, MVT::i8), 10080 Op.getValue(1) 10081 }; 10082 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10083} 10084 10085// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10086// ones, and then concatenate the result back. 10087static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10088 EVT VT = Op.getValueType(); 10089 10090 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10091 "Unsupported value type for operation"); 10092 10093 int NumElems = VT.getVectorNumElements(); 10094 DebugLoc dl = Op.getDebugLoc(); 10095 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10096 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10097 10098 // Extract the LHS vectors 10099 SDValue LHS = Op.getOperand(0); 10100 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10101 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10102 10103 // Extract the RHS vectors 10104 SDValue RHS = Op.getOperand(1); 10105 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 10106 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 10107 10108 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10109 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10110 10111 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10112 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10113 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10114} 10115 10116SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10117 assert(Op.getValueType().getSizeInBits() == 256 && 10118 Op.getValueType().isInteger() && 10119 "Only handle AVX 256-bit vector integer operation"); 10120 return Lower256IntArith(Op, DAG); 10121} 10122 10123SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10124 assert(Op.getValueType().getSizeInBits() == 256 && 10125 Op.getValueType().isInteger() && 10126 "Only handle AVX 256-bit vector integer operation"); 10127 return Lower256IntArith(Op, DAG); 10128} 10129 10130SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10131 EVT VT = Op.getValueType(); 10132 10133 // Decompose 256-bit ops into smaller 128-bit ops. 10134 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10135 return Lower256IntArith(Op, DAG); 10136 10137 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10138 "Only know how to lower V2I64/V4I64 multiply"); 10139 10140 DebugLoc dl = Op.getDebugLoc(); 10141 10142 // Ahi = psrlqi(a, 32); 10143 // Bhi = psrlqi(b, 32); 10144 // 10145 // AloBlo = pmuludq(a, b); 10146 // AloBhi = pmuludq(a, Bhi); 10147 // AhiBlo = pmuludq(Ahi, b); 10148 10149 // AloBhi = psllqi(AloBhi, 32); 10150 // AhiBlo = psllqi(AhiBlo, 32); 10151 // return AloBlo + AloBhi + AhiBlo; 10152 10153 SDValue A = Op.getOperand(0); 10154 SDValue B = Op.getOperand(1); 10155 10156 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10157 10158 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10159 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10160 10161 // Bit cast to 32-bit vectors for MULUDQ 10162 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10163 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10164 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10165 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10166 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10167 10168 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10169 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10170 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10171 10172 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10173 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10174 10175 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10176 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10177} 10178 10179SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10180 10181 EVT VT = Op.getValueType(); 10182 DebugLoc dl = Op.getDebugLoc(); 10183 SDValue R = Op.getOperand(0); 10184 SDValue Amt = Op.getOperand(1); 10185 LLVMContext *Context = DAG.getContext(); 10186 10187 if (!Subtarget->hasSSE2()) 10188 return SDValue(); 10189 10190 // Optimize shl/srl/sra with constant shift amount. 10191 if (isSplatVector(Amt.getNode())) { 10192 SDValue SclrAmt = Amt->getOperand(0); 10193 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10194 uint64_t ShiftAmt = C->getZExtValue(); 10195 10196 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10197 (Subtarget->hasAVX2() && 10198 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10199 if (Op.getOpcode() == ISD::SHL) 10200 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10201 DAG.getConstant(ShiftAmt, MVT::i32)); 10202 if (Op.getOpcode() == ISD::SRL) 10203 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10204 DAG.getConstant(ShiftAmt, MVT::i32)); 10205 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10206 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10207 DAG.getConstant(ShiftAmt, MVT::i32)); 10208 } 10209 10210 if (VT == MVT::v16i8) { 10211 if (Op.getOpcode() == ISD::SHL) { 10212 // Make a large shift. 10213 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10214 DAG.getConstant(ShiftAmt, MVT::i32)); 10215 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10216 // Zero out the rightmost bits. 10217 SmallVector<SDValue, 16> V(16, 10218 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10219 MVT::i8)); 10220 return DAG.getNode(ISD::AND, dl, VT, SHL, 10221 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10222 } 10223 if (Op.getOpcode() == ISD::SRL) { 10224 // Make a large shift. 10225 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10226 DAG.getConstant(ShiftAmt, MVT::i32)); 10227 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10228 // Zero out the leftmost bits. 10229 SmallVector<SDValue, 16> V(16, 10230 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10231 MVT::i8)); 10232 return DAG.getNode(ISD::AND, dl, VT, SRL, 10233 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10234 } 10235 if (Op.getOpcode() == ISD::SRA) { 10236 if (ShiftAmt == 7) { 10237 // R s>> 7 === R s< 0 10238 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10239 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10240 } 10241 10242 // R s>> a === ((R u>> a) ^ m) - m 10243 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10244 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10245 MVT::i8)); 10246 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10247 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10248 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10249 return Res; 10250 } 10251 } 10252 10253 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10254 if (Op.getOpcode() == ISD::SHL) { 10255 // Make a large shift. 10256 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10257 DAG.getConstant(ShiftAmt, MVT::i32)); 10258 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10259 // Zero out the rightmost bits. 10260 SmallVector<SDValue, 32> V(32, 10261 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10262 MVT::i8)); 10263 return DAG.getNode(ISD::AND, dl, VT, SHL, 10264 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10265 } 10266 if (Op.getOpcode() == ISD::SRL) { 10267 // Make a large shift. 10268 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10269 DAG.getConstant(ShiftAmt, MVT::i32)); 10270 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10271 // Zero out the leftmost bits. 10272 SmallVector<SDValue, 32> V(32, 10273 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10274 MVT::i8)); 10275 return DAG.getNode(ISD::AND, dl, VT, SRL, 10276 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10277 } 10278 if (Op.getOpcode() == ISD::SRA) { 10279 if (ShiftAmt == 7) { 10280 // R s>> 7 === R s< 0 10281 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10282 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10283 } 10284 10285 // R s>> a === ((R u>> a) ^ m) - m 10286 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10287 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10288 MVT::i8)); 10289 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10290 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10291 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10292 return Res; 10293 } 10294 } 10295 } 10296 } 10297 10298 // Lower SHL with variable shift amount. 10299 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10300 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10301 DAG.getConstant(23, MVT::i32)); 10302 10303 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10304 Constant *C = ConstantDataVector::get(*Context, CV); 10305 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10306 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10307 MachinePointerInfo::getConstantPool(), 10308 false, false, false, 16); 10309 10310 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10311 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10312 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10313 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10314 } 10315 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10316 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10317 10318 // a = a << 5; 10319 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10320 DAG.getConstant(5, MVT::i32)); 10321 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10322 10323 // Turn 'a' into a mask suitable for VSELECT 10324 SDValue VSelM = DAG.getConstant(0x80, VT); 10325 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10326 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10327 10328 SDValue CM1 = DAG.getConstant(0x0f, VT); 10329 SDValue CM2 = DAG.getConstant(0x3f, VT); 10330 10331 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10332 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10333 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10334 DAG.getConstant(4, MVT::i32), DAG); 10335 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10336 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10337 10338 // a += a 10339 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10340 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10341 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10342 10343 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10344 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10345 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10346 DAG.getConstant(2, MVT::i32), DAG); 10347 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10348 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10349 10350 // a += a 10351 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10352 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10353 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10354 10355 // return VSELECT(r, r+r, a); 10356 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10357 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10358 return R; 10359 } 10360 10361 // Decompose 256-bit shifts into smaller 128-bit shifts. 10362 if (VT.getSizeInBits() == 256) { 10363 unsigned NumElems = VT.getVectorNumElements(); 10364 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10365 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10366 10367 // Extract the two vectors 10368 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10369 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10370 DAG, dl); 10371 10372 // Recreate the shift amount vectors 10373 SDValue Amt1, Amt2; 10374 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10375 // Constant shift amount 10376 SmallVector<SDValue, 4> Amt1Csts; 10377 SmallVector<SDValue, 4> Amt2Csts; 10378 for (unsigned i = 0; i != NumElems/2; ++i) 10379 Amt1Csts.push_back(Amt->getOperand(i)); 10380 for (unsigned i = NumElems/2; i != NumElems; ++i) 10381 Amt2Csts.push_back(Amt->getOperand(i)); 10382 10383 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10384 &Amt1Csts[0], NumElems/2); 10385 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10386 &Amt2Csts[0], NumElems/2); 10387 } else { 10388 // Variable shift amount 10389 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10390 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10391 DAG, dl); 10392 } 10393 10394 // Issue new vector shifts for the smaller types 10395 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10396 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10397 10398 // Concatenate the result back 10399 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10400 } 10401 10402 return SDValue(); 10403} 10404 10405SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10406 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10407 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10408 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10409 // has only one use. 10410 SDNode *N = Op.getNode(); 10411 SDValue LHS = N->getOperand(0); 10412 SDValue RHS = N->getOperand(1); 10413 unsigned BaseOp = 0; 10414 unsigned Cond = 0; 10415 DebugLoc DL = Op.getDebugLoc(); 10416 switch (Op.getOpcode()) { 10417 default: llvm_unreachable("Unknown ovf instruction!"); 10418 case ISD::SADDO: 10419 // A subtract of one will be selected as a INC. Note that INC doesn't 10420 // set CF, so we can't do this for UADDO. 10421 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10422 if (C->isOne()) { 10423 BaseOp = X86ISD::INC; 10424 Cond = X86::COND_O; 10425 break; 10426 } 10427 BaseOp = X86ISD::ADD; 10428 Cond = X86::COND_O; 10429 break; 10430 case ISD::UADDO: 10431 BaseOp = X86ISD::ADD; 10432 Cond = X86::COND_B; 10433 break; 10434 case ISD::SSUBO: 10435 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10436 // set CF, so we can't do this for USUBO. 10437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10438 if (C->isOne()) { 10439 BaseOp = X86ISD::DEC; 10440 Cond = X86::COND_O; 10441 break; 10442 } 10443 BaseOp = X86ISD::SUB; 10444 Cond = X86::COND_O; 10445 break; 10446 case ISD::USUBO: 10447 BaseOp = X86ISD::SUB; 10448 Cond = X86::COND_B; 10449 break; 10450 case ISD::SMULO: 10451 BaseOp = X86ISD::SMUL; 10452 Cond = X86::COND_O; 10453 break; 10454 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10455 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10456 MVT::i32); 10457 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10458 10459 SDValue SetCC = 10460 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10461 DAG.getConstant(X86::COND_O, MVT::i32), 10462 SDValue(Sum.getNode(), 2)); 10463 10464 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10465 } 10466 } 10467 10468 // Also sets EFLAGS. 10469 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10470 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10471 10472 SDValue SetCC = 10473 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10474 DAG.getConstant(Cond, MVT::i32), 10475 SDValue(Sum.getNode(), 1)); 10476 10477 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10478} 10479 10480SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10481 SelectionDAG &DAG) const { 10482 DebugLoc dl = Op.getDebugLoc(); 10483 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10484 EVT VT = Op.getValueType(); 10485 10486 if (!Subtarget->hasSSE2() || !VT.isVector()) 10487 return SDValue(); 10488 10489 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10490 ExtraVT.getScalarType().getSizeInBits(); 10491 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10492 10493 switch (VT.getSimpleVT().SimpleTy) { 10494 default: return SDValue(); 10495 case MVT::v8i32: 10496 case MVT::v16i16: 10497 if (!Subtarget->hasAVX()) 10498 return SDValue(); 10499 if (!Subtarget->hasAVX2()) { 10500 // needs to be split 10501 int NumElems = VT.getVectorNumElements(); 10502 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10503 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10504 10505 // Extract the LHS vectors 10506 SDValue LHS = Op.getOperand(0); 10507 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10508 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10509 10510 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10511 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10512 10513 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10514 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10515 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10516 ExtraNumElems/2); 10517 SDValue Extra = DAG.getValueType(ExtraVT); 10518 10519 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10520 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10521 10522 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10523 } 10524 // fall through 10525 case MVT::v4i32: 10526 case MVT::v8i16: { 10527 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10528 Op.getOperand(0), ShAmt, DAG); 10529 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10530 } 10531 } 10532} 10533 10534 10535SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10536 DebugLoc dl = Op.getDebugLoc(); 10537 10538 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10539 // There isn't any reason to disable it if the target processor supports it. 10540 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10541 SDValue Chain = Op.getOperand(0); 10542 SDValue Zero = DAG.getConstant(0, MVT::i32); 10543 SDValue Ops[] = { 10544 DAG.getRegister(X86::ESP, MVT::i32), // Base 10545 DAG.getTargetConstant(1, MVT::i8), // Scale 10546 DAG.getRegister(0, MVT::i32), // Index 10547 DAG.getTargetConstant(0, MVT::i32), // Disp 10548 DAG.getRegister(0, MVT::i32), // Segment. 10549 Zero, 10550 Chain 10551 }; 10552 SDNode *Res = 10553 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10554 array_lengthof(Ops)); 10555 return SDValue(Res, 0); 10556 } 10557 10558 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10559 if (!isDev) 10560 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10561 10562 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10563 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10564 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10565 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10566 10567 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10568 if (!Op1 && !Op2 && !Op3 && Op4) 10569 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10570 10571 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10572 if (Op1 && !Op2 && !Op3 && !Op4) 10573 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10574 10575 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10576 // (MFENCE)>; 10577 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10578} 10579 10580SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10581 SelectionDAG &DAG) const { 10582 DebugLoc dl = Op.getDebugLoc(); 10583 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10584 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10585 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10586 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10587 10588 // The only fence that needs an instruction is a sequentially-consistent 10589 // cross-thread fence. 10590 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10591 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10592 // no-sse2). There isn't any reason to disable it if the target processor 10593 // supports it. 10594 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10595 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10596 10597 SDValue Chain = Op.getOperand(0); 10598 SDValue Zero = DAG.getConstant(0, MVT::i32); 10599 SDValue Ops[] = { 10600 DAG.getRegister(X86::ESP, MVT::i32), // Base 10601 DAG.getTargetConstant(1, MVT::i8), // Scale 10602 DAG.getRegister(0, MVT::i32), // Index 10603 DAG.getTargetConstant(0, MVT::i32), // Disp 10604 DAG.getRegister(0, MVT::i32), // Segment. 10605 Zero, 10606 Chain 10607 }; 10608 SDNode *Res = 10609 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10610 array_lengthof(Ops)); 10611 return SDValue(Res, 0); 10612 } 10613 10614 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10615 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10616} 10617 10618 10619SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10620 EVT T = Op.getValueType(); 10621 DebugLoc DL = Op.getDebugLoc(); 10622 unsigned Reg = 0; 10623 unsigned size = 0; 10624 switch(T.getSimpleVT().SimpleTy) { 10625 default: llvm_unreachable("Invalid value type!"); 10626 case MVT::i8: Reg = X86::AL; size = 1; break; 10627 case MVT::i16: Reg = X86::AX; size = 2; break; 10628 case MVT::i32: Reg = X86::EAX; size = 4; break; 10629 case MVT::i64: 10630 assert(Subtarget->is64Bit() && "Node not type legal!"); 10631 Reg = X86::RAX; size = 8; 10632 break; 10633 } 10634 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10635 Op.getOperand(2), SDValue()); 10636 SDValue Ops[] = { cpIn.getValue(0), 10637 Op.getOperand(1), 10638 Op.getOperand(3), 10639 DAG.getTargetConstant(size, MVT::i8), 10640 cpIn.getValue(1) }; 10641 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10642 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10643 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10644 Ops, 5, T, MMO); 10645 SDValue cpOut = 10646 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10647 return cpOut; 10648} 10649 10650SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10651 SelectionDAG &DAG) const { 10652 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10653 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10654 SDValue TheChain = Op.getOperand(0); 10655 DebugLoc dl = Op.getDebugLoc(); 10656 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10657 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10658 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10659 rax.getValue(2)); 10660 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10661 DAG.getConstant(32, MVT::i8)); 10662 SDValue Ops[] = { 10663 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10664 rdx.getValue(1) 10665 }; 10666 return DAG.getMergeValues(Ops, 2, dl); 10667} 10668 10669SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10670 SelectionDAG &DAG) const { 10671 EVT SrcVT = Op.getOperand(0).getValueType(); 10672 EVT DstVT = Op.getValueType(); 10673 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10674 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10675 assert((DstVT == MVT::i64 || 10676 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10677 "Unexpected custom BITCAST"); 10678 // i64 <=> MMX conversions are Legal. 10679 if (SrcVT==MVT::i64 && DstVT.isVector()) 10680 return Op; 10681 if (DstVT==MVT::i64 && SrcVT.isVector()) 10682 return Op; 10683 // MMX <=> MMX conversions are Legal. 10684 if (SrcVT.isVector() && DstVT.isVector()) 10685 return Op; 10686 // All other conversions need to be expanded. 10687 return SDValue(); 10688} 10689 10690SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10691 SDNode *Node = Op.getNode(); 10692 DebugLoc dl = Node->getDebugLoc(); 10693 EVT T = Node->getValueType(0); 10694 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10695 DAG.getConstant(0, T), Node->getOperand(2)); 10696 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10697 cast<AtomicSDNode>(Node)->getMemoryVT(), 10698 Node->getOperand(0), 10699 Node->getOperand(1), negOp, 10700 cast<AtomicSDNode>(Node)->getSrcValue(), 10701 cast<AtomicSDNode>(Node)->getAlignment(), 10702 cast<AtomicSDNode>(Node)->getOrdering(), 10703 cast<AtomicSDNode>(Node)->getSynchScope()); 10704} 10705 10706static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10707 SDNode *Node = Op.getNode(); 10708 DebugLoc dl = Node->getDebugLoc(); 10709 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10710 10711 // Convert seq_cst store -> xchg 10712 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10713 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10714 // (The only way to get a 16-byte store is cmpxchg16b) 10715 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10716 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10717 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10718 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10719 cast<AtomicSDNode>(Node)->getMemoryVT(), 10720 Node->getOperand(0), 10721 Node->getOperand(1), Node->getOperand(2), 10722 cast<AtomicSDNode>(Node)->getMemOperand(), 10723 cast<AtomicSDNode>(Node)->getOrdering(), 10724 cast<AtomicSDNode>(Node)->getSynchScope()); 10725 return Swap.getValue(1); 10726 } 10727 // Other atomic stores have a simple pattern. 10728 return Op; 10729} 10730 10731static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10732 EVT VT = Op.getNode()->getValueType(0); 10733 10734 // Let legalize expand this if it isn't a legal type yet. 10735 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10736 return SDValue(); 10737 10738 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10739 10740 unsigned Opc; 10741 bool ExtraOp = false; 10742 switch (Op.getOpcode()) { 10743 default: llvm_unreachable("Invalid code"); 10744 case ISD::ADDC: Opc = X86ISD::ADD; break; 10745 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10746 case ISD::SUBC: Opc = X86ISD::SUB; break; 10747 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10748 } 10749 10750 if (!ExtraOp) 10751 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10752 Op.getOperand(1)); 10753 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10754 Op.getOperand(1), Op.getOperand(2)); 10755} 10756 10757/// LowerOperation - Provide custom lowering hooks for some operations. 10758/// 10759SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10760 switch (Op.getOpcode()) { 10761 default: llvm_unreachable("Should not custom lower this!"); 10762 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10763 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10764 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10765 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10766 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10767 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10768 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10769 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10770 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10771 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10772 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10773 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10774 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10775 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10776 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10777 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10778 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10779 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10780 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10781 case ISD::SHL_PARTS: 10782 case ISD::SRA_PARTS: 10783 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10784 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10785 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10786 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10787 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10788 case ISD::FABS: return LowerFABS(Op, DAG); 10789 case ISD::FNEG: return LowerFNEG(Op, DAG); 10790 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10791 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10792 case ISD::SETCC: return LowerSETCC(Op, DAG); 10793 case ISD::SELECT: return LowerSELECT(Op, DAG); 10794 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10795 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10796 case ISD::VASTART: return LowerVASTART(Op, DAG); 10797 case ISD::VAARG: return LowerVAARG(Op, DAG); 10798 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10799 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10800 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10801 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10802 case ISD::FRAME_TO_ARGS_OFFSET: 10803 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10804 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10805 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10806 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10807 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10808 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10809 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10810 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10811 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10812 case ISD::MUL: return LowerMUL(Op, DAG); 10813 case ISD::SRA: 10814 case ISD::SRL: 10815 case ISD::SHL: return LowerShift(Op, DAG); 10816 case ISD::SADDO: 10817 case ISD::UADDO: 10818 case ISD::SSUBO: 10819 case ISD::USUBO: 10820 case ISD::SMULO: 10821 case ISD::UMULO: return LowerXALUO(Op, DAG); 10822 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10823 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10824 case ISD::ADDC: 10825 case ISD::ADDE: 10826 case ISD::SUBC: 10827 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10828 case ISD::ADD: return LowerADD(Op, DAG); 10829 case ISD::SUB: return LowerSUB(Op, DAG); 10830 } 10831} 10832 10833static void ReplaceATOMIC_LOAD(SDNode *Node, 10834 SmallVectorImpl<SDValue> &Results, 10835 SelectionDAG &DAG) { 10836 DebugLoc dl = Node->getDebugLoc(); 10837 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10838 10839 // Convert wide load -> cmpxchg8b/cmpxchg16b 10840 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10841 // (The only way to get a 16-byte load is cmpxchg16b) 10842 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10843 SDValue Zero = DAG.getConstant(0, VT); 10844 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10845 Node->getOperand(0), 10846 Node->getOperand(1), Zero, Zero, 10847 cast<AtomicSDNode>(Node)->getMemOperand(), 10848 cast<AtomicSDNode>(Node)->getOrdering(), 10849 cast<AtomicSDNode>(Node)->getSynchScope()); 10850 Results.push_back(Swap.getValue(0)); 10851 Results.push_back(Swap.getValue(1)); 10852} 10853 10854void X86TargetLowering:: 10855ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10856 SelectionDAG &DAG, unsigned NewOp) const { 10857 DebugLoc dl = Node->getDebugLoc(); 10858 assert (Node->getValueType(0) == MVT::i64 && 10859 "Only know how to expand i64 atomics"); 10860 10861 SDValue Chain = Node->getOperand(0); 10862 SDValue In1 = Node->getOperand(1); 10863 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10864 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10865 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10866 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10867 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10868 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10869 SDValue Result = 10870 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10871 cast<MemSDNode>(Node)->getMemOperand()); 10872 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10873 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10874 Results.push_back(Result.getValue(2)); 10875} 10876 10877/// ReplaceNodeResults - Replace a node with an illegal result type 10878/// with a new node built out of custom code. 10879void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10880 SmallVectorImpl<SDValue>&Results, 10881 SelectionDAG &DAG) const { 10882 DebugLoc dl = N->getDebugLoc(); 10883 switch (N->getOpcode()) { 10884 default: 10885 llvm_unreachable("Do not know how to custom type legalize this operation!"); 10886 case ISD::SIGN_EXTEND_INREG: 10887 case ISD::ADDC: 10888 case ISD::ADDE: 10889 case ISD::SUBC: 10890 case ISD::SUBE: 10891 // We don't want to expand or promote these. 10892 return; 10893 case ISD::FP_TO_SINT: 10894 case ISD::FP_TO_UINT: { 10895 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 10896 10897 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 10898 return; 10899 10900 std::pair<SDValue,SDValue> Vals = 10901 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 10902 SDValue FIST = Vals.first, StackSlot = Vals.second; 10903 if (FIST.getNode() != 0) { 10904 EVT VT = N->getValueType(0); 10905 // Return a load from the stack slot. 10906 if (StackSlot.getNode() != 0) 10907 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10908 MachinePointerInfo(), 10909 false, false, false, 0)); 10910 else 10911 Results.push_back(FIST); 10912 } 10913 return; 10914 } 10915 case ISD::READCYCLECOUNTER: { 10916 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10917 SDValue TheChain = N->getOperand(0); 10918 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10919 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10920 rd.getValue(1)); 10921 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10922 eax.getValue(2)); 10923 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10924 SDValue Ops[] = { eax, edx }; 10925 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10926 Results.push_back(edx.getValue(1)); 10927 return; 10928 } 10929 case ISD::ATOMIC_CMP_SWAP: { 10930 EVT T = N->getValueType(0); 10931 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10932 bool Regs64bit = T == MVT::i128; 10933 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10934 SDValue cpInL, cpInH; 10935 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10936 DAG.getConstant(0, HalfT)); 10937 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10938 DAG.getConstant(1, HalfT)); 10939 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10940 Regs64bit ? X86::RAX : X86::EAX, 10941 cpInL, SDValue()); 10942 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10943 Regs64bit ? X86::RDX : X86::EDX, 10944 cpInH, cpInL.getValue(1)); 10945 SDValue swapInL, swapInH; 10946 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10947 DAG.getConstant(0, HalfT)); 10948 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10949 DAG.getConstant(1, HalfT)); 10950 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10951 Regs64bit ? X86::RBX : X86::EBX, 10952 swapInL, cpInH.getValue(1)); 10953 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10954 Regs64bit ? X86::RCX : X86::ECX, 10955 swapInH, swapInL.getValue(1)); 10956 SDValue Ops[] = { swapInH.getValue(0), 10957 N->getOperand(1), 10958 swapInH.getValue(1) }; 10959 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10960 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10961 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10962 X86ISD::LCMPXCHG8_DAG; 10963 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10964 Ops, 3, T, MMO); 10965 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10966 Regs64bit ? X86::RAX : X86::EAX, 10967 HalfT, Result.getValue(1)); 10968 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10969 Regs64bit ? X86::RDX : X86::EDX, 10970 HalfT, cpOutL.getValue(2)); 10971 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10972 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10973 Results.push_back(cpOutH.getValue(1)); 10974 return; 10975 } 10976 case ISD::ATOMIC_LOAD_ADD: 10977 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10978 return; 10979 case ISD::ATOMIC_LOAD_AND: 10980 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10981 return; 10982 case ISD::ATOMIC_LOAD_NAND: 10983 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10984 return; 10985 case ISD::ATOMIC_LOAD_OR: 10986 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10987 return; 10988 case ISD::ATOMIC_LOAD_SUB: 10989 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10990 return; 10991 case ISD::ATOMIC_LOAD_XOR: 10992 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10993 return; 10994 case ISD::ATOMIC_SWAP: 10995 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10996 return; 10997 case ISD::ATOMIC_LOAD: 10998 ReplaceATOMIC_LOAD(N, Results, DAG); 10999 } 11000} 11001 11002const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11003 switch (Opcode) { 11004 default: return NULL; 11005 case X86ISD::BSF: return "X86ISD::BSF"; 11006 case X86ISD::BSR: return "X86ISD::BSR"; 11007 case X86ISD::SHLD: return "X86ISD::SHLD"; 11008 case X86ISD::SHRD: return "X86ISD::SHRD"; 11009 case X86ISD::FAND: return "X86ISD::FAND"; 11010 case X86ISD::FOR: return "X86ISD::FOR"; 11011 case X86ISD::FXOR: return "X86ISD::FXOR"; 11012 case X86ISD::FSRL: return "X86ISD::FSRL"; 11013 case X86ISD::FILD: return "X86ISD::FILD"; 11014 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11015 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11016 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11017 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11018 case X86ISD::FLD: return "X86ISD::FLD"; 11019 case X86ISD::FST: return "X86ISD::FST"; 11020 case X86ISD::CALL: return "X86ISD::CALL"; 11021 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11022 case X86ISD::BT: return "X86ISD::BT"; 11023 case X86ISD::CMP: return "X86ISD::CMP"; 11024 case X86ISD::COMI: return "X86ISD::COMI"; 11025 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11026 case X86ISD::SETCC: return "X86ISD::SETCC"; 11027 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11028 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11029 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11030 case X86ISD::CMOV: return "X86ISD::CMOV"; 11031 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11032 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11033 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11034 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11035 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11036 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11037 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11038 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11039 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11040 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11041 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11042 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11043 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11044 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11045 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11046 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11047 case X86ISD::HADD: return "X86ISD::HADD"; 11048 case X86ISD::HSUB: return "X86ISD::HSUB"; 11049 case X86ISD::FHADD: return "X86ISD::FHADD"; 11050 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11051 case X86ISD::FMAX: return "X86ISD::FMAX"; 11052 case X86ISD::FMIN: return "X86ISD::FMIN"; 11053 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11054 case X86ISD::FRCP: return "X86ISD::FRCP"; 11055 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11056 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11057 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11058 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11059 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11060 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11061 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11062 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11063 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11064 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11065 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11066 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11067 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11068 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11069 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11070 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11071 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11072 case X86ISD::VSHL: return "X86ISD::VSHL"; 11073 case X86ISD::VSRL: return "X86ISD::VSRL"; 11074 case X86ISD::VSRA: return "X86ISD::VSRA"; 11075 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11076 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11077 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11078 case X86ISD::CMPP: return "X86ISD::CMPP"; 11079 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11080 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11081 case X86ISD::ADD: return "X86ISD::ADD"; 11082 case X86ISD::SUB: return "X86ISD::SUB"; 11083 case X86ISD::ADC: return "X86ISD::ADC"; 11084 case X86ISD::SBB: return "X86ISD::SBB"; 11085 case X86ISD::SMUL: return "X86ISD::SMUL"; 11086 case X86ISD::UMUL: return "X86ISD::UMUL"; 11087 case X86ISD::INC: return "X86ISD::INC"; 11088 case X86ISD::DEC: return "X86ISD::DEC"; 11089 case X86ISD::OR: return "X86ISD::OR"; 11090 case X86ISD::XOR: return "X86ISD::XOR"; 11091 case X86ISD::AND: return "X86ISD::AND"; 11092 case X86ISD::ANDN: return "X86ISD::ANDN"; 11093 case X86ISD::BLSI: return "X86ISD::BLSI"; 11094 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11095 case X86ISD::BLSR: return "X86ISD::BLSR"; 11096 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11097 case X86ISD::PTEST: return "X86ISD::PTEST"; 11098 case X86ISD::TESTP: return "X86ISD::TESTP"; 11099 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11100 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11101 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11102 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11103 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11104 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11105 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11106 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11107 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11108 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11109 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11110 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11111 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11112 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11113 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11114 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11115 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11116 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11117 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11118 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11119 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11120 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11121 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11122 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11123 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11124 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11125 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11126 } 11127} 11128 11129// isLegalAddressingMode - Return true if the addressing mode represented 11130// by AM is legal for this target, for a load/store of the specified type. 11131bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11132 Type *Ty) const { 11133 // X86 supports extremely general addressing modes. 11134 CodeModel::Model M = getTargetMachine().getCodeModel(); 11135 Reloc::Model R = getTargetMachine().getRelocationModel(); 11136 11137 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11138 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11139 return false; 11140 11141 if (AM.BaseGV) { 11142 unsigned GVFlags = 11143 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11144 11145 // If a reference to this global requires an extra load, we can't fold it. 11146 if (isGlobalStubReference(GVFlags)) 11147 return false; 11148 11149 // If BaseGV requires a register for the PIC base, we cannot also have a 11150 // BaseReg specified. 11151 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11152 return false; 11153 11154 // If lower 4G is not available, then we must use rip-relative addressing. 11155 if ((M != CodeModel::Small || R != Reloc::Static) && 11156 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11157 return false; 11158 } 11159 11160 switch (AM.Scale) { 11161 case 0: 11162 case 1: 11163 case 2: 11164 case 4: 11165 case 8: 11166 // These scales always work. 11167 break; 11168 case 3: 11169 case 5: 11170 case 9: 11171 // These scales are formed with basereg+scalereg. Only accept if there is 11172 // no basereg yet. 11173 if (AM.HasBaseReg) 11174 return false; 11175 break; 11176 default: // Other stuff never works. 11177 return false; 11178 } 11179 11180 return true; 11181} 11182 11183 11184bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11185 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11186 return false; 11187 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11188 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11189 if (NumBits1 <= NumBits2) 11190 return false; 11191 return true; 11192} 11193 11194bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11195 if (!VT1.isInteger() || !VT2.isInteger()) 11196 return false; 11197 unsigned NumBits1 = VT1.getSizeInBits(); 11198 unsigned NumBits2 = VT2.getSizeInBits(); 11199 if (NumBits1 <= NumBits2) 11200 return false; 11201 return true; 11202} 11203 11204bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11205 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11206 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11207} 11208 11209bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11210 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11211 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11212} 11213 11214bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11215 // i16 instructions are longer (0x66 prefix) and potentially slower. 11216 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11217} 11218 11219/// isShuffleMaskLegal - Targets can use this to indicate that they only 11220/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11221/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11222/// are assumed to be legal. 11223bool 11224X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11225 EVT VT) const { 11226 // Very little shuffling can be done for 64-bit vectors right now. 11227 if (VT.getSizeInBits() == 64) 11228 return false; 11229 11230 // FIXME: pshufb, blends, shifts. 11231 return (VT.getVectorNumElements() == 2 || 11232 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11233 isMOVLMask(M, VT) || 11234 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11235 isPSHUFDMask(M, VT) || 11236 isPSHUFHWMask(M, VT) || 11237 isPSHUFLWMask(M, VT) || 11238 isPALIGNRMask(M, VT, Subtarget) || 11239 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11240 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11241 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11242 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11243} 11244 11245bool 11246X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11247 EVT VT) const { 11248 unsigned NumElts = VT.getVectorNumElements(); 11249 // FIXME: This collection of masks seems suspect. 11250 if (NumElts == 2) 11251 return true; 11252 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11253 return (isMOVLMask(Mask, VT) || 11254 isCommutedMOVLMask(Mask, VT, true) || 11255 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11256 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11257 } 11258 return false; 11259} 11260 11261//===----------------------------------------------------------------------===// 11262// X86 Scheduler Hooks 11263//===----------------------------------------------------------------------===// 11264 11265// private utility function 11266MachineBasicBlock * 11267X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11268 MachineBasicBlock *MBB, 11269 unsigned regOpc, 11270 unsigned immOpc, 11271 unsigned LoadOpc, 11272 unsigned CXchgOpc, 11273 unsigned notOpc, 11274 unsigned EAXreg, 11275 const TargetRegisterClass *RC, 11276 bool invSrc) const { 11277 // For the atomic bitwise operator, we generate 11278 // thisMBB: 11279 // newMBB: 11280 // ld t1 = [bitinstr.addr] 11281 // op t2 = t1, [bitinstr.val] 11282 // mov EAX = t1 11283 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11284 // bz newMBB 11285 // fallthrough -->nextMBB 11286 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11287 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11288 MachineFunction::iterator MBBIter = MBB; 11289 ++MBBIter; 11290 11291 /// First build the CFG 11292 MachineFunction *F = MBB->getParent(); 11293 MachineBasicBlock *thisMBB = MBB; 11294 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11295 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11296 F->insert(MBBIter, newMBB); 11297 F->insert(MBBIter, nextMBB); 11298 11299 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11300 nextMBB->splice(nextMBB->begin(), thisMBB, 11301 llvm::next(MachineBasicBlock::iterator(bInstr)), 11302 thisMBB->end()); 11303 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11304 11305 // Update thisMBB to fall through to newMBB 11306 thisMBB->addSuccessor(newMBB); 11307 11308 // newMBB jumps to itself and fall through to nextMBB 11309 newMBB->addSuccessor(nextMBB); 11310 newMBB->addSuccessor(newMBB); 11311 11312 // Insert instructions into newMBB based on incoming instruction 11313 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11314 "unexpected number of operands"); 11315 DebugLoc dl = bInstr->getDebugLoc(); 11316 MachineOperand& destOper = bInstr->getOperand(0); 11317 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11318 int numArgs = bInstr->getNumOperands() - 1; 11319 for (int i=0; i < numArgs; ++i) 11320 argOpers[i] = &bInstr->getOperand(i+1); 11321 11322 // x86 address has 4 operands: base, index, scale, and displacement 11323 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11324 int valArgIndx = lastAddrIndx + 1; 11325 11326 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11327 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11328 for (int i=0; i <= lastAddrIndx; ++i) 11329 (*MIB).addOperand(*argOpers[i]); 11330 11331 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11332 if (invSrc) { 11333 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11334 } 11335 else 11336 tt = t1; 11337 11338 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11339 assert((argOpers[valArgIndx]->isReg() || 11340 argOpers[valArgIndx]->isImm()) && 11341 "invalid operand"); 11342 if (argOpers[valArgIndx]->isReg()) 11343 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11344 else 11345 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11346 MIB.addReg(tt); 11347 (*MIB).addOperand(*argOpers[valArgIndx]); 11348 11349 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11350 MIB.addReg(t1); 11351 11352 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11353 for (int i=0; i <= lastAddrIndx; ++i) 11354 (*MIB).addOperand(*argOpers[i]); 11355 MIB.addReg(t2); 11356 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11357 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11358 bInstr->memoperands_end()); 11359 11360 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11361 MIB.addReg(EAXreg); 11362 11363 // insert branch 11364 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11365 11366 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11367 return nextMBB; 11368} 11369 11370// private utility function: 64 bit atomics on 32 bit host. 11371MachineBasicBlock * 11372X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11373 MachineBasicBlock *MBB, 11374 unsigned regOpcL, 11375 unsigned regOpcH, 11376 unsigned immOpcL, 11377 unsigned immOpcH, 11378 bool invSrc) const { 11379 // For the atomic bitwise operator, we generate 11380 // thisMBB (instructions are in pairs, except cmpxchg8b) 11381 // ld t1,t2 = [bitinstr.addr] 11382 // newMBB: 11383 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11384 // op t5, t6 <- out1, out2, [bitinstr.val] 11385 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11386 // mov ECX, EBX <- t5, t6 11387 // mov EAX, EDX <- t1, t2 11388 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11389 // mov t3, t4 <- EAX, EDX 11390 // bz newMBB 11391 // result in out1, out2 11392 // fallthrough -->nextMBB 11393 11394 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11395 const unsigned LoadOpc = X86::MOV32rm; 11396 const unsigned NotOpc = X86::NOT32r; 11397 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11398 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11399 MachineFunction::iterator MBBIter = MBB; 11400 ++MBBIter; 11401 11402 /// First build the CFG 11403 MachineFunction *F = MBB->getParent(); 11404 MachineBasicBlock *thisMBB = MBB; 11405 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11406 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11407 F->insert(MBBIter, newMBB); 11408 F->insert(MBBIter, nextMBB); 11409 11410 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11411 nextMBB->splice(nextMBB->begin(), thisMBB, 11412 llvm::next(MachineBasicBlock::iterator(bInstr)), 11413 thisMBB->end()); 11414 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11415 11416 // Update thisMBB to fall through to newMBB 11417 thisMBB->addSuccessor(newMBB); 11418 11419 // newMBB jumps to itself and fall through to nextMBB 11420 newMBB->addSuccessor(nextMBB); 11421 newMBB->addSuccessor(newMBB); 11422 11423 DebugLoc dl = bInstr->getDebugLoc(); 11424 // Insert instructions into newMBB based on incoming instruction 11425 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11426 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11427 "unexpected number of operands"); 11428 MachineOperand& dest1Oper = bInstr->getOperand(0); 11429 MachineOperand& dest2Oper = bInstr->getOperand(1); 11430 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11431 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11432 argOpers[i] = &bInstr->getOperand(i+2); 11433 11434 // We use some of the operands multiple times, so conservatively just 11435 // clear any kill flags that might be present. 11436 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11437 argOpers[i]->setIsKill(false); 11438 } 11439 11440 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11441 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11442 11443 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11444 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11445 for (int i=0; i <= lastAddrIndx; ++i) 11446 (*MIB).addOperand(*argOpers[i]); 11447 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11448 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11449 // add 4 to displacement. 11450 for (int i=0; i <= lastAddrIndx-2; ++i) 11451 (*MIB).addOperand(*argOpers[i]); 11452 MachineOperand newOp3 = *(argOpers[3]); 11453 if (newOp3.isImm()) 11454 newOp3.setImm(newOp3.getImm()+4); 11455 else 11456 newOp3.setOffset(newOp3.getOffset()+4); 11457 (*MIB).addOperand(newOp3); 11458 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11459 11460 // t3/4 are defined later, at the bottom of the loop 11461 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11462 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11463 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11464 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11465 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11466 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11467 11468 // The subsequent operations should be using the destination registers of 11469 //the PHI instructions. 11470 if (invSrc) { 11471 t1 = F->getRegInfo().createVirtualRegister(RC); 11472 t2 = F->getRegInfo().createVirtualRegister(RC); 11473 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11474 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11475 } else { 11476 t1 = dest1Oper.getReg(); 11477 t2 = dest2Oper.getReg(); 11478 } 11479 11480 int valArgIndx = lastAddrIndx + 1; 11481 assert((argOpers[valArgIndx]->isReg() || 11482 argOpers[valArgIndx]->isImm()) && 11483 "invalid operand"); 11484 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11485 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11486 if (argOpers[valArgIndx]->isReg()) 11487 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11488 else 11489 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11490 if (regOpcL != X86::MOV32rr) 11491 MIB.addReg(t1); 11492 (*MIB).addOperand(*argOpers[valArgIndx]); 11493 assert(argOpers[valArgIndx + 1]->isReg() == 11494 argOpers[valArgIndx]->isReg()); 11495 assert(argOpers[valArgIndx + 1]->isImm() == 11496 argOpers[valArgIndx]->isImm()); 11497 if (argOpers[valArgIndx + 1]->isReg()) 11498 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11499 else 11500 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11501 if (regOpcH != X86::MOV32rr) 11502 MIB.addReg(t2); 11503 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11504 11505 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11506 MIB.addReg(t1); 11507 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11508 MIB.addReg(t2); 11509 11510 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11511 MIB.addReg(t5); 11512 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11513 MIB.addReg(t6); 11514 11515 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11516 for (int i=0; i <= lastAddrIndx; ++i) 11517 (*MIB).addOperand(*argOpers[i]); 11518 11519 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11520 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11521 bInstr->memoperands_end()); 11522 11523 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11524 MIB.addReg(X86::EAX); 11525 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11526 MIB.addReg(X86::EDX); 11527 11528 // insert branch 11529 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11530 11531 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11532 return nextMBB; 11533} 11534 11535// private utility function 11536MachineBasicBlock * 11537X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11538 MachineBasicBlock *MBB, 11539 unsigned cmovOpc) const { 11540 // For the atomic min/max operator, we generate 11541 // thisMBB: 11542 // newMBB: 11543 // ld t1 = [min/max.addr] 11544 // mov t2 = [min/max.val] 11545 // cmp t1, t2 11546 // cmov[cond] t2 = t1 11547 // mov EAX = t1 11548 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11549 // bz newMBB 11550 // fallthrough -->nextMBB 11551 // 11552 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11553 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11554 MachineFunction::iterator MBBIter = MBB; 11555 ++MBBIter; 11556 11557 /// First build the CFG 11558 MachineFunction *F = MBB->getParent(); 11559 MachineBasicBlock *thisMBB = MBB; 11560 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11561 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11562 F->insert(MBBIter, newMBB); 11563 F->insert(MBBIter, nextMBB); 11564 11565 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11566 nextMBB->splice(nextMBB->begin(), thisMBB, 11567 llvm::next(MachineBasicBlock::iterator(mInstr)), 11568 thisMBB->end()); 11569 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11570 11571 // Update thisMBB to fall through to newMBB 11572 thisMBB->addSuccessor(newMBB); 11573 11574 // newMBB jumps to newMBB and fall through to nextMBB 11575 newMBB->addSuccessor(nextMBB); 11576 newMBB->addSuccessor(newMBB); 11577 11578 DebugLoc dl = mInstr->getDebugLoc(); 11579 // Insert instructions into newMBB based on incoming instruction 11580 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11581 "unexpected number of operands"); 11582 MachineOperand& destOper = mInstr->getOperand(0); 11583 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11584 int numArgs = mInstr->getNumOperands() - 1; 11585 for (int i=0; i < numArgs; ++i) 11586 argOpers[i] = &mInstr->getOperand(i+1); 11587 11588 // x86 address has 4 operands: base, index, scale, and displacement 11589 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11590 int valArgIndx = lastAddrIndx + 1; 11591 11592 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11593 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11594 for (int i=0; i <= lastAddrIndx; ++i) 11595 (*MIB).addOperand(*argOpers[i]); 11596 11597 // We only support register and immediate values 11598 assert((argOpers[valArgIndx]->isReg() || 11599 argOpers[valArgIndx]->isImm()) && 11600 "invalid operand"); 11601 11602 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11603 if (argOpers[valArgIndx]->isReg()) 11604 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11605 else 11606 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11607 (*MIB).addOperand(*argOpers[valArgIndx]); 11608 11609 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11610 MIB.addReg(t1); 11611 11612 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11613 MIB.addReg(t1); 11614 MIB.addReg(t2); 11615 11616 // Generate movc 11617 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11618 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11619 MIB.addReg(t2); 11620 MIB.addReg(t1); 11621 11622 // Cmp and exchange if none has modified the memory location 11623 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11624 for (int i=0; i <= lastAddrIndx; ++i) 11625 (*MIB).addOperand(*argOpers[i]); 11626 MIB.addReg(t3); 11627 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11628 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11629 mInstr->memoperands_end()); 11630 11631 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11632 MIB.addReg(X86::EAX); 11633 11634 // insert branch 11635 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11636 11637 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11638 return nextMBB; 11639} 11640 11641// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11642// or XMM0_V32I8 in AVX all of this code can be replaced with that 11643// in the .td file. 11644MachineBasicBlock * 11645X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11646 unsigned numArgs, bool memArg) const { 11647 assert(Subtarget->hasSSE42() && 11648 "Target must have SSE4.2 or AVX features enabled"); 11649 11650 DebugLoc dl = MI->getDebugLoc(); 11651 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11652 unsigned Opc; 11653 if (!Subtarget->hasAVX()) { 11654 if (memArg) 11655 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11656 else 11657 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11658 } else { 11659 if (memArg) 11660 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11661 else 11662 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11663 } 11664 11665 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11666 for (unsigned i = 0; i < numArgs; ++i) { 11667 MachineOperand &Op = MI->getOperand(i+1); 11668 if (!(Op.isReg() && Op.isImplicit())) 11669 MIB.addOperand(Op); 11670 } 11671 BuildMI(*BB, MI, dl, 11672 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11673 MI->getOperand(0).getReg()) 11674 .addReg(X86::XMM0); 11675 11676 MI->eraseFromParent(); 11677 return BB; 11678} 11679 11680MachineBasicBlock * 11681X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11682 DebugLoc dl = MI->getDebugLoc(); 11683 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11684 11685 // Address into RAX/EAX, other two args into ECX, EDX. 11686 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11687 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11688 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11689 for (int i = 0; i < X86::AddrNumOperands; ++i) 11690 MIB.addOperand(MI->getOperand(i)); 11691 11692 unsigned ValOps = X86::AddrNumOperands; 11693 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11694 .addReg(MI->getOperand(ValOps).getReg()); 11695 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11696 .addReg(MI->getOperand(ValOps+1).getReg()); 11697 11698 // The instruction doesn't actually take any operands though. 11699 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11700 11701 MI->eraseFromParent(); // The pseudo is gone now. 11702 return BB; 11703} 11704 11705MachineBasicBlock * 11706X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11707 DebugLoc dl = MI->getDebugLoc(); 11708 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11709 11710 // First arg in ECX, the second in EAX. 11711 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11712 .addReg(MI->getOperand(0).getReg()); 11713 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11714 .addReg(MI->getOperand(1).getReg()); 11715 11716 // The instruction doesn't actually take any operands though. 11717 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11718 11719 MI->eraseFromParent(); // The pseudo is gone now. 11720 return BB; 11721} 11722 11723MachineBasicBlock * 11724X86TargetLowering::EmitVAARG64WithCustomInserter( 11725 MachineInstr *MI, 11726 MachineBasicBlock *MBB) const { 11727 // Emit va_arg instruction on X86-64. 11728 11729 // Operands to this pseudo-instruction: 11730 // 0 ) Output : destination address (reg) 11731 // 1-5) Input : va_list address (addr, i64mem) 11732 // 6 ) ArgSize : Size (in bytes) of vararg type 11733 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11734 // 8 ) Align : Alignment of type 11735 // 9 ) EFLAGS (implicit-def) 11736 11737 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11738 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11739 11740 unsigned DestReg = MI->getOperand(0).getReg(); 11741 MachineOperand &Base = MI->getOperand(1); 11742 MachineOperand &Scale = MI->getOperand(2); 11743 MachineOperand &Index = MI->getOperand(3); 11744 MachineOperand &Disp = MI->getOperand(4); 11745 MachineOperand &Segment = MI->getOperand(5); 11746 unsigned ArgSize = MI->getOperand(6).getImm(); 11747 unsigned ArgMode = MI->getOperand(7).getImm(); 11748 unsigned Align = MI->getOperand(8).getImm(); 11749 11750 // Memory Reference 11751 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11752 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11753 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11754 11755 // Machine Information 11756 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11757 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11758 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11759 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11760 DebugLoc DL = MI->getDebugLoc(); 11761 11762 // struct va_list { 11763 // i32 gp_offset 11764 // i32 fp_offset 11765 // i64 overflow_area (address) 11766 // i64 reg_save_area (address) 11767 // } 11768 // sizeof(va_list) = 24 11769 // alignment(va_list) = 8 11770 11771 unsigned TotalNumIntRegs = 6; 11772 unsigned TotalNumXMMRegs = 8; 11773 bool UseGPOffset = (ArgMode == 1); 11774 bool UseFPOffset = (ArgMode == 2); 11775 unsigned MaxOffset = TotalNumIntRegs * 8 + 11776 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11777 11778 /* Align ArgSize to a multiple of 8 */ 11779 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11780 bool NeedsAlign = (Align > 8); 11781 11782 MachineBasicBlock *thisMBB = MBB; 11783 MachineBasicBlock *overflowMBB; 11784 MachineBasicBlock *offsetMBB; 11785 MachineBasicBlock *endMBB; 11786 11787 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11788 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11789 unsigned OffsetReg = 0; 11790 11791 if (!UseGPOffset && !UseFPOffset) { 11792 // If we only pull from the overflow region, we don't create a branch. 11793 // We don't need to alter control flow. 11794 OffsetDestReg = 0; // unused 11795 OverflowDestReg = DestReg; 11796 11797 offsetMBB = NULL; 11798 overflowMBB = thisMBB; 11799 endMBB = thisMBB; 11800 } else { 11801 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11802 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11803 // If not, pull from overflow_area. (branch to overflowMBB) 11804 // 11805 // thisMBB 11806 // | . 11807 // | . 11808 // offsetMBB overflowMBB 11809 // | . 11810 // | . 11811 // endMBB 11812 11813 // Registers for the PHI in endMBB 11814 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11815 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11816 11817 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11818 MachineFunction *MF = MBB->getParent(); 11819 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11820 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11821 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11822 11823 MachineFunction::iterator MBBIter = MBB; 11824 ++MBBIter; 11825 11826 // Insert the new basic blocks 11827 MF->insert(MBBIter, offsetMBB); 11828 MF->insert(MBBIter, overflowMBB); 11829 MF->insert(MBBIter, endMBB); 11830 11831 // Transfer the remainder of MBB and its successor edges to endMBB. 11832 endMBB->splice(endMBB->begin(), thisMBB, 11833 llvm::next(MachineBasicBlock::iterator(MI)), 11834 thisMBB->end()); 11835 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11836 11837 // Make offsetMBB and overflowMBB successors of thisMBB 11838 thisMBB->addSuccessor(offsetMBB); 11839 thisMBB->addSuccessor(overflowMBB); 11840 11841 // endMBB is a successor of both offsetMBB and overflowMBB 11842 offsetMBB->addSuccessor(endMBB); 11843 overflowMBB->addSuccessor(endMBB); 11844 11845 // Load the offset value into a register 11846 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11847 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11848 .addOperand(Base) 11849 .addOperand(Scale) 11850 .addOperand(Index) 11851 .addDisp(Disp, UseFPOffset ? 4 : 0) 11852 .addOperand(Segment) 11853 .setMemRefs(MMOBegin, MMOEnd); 11854 11855 // Check if there is enough room left to pull this argument. 11856 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11857 .addReg(OffsetReg) 11858 .addImm(MaxOffset + 8 - ArgSizeA8); 11859 11860 // Branch to "overflowMBB" if offset >= max 11861 // Fall through to "offsetMBB" otherwise 11862 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11863 .addMBB(overflowMBB); 11864 } 11865 11866 // In offsetMBB, emit code to use the reg_save_area. 11867 if (offsetMBB) { 11868 assert(OffsetReg != 0); 11869 11870 // Read the reg_save_area address. 11871 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11872 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11873 .addOperand(Base) 11874 .addOperand(Scale) 11875 .addOperand(Index) 11876 .addDisp(Disp, 16) 11877 .addOperand(Segment) 11878 .setMemRefs(MMOBegin, MMOEnd); 11879 11880 // Zero-extend the offset 11881 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11882 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11883 .addImm(0) 11884 .addReg(OffsetReg) 11885 .addImm(X86::sub_32bit); 11886 11887 // Add the offset to the reg_save_area to get the final address. 11888 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11889 .addReg(OffsetReg64) 11890 .addReg(RegSaveReg); 11891 11892 // Compute the offset for the next argument 11893 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11894 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11895 .addReg(OffsetReg) 11896 .addImm(UseFPOffset ? 16 : 8); 11897 11898 // Store it back into the va_list. 11899 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11900 .addOperand(Base) 11901 .addOperand(Scale) 11902 .addOperand(Index) 11903 .addDisp(Disp, UseFPOffset ? 4 : 0) 11904 .addOperand(Segment) 11905 .addReg(NextOffsetReg) 11906 .setMemRefs(MMOBegin, MMOEnd); 11907 11908 // Jump to endMBB 11909 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11910 .addMBB(endMBB); 11911 } 11912 11913 // 11914 // Emit code to use overflow area 11915 // 11916 11917 // Load the overflow_area address into a register. 11918 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11919 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11920 .addOperand(Base) 11921 .addOperand(Scale) 11922 .addOperand(Index) 11923 .addDisp(Disp, 8) 11924 .addOperand(Segment) 11925 .setMemRefs(MMOBegin, MMOEnd); 11926 11927 // If we need to align it, do so. Otherwise, just copy the address 11928 // to OverflowDestReg. 11929 if (NeedsAlign) { 11930 // Align the overflow address 11931 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11932 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11933 11934 // aligned_addr = (addr + (align-1)) & ~(align-1) 11935 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11936 .addReg(OverflowAddrReg) 11937 .addImm(Align-1); 11938 11939 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11940 .addReg(TmpReg) 11941 .addImm(~(uint64_t)(Align-1)); 11942 } else { 11943 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11944 .addReg(OverflowAddrReg); 11945 } 11946 11947 // Compute the next overflow address after this argument. 11948 // (the overflow address should be kept 8-byte aligned) 11949 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11950 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11951 .addReg(OverflowDestReg) 11952 .addImm(ArgSizeA8); 11953 11954 // Store the new overflow address. 11955 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11956 .addOperand(Base) 11957 .addOperand(Scale) 11958 .addOperand(Index) 11959 .addDisp(Disp, 8) 11960 .addOperand(Segment) 11961 .addReg(NextAddrReg) 11962 .setMemRefs(MMOBegin, MMOEnd); 11963 11964 // If we branched, emit the PHI to the front of endMBB. 11965 if (offsetMBB) { 11966 BuildMI(*endMBB, endMBB->begin(), DL, 11967 TII->get(X86::PHI), DestReg) 11968 .addReg(OffsetDestReg).addMBB(offsetMBB) 11969 .addReg(OverflowDestReg).addMBB(overflowMBB); 11970 } 11971 11972 // Erase the pseudo instruction 11973 MI->eraseFromParent(); 11974 11975 return endMBB; 11976} 11977 11978MachineBasicBlock * 11979X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11980 MachineInstr *MI, 11981 MachineBasicBlock *MBB) const { 11982 // Emit code to save XMM registers to the stack. The ABI says that the 11983 // number of registers to save is given in %al, so it's theoretically 11984 // possible to do an indirect jump trick to avoid saving all of them, 11985 // however this code takes a simpler approach and just executes all 11986 // of the stores if %al is non-zero. It's less code, and it's probably 11987 // easier on the hardware branch predictor, and stores aren't all that 11988 // expensive anyway. 11989 11990 // Create the new basic blocks. One block contains all the XMM stores, 11991 // and one block is the final destination regardless of whether any 11992 // stores were performed. 11993 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11994 MachineFunction *F = MBB->getParent(); 11995 MachineFunction::iterator MBBIter = MBB; 11996 ++MBBIter; 11997 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11998 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11999 F->insert(MBBIter, XMMSaveMBB); 12000 F->insert(MBBIter, EndMBB); 12001 12002 // Transfer the remainder of MBB and its successor edges to EndMBB. 12003 EndMBB->splice(EndMBB->begin(), MBB, 12004 llvm::next(MachineBasicBlock::iterator(MI)), 12005 MBB->end()); 12006 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12007 12008 // The original block will now fall through to the XMM save block. 12009 MBB->addSuccessor(XMMSaveMBB); 12010 // The XMMSaveMBB will fall through to the end block. 12011 XMMSaveMBB->addSuccessor(EndMBB); 12012 12013 // Now add the instructions. 12014 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12015 DebugLoc DL = MI->getDebugLoc(); 12016 12017 unsigned CountReg = MI->getOperand(0).getReg(); 12018 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12019 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12020 12021 if (!Subtarget->isTargetWin64()) { 12022 // If %al is 0, branch around the XMM save block. 12023 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12024 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12025 MBB->addSuccessor(EndMBB); 12026 } 12027 12028 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12029 // In the XMM save block, save all the XMM argument registers. 12030 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12031 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12032 MachineMemOperand *MMO = 12033 F->getMachineMemOperand( 12034 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12035 MachineMemOperand::MOStore, 12036 /*Size=*/16, /*Align=*/16); 12037 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12038 .addFrameIndex(RegSaveFrameIndex) 12039 .addImm(/*Scale=*/1) 12040 .addReg(/*IndexReg=*/0) 12041 .addImm(/*Disp=*/Offset) 12042 .addReg(/*Segment=*/0) 12043 .addReg(MI->getOperand(i).getReg()) 12044 .addMemOperand(MMO); 12045 } 12046 12047 MI->eraseFromParent(); // The pseudo instruction is gone now. 12048 12049 return EndMBB; 12050} 12051 12052// The EFLAGS operand of SelectItr might be missing a kill marker 12053// because there were multiple uses of EFLAGS, and ISel didn't know 12054// which to mark. Figure out whether SelectItr should have had a 12055// kill marker, and set it if it should. Returns the correct kill 12056// marker value. 12057static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12058 MachineBasicBlock* BB, 12059 const TargetRegisterInfo* TRI) { 12060 // Scan forward through BB for a use/def of EFLAGS. 12061 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12062 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12063 const MachineInstr& mi = *miI; 12064 if (mi.readsRegister(X86::EFLAGS)) 12065 return false; 12066 if (mi.definesRegister(X86::EFLAGS)) 12067 break; // Should have kill-flag - update below. 12068 } 12069 12070 // If we hit the end of the block, check whether EFLAGS is live into a 12071 // successor. 12072 if (miI == BB->end()) { 12073 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12074 sEnd = BB->succ_end(); 12075 sItr != sEnd; ++sItr) { 12076 MachineBasicBlock* succ = *sItr; 12077 if (succ->isLiveIn(X86::EFLAGS)) 12078 return false; 12079 } 12080 } 12081 12082 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12083 // out. SelectMI should have a kill flag on EFLAGS. 12084 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12085 return true; 12086} 12087 12088MachineBasicBlock * 12089X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12090 MachineBasicBlock *BB) const { 12091 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12092 DebugLoc DL = MI->getDebugLoc(); 12093 12094 // To "insert" a SELECT_CC instruction, we actually have to insert the 12095 // diamond control-flow pattern. The incoming instruction knows the 12096 // destination vreg to set, the condition code register to branch on, the 12097 // true/false values to select between, and a branch opcode to use. 12098 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12099 MachineFunction::iterator It = BB; 12100 ++It; 12101 12102 // thisMBB: 12103 // ... 12104 // TrueVal = ... 12105 // cmpTY ccX, r1, r2 12106 // bCC copy1MBB 12107 // fallthrough --> copy0MBB 12108 MachineBasicBlock *thisMBB = BB; 12109 MachineFunction *F = BB->getParent(); 12110 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12111 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12112 F->insert(It, copy0MBB); 12113 F->insert(It, sinkMBB); 12114 12115 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12116 // live into the sink and copy blocks. 12117 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12118 if (!MI->killsRegister(X86::EFLAGS) && 12119 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12120 copy0MBB->addLiveIn(X86::EFLAGS); 12121 sinkMBB->addLiveIn(X86::EFLAGS); 12122 } 12123 12124 // Transfer the remainder of BB and its successor edges to sinkMBB. 12125 sinkMBB->splice(sinkMBB->begin(), BB, 12126 llvm::next(MachineBasicBlock::iterator(MI)), 12127 BB->end()); 12128 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12129 12130 // Add the true and fallthrough blocks as its successors. 12131 BB->addSuccessor(copy0MBB); 12132 BB->addSuccessor(sinkMBB); 12133 12134 // Create the conditional branch instruction. 12135 unsigned Opc = 12136 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12137 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12138 12139 // copy0MBB: 12140 // %FalseValue = ... 12141 // # fallthrough to sinkMBB 12142 copy0MBB->addSuccessor(sinkMBB); 12143 12144 // sinkMBB: 12145 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12146 // ... 12147 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12148 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12149 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12150 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12151 12152 MI->eraseFromParent(); // The pseudo instruction is gone now. 12153 return sinkMBB; 12154} 12155 12156MachineBasicBlock * 12157X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12158 bool Is64Bit) const { 12159 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12160 DebugLoc DL = MI->getDebugLoc(); 12161 MachineFunction *MF = BB->getParent(); 12162 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12163 12164 assert(getTargetMachine().Options.EnableSegmentedStacks); 12165 12166 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12167 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12168 12169 // BB: 12170 // ... [Till the alloca] 12171 // If stacklet is not large enough, jump to mallocMBB 12172 // 12173 // bumpMBB: 12174 // Allocate by subtracting from RSP 12175 // Jump to continueMBB 12176 // 12177 // mallocMBB: 12178 // Allocate by call to runtime 12179 // 12180 // continueMBB: 12181 // ... 12182 // [rest of original BB] 12183 // 12184 12185 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12186 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12187 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12188 12189 MachineRegisterInfo &MRI = MF->getRegInfo(); 12190 const TargetRegisterClass *AddrRegClass = 12191 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12192 12193 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12194 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12195 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12196 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12197 sizeVReg = MI->getOperand(1).getReg(), 12198 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12199 12200 MachineFunction::iterator MBBIter = BB; 12201 ++MBBIter; 12202 12203 MF->insert(MBBIter, bumpMBB); 12204 MF->insert(MBBIter, mallocMBB); 12205 MF->insert(MBBIter, continueMBB); 12206 12207 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12208 (MachineBasicBlock::iterator(MI)), BB->end()); 12209 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12210 12211 // Add code to the main basic block to check if the stack limit has been hit, 12212 // and if so, jump to mallocMBB otherwise to bumpMBB. 12213 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12214 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12215 .addReg(tmpSPVReg).addReg(sizeVReg); 12216 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12217 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12218 .addReg(SPLimitVReg); 12219 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12220 12221 // bumpMBB simply decreases the stack pointer, since we know the current 12222 // stacklet has enough space. 12223 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12224 .addReg(SPLimitVReg); 12225 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12226 .addReg(SPLimitVReg); 12227 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12228 12229 // Calls into a routine in libgcc to allocate more space from the heap. 12230 const uint32_t *RegMask = 12231 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12232 if (Is64Bit) { 12233 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12234 .addReg(sizeVReg); 12235 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12236 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI) 12237 .addRegMask(RegMask) 12238 .addReg(X86::RAX, RegState::ImplicitDefine); 12239 } else { 12240 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12241 .addImm(12); 12242 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12243 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12244 .addExternalSymbol("__morestack_allocate_stack_space") 12245 .addRegMask(RegMask) 12246 .addReg(X86::EAX, RegState::ImplicitDefine); 12247 } 12248 12249 if (!Is64Bit) 12250 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12251 .addImm(16); 12252 12253 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12254 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12255 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12256 12257 // Set up the CFG correctly. 12258 BB->addSuccessor(bumpMBB); 12259 BB->addSuccessor(mallocMBB); 12260 mallocMBB->addSuccessor(continueMBB); 12261 bumpMBB->addSuccessor(continueMBB); 12262 12263 // Take care of the PHI nodes. 12264 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12265 MI->getOperand(0).getReg()) 12266 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12267 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12268 12269 // Delete the original pseudo instruction. 12270 MI->eraseFromParent(); 12271 12272 // And we're done. 12273 return continueMBB; 12274} 12275 12276MachineBasicBlock * 12277X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12278 MachineBasicBlock *BB) const { 12279 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12280 DebugLoc DL = MI->getDebugLoc(); 12281 12282 assert(!Subtarget->isTargetEnvMacho()); 12283 12284 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12285 // non-trivial part is impdef of ESP. 12286 12287 if (Subtarget->isTargetWin64()) { 12288 if (Subtarget->isTargetCygMing()) { 12289 // ___chkstk(Mingw64): 12290 // Clobbers R10, R11, RAX and EFLAGS. 12291 // Updates RSP. 12292 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12293 .addExternalSymbol("___chkstk") 12294 .addReg(X86::RAX, RegState::Implicit) 12295 .addReg(X86::RSP, RegState::Implicit) 12296 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12297 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12298 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12299 } else { 12300 // __chkstk(MSVCRT): does not update stack pointer. 12301 // Clobbers R10, R11 and EFLAGS. 12302 // FIXME: RAX(allocated size) might be reused and not killed. 12303 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12304 .addExternalSymbol("__chkstk") 12305 .addReg(X86::RAX, RegState::Implicit) 12306 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12307 // RAX has the offset to subtracted from RSP. 12308 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12309 .addReg(X86::RSP) 12310 .addReg(X86::RAX); 12311 } 12312 } else { 12313 const char *StackProbeSymbol = 12314 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12315 12316 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12317 .addExternalSymbol(StackProbeSymbol) 12318 .addReg(X86::EAX, RegState::Implicit) 12319 .addReg(X86::ESP, RegState::Implicit) 12320 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12321 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12322 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12323 } 12324 12325 MI->eraseFromParent(); // The pseudo instruction is gone now. 12326 return BB; 12327} 12328 12329MachineBasicBlock * 12330X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12331 MachineBasicBlock *BB) const { 12332 // This is pretty easy. We're taking the value that we received from 12333 // our load from the relocation, sticking it in either RDI (x86-64) 12334 // or EAX and doing an indirect call. The return value will then 12335 // be in the normal return register. 12336 const X86InstrInfo *TII 12337 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12338 DebugLoc DL = MI->getDebugLoc(); 12339 MachineFunction *F = BB->getParent(); 12340 12341 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12342 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12343 12344 // Get a register mask for the lowered call. 12345 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12346 // proper register mask. 12347 const uint32_t *RegMask = 12348 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12349 if (Subtarget->is64Bit()) { 12350 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12351 TII->get(X86::MOV64rm), X86::RDI) 12352 .addReg(X86::RIP) 12353 .addImm(0).addReg(0) 12354 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12355 MI->getOperand(3).getTargetFlags()) 12356 .addReg(0); 12357 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12358 addDirectMem(MIB, X86::RDI); 12359 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12360 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12361 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12362 TII->get(X86::MOV32rm), X86::EAX) 12363 .addReg(0) 12364 .addImm(0).addReg(0) 12365 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12366 MI->getOperand(3).getTargetFlags()) 12367 .addReg(0); 12368 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12369 addDirectMem(MIB, X86::EAX); 12370 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12371 } else { 12372 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12373 TII->get(X86::MOV32rm), X86::EAX) 12374 .addReg(TII->getGlobalBaseReg(F)) 12375 .addImm(0).addReg(0) 12376 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12377 MI->getOperand(3).getTargetFlags()) 12378 .addReg(0); 12379 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12380 addDirectMem(MIB, X86::EAX); 12381 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12382 } 12383 12384 MI->eraseFromParent(); // The pseudo instruction is gone now. 12385 return BB; 12386} 12387 12388MachineBasicBlock * 12389X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12390 MachineBasicBlock *BB) const { 12391 switch (MI->getOpcode()) { 12392 default: llvm_unreachable("Unexpected instr type to insert"); 12393 case X86::TAILJMPd64: 12394 case X86::TAILJMPr64: 12395 case X86::TAILJMPm64: 12396 llvm_unreachable("TAILJMP64 would not be touched here."); 12397 case X86::TCRETURNdi64: 12398 case X86::TCRETURNri64: 12399 case X86::TCRETURNmi64: 12400 return BB; 12401 case X86::WIN_ALLOCA: 12402 return EmitLoweredWinAlloca(MI, BB); 12403 case X86::SEG_ALLOCA_32: 12404 return EmitLoweredSegAlloca(MI, BB, false); 12405 case X86::SEG_ALLOCA_64: 12406 return EmitLoweredSegAlloca(MI, BB, true); 12407 case X86::TLSCall_32: 12408 case X86::TLSCall_64: 12409 return EmitLoweredTLSCall(MI, BB); 12410 case X86::CMOV_GR8: 12411 case X86::CMOV_FR32: 12412 case X86::CMOV_FR64: 12413 case X86::CMOV_V4F32: 12414 case X86::CMOV_V2F64: 12415 case X86::CMOV_V2I64: 12416 case X86::CMOV_V8F32: 12417 case X86::CMOV_V4F64: 12418 case X86::CMOV_V4I64: 12419 case X86::CMOV_GR16: 12420 case X86::CMOV_GR32: 12421 case X86::CMOV_RFP32: 12422 case X86::CMOV_RFP64: 12423 case X86::CMOV_RFP80: 12424 return EmitLoweredSelect(MI, BB); 12425 12426 case X86::FP32_TO_INT16_IN_MEM: 12427 case X86::FP32_TO_INT32_IN_MEM: 12428 case X86::FP32_TO_INT64_IN_MEM: 12429 case X86::FP64_TO_INT16_IN_MEM: 12430 case X86::FP64_TO_INT32_IN_MEM: 12431 case X86::FP64_TO_INT64_IN_MEM: 12432 case X86::FP80_TO_INT16_IN_MEM: 12433 case X86::FP80_TO_INT32_IN_MEM: 12434 case X86::FP80_TO_INT64_IN_MEM: { 12435 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12436 DebugLoc DL = MI->getDebugLoc(); 12437 12438 // Change the floating point control register to use "round towards zero" 12439 // mode when truncating to an integer value. 12440 MachineFunction *F = BB->getParent(); 12441 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12442 addFrameReference(BuildMI(*BB, MI, DL, 12443 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12444 12445 // Load the old value of the high byte of the control word... 12446 unsigned OldCW = 12447 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12448 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12449 CWFrameIdx); 12450 12451 // Set the high part to be round to zero... 12452 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12453 .addImm(0xC7F); 12454 12455 // Reload the modified control word now... 12456 addFrameReference(BuildMI(*BB, MI, DL, 12457 TII->get(X86::FLDCW16m)), CWFrameIdx); 12458 12459 // Restore the memory image of control word to original value 12460 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12461 .addReg(OldCW); 12462 12463 // Get the X86 opcode to use. 12464 unsigned Opc; 12465 switch (MI->getOpcode()) { 12466 default: llvm_unreachable("illegal opcode!"); 12467 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12468 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12469 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12470 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12471 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12472 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12473 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12474 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12475 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12476 } 12477 12478 X86AddressMode AM; 12479 MachineOperand &Op = MI->getOperand(0); 12480 if (Op.isReg()) { 12481 AM.BaseType = X86AddressMode::RegBase; 12482 AM.Base.Reg = Op.getReg(); 12483 } else { 12484 AM.BaseType = X86AddressMode::FrameIndexBase; 12485 AM.Base.FrameIndex = Op.getIndex(); 12486 } 12487 Op = MI->getOperand(1); 12488 if (Op.isImm()) 12489 AM.Scale = Op.getImm(); 12490 Op = MI->getOperand(2); 12491 if (Op.isImm()) 12492 AM.IndexReg = Op.getImm(); 12493 Op = MI->getOperand(3); 12494 if (Op.isGlobal()) { 12495 AM.GV = Op.getGlobal(); 12496 } else { 12497 AM.Disp = Op.getImm(); 12498 } 12499 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12500 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12501 12502 // Reload the original control word now. 12503 addFrameReference(BuildMI(*BB, MI, DL, 12504 TII->get(X86::FLDCW16m)), CWFrameIdx); 12505 12506 MI->eraseFromParent(); // The pseudo instruction is gone now. 12507 return BB; 12508 } 12509 // String/text processing lowering. 12510 case X86::PCMPISTRM128REG: 12511 case X86::VPCMPISTRM128REG: 12512 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12513 case X86::PCMPISTRM128MEM: 12514 case X86::VPCMPISTRM128MEM: 12515 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12516 case X86::PCMPESTRM128REG: 12517 case X86::VPCMPESTRM128REG: 12518 return EmitPCMP(MI, BB, 5, false /* in mem */); 12519 case X86::PCMPESTRM128MEM: 12520 case X86::VPCMPESTRM128MEM: 12521 return EmitPCMP(MI, BB, 5, true /* in mem */); 12522 12523 // Thread synchronization. 12524 case X86::MONITOR: 12525 return EmitMonitor(MI, BB); 12526 case X86::MWAIT: 12527 return EmitMwait(MI, BB); 12528 12529 // Atomic Lowering. 12530 case X86::ATOMAND32: 12531 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12532 X86::AND32ri, X86::MOV32rm, 12533 X86::LCMPXCHG32, 12534 X86::NOT32r, X86::EAX, 12535 X86::GR32RegisterClass); 12536 case X86::ATOMOR32: 12537 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12538 X86::OR32ri, X86::MOV32rm, 12539 X86::LCMPXCHG32, 12540 X86::NOT32r, X86::EAX, 12541 X86::GR32RegisterClass); 12542 case X86::ATOMXOR32: 12543 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12544 X86::XOR32ri, X86::MOV32rm, 12545 X86::LCMPXCHG32, 12546 X86::NOT32r, X86::EAX, 12547 X86::GR32RegisterClass); 12548 case X86::ATOMNAND32: 12549 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12550 X86::AND32ri, X86::MOV32rm, 12551 X86::LCMPXCHG32, 12552 X86::NOT32r, X86::EAX, 12553 X86::GR32RegisterClass, true); 12554 case X86::ATOMMIN32: 12555 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12556 case X86::ATOMMAX32: 12557 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12558 case X86::ATOMUMIN32: 12559 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12560 case X86::ATOMUMAX32: 12561 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12562 12563 case X86::ATOMAND16: 12564 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12565 X86::AND16ri, X86::MOV16rm, 12566 X86::LCMPXCHG16, 12567 X86::NOT16r, X86::AX, 12568 X86::GR16RegisterClass); 12569 case X86::ATOMOR16: 12570 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12571 X86::OR16ri, X86::MOV16rm, 12572 X86::LCMPXCHG16, 12573 X86::NOT16r, X86::AX, 12574 X86::GR16RegisterClass); 12575 case X86::ATOMXOR16: 12576 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12577 X86::XOR16ri, X86::MOV16rm, 12578 X86::LCMPXCHG16, 12579 X86::NOT16r, X86::AX, 12580 X86::GR16RegisterClass); 12581 case X86::ATOMNAND16: 12582 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12583 X86::AND16ri, X86::MOV16rm, 12584 X86::LCMPXCHG16, 12585 X86::NOT16r, X86::AX, 12586 X86::GR16RegisterClass, true); 12587 case X86::ATOMMIN16: 12588 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12589 case X86::ATOMMAX16: 12590 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12591 case X86::ATOMUMIN16: 12592 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12593 case X86::ATOMUMAX16: 12594 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12595 12596 case X86::ATOMAND8: 12597 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12598 X86::AND8ri, X86::MOV8rm, 12599 X86::LCMPXCHG8, 12600 X86::NOT8r, X86::AL, 12601 X86::GR8RegisterClass); 12602 case X86::ATOMOR8: 12603 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12604 X86::OR8ri, X86::MOV8rm, 12605 X86::LCMPXCHG8, 12606 X86::NOT8r, X86::AL, 12607 X86::GR8RegisterClass); 12608 case X86::ATOMXOR8: 12609 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12610 X86::XOR8ri, X86::MOV8rm, 12611 X86::LCMPXCHG8, 12612 X86::NOT8r, X86::AL, 12613 X86::GR8RegisterClass); 12614 case X86::ATOMNAND8: 12615 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12616 X86::AND8ri, X86::MOV8rm, 12617 X86::LCMPXCHG8, 12618 X86::NOT8r, X86::AL, 12619 X86::GR8RegisterClass, true); 12620 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12621 // This group is for 64-bit host. 12622 case X86::ATOMAND64: 12623 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12624 X86::AND64ri32, X86::MOV64rm, 12625 X86::LCMPXCHG64, 12626 X86::NOT64r, X86::RAX, 12627 X86::GR64RegisterClass); 12628 case X86::ATOMOR64: 12629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12630 X86::OR64ri32, X86::MOV64rm, 12631 X86::LCMPXCHG64, 12632 X86::NOT64r, X86::RAX, 12633 X86::GR64RegisterClass); 12634 case X86::ATOMXOR64: 12635 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12636 X86::XOR64ri32, X86::MOV64rm, 12637 X86::LCMPXCHG64, 12638 X86::NOT64r, X86::RAX, 12639 X86::GR64RegisterClass); 12640 case X86::ATOMNAND64: 12641 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12642 X86::AND64ri32, X86::MOV64rm, 12643 X86::LCMPXCHG64, 12644 X86::NOT64r, X86::RAX, 12645 X86::GR64RegisterClass, true); 12646 case X86::ATOMMIN64: 12647 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12648 case X86::ATOMMAX64: 12649 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12650 case X86::ATOMUMIN64: 12651 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12652 case X86::ATOMUMAX64: 12653 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12654 12655 // This group does 64-bit operations on a 32-bit host. 12656 case X86::ATOMAND6432: 12657 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12658 X86::AND32rr, X86::AND32rr, 12659 X86::AND32ri, X86::AND32ri, 12660 false); 12661 case X86::ATOMOR6432: 12662 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12663 X86::OR32rr, X86::OR32rr, 12664 X86::OR32ri, X86::OR32ri, 12665 false); 12666 case X86::ATOMXOR6432: 12667 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12668 X86::XOR32rr, X86::XOR32rr, 12669 X86::XOR32ri, X86::XOR32ri, 12670 false); 12671 case X86::ATOMNAND6432: 12672 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12673 X86::AND32rr, X86::AND32rr, 12674 X86::AND32ri, X86::AND32ri, 12675 true); 12676 case X86::ATOMADD6432: 12677 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12678 X86::ADD32rr, X86::ADC32rr, 12679 X86::ADD32ri, X86::ADC32ri, 12680 false); 12681 case X86::ATOMSUB6432: 12682 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12683 X86::SUB32rr, X86::SBB32rr, 12684 X86::SUB32ri, X86::SBB32ri, 12685 false); 12686 case X86::ATOMSWAP6432: 12687 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12688 X86::MOV32rr, X86::MOV32rr, 12689 X86::MOV32ri, X86::MOV32ri, 12690 false); 12691 case X86::VASTART_SAVE_XMM_REGS: 12692 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12693 12694 case X86::VAARG_64: 12695 return EmitVAARG64WithCustomInserter(MI, BB); 12696 } 12697} 12698 12699//===----------------------------------------------------------------------===// 12700// X86 Optimization Hooks 12701//===----------------------------------------------------------------------===// 12702 12703void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12704 APInt &KnownZero, 12705 APInt &KnownOne, 12706 const SelectionDAG &DAG, 12707 unsigned Depth) const { 12708 unsigned BitWidth = KnownZero.getBitWidth(); 12709 unsigned Opc = Op.getOpcode(); 12710 assert((Opc >= ISD::BUILTIN_OP_END || 12711 Opc == ISD::INTRINSIC_WO_CHAIN || 12712 Opc == ISD::INTRINSIC_W_CHAIN || 12713 Opc == ISD::INTRINSIC_VOID) && 12714 "Should use MaskedValueIsZero if you don't know whether Op" 12715 " is a target node!"); 12716 12717 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 12718 switch (Opc) { 12719 default: break; 12720 case X86ISD::ADD: 12721 case X86ISD::SUB: 12722 case X86ISD::ADC: 12723 case X86ISD::SBB: 12724 case X86ISD::SMUL: 12725 case X86ISD::UMUL: 12726 case X86ISD::INC: 12727 case X86ISD::DEC: 12728 case X86ISD::OR: 12729 case X86ISD::XOR: 12730 case X86ISD::AND: 12731 // These nodes' second result is a boolean. 12732 if (Op.getResNo() == 0) 12733 break; 12734 // Fallthrough 12735 case X86ISD::SETCC: 12736 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 12737 break; 12738 case ISD::INTRINSIC_WO_CHAIN: { 12739 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12740 unsigned NumLoBits = 0; 12741 switch (IntId) { 12742 default: break; 12743 case Intrinsic::x86_sse_movmsk_ps: 12744 case Intrinsic::x86_avx_movmsk_ps_256: 12745 case Intrinsic::x86_sse2_movmsk_pd: 12746 case Intrinsic::x86_avx_movmsk_pd_256: 12747 case Intrinsic::x86_mmx_pmovmskb: 12748 case Intrinsic::x86_sse2_pmovmskb_128: 12749 case Intrinsic::x86_avx2_pmovmskb: { 12750 // High bits of movmskp{s|d}, pmovmskb are known zero. 12751 switch (IntId) { 12752 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12753 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12754 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12755 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12756 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12757 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12758 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12759 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12760 } 12761 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 12762 break; 12763 } 12764 } 12765 break; 12766 } 12767 } 12768} 12769 12770unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12771 unsigned Depth) const { 12772 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12773 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12774 return Op.getValueType().getScalarType().getSizeInBits(); 12775 12776 // Fallback case. 12777 return 1; 12778} 12779 12780/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12781/// node is a GlobalAddress + offset. 12782bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12783 const GlobalValue* &GA, 12784 int64_t &Offset) const { 12785 if (N->getOpcode() == X86ISD::Wrapper) { 12786 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12787 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12788 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12789 return true; 12790 } 12791 } 12792 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12793} 12794 12795/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12796/// same as extracting the high 128-bit part of 256-bit vector and then 12797/// inserting the result into the low part of a new 256-bit vector 12798static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12799 EVT VT = SVOp->getValueType(0); 12800 int NumElems = VT.getVectorNumElements(); 12801 12802 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12803 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12804 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12805 SVOp->getMaskElt(j) >= 0) 12806 return false; 12807 12808 return true; 12809} 12810 12811/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12812/// same as extracting the low 128-bit part of 256-bit vector and then 12813/// inserting the result into the high part of a new 256-bit vector 12814static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12815 EVT VT = SVOp->getValueType(0); 12816 int NumElems = VT.getVectorNumElements(); 12817 12818 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12819 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12820 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12821 SVOp->getMaskElt(j) >= 0) 12822 return false; 12823 12824 return true; 12825} 12826 12827/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12828static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12829 TargetLowering::DAGCombinerInfo &DCI, 12830 const X86Subtarget* Subtarget) { 12831 DebugLoc dl = N->getDebugLoc(); 12832 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12833 SDValue V1 = SVOp->getOperand(0); 12834 SDValue V2 = SVOp->getOperand(1); 12835 EVT VT = SVOp->getValueType(0); 12836 int NumElems = VT.getVectorNumElements(); 12837 12838 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12839 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12840 // 12841 // 0,0,0,... 12842 // | 12843 // V UNDEF BUILD_VECTOR UNDEF 12844 // \ / \ / 12845 // CONCAT_VECTOR CONCAT_VECTOR 12846 // \ / 12847 // \ / 12848 // RESULT: V + zero extended 12849 // 12850 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12851 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12852 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12853 return SDValue(); 12854 12855 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12856 return SDValue(); 12857 12858 // To match the shuffle mask, the first half of the mask should 12859 // be exactly the first vector, and all the rest a splat with the 12860 // first element of the second one. 12861 for (int i = 0; i < NumElems/2; ++i) 12862 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12863 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12864 return SDValue(); 12865 12866 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12867 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12868 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12869 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12870 SDValue ResNode = 12871 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12872 Ld->getMemoryVT(), 12873 Ld->getPointerInfo(), 12874 Ld->getAlignment(), 12875 false/*isVolatile*/, true/*ReadMem*/, 12876 false/*WriteMem*/); 12877 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12878 } 12879 12880 // Emit a zeroed vector and insert the desired subvector on its 12881 // first half. 12882 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12883 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12884 DAG.getConstant(0, MVT::i32), DAG, dl); 12885 return DCI.CombineTo(N, InsV); 12886 } 12887 12888 //===--------------------------------------------------------------------===// 12889 // Combine some shuffles into subvector extracts and inserts: 12890 // 12891 12892 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12893 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12894 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12895 DAG, dl); 12896 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12897 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12898 return DCI.CombineTo(N, InsV); 12899 } 12900 12901 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12902 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12903 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12904 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12905 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12906 return DCI.CombineTo(N, InsV); 12907 } 12908 12909 return SDValue(); 12910} 12911 12912/// PerformShuffleCombine - Performs several different shuffle combines. 12913static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12914 TargetLowering::DAGCombinerInfo &DCI, 12915 const X86Subtarget *Subtarget) { 12916 DebugLoc dl = N->getDebugLoc(); 12917 EVT VT = N->getValueType(0); 12918 12919 // Don't create instructions with illegal types after legalize types has run. 12920 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12921 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12922 return SDValue(); 12923 12924 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12925 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12926 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12927 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 12928 12929 // Only handle 128 wide vector from here on. 12930 if (VT.getSizeInBits() != 128) 12931 return SDValue(); 12932 12933 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12934 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12935 // consecutive, non-overlapping, and in the right order. 12936 SmallVector<SDValue, 16> Elts; 12937 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12938 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12939 12940 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12941} 12942 12943 12944/// PerformTruncateCombine - Converts truncate operation to 12945/// a sequence of vector shuffle operations. 12946/// It is possible when we truncate 256-bit vector to 128-bit vector 12947 12948SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 12949 DAGCombinerInfo &DCI) const { 12950 if (!DCI.isBeforeLegalizeOps()) 12951 return SDValue(); 12952 12953 if (!Subtarget->hasAVX()) return SDValue(); 12954 12955 EVT VT = N->getValueType(0); 12956 SDValue Op = N->getOperand(0); 12957 EVT OpVT = Op.getValueType(); 12958 DebugLoc dl = N->getDebugLoc(); 12959 12960 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 12961 12962 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12963 DAG.getIntPtrConstant(0)); 12964 12965 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12966 DAG.getIntPtrConstant(2)); 12967 12968 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 12969 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 12970 12971 // PSHUFD 12972 int ShufMask1[] = {0, 2, 0, 0}; 12973 12974 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), 12975 ShufMask1); 12976 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), 12977 ShufMask1); 12978 12979 // MOVLHPS 12980 int ShufMask2[] = {0, 1, 4, 5}; 12981 12982 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 12983 } 12984 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 12985 12986 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12987 DAG.getIntPtrConstant(0)); 12988 12989 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12990 DAG.getIntPtrConstant(4)); 12991 12992 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 12993 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 12994 12995 // PSHUFB 12996 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 12997 -1, -1, -1, -1, -1, -1, -1, -1}; 12998 12999 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, 13000 DAG.getUNDEF(MVT::v16i8), 13001 ShufMask1); 13002 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, 13003 DAG.getUNDEF(MVT::v16i8), 13004 ShufMask1); 13005 13006 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13007 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13008 13009 // MOVLHPS 13010 int ShufMask2[] = {0, 1, 4, 5}; 13011 13012 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 13013 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 13014 } 13015 13016 return SDValue(); 13017} 13018 13019/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 13020/// specific shuffle of a load can be folded into a single element load. 13021/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 13022/// shuffles have been customed lowered so we need to handle those here. 13023static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 13024 TargetLowering::DAGCombinerInfo &DCI) { 13025 if (DCI.isBeforeLegalizeOps()) 13026 return SDValue(); 13027 13028 SDValue InVec = N->getOperand(0); 13029 SDValue EltNo = N->getOperand(1); 13030 13031 if (!isa<ConstantSDNode>(EltNo)) 13032 return SDValue(); 13033 13034 EVT VT = InVec.getValueType(); 13035 13036 bool HasShuffleIntoBitcast = false; 13037 if (InVec.getOpcode() == ISD::BITCAST) { 13038 // Don't duplicate a load with other uses. 13039 if (!InVec.hasOneUse()) 13040 return SDValue(); 13041 EVT BCVT = InVec.getOperand(0).getValueType(); 13042 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 13043 return SDValue(); 13044 InVec = InVec.getOperand(0); 13045 HasShuffleIntoBitcast = true; 13046 } 13047 13048 if (!isTargetShuffle(InVec.getOpcode())) 13049 return SDValue(); 13050 13051 // Don't duplicate a load with other uses. 13052 if (!InVec.hasOneUse()) 13053 return SDValue(); 13054 13055 SmallVector<int, 16> ShuffleMask; 13056 bool UnaryShuffle; 13057 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle)) 13058 return SDValue(); 13059 13060 // Select the input vector, guarding against out of range extract vector. 13061 unsigned NumElems = VT.getVectorNumElements(); 13062 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 13063 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 13064 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 13065 : InVec.getOperand(1); 13066 13067 // If inputs to shuffle are the same for both ops, then allow 2 uses 13068 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 13069 13070 if (LdNode.getOpcode() == ISD::BITCAST) { 13071 // Don't duplicate a load with other uses. 13072 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 13073 return SDValue(); 13074 13075 AllowedUses = 1; // only allow 1 load use if we have a bitcast 13076 LdNode = LdNode.getOperand(0); 13077 } 13078 13079 if (!ISD::isNormalLoad(LdNode.getNode())) 13080 return SDValue(); 13081 13082 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13083 13084 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13085 return SDValue(); 13086 13087 if (HasShuffleIntoBitcast) { 13088 // If there's a bitcast before the shuffle, check if the load type and 13089 // alignment is valid. 13090 unsigned Align = LN0->getAlignment(); 13091 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13092 unsigned NewAlign = TLI.getTargetData()-> 13093 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13094 13095 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13096 return SDValue(); 13097 } 13098 13099 // All checks match so transform back to vector_shuffle so that DAG combiner 13100 // can finish the job 13101 DebugLoc dl = N->getDebugLoc(); 13102 13103 // Create shuffle node taking into account the case that its a unary shuffle 13104 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13105 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13106 InVec.getOperand(0), Shuffle, 13107 &ShuffleMask[0]); 13108 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13109 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13110 EltNo); 13111} 13112 13113/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13114/// generation and convert it from being a bunch of shuffles and extracts 13115/// to a simple store and scalar loads to extract the elements. 13116static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13117 TargetLowering::DAGCombinerInfo &DCI) { 13118 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13119 if (NewOp.getNode()) 13120 return NewOp; 13121 13122 SDValue InputVector = N->getOperand(0); 13123 13124 // Only operate on vectors of 4 elements, where the alternative shuffling 13125 // gets to be more expensive. 13126 if (InputVector.getValueType() != MVT::v4i32) 13127 return SDValue(); 13128 13129 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13130 // single use which is a sign-extend or zero-extend, and all elements are 13131 // used. 13132 SmallVector<SDNode *, 4> Uses; 13133 unsigned ExtractedElements = 0; 13134 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13135 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13136 if (UI.getUse().getResNo() != InputVector.getResNo()) 13137 return SDValue(); 13138 13139 SDNode *Extract = *UI; 13140 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13141 return SDValue(); 13142 13143 if (Extract->getValueType(0) != MVT::i32) 13144 return SDValue(); 13145 if (!Extract->hasOneUse()) 13146 return SDValue(); 13147 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13148 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13149 return SDValue(); 13150 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13151 return SDValue(); 13152 13153 // Record which element was extracted. 13154 ExtractedElements |= 13155 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13156 13157 Uses.push_back(Extract); 13158 } 13159 13160 // If not all the elements were used, this may not be worthwhile. 13161 if (ExtractedElements != 15) 13162 return SDValue(); 13163 13164 // Ok, we've now decided to do the transformation. 13165 DebugLoc dl = InputVector.getDebugLoc(); 13166 13167 // Store the value to a temporary stack slot. 13168 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13169 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13170 MachinePointerInfo(), false, false, 0); 13171 13172 // Replace each use (extract) with a load of the appropriate element. 13173 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13174 UE = Uses.end(); UI != UE; ++UI) { 13175 SDNode *Extract = *UI; 13176 13177 // cOMpute the element's address. 13178 SDValue Idx = Extract->getOperand(1); 13179 unsigned EltSize = 13180 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13181 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13182 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13183 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13184 13185 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13186 StackPtr, OffsetVal); 13187 13188 // Load the scalar. 13189 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13190 ScalarAddr, MachinePointerInfo(), 13191 false, false, false, 0); 13192 13193 // Replace the exact with the load. 13194 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13195 } 13196 13197 // The replacement was made in place; don't return anything. 13198 return SDValue(); 13199} 13200 13201/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13202/// nodes. 13203static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13204 TargetLowering::DAGCombinerInfo &DCI, 13205 const X86Subtarget *Subtarget) { 13206 13207 13208 DebugLoc DL = N->getDebugLoc(); 13209 SDValue Cond = N->getOperand(0); 13210 // Get the LHS/RHS of the select. 13211 SDValue LHS = N->getOperand(1); 13212 SDValue RHS = N->getOperand(2); 13213 EVT VT = LHS.getValueType(); 13214 13215 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13216 // instructions match the semantics of the common C idiom x<y?x:y but not 13217 // x<=y?x:y, because of how they handle negative zero (which can be 13218 // ignored in unsafe-math mode). 13219 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13220 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13221 (Subtarget->hasSSE2() || 13222 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13223 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13224 13225 unsigned Opcode = 0; 13226 // Check for x CC y ? x : y. 13227 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13228 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13229 switch (CC) { 13230 default: break; 13231 case ISD::SETULT: 13232 // Converting this to a min would handle NaNs incorrectly, and swapping 13233 // the operands would cause it to handle comparisons between positive 13234 // and negative zero incorrectly. 13235 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13236 if (!DAG.getTarget().Options.UnsafeFPMath && 13237 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13238 break; 13239 std::swap(LHS, RHS); 13240 } 13241 Opcode = X86ISD::FMIN; 13242 break; 13243 case ISD::SETOLE: 13244 // Converting this to a min would handle comparisons between positive 13245 // and negative zero incorrectly. 13246 if (!DAG.getTarget().Options.UnsafeFPMath && 13247 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13248 break; 13249 Opcode = X86ISD::FMIN; 13250 break; 13251 case ISD::SETULE: 13252 // Converting this to a min would handle both negative zeros and NaNs 13253 // incorrectly, but we can swap the operands to fix both. 13254 std::swap(LHS, RHS); 13255 case ISD::SETOLT: 13256 case ISD::SETLT: 13257 case ISD::SETLE: 13258 Opcode = X86ISD::FMIN; 13259 break; 13260 13261 case ISD::SETOGE: 13262 // Converting this to a max would handle comparisons between positive 13263 // and negative zero incorrectly. 13264 if (!DAG.getTarget().Options.UnsafeFPMath && 13265 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13266 break; 13267 Opcode = X86ISD::FMAX; 13268 break; 13269 case ISD::SETUGT: 13270 // Converting this to a max would handle NaNs incorrectly, and swapping 13271 // the operands would cause it to handle comparisons between positive 13272 // and negative zero incorrectly. 13273 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13274 if (!DAG.getTarget().Options.UnsafeFPMath && 13275 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13276 break; 13277 std::swap(LHS, RHS); 13278 } 13279 Opcode = X86ISD::FMAX; 13280 break; 13281 case ISD::SETUGE: 13282 // Converting this to a max would handle both negative zeros and NaNs 13283 // incorrectly, but we can swap the operands to fix both. 13284 std::swap(LHS, RHS); 13285 case ISD::SETOGT: 13286 case ISD::SETGT: 13287 case ISD::SETGE: 13288 Opcode = X86ISD::FMAX; 13289 break; 13290 } 13291 // Check for x CC y ? y : x -- a min/max with reversed arms. 13292 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13293 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13294 switch (CC) { 13295 default: break; 13296 case ISD::SETOGE: 13297 // Converting this to a min would handle comparisons between positive 13298 // and negative zero incorrectly, and swapping the operands would 13299 // cause it to handle NaNs incorrectly. 13300 if (!DAG.getTarget().Options.UnsafeFPMath && 13301 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13302 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13303 break; 13304 std::swap(LHS, RHS); 13305 } 13306 Opcode = X86ISD::FMIN; 13307 break; 13308 case ISD::SETUGT: 13309 // Converting this to a min would handle NaNs incorrectly. 13310 if (!DAG.getTarget().Options.UnsafeFPMath && 13311 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13312 break; 13313 Opcode = X86ISD::FMIN; 13314 break; 13315 case ISD::SETUGE: 13316 // Converting this to a min would handle both negative zeros and NaNs 13317 // incorrectly, but we can swap the operands to fix both. 13318 std::swap(LHS, RHS); 13319 case ISD::SETOGT: 13320 case ISD::SETGT: 13321 case ISD::SETGE: 13322 Opcode = X86ISD::FMIN; 13323 break; 13324 13325 case ISD::SETULT: 13326 // Converting this to a max would handle NaNs incorrectly. 13327 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13328 break; 13329 Opcode = X86ISD::FMAX; 13330 break; 13331 case ISD::SETOLE: 13332 // Converting this to a max would handle comparisons between positive 13333 // and negative zero incorrectly, and swapping the operands would 13334 // cause it to handle NaNs incorrectly. 13335 if (!DAG.getTarget().Options.UnsafeFPMath && 13336 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13337 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13338 break; 13339 std::swap(LHS, RHS); 13340 } 13341 Opcode = X86ISD::FMAX; 13342 break; 13343 case ISD::SETULE: 13344 // Converting this to a max would handle both negative zeros and NaNs 13345 // incorrectly, but we can swap the operands to fix both. 13346 std::swap(LHS, RHS); 13347 case ISD::SETOLT: 13348 case ISD::SETLT: 13349 case ISD::SETLE: 13350 Opcode = X86ISD::FMAX; 13351 break; 13352 } 13353 } 13354 13355 if (Opcode) 13356 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13357 } 13358 13359 // If this is a select between two integer constants, try to do some 13360 // optimizations. 13361 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13362 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13363 // Don't do this for crazy integer types. 13364 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13365 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13366 // so that TrueC (the true value) is larger than FalseC. 13367 bool NeedsCondInvert = false; 13368 13369 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13370 // Efficiently invertible. 13371 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13372 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13373 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13374 NeedsCondInvert = true; 13375 std::swap(TrueC, FalseC); 13376 } 13377 13378 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13379 if (FalseC->getAPIntValue() == 0 && 13380 TrueC->getAPIntValue().isPowerOf2()) { 13381 if (NeedsCondInvert) // Invert the condition if needed. 13382 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13383 DAG.getConstant(1, Cond.getValueType())); 13384 13385 // Zero extend the condition if needed. 13386 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13387 13388 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13389 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13390 DAG.getConstant(ShAmt, MVT::i8)); 13391 } 13392 13393 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13394 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13395 if (NeedsCondInvert) // Invert the condition if needed. 13396 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13397 DAG.getConstant(1, Cond.getValueType())); 13398 13399 // Zero extend the condition if needed. 13400 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13401 FalseC->getValueType(0), Cond); 13402 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13403 SDValue(FalseC, 0)); 13404 } 13405 13406 // Optimize cases that will turn into an LEA instruction. This requires 13407 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13408 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13409 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13410 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13411 13412 bool isFastMultiplier = false; 13413 if (Diff < 10) { 13414 switch ((unsigned char)Diff) { 13415 default: break; 13416 case 1: // result = add base, cond 13417 case 2: // result = lea base( , cond*2) 13418 case 3: // result = lea base(cond, cond*2) 13419 case 4: // result = lea base( , cond*4) 13420 case 5: // result = lea base(cond, cond*4) 13421 case 8: // result = lea base( , cond*8) 13422 case 9: // result = lea base(cond, cond*8) 13423 isFastMultiplier = true; 13424 break; 13425 } 13426 } 13427 13428 if (isFastMultiplier) { 13429 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13430 if (NeedsCondInvert) // Invert the condition if needed. 13431 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13432 DAG.getConstant(1, Cond.getValueType())); 13433 13434 // Zero extend the condition if needed. 13435 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13436 Cond); 13437 // Scale the condition by the difference. 13438 if (Diff != 1) 13439 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13440 DAG.getConstant(Diff, Cond.getValueType())); 13441 13442 // Add the base if non-zero. 13443 if (FalseC->getAPIntValue() != 0) 13444 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13445 SDValue(FalseC, 0)); 13446 return Cond; 13447 } 13448 } 13449 } 13450 } 13451 13452 // Canonicalize max and min: 13453 // (x > y) ? x : y -> (x >= y) ? x : y 13454 // (x < y) ? x : y -> (x <= y) ? x : y 13455 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13456 // the need for an extra compare 13457 // against zero. e.g. 13458 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13459 // subl %esi, %edi 13460 // testl %edi, %edi 13461 // movl $0, %eax 13462 // cmovgl %edi, %eax 13463 // => 13464 // xorl %eax, %eax 13465 // subl %esi, $edi 13466 // cmovsl %eax, %edi 13467 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13468 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13469 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13470 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13471 switch (CC) { 13472 default: break; 13473 case ISD::SETLT: 13474 case ISD::SETGT: { 13475 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13476 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13477 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13478 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13479 } 13480 } 13481 } 13482 13483 // If we know that this node is legal then we know that it is going to be 13484 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13485 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13486 // to simplify previous instructions. 13487 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13488 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13489 !DCI.isBeforeLegalize() && 13490 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13491 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13492 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13493 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13494 13495 APInt KnownZero, KnownOne; 13496 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13497 DCI.isBeforeLegalizeOps()); 13498 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13499 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13500 DCI.CommitTargetLoweringOpt(TLO); 13501 } 13502 13503 return SDValue(); 13504} 13505 13506/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13507static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13508 TargetLowering::DAGCombinerInfo &DCI) { 13509 DebugLoc DL = N->getDebugLoc(); 13510 13511 // If the flag operand isn't dead, don't touch this CMOV. 13512 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13513 return SDValue(); 13514 13515 SDValue FalseOp = N->getOperand(0); 13516 SDValue TrueOp = N->getOperand(1); 13517 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13518 SDValue Cond = N->getOperand(3); 13519 if (CC == X86::COND_E || CC == X86::COND_NE) { 13520 switch (Cond.getOpcode()) { 13521 default: break; 13522 case X86ISD::BSR: 13523 case X86ISD::BSF: 13524 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13525 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13526 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13527 } 13528 } 13529 13530 // If this is a select between two integer constants, try to do some 13531 // optimizations. Note that the operands are ordered the opposite of SELECT 13532 // operands. 13533 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13534 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13535 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13536 // larger than FalseC (the false value). 13537 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13538 CC = X86::GetOppositeBranchCondition(CC); 13539 std::swap(TrueC, FalseC); 13540 } 13541 13542 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13543 // This is efficient for any integer data type (including i8/i16) and 13544 // shift amount. 13545 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13546 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13547 DAG.getConstant(CC, MVT::i8), Cond); 13548 13549 // Zero extend the condition if needed. 13550 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13551 13552 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13553 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13554 DAG.getConstant(ShAmt, MVT::i8)); 13555 if (N->getNumValues() == 2) // Dead flag value? 13556 return DCI.CombineTo(N, Cond, SDValue()); 13557 return Cond; 13558 } 13559 13560 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13561 // for any integer data type, including i8/i16. 13562 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13563 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13564 DAG.getConstant(CC, MVT::i8), Cond); 13565 13566 // Zero extend the condition if needed. 13567 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13568 FalseC->getValueType(0), Cond); 13569 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13570 SDValue(FalseC, 0)); 13571 13572 if (N->getNumValues() == 2) // Dead flag value? 13573 return DCI.CombineTo(N, Cond, SDValue()); 13574 return Cond; 13575 } 13576 13577 // Optimize cases that will turn into an LEA instruction. This requires 13578 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13579 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13580 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13581 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13582 13583 bool isFastMultiplier = false; 13584 if (Diff < 10) { 13585 switch ((unsigned char)Diff) { 13586 default: break; 13587 case 1: // result = add base, cond 13588 case 2: // result = lea base( , cond*2) 13589 case 3: // result = lea base(cond, cond*2) 13590 case 4: // result = lea base( , cond*4) 13591 case 5: // result = lea base(cond, cond*4) 13592 case 8: // result = lea base( , cond*8) 13593 case 9: // result = lea base(cond, cond*8) 13594 isFastMultiplier = true; 13595 break; 13596 } 13597 } 13598 13599 if (isFastMultiplier) { 13600 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13601 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13602 DAG.getConstant(CC, MVT::i8), Cond); 13603 // Zero extend the condition if needed. 13604 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13605 Cond); 13606 // Scale the condition by the difference. 13607 if (Diff != 1) 13608 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13609 DAG.getConstant(Diff, Cond.getValueType())); 13610 13611 // Add the base if non-zero. 13612 if (FalseC->getAPIntValue() != 0) 13613 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13614 SDValue(FalseC, 0)); 13615 if (N->getNumValues() == 2) // Dead flag value? 13616 return DCI.CombineTo(N, Cond, SDValue()); 13617 return Cond; 13618 } 13619 } 13620 } 13621 } 13622 return SDValue(); 13623} 13624 13625 13626/// PerformMulCombine - Optimize a single multiply with constant into two 13627/// in order to implement it with two cheaper instructions, e.g. 13628/// LEA + SHL, LEA + LEA. 13629static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13630 TargetLowering::DAGCombinerInfo &DCI) { 13631 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13632 return SDValue(); 13633 13634 EVT VT = N->getValueType(0); 13635 if (VT != MVT::i64) 13636 return SDValue(); 13637 13638 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13639 if (!C) 13640 return SDValue(); 13641 uint64_t MulAmt = C->getZExtValue(); 13642 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13643 return SDValue(); 13644 13645 uint64_t MulAmt1 = 0; 13646 uint64_t MulAmt2 = 0; 13647 if ((MulAmt % 9) == 0) { 13648 MulAmt1 = 9; 13649 MulAmt2 = MulAmt / 9; 13650 } else if ((MulAmt % 5) == 0) { 13651 MulAmt1 = 5; 13652 MulAmt2 = MulAmt / 5; 13653 } else if ((MulAmt % 3) == 0) { 13654 MulAmt1 = 3; 13655 MulAmt2 = MulAmt / 3; 13656 } 13657 if (MulAmt2 && 13658 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13659 DebugLoc DL = N->getDebugLoc(); 13660 13661 if (isPowerOf2_64(MulAmt2) && 13662 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13663 // If second multiplifer is pow2, issue it first. We want the multiply by 13664 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13665 // is an add. 13666 std::swap(MulAmt1, MulAmt2); 13667 13668 SDValue NewMul; 13669 if (isPowerOf2_64(MulAmt1)) 13670 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13671 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13672 else 13673 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13674 DAG.getConstant(MulAmt1, VT)); 13675 13676 if (isPowerOf2_64(MulAmt2)) 13677 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13678 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13679 else 13680 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13681 DAG.getConstant(MulAmt2, VT)); 13682 13683 // Do not add new nodes to DAG combiner worklist. 13684 DCI.CombineTo(N, NewMul, false); 13685 } 13686 return SDValue(); 13687} 13688 13689static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13690 SDValue N0 = N->getOperand(0); 13691 SDValue N1 = N->getOperand(1); 13692 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13693 EVT VT = N0.getValueType(); 13694 13695 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13696 // since the result of setcc_c is all zero's or all ones. 13697 if (VT.isInteger() && !VT.isVector() && 13698 N1C && N0.getOpcode() == ISD::AND && 13699 N0.getOperand(1).getOpcode() == ISD::Constant) { 13700 SDValue N00 = N0.getOperand(0); 13701 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13702 ((N00.getOpcode() == ISD::ANY_EXTEND || 13703 N00.getOpcode() == ISD::ZERO_EXTEND) && 13704 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13705 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13706 APInt ShAmt = N1C->getAPIntValue(); 13707 Mask = Mask.shl(ShAmt); 13708 if (Mask != 0) 13709 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13710 N00, DAG.getConstant(Mask, VT)); 13711 } 13712 } 13713 13714 13715 // Hardware support for vector shifts is sparse which makes us scalarize the 13716 // vector operations in many cases. Also, on sandybridge ADD is faster than 13717 // shl. 13718 // (shl V, 1) -> add V,V 13719 if (isSplatVector(N1.getNode())) { 13720 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13721 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13722 // We shift all of the values by one. In many cases we do not have 13723 // hardware support for this operation. This is better expressed as an ADD 13724 // of two values. 13725 if (N1C && (1 == N1C->getZExtValue())) { 13726 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13727 } 13728 } 13729 13730 return SDValue(); 13731} 13732 13733/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13734/// when possible. 13735static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13736 TargetLowering::DAGCombinerInfo &DCI, 13737 const X86Subtarget *Subtarget) { 13738 EVT VT = N->getValueType(0); 13739 if (N->getOpcode() == ISD::SHL) { 13740 SDValue V = PerformSHLCombine(N, DAG); 13741 if (V.getNode()) return V; 13742 } 13743 13744 // On X86 with SSE2 support, we can transform this to a vector shift if 13745 // all elements are shifted by the same amount. We can't do this in legalize 13746 // because the a constant vector is typically transformed to a constant pool 13747 // so we have no knowledge of the shift amount. 13748 if (!Subtarget->hasSSE2()) 13749 return SDValue(); 13750 13751 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13752 (!Subtarget->hasAVX2() || 13753 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13754 return SDValue(); 13755 13756 SDValue ShAmtOp = N->getOperand(1); 13757 EVT EltVT = VT.getVectorElementType(); 13758 DebugLoc DL = N->getDebugLoc(); 13759 SDValue BaseShAmt = SDValue(); 13760 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13761 unsigned NumElts = VT.getVectorNumElements(); 13762 unsigned i = 0; 13763 for (; i != NumElts; ++i) { 13764 SDValue Arg = ShAmtOp.getOperand(i); 13765 if (Arg.getOpcode() == ISD::UNDEF) continue; 13766 BaseShAmt = Arg; 13767 break; 13768 } 13769 // Handle the case where the build_vector is all undef 13770 // FIXME: Should DAG allow this? 13771 if (i == NumElts) 13772 return SDValue(); 13773 13774 for (; i != NumElts; ++i) { 13775 SDValue Arg = ShAmtOp.getOperand(i); 13776 if (Arg.getOpcode() == ISD::UNDEF) continue; 13777 if (Arg != BaseShAmt) { 13778 return SDValue(); 13779 } 13780 } 13781 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13782 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13783 SDValue InVec = ShAmtOp.getOperand(0); 13784 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13785 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13786 unsigned i = 0; 13787 for (; i != NumElts; ++i) { 13788 SDValue Arg = InVec.getOperand(i); 13789 if (Arg.getOpcode() == ISD::UNDEF) continue; 13790 BaseShAmt = Arg; 13791 break; 13792 } 13793 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13794 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13795 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13796 if (C->getZExtValue() == SplatIdx) 13797 BaseShAmt = InVec.getOperand(1); 13798 } 13799 } 13800 if (BaseShAmt.getNode() == 0) { 13801 // Don't create instructions with illegal types after legalize 13802 // types has run. 13803 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 13804 !DCI.isBeforeLegalize()) 13805 return SDValue(); 13806 13807 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13808 DAG.getIntPtrConstant(0)); 13809 } 13810 } else 13811 return SDValue(); 13812 13813 // The shift amount is an i32. 13814 if (EltVT.bitsGT(MVT::i32)) 13815 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13816 else if (EltVT.bitsLT(MVT::i32)) 13817 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13818 13819 // The shift amount is identical so we can do a vector shift. 13820 SDValue ValOp = N->getOperand(0); 13821 switch (N->getOpcode()) { 13822 default: 13823 llvm_unreachable("Unknown shift opcode!"); 13824 case ISD::SHL: 13825 switch (VT.getSimpleVT().SimpleTy) { 13826 default: return SDValue(); 13827 case MVT::v2i64: 13828 case MVT::v4i32: 13829 case MVT::v8i16: 13830 case MVT::v4i64: 13831 case MVT::v8i32: 13832 case MVT::v16i16: 13833 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 13834 } 13835 case ISD::SRA: 13836 switch (VT.getSimpleVT().SimpleTy) { 13837 default: return SDValue(); 13838 case MVT::v4i32: 13839 case MVT::v8i16: 13840 case MVT::v8i32: 13841 case MVT::v16i16: 13842 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 13843 } 13844 case ISD::SRL: 13845 switch (VT.getSimpleVT().SimpleTy) { 13846 default: return SDValue(); 13847 case MVT::v2i64: 13848 case MVT::v4i32: 13849 case MVT::v8i16: 13850 case MVT::v4i64: 13851 case MVT::v8i32: 13852 case MVT::v16i16: 13853 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 13854 } 13855 } 13856} 13857 13858 13859// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13860// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13861// and friends. Likewise for OR -> CMPNEQSS. 13862static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13863 TargetLowering::DAGCombinerInfo &DCI, 13864 const X86Subtarget *Subtarget) { 13865 unsigned opcode; 13866 13867 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13868 // we're requiring SSE2 for both. 13869 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13870 SDValue N0 = N->getOperand(0); 13871 SDValue N1 = N->getOperand(1); 13872 SDValue CMP0 = N0->getOperand(1); 13873 SDValue CMP1 = N1->getOperand(1); 13874 DebugLoc DL = N->getDebugLoc(); 13875 13876 // The SETCCs should both refer to the same CMP. 13877 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13878 return SDValue(); 13879 13880 SDValue CMP00 = CMP0->getOperand(0); 13881 SDValue CMP01 = CMP0->getOperand(1); 13882 EVT VT = CMP00.getValueType(); 13883 13884 if (VT == MVT::f32 || VT == MVT::f64) { 13885 bool ExpectingFlags = false; 13886 // Check for any users that want flags: 13887 for (SDNode::use_iterator UI = N->use_begin(), 13888 UE = N->use_end(); 13889 !ExpectingFlags && UI != UE; ++UI) 13890 switch (UI->getOpcode()) { 13891 default: 13892 case ISD::BR_CC: 13893 case ISD::BRCOND: 13894 case ISD::SELECT: 13895 ExpectingFlags = true; 13896 break; 13897 case ISD::CopyToReg: 13898 case ISD::SIGN_EXTEND: 13899 case ISD::ZERO_EXTEND: 13900 case ISD::ANY_EXTEND: 13901 break; 13902 } 13903 13904 if (!ExpectingFlags) { 13905 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13906 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13907 13908 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13909 X86::CondCode tmp = cc0; 13910 cc0 = cc1; 13911 cc1 = tmp; 13912 } 13913 13914 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13915 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13916 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13917 X86ISD::NodeType NTOperator = is64BitFP ? 13918 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13919 // FIXME: need symbolic constants for these magic numbers. 13920 // See X86ATTInstPrinter.cpp:printSSECC(). 13921 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13922 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13923 DAG.getConstant(x86cc, MVT::i8)); 13924 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13925 OnesOrZeroesF); 13926 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13927 DAG.getConstant(1, MVT::i32)); 13928 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13929 return OneBitOfTruth; 13930 } 13931 } 13932 } 13933 } 13934 return SDValue(); 13935} 13936 13937/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13938/// so it can be folded inside ANDNP. 13939static bool CanFoldXORWithAllOnes(const SDNode *N) { 13940 EVT VT = N->getValueType(0); 13941 13942 // Match direct AllOnes for 128 and 256-bit vectors 13943 if (ISD::isBuildVectorAllOnes(N)) 13944 return true; 13945 13946 // Look through a bit convert. 13947 if (N->getOpcode() == ISD::BITCAST) 13948 N = N->getOperand(0).getNode(); 13949 13950 // Sometimes the operand may come from a insert_subvector building a 256-bit 13951 // allones vector 13952 if (VT.getSizeInBits() == 256 && 13953 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13954 SDValue V1 = N->getOperand(0); 13955 SDValue V2 = N->getOperand(1); 13956 13957 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13958 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13959 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13960 ISD::isBuildVectorAllOnes(V2.getNode())) 13961 return true; 13962 } 13963 13964 return false; 13965} 13966 13967static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13968 TargetLowering::DAGCombinerInfo &DCI, 13969 const X86Subtarget *Subtarget) { 13970 if (DCI.isBeforeLegalizeOps()) 13971 return SDValue(); 13972 13973 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13974 if (R.getNode()) 13975 return R; 13976 13977 EVT VT = N->getValueType(0); 13978 13979 // Create ANDN, BLSI, and BLSR instructions 13980 // BLSI is X & (-X) 13981 // BLSR is X & (X-1) 13982 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13983 SDValue N0 = N->getOperand(0); 13984 SDValue N1 = N->getOperand(1); 13985 DebugLoc DL = N->getDebugLoc(); 13986 13987 // Check LHS for not 13988 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13989 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13990 // Check RHS for not 13991 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13992 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13993 13994 // Check LHS for neg 13995 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13996 isZero(N0.getOperand(0))) 13997 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13998 13999 // Check RHS for neg 14000 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 14001 isZero(N1.getOperand(0))) 14002 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 14003 14004 // Check LHS for X-1 14005 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14006 isAllOnes(N0.getOperand(1))) 14007 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 14008 14009 // Check RHS for X-1 14010 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14011 isAllOnes(N1.getOperand(1))) 14012 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 14013 14014 return SDValue(); 14015 } 14016 14017 // Want to form ANDNP nodes: 14018 // 1) In the hopes of then easily combining them with OR and AND nodes 14019 // to form PBLEND/PSIGN. 14020 // 2) To match ANDN packed intrinsics 14021 if (VT != MVT::v2i64 && VT != MVT::v4i64) 14022 return SDValue(); 14023 14024 SDValue N0 = N->getOperand(0); 14025 SDValue N1 = N->getOperand(1); 14026 DebugLoc DL = N->getDebugLoc(); 14027 14028 // Check LHS for vnot 14029 if (N0.getOpcode() == ISD::XOR && 14030 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 14031 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 14032 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 14033 14034 // Check RHS for vnot 14035 if (N1.getOpcode() == ISD::XOR && 14036 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 14037 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 14038 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 14039 14040 return SDValue(); 14041} 14042 14043static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14044 TargetLowering::DAGCombinerInfo &DCI, 14045 const X86Subtarget *Subtarget) { 14046 if (DCI.isBeforeLegalizeOps()) 14047 return SDValue(); 14048 14049 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14050 if (R.getNode()) 14051 return R; 14052 14053 EVT VT = N->getValueType(0); 14054 14055 SDValue N0 = N->getOperand(0); 14056 SDValue N1 = N->getOperand(1); 14057 14058 // look for psign/blend 14059 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14060 if (!Subtarget->hasSSSE3() || 14061 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14062 return SDValue(); 14063 14064 // Canonicalize pandn to RHS 14065 if (N0.getOpcode() == X86ISD::ANDNP) 14066 std::swap(N0, N1); 14067 // or (and (m, y), (pandn m, x)) 14068 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14069 SDValue Mask = N1.getOperand(0); 14070 SDValue X = N1.getOperand(1); 14071 SDValue Y; 14072 if (N0.getOperand(0) == Mask) 14073 Y = N0.getOperand(1); 14074 if (N0.getOperand(1) == Mask) 14075 Y = N0.getOperand(0); 14076 14077 // Check to see if the mask appeared in both the AND and ANDNP and 14078 if (!Y.getNode()) 14079 return SDValue(); 14080 14081 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14082 // Look through mask bitcast. 14083 if (Mask.getOpcode() == ISD::BITCAST) 14084 Mask = Mask.getOperand(0); 14085 if (X.getOpcode() == ISD::BITCAST) 14086 X = X.getOperand(0); 14087 if (Y.getOpcode() == ISD::BITCAST) 14088 Y = Y.getOperand(0); 14089 14090 EVT MaskVT = Mask.getValueType(); 14091 14092 // Validate that the Mask operand is a vector sra node. 14093 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14094 // there is no psrai.b 14095 if (Mask.getOpcode() != X86ISD::VSRAI) 14096 return SDValue(); 14097 14098 // Check that the SRA is all signbits. 14099 SDValue SraC = Mask.getOperand(1); 14100 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14101 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14102 if ((SraAmt + 1) != EltBits) 14103 return SDValue(); 14104 14105 DebugLoc DL = N->getDebugLoc(); 14106 14107 // Now we know we at least have a plendvb with the mask val. See if 14108 // we can form a psignb/w/d. 14109 // psign = x.type == y.type == mask.type && y = sub(0, x); 14110 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14111 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14112 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14113 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14114 "Unsupported VT for PSIGN"); 14115 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14116 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14117 } 14118 // PBLENDVB only available on SSE 4.1 14119 if (!Subtarget->hasSSE41()) 14120 return SDValue(); 14121 14122 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14123 14124 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14125 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14126 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14127 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14128 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14129 } 14130 } 14131 14132 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14133 return SDValue(); 14134 14135 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14136 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14137 std::swap(N0, N1); 14138 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14139 return SDValue(); 14140 if (!N0.hasOneUse() || !N1.hasOneUse()) 14141 return SDValue(); 14142 14143 SDValue ShAmt0 = N0.getOperand(1); 14144 if (ShAmt0.getValueType() != MVT::i8) 14145 return SDValue(); 14146 SDValue ShAmt1 = N1.getOperand(1); 14147 if (ShAmt1.getValueType() != MVT::i8) 14148 return SDValue(); 14149 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14150 ShAmt0 = ShAmt0.getOperand(0); 14151 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14152 ShAmt1 = ShAmt1.getOperand(0); 14153 14154 DebugLoc DL = N->getDebugLoc(); 14155 unsigned Opc = X86ISD::SHLD; 14156 SDValue Op0 = N0.getOperand(0); 14157 SDValue Op1 = N1.getOperand(0); 14158 if (ShAmt0.getOpcode() == ISD::SUB) { 14159 Opc = X86ISD::SHRD; 14160 std::swap(Op0, Op1); 14161 std::swap(ShAmt0, ShAmt1); 14162 } 14163 14164 unsigned Bits = VT.getSizeInBits(); 14165 if (ShAmt1.getOpcode() == ISD::SUB) { 14166 SDValue Sum = ShAmt1.getOperand(0); 14167 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14168 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14169 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14170 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14171 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14172 return DAG.getNode(Opc, DL, VT, 14173 Op0, Op1, 14174 DAG.getNode(ISD::TRUNCATE, DL, 14175 MVT::i8, ShAmt0)); 14176 } 14177 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14178 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14179 if (ShAmt0C && 14180 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14181 return DAG.getNode(Opc, DL, VT, 14182 N0.getOperand(0), N1.getOperand(0), 14183 DAG.getNode(ISD::TRUNCATE, DL, 14184 MVT::i8, ShAmt0)); 14185 } 14186 14187 return SDValue(); 14188} 14189 14190// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14191static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14192 TargetLowering::DAGCombinerInfo &DCI, 14193 const X86Subtarget *Subtarget) { 14194 if (DCI.isBeforeLegalizeOps()) 14195 return SDValue(); 14196 14197 EVT VT = N->getValueType(0); 14198 14199 if (VT != MVT::i32 && VT != MVT::i64) 14200 return SDValue(); 14201 14202 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14203 14204 // Create BLSMSK instructions by finding X ^ (X-1) 14205 SDValue N0 = N->getOperand(0); 14206 SDValue N1 = N->getOperand(1); 14207 DebugLoc DL = N->getDebugLoc(); 14208 14209 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14210 isAllOnes(N0.getOperand(1))) 14211 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14212 14213 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14214 isAllOnes(N1.getOperand(1))) 14215 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14216 14217 return SDValue(); 14218} 14219 14220/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14221static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14222 const X86Subtarget *Subtarget) { 14223 LoadSDNode *Ld = cast<LoadSDNode>(N); 14224 EVT RegVT = Ld->getValueType(0); 14225 EVT MemVT = Ld->getMemoryVT(); 14226 DebugLoc dl = Ld->getDebugLoc(); 14227 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14228 14229 ISD::LoadExtType Ext = Ld->getExtensionType(); 14230 14231 // If this is a vector EXT Load then attempt to optimize it using a 14232 // shuffle. We need SSE4 for the shuffles. 14233 // TODO: It is possible to support ZExt by zeroing the undef values 14234 // during the shuffle phase or after the shuffle. 14235 if (RegVT.isVector() && RegVT.isInteger() && 14236 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14237 assert(MemVT != RegVT && "Cannot extend to the same type"); 14238 assert(MemVT.isVector() && "Must load a vector from memory"); 14239 14240 unsigned NumElems = RegVT.getVectorNumElements(); 14241 unsigned RegSz = RegVT.getSizeInBits(); 14242 unsigned MemSz = MemVT.getSizeInBits(); 14243 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14244 // All sizes must be a power of two 14245 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14246 14247 // Attempt to load the original value using a single load op. 14248 // Find a scalar type which is equal to the loaded word size. 14249 MVT SclrLoadTy = MVT::i8; 14250 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14251 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14252 MVT Tp = (MVT::SimpleValueType)tp; 14253 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14254 SclrLoadTy = Tp; 14255 break; 14256 } 14257 } 14258 14259 // Proceed if a load word is found. 14260 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14261 14262 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14263 RegSz/SclrLoadTy.getSizeInBits()); 14264 14265 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14266 RegSz/MemVT.getScalarType().getSizeInBits()); 14267 // Can't shuffle using an illegal type. 14268 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14269 14270 // Perform a single load. 14271 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14272 Ld->getBasePtr(), 14273 Ld->getPointerInfo(), Ld->isVolatile(), 14274 Ld->isNonTemporal(), Ld->isInvariant(), 14275 Ld->getAlignment()); 14276 14277 // Insert the word loaded into a vector. 14278 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14279 LoadUnitVecVT, ScalarLoad); 14280 14281 // Bitcast the loaded value to a vector of the original element type, in 14282 // the size of the target vector type. 14283 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14284 ScalarInVector); 14285 unsigned SizeRatio = RegSz/MemSz; 14286 14287 // Redistribute the loaded elements into the different locations. 14288 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14289 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14290 14291 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14292 DAG.getUNDEF(SlicedVec.getValueType()), 14293 ShuffleVec.data()); 14294 14295 // Bitcast to the requested type. 14296 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14297 // Replace the original load with the new sequence 14298 // and return the new chain. 14299 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14300 return SDValue(ScalarLoad.getNode(), 1); 14301 } 14302 14303 return SDValue(); 14304} 14305 14306/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14307static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14308 const X86Subtarget *Subtarget) { 14309 StoreSDNode *St = cast<StoreSDNode>(N); 14310 EVT VT = St->getValue().getValueType(); 14311 EVT StVT = St->getMemoryVT(); 14312 DebugLoc dl = St->getDebugLoc(); 14313 SDValue StoredVal = St->getOperand(1); 14314 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14315 14316 // If we are saving a concatenation of two XMM registers, perform two stores. 14317 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14318 // 128-bit ones. If in the future the cost becomes only one memory access the 14319 // first version would be better. 14320 if (VT.getSizeInBits() == 256 && 14321 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14322 StoredVal.getNumOperands() == 2) { 14323 14324 SDValue Value0 = StoredVal.getOperand(0); 14325 SDValue Value1 = StoredVal.getOperand(1); 14326 14327 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14328 SDValue Ptr0 = St->getBasePtr(); 14329 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14330 14331 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14332 St->getPointerInfo(), St->isVolatile(), 14333 St->isNonTemporal(), St->getAlignment()); 14334 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14335 St->getPointerInfo(), St->isVolatile(), 14336 St->isNonTemporal(), St->getAlignment()); 14337 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14338 } 14339 14340 // Optimize trunc store (of multiple scalars) to shuffle and store. 14341 // First, pack all of the elements in one place. Next, store to memory 14342 // in fewer chunks. 14343 if (St->isTruncatingStore() && VT.isVector()) { 14344 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14345 unsigned NumElems = VT.getVectorNumElements(); 14346 assert(StVT != VT && "Cannot truncate to the same type"); 14347 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14348 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14349 14350 // From, To sizes and ElemCount must be pow of two 14351 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14352 // We are going to use the original vector elt for storing. 14353 // Accumulated smaller vector elements must be a multiple of the store size. 14354 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14355 14356 unsigned SizeRatio = FromSz / ToSz; 14357 14358 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14359 14360 // Create a type on which we perform the shuffle 14361 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14362 StVT.getScalarType(), NumElems*SizeRatio); 14363 14364 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14365 14366 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14367 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14368 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14369 14370 // Can't shuffle using an illegal type 14371 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14372 14373 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14374 DAG.getUNDEF(WideVec.getValueType()), 14375 ShuffleVec.data()); 14376 // At this point all of the data is stored at the bottom of the 14377 // register. We now need to save it to mem. 14378 14379 // Find the largest store unit 14380 MVT StoreType = MVT::i8; 14381 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14382 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14383 MVT Tp = (MVT::SimpleValueType)tp; 14384 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14385 StoreType = Tp; 14386 } 14387 14388 // Bitcast the original vector into a vector of store-size units 14389 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14390 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14391 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14392 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14393 SmallVector<SDValue, 8> Chains; 14394 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14395 TLI.getPointerTy()); 14396 SDValue Ptr = St->getBasePtr(); 14397 14398 // Perform one or more big stores into memory. 14399 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14400 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14401 StoreType, ShuffWide, 14402 DAG.getIntPtrConstant(i)); 14403 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14404 St->getPointerInfo(), St->isVolatile(), 14405 St->isNonTemporal(), St->getAlignment()); 14406 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14407 Chains.push_back(Ch); 14408 } 14409 14410 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14411 Chains.size()); 14412 } 14413 14414 14415 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14416 // the FP state in cases where an emms may be missing. 14417 // A preferable solution to the general problem is to figure out the right 14418 // places to insert EMMS. This qualifies as a quick hack. 14419 14420 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14421 if (VT.getSizeInBits() != 64) 14422 return SDValue(); 14423 14424 const Function *F = DAG.getMachineFunction().getFunction(); 14425 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14426 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14427 && Subtarget->hasSSE2(); 14428 if ((VT.isVector() || 14429 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14430 isa<LoadSDNode>(St->getValue()) && 14431 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14432 St->getChain().hasOneUse() && !St->isVolatile()) { 14433 SDNode* LdVal = St->getValue().getNode(); 14434 LoadSDNode *Ld = 0; 14435 int TokenFactorIndex = -1; 14436 SmallVector<SDValue, 8> Ops; 14437 SDNode* ChainVal = St->getChain().getNode(); 14438 // Must be a store of a load. We currently handle two cases: the load 14439 // is a direct child, and it's under an intervening TokenFactor. It is 14440 // possible to dig deeper under nested TokenFactors. 14441 if (ChainVal == LdVal) 14442 Ld = cast<LoadSDNode>(St->getChain()); 14443 else if (St->getValue().hasOneUse() && 14444 ChainVal->getOpcode() == ISD::TokenFactor) { 14445 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14446 if (ChainVal->getOperand(i).getNode() == LdVal) { 14447 TokenFactorIndex = i; 14448 Ld = cast<LoadSDNode>(St->getValue()); 14449 } else 14450 Ops.push_back(ChainVal->getOperand(i)); 14451 } 14452 } 14453 14454 if (!Ld || !ISD::isNormalLoad(Ld)) 14455 return SDValue(); 14456 14457 // If this is not the MMX case, i.e. we are just turning i64 load/store 14458 // into f64 load/store, avoid the transformation if there are multiple 14459 // uses of the loaded value. 14460 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14461 return SDValue(); 14462 14463 DebugLoc LdDL = Ld->getDebugLoc(); 14464 DebugLoc StDL = N->getDebugLoc(); 14465 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14466 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14467 // pair instead. 14468 if (Subtarget->is64Bit() || F64IsLegal) { 14469 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14470 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14471 Ld->getPointerInfo(), Ld->isVolatile(), 14472 Ld->isNonTemporal(), Ld->isInvariant(), 14473 Ld->getAlignment()); 14474 SDValue NewChain = NewLd.getValue(1); 14475 if (TokenFactorIndex != -1) { 14476 Ops.push_back(NewChain); 14477 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14478 Ops.size()); 14479 } 14480 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14481 St->getPointerInfo(), 14482 St->isVolatile(), St->isNonTemporal(), 14483 St->getAlignment()); 14484 } 14485 14486 // Otherwise, lower to two pairs of 32-bit loads / stores. 14487 SDValue LoAddr = Ld->getBasePtr(); 14488 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14489 DAG.getConstant(4, MVT::i32)); 14490 14491 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14492 Ld->getPointerInfo(), 14493 Ld->isVolatile(), Ld->isNonTemporal(), 14494 Ld->isInvariant(), Ld->getAlignment()); 14495 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14496 Ld->getPointerInfo().getWithOffset(4), 14497 Ld->isVolatile(), Ld->isNonTemporal(), 14498 Ld->isInvariant(), 14499 MinAlign(Ld->getAlignment(), 4)); 14500 14501 SDValue NewChain = LoLd.getValue(1); 14502 if (TokenFactorIndex != -1) { 14503 Ops.push_back(LoLd); 14504 Ops.push_back(HiLd); 14505 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14506 Ops.size()); 14507 } 14508 14509 LoAddr = St->getBasePtr(); 14510 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14511 DAG.getConstant(4, MVT::i32)); 14512 14513 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14514 St->getPointerInfo(), 14515 St->isVolatile(), St->isNonTemporal(), 14516 St->getAlignment()); 14517 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14518 St->getPointerInfo().getWithOffset(4), 14519 St->isVolatile(), 14520 St->isNonTemporal(), 14521 MinAlign(St->getAlignment(), 4)); 14522 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14523 } 14524 return SDValue(); 14525} 14526 14527/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14528/// and return the operands for the horizontal operation in LHS and RHS. A 14529/// horizontal operation performs the binary operation on successive elements 14530/// of its first operand, then on successive elements of its second operand, 14531/// returning the resulting values in a vector. For example, if 14532/// A = < float a0, float a1, float a2, float a3 > 14533/// and 14534/// B = < float b0, float b1, float b2, float b3 > 14535/// then the result of doing a horizontal operation on A and B is 14536/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14537/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14538/// A horizontal-op B, for some already available A and B, and if so then LHS is 14539/// set to A, RHS to B, and the routine returns 'true'. 14540/// Note that the binary operation should have the property that if one of the 14541/// operands is UNDEF then the result is UNDEF. 14542static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14543 // Look for the following pattern: if 14544 // A = < float a0, float a1, float a2, float a3 > 14545 // B = < float b0, float b1, float b2, float b3 > 14546 // and 14547 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14548 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14549 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14550 // which is A horizontal-op B. 14551 14552 // At least one of the operands should be a vector shuffle. 14553 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14554 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14555 return false; 14556 14557 EVT VT = LHS.getValueType(); 14558 14559 assert((VT.is128BitVector() || VT.is256BitVector()) && 14560 "Unsupported vector type for horizontal add/sub"); 14561 14562 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14563 // operate independently on 128-bit lanes. 14564 unsigned NumElts = VT.getVectorNumElements(); 14565 unsigned NumLanes = VT.getSizeInBits()/128; 14566 unsigned NumLaneElts = NumElts / NumLanes; 14567 assert((NumLaneElts % 2 == 0) && 14568 "Vector type should have an even number of elements in each lane"); 14569 unsigned HalfLaneElts = NumLaneElts/2; 14570 14571 // View LHS in the form 14572 // LHS = VECTOR_SHUFFLE A, B, LMask 14573 // If LHS is not a shuffle then pretend it is the shuffle 14574 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14575 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14576 // type VT. 14577 SDValue A, B; 14578 SmallVector<int, 16> LMask(NumElts); 14579 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14580 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14581 A = LHS.getOperand(0); 14582 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14583 B = LHS.getOperand(1); 14584 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14585 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14586 } else { 14587 if (LHS.getOpcode() != ISD::UNDEF) 14588 A = LHS; 14589 for (unsigned i = 0; i != NumElts; ++i) 14590 LMask[i] = i; 14591 } 14592 14593 // Likewise, view RHS in the form 14594 // RHS = VECTOR_SHUFFLE C, D, RMask 14595 SDValue C, D; 14596 SmallVector<int, 16> RMask(NumElts); 14597 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14598 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14599 C = RHS.getOperand(0); 14600 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14601 D = RHS.getOperand(1); 14602 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14603 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14604 } else { 14605 if (RHS.getOpcode() != ISD::UNDEF) 14606 C = RHS; 14607 for (unsigned i = 0; i != NumElts; ++i) 14608 RMask[i] = i; 14609 } 14610 14611 // Check that the shuffles are both shuffling the same vectors. 14612 if (!(A == C && B == D) && !(A == D && B == C)) 14613 return false; 14614 14615 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14616 if (!A.getNode() && !B.getNode()) 14617 return false; 14618 14619 // If A and B occur in reverse order in RHS, then "swap" them (which means 14620 // rewriting the mask). 14621 if (A != C) 14622 CommuteVectorShuffleMask(RMask, NumElts); 14623 14624 // At this point LHS and RHS are equivalent to 14625 // LHS = VECTOR_SHUFFLE A, B, LMask 14626 // RHS = VECTOR_SHUFFLE A, B, RMask 14627 // Check that the masks correspond to performing a horizontal operation. 14628 for (unsigned i = 0; i != NumElts; ++i) { 14629 int LIdx = LMask[i], RIdx = RMask[i]; 14630 14631 // Ignore any UNDEF components. 14632 if (LIdx < 0 || RIdx < 0 || 14633 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14634 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14635 continue; 14636 14637 // Check that successive elements are being operated on. If not, this is 14638 // not a horizontal operation. 14639 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14640 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14641 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14642 if (!(LIdx == Index && RIdx == Index + 1) && 14643 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14644 return false; 14645 } 14646 14647 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14648 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14649 return true; 14650} 14651 14652/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14653static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14654 const X86Subtarget *Subtarget) { 14655 EVT VT = N->getValueType(0); 14656 SDValue LHS = N->getOperand(0); 14657 SDValue RHS = N->getOperand(1); 14658 14659 // Try to synthesize horizontal adds from adds of shuffles. 14660 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14661 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14662 isHorizontalBinOp(LHS, RHS, true)) 14663 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14664 return SDValue(); 14665} 14666 14667/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14668static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14669 const X86Subtarget *Subtarget) { 14670 EVT VT = N->getValueType(0); 14671 SDValue LHS = N->getOperand(0); 14672 SDValue RHS = N->getOperand(1); 14673 14674 // Try to synthesize horizontal subs from subs of shuffles. 14675 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14676 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14677 isHorizontalBinOp(LHS, RHS, false)) 14678 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14679 return SDValue(); 14680} 14681 14682/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14683/// X86ISD::FXOR nodes. 14684static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14685 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14686 // F[X]OR(0.0, x) -> x 14687 // F[X]OR(x, 0.0) -> x 14688 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14689 if (C->getValueAPF().isPosZero()) 14690 return N->getOperand(1); 14691 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14692 if (C->getValueAPF().isPosZero()) 14693 return N->getOperand(0); 14694 return SDValue(); 14695} 14696 14697/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14698static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14699 // FAND(0.0, x) -> 0.0 14700 // FAND(x, 0.0) -> 0.0 14701 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14702 if (C->getValueAPF().isPosZero()) 14703 return N->getOperand(0); 14704 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14705 if (C->getValueAPF().isPosZero()) 14706 return N->getOperand(1); 14707 return SDValue(); 14708} 14709 14710static SDValue PerformBTCombine(SDNode *N, 14711 SelectionDAG &DAG, 14712 TargetLowering::DAGCombinerInfo &DCI) { 14713 // BT ignores high bits in the bit index operand. 14714 SDValue Op1 = N->getOperand(1); 14715 if (Op1.hasOneUse()) { 14716 unsigned BitWidth = Op1.getValueSizeInBits(); 14717 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14718 APInt KnownZero, KnownOne; 14719 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14720 !DCI.isBeforeLegalizeOps()); 14721 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14722 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14723 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14724 DCI.CommitTargetLoweringOpt(TLO); 14725 } 14726 return SDValue(); 14727} 14728 14729static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14730 SDValue Op = N->getOperand(0); 14731 if (Op.getOpcode() == ISD::BITCAST) 14732 Op = Op.getOperand(0); 14733 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14734 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14735 VT.getVectorElementType().getSizeInBits() == 14736 OpVT.getVectorElementType().getSizeInBits()) { 14737 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14738 } 14739 return SDValue(); 14740} 14741 14742static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14743 TargetLowering::DAGCombinerInfo &DCI, 14744 const X86Subtarget *Subtarget) { 14745 if (!DCI.isBeforeLegalizeOps()) 14746 return SDValue(); 14747 14748 if (!Subtarget->hasAVX()) 14749 return SDValue(); 14750 14751 // Optimize vectors in AVX mode 14752 // Sign extend v8i16 to v8i32 and 14753 // v4i32 to v4i64 14754 // 14755 // Divide input vector into two parts 14756 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 14757 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 14758 // concat the vectors to original VT 14759 14760 EVT VT = N->getValueType(0); 14761 SDValue Op = N->getOperand(0); 14762 EVT OpVT = Op.getValueType(); 14763 DebugLoc dl = N->getDebugLoc(); 14764 14765 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 14766 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 14767 14768 unsigned NumElems = OpVT.getVectorNumElements(); 14769 SmallVector<int,8> ShufMask1(NumElems, -1); 14770 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i; 14771 14772 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14773 ShufMask1.data()); 14774 14775 SmallVector<int,8> ShufMask2(NumElems, -1); 14776 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2; 14777 14778 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14779 ShufMask2.data()); 14780 14781 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 14782 VT.getVectorNumElements()/2); 14783 14784 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 14785 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 14786 14787 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14788 } 14789 return SDValue(); 14790} 14791 14792static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 14793 const X86Subtarget *Subtarget) { 14794 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14795 // (and (i32 x86isd::setcc_carry), 1) 14796 // This eliminates the zext. This transformation is necessary because 14797 // ISD::SETCC is always legalized to i8. 14798 DebugLoc dl = N->getDebugLoc(); 14799 SDValue N0 = N->getOperand(0); 14800 EVT VT = N->getValueType(0); 14801 EVT OpVT = N0.getValueType(); 14802 14803 if (N0.getOpcode() == ISD::AND && 14804 N0.hasOneUse() && 14805 N0.getOperand(0).hasOneUse()) { 14806 SDValue N00 = N0.getOperand(0); 14807 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14808 return SDValue(); 14809 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14810 if (!C || C->getZExtValue() != 1) 14811 return SDValue(); 14812 return DAG.getNode(ISD::AND, dl, VT, 14813 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14814 N00.getOperand(0), N00.getOperand(1)), 14815 DAG.getConstant(1, VT)); 14816 } 14817 // Optimize vectors in AVX mode: 14818 // 14819 // v8i16 -> v8i32 14820 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 14821 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 14822 // Concat upper and lower parts. 14823 // 14824 // v4i32 -> v4i64 14825 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 14826 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 14827 // Concat upper and lower parts. 14828 // 14829 if (Subtarget->hasAVX()) { 14830 14831 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 14832 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 14833 14834 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 14835 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG); 14836 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG); 14837 14838 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 14839 VT.getVectorNumElements()/2); 14840 14841 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 14842 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 14843 14844 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14845 } 14846 } 14847 14848 14849 return SDValue(); 14850} 14851 14852// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14853static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14854 unsigned X86CC = N->getConstantOperandVal(0); 14855 SDValue EFLAG = N->getOperand(1); 14856 DebugLoc DL = N->getDebugLoc(); 14857 14858 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14859 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14860 // cases. 14861 if (X86CC == X86::COND_B) 14862 return DAG.getNode(ISD::AND, DL, MVT::i8, 14863 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14864 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14865 DAG.getConstant(1, MVT::i8)); 14866 14867 return SDValue(); 14868} 14869 14870static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14871 const X86TargetLowering *XTLI) { 14872 SDValue Op0 = N->getOperand(0); 14873 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14874 // a 32-bit target where SSE doesn't support i64->FP operations. 14875 if (Op0.getOpcode() == ISD::LOAD) { 14876 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14877 EVT VT = Ld->getValueType(0); 14878 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14879 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14880 !XTLI->getSubtarget()->is64Bit() && 14881 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14882 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14883 Ld->getChain(), Op0, DAG); 14884 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14885 return FILDChain; 14886 } 14887 } 14888 return SDValue(); 14889} 14890 14891// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14892static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14893 X86TargetLowering::DAGCombinerInfo &DCI) { 14894 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14895 // the result is either zero or one (depending on the input carry bit). 14896 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14897 if (X86::isZeroNode(N->getOperand(0)) && 14898 X86::isZeroNode(N->getOperand(1)) && 14899 // We don't have a good way to replace an EFLAGS use, so only do this when 14900 // dead right now. 14901 SDValue(N, 1).use_empty()) { 14902 DebugLoc DL = N->getDebugLoc(); 14903 EVT VT = N->getValueType(0); 14904 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14905 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14906 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14907 DAG.getConstant(X86::COND_B,MVT::i8), 14908 N->getOperand(2)), 14909 DAG.getConstant(1, VT)); 14910 return DCI.CombineTo(N, Res1, CarryOut); 14911 } 14912 14913 return SDValue(); 14914} 14915 14916// fold (add Y, (sete X, 0)) -> adc 0, Y 14917// (add Y, (setne X, 0)) -> sbb -1, Y 14918// (sub (sete X, 0), Y) -> sbb 0, Y 14919// (sub (setne X, 0), Y) -> adc -1, Y 14920static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14921 DebugLoc DL = N->getDebugLoc(); 14922 14923 // Look through ZExts. 14924 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14925 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14926 return SDValue(); 14927 14928 SDValue SetCC = Ext.getOperand(0); 14929 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14930 return SDValue(); 14931 14932 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14933 if (CC != X86::COND_E && CC != X86::COND_NE) 14934 return SDValue(); 14935 14936 SDValue Cmp = SetCC.getOperand(1); 14937 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14938 !X86::isZeroNode(Cmp.getOperand(1)) || 14939 !Cmp.getOperand(0).getValueType().isInteger()) 14940 return SDValue(); 14941 14942 SDValue CmpOp0 = Cmp.getOperand(0); 14943 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14944 DAG.getConstant(1, CmpOp0.getValueType())); 14945 14946 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14947 if (CC == X86::COND_NE) 14948 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14949 DL, OtherVal.getValueType(), OtherVal, 14950 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14951 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14952 DL, OtherVal.getValueType(), OtherVal, 14953 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14954} 14955 14956/// PerformADDCombine - Do target-specific dag combines on integer adds. 14957static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14958 const X86Subtarget *Subtarget) { 14959 EVT VT = N->getValueType(0); 14960 SDValue Op0 = N->getOperand(0); 14961 SDValue Op1 = N->getOperand(1); 14962 14963 // Try to synthesize horizontal adds from adds of shuffles. 14964 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14965 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14966 isHorizontalBinOp(Op0, Op1, true)) 14967 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14968 14969 return OptimizeConditionalInDecrement(N, DAG); 14970} 14971 14972static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14973 const X86Subtarget *Subtarget) { 14974 SDValue Op0 = N->getOperand(0); 14975 SDValue Op1 = N->getOperand(1); 14976 14977 // X86 can't encode an immediate LHS of a sub. See if we can push the 14978 // negation into a preceding instruction. 14979 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14980 // If the RHS of the sub is a XOR with one use and a constant, invert the 14981 // immediate. Then add one to the LHS of the sub so we can turn 14982 // X-Y -> X+~Y+1, saving one register. 14983 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14984 isa<ConstantSDNode>(Op1.getOperand(1))) { 14985 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14986 EVT VT = Op0.getValueType(); 14987 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14988 Op1.getOperand(0), 14989 DAG.getConstant(~XorC, VT)); 14990 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14991 DAG.getConstant(C->getAPIntValue()+1, VT)); 14992 } 14993 } 14994 14995 // Try to synthesize horizontal adds from adds of shuffles. 14996 EVT VT = N->getValueType(0); 14997 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14998 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14999 isHorizontalBinOp(Op0, Op1, true)) 15000 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 15001 15002 return OptimizeConditionalInDecrement(N, DAG); 15003} 15004 15005SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 15006 DAGCombinerInfo &DCI) const { 15007 SelectionDAG &DAG = DCI.DAG; 15008 switch (N->getOpcode()) { 15009 default: break; 15010 case ISD::EXTRACT_VECTOR_ELT: 15011 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 15012 case ISD::VSELECT: 15013 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 15014 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 15015 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 15016 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 15017 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 15018 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 15019 case ISD::SHL: 15020 case ISD::SRA: 15021 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 15022 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 15023 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 15024 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 15025 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 15026 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 15027 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 15028 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 15029 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 15030 case X86ISD::FXOR: 15031 case X86ISD::FOR: return PerformFORCombine(N, DAG); 15032 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 15033 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 15034 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 15035 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget); 15036 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 15037 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 15038 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 15039 case X86ISD::SHUFP: // Handle all target specific shuffles 15040 case X86ISD::PALIGN: 15041 case X86ISD::UNPCKH: 15042 case X86ISD::UNPCKL: 15043 case X86ISD::MOVHLPS: 15044 case X86ISD::MOVLHPS: 15045 case X86ISD::PSHUFD: 15046 case X86ISD::PSHUFHW: 15047 case X86ISD::PSHUFLW: 15048 case X86ISD::MOVSS: 15049 case X86ISD::MOVSD: 15050 case X86ISD::VPERMILP: 15051 case X86ISD::VPERM2X128: 15052 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 15053 } 15054 15055 return SDValue(); 15056} 15057 15058/// isTypeDesirableForOp - Return true if the target has native support for 15059/// the specified value type and it is 'desirable' to use the type for the 15060/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 15061/// instruction encodings are longer and some i16 instructions are slow. 15062bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 15063 if (!isTypeLegal(VT)) 15064 return false; 15065 if (VT != MVT::i16) 15066 return true; 15067 15068 switch (Opc) { 15069 default: 15070 return true; 15071 case ISD::LOAD: 15072 case ISD::SIGN_EXTEND: 15073 case ISD::ZERO_EXTEND: 15074 case ISD::ANY_EXTEND: 15075 case ISD::SHL: 15076 case ISD::SRL: 15077 case ISD::SUB: 15078 case ISD::ADD: 15079 case ISD::MUL: 15080 case ISD::AND: 15081 case ISD::OR: 15082 case ISD::XOR: 15083 return false; 15084 } 15085} 15086 15087/// IsDesirableToPromoteOp - This method query the target whether it is 15088/// beneficial for dag combiner to promote the specified node. If true, it 15089/// should return the desired promotion type by reference. 15090bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 15091 EVT VT = Op.getValueType(); 15092 if (VT != MVT::i16) 15093 return false; 15094 15095 bool Promote = false; 15096 bool Commute = false; 15097 switch (Op.getOpcode()) { 15098 default: break; 15099 case ISD::LOAD: { 15100 LoadSDNode *LD = cast<LoadSDNode>(Op); 15101 // If the non-extending load has a single use and it's not live out, then it 15102 // might be folded. 15103 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 15104 Op.hasOneUse()*/) { 15105 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 15106 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 15107 // The only case where we'd want to promote LOAD (rather then it being 15108 // promoted as an operand is when it's only use is liveout. 15109 if (UI->getOpcode() != ISD::CopyToReg) 15110 return false; 15111 } 15112 } 15113 Promote = true; 15114 break; 15115 } 15116 case ISD::SIGN_EXTEND: 15117 case ISD::ZERO_EXTEND: 15118 case ISD::ANY_EXTEND: 15119 Promote = true; 15120 break; 15121 case ISD::SHL: 15122 case ISD::SRL: { 15123 SDValue N0 = Op.getOperand(0); 15124 // Look out for (store (shl (load), x)). 15125 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15126 return false; 15127 Promote = true; 15128 break; 15129 } 15130 case ISD::ADD: 15131 case ISD::MUL: 15132 case ISD::AND: 15133 case ISD::OR: 15134 case ISD::XOR: 15135 Commute = true; 15136 // fallthrough 15137 case ISD::SUB: { 15138 SDValue N0 = Op.getOperand(0); 15139 SDValue N1 = Op.getOperand(1); 15140 if (!Commute && MayFoldLoad(N1)) 15141 return false; 15142 // Avoid disabling potential load folding opportunities. 15143 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15144 return false; 15145 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15146 return false; 15147 Promote = true; 15148 } 15149 } 15150 15151 PVT = MVT::i32; 15152 return Promote; 15153} 15154 15155//===----------------------------------------------------------------------===// 15156// X86 Inline Assembly Support 15157//===----------------------------------------------------------------------===// 15158 15159namespace { 15160 // Helper to match a string separated by whitespace. 15161 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15162 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15163 15164 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15165 StringRef piece(*args[i]); 15166 if (!s.startswith(piece)) // Check if the piece matches. 15167 return false; 15168 15169 s = s.substr(piece.size()); 15170 StringRef::size_type pos = s.find_first_not_of(" \t"); 15171 if (pos == 0) // We matched a prefix. 15172 return false; 15173 15174 s = s.substr(pos); 15175 } 15176 15177 return s.empty(); 15178 } 15179 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15180} 15181 15182bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15183 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15184 15185 std::string AsmStr = IA->getAsmString(); 15186 15187 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15188 if (!Ty || Ty->getBitWidth() % 16 != 0) 15189 return false; 15190 15191 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15192 SmallVector<StringRef, 4> AsmPieces; 15193 SplitString(AsmStr, AsmPieces, ";\n"); 15194 15195 switch (AsmPieces.size()) { 15196 default: return false; 15197 case 1: 15198 // FIXME: this should verify that we are targeting a 486 or better. If not, 15199 // we will turn this bswap into something that will be lowered to logical 15200 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15201 // lower so don't worry about this. 15202 // bswap $0 15203 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15204 matchAsm(AsmPieces[0], "bswapl", "$0") || 15205 matchAsm(AsmPieces[0], "bswapq", "$0") || 15206 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15207 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15208 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15209 // No need to check constraints, nothing other than the equivalent of 15210 // "=r,0" would be valid here. 15211 return IntrinsicLowering::LowerToByteSwap(CI); 15212 } 15213 15214 // rorw $$8, ${0:w} --> llvm.bswap.i16 15215 if (CI->getType()->isIntegerTy(16) && 15216 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15217 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15218 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15219 AsmPieces.clear(); 15220 const std::string &ConstraintsStr = IA->getConstraintString(); 15221 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15222 std::sort(AsmPieces.begin(), AsmPieces.end()); 15223 if (AsmPieces.size() == 4 && 15224 AsmPieces[0] == "~{cc}" && 15225 AsmPieces[1] == "~{dirflag}" && 15226 AsmPieces[2] == "~{flags}" && 15227 AsmPieces[3] == "~{fpsr}") 15228 return IntrinsicLowering::LowerToByteSwap(CI); 15229 } 15230 break; 15231 case 3: 15232 if (CI->getType()->isIntegerTy(32) && 15233 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15234 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15235 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15236 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15237 AsmPieces.clear(); 15238 const std::string &ConstraintsStr = IA->getConstraintString(); 15239 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15240 std::sort(AsmPieces.begin(), AsmPieces.end()); 15241 if (AsmPieces.size() == 4 && 15242 AsmPieces[0] == "~{cc}" && 15243 AsmPieces[1] == "~{dirflag}" && 15244 AsmPieces[2] == "~{flags}" && 15245 AsmPieces[3] == "~{fpsr}") 15246 return IntrinsicLowering::LowerToByteSwap(CI); 15247 } 15248 15249 if (CI->getType()->isIntegerTy(64)) { 15250 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15251 if (Constraints.size() >= 2 && 15252 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15253 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15254 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15255 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15256 matchAsm(AsmPieces[1], "bswap", "%edx") && 15257 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15258 return IntrinsicLowering::LowerToByteSwap(CI); 15259 } 15260 } 15261 break; 15262 } 15263 return false; 15264} 15265 15266 15267 15268/// getConstraintType - Given a constraint letter, return the type of 15269/// constraint it is for this target. 15270X86TargetLowering::ConstraintType 15271X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15272 if (Constraint.size() == 1) { 15273 switch (Constraint[0]) { 15274 case 'R': 15275 case 'q': 15276 case 'Q': 15277 case 'f': 15278 case 't': 15279 case 'u': 15280 case 'y': 15281 case 'x': 15282 case 'Y': 15283 case 'l': 15284 return C_RegisterClass; 15285 case 'a': 15286 case 'b': 15287 case 'c': 15288 case 'd': 15289 case 'S': 15290 case 'D': 15291 case 'A': 15292 return C_Register; 15293 case 'I': 15294 case 'J': 15295 case 'K': 15296 case 'L': 15297 case 'M': 15298 case 'N': 15299 case 'G': 15300 case 'C': 15301 case 'e': 15302 case 'Z': 15303 return C_Other; 15304 default: 15305 break; 15306 } 15307 } 15308 return TargetLowering::getConstraintType(Constraint); 15309} 15310 15311/// Examine constraint type and operand type and determine a weight value. 15312/// This object must already have been set up with the operand type 15313/// and the current alternative constraint selected. 15314TargetLowering::ConstraintWeight 15315 X86TargetLowering::getSingleConstraintMatchWeight( 15316 AsmOperandInfo &info, const char *constraint) const { 15317 ConstraintWeight weight = CW_Invalid; 15318 Value *CallOperandVal = info.CallOperandVal; 15319 // If we don't have a value, we can't do a match, 15320 // but allow it at the lowest weight. 15321 if (CallOperandVal == NULL) 15322 return CW_Default; 15323 Type *type = CallOperandVal->getType(); 15324 // Look at the constraint type. 15325 switch (*constraint) { 15326 default: 15327 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15328 case 'R': 15329 case 'q': 15330 case 'Q': 15331 case 'a': 15332 case 'b': 15333 case 'c': 15334 case 'd': 15335 case 'S': 15336 case 'D': 15337 case 'A': 15338 if (CallOperandVal->getType()->isIntegerTy()) 15339 weight = CW_SpecificReg; 15340 break; 15341 case 'f': 15342 case 't': 15343 case 'u': 15344 if (type->isFloatingPointTy()) 15345 weight = CW_SpecificReg; 15346 break; 15347 case 'y': 15348 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15349 weight = CW_SpecificReg; 15350 break; 15351 case 'x': 15352 case 'Y': 15353 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15354 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15355 weight = CW_Register; 15356 break; 15357 case 'I': 15358 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15359 if (C->getZExtValue() <= 31) 15360 weight = CW_Constant; 15361 } 15362 break; 15363 case 'J': 15364 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15365 if (C->getZExtValue() <= 63) 15366 weight = CW_Constant; 15367 } 15368 break; 15369 case 'K': 15370 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15371 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15372 weight = CW_Constant; 15373 } 15374 break; 15375 case 'L': 15376 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15377 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15378 weight = CW_Constant; 15379 } 15380 break; 15381 case 'M': 15382 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15383 if (C->getZExtValue() <= 3) 15384 weight = CW_Constant; 15385 } 15386 break; 15387 case 'N': 15388 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15389 if (C->getZExtValue() <= 0xff) 15390 weight = CW_Constant; 15391 } 15392 break; 15393 case 'G': 15394 case 'C': 15395 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15396 weight = CW_Constant; 15397 } 15398 break; 15399 case 'e': 15400 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15401 if ((C->getSExtValue() >= -0x80000000LL) && 15402 (C->getSExtValue() <= 0x7fffffffLL)) 15403 weight = CW_Constant; 15404 } 15405 break; 15406 case 'Z': 15407 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15408 if (C->getZExtValue() <= 0xffffffff) 15409 weight = CW_Constant; 15410 } 15411 break; 15412 } 15413 return weight; 15414} 15415 15416/// LowerXConstraint - try to replace an X constraint, which matches anything, 15417/// with another that has more specific requirements based on the type of the 15418/// corresponding operand. 15419const char *X86TargetLowering:: 15420LowerXConstraint(EVT ConstraintVT) const { 15421 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15422 // 'f' like normal targets. 15423 if (ConstraintVT.isFloatingPoint()) { 15424 if (Subtarget->hasSSE2()) 15425 return "Y"; 15426 if (Subtarget->hasSSE1()) 15427 return "x"; 15428 } 15429 15430 return TargetLowering::LowerXConstraint(ConstraintVT); 15431} 15432 15433/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15434/// vector. If it is invalid, don't add anything to Ops. 15435void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15436 std::string &Constraint, 15437 std::vector<SDValue>&Ops, 15438 SelectionDAG &DAG) const { 15439 SDValue Result(0, 0); 15440 15441 // Only support length 1 constraints for now. 15442 if (Constraint.length() > 1) return; 15443 15444 char ConstraintLetter = Constraint[0]; 15445 switch (ConstraintLetter) { 15446 default: break; 15447 case 'I': 15448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15449 if (C->getZExtValue() <= 31) { 15450 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15451 break; 15452 } 15453 } 15454 return; 15455 case 'J': 15456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15457 if (C->getZExtValue() <= 63) { 15458 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15459 break; 15460 } 15461 } 15462 return; 15463 case 'K': 15464 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15465 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15466 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15467 break; 15468 } 15469 } 15470 return; 15471 case 'N': 15472 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15473 if (C->getZExtValue() <= 255) { 15474 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15475 break; 15476 } 15477 } 15478 return; 15479 case 'e': { 15480 // 32-bit signed value 15481 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15482 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15483 C->getSExtValue())) { 15484 // Widen to 64 bits here to get it sign extended. 15485 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15486 break; 15487 } 15488 // FIXME gcc accepts some relocatable values here too, but only in certain 15489 // memory models; it's complicated. 15490 } 15491 return; 15492 } 15493 case 'Z': { 15494 // 32-bit unsigned value 15495 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15496 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15497 C->getZExtValue())) { 15498 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15499 break; 15500 } 15501 } 15502 // FIXME gcc accepts some relocatable values here too, but only in certain 15503 // memory models; it's complicated. 15504 return; 15505 } 15506 case 'i': { 15507 // Literal immediates are always ok. 15508 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15509 // Widen to 64 bits here to get it sign extended. 15510 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15511 break; 15512 } 15513 15514 // In any sort of PIC mode addresses need to be computed at runtime by 15515 // adding in a register or some sort of table lookup. These can't 15516 // be used as immediates. 15517 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15518 return; 15519 15520 // If we are in non-pic codegen mode, we allow the address of a global (with 15521 // an optional displacement) to be used with 'i'. 15522 GlobalAddressSDNode *GA = 0; 15523 int64_t Offset = 0; 15524 15525 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15526 while (1) { 15527 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15528 Offset += GA->getOffset(); 15529 break; 15530 } else if (Op.getOpcode() == ISD::ADD) { 15531 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15532 Offset += C->getZExtValue(); 15533 Op = Op.getOperand(0); 15534 continue; 15535 } 15536 } else if (Op.getOpcode() == ISD::SUB) { 15537 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15538 Offset += -C->getZExtValue(); 15539 Op = Op.getOperand(0); 15540 continue; 15541 } 15542 } 15543 15544 // Otherwise, this isn't something we can handle, reject it. 15545 return; 15546 } 15547 15548 const GlobalValue *GV = GA->getGlobal(); 15549 // If we require an extra load to get this address, as in PIC mode, we 15550 // can't accept it. 15551 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15552 getTargetMachine()))) 15553 return; 15554 15555 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15556 GA->getValueType(0), Offset); 15557 break; 15558 } 15559 } 15560 15561 if (Result.getNode()) { 15562 Ops.push_back(Result); 15563 return; 15564 } 15565 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15566} 15567 15568std::pair<unsigned, const TargetRegisterClass*> 15569X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15570 EVT VT) const { 15571 // First, see if this is a constraint that directly corresponds to an LLVM 15572 // register class. 15573 if (Constraint.size() == 1) { 15574 // GCC Constraint Letters 15575 switch (Constraint[0]) { 15576 default: break; 15577 // TODO: Slight differences here in allocation order and leaving 15578 // RIP in the class. Do they matter any more here than they do 15579 // in the normal allocation? 15580 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15581 if (Subtarget->is64Bit()) { 15582 if (VT == MVT::i32 || VT == MVT::f32) 15583 return std::make_pair(0U, X86::GR32RegisterClass); 15584 else if (VT == MVT::i16) 15585 return std::make_pair(0U, X86::GR16RegisterClass); 15586 else if (VT == MVT::i8 || VT == MVT::i1) 15587 return std::make_pair(0U, X86::GR8RegisterClass); 15588 else if (VT == MVT::i64 || VT == MVT::f64) 15589 return std::make_pair(0U, X86::GR64RegisterClass); 15590 break; 15591 } 15592 // 32-bit fallthrough 15593 case 'Q': // Q_REGS 15594 if (VT == MVT::i32 || VT == MVT::f32) 15595 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15596 else if (VT == MVT::i16) 15597 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15598 else if (VT == MVT::i8 || VT == MVT::i1) 15599 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15600 else if (VT == MVT::i64) 15601 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15602 break; 15603 case 'r': // GENERAL_REGS 15604 case 'l': // INDEX_REGS 15605 if (VT == MVT::i8 || VT == MVT::i1) 15606 return std::make_pair(0U, X86::GR8RegisterClass); 15607 if (VT == MVT::i16) 15608 return std::make_pair(0U, X86::GR16RegisterClass); 15609 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15610 return std::make_pair(0U, X86::GR32RegisterClass); 15611 return std::make_pair(0U, X86::GR64RegisterClass); 15612 case 'R': // LEGACY_REGS 15613 if (VT == MVT::i8 || VT == MVT::i1) 15614 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15615 if (VT == MVT::i16) 15616 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15617 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15618 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15619 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15620 case 'f': // FP Stack registers. 15621 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15622 // value to the correct fpstack register class. 15623 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15624 return std::make_pair(0U, X86::RFP32RegisterClass); 15625 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15626 return std::make_pair(0U, X86::RFP64RegisterClass); 15627 return std::make_pair(0U, X86::RFP80RegisterClass); 15628 case 'y': // MMX_REGS if MMX allowed. 15629 if (!Subtarget->hasMMX()) break; 15630 return std::make_pair(0U, X86::VR64RegisterClass); 15631 case 'Y': // SSE_REGS if SSE2 allowed 15632 if (!Subtarget->hasSSE2()) break; 15633 // FALL THROUGH. 15634 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15635 if (!Subtarget->hasSSE1()) break; 15636 15637 switch (VT.getSimpleVT().SimpleTy) { 15638 default: break; 15639 // Scalar SSE types. 15640 case MVT::f32: 15641 case MVT::i32: 15642 return std::make_pair(0U, X86::FR32RegisterClass); 15643 case MVT::f64: 15644 case MVT::i64: 15645 return std::make_pair(0U, X86::FR64RegisterClass); 15646 // Vector types. 15647 case MVT::v16i8: 15648 case MVT::v8i16: 15649 case MVT::v4i32: 15650 case MVT::v2i64: 15651 case MVT::v4f32: 15652 case MVT::v2f64: 15653 return std::make_pair(0U, X86::VR128RegisterClass); 15654 // AVX types. 15655 case MVT::v32i8: 15656 case MVT::v16i16: 15657 case MVT::v8i32: 15658 case MVT::v4i64: 15659 case MVT::v8f32: 15660 case MVT::v4f64: 15661 return std::make_pair(0U, X86::VR256RegisterClass); 15662 15663 } 15664 break; 15665 } 15666 } 15667 15668 // Use the default implementation in TargetLowering to convert the register 15669 // constraint into a member of a register class. 15670 std::pair<unsigned, const TargetRegisterClass*> Res; 15671 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15672 15673 // Not found as a standard register? 15674 if (Res.second == 0) { 15675 // Map st(0) -> st(7) -> ST0 15676 if (Constraint.size() == 7 && Constraint[0] == '{' && 15677 tolower(Constraint[1]) == 's' && 15678 tolower(Constraint[2]) == 't' && 15679 Constraint[3] == '(' && 15680 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15681 Constraint[5] == ')' && 15682 Constraint[6] == '}') { 15683 15684 Res.first = X86::ST0+Constraint[4]-'0'; 15685 Res.second = X86::RFP80RegisterClass; 15686 return Res; 15687 } 15688 15689 // GCC allows "st(0)" to be called just plain "st". 15690 if (StringRef("{st}").equals_lower(Constraint)) { 15691 Res.first = X86::ST0; 15692 Res.second = X86::RFP80RegisterClass; 15693 return Res; 15694 } 15695 15696 // flags -> EFLAGS 15697 if (StringRef("{flags}").equals_lower(Constraint)) { 15698 Res.first = X86::EFLAGS; 15699 Res.second = X86::CCRRegisterClass; 15700 return Res; 15701 } 15702 15703 // 'A' means EAX + EDX. 15704 if (Constraint == "A") { 15705 Res.first = X86::EAX; 15706 Res.second = X86::GR32_ADRegisterClass; 15707 return Res; 15708 } 15709 return Res; 15710 } 15711 15712 // Otherwise, check to see if this is a register class of the wrong value 15713 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15714 // turn into {ax},{dx}. 15715 if (Res.second->hasType(VT)) 15716 return Res; // Correct type already, nothing to do. 15717 15718 // All of the single-register GCC register classes map their values onto 15719 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15720 // really want an 8-bit or 32-bit register, map to the appropriate register 15721 // class and return the appropriate register. 15722 if (Res.second == X86::GR16RegisterClass) { 15723 if (VT == MVT::i8) { 15724 unsigned DestReg = 0; 15725 switch (Res.first) { 15726 default: break; 15727 case X86::AX: DestReg = X86::AL; break; 15728 case X86::DX: DestReg = X86::DL; break; 15729 case X86::CX: DestReg = X86::CL; break; 15730 case X86::BX: DestReg = X86::BL; break; 15731 } 15732 if (DestReg) { 15733 Res.first = DestReg; 15734 Res.second = X86::GR8RegisterClass; 15735 } 15736 } else if (VT == MVT::i32) { 15737 unsigned DestReg = 0; 15738 switch (Res.first) { 15739 default: break; 15740 case X86::AX: DestReg = X86::EAX; break; 15741 case X86::DX: DestReg = X86::EDX; break; 15742 case X86::CX: DestReg = X86::ECX; break; 15743 case X86::BX: DestReg = X86::EBX; break; 15744 case X86::SI: DestReg = X86::ESI; break; 15745 case X86::DI: DestReg = X86::EDI; break; 15746 case X86::BP: DestReg = X86::EBP; break; 15747 case X86::SP: DestReg = X86::ESP; break; 15748 } 15749 if (DestReg) { 15750 Res.first = DestReg; 15751 Res.second = X86::GR32RegisterClass; 15752 } 15753 } else if (VT == MVT::i64) { 15754 unsigned DestReg = 0; 15755 switch (Res.first) { 15756 default: break; 15757 case X86::AX: DestReg = X86::RAX; break; 15758 case X86::DX: DestReg = X86::RDX; break; 15759 case X86::CX: DestReg = X86::RCX; break; 15760 case X86::BX: DestReg = X86::RBX; break; 15761 case X86::SI: DestReg = X86::RSI; break; 15762 case X86::DI: DestReg = X86::RDI; break; 15763 case X86::BP: DestReg = X86::RBP; break; 15764 case X86::SP: DestReg = X86::RSP; break; 15765 } 15766 if (DestReg) { 15767 Res.first = DestReg; 15768 Res.second = X86::GR64RegisterClass; 15769 } 15770 } 15771 } else if (Res.second == X86::FR32RegisterClass || 15772 Res.second == X86::FR64RegisterClass || 15773 Res.second == X86::VR128RegisterClass) { 15774 // Handle references to XMM physical registers that got mapped into the 15775 // wrong class. This can happen with constraints like {xmm0} where the 15776 // target independent register mapper will just pick the first match it can 15777 // find, ignoring the required type. 15778 if (VT == MVT::f32) 15779 Res.second = X86::FR32RegisterClass; 15780 else if (VT == MVT::f64) 15781 Res.second = X86::FR64RegisterClass; 15782 else if (X86::VR128RegisterClass->hasType(VT)) 15783 Res.second = X86::VR128RegisterClass; 15784 } 15785 15786 return Res; 15787} 15788