X86ISelLowering.cpp revision e915047fed99221afb8c540d8a7e81038a6483f1
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "Utils/X86ShuffleDecode.h" 18#include "X86.h" 19#include "X86InstrBuilder.h" 20#include "X86TargetMachine.h" 21#include "X86TargetObjectFile.h" 22#include "llvm/ADT/SmallSet.h" 23#include "llvm/ADT/Statistic.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/VariadicFunction.h" 26#include "llvm/CodeGen/IntrinsicLowering.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineJumpTableInfo.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/IR/CallingConv.h" 34#include "llvm/IR/Constants.h" 35#include "llvm/IR/DerivedTypes.h" 36#include "llvm/IR/Function.h" 37#include "llvm/IR/GlobalAlias.h" 38#include "llvm/IR/GlobalVariable.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/Intrinsics.h" 41#include "llvm/IR/LLVMContext.h" 42#include "llvm/MC/MCAsmInfo.h" 43#include "llvm/MC/MCContext.h" 44#include "llvm/MC/MCExpr.h" 45#include "llvm/MC/MCSymbol.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52#include <cctype> 53using namespace llvm; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57// Forward declarations. 58static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 59 SDValue V2); 60 61/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 62/// sets things up to match to an AVX VEXTRACTF128 instruction or a 63/// simple subregister reference. Idx is an index in the 128 bits we 64/// want. It need not be aligned to a 128-bit bounday. That makes 65/// lowering EXTRACT_VECTOR_ELT operations easier. 66static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, 67 SelectionDAG &DAG, DebugLoc dl) { 68 EVT VT = Vec.getValueType(); 69 assert(VT.is256BitVector() && "Unexpected vector size!"); 70 EVT ElVT = VT.getVectorElementType(); 71 unsigned Factor = VT.getSizeInBits()/128; 72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 73 VT.getVectorNumElements()/Factor); 74 75 // Extract from UNDEF is UNDEF. 76 if (Vec.getOpcode() == ISD::UNDEF) 77 return DAG.getUNDEF(ResultVT); 78 79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 80 // we can match to VEXTRACTF128. 81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 82 83 // This is the index of the first element of the 128-bit chunk 84 // we want. 85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 86 * ElemsPerChunk); 87 88 // If the input is a buildvector just emit a smaller one. 89 if (Vec.getOpcode() == ISD::BUILD_VECTOR) 90 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, 91 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk); 92 93 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 95 VecIdx); 96 97 return Result; 98} 99 100/// Generate a DAG to put 128-bits into a vector > 128 bits. This 101/// sets things up to match to an AVX VINSERTF128 instruction or a 102/// simple superregister reference. Idx is an index in the 128 bits 103/// we want. It need not be aligned to a 128-bit bounday. That makes 104/// lowering INSERT_VECTOR_ELT operations easier. 105static SDValue Insert128BitVector(SDValue Result, SDValue Vec, 106 unsigned IdxVal, SelectionDAG &DAG, 107 DebugLoc dl) { 108 // Inserting UNDEF is Result 109 if (Vec.getOpcode() == ISD::UNDEF) 110 return Result; 111 112 EVT VT = Vec.getValueType(); 113 assert(VT.is128BitVector() && "Unexpected vector size!"); 114 115 EVT ElVT = VT.getVectorElementType(); 116 EVT ResultVT = Result.getValueType(); 117 118 // Insert the relevant 128 bits. 119 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 120 121 // This is the index of the first element of the 128-bit chunk 122 // we want. 123 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 124 * ElemsPerChunk); 125 126 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 127 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 128 VecIdx); 129} 130 131/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 132/// instructions. This is used because creating CONCAT_VECTOR nodes of 133/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower 134/// large BUILD_VECTORS. 135static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 136 unsigned NumElems, SelectionDAG &DAG, 137 DebugLoc dl) { 138 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 139 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 140} 141 142static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 143 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 144 bool is64Bit = Subtarget->is64Bit(); 145 146 if (Subtarget->isTargetEnvMacho()) { 147 if (is64Bit) 148 return new X86_64MachoTargetObjectFile(); 149 return new TargetLoweringObjectFileMachO(); 150 } 151 152 if (Subtarget->isTargetLinux()) 153 return new X86LinuxTargetObjectFile(); 154 if (Subtarget->isTargetELF()) 155 return new TargetLoweringObjectFileELF(); 156 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 157 return new TargetLoweringObjectFileCOFF(); 158 llvm_unreachable("unknown subtarget type"); 159} 160 161X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 162 : TargetLowering(TM, createTLOF(TM)) { 163 Subtarget = &TM.getSubtarget<X86Subtarget>(); 164 X86ScalarSSEf64 = Subtarget->hasSSE2(); 165 X86ScalarSSEf32 = Subtarget->hasSSE1(); 166 167 RegInfo = TM.getRegisterInfo(); 168 TD = getDataLayout(); 169 170 // Set up the TargetLowering object. 171 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 172 173 // X86 is weird, it always uses i8 for shift amounts and setcc results. 174 setBooleanContents(ZeroOrOneBooleanContent); 175 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 176 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 177 178 // For 64-bit since we have so many registers use the ILP scheduler, for 179 // 32-bit code use the register pressure specific scheduling. 180 // For Atom, always use ILP scheduling. 181 if (Subtarget->isAtom()) 182 setSchedulingPreference(Sched::ILP); 183 else if (Subtarget->is64Bit()) 184 setSchedulingPreference(Sched::ILP); 185 else 186 setSchedulingPreference(Sched::RegPressure); 187 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister()); 188 189 // Bypass expensive divides on Atom when compiling with O2 190 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) { 191 addBypassSlowDiv(32, 8); 192 if (Subtarget->is64Bit()) 193 addBypassSlowDiv(64, 16); 194 } 195 196 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 197 // Setup Windows compiler runtime calls. 198 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 199 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 200 setLibcallName(RTLIB::SREM_I64, "_allrem"); 201 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 202 setLibcallName(RTLIB::MUL_I64, "_allmul"); 203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 208 209 // The _ftol2 runtime function has an unusual calling conv, which 210 // is modeled by a special pseudo-instruction. 211 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 212 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 213 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 214 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 215 } 216 217 if (Subtarget->isTargetDarwin()) { 218 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 219 setUseUnderscoreSetJmp(false); 220 setUseUnderscoreLongJmp(false); 221 } else if (Subtarget->isTargetMingw()) { 222 // MS runtime is weird: it exports _setjmp, but longjmp! 223 setUseUnderscoreSetJmp(true); 224 setUseUnderscoreLongJmp(false); 225 } else { 226 setUseUnderscoreSetJmp(true); 227 setUseUnderscoreLongJmp(true); 228 } 229 230 // Set up the register classes. 231 addRegisterClass(MVT::i8, &X86::GR8RegClass); 232 addRegisterClass(MVT::i16, &X86::GR16RegClass); 233 addRegisterClass(MVT::i32, &X86::GR32RegClass); 234 if (Subtarget->is64Bit()) 235 addRegisterClass(MVT::i64, &X86::GR64RegClass); 236 237 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 238 239 // We don't accept any truncstore of integer registers. 240 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 241 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 242 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 243 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 244 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 245 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 246 247 // SETOEQ and SETUNE require checking two conditions. 248 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 249 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 250 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 251 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 252 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 253 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 254 255 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 256 // operation. 257 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 258 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 259 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 260 261 if (Subtarget->is64Bit()) { 262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 264 } else if (!TM.Options.UseSoftFloat) { 265 // We have an algorithm for SSE2->double, and we turn this into a 266 // 64-bit FILD followed by conditional FADD for other targets. 267 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 268 // We have an algorithm for SSE2, and we turn this into a 64-bit 269 // FILD for other targets. 270 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 271 } 272 273 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 274 // this operation. 275 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 276 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 277 278 if (!TM.Options.UseSoftFloat) { 279 // SSE has no i16 to fp conversion, only i32 280 if (X86ScalarSSEf32) { 281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 282 // f32 and f64 cases are Legal, f80 case is not 283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 284 } else { 285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 287 } 288 } else { 289 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 290 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 291 } 292 293 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 294 // are Legal, f80 is custom lowered. 295 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 296 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 297 298 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 299 // this operation. 300 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 301 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 302 303 if (X86ScalarSSEf32) { 304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 305 // f32 and f64 cases are Legal, f80 case is not 306 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 307 } else { 308 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 309 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 310 } 311 312 // Handle FP_TO_UINT by promoting the destination to a larger signed 313 // conversion. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 315 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 316 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 317 318 if (Subtarget->is64Bit()) { 319 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 321 } else if (!TM.Options.UseSoftFloat) { 322 // Since AVX is a superset of SSE3, only check for SSE here. 323 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 324 // Expand FP_TO_UINT into a select. 325 // FIXME: We would like to use a Custom expander here eventually to do 326 // the optimal thing for SSE vs. the default expansion in the legalizer. 327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 328 else 329 // With SSE3 we can use fisttpll to convert to a signed i64; without 330 // SSE, we're stuck with a fistpll. 331 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 332 } 333 334 if (isTargetFTOL()) { 335 // Use the _ftol2 runtime function, which has a pseudo-instruction 336 // to handle its weird calling convention. 337 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 338 } 339 340 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 341 if (!X86ScalarSSEf64) { 342 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 343 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 344 if (Subtarget->is64Bit()) { 345 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 346 // Without SSE, i64->f64 goes through memory. 347 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 348 } 349 } 350 351 // Scalar integer divide and remainder are lowered to use operations that 352 // produce two results, to match the available instructions. This exposes 353 // the two-result form to trivial CSE, which is able to combine x/y and x%y 354 // into a single instruction. 355 // 356 // Scalar integer multiply-high is also lowered to use two-result 357 // operations, to match the available instructions. However, plain multiply 358 // (low) operations are left as Legal, as there are single-result 359 // instructions for this in x86. Using the two-result multiply instructions 360 // when both high and low results are needed must be arranged by dagcombine. 361 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 362 MVT VT = IntVTs[i]; 363 setOperationAction(ISD::MULHS, VT, Expand); 364 setOperationAction(ISD::MULHU, VT, Expand); 365 setOperationAction(ISD::SDIV, VT, Expand); 366 setOperationAction(ISD::UDIV, VT, Expand); 367 setOperationAction(ISD::SREM, VT, Expand); 368 setOperationAction(ISD::UREM, VT, Expand); 369 370 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 371 setOperationAction(ISD::ADDC, VT, Custom); 372 setOperationAction(ISD::ADDE, VT, Custom); 373 setOperationAction(ISD::SUBC, VT, Custom); 374 setOperationAction(ISD::SUBE, VT, Custom); 375 } 376 377 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 378 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 379 setOperationAction(ISD::BR_CC , MVT::f32, Expand); 380 setOperationAction(ISD::BR_CC , MVT::f64, Expand); 381 setOperationAction(ISD::BR_CC , MVT::f80, Expand); 382 setOperationAction(ISD::BR_CC , MVT::i8, Expand); 383 setOperationAction(ISD::BR_CC , MVT::i16, Expand); 384 setOperationAction(ISD::BR_CC , MVT::i32, Expand); 385 setOperationAction(ISD::BR_CC , MVT::i64, Expand); 386 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 387 if (Subtarget->is64Bit()) 388 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 389 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 390 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 391 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 392 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 393 setOperationAction(ISD::FREM , MVT::f32 , Expand); 394 setOperationAction(ISD::FREM , MVT::f64 , Expand); 395 setOperationAction(ISD::FREM , MVT::f80 , Expand); 396 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 397 398 // Promote the i8 variants and force them on up to i32 which has a shorter 399 // encoding. 400 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 401 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 402 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 403 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 404 if (Subtarget->hasBMI()) { 405 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 406 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 407 if (Subtarget->is64Bit()) 408 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 409 } else { 410 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 411 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 412 if (Subtarget->is64Bit()) 413 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 414 } 415 416 if (Subtarget->hasLZCNT()) { 417 // When promoting the i8 variants, force them to i32 for a shorter 418 // encoding. 419 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 420 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 421 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 422 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 424 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 425 if (Subtarget->is64Bit()) 426 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 427 } else { 428 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 429 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 430 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 431 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 432 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 433 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 434 if (Subtarget->is64Bit()) { 435 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 436 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 437 } 438 } 439 440 if (Subtarget->hasPOPCNT()) { 441 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 442 } else { 443 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 444 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 445 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 446 if (Subtarget->is64Bit()) 447 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 448 } 449 450 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 451 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 452 453 // These should be promoted to a larger select which is supported. 454 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 455 // X86 wants to expand cmov itself. 456 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 457 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 458 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 459 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 460 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 461 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 462 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 463 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 464 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 465 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 466 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 467 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 468 if (Subtarget->is64Bit()) { 469 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 470 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 471 } 472 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 473 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support 474 // SjLj exception handling but a light-weight setjmp/longjmp replacement to 475 // support continuation, user-level threading, and etc.. As a result, no 476 // other SjLj exception interfaces are implemented and please don't build 477 // your own exception handling based on them. 478 // LLVM/Clang supports zero-cost DWARF exception handling. 479 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 480 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 481 482 // Darwin ABI issue. 483 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 484 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 485 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 486 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 487 if (Subtarget->is64Bit()) 488 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 489 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 490 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 491 if (Subtarget->is64Bit()) { 492 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 493 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 494 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 495 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 496 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 497 } 498 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 499 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 500 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 501 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 502 if (Subtarget->is64Bit()) { 503 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 504 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 505 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 506 } 507 508 if (Subtarget->hasSSE1()) 509 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 510 511 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 512 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 513 514 // On X86 and X86-64, atomic operations are lowered to locked instructions. 515 // Locked instructions, in turn, have implicit fence semantics (all memory 516 // operations are flushed before issuing the locked instruction, and they 517 // are not buffered), so we can fold away the common pattern of 518 // fence-atomic-fence. 519 setShouldFoldAtomicFences(true); 520 521 // Expand certain atomics 522 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 523 MVT VT = IntVTs[i]; 524 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 525 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 526 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 527 } 528 529 if (!Subtarget->is64Bit()) { 530 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 531 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 532 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 533 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 534 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 535 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 536 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 537 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 538 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom); 539 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom); 540 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom); 541 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom); 542 } 543 544 if (Subtarget->hasCmpxchg16b()) { 545 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 546 } 547 548 // FIXME - use subtarget debug flags 549 if (!Subtarget->isTargetDarwin() && 550 !Subtarget->isTargetELF() && 551 !Subtarget->isTargetCygMing()) { 552 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 553 } 554 555 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 556 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 557 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 558 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 559 if (Subtarget->is64Bit()) { 560 setExceptionPointerRegister(X86::RAX); 561 setExceptionSelectorRegister(X86::RDX); 562 } else { 563 setExceptionPointerRegister(X86::EAX); 564 setExceptionSelectorRegister(X86::EDX); 565 } 566 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 567 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 568 569 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 570 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 571 572 setOperationAction(ISD::TRAP, MVT::Other, Legal); 573 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); 574 575 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 576 setOperationAction(ISD::VASTART , MVT::Other, Custom); 577 setOperationAction(ISD::VAEND , MVT::Other, Expand); 578 if (Subtarget->is64Bit()) { 579 setOperationAction(ISD::VAARG , MVT::Other, Custom); 580 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 581 } else { 582 setOperationAction(ISD::VAARG , MVT::Other, Expand); 583 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 584 } 585 586 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 587 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 588 589 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 590 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 591 MVT::i64 : MVT::i32, Custom); 592 else if (TM.Options.EnableSegmentedStacks) 593 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 594 MVT::i64 : MVT::i32, Custom); 595 else 596 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 597 MVT::i64 : MVT::i32, Expand); 598 599 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 600 // f32 and f64 use SSE. 601 // Set up the FP register classes. 602 addRegisterClass(MVT::f32, &X86::FR32RegClass); 603 addRegisterClass(MVT::f64, &X86::FR64RegClass); 604 605 // Use ANDPD to simulate FABS. 606 setOperationAction(ISD::FABS , MVT::f64, Custom); 607 setOperationAction(ISD::FABS , MVT::f32, Custom); 608 609 // Use XORP to simulate FNEG. 610 setOperationAction(ISD::FNEG , MVT::f64, Custom); 611 setOperationAction(ISD::FNEG , MVT::f32, Custom); 612 613 // Use ANDPD and ORPD to simulate FCOPYSIGN. 614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 616 617 // Lower this to FGETSIGNx86 plus an AND. 618 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 619 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 620 621 // We don't support sin/cos/fmod 622 setOperationAction(ISD::FSIN , MVT::f64, Expand); 623 setOperationAction(ISD::FCOS , MVT::f64, Expand); 624 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 625 setOperationAction(ISD::FSIN , MVT::f32, Expand); 626 setOperationAction(ISD::FCOS , MVT::f32, Expand); 627 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 628 629 // Expand FP immediates into loads from the stack, except for the special 630 // cases we handle. 631 addLegalFPImmediate(APFloat(+0.0)); // xorpd 632 addLegalFPImmediate(APFloat(+0.0f)); // xorps 633 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 634 // Use SSE for f32, x87 for f64. 635 // Set up the FP register classes. 636 addRegisterClass(MVT::f32, &X86::FR32RegClass); 637 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 638 639 // Use ANDPS to simulate FABS. 640 setOperationAction(ISD::FABS , MVT::f32, Custom); 641 642 // Use XORP to simulate FNEG. 643 setOperationAction(ISD::FNEG , MVT::f32, Custom); 644 645 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 646 647 // Use ANDPS and ORPS to simulate FCOPYSIGN. 648 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 649 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 650 651 // We don't support sin/cos/fmod 652 setOperationAction(ISD::FSIN , MVT::f32, Expand); 653 setOperationAction(ISD::FCOS , MVT::f32, Expand); 654 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 655 656 // Special cases we handle for FP constants. 657 addLegalFPImmediate(APFloat(+0.0f)); // xorps 658 addLegalFPImmediate(APFloat(+0.0)); // FLD0 659 addLegalFPImmediate(APFloat(+1.0)); // FLD1 660 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 661 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 662 663 if (!TM.Options.UnsafeFPMath) { 664 setOperationAction(ISD::FSIN , MVT::f64, Expand); 665 setOperationAction(ISD::FCOS , MVT::f64, Expand); 666 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 667 } 668 } else if (!TM.Options.UseSoftFloat) { 669 // f32 and f64 in x87. 670 // Set up the FP register classes. 671 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 672 addRegisterClass(MVT::f32, &X86::RFP32RegClass); 673 674 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 675 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 676 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 677 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 678 679 if (!TM.Options.UnsafeFPMath) { 680 setOperationAction(ISD::FSIN , MVT::f64, Expand); 681 setOperationAction(ISD::FSIN , MVT::f32, Expand); 682 setOperationAction(ISD::FCOS , MVT::f64, Expand); 683 setOperationAction(ISD::FCOS , MVT::f32, Expand); 684 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 685 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 686 } 687 addLegalFPImmediate(APFloat(+0.0)); // FLD0 688 addLegalFPImmediate(APFloat(+1.0)); // FLD1 689 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 690 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 691 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 692 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 693 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 694 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 695 } 696 697 // We don't support FMA. 698 setOperationAction(ISD::FMA, MVT::f64, Expand); 699 setOperationAction(ISD::FMA, MVT::f32, Expand); 700 701 // Long double always uses X87. 702 if (!TM.Options.UseSoftFloat) { 703 addRegisterClass(MVT::f80, &X86::RFP80RegClass); 704 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 705 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 706 { 707 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 708 addLegalFPImmediate(TmpFlt); // FLD0 709 TmpFlt.changeSign(); 710 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 711 712 bool ignored; 713 APFloat TmpFlt2(+1.0); 714 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 715 &ignored); 716 addLegalFPImmediate(TmpFlt2); // FLD1 717 TmpFlt2.changeSign(); 718 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 719 } 720 721 if (!TM.Options.UnsafeFPMath) { 722 setOperationAction(ISD::FSIN , MVT::f80, Expand); 723 setOperationAction(ISD::FCOS , MVT::f80, Expand); 724 setOperationAction(ISD::FSINCOS, MVT::f80, Expand); 725 } 726 727 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 728 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 729 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 730 setOperationAction(ISD::FRINT, MVT::f80, Expand); 731 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 732 setOperationAction(ISD::FMA, MVT::f80, Expand); 733 } 734 735 // Always use a library call for pow. 736 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 737 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 738 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 739 740 setOperationAction(ISD::FLOG, MVT::f80, Expand); 741 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 742 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 743 setOperationAction(ISD::FEXP, MVT::f80, Expand); 744 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 745 746 // First set operation action for all vector types to either promote 747 // (for widening) or expand (for scalarization). Then we will selectively 748 // turn on ones that can be effectively codegen'd. 749 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 750 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 751 MVT VT = (MVT::SimpleValueType)i; 752 setOperationAction(ISD::ADD , VT, Expand); 753 setOperationAction(ISD::SUB , VT, Expand); 754 setOperationAction(ISD::FADD, VT, Expand); 755 setOperationAction(ISD::FNEG, VT, Expand); 756 setOperationAction(ISD::FSUB, VT, Expand); 757 setOperationAction(ISD::MUL , VT, Expand); 758 setOperationAction(ISD::FMUL, VT, Expand); 759 setOperationAction(ISD::SDIV, VT, Expand); 760 setOperationAction(ISD::UDIV, VT, Expand); 761 setOperationAction(ISD::FDIV, VT, Expand); 762 setOperationAction(ISD::SREM, VT, Expand); 763 setOperationAction(ISD::UREM, VT, Expand); 764 setOperationAction(ISD::LOAD, VT, Expand); 765 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); 766 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand); 767 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 768 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); 769 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); 770 setOperationAction(ISD::FABS, VT, Expand); 771 setOperationAction(ISD::FSIN, VT, Expand); 772 setOperationAction(ISD::FSINCOS, VT, Expand); 773 setOperationAction(ISD::FCOS, VT, Expand); 774 setOperationAction(ISD::FSINCOS, VT, Expand); 775 setOperationAction(ISD::FREM, VT, Expand); 776 setOperationAction(ISD::FMA, VT, Expand); 777 setOperationAction(ISD::FPOWI, VT, Expand); 778 setOperationAction(ISD::FSQRT, VT, Expand); 779 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 780 setOperationAction(ISD::FFLOOR, VT, Expand); 781 setOperationAction(ISD::FCEIL, VT, Expand); 782 setOperationAction(ISD::FTRUNC, VT, Expand); 783 setOperationAction(ISD::FRINT, VT, Expand); 784 setOperationAction(ISD::FNEARBYINT, VT, Expand); 785 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 786 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 787 setOperationAction(ISD::SDIVREM, VT, Expand); 788 setOperationAction(ISD::UDIVREM, VT, Expand); 789 setOperationAction(ISD::FPOW, VT, Expand); 790 setOperationAction(ISD::CTPOP, VT, Expand); 791 setOperationAction(ISD::CTTZ, VT, Expand); 792 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 793 setOperationAction(ISD::CTLZ, VT, Expand); 794 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 795 setOperationAction(ISD::SHL, VT, Expand); 796 setOperationAction(ISD::SRA, VT, Expand); 797 setOperationAction(ISD::SRL, VT, Expand); 798 setOperationAction(ISD::ROTL, VT, Expand); 799 setOperationAction(ISD::ROTR, VT, Expand); 800 setOperationAction(ISD::BSWAP, VT, Expand); 801 setOperationAction(ISD::SETCC, VT, Expand); 802 setOperationAction(ISD::FLOG, VT, Expand); 803 setOperationAction(ISD::FLOG2, VT, Expand); 804 setOperationAction(ISD::FLOG10, VT, Expand); 805 setOperationAction(ISD::FEXP, VT, Expand); 806 setOperationAction(ISD::FEXP2, VT, Expand); 807 setOperationAction(ISD::FP_TO_UINT, VT, Expand); 808 setOperationAction(ISD::FP_TO_SINT, VT, Expand); 809 setOperationAction(ISD::UINT_TO_FP, VT, Expand); 810 setOperationAction(ISD::SINT_TO_FP, VT, Expand); 811 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand); 812 setOperationAction(ISD::TRUNCATE, VT, Expand); 813 setOperationAction(ISD::SIGN_EXTEND, VT, Expand); 814 setOperationAction(ISD::ZERO_EXTEND, VT, Expand); 815 setOperationAction(ISD::ANY_EXTEND, VT, Expand); 816 setOperationAction(ISD::VSELECT, VT, Expand); 817 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE; 818 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 819 setTruncStoreAction(VT, 820 (MVT::SimpleValueType)InnerVT, Expand); 821 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); 822 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); 823 setLoadExtAction(ISD::EXTLOAD, VT, Expand); 824 } 825 826 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 827 // with -msoft-float, disable use of MMX as well. 828 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 829 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass); 830 // No operations on x86mmx supported, everything uses intrinsics. 831 } 832 833 // MMX-sized vectors (other than x86mmx) are expected to be expanded 834 // into smaller operations. 835 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 836 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 837 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 838 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 839 setOperationAction(ISD::AND, MVT::v8i8, Expand); 840 setOperationAction(ISD::AND, MVT::v4i16, Expand); 841 setOperationAction(ISD::AND, MVT::v2i32, Expand); 842 setOperationAction(ISD::AND, MVT::v1i64, Expand); 843 setOperationAction(ISD::OR, MVT::v8i8, Expand); 844 setOperationAction(ISD::OR, MVT::v4i16, Expand); 845 setOperationAction(ISD::OR, MVT::v2i32, Expand); 846 setOperationAction(ISD::OR, MVT::v1i64, Expand); 847 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 848 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 849 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 850 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 851 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 852 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 853 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 854 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 856 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 857 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 858 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 859 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 860 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 861 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 862 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 863 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 864 865 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 866 addRegisterClass(MVT::v4f32, &X86::VR128RegClass); 867 868 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 869 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 870 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 871 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 872 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 873 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 874 setOperationAction(ISD::FABS, MVT::v4f32, Custom); 875 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 876 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 878 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 879 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 880 } 881 882 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 883 addRegisterClass(MVT::v2f64, &X86::VR128RegClass); 884 885 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 886 // registers cannot be used even for integer operations. 887 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 888 addRegisterClass(MVT::v8i16, &X86::VR128RegClass); 889 addRegisterClass(MVT::v4i32, &X86::VR128RegClass); 890 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); 891 892 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 893 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 894 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 895 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 896 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 897 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 898 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 899 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 900 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 901 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 902 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 903 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 904 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 905 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 906 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 907 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 908 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 909 setOperationAction(ISD::FABS, MVT::v2f64, Custom); 910 911 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 912 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 913 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 914 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 915 916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 921 922 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 923 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 924 MVT VT = (MVT::SimpleValueType)i; 925 // Do not attempt to custom lower non-power-of-2 vectors 926 if (!isPowerOf2_32(VT.getVectorNumElements())) 927 continue; 928 // Do not attempt to custom lower non-128-bit vectors 929 if (!VT.is128BitVector()) 930 continue; 931 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 932 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 933 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 934 } 935 936 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 937 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 938 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 939 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 942 943 if (Subtarget->is64Bit()) { 944 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 946 } 947 948 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 949 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 950 MVT VT = (MVT::SimpleValueType)i; 951 952 // Do not attempt to promote non-128-bit vectors 953 if (!VT.is128BitVector()) 954 continue; 955 956 setOperationAction(ISD::AND, VT, Promote); 957 AddPromotedToType (ISD::AND, VT, MVT::v2i64); 958 setOperationAction(ISD::OR, VT, Promote); 959 AddPromotedToType (ISD::OR, VT, MVT::v2i64); 960 setOperationAction(ISD::XOR, VT, Promote); 961 AddPromotedToType (ISD::XOR, VT, MVT::v2i64); 962 setOperationAction(ISD::LOAD, VT, Promote); 963 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64); 964 setOperationAction(ISD::SELECT, VT, Promote); 965 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64); 966 } 967 968 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 969 970 // Custom lower v2i64 and v2f64 selects. 971 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 972 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 973 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 974 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 975 976 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 977 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 978 979 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom); 980 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 981 // As there is no 64-bit GPR available, we need build a special custom 982 // sequence to convert from v2i32 to v2f32. 983 if (!Subtarget->is64Bit()) 984 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom); 985 986 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); 987 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom); 988 989 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal); 990 } 991 992 if (Subtarget->hasSSE41()) { 993 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 994 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 995 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 996 setOperationAction(ISD::FRINT, MVT::f32, Legal); 997 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 998 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 999 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 1000 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 1001 setOperationAction(ISD::FRINT, MVT::f64, Legal); 1002 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 1003 1004 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 1005 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 1006 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 1007 setOperationAction(ISD::FRINT, MVT::v4f32, Legal); 1008 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 1009 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); 1010 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); 1011 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); 1012 setOperationAction(ISD::FRINT, MVT::v2f64, Legal); 1013 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); 1014 1015 // FIXME: Do we need to handle scalar-to-vector here? 1016 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 1017 1018 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 1019 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 1020 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 1021 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 1022 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 1023 1024 // i8 and i16 vectors are custom , because the source register and source 1025 // source memory operand types are not the same width. f32 vectors are 1026 // custom since the immediate controlling the insert encodes additional 1027 // information. 1028 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 1029 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 1031 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 1032 1033 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 1034 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 1037 1038 // FIXME: these should be Legal but thats only for the case where 1039 // the index is constant. For now custom expand to deal with that. 1040 if (Subtarget->is64Bit()) { 1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 1042 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 1043 } 1044 } 1045 1046 if (Subtarget->hasSSE2()) { 1047 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 1048 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 1049 1050 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 1051 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 1052 1053 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 1054 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 1055 1056 // In the customized shift lowering, the legal cases in AVX2 will be 1057 // recognized. 1058 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1059 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1060 1061 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1062 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1063 1064 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1065 1066 setOperationAction(ISD::SDIV, MVT::v8i16, Custom); 1067 setOperationAction(ISD::SDIV, MVT::v4i32, Custom); 1068 } 1069 1070 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) { 1071 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); 1072 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); 1073 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); 1074 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); 1075 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); 1076 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); 1077 1078 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1079 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1080 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1081 1082 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1083 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1084 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1085 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1086 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1087 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal); 1088 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal); 1089 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal); 1090 setOperationAction(ISD::FRINT, MVT::v8f32, Legal); 1091 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal); 1092 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1093 setOperationAction(ISD::FABS, MVT::v8f32, Custom); 1094 1095 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1096 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1097 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1098 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1099 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1100 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); 1101 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); 1102 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal); 1103 setOperationAction(ISD::FRINT, MVT::v4f64, Legal); 1104 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal); 1105 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1106 setOperationAction(ISD::FABS, MVT::v4f64, Custom); 1107 1108 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom); 1109 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom); 1110 1111 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); 1112 1113 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1114 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1115 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1116 1117 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); 1118 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom); 1119 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); 1120 1121 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal); 1122 1123 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1124 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1125 1126 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1127 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1128 1129 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1130 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1131 1132 setOperationAction(ISD::SDIV, MVT::v16i16, Custom); 1133 1134 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1135 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1136 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1137 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1138 1139 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1140 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1141 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1142 1143 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1144 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1145 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1146 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1147 1148 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); 1149 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); 1150 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom); 1151 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); 1152 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom); 1153 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom); 1154 1155 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) { 1156 setOperationAction(ISD::FMA, MVT::v8f32, Legal); 1157 setOperationAction(ISD::FMA, MVT::v4f64, Legal); 1158 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 1159 setOperationAction(ISD::FMA, MVT::v2f64, Legal); 1160 setOperationAction(ISD::FMA, MVT::f32, Legal); 1161 setOperationAction(ISD::FMA, MVT::f64, Legal); 1162 } 1163 1164 if (Subtarget->hasInt256()) { 1165 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1166 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1167 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1168 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1169 1170 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1171 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1172 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1173 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1174 1175 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1176 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1177 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1178 // Don't lower v32i8 because there is no 128-bit byte mul 1179 1180 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1181 1182 setOperationAction(ISD::SDIV, MVT::v8i32, Custom); 1183 } else { 1184 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1185 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1186 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1187 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1188 1189 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1190 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1191 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1192 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1193 1194 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1195 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1196 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1197 // Don't lower v32i8 because there is no 128-bit byte mul 1198 } 1199 1200 // In the customized shift lowering, the legal cases in AVX2 will be 1201 // recognized. 1202 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1203 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1204 1205 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1206 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1207 1208 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1209 1210 // Custom lower several nodes for 256-bit types. 1211 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 1212 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 1213 MVT VT = (MVT::SimpleValueType)i; 1214 1215 // Extract subvector is special because the value type 1216 // (result) is 128-bit but the source is 256-bit wide. 1217 if (VT.is128BitVector()) 1218 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 1219 1220 // Do not attempt to custom lower other non-256-bit vectors 1221 if (!VT.is256BitVector()) 1222 continue; 1223 1224 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 1225 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1226 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1227 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1228 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); 1229 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); 1230 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); 1231 } 1232 1233 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1234 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) { 1235 MVT VT = (MVT::SimpleValueType)i; 1236 1237 // Do not attempt to promote non-256-bit vectors 1238 if (!VT.is256BitVector()) 1239 continue; 1240 1241 setOperationAction(ISD::AND, VT, Promote); 1242 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 1243 setOperationAction(ISD::OR, VT, Promote); 1244 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 1245 setOperationAction(ISD::XOR, VT, Promote); 1246 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 1247 setOperationAction(ISD::LOAD, VT, Promote); 1248 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 1249 setOperationAction(ISD::SELECT, VT, Promote); 1250 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 1251 } 1252 } 1253 1254 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1255 // of this type with custom code. 1256 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 1257 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) { 1258 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1259 Custom); 1260 } 1261 1262 // We want to custom lower some of our intrinsics. 1263 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1264 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 1265 1266 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1267 // handle type legalization for these operations here. 1268 // 1269 // FIXME: We really should do custom legalization for addition and 1270 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1271 // than generic legalization for 64-bit multiplication-with-overflow, though. 1272 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1273 // Add/Sub/Mul with overflow operations are custom lowered. 1274 MVT VT = IntVTs[i]; 1275 setOperationAction(ISD::SADDO, VT, Custom); 1276 setOperationAction(ISD::UADDO, VT, Custom); 1277 setOperationAction(ISD::SSUBO, VT, Custom); 1278 setOperationAction(ISD::USUBO, VT, Custom); 1279 setOperationAction(ISD::SMULO, VT, Custom); 1280 setOperationAction(ISD::UMULO, VT, Custom); 1281 } 1282 1283 // There are no 8-bit 3-address imul/mul instructions 1284 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1285 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1286 1287 if (!Subtarget->is64Bit()) { 1288 // These libcalls are not available in 32-bit. 1289 setLibcallName(RTLIB::SHL_I128, 0); 1290 setLibcallName(RTLIB::SRL_I128, 0); 1291 setLibcallName(RTLIB::SRA_I128, 0); 1292 } 1293 1294 // Combine sin / cos into one node or libcall if possible. 1295 if (Subtarget->hasSinCos()) { 1296 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 1297 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 1298 if (Subtarget->isTargetDarwin()) { 1299 // For MacOSX, we don't want to the normal expansion of a libcall to 1300 // sincos. We want to issue a libcall to __sincos_stret to avoid memory 1301 // traffic. 1302 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); 1303 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); 1304 } 1305 } 1306 1307 // We have target-specific dag combine patterns for the following nodes: 1308 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1309 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1310 setTargetDAGCombine(ISD::VSELECT); 1311 setTargetDAGCombine(ISD::SELECT); 1312 setTargetDAGCombine(ISD::SHL); 1313 setTargetDAGCombine(ISD::SRA); 1314 setTargetDAGCombine(ISD::SRL); 1315 setTargetDAGCombine(ISD::OR); 1316 setTargetDAGCombine(ISD::AND); 1317 setTargetDAGCombine(ISD::ADD); 1318 setTargetDAGCombine(ISD::FADD); 1319 setTargetDAGCombine(ISD::FSUB); 1320 setTargetDAGCombine(ISD::FMA); 1321 setTargetDAGCombine(ISD::SUB); 1322 setTargetDAGCombine(ISD::LOAD); 1323 setTargetDAGCombine(ISD::STORE); 1324 setTargetDAGCombine(ISD::ZERO_EXTEND); 1325 setTargetDAGCombine(ISD::ANY_EXTEND); 1326 setTargetDAGCombine(ISD::SIGN_EXTEND); 1327 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); 1328 setTargetDAGCombine(ISD::TRUNCATE); 1329 setTargetDAGCombine(ISD::SINT_TO_FP); 1330 setTargetDAGCombine(ISD::SETCC); 1331 if (Subtarget->is64Bit()) 1332 setTargetDAGCombine(ISD::MUL); 1333 setTargetDAGCombine(ISD::XOR); 1334 1335 computeRegisterProperties(); 1336 1337 // On Darwin, -Os means optimize for size without hurting performance, 1338 // do not reduce the limit. 1339 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1340 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1341 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1342 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1343 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1344 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1345 setPrefLoopAlignment(4); // 2^4 bytes. 1346 BenefitFromCodePlacementOpt = true; 1347 1348 // Predictable cmov don't hurt on atom because it's in-order. 1349 PredictableSelectIsExpensive = !Subtarget->isAtom(); 1350 1351 setPrefFunctionAlignment(4); // 2^4 bytes. 1352} 1353 1354EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1355 if (!VT.isVector()) return MVT::i8; 1356 return VT.changeVectorElementTypeToInteger(); 1357} 1358 1359/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1360/// the desired ByVal argument alignment. 1361static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1362 if (MaxAlign == 16) 1363 return; 1364 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1365 if (VTy->getBitWidth() == 128) 1366 MaxAlign = 16; 1367 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1368 unsigned EltAlign = 0; 1369 getMaxByValAlign(ATy->getElementType(), EltAlign); 1370 if (EltAlign > MaxAlign) 1371 MaxAlign = EltAlign; 1372 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1373 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1374 unsigned EltAlign = 0; 1375 getMaxByValAlign(STy->getElementType(i), EltAlign); 1376 if (EltAlign > MaxAlign) 1377 MaxAlign = EltAlign; 1378 if (MaxAlign == 16) 1379 break; 1380 } 1381 } 1382} 1383 1384/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1385/// function arguments in the caller parameter area. For X86, aggregates 1386/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1387/// are at 4-byte boundaries. 1388unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1389 if (Subtarget->is64Bit()) { 1390 // Max of 8 and alignment of type. 1391 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1392 if (TyAlign > 8) 1393 return TyAlign; 1394 return 8; 1395 } 1396 1397 unsigned Align = 4; 1398 if (Subtarget->hasSSE1()) 1399 getMaxByValAlign(Ty, Align); 1400 return Align; 1401} 1402 1403/// getOptimalMemOpType - Returns the target specific optimal type for load 1404/// and store operations as a result of memset, memcpy, and memmove 1405/// lowering. If DstAlign is zero that means it's safe to destination 1406/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1407/// means there isn't a need to check it against alignment requirement, 1408/// probably because the source does not need to be loaded. If 'IsMemset' is 1409/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 1410/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 1411/// source is constant so it does not need to be loaded. 1412/// It returns EVT::Other if the type should be determined using generic 1413/// target-independent logic. 1414EVT 1415X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1416 unsigned DstAlign, unsigned SrcAlign, 1417 bool IsMemset, bool ZeroMemset, 1418 bool MemcpyStrSrc, 1419 MachineFunction &MF) const { 1420 const Function *F = MF.getFunction(); 1421 if ((!IsMemset || ZeroMemset) && 1422 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 1423 Attribute::NoImplicitFloat)) { 1424 if (Size >= 16 && 1425 (Subtarget->isUnalignedMemAccessFast() || 1426 ((DstAlign == 0 || DstAlign >= 16) && 1427 (SrcAlign == 0 || SrcAlign >= 16)))) { 1428 if (Size >= 32) { 1429 if (Subtarget->hasInt256()) 1430 return MVT::v8i32; 1431 if (Subtarget->hasFp256()) 1432 return MVT::v8f32; 1433 } 1434 if (Subtarget->hasSSE2()) 1435 return MVT::v4i32; 1436 if (Subtarget->hasSSE1()) 1437 return MVT::v4f32; 1438 } else if (!MemcpyStrSrc && Size >= 8 && 1439 !Subtarget->is64Bit() && 1440 Subtarget->hasSSE2()) { 1441 // Do not use f64 to lower memcpy if source is string constant. It's 1442 // better to use i32 to avoid the loads. 1443 return MVT::f64; 1444 } 1445 } 1446 if (Subtarget->is64Bit() && Size >= 8) 1447 return MVT::i64; 1448 return MVT::i32; 1449} 1450 1451bool X86TargetLowering::isSafeMemOpType(MVT VT) const { 1452 if (VT == MVT::f32) 1453 return X86ScalarSSEf32; 1454 else if (VT == MVT::f64) 1455 return X86ScalarSSEf64; 1456 return true; 1457} 1458 1459bool 1460X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 1461 if (Fast) 1462 *Fast = Subtarget->isUnalignedMemAccessFast(); 1463 return true; 1464} 1465 1466/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1467/// current function. The returned value is a member of the 1468/// MachineJumpTableInfo::JTEntryKind enum. 1469unsigned X86TargetLowering::getJumpTableEncoding() const { 1470 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1471 // symbol. 1472 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1473 Subtarget->isPICStyleGOT()) 1474 return MachineJumpTableInfo::EK_Custom32; 1475 1476 // Otherwise, use the normal jump table encoding heuristics. 1477 return TargetLowering::getJumpTableEncoding(); 1478} 1479 1480const MCExpr * 1481X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1482 const MachineBasicBlock *MBB, 1483 unsigned uid,MCContext &Ctx) const{ 1484 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1485 Subtarget->isPICStyleGOT()); 1486 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1487 // entries. 1488 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1489 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1490} 1491 1492/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1493/// jumptable. 1494SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1495 SelectionDAG &DAG) const { 1496 if (!Subtarget->is64Bit()) 1497 // This doesn't have DebugLoc associated with it, but is not really the 1498 // same as a Register. 1499 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1500 return Table; 1501} 1502 1503/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1504/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1505/// MCExpr. 1506const MCExpr *X86TargetLowering:: 1507getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1508 MCContext &Ctx) const { 1509 // X86-64 uses RIP relative addressing based on the jump table label. 1510 if (Subtarget->isPICStyleRIPRel()) 1511 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1512 1513 // Otherwise, the reference is relative to the PIC base. 1514 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1515} 1516 1517// FIXME: Why this routine is here? Move to RegInfo! 1518std::pair<const TargetRegisterClass*, uint8_t> 1519X86TargetLowering::findRepresentativeClass(MVT VT) const{ 1520 const TargetRegisterClass *RRC = 0; 1521 uint8_t Cost = 1; 1522 switch (VT.SimpleTy) { 1523 default: 1524 return TargetLowering::findRepresentativeClass(VT); 1525 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1526 RRC = Subtarget->is64Bit() ? 1527 (const TargetRegisterClass*)&X86::GR64RegClass : 1528 (const TargetRegisterClass*)&X86::GR32RegClass; 1529 break; 1530 case MVT::x86mmx: 1531 RRC = &X86::VR64RegClass; 1532 break; 1533 case MVT::f32: case MVT::f64: 1534 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1535 case MVT::v4f32: case MVT::v2f64: 1536 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1537 case MVT::v4f64: 1538 RRC = &X86::VR128RegClass; 1539 break; 1540 } 1541 return std::make_pair(RRC, Cost); 1542} 1543 1544bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1545 unsigned &Offset) const { 1546 if (!Subtarget->isTargetLinux()) 1547 return false; 1548 1549 if (Subtarget->is64Bit()) { 1550 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1551 Offset = 0x28; 1552 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1553 AddressSpace = 256; 1554 else 1555 AddressSpace = 257; 1556 } else { 1557 // %gs:0x14 on i386 1558 Offset = 0x14; 1559 AddressSpace = 256; 1560 } 1561 return true; 1562} 1563 1564//===----------------------------------------------------------------------===// 1565// Return Value Calling Convention Implementation 1566//===----------------------------------------------------------------------===// 1567 1568#include "X86GenCallingConv.inc" 1569 1570bool 1571X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1572 MachineFunction &MF, bool isVarArg, 1573 const SmallVectorImpl<ISD::OutputArg> &Outs, 1574 LLVMContext &Context) const { 1575 SmallVector<CCValAssign, 16> RVLocs; 1576 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1577 RVLocs, Context); 1578 return CCInfo.CheckReturn(Outs, RetCC_X86); 1579} 1580 1581SDValue 1582X86TargetLowering::LowerReturn(SDValue Chain, 1583 CallingConv::ID CallConv, bool isVarArg, 1584 const SmallVectorImpl<ISD::OutputArg> &Outs, 1585 const SmallVectorImpl<SDValue> &OutVals, 1586 DebugLoc dl, SelectionDAG &DAG) const { 1587 MachineFunction &MF = DAG.getMachineFunction(); 1588 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1589 1590 SmallVector<CCValAssign, 16> RVLocs; 1591 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1592 RVLocs, *DAG.getContext()); 1593 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1594 1595 SDValue Flag; 1596 SmallVector<SDValue, 6> RetOps; 1597 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1598 // Operand #1 = Bytes To Pop 1599 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1600 MVT::i16)); 1601 1602 // Copy the result values into the output registers. 1603 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1604 CCValAssign &VA = RVLocs[i]; 1605 assert(VA.isRegLoc() && "Can only return in registers!"); 1606 SDValue ValToCopy = OutVals[i]; 1607 EVT ValVT = ValToCopy.getValueType(); 1608 1609 // Promote values to the appropriate types 1610 if (VA.getLocInfo() == CCValAssign::SExt) 1611 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1612 else if (VA.getLocInfo() == CCValAssign::ZExt) 1613 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1614 else if (VA.getLocInfo() == CCValAssign::AExt) 1615 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1616 else if (VA.getLocInfo() == CCValAssign::BCvt) 1617 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); 1618 1619 // If this is x86-64, and we disabled SSE, we can't return FP values, 1620 // or SSE or MMX vectors. 1621 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1622 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1623 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1624 report_fatal_error("SSE register return with SSE disabled"); 1625 } 1626 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1627 // llvm-gcc has never done it right and no one has noticed, so this 1628 // should be OK for now. 1629 if (ValVT == MVT::f64 && 1630 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1631 report_fatal_error("SSE2 register return with SSE2 disabled"); 1632 1633 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1634 // the RET instruction and handled by the FP Stackifier. 1635 if (VA.getLocReg() == X86::ST0 || 1636 VA.getLocReg() == X86::ST1) { 1637 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1638 // change the value to the FP stack register class. 1639 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1640 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1641 RetOps.push_back(ValToCopy); 1642 // Don't emit a copytoreg. 1643 continue; 1644 } 1645 1646 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1647 // which is returned in RAX / RDX. 1648 if (Subtarget->is64Bit()) { 1649 if (ValVT == MVT::x86mmx) { 1650 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1651 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1652 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1653 ValToCopy); 1654 // If we don't have SSE2 available, convert to v4f32 so the generated 1655 // register is legal. 1656 if (!Subtarget->hasSSE2()) 1657 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1658 } 1659 } 1660 } 1661 1662 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1663 Flag = Chain.getValue(1); 1664 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1665 } 1666 1667 // The x86-64 ABIs require that for returning structs by value we copy 1668 // the sret argument into %rax/%eax (depending on ABI) for the return. 1669 // We saved the argument into a virtual register in the entry block, 1670 // so now we copy the value out and into %rax/%eax. 1671 if (Subtarget->is64Bit() && 1672 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1673 MachineFunction &MF = DAG.getMachineFunction(); 1674 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1675 unsigned Reg = FuncInfo->getSRetReturnReg(); 1676 assert(Reg && 1677 "SRetReturnReg should have been set in LowerFormalArguments()."); 1678 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1679 1680 unsigned RetValReg = Subtarget->isTarget64BitILP32() ? X86::EAX : X86::RAX; 1681 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag); 1682 Flag = Chain.getValue(1); 1683 1684 // RAX/EAX now acts like a return value. 1685 RetOps.push_back(DAG.getRegister(RetValReg, MVT::i64)); 1686 } 1687 1688 RetOps[0] = Chain; // Update chain. 1689 1690 // Add the flag if we have it. 1691 if (Flag.getNode()) 1692 RetOps.push_back(Flag); 1693 1694 return DAG.getNode(X86ISD::RET_FLAG, dl, 1695 MVT::Other, &RetOps[0], RetOps.size()); 1696} 1697 1698bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1699 if (N->getNumValues() != 1) 1700 return false; 1701 if (!N->hasNUsesOfValue(1, 0)) 1702 return false; 1703 1704 SDValue TCChain = Chain; 1705 SDNode *Copy = *N->use_begin(); 1706 if (Copy->getOpcode() == ISD::CopyToReg) { 1707 // If the copy has a glue operand, we conservatively assume it isn't safe to 1708 // perform a tail call. 1709 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1710 return false; 1711 TCChain = Copy->getOperand(0); 1712 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1713 return false; 1714 1715 bool HasRet = false; 1716 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1717 UI != UE; ++UI) { 1718 if (UI->getOpcode() != X86ISD::RET_FLAG) 1719 return false; 1720 HasRet = true; 1721 } 1722 1723 if (!HasRet) 1724 return false; 1725 1726 Chain = TCChain; 1727 return true; 1728} 1729 1730MVT 1731X86TargetLowering::getTypeForExtArgOrReturn(MVT VT, 1732 ISD::NodeType ExtendKind) const { 1733 MVT ReturnMVT; 1734 // TODO: Is this also valid on 32-bit? 1735 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1736 ReturnMVT = MVT::i8; 1737 else 1738 ReturnMVT = MVT::i32; 1739 1740 MVT MinVT = getRegisterType(ReturnMVT); 1741 return VT.bitsLT(MinVT) ? MinVT : VT; 1742} 1743 1744/// LowerCallResult - Lower the result values of a call into the 1745/// appropriate copies out of appropriate physical registers. 1746/// 1747SDValue 1748X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1749 CallingConv::ID CallConv, bool isVarArg, 1750 const SmallVectorImpl<ISD::InputArg> &Ins, 1751 DebugLoc dl, SelectionDAG &DAG, 1752 SmallVectorImpl<SDValue> &InVals) const { 1753 1754 // Assign locations to each value returned by this call. 1755 SmallVector<CCValAssign, 16> RVLocs; 1756 bool Is64Bit = Subtarget->is64Bit(); 1757 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1758 getTargetMachine(), RVLocs, *DAG.getContext()); 1759 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1760 1761 // Copy all of the result registers out of their specified physreg. 1762 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1763 CCValAssign &VA = RVLocs[i]; 1764 EVT CopyVT = VA.getValVT(); 1765 1766 // If this is x86-64, and we disabled SSE, we can't return FP values 1767 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1768 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1769 report_fatal_error("SSE register return with SSE disabled"); 1770 } 1771 1772 SDValue Val; 1773 1774 // If this is a call to a function that returns an fp value on the floating 1775 // point stack, we must guarantee the value is popped from the stack, so 1776 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1777 // if the return value is not used. We use the FpPOP_RETVAL instruction 1778 // instead. 1779 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1780 // If we prefer to use the value in xmm registers, copy it out as f80 and 1781 // use a truncate to move it from fp stack reg to xmm reg. 1782 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1783 SDValue Ops[] = { Chain, InFlag }; 1784 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1785 MVT::Other, MVT::Glue, Ops, 2), 1); 1786 Val = Chain.getValue(0); 1787 1788 // Round the f80 to the right size, which also moves it to the appropriate 1789 // xmm register. 1790 if (CopyVT != VA.getValVT()) 1791 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1792 // This truncation won't change the value. 1793 DAG.getIntPtrConstant(1)); 1794 } else { 1795 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1796 CopyVT, InFlag).getValue(1); 1797 Val = Chain.getValue(0); 1798 } 1799 InFlag = Chain.getValue(2); 1800 InVals.push_back(Val); 1801 } 1802 1803 return Chain; 1804} 1805 1806//===----------------------------------------------------------------------===// 1807// C & StdCall & Fast Calling Convention implementation 1808//===----------------------------------------------------------------------===// 1809// StdCall calling convention seems to be standard for many Windows' API 1810// routines and around. It differs from C calling convention just a little: 1811// callee should clean up the stack, not caller. Symbols should be also 1812// decorated in some fancy way :) It doesn't support any vector arguments. 1813// For info on fast calling convention see Fast Calling Convention (tail call) 1814// implementation LowerX86_32FastCCCallTo. 1815 1816/// CallIsStructReturn - Determines whether a call uses struct return 1817/// semantics. 1818enum StructReturnType { 1819 NotStructReturn, 1820 RegStructReturn, 1821 StackStructReturn 1822}; 1823static StructReturnType 1824callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1825 if (Outs.empty()) 1826 return NotStructReturn; 1827 1828 const ISD::ArgFlagsTy &Flags = Outs[0].Flags; 1829 if (!Flags.isSRet()) 1830 return NotStructReturn; 1831 if (Flags.isInReg()) 1832 return RegStructReturn; 1833 return StackStructReturn; 1834} 1835 1836/// ArgsAreStructReturn - Determines whether a function uses struct 1837/// return semantics. 1838static StructReturnType 1839argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1840 if (Ins.empty()) 1841 return NotStructReturn; 1842 1843 const ISD::ArgFlagsTy &Flags = Ins[0].Flags; 1844 if (!Flags.isSRet()) 1845 return NotStructReturn; 1846 if (Flags.isInReg()) 1847 return RegStructReturn; 1848 return StackStructReturn; 1849} 1850 1851/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1852/// by "Src" to address "Dst" with size and alignment information specified by 1853/// the specific parameter attribute. The copy will be passed as a byval 1854/// function parameter. 1855static SDValue 1856CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1857 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1858 DebugLoc dl) { 1859 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1860 1861 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1862 /*isVolatile*/false, /*AlwaysInline=*/true, 1863 MachinePointerInfo(), MachinePointerInfo()); 1864} 1865 1866/// IsTailCallConvention - Return true if the calling convention is one that 1867/// supports tail call optimization. 1868static bool IsTailCallConvention(CallingConv::ID CC) { 1869 return (CC == CallingConv::Fast || CC == CallingConv::GHC || 1870 CC == CallingConv::HiPE); 1871} 1872 1873bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1874 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1875 return false; 1876 1877 CallSite CS(CI); 1878 CallingConv::ID CalleeCC = CS.getCallingConv(); 1879 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1880 return false; 1881 1882 return true; 1883} 1884 1885/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1886/// a tailcall target by changing its ABI. 1887static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1888 bool GuaranteedTailCallOpt) { 1889 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1890} 1891 1892SDValue 1893X86TargetLowering::LowerMemArgument(SDValue Chain, 1894 CallingConv::ID CallConv, 1895 const SmallVectorImpl<ISD::InputArg> &Ins, 1896 DebugLoc dl, SelectionDAG &DAG, 1897 const CCValAssign &VA, 1898 MachineFrameInfo *MFI, 1899 unsigned i) const { 1900 // Create the nodes corresponding to a load from this parameter slot. 1901 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1902 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1903 getTargetMachine().Options.GuaranteedTailCallOpt); 1904 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1905 EVT ValVT; 1906 1907 // If value is passed by pointer we have address passed instead of the value 1908 // itself. 1909 if (VA.getLocInfo() == CCValAssign::Indirect) 1910 ValVT = VA.getLocVT(); 1911 else 1912 ValVT = VA.getValVT(); 1913 1914 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1915 // changed with more analysis. 1916 // In case of tail call optimization mark all arguments mutable. Since they 1917 // could be overwritten by lowering of arguments in case of a tail call. 1918 if (Flags.isByVal()) { 1919 unsigned Bytes = Flags.getByValSize(); 1920 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1921 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1922 return DAG.getFrameIndex(FI, getPointerTy()); 1923 } else { 1924 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1925 VA.getLocMemOffset(), isImmutable); 1926 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1927 return DAG.getLoad(ValVT, dl, Chain, FIN, 1928 MachinePointerInfo::getFixedStack(FI), 1929 false, false, false, 0); 1930 } 1931} 1932 1933SDValue 1934X86TargetLowering::LowerFormalArguments(SDValue Chain, 1935 CallingConv::ID CallConv, 1936 bool isVarArg, 1937 const SmallVectorImpl<ISD::InputArg> &Ins, 1938 DebugLoc dl, 1939 SelectionDAG &DAG, 1940 SmallVectorImpl<SDValue> &InVals) 1941 const { 1942 MachineFunction &MF = DAG.getMachineFunction(); 1943 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1944 1945 const Function* Fn = MF.getFunction(); 1946 if (Fn->hasExternalLinkage() && 1947 Subtarget->isTargetCygMing() && 1948 Fn->getName() == "main") 1949 FuncInfo->setForceFramePointer(true); 1950 1951 MachineFrameInfo *MFI = MF.getFrameInfo(); 1952 bool Is64Bit = Subtarget->is64Bit(); 1953 bool IsWindows = Subtarget->isTargetWindows(); 1954 bool IsWin64 = Subtarget->isTargetWin64(); 1955 1956 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1957 "Var args not supported with calling convention fastcc, ghc or hipe"); 1958 1959 // Assign locations to all of the incoming arguments. 1960 SmallVector<CCValAssign, 16> ArgLocs; 1961 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1962 ArgLocs, *DAG.getContext()); 1963 1964 // Allocate shadow area for Win64 1965 if (IsWin64) { 1966 CCInfo.AllocateStack(32, 8); 1967 } 1968 1969 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1970 1971 unsigned LastVal = ~0U; 1972 SDValue ArgValue; 1973 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1974 CCValAssign &VA = ArgLocs[i]; 1975 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1976 // places. 1977 assert(VA.getValNo() != LastVal && 1978 "Don't support value assigned to multiple locs yet"); 1979 (void)LastVal; 1980 LastVal = VA.getValNo(); 1981 1982 if (VA.isRegLoc()) { 1983 EVT RegVT = VA.getLocVT(); 1984 const TargetRegisterClass *RC; 1985 if (RegVT == MVT::i32) 1986 RC = &X86::GR32RegClass; 1987 else if (Is64Bit && RegVT == MVT::i64) 1988 RC = &X86::GR64RegClass; 1989 else if (RegVT == MVT::f32) 1990 RC = &X86::FR32RegClass; 1991 else if (RegVT == MVT::f64) 1992 RC = &X86::FR64RegClass; 1993 else if (RegVT.is256BitVector()) 1994 RC = &X86::VR256RegClass; 1995 else if (RegVT.is128BitVector()) 1996 RC = &X86::VR128RegClass; 1997 else if (RegVT == MVT::x86mmx) 1998 RC = &X86::VR64RegClass; 1999 else 2000 llvm_unreachable("Unknown argument type!"); 2001 2002 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2003 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2004 2005 // If this is an 8 or 16-bit value, it is really passed promoted to 32 2006 // bits. Insert an assert[sz]ext to capture this, then truncate to the 2007 // right size. 2008 if (VA.getLocInfo() == CCValAssign::SExt) 2009 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2010 DAG.getValueType(VA.getValVT())); 2011 else if (VA.getLocInfo() == CCValAssign::ZExt) 2012 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2013 DAG.getValueType(VA.getValVT())); 2014 else if (VA.getLocInfo() == CCValAssign::BCvt) 2015 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2016 2017 if (VA.isExtInLoc()) { 2018 // Handle MMX values passed in XMM regs. 2019 if (RegVT.isVector()) 2020 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue); 2021 else 2022 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2023 } 2024 } else { 2025 assert(VA.isMemLoc()); 2026 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 2027 } 2028 2029 // If value is passed via pointer - do a load. 2030 if (VA.getLocInfo() == CCValAssign::Indirect) 2031 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 2032 MachinePointerInfo(), false, false, false, 0); 2033 2034 InVals.push_back(ArgValue); 2035 } 2036 2037 // The x86-64 ABIs require that for returning structs by value we copy 2038 // the sret argument into %rax/%eax (depending on ABI) for the return. 2039 // Save the argument into a virtual register so that we can access it 2040 // from the return points. 2041 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 2042 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2043 unsigned Reg = FuncInfo->getSRetReturnReg(); 2044 if (!Reg) { 2045 MVT PtrTy = getPointerTy(); 2046 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); 2047 FuncInfo->setSRetReturnReg(Reg); 2048 } 2049 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2050 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2051 } 2052 2053 unsigned StackSize = CCInfo.getNextStackOffset(); 2054 // Align stack specially for tail calls. 2055 if (FuncIsMadeTailCallSafe(CallConv, 2056 MF.getTarget().Options.GuaranteedTailCallOpt)) 2057 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 2058 2059 // If the function takes variable number of arguments, make a frame index for 2060 // the start of the first vararg value... for expansion of llvm.va_start. 2061 if (isVarArg) { 2062 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 2063 CallConv != CallingConv::X86_ThisCall)) { 2064 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 2065 } 2066 if (Is64Bit) { 2067 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 2068 2069 // FIXME: We should really autogenerate these arrays 2070 static const uint16_t GPR64ArgRegsWin64[] = { 2071 X86::RCX, X86::RDX, X86::R8, X86::R9 2072 }; 2073 static const uint16_t GPR64ArgRegs64Bit[] = { 2074 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 2075 }; 2076 static const uint16_t XMMArgRegs64Bit[] = { 2077 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2078 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2079 }; 2080 const uint16_t *GPR64ArgRegs; 2081 unsigned NumXMMRegs = 0; 2082 2083 if (IsWin64) { 2084 // The XMM registers which might contain var arg parameters are shadowed 2085 // in their paired GPR. So we only need to save the GPR to their home 2086 // slots. 2087 TotalNumIntRegs = 4; 2088 GPR64ArgRegs = GPR64ArgRegsWin64; 2089 } else { 2090 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 2091 GPR64ArgRegs = GPR64ArgRegs64Bit; 2092 2093 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 2094 TotalNumXMMRegs); 2095 } 2096 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 2097 TotalNumIntRegs); 2098 2099 bool NoImplicitFloatOps = Fn->getAttributes(). 2100 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 2101 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 2102 "SSE register cannot be used when SSE is disabled!"); 2103 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 2104 NoImplicitFloatOps) && 2105 "SSE register cannot be used when SSE is disabled!"); 2106 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 2107 !Subtarget->hasSSE1()) 2108 // Kernel mode asks for SSE to be disabled, so don't push them 2109 // on the stack. 2110 TotalNumXMMRegs = 0; 2111 2112 if (IsWin64) { 2113 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 2114 // Get to the caller-allocated home save location. Add 8 to account 2115 // for the return address. 2116 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 2117 FuncInfo->setRegSaveFrameIndex( 2118 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 2119 // Fixup to set vararg frame on shadow area (4 x i64). 2120 if (NumIntRegs < 4) 2121 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 2122 } else { 2123 // For X86-64, if there are vararg parameters that are passed via 2124 // registers, then we must store them to their spots on the stack so 2125 // they may be loaded by deferencing the result of va_next. 2126 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 2127 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 2128 FuncInfo->setRegSaveFrameIndex( 2129 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 2130 false)); 2131 } 2132 2133 // Store the integer parameter registers. 2134 SmallVector<SDValue, 8> MemOps; 2135 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2136 getPointerTy()); 2137 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2138 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2139 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2140 DAG.getIntPtrConstant(Offset)); 2141 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2142 &X86::GR64RegClass); 2143 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2144 SDValue Store = 2145 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2146 MachinePointerInfo::getFixedStack( 2147 FuncInfo->getRegSaveFrameIndex(), Offset), 2148 false, false, 0); 2149 MemOps.push_back(Store); 2150 Offset += 8; 2151 } 2152 2153 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2154 // Now store the XMM (fp + vector) parameter registers. 2155 SmallVector<SDValue, 11> SaveXMMOps; 2156 SaveXMMOps.push_back(Chain); 2157 2158 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass); 2159 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2160 SaveXMMOps.push_back(ALVal); 2161 2162 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2163 FuncInfo->getRegSaveFrameIndex())); 2164 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2165 FuncInfo->getVarArgsFPOffset())); 2166 2167 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2168 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2169 &X86::VR128RegClass); 2170 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2171 SaveXMMOps.push_back(Val); 2172 } 2173 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2174 MVT::Other, 2175 &SaveXMMOps[0], SaveXMMOps.size())); 2176 } 2177 2178 if (!MemOps.empty()) 2179 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2180 &MemOps[0], MemOps.size()); 2181 } 2182 } 2183 2184 // Some CCs need callee pop. 2185 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2186 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2187 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2188 } else { 2189 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2190 // If this is an sret function, the return should pop the hidden pointer. 2191 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2192 argsAreStructReturn(Ins) == StackStructReturn) 2193 FuncInfo->setBytesToPopOnReturn(4); 2194 } 2195 2196 if (!Is64Bit) { 2197 // RegSaveFrameIndex is X86-64 only. 2198 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2199 if (CallConv == CallingConv::X86_FastCall || 2200 CallConv == CallingConv::X86_ThisCall) 2201 // fastcc functions can't have varargs. 2202 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2203 } 2204 2205 FuncInfo->setArgumentStackSize(StackSize); 2206 2207 return Chain; 2208} 2209 2210SDValue 2211X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2212 SDValue StackPtr, SDValue Arg, 2213 DebugLoc dl, SelectionDAG &DAG, 2214 const CCValAssign &VA, 2215 ISD::ArgFlagsTy Flags) const { 2216 unsigned LocMemOffset = VA.getLocMemOffset(); 2217 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2218 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2219 if (Flags.isByVal()) 2220 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2221 2222 return DAG.getStore(Chain, dl, Arg, PtrOff, 2223 MachinePointerInfo::getStack(LocMemOffset), 2224 false, false, 0); 2225} 2226 2227/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2228/// optimization is performed and it is required. 2229SDValue 2230X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2231 SDValue &OutRetAddr, SDValue Chain, 2232 bool IsTailCall, bool Is64Bit, 2233 int FPDiff, DebugLoc dl) const { 2234 // Adjust the Return address stack slot. 2235 EVT VT = getPointerTy(); 2236 OutRetAddr = getReturnAddressFrameIndex(DAG); 2237 2238 // Load the "old" Return address. 2239 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2240 false, false, false, 0); 2241 return SDValue(OutRetAddr.getNode(), 1); 2242} 2243 2244/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2245/// optimization is performed and it is required (FPDiff!=0). 2246static SDValue 2247EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2248 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, 2249 unsigned SlotSize, int FPDiff, DebugLoc dl) { 2250 // Store the return address to the appropriate stack slot. 2251 if (!FPDiff) return Chain; 2252 // Calculate the new stack slot for the return address. 2253 int NewReturnAddrFI = 2254 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2255 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT); 2256 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2257 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2258 false, false, 0); 2259 return Chain; 2260} 2261 2262SDValue 2263X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2264 SmallVectorImpl<SDValue> &InVals) const { 2265 SelectionDAG &DAG = CLI.DAG; 2266 DebugLoc &dl = CLI.DL; 2267 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2268 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2269 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2270 SDValue Chain = CLI.Chain; 2271 SDValue Callee = CLI.Callee; 2272 CallingConv::ID CallConv = CLI.CallConv; 2273 bool &isTailCall = CLI.IsTailCall; 2274 bool isVarArg = CLI.IsVarArg; 2275 2276 MachineFunction &MF = DAG.getMachineFunction(); 2277 bool Is64Bit = Subtarget->is64Bit(); 2278 bool IsWin64 = Subtarget->isTargetWin64(); 2279 bool IsWindows = Subtarget->isTargetWindows(); 2280 StructReturnType SR = callIsStructReturn(Outs); 2281 bool IsSibcall = false; 2282 2283 if (MF.getTarget().Options.DisableTailCalls) 2284 isTailCall = false; 2285 2286 if (isTailCall) { 2287 // Check if it's really possible to do a tail call. 2288 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2289 isVarArg, SR != NotStructReturn, 2290 MF.getFunction()->hasStructRetAttr(), CLI.RetTy, 2291 Outs, OutVals, Ins, DAG); 2292 2293 // Sibcalls are automatically detected tailcalls which do not require 2294 // ABI changes. 2295 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2296 IsSibcall = true; 2297 2298 if (isTailCall) 2299 ++NumTailCalls; 2300 } 2301 2302 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2303 "Var args not supported with calling convention fastcc, ghc or hipe"); 2304 2305 // Analyze operands of the call, assigning locations to each operand. 2306 SmallVector<CCValAssign, 16> ArgLocs; 2307 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2308 ArgLocs, *DAG.getContext()); 2309 2310 // Allocate shadow area for Win64 2311 if (IsWin64) { 2312 CCInfo.AllocateStack(32, 8); 2313 } 2314 2315 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2316 2317 // Get a count of how many bytes are to be pushed on the stack. 2318 unsigned NumBytes = CCInfo.getNextStackOffset(); 2319 if (IsSibcall) 2320 // This is a sibcall. The memory operands are available in caller's 2321 // own caller's stack. 2322 NumBytes = 0; 2323 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2324 IsTailCallConvention(CallConv)) 2325 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2326 2327 int FPDiff = 0; 2328 if (isTailCall && !IsSibcall) { 2329 // Lower arguments at fp - stackoffset + fpdiff. 2330 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>(); 2331 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn(); 2332 2333 FPDiff = NumBytesCallerPushed - NumBytes; 2334 2335 // Set the delta of movement of the returnaddr stackslot. 2336 // But only set if delta is greater than previous delta. 2337 if (FPDiff < X86Info->getTCReturnAddrDelta()) 2338 X86Info->setTCReturnAddrDelta(FPDiff); 2339 } 2340 2341 if (!IsSibcall) 2342 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2343 2344 SDValue RetAddrFrIdx; 2345 // Load return address for tail calls. 2346 if (isTailCall && FPDiff) 2347 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2348 Is64Bit, FPDiff, dl); 2349 2350 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2351 SmallVector<SDValue, 8> MemOpChains; 2352 SDValue StackPtr; 2353 2354 // Walk the register/memloc assignments, inserting copies/loads. In the case 2355 // of tail call optimization arguments are handle later. 2356 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2357 CCValAssign &VA = ArgLocs[i]; 2358 EVT RegVT = VA.getLocVT(); 2359 SDValue Arg = OutVals[i]; 2360 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2361 bool isByVal = Flags.isByVal(); 2362 2363 // Promote the value if needed. 2364 switch (VA.getLocInfo()) { 2365 default: llvm_unreachable("Unknown loc info!"); 2366 case CCValAssign::Full: break; 2367 case CCValAssign::SExt: 2368 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2369 break; 2370 case CCValAssign::ZExt: 2371 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2372 break; 2373 case CCValAssign::AExt: 2374 if (RegVT.is128BitVector()) { 2375 // Special case: passing MMX values in XMM registers. 2376 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2377 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2378 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2379 } else 2380 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2381 break; 2382 case CCValAssign::BCvt: 2383 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2384 break; 2385 case CCValAssign::Indirect: { 2386 // Store the argument. 2387 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2388 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2389 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2390 MachinePointerInfo::getFixedStack(FI), 2391 false, false, 0); 2392 Arg = SpillSlot; 2393 break; 2394 } 2395 } 2396 2397 if (VA.isRegLoc()) { 2398 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2399 if (isVarArg && IsWin64) { 2400 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2401 // shadow reg if callee is a varargs function. 2402 unsigned ShadowReg = 0; 2403 switch (VA.getLocReg()) { 2404 case X86::XMM0: ShadowReg = X86::RCX; break; 2405 case X86::XMM1: ShadowReg = X86::RDX; break; 2406 case X86::XMM2: ShadowReg = X86::R8; break; 2407 case X86::XMM3: ShadowReg = X86::R9; break; 2408 } 2409 if (ShadowReg) 2410 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2411 } 2412 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2413 assert(VA.isMemLoc()); 2414 if (StackPtr.getNode() == 0) 2415 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(), 2416 getPointerTy()); 2417 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2418 dl, DAG, VA, Flags)); 2419 } 2420 } 2421 2422 if (!MemOpChains.empty()) 2423 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2424 &MemOpChains[0], MemOpChains.size()); 2425 2426 if (Subtarget->isPICStyleGOT()) { 2427 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2428 // GOT pointer. 2429 if (!isTailCall) { 2430 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX), 2431 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()))); 2432 } else { 2433 // If we are tail calling and generating PIC/GOT style code load the 2434 // address of the callee into ECX. The value in ecx is used as target of 2435 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2436 // for tail calls on PIC/GOT architectures. Normally we would just put the 2437 // address of GOT into ebx and then call target@PLT. But for tail calls 2438 // ebx would be restored (since ebx is callee saved) before jumping to the 2439 // target@PLT. 2440 2441 // Note: The actual moving to ECX is done further down. 2442 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2443 if (G && !G->getGlobal()->hasHiddenVisibility() && 2444 !G->getGlobal()->hasProtectedVisibility()) 2445 Callee = LowerGlobalAddress(Callee, DAG); 2446 else if (isa<ExternalSymbolSDNode>(Callee)) 2447 Callee = LowerExternalSymbol(Callee, DAG); 2448 } 2449 } 2450 2451 if (Is64Bit && isVarArg && !IsWin64) { 2452 // From AMD64 ABI document: 2453 // For calls that may call functions that use varargs or stdargs 2454 // (prototype-less calls or calls to functions containing ellipsis (...) in 2455 // the declaration) %al is used as hidden argument to specify the number 2456 // of SSE registers used. The contents of %al do not need to match exactly 2457 // the number of registers, but must be an ubound on the number of SSE 2458 // registers used and is in the range 0 - 8 inclusive. 2459 2460 // Count the number of XMM registers allocated. 2461 static const uint16_t XMMArgRegs[] = { 2462 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2463 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2464 }; 2465 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2466 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2467 && "SSE registers cannot be used when SSE is disabled"); 2468 2469 RegsToPass.push_back(std::make_pair(unsigned(X86::AL), 2470 DAG.getConstant(NumXMMRegs, MVT::i8))); 2471 } 2472 2473 // For tail calls lower the arguments to the 'real' stack slot. 2474 if (isTailCall) { 2475 // Force all the incoming stack arguments to be loaded from the stack 2476 // before any new outgoing arguments are stored to the stack, because the 2477 // outgoing stack slots may alias the incoming argument stack slots, and 2478 // the alias isn't otherwise explicit. This is slightly more conservative 2479 // than necessary, because it means that each store effectively depends 2480 // on every argument instead of just those arguments it would clobber. 2481 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2482 2483 SmallVector<SDValue, 8> MemOpChains2; 2484 SDValue FIN; 2485 int FI = 0; 2486 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2487 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2488 CCValAssign &VA = ArgLocs[i]; 2489 if (VA.isRegLoc()) 2490 continue; 2491 assert(VA.isMemLoc()); 2492 SDValue Arg = OutVals[i]; 2493 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2494 // Create frame index. 2495 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2496 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2497 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2498 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2499 2500 if (Flags.isByVal()) { 2501 // Copy relative to framepointer. 2502 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2503 if (StackPtr.getNode() == 0) 2504 StackPtr = DAG.getCopyFromReg(Chain, dl, 2505 RegInfo->getStackRegister(), 2506 getPointerTy()); 2507 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2508 2509 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2510 ArgChain, 2511 Flags, DAG, dl)); 2512 } else { 2513 // Store relative to framepointer. 2514 MemOpChains2.push_back( 2515 DAG.getStore(ArgChain, dl, Arg, FIN, 2516 MachinePointerInfo::getFixedStack(FI), 2517 false, false, 0)); 2518 } 2519 } 2520 } 2521 2522 if (!MemOpChains2.empty()) 2523 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2524 &MemOpChains2[0], MemOpChains2.size()); 2525 2526 // Store the return address to the appropriate stack slot. 2527 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, 2528 getPointerTy(), RegInfo->getSlotSize(), 2529 FPDiff, dl); 2530 } 2531 2532 // Build a sequence of copy-to-reg nodes chained together with token chain 2533 // and flag operands which copy the outgoing args into registers. 2534 SDValue InFlag; 2535 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2536 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2537 RegsToPass[i].second, InFlag); 2538 InFlag = Chain.getValue(1); 2539 } 2540 2541 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2542 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2543 // In the 64-bit large code model, we have to make all calls 2544 // through a register, since the call instruction's 32-bit 2545 // pc-relative offset may not be large enough to hold the whole 2546 // address. 2547 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2548 // If the callee is a GlobalAddress node (quite common, every direct call 2549 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2550 // it. 2551 2552 // We should use extra load for direct calls to dllimported functions in 2553 // non-JIT mode. 2554 const GlobalValue *GV = G->getGlobal(); 2555 if (!GV->hasDLLImportLinkage()) { 2556 unsigned char OpFlags = 0; 2557 bool ExtraLoad = false; 2558 unsigned WrapperKind = ISD::DELETED_NODE; 2559 2560 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2561 // external symbols most go through the PLT in PIC mode. If the symbol 2562 // has hidden or protected visibility, or if it is static or local, then 2563 // we don't need to use the PLT - we can directly call it. 2564 if (Subtarget->isTargetELF() && 2565 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2566 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2567 OpFlags = X86II::MO_PLT; 2568 } else if (Subtarget->isPICStyleStubAny() && 2569 (GV->isDeclaration() || GV->isWeakForLinker()) && 2570 (!Subtarget->getTargetTriple().isMacOSX() || 2571 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2572 // PC-relative references to external symbols should go through $stub, 2573 // unless we're building with the leopard linker or later, which 2574 // automatically synthesizes these stubs. 2575 OpFlags = X86II::MO_DARWIN_STUB; 2576 } else if (Subtarget->isPICStyleRIPRel() && 2577 isa<Function>(GV) && 2578 cast<Function>(GV)->getAttributes(). 2579 hasAttribute(AttributeSet::FunctionIndex, 2580 Attribute::NonLazyBind)) { 2581 // If the function is marked as non-lazy, generate an indirect call 2582 // which loads from the GOT directly. This avoids runtime overhead 2583 // at the cost of eager binding (and one extra byte of encoding). 2584 OpFlags = X86II::MO_GOTPCREL; 2585 WrapperKind = X86ISD::WrapperRIP; 2586 ExtraLoad = true; 2587 } 2588 2589 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2590 G->getOffset(), OpFlags); 2591 2592 // Add a wrapper if needed. 2593 if (WrapperKind != ISD::DELETED_NODE) 2594 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2595 // Add extra indirection if needed. 2596 if (ExtraLoad) 2597 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2598 MachinePointerInfo::getGOT(), 2599 false, false, false, 0); 2600 } 2601 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2602 unsigned char OpFlags = 0; 2603 2604 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2605 // external symbols should go through the PLT. 2606 if (Subtarget->isTargetELF() && 2607 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2608 OpFlags = X86II::MO_PLT; 2609 } else if (Subtarget->isPICStyleStubAny() && 2610 (!Subtarget->getTargetTriple().isMacOSX() || 2611 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2612 // PC-relative references to external symbols should go through $stub, 2613 // unless we're building with the leopard linker or later, which 2614 // automatically synthesizes these stubs. 2615 OpFlags = X86II::MO_DARWIN_STUB; 2616 } 2617 2618 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2619 OpFlags); 2620 } 2621 2622 // Returns a chain & a flag for retval copy to use. 2623 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2624 SmallVector<SDValue, 8> Ops; 2625 2626 if (!IsSibcall && isTailCall) { 2627 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2628 DAG.getIntPtrConstant(0, true), InFlag); 2629 InFlag = Chain.getValue(1); 2630 } 2631 2632 Ops.push_back(Chain); 2633 Ops.push_back(Callee); 2634 2635 if (isTailCall) 2636 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2637 2638 // Add argument registers to the end of the list so that they are known live 2639 // into the call. 2640 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2641 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2642 RegsToPass[i].second.getValueType())); 2643 2644 // Add a register mask operand representing the call-preserved registers. 2645 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2646 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2647 assert(Mask && "Missing call preserved mask for calling convention"); 2648 Ops.push_back(DAG.getRegisterMask(Mask)); 2649 2650 if (InFlag.getNode()) 2651 Ops.push_back(InFlag); 2652 2653 if (isTailCall) { 2654 // We used to do: 2655 //// If this is the first return lowered for this function, add the regs 2656 //// to the liveout set for the function. 2657 // This isn't right, although it's probably harmless on x86; liveouts 2658 // should be computed from returns not tail calls. Consider a void 2659 // function making a tail call to a function returning int. 2660 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 2661 } 2662 2663 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2664 InFlag = Chain.getValue(1); 2665 2666 // Create the CALLSEQ_END node. 2667 unsigned NumBytesForCalleeToPush; 2668 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2669 getTargetMachine().Options.GuaranteedTailCallOpt)) 2670 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2671 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2672 SR == StackStructReturn) 2673 // If this is a call to a struct-return function, the callee 2674 // pops the hidden struct pointer, so we have to push it back. 2675 // This is common for Darwin/X86, Linux & Mingw32 targets. 2676 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2677 NumBytesForCalleeToPush = 4; 2678 else 2679 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2680 2681 // Returns a flag for retval copy to use. 2682 if (!IsSibcall) { 2683 Chain = DAG.getCALLSEQ_END(Chain, 2684 DAG.getIntPtrConstant(NumBytes, true), 2685 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2686 true), 2687 InFlag); 2688 InFlag = Chain.getValue(1); 2689 } 2690 2691 // Handle result values, copying them out of physregs into vregs that we 2692 // return. 2693 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2694 Ins, dl, DAG, InVals); 2695} 2696 2697//===----------------------------------------------------------------------===// 2698// Fast Calling Convention (tail call) implementation 2699//===----------------------------------------------------------------------===// 2700 2701// Like std call, callee cleans arguments, convention except that ECX is 2702// reserved for storing the tail called function address. Only 2 registers are 2703// free for argument passing (inreg). Tail call optimization is performed 2704// provided: 2705// * tailcallopt is enabled 2706// * caller/callee are fastcc 2707// On X86_64 architecture with GOT-style position independent code only local 2708// (within module) calls are supported at the moment. 2709// To keep the stack aligned according to platform abi the function 2710// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2711// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2712// If a tail called function callee has more arguments than the caller the 2713// caller needs to make sure that there is room to move the RETADDR to. This is 2714// achieved by reserving an area the size of the argument delta right after the 2715// original REtADDR, but before the saved framepointer or the spilled registers 2716// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2717// stack layout: 2718// arg1 2719// arg2 2720// RETADDR 2721// [ new RETADDR 2722// move area ] 2723// (possible EBP) 2724// ESI 2725// EDI 2726// local1 .. 2727 2728/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2729/// for a 16 byte align requirement. 2730unsigned 2731X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2732 SelectionDAG& DAG) const { 2733 MachineFunction &MF = DAG.getMachineFunction(); 2734 const TargetMachine &TM = MF.getTarget(); 2735 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2736 unsigned StackAlignment = TFI.getStackAlignment(); 2737 uint64_t AlignMask = StackAlignment - 1; 2738 int64_t Offset = StackSize; 2739 unsigned SlotSize = RegInfo->getSlotSize(); 2740 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2741 // Number smaller than 12 so just add the difference. 2742 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2743 } else { 2744 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2745 Offset = ((~AlignMask) & Offset) + StackAlignment + 2746 (StackAlignment-SlotSize); 2747 } 2748 return Offset; 2749} 2750 2751/// MatchingStackOffset - Return true if the given stack call argument is 2752/// already available in the same position (relatively) of the caller's 2753/// incoming argument stack. 2754static 2755bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2756 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2757 const X86InstrInfo *TII) { 2758 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2759 int FI = INT_MAX; 2760 if (Arg.getOpcode() == ISD::CopyFromReg) { 2761 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2762 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2763 return false; 2764 MachineInstr *Def = MRI->getVRegDef(VR); 2765 if (!Def) 2766 return false; 2767 if (!Flags.isByVal()) { 2768 if (!TII->isLoadFromStackSlot(Def, FI)) 2769 return false; 2770 } else { 2771 unsigned Opcode = Def->getOpcode(); 2772 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2773 Def->getOperand(1).isFI()) { 2774 FI = Def->getOperand(1).getIndex(); 2775 Bytes = Flags.getByValSize(); 2776 } else 2777 return false; 2778 } 2779 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2780 if (Flags.isByVal()) 2781 // ByVal argument is passed in as a pointer but it's now being 2782 // dereferenced. e.g. 2783 // define @foo(%struct.X* %A) { 2784 // tail call @bar(%struct.X* byval %A) 2785 // } 2786 return false; 2787 SDValue Ptr = Ld->getBasePtr(); 2788 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2789 if (!FINode) 2790 return false; 2791 FI = FINode->getIndex(); 2792 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2793 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2794 FI = FINode->getIndex(); 2795 Bytes = Flags.getByValSize(); 2796 } else 2797 return false; 2798 2799 assert(FI != INT_MAX); 2800 if (!MFI->isFixedObjectIndex(FI)) 2801 return false; 2802 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2803} 2804 2805/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2806/// for tail call optimization. Targets which want to do tail call 2807/// optimization should implement this function. 2808bool 2809X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2810 CallingConv::ID CalleeCC, 2811 bool isVarArg, 2812 bool isCalleeStructRet, 2813 bool isCallerStructRet, 2814 Type *RetTy, 2815 const SmallVectorImpl<ISD::OutputArg> &Outs, 2816 const SmallVectorImpl<SDValue> &OutVals, 2817 const SmallVectorImpl<ISD::InputArg> &Ins, 2818 SelectionDAG &DAG) const { 2819 if (!IsTailCallConvention(CalleeCC) && 2820 CalleeCC != CallingConv::C) 2821 return false; 2822 2823 // If -tailcallopt is specified, make fastcc functions tail-callable. 2824 const MachineFunction &MF = DAG.getMachineFunction(); 2825 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2826 2827 // If the function return type is x86_fp80 and the callee return type is not, 2828 // then the FP_EXTEND of the call result is not a nop. It's not safe to 2829 // perform a tailcall optimization here. 2830 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty()) 2831 return false; 2832 2833 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2834 bool CCMatch = CallerCC == CalleeCC; 2835 2836 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2837 if (IsTailCallConvention(CalleeCC) && CCMatch) 2838 return true; 2839 return false; 2840 } 2841 2842 // Look for obvious safe cases to perform tail call optimization that do not 2843 // require ABI changes. This is what gcc calls sibcall. 2844 2845 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2846 // emit a special epilogue. 2847 if (RegInfo->needsStackRealignment(MF)) 2848 return false; 2849 2850 // Also avoid sibcall optimization if either caller or callee uses struct 2851 // return semantics. 2852 if (isCalleeStructRet || isCallerStructRet) 2853 return false; 2854 2855 // An stdcall caller is expected to clean up its arguments; the callee 2856 // isn't going to do that. 2857 if (!CCMatch && CallerCC == CallingConv::X86_StdCall) 2858 return false; 2859 2860 // Do not sibcall optimize vararg calls unless all arguments are passed via 2861 // registers. 2862 if (isVarArg && !Outs.empty()) { 2863 2864 // Optimizing for varargs on Win64 is unlikely to be safe without 2865 // additional testing. 2866 if (Subtarget->isTargetWin64()) 2867 return false; 2868 2869 SmallVector<CCValAssign, 16> ArgLocs; 2870 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2871 getTargetMachine(), ArgLocs, *DAG.getContext()); 2872 2873 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2874 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2875 if (!ArgLocs[i].isRegLoc()) 2876 return false; 2877 } 2878 2879 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2880 // stack. Therefore, if it's not used by the call it is not safe to optimize 2881 // this into a sibcall. 2882 bool Unused = false; 2883 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2884 if (!Ins[i].Used) { 2885 Unused = true; 2886 break; 2887 } 2888 } 2889 if (Unused) { 2890 SmallVector<CCValAssign, 16> RVLocs; 2891 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2892 getTargetMachine(), RVLocs, *DAG.getContext()); 2893 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2894 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2895 CCValAssign &VA = RVLocs[i]; 2896 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2897 return false; 2898 } 2899 } 2900 2901 // If the calling conventions do not match, then we'd better make sure the 2902 // results are returned in the same way as what the caller expects. 2903 if (!CCMatch) { 2904 SmallVector<CCValAssign, 16> RVLocs1; 2905 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2906 getTargetMachine(), RVLocs1, *DAG.getContext()); 2907 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2908 2909 SmallVector<CCValAssign, 16> RVLocs2; 2910 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2911 getTargetMachine(), RVLocs2, *DAG.getContext()); 2912 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2913 2914 if (RVLocs1.size() != RVLocs2.size()) 2915 return false; 2916 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2917 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2918 return false; 2919 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2920 return false; 2921 if (RVLocs1[i].isRegLoc()) { 2922 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2923 return false; 2924 } else { 2925 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2926 return false; 2927 } 2928 } 2929 } 2930 2931 // If the callee takes no arguments then go on to check the results of the 2932 // call. 2933 if (!Outs.empty()) { 2934 // Check if stack adjustment is needed. For now, do not do this if any 2935 // argument is passed on the stack. 2936 SmallVector<CCValAssign, 16> ArgLocs; 2937 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2938 getTargetMachine(), ArgLocs, *DAG.getContext()); 2939 2940 // Allocate shadow area for Win64 2941 if (Subtarget->isTargetWin64()) { 2942 CCInfo.AllocateStack(32, 8); 2943 } 2944 2945 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2946 if (CCInfo.getNextStackOffset()) { 2947 MachineFunction &MF = DAG.getMachineFunction(); 2948 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2949 return false; 2950 2951 // Check if the arguments are already laid out in the right way as 2952 // the caller's fixed stack objects. 2953 MachineFrameInfo *MFI = MF.getFrameInfo(); 2954 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2955 const X86InstrInfo *TII = 2956 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2957 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2958 CCValAssign &VA = ArgLocs[i]; 2959 SDValue Arg = OutVals[i]; 2960 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2961 if (VA.getLocInfo() == CCValAssign::Indirect) 2962 return false; 2963 if (!VA.isRegLoc()) { 2964 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2965 MFI, MRI, TII)) 2966 return false; 2967 } 2968 } 2969 } 2970 2971 // If the tailcall address may be in a register, then make sure it's 2972 // possible to register allocate for it. In 32-bit, the call address can 2973 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2974 // callee-saved registers are restored. These happen to be the same 2975 // registers used to pass 'inreg' arguments so watch out for those. 2976 if (!Subtarget->is64Bit() && 2977 ((!isa<GlobalAddressSDNode>(Callee) && 2978 !isa<ExternalSymbolSDNode>(Callee)) || 2979 getTargetMachine().getRelocationModel() == Reloc::PIC_)) { 2980 unsigned NumInRegs = 0; 2981 // In PIC we need an extra register to formulate the address computation 2982 // for the callee. 2983 unsigned MaxInRegs = 2984 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3; 2985 2986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2987 CCValAssign &VA = ArgLocs[i]; 2988 if (!VA.isRegLoc()) 2989 continue; 2990 unsigned Reg = VA.getLocReg(); 2991 switch (Reg) { 2992 default: break; 2993 case X86::EAX: case X86::EDX: case X86::ECX: 2994 if (++NumInRegs == MaxInRegs) 2995 return false; 2996 break; 2997 } 2998 } 2999 } 3000 } 3001 3002 return true; 3003} 3004 3005FastISel * 3006X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 3007 const TargetLibraryInfo *libInfo) const { 3008 return X86::createFastISel(funcInfo, libInfo); 3009} 3010 3011//===----------------------------------------------------------------------===// 3012// Other Lowering Hooks 3013//===----------------------------------------------------------------------===// 3014 3015static bool MayFoldLoad(SDValue Op) { 3016 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 3017} 3018 3019static bool MayFoldIntoStore(SDValue Op) { 3020 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 3021} 3022 3023static bool isTargetShuffle(unsigned Opcode) { 3024 switch(Opcode) { 3025 default: return false; 3026 case X86ISD::PSHUFD: 3027 case X86ISD::PSHUFHW: 3028 case X86ISD::PSHUFLW: 3029 case X86ISD::SHUFP: 3030 case X86ISD::PALIGNR: 3031 case X86ISD::MOVLHPS: 3032 case X86ISD::MOVLHPD: 3033 case X86ISD::MOVHLPS: 3034 case X86ISD::MOVLPS: 3035 case X86ISD::MOVLPD: 3036 case X86ISD::MOVSHDUP: 3037 case X86ISD::MOVSLDUP: 3038 case X86ISD::MOVDDUP: 3039 case X86ISD::MOVSS: 3040 case X86ISD::MOVSD: 3041 case X86ISD::UNPCKL: 3042 case X86ISD::UNPCKH: 3043 case X86ISD::VPERMILP: 3044 case X86ISD::VPERM2X128: 3045 case X86ISD::VPERMI: 3046 return true; 3047 } 3048} 3049 3050static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 3051 SDValue V1, SelectionDAG &DAG) { 3052 switch(Opc) { 3053 default: llvm_unreachable("Unknown x86 shuffle node"); 3054 case X86ISD::MOVSHDUP: 3055 case X86ISD::MOVSLDUP: 3056 case X86ISD::MOVDDUP: 3057 return DAG.getNode(Opc, dl, VT, V1); 3058 } 3059} 3060 3061static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 3062 SDValue V1, unsigned TargetMask, 3063 SelectionDAG &DAG) { 3064 switch(Opc) { 3065 default: llvm_unreachable("Unknown x86 shuffle node"); 3066 case X86ISD::PSHUFD: 3067 case X86ISD::PSHUFHW: 3068 case X86ISD::PSHUFLW: 3069 case X86ISD::VPERMILP: 3070 case X86ISD::VPERMI: 3071 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 3072 } 3073} 3074 3075static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 3076 SDValue V1, SDValue V2, unsigned TargetMask, 3077 SelectionDAG &DAG) { 3078 switch(Opc) { 3079 default: llvm_unreachable("Unknown x86 shuffle node"); 3080 case X86ISD::PALIGNR: 3081 case X86ISD::SHUFP: 3082 case X86ISD::VPERM2X128: 3083 return DAG.getNode(Opc, dl, VT, V1, V2, 3084 DAG.getConstant(TargetMask, MVT::i8)); 3085 } 3086} 3087 3088static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 3089 SDValue V1, SDValue V2, SelectionDAG &DAG) { 3090 switch(Opc) { 3091 default: llvm_unreachable("Unknown x86 shuffle node"); 3092 case X86ISD::MOVLHPS: 3093 case X86ISD::MOVLHPD: 3094 case X86ISD::MOVHLPS: 3095 case X86ISD::MOVLPS: 3096 case X86ISD::MOVLPD: 3097 case X86ISD::MOVSS: 3098 case X86ISD::MOVSD: 3099 case X86ISD::UNPCKL: 3100 case X86ISD::UNPCKH: 3101 return DAG.getNode(Opc, dl, VT, V1, V2); 3102 } 3103} 3104 3105SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 3106 MachineFunction &MF = DAG.getMachineFunction(); 3107 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 3108 int ReturnAddrIndex = FuncInfo->getRAIndex(); 3109 3110 if (ReturnAddrIndex == 0) { 3111 // Set up a frame object for the return address. 3112 unsigned SlotSize = RegInfo->getSlotSize(); 3113 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 3114 false); 3115 FuncInfo->setRAIndex(ReturnAddrIndex); 3116 } 3117 3118 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 3119} 3120 3121bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 3122 bool hasSymbolicDisplacement) { 3123 // Offset should fit into 32 bit immediate field. 3124 if (!isInt<32>(Offset)) 3125 return false; 3126 3127 // If we don't have a symbolic displacement - we don't have any extra 3128 // restrictions. 3129 if (!hasSymbolicDisplacement) 3130 return true; 3131 3132 // FIXME: Some tweaks might be needed for medium code model. 3133 if (M != CodeModel::Small && M != CodeModel::Kernel) 3134 return false; 3135 3136 // For small code model we assume that latest object is 16MB before end of 31 3137 // bits boundary. We may also accept pretty large negative constants knowing 3138 // that all objects are in the positive half of address space. 3139 if (M == CodeModel::Small && Offset < 16*1024*1024) 3140 return true; 3141 3142 // For kernel code model we know that all object resist in the negative half 3143 // of 32bits address space. We may not accept negative offsets, since they may 3144 // be just off and we may accept pretty large positive ones. 3145 if (M == CodeModel::Kernel && Offset > 0) 3146 return true; 3147 3148 return false; 3149} 3150 3151/// isCalleePop - Determines whether the callee is required to pop its 3152/// own arguments. Callee pop is necessary to support tail calls. 3153bool X86::isCalleePop(CallingConv::ID CallingConv, 3154 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3155 if (IsVarArg) 3156 return false; 3157 3158 switch (CallingConv) { 3159 default: 3160 return false; 3161 case CallingConv::X86_StdCall: 3162 return !is64Bit; 3163 case CallingConv::X86_FastCall: 3164 return !is64Bit; 3165 case CallingConv::X86_ThisCall: 3166 return !is64Bit; 3167 case CallingConv::Fast: 3168 return TailCallOpt; 3169 case CallingConv::GHC: 3170 return TailCallOpt; 3171 case CallingConv::HiPE: 3172 return TailCallOpt; 3173 } 3174} 3175 3176/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3177/// specific condition code, returning the condition code and the LHS/RHS of the 3178/// comparison to make. 3179static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3180 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3181 if (!isFP) { 3182 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3183 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3184 // X > -1 -> X == 0, jump !sign. 3185 RHS = DAG.getConstant(0, RHS.getValueType()); 3186 return X86::COND_NS; 3187 } 3188 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3189 // X < 0 -> X == 0, jump on sign. 3190 return X86::COND_S; 3191 } 3192 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3193 // X < 1 -> X <= 0 3194 RHS = DAG.getConstant(0, RHS.getValueType()); 3195 return X86::COND_LE; 3196 } 3197 } 3198 3199 switch (SetCCOpcode) { 3200 default: llvm_unreachable("Invalid integer condition!"); 3201 case ISD::SETEQ: return X86::COND_E; 3202 case ISD::SETGT: return X86::COND_G; 3203 case ISD::SETGE: return X86::COND_GE; 3204 case ISD::SETLT: return X86::COND_L; 3205 case ISD::SETLE: return X86::COND_LE; 3206 case ISD::SETNE: return X86::COND_NE; 3207 case ISD::SETULT: return X86::COND_B; 3208 case ISD::SETUGT: return X86::COND_A; 3209 case ISD::SETULE: return X86::COND_BE; 3210 case ISD::SETUGE: return X86::COND_AE; 3211 } 3212 } 3213 3214 // First determine if it is required or is profitable to flip the operands. 3215 3216 // If LHS is a foldable load, but RHS is not, flip the condition. 3217 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3218 !ISD::isNON_EXTLoad(RHS.getNode())) { 3219 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3220 std::swap(LHS, RHS); 3221 } 3222 3223 switch (SetCCOpcode) { 3224 default: break; 3225 case ISD::SETOLT: 3226 case ISD::SETOLE: 3227 case ISD::SETUGT: 3228 case ISD::SETUGE: 3229 std::swap(LHS, RHS); 3230 break; 3231 } 3232 3233 // On a floating point condition, the flags are set as follows: 3234 // ZF PF CF op 3235 // 0 | 0 | 0 | X > Y 3236 // 0 | 0 | 1 | X < Y 3237 // 1 | 0 | 0 | X == Y 3238 // 1 | 1 | 1 | unordered 3239 switch (SetCCOpcode) { 3240 default: llvm_unreachable("Condcode should be pre-legalized away"); 3241 case ISD::SETUEQ: 3242 case ISD::SETEQ: return X86::COND_E; 3243 case ISD::SETOLT: // flipped 3244 case ISD::SETOGT: 3245 case ISD::SETGT: return X86::COND_A; 3246 case ISD::SETOLE: // flipped 3247 case ISD::SETOGE: 3248 case ISD::SETGE: return X86::COND_AE; 3249 case ISD::SETUGT: // flipped 3250 case ISD::SETULT: 3251 case ISD::SETLT: return X86::COND_B; 3252 case ISD::SETUGE: // flipped 3253 case ISD::SETULE: 3254 case ISD::SETLE: return X86::COND_BE; 3255 case ISD::SETONE: 3256 case ISD::SETNE: return X86::COND_NE; 3257 case ISD::SETUO: return X86::COND_P; 3258 case ISD::SETO: return X86::COND_NP; 3259 case ISD::SETOEQ: 3260 case ISD::SETUNE: return X86::COND_INVALID; 3261 } 3262} 3263 3264/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3265/// code. Current x86 isa includes the following FP cmov instructions: 3266/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3267static bool hasFPCMov(unsigned X86CC) { 3268 switch (X86CC) { 3269 default: 3270 return false; 3271 case X86::COND_B: 3272 case X86::COND_BE: 3273 case X86::COND_E: 3274 case X86::COND_P: 3275 case X86::COND_A: 3276 case X86::COND_AE: 3277 case X86::COND_NE: 3278 case X86::COND_NP: 3279 return true; 3280 } 3281} 3282 3283/// isFPImmLegal - Returns true if the target can instruction select the 3284/// specified FP immediate natively. If false, the legalizer will 3285/// materialize the FP immediate as a load from a constant pool. 3286bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3287 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3288 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3289 return true; 3290 } 3291 return false; 3292} 3293 3294/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3295/// the specified range (L, H]. 3296static bool isUndefOrInRange(int Val, int Low, int Hi) { 3297 return (Val < 0) || (Val >= Low && Val < Hi); 3298} 3299 3300/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3301/// specified value. 3302static bool isUndefOrEqual(int Val, int CmpVal) { 3303 return (Val < 0 || Val == CmpVal); 3304} 3305 3306/// isSequentialOrUndefInRange - Return true if every element in Mask, beginning 3307/// from position Pos and ending in Pos+Size, falls within the specified 3308/// sequential range (L, L+Pos]. or is undef. 3309static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3310 unsigned Pos, unsigned Size, int Low) { 3311 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3312 if (!isUndefOrEqual(Mask[i], Low)) 3313 return false; 3314 return true; 3315} 3316 3317/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3318/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3319/// the second operand. 3320static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3321 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3322 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3323 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3324 return (Mask[0] < 2 && Mask[1] < 2); 3325 return false; 3326} 3327 3328/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3329/// is suitable for input to PSHUFHW. 3330static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { 3331 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16)) 3332 return false; 3333 3334 // Lower quadword copied in order or undef. 3335 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3336 return false; 3337 3338 // Upper quadword shuffled. 3339 for (unsigned i = 4; i != 8; ++i) 3340 if (!isUndefOrInRange(Mask[i], 4, 8)) 3341 return false; 3342 3343 if (VT == MVT::v16i16) { 3344 // Lower quadword copied in order or undef. 3345 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8)) 3346 return false; 3347 3348 // Upper quadword shuffled. 3349 for (unsigned i = 12; i != 16; ++i) 3350 if (!isUndefOrInRange(Mask[i], 12, 16)) 3351 return false; 3352 } 3353 3354 return true; 3355} 3356 3357/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3358/// is suitable for input to PSHUFLW. 3359static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { 3360 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16)) 3361 return false; 3362 3363 // Upper quadword copied in order. 3364 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3365 return false; 3366 3367 // Lower quadword shuffled. 3368 for (unsigned i = 0; i != 4; ++i) 3369 if (!isUndefOrInRange(Mask[i], 0, 4)) 3370 return false; 3371 3372 if (VT == MVT::v16i16) { 3373 // Upper quadword copied in order. 3374 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12)) 3375 return false; 3376 3377 // Lower quadword shuffled. 3378 for (unsigned i = 8; i != 12; ++i) 3379 if (!isUndefOrInRange(Mask[i], 8, 12)) 3380 return false; 3381 } 3382 3383 return true; 3384} 3385 3386/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3387/// is suitable for input to PALIGNR. 3388static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3389 const X86Subtarget *Subtarget) { 3390 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) || 3391 (VT.is256BitVector() && !Subtarget->hasInt256())) 3392 return false; 3393 3394 unsigned NumElts = VT.getVectorNumElements(); 3395 unsigned NumLanes = VT.getSizeInBits()/128; 3396 unsigned NumLaneElts = NumElts/NumLanes; 3397 3398 // Do not handle 64-bit element shuffles with palignr. 3399 if (NumLaneElts == 2) 3400 return false; 3401 3402 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3403 unsigned i; 3404 for (i = 0; i != NumLaneElts; ++i) { 3405 if (Mask[i+l] >= 0) 3406 break; 3407 } 3408 3409 // Lane is all undef, go to next lane 3410 if (i == NumLaneElts) 3411 continue; 3412 3413 int Start = Mask[i+l]; 3414 3415 // Make sure its in this lane in one of the sources 3416 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3417 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3418 return false; 3419 3420 // If not lane 0, then we must match lane 0 3421 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3422 return false; 3423 3424 // Correct second source to be contiguous with first source 3425 if (Start >= (int)NumElts) 3426 Start -= NumElts - NumLaneElts; 3427 3428 // Make sure we're shifting in the right direction. 3429 if (Start <= (int)(i+l)) 3430 return false; 3431 3432 Start -= i; 3433 3434 // Check the rest of the elements to see if they are consecutive. 3435 for (++i; i != NumLaneElts; ++i) { 3436 int Idx = Mask[i+l]; 3437 3438 // Make sure its in this lane 3439 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3440 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3441 return false; 3442 3443 // If not lane 0, then we must match lane 0 3444 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3445 return false; 3446 3447 if (Idx >= (int)NumElts) 3448 Idx -= NumElts - NumLaneElts; 3449 3450 if (!isUndefOrEqual(Idx, Start+i)) 3451 return false; 3452 3453 } 3454 } 3455 3456 return true; 3457} 3458 3459/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3460/// the two vector operands have swapped position. 3461static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3462 unsigned NumElems) { 3463 for (unsigned i = 0; i != NumElems; ++i) { 3464 int idx = Mask[i]; 3465 if (idx < 0) 3466 continue; 3467 else if (idx < (int)NumElems) 3468 Mask[i] = idx + NumElems; 3469 else 3470 Mask[i] = idx - NumElems; 3471 } 3472} 3473 3474/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3475/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3476/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3477/// reverse of what x86 shuffles want. 3478static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256, 3479 bool Commuted = false) { 3480 if (!HasFp256 && VT.is256BitVector()) 3481 return false; 3482 3483 unsigned NumElems = VT.getVectorNumElements(); 3484 unsigned NumLanes = VT.getSizeInBits()/128; 3485 unsigned NumLaneElems = NumElems/NumLanes; 3486 3487 if (NumLaneElems != 2 && NumLaneElems != 4) 3488 return false; 3489 3490 // VSHUFPSY divides the resulting vector into 4 chunks. 3491 // The sources are also splitted into 4 chunks, and each destination 3492 // chunk must come from a different source chunk. 3493 // 3494 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3495 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3496 // 3497 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3498 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3499 // 3500 // VSHUFPDY divides the resulting vector into 4 chunks. 3501 // The sources are also splitted into 4 chunks, and each destination 3502 // chunk must come from a different source chunk. 3503 // 3504 // SRC1 => X3 X2 X1 X0 3505 // SRC2 => Y3 Y2 Y1 Y0 3506 // 3507 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3508 // 3509 unsigned HalfLaneElems = NumLaneElems/2; 3510 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3511 for (unsigned i = 0; i != NumLaneElems; ++i) { 3512 int Idx = Mask[i+l]; 3513 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3514 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3515 return false; 3516 // For VSHUFPSY, the mask of the second half must be the same as the 3517 // first but with the appropriate offsets. This works in the same way as 3518 // VPERMILPS works with masks. 3519 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3520 continue; 3521 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3522 return false; 3523 } 3524 } 3525 3526 return true; 3527} 3528 3529/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3530/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3531static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3532 if (!VT.is128BitVector()) 3533 return false; 3534 3535 unsigned NumElems = VT.getVectorNumElements(); 3536 3537 if (NumElems != 4) 3538 return false; 3539 3540 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3541 return isUndefOrEqual(Mask[0], 6) && 3542 isUndefOrEqual(Mask[1], 7) && 3543 isUndefOrEqual(Mask[2], 2) && 3544 isUndefOrEqual(Mask[3], 3); 3545} 3546 3547/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3548/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3549/// <2, 3, 2, 3> 3550static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3551 if (!VT.is128BitVector()) 3552 return false; 3553 3554 unsigned NumElems = VT.getVectorNumElements(); 3555 3556 if (NumElems != 4) 3557 return false; 3558 3559 return isUndefOrEqual(Mask[0], 2) && 3560 isUndefOrEqual(Mask[1], 3) && 3561 isUndefOrEqual(Mask[2], 2) && 3562 isUndefOrEqual(Mask[3], 3); 3563} 3564 3565/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3566/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3567static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3568 if (!VT.is128BitVector()) 3569 return false; 3570 3571 unsigned NumElems = VT.getVectorNumElements(); 3572 3573 if (NumElems != 2 && NumElems != 4) 3574 return false; 3575 3576 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3577 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3578 return false; 3579 3580 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 3581 if (!isUndefOrEqual(Mask[i], i)) 3582 return false; 3583 3584 return true; 3585} 3586 3587/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3588/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3589static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3590 if (!VT.is128BitVector()) 3591 return false; 3592 3593 unsigned NumElems = VT.getVectorNumElements(); 3594 3595 if (NumElems != 2 && NumElems != 4) 3596 return false; 3597 3598 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3599 if (!isUndefOrEqual(Mask[i], i)) 3600 return false; 3601 3602 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3603 if (!isUndefOrEqual(Mask[i + e], i + NumElems)) 3604 return false; 3605 3606 return true; 3607} 3608 3609// 3610// Some special combinations that can be optimized. 3611// 3612static 3613SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp, 3614 SelectionDAG &DAG) { 3615 MVT VT = SVOp->getValueType(0).getSimpleVT(); 3616 DebugLoc dl = SVOp->getDebugLoc(); 3617 3618 if (VT != MVT::v8i32 && VT != MVT::v8f32) 3619 return SDValue(); 3620 3621 ArrayRef<int> Mask = SVOp->getMask(); 3622 3623 // These are the special masks that may be optimized. 3624 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14}; 3625 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15}; 3626 bool MatchEvenMask = true; 3627 bool MatchOddMask = true; 3628 for (int i=0; i<8; ++i) { 3629 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i])) 3630 MatchEvenMask = false; 3631 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i])) 3632 MatchOddMask = false; 3633 } 3634 3635 if (!MatchEvenMask && !MatchOddMask) 3636 return SDValue(); 3637 3638 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT); 3639 3640 SDValue Op0 = SVOp->getOperand(0); 3641 SDValue Op1 = SVOp->getOperand(1); 3642 3643 if (MatchEvenMask) { 3644 // Shift the second operand right to 32 bits. 3645 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 }; 3646 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask); 3647 } else { 3648 // Shift the first operand left to 32 bits. 3649 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 }; 3650 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask); 3651 } 3652 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15}; 3653 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask); 3654} 3655 3656/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3657/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3658static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3659 bool HasInt256, bool V2IsSplat = false) { 3660 unsigned NumElts = VT.getVectorNumElements(); 3661 3662 assert((VT.is128BitVector() || VT.is256BitVector()) && 3663 "Unsupported vector type for unpckh"); 3664 3665 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 && 3666 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3667 return false; 3668 3669 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3670 // independently on 128-bit lanes. 3671 unsigned NumLanes = VT.getSizeInBits()/128; 3672 unsigned NumLaneElts = NumElts/NumLanes; 3673 3674 for (unsigned l = 0; l != NumLanes; ++l) { 3675 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3676 i != (l+1)*NumLaneElts; 3677 i += 2, ++j) { 3678 int BitI = Mask[i]; 3679 int BitI1 = Mask[i+1]; 3680 if (!isUndefOrEqual(BitI, j)) 3681 return false; 3682 if (V2IsSplat) { 3683 if (!isUndefOrEqual(BitI1, NumElts)) 3684 return false; 3685 } else { 3686 if (!isUndefOrEqual(BitI1, j + NumElts)) 3687 return false; 3688 } 3689 } 3690 } 3691 3692 return true; 3693} 3694 3695/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3696/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3697static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3698 bool HasInt256, bool V2IsSplat = false) { 3699 unsigned NumElts = VT.getVectorNumElements(); 3700 3701 assert((VT.is128BitVector() || VT.is256BitVector()) && 3702 "Unsupported vector type for unpckh"); 3703 3704 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 && 3705 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3706 return false; 3707 3708 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3709 // independently on 128-bit lanes. 3710 unsigned NumLanes = VT.getSizeInBits()/128; 3711 unsigned NumLaneElts = NumElts/NumLanes; 3712 3713 for (unsigned l = 0; l != NumLanes; ++l) { 3714 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3715 i != (l+1)*NumLaneElts; i += 2, ++j) { 3716 int BitI = Mask[i]; 3717 int BitI1 = Mask[i+1]; 3718 if (!isUndefOrEqual(BitI, j)) 3719 return false; 3720 if (V2IsSplat) { 3721 if (isUndefOrEqual(BitI1, NumElts)) 3722 return false; 3723 } else { 3724 if (!isUndefOrEqual(BitI1, j+NumElts)) 3725 return false; 3726 } 3727 } 3728 } 3729 return true; 3730} 3731 3732/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3733/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3734/// <0, 0, 1, 1> 3735static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { 3736 unsigned NumElts = VT.getVectorNumElements(); 3737 bool Is256BitVec = VT.is256BitVector(); 3738 3739 assert((VT.is128BitVector() || VT.is256BitVector()) && 3740 "Unsupported vector type for unpckh"); 3741 3742 if (Is256BitVec && NumElts != 4 && NumElts != 8 && 3743 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3744 return false; 3745 3746 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3747 // FIXME: Need a better way to get rid of this, there's no latency difference 3748 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3749 // the former later. We should also remove the "_undef" special mask. 3750 if (NumElts == 4 && Is256BitVec) 3751 return false; 3752 3753 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3754 // independently on 128-bit lanes. 3755 unsigned NumLanes = VT.getSizeInBits()/128; 3756 unsigned NumLaneElts = NumElts/NumLanes; 3757 3758 for (unsigned l = 0; l != NumLanes; ++l) { 3759 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3760 i != (l+1)*NumLaneElts; 3761 i += 2, ++j) { 3762 int BitI = Mask[i]; 3763 int BitI1 = Mask[i+1]; 3764 3765 if (!isUndefOrEqual(BitI, j)) 3766 return false; 3767 if (!isUndefOrEqual(BitI1, j)) 3768 return false; 3769 } 3770 } 3771 3772 return true; 3773} 3774 3775/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3776/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3777/// <2, 2, 3, 3> 3778static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { 3779 unsigned NumElts = VT.getVectorNumElements(); 3780 3781 assert((VT.is128BitVector() || VT.is256BitVector()) && 3782 "Unsupported vector type for unpckh"); 3783 3784 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 && 3785 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3786 return false; 3787 3788 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3789 // independently on 128-bit lanes. 3790 unsigned NumLanes = VT.getSizeInBits()/128; 3791 unsigned NumLaneElts = NumElts/NumLanes; 3792 3793 for (unsigned l = 0; l != NumLanes; ++l) { 3794 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3795 i != (l+1)*NumLaneElts; i += 2, ++j) { 3796 int BitI = Mask[i]; 3797 int BitI1 = Mask[i+1]; 3798 if (!isUndefOrEqual(BitI, j)) 3799 return false; 3800 if (!isUndefOrEqual(BitI1, j)) 3801 return false; 3802 } 3803 } 3804 return true; 3805} 3806 3807/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3808/// specifies a shuffle of elements that is suitable for input to MOVSS, 3809/// MOVSD, and MOVD, i.e. setting the lowest element. 3810static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3811 if (VT.getVectorElementType().getSizeInBits() < 32) 3812 return false; 3813 if (!VT.is128BitVector()) 3814 return false; 3815 3816 unsigned NumElts = VT.getVectorNumElements(); 3817 3818 if (!isUndefOrEqual(Mask[0], NumElts)) 3819 return false; 3820 3821 for (unsigned i = 1; i != NumElts; ++i) 3822 if (!isUndefOrEqual(Mask[i], i)) 3823 return false; 3824 3825 return true; 3826} 3827 3828/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3829/// as permutations between 128-bit chunks or halves. As an example: this 3830/// shuffle bellow: 3831/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3832/// The first half comes from the second half of V1 and the second half from the 3833/// the second half of V2. 3834static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { 3835 if (!HasFp256 || !VT.is256BitVector()) 3836 return false; 3837 3838 // The shuffle result is divided into half A and half B. In total the two 3839 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3840 // B must come from C, D, E or F. 3841 unsigned HalfSize = VT.getVectorNumElements()/2; 3842 bool MatchA = false, MatchB = false; 3843 3844 // Check if A comes from one of C, D, E, F. 3845 for (unsigned Half = 0; Half != 4; ++Half) { 3846 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3847 MatchA = true; 3848 break; 3849 } 3850 } 3851 3852 // Check if B comes from one of C, D, E, F. 3853 for (unsigned Half = 0; Half != 4; ++Half) { 3854 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3855 MatchB = true; 3856 break; 3857 } 3858 } 3859 3860 return MatchA && MatchB; 3861} 3862 3863/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3864/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3865static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3866 MVT VT = SVOp->getValueType(0).getSimpleVT(); 3867 3868 unsigned HalfSize = VT.getVectorNumElements()/2; 3869 3870 unsigned FstHalf = 0, SndHalf = 0; 3871 for (unsigned i = 0; i < HalfSize; ++i) { 3872 if (SVOp->getMaskElt(i) > 0) { 3873 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3874 break; 3875 } 3876 } 3877 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3878 if (SVOp->getMaskElt(i) > 0) { 3879 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3880 break; 3881 } 3882 } 3883 3884 return (FstHalf | (SndHalf << 4)); 3885} 3886 3887/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3888/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3889/// Note that VPERMIL mask matching is different depending whether theunderlying 3890/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3891/// to the same elements of the low, but to the higher half of the source. 3892/// In VPERMILPD the two lanes could be shuffled independently of each other 3893/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3894static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { 3895 if (!HasFp256) 3896 return false; 3897 3898 unsigned NumElts = VT.getVectorNumElements(); 3899 // Only match 256-bit with 32/64-bit types 3900 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8)) 3901 return false; 3902 3903 unsigned NumLanes = VT.getSizeInBits()/128; 3904 unsigned LaneSize = NumElts/NumLanes; 3905 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3906 for (unsigned i = 0; i != LaneSize; ++i) { 3907 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3908 return false; 3909 if (NumElts != 8 || l == 0) 3910 continue; 3911 // VPERMILPS handling 3912 if (Mask[i] < 0) 3913 continue; 3914 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3915 return false; 3916 } 3917 } 3918 3919 return true; 3920} 3921 3922/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3923/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3924/// element of vector 2 and the other elements to come from vector 1 in order. 3925static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3926 bool V2IsSplat = false, bool V2IsUndef = false) { 3927 if (!VT.is128BitVector()) 3928 return false; 3929 3930 unsigned NumOps = VT.getVectorNumElements(); 3931 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3932 return false; 3933 3934 if (!isUndefOrEqual(Mask[0], 0)) 3935 return false; 3936 3937 for (unsigned i = 1; i != NumOps; ++i) 3938 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3939 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3940 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3941 return false; 3942 3943 return true; 3944} 3945 3946/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3947/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3948/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3949static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3950 const X86Subtarget *Subtarget) { 3951 if (!Subtarget->hasSSE3()) 3952 return false; 3953 3954 unsigned NumElems = VT.getVectorNumElements(); 3955 3956 if ((VT.is128BitVector() && NumElems != 4) || 3957 (VT.is256BitVector() && NumElems != 8)) 3958 return false; 3959 3960 // "i+1" is the value the indexed mask element must have 3961 for (unsigned i = 0; i != NumElems; i += 2) 3962 if (!isUndefOrEqual(Mask[i], i+1) || 3963 !isUndefOrEqual(Mask[i+1], i+1)) 3964 return false; 3965 3966 return true; 3967} 3968 3969/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3970/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3971/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3972static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3973 const X86Subtarget *Subtarget) { 3974 if (!Subtarget->hasSSE3()) 3975 return false; 3976 3977 unsigned NumElems = VT.getVectorNumElements(); 3978 3979 if ((VT.is128BitVector() && NumElems != 4) || 3980 (VT.is256BitVector() && NumElems != 8)) 3981 return false; 3982 3983 // "i" is the value the indexed mask element must have 3984 for (unsigned i = 0; i != NumElems; i += 2) 3985 if (!isUndefOrEqual(Mask[i], i) || 3986 !isUndefOrEqual(Mask[i+1], i)) 3987 return false; 3988 3989 return true; 3990} 3991 3992/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3993/// specifies a shuffle of elements that is suitable for input to 256-bit 3994/// version of MOVDDUP. 3995static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { 3996 if (!HasFp256 || !VT.is256BitVector()) 3997 return false; 3998 3999 unsigned NumElts = VT.getVectorNumElements(); 4000 if (NumElts != 4) 4001 return false; 4002 4003 for (unsigned i = 0; i != NumElts/2; ++i) 4004 if (!isUndefOrEqual(Mask[i], 0)) 4005 return false; 4006 for (unsigned i = NumElts/2; i != NumElts; ++i) 4007 if (!isUndefOrEqual(Mask[i], NumElts/2)) 4008 return false; 4009 return true; 4010} 4011 4012/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 4013/// specifies a shuffle of elements that is suitable for input to 128-bit 4014/// version of MOVDDUP. 4015static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 4016 if (!VT.is128BitVector()) 4017 return false; 4018 4019 unsigned e = VT.getVectorNumElements() / 2; 4020 for (unsigned i = 0; i != e; ++i) 4021 if (!isUndefOrEqual(Mask[i], i)) 4022 return false; 4023 for (unsigned i = 0; i != e; ++i) 4024 if (!isUndefOrEqual(Mask[e+i], i)) 4025 return false; 4026 return true; 4027} 4028 4029/// isVEXTRACTF128Index - Return true if the specified 4030/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 4031/// suitable for input to VEXTRACTF128. 4032bool X86::isVEXTRACTF128Index(SDNode *N) { 4033 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4034 return false; 4035 4036 // The index should be aligned on a 128-bit boundary. 4037 uint64_t Index = 4038 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4039 4040 MVT VT = N->getValueType(0).getSimpleVT(); 4041 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); 4042 bool Result = (Index * ElSize) % 128 == 0; 4043 4044 return Result; 4045} 4046 4047/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 4048/// operand specifies a subvector insert that is suitable for input to 4049/// VINSERTF128. 4050bool X86::isVINSERTF128Index(SDNode *N) { 4051 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4052 return false; 4053 4054 // The index should be aligned on a 128-bit boundary. 4055 uint64_t Index = 4056 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4057 4058 MVT VT = N->getValueType(0).getSimpleVT(); 4059 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); 4060 bool Result = (Index * ElSize) % 128 == 0; 4061 4062 return Result; 4063} 4064 4065/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 4066/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 4067/// Handles 128-bit and 256-bit. 4068static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 4069 MVT VT = N->getValueType(0).getSimpleVT(); 4070 4071 assert((VT.is128BitVector() || VT.is256BitVector()) && 4072 "Unsupported vector type for PSHUF/SHUFP"); 4073 4074 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 4075 // independently on 128-bit lanes. 4076 unsigned NumElts = VT.getVectorNumElements(); 4077 unsigned NumLanes = VT.getSizeInBits()/128; 4078 unsigned NumLaneElts = NumElts/NumLanes; 4079 4080 assert((NumLaneElts == 2 || NumLaneElts == 4) && 4081 "Only supports 2 or 4 elements per lane"); 4082 4083 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 4084 unsigned Mask = 0; 4085 for (unsigned i = 0; i != NumElts; ++i) { 4086 int Elt = N->getMaskElt(i); 4087 if (Elt < 0) continue; 4088 Elt &= NumLaneElts - 1; 4089 unsigned ShAmt = (i << Shift) % 8; 4090 Mask |= Elt << ShAmt; 4091 } 4092 4093 return Mask; 4094} 4095 4096/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4097/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4098static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 4099 MVT VT = N->getValueType(0).getSimpleVT(); 4100 4101 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4102 "Unsupported vector type for PSHUFHW"); 4103 4104 unsigned NumElts = VT.getVectorNumElements(); 4105 4106 unsigned Mask = 0; 4107 for (unsigned l = 0; l != NumElts; l += 8) { 4108 // 8 nodes per lane, but we only care about the last 4. 4109 for (unsigned i = 0; i < 4; ++i) { 4110 int Elt = N->getMaskElt(l+i+4); 4111 if (Elt < 0) continue; 4112 Elt &= 0x3; // only 2-bits. 4113 Mask |= Elt << (i * 2); 4114 } 4115 } 4116 4117 return Mask; 4118} 4119 4120/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4121/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4122static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 4123 MVT VT = N->getValueType(0).getSimpleVT(); 4124 4125 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4126 "Unsupported vector type for PSHUFHW"); 4127 4128 unsigned NumElts = VT.getVectorNumElements(); 4129 4130 unsigned Mask = 0; 4131 for (unsigned l = 0; l != NumElts; l += 8) { 4132 // 8 nodes per lane, but we only care about the first 4. 4133 for (unsigned i = 0; i < 4; ++i) { 4134 int Elt = N->getMaskElt(l+i); 4135 if (Elt < 0) continue; 4136 Elt &= 0x3; // only 2-bits 4137 Mask |= Elt << (i * 2); 4138 } 4139 } 4140 4141 return Mask; 4142} 4143 4144/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4145/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4146static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4147 MVT VT = SVOp->getValueType(0).getSimpleVT(); 4148 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 4149 4150 unsigned NumElts = VT.getVectorNumElements(); 4151 unsigned NumLanes = VT.getSizeInBits()/128; 4152 unsigned NumLaneElts = NumElts/NumLanes; 4153 4154 int Val = 0; 4155 unsigned i; 4156 for (i = 0; i != NumElts; ++i) { 4157 Val = SVOp->getMaskElt(i); 4158 if (Val >= 0) 4159 break; 4160 } 4161 if (Val >= (int)NumElts) 4162 Val -= NumElts - NumLaneElts; 4163 4164 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4165 return (Val - i) * EltSize; 4166} 4167 4168/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4169/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4170/// instructions. 4171unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4172 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4173 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4174 4175 uint64_t Index = 4176 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4177 4178 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT(); 4179 MVT ElVT = VecVT.getVectorElementType(); 4180 4181 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4182 return Index / NumElemsPerChunk; 4183} 4184 4185/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4186/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4187/// instructions. 4188unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4189 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4190 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4191 4192 uint64_t Index = 4193 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4194 4195 MVT VecVT = N->getValueType(0).getSimpleVT(); 4196 MVT ElVT = VecVT.getVectorElementType(); 4197 4198 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4199 return Index / NumElemsPerChunk; 4200} 4201 4202/// getShuffleCLImmediate - Return the appropriate immediate to shuffle 4203/// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions. 4204/// Handles 256-bit. 4205static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { 4206 MVT VT = N->getValueType(0).getSimpleVT(); 4207 4208 unsigned NumElts = VT.getVectorNumElements(); 4209 4210 assert((VT.is256BitVector() && NumElts == 4) && 4211 "Unsupported vector type for VPERMQ/VPERMPD"); 4212 4213 unsigned Mask = 0; 4214 for (unsigned i = 0; i != NumElts; ++i) { 4215 int Elt = N->getMaskElt(i); 4216 if (Elt < 0) 4217 continue; 4218 Mask |= Elt << (i*2); 4219 } 4220 4221 return Mask; 4222} 4223/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4224/// constant +0.0. 4225bool X86::isZeroNode(SDValue Elt) { 4226 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt)) 4227 return CN->isNullValue(); 4228 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt)) 4229 return CFP->getValueAPF().isPosZero(); 4230 return false; 4231} 4232 4233/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4234/// their permute mask. 4235static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4236 SelectionDAG &DAG) { 4237 MVT VT = SVOp->getValueType(0).getSimpleVT(); 4238 unsigned NumElems = VT.getVectorNumElements(); 4239 SmallVector<int, 8> MaskVec; 4240 4241 for (unsigned i = 0; i != NumElems; ++i) { 4242 int Idx = SVOp->getMaskElt(i); 4243 if (Idx >= 0) { 4244 if (Idx < (int)NumElems) 4245 Idx += NumElems; 4246 else 4247 Idx -= NumElems; 4248 } 4249 MaskVec.push_back(Idx); 4250 } 4251 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4252 SVOp->getOperand(0), &MaskVec[0]); 4253} 4254 4255/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4256/// match movhlps. The lower half elements should come from upper half of 4257/// V1 (and in order), and the upper half elements should come from the upper 4258/// half of V2 (and in order). 4259static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4260 if (!VT.is128BitVector()) 4261 return false; 4262 if (VT.getVectorNumElements() != 4) 4263 return false; 4264 for (unsigned i = 0, e = 2; i != e; ++i) 4265 if (!isUndefOrEqual(Mask[i], i+2)) 4266 return false; 4267 for (unsigned i = 2; i != 4; ++i) 4268 if (!isUndefOrEqual(Mask[i], i+4)) 4269 return false; 4270 return true; 4271} 4272 4273/// isScalarLoadToVector - Returns true if the node is a scalar load that 4274/// is promoted to a vector. It also returns the LoadSDNode by reference if 4275/// required. 4276static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4277 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4278 return false; 4279 N = N->getOperand(0).getNode(); 4280 if (!ISD::isNON_EXTLoad(N)) 4281 return false; 4282 if (LD) 4283 *LD = cast<LoadSDNode>(N); 4284 return true; 4285} 4286 4287// Test whether the given value is a vector value which will be legalized 4288// into a load. 4289static bool WillBeConstantPoolLoad(SDNode *N) { 4290 if (N->getOpcode() != ISD::BUILD_VECTOR) 4291 return false; 4292 4293 // Check for any non-constant elements. 4294 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4295 switch (N->getOperand(i).getNode()->getOpcode()) { 4296 case ISD::UNDEF: 4297 case ISD::ConstantFP: 4298 case ISD::Constant: 4299 break; 4300 default: 4301 return false; 4302 } 4303 4304 // Vectors of all-zeros and all-ones are materialized with special 4305 // instructions rather than being loaded. 4306 return !ISD::isBuildVectorAllZeros(N) && 4307 !ISD::isBuildVectorAllOnes(N); 4308} 4309 4310/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4311/// match movlp{s|d}. The lower half elements should come from lower half of 4312/// V1 (and in order), and the upper half elements should come from the upper 4313/// half of V2 (and in order). And since V1 will become the source of the 4314/// MOVLP, it must be either a vector load or a scalar load to vector. 4315static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4316 ArrayRef<int> Mask, EVT VT) { 4317 if (!VT.is128BitVector()) 4318 return false; 4319 4320 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4321 return false; 4322 // Is V2 is a vector load, don't do this transformation. We will try to use 4323 // load folding shufps op. 4324 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4325 return false; 4326 4327 unsigned NumElems = VT.getVectorNumElements(); 4328 4329 if (NumElems != 2 && NumElems != 4) 4330 return false; 4331 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4332 if (!isUndefOrEqual(Mask[i], i)) 4333 return false; 4334 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 4335 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4336 return false; 4337 return true; 4338} 4339 4340/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4341/// all the same. 4342static bool isSplatVector(SDNode *N) { 4343 if (N->getOpcode() != ISD::BUILD_VECTOR) 4344 return false; 4345 4346 SDValue SplatValue = N->getOperand(0); 4347 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4348 if (N->getOperand(i) != SplatValue) 4349 return false; 4350 return true; 4351} 4352 4353/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4354/// to an zero vector. 4355/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4356static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4357 SDValue V1 = N->getOperand(0); 4358 SDValue V2 = N->getOperand(1); 4359 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4360 for (unsigned i = 0; i != NumElems; ++i) { 4361 int Idx = N->getMaskElt(i); 4362 if (Idx >= (int)NumElems) { 4363 unsigned Opc = V2.getOpcode(); 4364 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4365 continue; 4366 if (Opc != ISD::BUILD_VECTOR || 4367 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4368 return false; 4369 } else if (Idx >= 0) { 4370 unsigned Opc = V1.getOpcode(); 4371 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4372 continue; 4373 if (Opc != ISD::BUILD_VECTOR || 4374 !X86::isZeroNode(V1.getOperand(Idx))) 4375 return false; 4376 } 4377 } 4378 return true; 4379} 4380 4381/// getZeroVector - Returns a vector of specified type with all zero elements. 4382/// 4383static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4384 SelectionDAG &DAG, DebugLoc dl) { 4385 assert(VT.isVector() && "Expected a vector type"); 4386 4387 // Always build SSE zero vectors as <4 x i32> bitcasted 4388 // to their dest type. This ensures they get CSE'd. 4389 SDValue Vec; 4390 if (VT.is128BitVector()) { // SSE 4391 if (Subtarget->hasSSE2()) { // SSE2 4392 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4393 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4394 } else { // SSE1 4395 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4396 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4397 } 4398 } else if (VT.is256BitVector()) { // AVX 4399 if (Subtarget->hasInt256()) { // AVX2 4400 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4401 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4402 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4403 } else { 4404 // 256-bit logic and arithmetic instructions in AVX are all 4405 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4406 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4407 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4408 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4409 } 4410 } else 4411 llvm_unreachable("Unexpected vector type"); 4412 4413 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4414} 4415 4416/// getOnesVector - Returns a vector of specified type with all bits set. 4417/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4418/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4419/// Then bitcast to their original type, ensuring they get CSE'd. 4420static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG, 4421 DebugLoc dl) { 4422 assert(VT.isVector() && "Expected a vector type"); 4423 4424 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4425 SDValue Vec; 4426 if (VT.is256BitVector()) { 4427 if (HasInt256) { // AVX2 4428 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4429 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4430 } else { // AVX 4431 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4432 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); 4433 } 4434 } else if (VT.is128BitVector()) { 4435 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4436 } else 4437 llvm_unreachable("Unexpected vector type"); 4438 4439 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4440} 4441 4442/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4443/// that point to V2 points to its first element. 4444static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4445 for (unsigned i = 0; i != NumElems; ++i) { 4446 if (Mask[i] > (int)NumElems) { 4447 Mask[i] = NumElems; 4448 } 4449 } 4450} 4451 4452/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4453/// operation of specified width. 4454static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4455 SDValue V2) { 4456 unsigned NumElems = VT.getVectorNumElements(); 4457 SmallVector<int, 8> Mask; 4458 Mask.push_back(NumElems); 4459 for (unsigned i = 1; i != NumElems; ++i) 4460 Mask.push_back(i); 4461 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4462} 4463 4464/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4465static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4466 SDValue V2) { 4467 unsigned NumElems = VT.getVectorNumElements(); 4468 SmallVector<int, 8> Mask; 4469 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4470 Mask.push_back(i); 4471 Mask.push_back(i + NumElems); 4472 } 4473 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4474} 4475 4476/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4477static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4478 SDValue V2) { 4479 unsigned NumElems = VT.getVectorNumElements(); 4480 SmallVector<int, 8> Mask; 4481 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) { 4482 Mask.push_back(i + Half); 4483 Mask.push_back(i + NumElems + Half); 4484 } 4485 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4486} 4487 4488// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4489// a generic shuffle instruction because the target has no such instructions. 4490// Generate shuffles which repeat i16 and i8 several times until they can be 4491// represented by v4f32 and then be manipulated by target suported shuffles. 4492static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4493 EVT VT = V.getValueType(); 4494 int NumElems = VT.getVectorNumElements(); 4495 DebugLoc dl = V.getDebugLoc(); 4496 4497 while (NumElems > 4) { 4498 if (EltNo < NumElems/2) { 4499 V = getUnpackl(DAG, dl, VT, V, V); 4500 } else { 4501 V = getUnpackh(DAG, dl, VT, V, V); 4502 EltNo -= NumElems/2; 4503 } 4504 NumElems >>= 1; 4505 } 4506 return V; 4507} 4508 4509/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4510static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4511 EVT VT = V.getValueType(); 4512 DebugLoc dl = V.getDebugLoc(); 4513 4514 if (VT.is128BitVector()) { 4515 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4516 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4517 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4518 &SplatMask[0]); 4519 } else if (VT.is256BitVector()) { 4520 // To use VPERMILPS to splat scalars, the second half of indicies must 4521 // refer to the higher part, which is a duplication of the lower one, 4522 // because VPERMILPS can only handle in-lane permutations. 4523 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4524 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4525 4526 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4527 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4528 &SplatMask[0]); 4529 } else 4530 llvm_unreachable("Vector size not supported"); 4531 4532 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4533} 4534 4535/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4536static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4537 EVT SrcVT = SV->getValueType(0); 4538 SDValue V1 = SV->getOperand(0); 4539 DebugLoc dl = SV->getDebugLoc(); 4540 4541 int EltNo = SV->getSplatIndex(); 4542 int NumElems = SrcVT.getVectorNumElements(); 4543 bool Is256BitVec = SrcVT.is256BitVector(); 4544 4545 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) && 4546 "Unknown how to promote splat for type"); 4547 4548 // Extract the 128-bit part containing the splat element and update 4549 // the splat element index when it refers to the higher register. 4550 if (Is256BitVec) { 4551 V1 = Extract128BitVector(V1, EltNo, DAG, dl); 4552 if (EltNo >= NumElems/2) 4553 EltNo -= NumElems/2; 4554 } 4555 4556 // All i16 and i8 vector types can't be used directly by a generic shuffle 4557 // instruction because the target has no such instruction. Generate shuffles 4558 // which repeat i16 and i8 several times until they fit in i32, and then can 4559 // be manipulated by target suported shuffles. 4560 EVT EltVT = SrcVT.getVectorElementType(); 4561 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4562 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4563 4564 // Recreate the 256-bit vector and place the same 128-bit vector 4565 // into the low and high part. This is necessary because we want 4566 // to use VPERM* to shuffle the vectors 4567 if (Is256BitVec) { 4568 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 4569 } 4570 4571 return getLegalSplat(DAG, V1, EltNo); 4572} 4573 4574/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4575/// vector of zero or undef vector. This produces a shuffle where the low 4576/// element of V2 is swizzled into the zero/undef vector, landing at element 4577/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4578static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4579 bool IsZero, 4580 const X86Subtarget *Subtarget, 4581 SelectionDAG &DAG) { 4582 EVT VT = V2.getValueType(); 4583 SDValue V1 = IsZero 4584 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4585 unsigned NumElems = VT.getVectorNumElements(); 4586 SmallVector<int, 16> MaskVec; 4587 for (unsigned i = 0; i != NumElems; ++i) 4588 // If this is the insertion idx, put the low elt of V2 here. 4589 MaskVec.push_back(i == Idx ? NumElems : i); 4590 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4591} 4592 4593/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4594/// target specific opcode. Returns true if the Mask could be calculated. 4595/// Sets IsUnary to true if only uses one source. 4596static bool getTargetShuffleMask(SDNode *N, MVT VT, 4597 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4598 unsigned NumElems = VT.getVectorNumElements(); 4599 SDValue ImmN; 4600 4601 IsUnary = false; 4602 switch(N->getOpcode()) { 4603 case X86ISD::SHUFP: 4604 ImmN = N->getOperand(N->getNumOperands()-1); 4605 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4606 break; 4607 case X86ISD::UNPCKH: 4608 DecodeUNPCKHMask(VT, Mask); 4609 break; 4610 case X86ISD::UNPCKL: 4611 DecodeUNPCKLMask(VT, Mask); 4612 break; 4613 case X86ISD::MOVHLPS: 4614 DecodeMOVHLPSMask(NumElems, Mask); 4615 break; 4616 case X86ISD::MOVLHPS: 4617 DecodeMOVLHPSMask(NumElems, Mask); 4618 break; 4619 case X86ISD::PALIGNR: 4620 ImmN = N->getOperand(N->getNumOperands()-1); 4621 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4622 break; 4623 case X86ISD::PSHUFD: 4624 case X86ISD::VPERMILP: 4625 ImmN = N->getOperand(N->getNumOperands()-1); 4626 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4627 IsUnary = true; 4628 break; 4629 case X86ISD::PSHUFHW: 4630 ImmN = N->getOperand(N->getNumOperands()-1); 4631 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4632 IsUnary = true; 4633 break; 4634 case X86ISD::PSHUFLW: 4635 ImmN = N->getOperand(N->getNumOperands()-1); 4636 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4637 IsUnary = true; 4638 break; 4639 case X86ISD::VPERMI: 4640 ImmN = N->getOperand(N->getNumOperands()-1); 4641 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4642 IsUnary = true; 4643 break; 4644 case X86ISD::MOVSS: 4645 case X86ISD::MOVSD: { 4646 // The index 0 always comes from the first element of the second source, 4647 // this is why MOVSS and MOVSD are used in the first place. The other 4648 // elements come from the other positions of the first source vector 4649 Mask.push_back(NumElems); 4650 for (unsigned i = 1; i != NumElems; ++i) { 4651 Mask.push_back(i); 4652 } 4653 break; 4654 } 4655 case X86ISD::VPERM2X128: 4656 ImmN = N->getOperand(N->getNumOperands()-1); 4657 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4658 if (Mask.empty()) return false; 4659 break; 4660 case X86ISD::MOVDDUP: 4661 case X86ISD::MOVLHPD: 4662 case X86ISD::MOVLPD: 4663 case X86ISD::MOVLPS: 4664 case X86ISD::MOVSHDUP: 4665 case X86ISD::MOVSLDUP: 4666 // Not yet implemented 4667 return false; 4668 default: llvm_unreachable("unknown target shuffle node"); 4669 } 4670 4671 return true; 4672} 4673 4674/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4675/// element of the result of the vector shuffle. 4676static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4677 unsigned Depth) { 4678 if (Depth == 6) 4679 return SDValue(); // Limit search depth. 4680 4681 SDValue V = SDValue(N, 0); 4682 EVT VT = V.getValueType(); 4683 unsigned Opcode = V.getOpcode(); 4684 4685 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4686 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4687 int Elt = SV->getMaskElt(Index); 4688 4689 if (Elt < 0) 4690 return DAG.getUNDEF(VT.getVectorElementType()); 4691 4692 unsigned NumElems = VT.getVectorNumElements(); 4693 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4694 : SV->getOperand(1); 4695 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4696 } 4697 4698 // Recurse into target specific vector shuffles to find scalars. 4699 if (isTargetShuffle(Opcode)) { 4700 MVT ShufVT = V.getValueType().getSimpleVT(); 4701 unsigned NumElems = ShufVT.getVectorNumElements(); 4702 SmallVector<int, 16> ShuffleMask; 4703 bool IsUnary; 4704 4705 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary)) 4706 return SDValue(); 4707 4708 int Elt = ShuffleMask[Index]; 4709 if (Elt < 0) 4710 return DAG.getUNDEF(ShufVT.getVectorElementType()); 4711 4712 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4713 : N->getOperand(1); 4714 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4715 Depth+1); 4716 } 4717 4718 // Actual nodes that may contain scalar elements 4719 if (Opcode == ISD::BITCAST) { 4720 V = V.getOperand(0); 4721 EVT SrcVT = V.getValueType(); 4722 unsigned NumElems = VT.getVectorNumElements(); 4723 4724 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4725 return SDValue(); 4726 } 4727 4728 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4729 return (Index == 0) ? V.getOperand(0) 4730 : DAG.getUNDEF(VT.getVectorElementType()); 4731 4732 if (V.getOpcode() == ISD::BUILD_VECTOR) 4733 return V.getOperand(Index); 4734 4735 return SDValue(); 4736} 4737 4738/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4739/// shuffle operation which come from a consecutively from a zero. The 4740/// search can start in two different directions, from left or right. 4741static 4742unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4743 bool ZerosFromLeft, SelectionDAG &DAG) { 4744 unsigned i; 4745 for (i = 0; i != NumElems; ++i) { 4746 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4747 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4748 if (!(Elt.getNode() && 4749 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4750 break; 4751 } 4752 4753 return i; 4754} 4755 4756/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4757/// correspond consecutively to elements from one of the vector operands, 4758/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4759static 4760bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4761 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4762 unsigned NumElems, unsigned &OpNum) { 4763 bool SeenV1 = false; 4764 bool SeenV2 = false; 4765 4766 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4767 int Idx = SVOp->getMaskElt(i); 4768 // Ignore undef indicies 4769 if (Idx < 0) 4770 continue; 4771 4772 if (Idx < (int)NumElems) 4773 SeenV1 = true; 4774 else 4775 SeenV2 = true; 4776 4777 // Only accept consecutive elements from the same vector 4778 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4779 return false; 4780 } 4781 4782 OpNum = SeenV1 ? 0 : 1; 4783 return true; 4784} 4785 4786/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4787/// logical left shift of a vector. 4788static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4789 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4790 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4791 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4792 false /* check zeros from right */, DAG); 4793 unsigned OpSrc; 4794 4795 if (!NumZeros) 4796 return false; 4797 4798 // Considering the elements in the mask that are not consecutive zeros, 4799 // check if they consecutively come from only one of the source vectors. 4800 // 4801 // V1 = {X, A, B, C} 0 4802 // \ \ \ / 4803 // vector_shuffle V1, V2 <1, 2, 3, X> 4804 // 4805 if (!isShuffleMaskConsecutive(SVOp, 4806 0, // Mask Start Index 4807 NumElems-NumZeros, // Mask End Index(exclusive) 4808 NumZeros, // Where to start looking in the src vector 4809 NumElems, // Number of elements in vector 4810 OpSrc)) // Which source operand ? 4811 return false; 4812 4813 isLeft = false; 4814 ShAmt = NumZeros; 4815 ShVal = SVOp->getOperand(OpSrc); 4816 return true; 4817} 4818 4819/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4820/// logical left shift of a vector. 4821static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4822 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4823 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4824 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4825 true /* check zeros from left */, DAG); 4826 unsigned OpSrc; 4827 4828 if (!NumZeros) 4829 return false; 4830 4831 // Considering the elements in the mask that are not consecutive zeros, 4832 // check if they consecutively come from only one of the source vectors. 4833 // 4834 // 0 { A, B, X, X } = V2 4835 // / \ / / 4836 // vector_shuffle V1, V2 <X, X, 4, 5> 4837 // 4838 if (!isShuffleMaskConsecutive(SVOp, 4839 NumZeros, // Mask Start Index 4840 NumElems, // Mask End Index(exclusive) 4841 0, // Where to start looking in the src vector 4842 NumElems, // Number of elements in vector 4843 OpSrc)) // Which source operand ? 4844 return false; 4845 4846 isLeft = true; 4847 ShAmt = NumZeros; 4848 ShVal = SVOp->getOperand(OpSrc); 4849 return true; 4850} 4851 4852/// isVectorShift - Returns true if the shuffle can be implemented as a 4853/// logical left or right shift of a vector. 4854static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4855 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4856 // Although the logic below support any bitwidth size, there are no 4857 // shift instructions which handle more than 128-bit vectors. 4858 if (!SVOp->getValueType(0).is128BitVector()) 4859 return false; 4860 4861 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4862 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4863 return true; 4864 4865 return false; 4866} 4867 4868/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4869/// 4870static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4871 unsigned NumNonZero, unsigned NumZero, 4872 SelectionDAG &DAG, 4873 const X86Subtarget* Subtarget, 4874 const TargetLowering &TLI) { 4875 if (NumNonZero > 8) 4876 return SDValue(); 4877 4878 DebugLoc dl = Op.getDebugLoc(); 4879 SDValue V(0, 0); 4880 bool First = true; 4881 for (unsigned i = 0; i < 16; ++i) { 4882 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4883 if (ThisIsNonZero && First) { 4884 if (NumZero) 4885 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4886 else 4887 V = DAG.getUNDEF(MVT::v8i16); 4888 First = false; 4889 } 4890 4891 if ((i & 1) != 0) { 4892 SDValue ThisElt(0, 0), LastElt(0, 0); 4893 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4894 if (LastIsNonZero) { 4895 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4896 MVT::i16, Op.getOperand(i-1)); 4897 } 4898 if (ThisIsNonZero) { 4899 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4900 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4901 ThisElt, DAG.getConstant(8, MVT::i8)); 4902 if (LastIsNonZero) 4903 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4904 } else 4905 ThisElt = LastElt; 4906 4907 if (ThisElt.getNode()) 4908 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4909 DAG.getIntPtrConstant(i/2)); 4910 } 4911 } 4912 4913 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4914} 4915 4916/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4917/// 4918static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4919 unsigned NumNonZero, unsigned NumZero, 4920 SelectionDAG &DAG, 4921 const X86Subtarget* Subtarget, 4922 const TargetLowering &TLI) { 4923 if (NumNonZero > 4) 4924 return SDValue(); 4925 4926 DebugLoc dl = Op.getDebugLoc(); 4927 SDValue V(0, 0); 4928 bool First = true; 4929 for (unsigned i = 0; i < 8; ++i) { 4930 bool isNonZero = (NonZeros & (1 << i)) != 0; 4931 if (isNonZero) { 4932 if (First) { 4933 if (NumZero) 4934 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4935 else 4936 V = DAG.getUNDEF(MVT::v8i16); 4937 First = false; 4938 } 4939 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4940 MVT::v8i16, V, Op.getOperand(i), 4941 DAG.getIntPtrConstant(i)); 4942 } 4943 } 4944 4945 return V; 4946} 4947 4948/// getVShift - Return a vector logical shift node. 4949/// 4950static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4951 unsigned NumBits, SelectionDAG &DAG, 4952 const TargetLowering &TLI, DebugLoc dl) { 4953 assert(VT.is128BitVector() && "Unknown type for VShift"); 4954 EVT ShVT = MVT::v2i64; 4955 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4956 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4957 return DAG.getNode(ISD::BITCAST, dl, VT, 4958 DAG.getNode(Opc, dl, ShVT, SrcOp, 4959 DAG.getConstant(NumBits, 4960 TLI.getScalarShiftAmountTy(SrcOp.getValueType())))); 4961} 4962 4963SDValue 4964X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4965 SelectionDAG &DAG) const { 4966 4967 // Check if the scalar load can be widened into a vector load. And if 4968 // the address is "base + cst" see if the cst can be "absorbed" into 4969 // the shuffle mask. 4970 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4971 SDValue Ptr = LD->getBasePtr(); 4972 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4973 return SDValue(); 4974 EVT PVT = LD->getValueType(0); 4975 if (PVT != MVT::i32 && PVT != MVT::f32) 4976 return SDValue(); 4977 4978 int FI = -1; 4979 int64_t Offset = 0; 4980 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4981 FI = FINode->getIndex(); 4982 Offset = 0; 4983 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4984 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4985 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4986 Offset = Ptr.getConstantOperandVal(1); 4987 Ptr = Ptr.getOperand(0); 4988 } else { 4989 return SDValue(); 4990 } 4991 4992 // FIXME: 256-bit vector instructions don't require a strict alignment, 4993 // improve this code to support it better. 4994 unsigned RequiredAlign = VT.getSizeInBits()/8; 4995 SDValue Chain = LD->getChain(); 4996 // Make sure the stack object alignment is at least 16 or 32. 4997 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4998 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4999 if (MFI->isFixedObjectIndex(FI)) { 5000 // Can't change the alignment. FIXME: It's possible to compute 5001 // the exact stack offset and reference FI + adjust offset instead. 5002 // If someone *really* cares about this. That's the way to implement it. 5003 return SDValue(); 5004 } else { 5005 MFI->setObjectAlignment(FI, RequiredAlign); 5006 } 5007 } 5008 5009 // (Offset % 16 or 32) must be multiple of 4. Then address is then 5010 // Ptr + (Offset & ~15). 5011 if (Offset < 0) 5012 return SDValue(); 5013 if ((Offset % RequiredAlign) & 3) 5014 return SDValue(); 5015 int64_t StartOffset = Offset & ~(RequiredAlign-1); 5016 if (StartOffset) 5017 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 5018 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 5019 5020 int EltNo = (Offset - StartOffset) >> 2; 5021 unsigned NumElems = VT.getVectorNumElements(); 5022 5023 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 5024 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 5025 LD->getPointerInfo().getWithOffset(StartOffset), 5026 false, false, false, 0); 5027 5028 SmallVector<int, 8> Mask; 5029 for (unsigned i = 0; i != NumElems; ++i) 5030 Mask.push_back(EltNo); 5031 5032 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 5033 } 5034 5035 return SDValue(); 5036} 5037 5038/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 5039/// vector of type 'VT', see if the elements can be replaced by a single large 5040/// load which has the same value as a build_vector whose operands are 'elts'. 5041/// 5042/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 5043/// 5044/// FIXME: we'd also like to handle the case where the last elements are zero 5045/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 5046/// There's even a handy isZeroNode for that purpose. 5047static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 5048 DebugLoc &DL, SelectionDAG &DAG) { 5049 EVT EltVT = VT.getVectorElementType(); 5050 unsigned NumElems = Elts.size(); 5051 5052 LoadSDNode *LDBase = NULL; 5053 unsigned LastLoadedElt = -1U; 5054 5055 // For each element in the initializer, see if we've found a load or an undef. 5056 // If we don't find an initial load element, or later load elements are 5057 // non-consecutive, bail out. 5058 for (unsigned i = 0; i < NumElems; ++i) { 5059 SDValue Elt = Elts[i]; 5060 5061 if (!Elt.getNode() || 5062 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 5063 return SDValue(); 5064 if (!LDBase) { 5065 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 5066 return SDValue(); 5067 LDBase = cast<LoadSDNode>(Elt.getNode()); 5068 LastLoadedElt = i; 5069 continue; 5070 } 5071 if (Elt.getOpcode() == ISD::UNDEF) 5072 continue; 5073 5074 LoadSDNode *LD = cast<LoadSDNode>(Elt); 5075 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 5076 return SDValue(); 5077 LastLoadedElt = i; 5078 } 5079 5080 // If we have found an entire vector of loads and undefs, then return a large 5081 // load of the entire vector width starting at the base pointer. If we found 5082 // consecutive loads for the low half, generate a vzext_load node. 5083 if (LastLoadedElt == NumElems - 1) { 5084 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 5085 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5086 LDBase->getPointerInfo(), 5087 LDBase->isVolatile(), LDBase->isNonTemporal(), 5088 LDBase->isInvariant(), 0); 5089 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5090 LDBase->getPointerInfo(), 5091 LDBase->isVolatile(), LDBase->isNonTemporal(), 5092 LDBase->isInvariant(), LDBase->getAlignment()); 5093 } 5094 if (NumElems == 4 && LastLoadedElt == 1 && 5095 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 5096 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 5097 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 5098 SDValue ResNode = 5099 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 5100 LDBase->getPointerInfo(), 5101 LDBase->getAlignment(), 5102 false/*isVolatile*/, true/*ReadMem*/, 5103 false/*WriteMem*/); 5104 5105 // Make sure the newly-created LOAD is in the same position as LDBase in 5106 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and 5107 // update uses of LDBase's output chain to use the TokenFactor. 5108 if (LDBase->hasAnyUseOfValue(1)) { 5109 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 5110 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1)); 5111 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain); 5112 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1), 5113 SDValue(ResNode.getNode(), 1)); 5114 } 5115 5116 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 5117 } 5118 return SDValue(); 5119} 5120 5121/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 5122/// to generate a splat value for the following cases: 5123/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 5124/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 5125/// a scalar load, or a constant. 5126/// The VBROADCAST node is returned when a pattern is found, 5127/// or SDValue() otherwise. 5128SDValue 5129X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const { 5130 if (!Subtarget->hasFp256()) 5131 return SDValue(); 5132 5133 MVT VT = Op.getValueType().getSimpleVT(); 5134 DebugLoc dl = Op.getDebugLoc(); 5135 5136 assert((VT.is128BitVector() || VT.is256BitVector()) && 5137 "Unsupported vector type for broadcast."); 5138 5139 SDValue Ld; 5140 bool ConstSplatVal; 5141 5142 switch (Op.getOpcode()) { 5143 default: 5144 // Unknown pattern found. 5145 return SDValue(); 5146 5147 case ISD::BUILD_VECTOR: { 5148 // The BUILD_VECTOR node must be a splat. 5149 if (!isSplatVector(Op.getNode())) 5150 return SDValue(); 5151 5152 Ld = Op.getOperand(0); 5153 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5154 Ld.getOpcode() == ISD::ConstantFP); 5155 5156 // The suspected load node has several users. Make sure that all 5157 // of its users are from the BUILD_VECTOR node. 5158 // Constants may have multiple users. 5159 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 5160 return SDValue(); 5161 break; 5162 } 5163 5164 case ISD::VECTOR_SHUFFLE: { 5165 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5166 5167 // Shuffles must have a splat mask where the first element is 5168 // broadcasted. 5169 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 5170 return SDValue(); 5171 5172 SDValue Sc = Op.getOperand(0); 5173 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR && 5174 Sc.getOpcode() != ISD::BUILD_VECTOR) { 5175 5176 if (!Subtarget->hasInt256()) 5177 return SDValue(); 5178 5179 // Use the register form of the broadcast instruction available on AVX2. 5180 if (VT.is256BitVector()) 5181 Sc = Extract128BitVector(Sc, 0, DAG, dl); 5182 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc); 5183 } 5184 5185 Ld = Sc.getOperand(0); 5186 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5187 Ld.getOpcode() == ISD::ConstantFP); 5188 5189 // The scalar_to_vector node and the suspected 5190 // load node must have exactly one user. 5191 // Constants may have multiple users. 5192 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 5193 return SDValue(); 5194 break; 5195 } 5196 } 5197 5198 bool Is256 = VT.is256BitVector(); 5199 5200 // Handle the broadcasting a single constant scalar from the constant pool 5201 // into a vector. On Sandybridge it is still better to load a constant vector 5202 // from the constant pool and not to broadcast it from a scalar. 5203 if (ConstSplatVal && Subtarget->hasInt256()) { 5204 EVT CVT = Ld.getValueType(); 5205 assert(!CVT.isVector() && "Must not broadcast a vector type"); 5206 unsigned ScalarSize = CVT.getSizeInBits(); 5207 5208 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) { 5209 const Constant *C = 0; 5210 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 5211 C = CI->getConstantIntValue(); 5212 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 5213 C = CF->getConstantFPValue(); 5214 5215 assert(C && "Invalid constant type"); 5216 5217 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 5218 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 5219 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 5220 MachinePointerInfo::getConstantPool(), 5221 false, false, false, Alignment); 5222 5223 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5224 } 5225 } 5226 5227 bool IsLoad = ISD::isNormalLoad(Ld.getNode()); 5228 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5229 5230 // Handle AVX2 in-register broadcasts. 5231 if (!IsLoad && Subtarget->hasInt256() && 5232 (ScalarSize == 32 || (Is256 && ScalarSize == 64))) 5233 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5234 5235 // The scalar source must be a normal load. 5236 if (!IsLoad) 5237 return SDValue(); 5238 5239 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) 5240 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5241 5242 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5243 // double since there is no vbroadcastsd xmm 5244 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) { 5245 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64) 5246 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5247 } 5248 5249 // Unsupported broadcast. 5250 return SDValue(); 5251} 5252 5253SDValue 5254X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const { 5255 EVT VT = Op.getValueType(); 5256 5257 // Skip if insert_vec_elt is not supported. 5258 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT)) 5259 return SDValue(); 5260 5261 DebugLoc DL = Op.getDebugLoc(); 5262 unsigned NumElems = Op.getNumOperands(); 5263 5264 SDValue VecIn1; 5265 SDValue VecIn2; 5266 SmallVector<unsigned, 4> InsertIndices; 5267 SmallVector<int, 8> Mask(NumElems, -1); 5268 5269 for (unsigned i = 0; i != NumElems; ++i) { 5270 unsigned Opc = Op.getOperand(i).getOpcode(); 5271 5272 if (Opc == ISD::UNDEF) 5273 continue; 5274 5275 if (Opc != ISD::EXTRACT_VECTOR_ELT) { 5276 // Quit if more than 1 elements need inserting. 5277 if (InsertIndices.size() > 1) 5278 return SDValue(); 5279 5280 InsertIndices.push_back(i); 5281 continue; 5282 } 5283 5284 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0); 5285 SDValue ExtIdx = Op.getOperand(i).getOperand(1); 5286 5287 // Quit if extracted from vector of different type. 5288 if (ExtractedFromVec.getValueType() != VT) 5289 return SDValue(); 5290 5291 // Quit if non-constant index. 5292 if (!isa<ConstantSDNode>(ExtIdx)) 5293 return SDValue(); 5294 5295 if (VecIn1.getNode() == 0) 5296 VecIn1 = ExtractedFromVec; 5297 else if (VecIn1 != ExtractedFromVec) { 5298 if (VecIn2.getNode() == 0) 5299 VecIn2 = ExtractedFromVec; 5300 else if (VecIn2 != ExtractedFromVec) 5301 // Quit if more than 2 vectors to shuffle 5302 return SDValue(); 5303 } 5304 5305 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue(); 5306 5307 if (ExtractedFromVec == VecIn1) 5308 Mask[i] = Idx; 5309 else if (ExtractedFromVec == VecIn2) 5310 Mask[i] = Idx + NumElems; 5311 } 5312 5313 if (VecIn1.getNode() == 0) 5314 return SDValue(); 5315 5316 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5317 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]); 5318 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) { 5319 unsigned Idx = InsertIndices[i]; 5320 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx), 5321 DAG.getIntPtrConstant(Idx)); 5322 } 5323 5324 return NV; 5325} 5326 5327SDValue 5328X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5329 DebugLoc dl = Op.getDebugLoc(); 5330 5331 MVT VT = Op.getValueType().getSimpleVT(); 5332 MVT ExtVT = VT.getVectorElementType(); 5333 unsigned NumElems = Op.getNumOperands(); 5334 5335 // Vectors containing all zeros can be matched by pxor and xorps later 5336 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5337 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5338 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5339 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5340 return Op; 5341 5342 return getZeroVector(VT, Subtarget, DAG, dl); 5343 } 5344 5345 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5346 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5347 // vpcmpeqd on 256-bit vectors. 5348 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) { 5349 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256())) 5350 return Op; 5351 5352 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl); 5353 } 5354 5355 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5356 if (Broadcast.getNode()) 5357 return Broadcast; 5358 5359 unsigned EVTBits = ExtVT.getSizeInBits(); 5360 5361 unsigned NumZero = 0; 5362 unsigned NumNonZero = 0; 5363 unsigned NonZeros = 0; 5364 bool IsAllConstants = true; 5365 SmallSet<SDValue, 8> Values; 5366 for (unsigned i = 0; i < NumElems; ++i) { 5367 SDValue Elt = Op.getOperand(i); 5368 if (Elt.getOpcode() == ISD::UNDEF) 5369 continue; 5370 Values.insert(Elt); 5371 if (Elt.getOpcode() != ISD::Constant && 5372 Elt.getOpcode() != ISD::ConstantFP) 5373 IsAllConstants = false; 5374 if (X86::isZeroNode(Elt)) 5375 NumZero++; 5376 else { 5377 NonZeros |= (1 << i); 5378 NumNonZero++; 5379 } 5380 } 5381 5382 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5383 if (NumNonZero == 0) 5384 return DAG.getUNDEF(VT); 5385 5386 // Special case for single non-zero, non-undef, element. 5387 if (NumNonZero == 1) { 5388 unsigned Idx = CountTrailingZeros_32(NonZeros); 5389 SDValue Item = Op.getOperand(Idx); 5390 5391 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5392 // the value are obviously zero, truncate the value to i32 and do the 5393 // insertion that way. Only do this if the value is non-constant or if the 5394 // value is a constant being inserted into element 0. It is cheaper to do 5395 // a constant pool load than it is to do a movd + shuffle. 5396 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5397 (!IsAllConstants || Idx == 0)) { 5398 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5399 // Handle SSE only. 5400 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5401 EVT VecVT = MVT::v4i32; 5402 unsigned VecElts = 4; 5403 5404 // Truncate the value (which may itself be a constant) to i32, and 5405 // convert it to a vector with movd (S2V+shuffle to zero extend). 5406 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5407 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5408 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5409 5410 // Now we have our 32-bit value zero extended in the low element of 5411 // a vector. If Idx != 0, swizzle it into place. 5412 if (Idx != 0) { 5413 SmallVector<int, 4> Mask; 5414 Mask.push_back(Idx); 5415 for (unsigned i = 1; i != VecElts; ++i) 5416 Mask.push_back(i); 5417 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), 5418 &Mask[0]); 5419 } 5420 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5421 } 5422 } 5423 5424 // If we have a constant or non-constant insertion into the low element of 5425 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5426 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5427 // depending on what the source datatype is. 5428 if (Idx == 0) { 5429 if (NumZero == 0) 5430 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5431 5432 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5433 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5434 if (VT.is256BitVector()) { 5435 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5436 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5437 Item, DAG.getIntPtrConstant(0)); 5438 } 5439 assert(VT.is128BitVector() && "Expected an SSE value type!"); 5440 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5441 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5442 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5443 } 5444 5445 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5446 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5447 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5448 if (VT.is256BitVector()) { 5449 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5450 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl); 5451 } else { 5452 assert(VT.is128BitVector() && "Expected an SSE value type!"); 5453 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5454 } 5455 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5456 } 5457 } 5458 5459 // Is it a vector logical left shift? 5460 if (NumElems == 2 && Idx == 1 && 5461 X86::isZeroNode(Op.getOperand(0)) && 5462 !X86::isZeroNode(Op.getOperand(1))) { 5463 unsigned NumBits = VT.getSizeInBits(); 5464 return getVShift(true, VT, 5465 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5466 VT, Op.getOperand(1)), 5467 NumBits/2, DAG, *this, dl); 5468 } 5469 5470 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5471 return SDValue(); 5472 5473 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5474 // is a non-constant being inserted into an element other than the low one, 5475 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5476 // movd/movss) to move this into the low element, then shuffle it into 5477 // place. 5478 if (EVTBits == 32) { 5479 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5480 5481 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5482 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5483 SmallVector<int, 8> MaskVec; 5484 for (unsigned i = 0; i != NumElems; ++i) 5485 MaskVec.push_back(i == Idx ? 0 : 1); 5486 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5487 } 5488 } 5489 5490 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5491 if (Values.size() == 1) { 5492 if (EVTBits == 32) { 5493 // Instead of a shuffle like this: 5494 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5495 // Check if it's possible to issue this instead. 5496 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5497 unsigned Idx = CountTrailingZeros_32(NonZeros); 5498 SDValue Item = Op.getOperand(Idx); 5499 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5500 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5501 } 5502 return SDValue(); 5503 } 5504 5505 // A vector full of immediates; various special cases are already 5506 // handled, so this is best done with a single constant-pool load. 5507 if (IsAllConstants) 5508 return SDValue(); 5509 5510 // For AVX-length vectors, build the individual 128-bit pieces and use 5511 // shuffles to put them in place. 5512 if (VT.is256BitVector()) { 5513 SmallVector<SDValue, 32> V; 5514 for (unsigned i = 0; i != NumElems; ++i) 5515 V.push_back(Op.getOperand(i)); 5516 5517 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5518 5519 // Build both the lower and upper subvector. 5520 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5521 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5522 NumElems/2); 5523 5524 // Recreate the wider vector with the lower and upper part. 5525 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl); 5526 } 5527 5528 // Let legalizer expand 2-wide build_vectors. 5529 if (EVTBits == 64) { 5530 if (NumNonZero == 1) { 5531 // One half is zero or undef. 5532 unsigned Idx = CountTrailingZeros_32(NonZeros); 5533 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5534 Op.getOperand(Idx)); 5535 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5536 } 5537 return SDValue(); 5538 } 5539 5540 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5541 if (EVTBits == 8 && NumElems == 16) { 5542 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5543 Subtarget, *this); 5544 if (V.getNode()) return V; 5545 } 5546 5547 if (EVTBits == 16 && NumElems == 8) { 5548 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5549 Subtarget, *this); 5550 if (V.getNode()) return V; 5551 } 5552 5553 // If element VT is == 32 bits, turn it into a number of shuffles. 5554 SmallVector<SDValue, 8> V(NumElems); 5555 if (NumElems == 4 && NumZero > 0) { 5556 for (unsigned i = 0; i < 4; ++i) { 5557 bool isZero = !(NonZeros & (1 << i)); 5558 if (isZero) 5559 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5560 else 5561 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5562 } 5563 5564 for (unsigned i = 0; i < 2; ++i) { 5565 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5566 default: break; 5567 case 0: 5568 V[i] = V[i*2]; // Must be a zero vector. 5569 break; 5570 case 1: 5571 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5572 break; 5573 case 2: 5574 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5575 break; 5576 case 3: 5577 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5578 break; 5579 } 5580 } 5581 5582 bool Reverse1 = (NonZeros & 0x3) == 2; 5583 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5584 int MaskVec[] = { 5585 Reverse1 ? 1 : 0, 5586 Reverse1 ? 0 : 1, 5587 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5588 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5589 }; 5590 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5591 } 5592 5593 if (Values.size() > 1 && VT.is128BitVector()) { 5594 // Check for a build vector of consecutive loads. 5595 for (unsigned i = 0; i < NumElems; ++i) 5596 V[i] = Op.getOperand(i); 5597 5598 // Check for elements which are consecutive loads. 5599 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5600 if (LD.getNode()) 5601 return LD; 5602 5603 // Check for a build vector from mostly shuffle plus few inserting. 5604 SDValue Sh = buildFromShuffleMostly(Op, DAG); 5605 if (Sh.getNode()) 5606 return Sh; 5607 5608 // For SSE 4.1, use insertps to put the high elements into the low element. 5609 if (getSubtarget()->hasSSE41()) { 5610 SDValue Result; 5611 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5612 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5613 else 5614 Result = DAG.getUNDEF(VT); 5615 5616 for (unsigned i = 1; i < NumElems; ++i) { 5617 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5618 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5619 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5620 } 5621 return Result; 5622 } 5623 5624 // Otherwise, expand into a number of unpckl*, start by extending each of 5625 // our (non-undef) elements to the full vector width with the element in the 5626 // bottom slot of the vector (which generates no code for SSE). 5627 for (unsigned i = 0; i < NumElems; ++i) { 5628 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5629 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5630 else 5631 V[i] = DAG.getUNDEF(VT); 5632 } 5633 5634 // Next, we iteratively mix elements, e.g. for v4f32: 5635 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5636 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5637 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5638 unsigned EltStride = NumElems >> 1; 5639 while (EltStride != 0) { 5640 for (unsigned i = 0; i < EltStride; ++i) { 5641 // If V[i+EltStride] is undef and this is the first round of mixing, 5642 // then it is safe to just drop this shuffle: V[i] is already in the 5643 // right place, the one element (since it's the first round) being 5644 // inserted as undef can be dropped. This isn't safe for successive 5645 // rounds because they will permute elements within both vectors. 5646 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5647 EltStride == NumElems/2) 5648 continue; 5649 5650 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5651 } 5652 EltStride >>= 1; 5653 } 5654 return V[0]; 5655 } 5656 return SDValue(); 5657} 5658 5659// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5660// to create 256-bit vectors from two other 128-bit ones. 5661static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5662 DebugLoc dl = Op.getDebugLoc(); 5663 MVT ResVT = Op.getValueType().getSimpleVT(); 5664 5665 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide"); 5666 5667 SDValue V1 = Op.getOperand(0); 5668 SDValue V2 = Op.getOperand(1); 5669 unsigned NumElems = ResVT.getVectorNumElements(); 5670 5671 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 5672} 5673 5674static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5675 assert(Op.getNumOperands() == 2); 5676 5677 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5678 // from two other 128-bit ones. 5679 return LowerAVXCONCAT_VECTORS(Op, DAG); 5680} 5681 5682// Try to lower a shuffle node into a simple blend instruction. 5683static SDValue 5684LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, 5685 const X86Subtarget *Subtarget, SelectionDAG &DAG) { 5686 SDValue V1 = SVOp->getOperand(0); 5687 SDValue V2 = SVOp->getOperand(1); 5688 DebugLoc dl = SVOp->getDebugLoc(); 5689 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5690 MVT EltVT = VT.getVectorElementType(); 5691 unsigned NumElems = VT.getVectorNumElements(); 5692 5693 if (!Subtarget->hasSSE41() || EltVT == MVT::i8) 5694 return SDValue(); 5695 if (!Subtarget->hasInt256() && VT == MVT::v16i16) 5696 return SDValue(); 5697 5698 // Check the mask for BLEND and build the value. 5699 unsigned MaskValue = 0; 5700 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise. 5701 unsigned NumLanes = (NumElems-1)/8 + 1; 5702 unsigned NumElemsInLane = NumElems / NumLanes; 5703 5704 // Blend for v16i16 should be symetric for the both lanes. 5705 for (unsigned i = 0; i < NumElemsInLane; ++i) { 5706 5707 int SndLaneEltIdx = (NumLanes == 2) ? 5708 SVOp->getMaskElt(i + NumElemsInLane) : -1; 5709 int EltIdx = SVOp->getMaskElt(i); 5710 5711 if ((EltIdx < 0 || EltIdx == (int)i) && 5712 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane))) 5713 continue; 5714 5715 if (((unsigned)EltIdx == (i + NumElems)) && 5716 (SndLaneEltIdx < 0 || 5717 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane)) 5718 MaskValue |= (1<<i); 5719 else 5720 return SDValue(); 5721 } 5722 5723 // Convert i32 vectors to floating point if it is not AVX2. 5724 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors. 5725 MVT BlendVT = VT; 5726 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) { 5727 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()), 5728 NumElems); 5729 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1); 5730 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2); 5731 } 5732 5733 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2, 5734 DAG.getConstant(MaskValue, MVT::i32)); 5735 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 5736} 5737 5738// v8i16 shuffles - Prefer shuffles in the following order: 5739// 1. [all] pshuflw, pshufhw, optional move 5740// 2. [ssse3] 1 x pshufb 5741// 3. [ssse3] 2 x pshufb + 1 x por 5742// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5743static SDValue 5744LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget, 5745 SelectionDAG &DAG) { 5746 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5747 SDValue V1 = SVOp->getOperand(0); 5748 SDValue V2 = SVOp->getOperand(1); 5749 DebugLoc dl = SVOp->getDebugLoc(); 5750 SmallVector<int, 8> MaskVals; 5751 5752 // Determine if more than 1 of the words in each of the low and high quadwords 5753 // of the result come from the same quadword of one of the two inputs. Undef 5754 // mask values count as coming from any quadword, for better codegen. 5755 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5756 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5757 std::bitset<4> InputQuads; 5758 for (unsigned i = 0; i < 8; ++i) { 5759 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5760 int EltIdx = SVOp->getMaskElt(i); 5761 MaskVals.push_back(EltIdx); 5762 if (EltIdx < 0) { 5763 ++Quad[0]; 5764 ++Quad[1]; 5765 ++Quad[2]; 5766 ++Quad[3]; 5767 continue; 5768 } 5769 ++Quad[EltIdx / 4]; 5770 InputQuads.set(EltIdx / 4); 5771 } 5772 5773 int BestLoQuad = -1; 5774 unsigned MaxQuad = 1; 5775 for (unsigned i = 0; i < 4; ++i) { 5776 if (LoQuad[i] > MaxQuad) { 5777 BestLoQuad = i; 5778 MaxQuad = LoQuad[i]; 5779 } 5780 } 5781 5782 int BestHiQuad = -1; 5783 MaxQuad = 1; 5784 for (unsigned i = 0; i < 4; ++i) { 5785 if (HiQuad[i] > MaxQuad) { 5786 BestHiQuad = i; 5787 MaxQuad = HiQuad[i]; 5788 } 5789 } 5790 5791 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5792 // of the two input vectors, shuffle them into one input vector so only a 5793 // single pshufb instruction is necessary. If There are more than 2 input 5794 // quads, disable the next transformation since it does not help SSSE3. 5795 bool V1Used = InputQuads[0] || InputQuads[1]; 5796 bool V2Used = InputQuads[2] || InputQuads[3]; 5797 if (Subtarget->hasSSSE3()) { 5798 if (InputQuads.count() == 2 && V1Used && V2Used) { 5799 BestLoQuad = InputQuads[0] ? 0 : 1; 5800 BestHiQuad = InputQuads[2] ? 2 : 3; 5801 } 5802 if (InputQuads.count() > 2) { 5803 BestLoQuad = -1; 5804 BestHiQuad = -1; 5805 } 5806 } 5807 5808 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5809 // the shuffle mask. If a quad is scored as -1, that means that it contains 5810 // words from all 4 input quadwords. 5811 SDValue NewV; 5812 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5813 int MaskV[] = { 5814 BestLoQuad < 0 ? 0 : BestLoQuad, 5815 BestHiQuad < 0 ? 1 : BestHiQuad 5816 }; 5817 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5818 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5819 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5820 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5821 5822 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5823 // source words for the shuffle, to aid later transformations. 5824 bool AllWordsInNewV = true; 5825 bool InOrder[2] = { true, true }; 5826 for (unsigned i = 0; i != 8; ++i) { 5827 int idx = MaskVals[i]; 5828 if (idx != (int)i) 5829 InOrder[i/4] = false; 5830 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5831 continue; 5832 AllWordsInNewV = false; 5833 break; 5834 } 5835 5836 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5837 if (AllWordsInNewV) { 5838 for (int i = 0; i != 8; ++i) { 5839 int idx = MaskVals[i]; 5840 if (idx < 0) 5841 continue; 5842 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5843 if ((idx != i) && idx < 4) 5844 pshufhw = false; 5845 if ((idx != i) && idx > 3) 5846 pshuflw = false; 5847 } 5848 V1 = NewV; 5849 V2Used = false; 5850 BestLoQuad = 0; 5851 BestHiQuad = 1; 5852 } 5853 5854 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5855 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5856 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5857 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5858 unsigned TargetMask = 0; 5859 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5860 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5861 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5862 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5863 getShufflePSHUFLWImmediate(SVOp); 5864 V1 = NewV.getOperand(0); 5865 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5866 } 5867 } 5868 5869 // Promote splats to a larger type which usually leads to more efficient code. 5870 // FIXME: Is this true if pshufb is available? 5871 if (SVOp->isSplat()) 5872 return PromoteSplat(SVOp, DAG); 5873 5874 // If we have SSSE3, and all words of the result are from 1 input vector, 5875 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5876 // is present, fall back to case 4. 5877 if (Subtarget->hasSSSE3()) { 5878 SmallVector<SDValue,16> pshufbMask; 5879 5880 // If we have elements from both input vectors, set the high bit of the 5881 // shuffle mask element to zero out elements that come from V2 in the V1 5882 // mask, and elements that come from V1 in the V2 mask, so that the two 5883 // results can be OR'd together. 5884 bool TwoInputs = V1Used && V2Used; 5885 for (unsigned i = 0; i != 8; ++i) { 5886 int EltIdx = MaskVals[i] * 2; 5887 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx; 5888 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1; 5889 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 5890 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 5891 } 5892 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5893 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5894 DAG.getNode(ISD::BUILD_VECTOR, dl, 5895 MVT::v16i8, &pshufbMask[0], 16)); 5896 if (!TwoInputs) 5897 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5898 5899 // Calculate the shuffle mask for the second input, shuffle it, and 5900 // OR it with the first shuffled input. 5901 pshufbMask.clear(); 5902 for (unsigned i = 0; i != 8; ++i) { 5903 int EltIdx = MaskVals[i] * 2; 5904 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16; 5905 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15; 5906 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 5907 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 5908 } 5909 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5910 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5911 DAG.getNode(ISD::BUILD_VECTOR, dl, 5912 MVT::v16i8, &pshufbMask[0], 16)); 5913 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5914 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5915 } 5916 5917 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5918 // and update MaskVals with new element order. 5919 std::bitset<8> InOrder; 5920 if (BestLoQuad >= 0) { 5921 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5922 for (int i = 0; i != 4; ++i) { 5923 int idx = MaskVals[i]; 5924 if (idx < 0) { 5925 InOrder.set(i); 5926 } else if ((idx / 4) == BestLoQuad) { 5927 MaskV[i] = idx & 3; 5928 InOrder.set(i); 5929 } 5930 } 5931 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5932 &MaskV[0]); 5933 5934 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5935 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5936 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5937 NewV.getOperand(0), 5938 getShufflePSHUFLWImmediate(SVOp), DAG); 5939 } 5940 } 5941 5942 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5943 // and update MaskVals with the new element order. 5944 if (BestHiQuad >= 0) { 5945 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5946 for (unsigned i = 4; i != 8; ++i) { 5947 int idx = MaskVals[i]; 5948 if (idx < 0) { 5949 InOrder.set(i); 5950 } else if ((idx / 4) == BestHiQuad) { 5951 MaskV[i] = (idx & 3) + 4; 5952 InOrder.set(i); 5953 } 5954 } 5955 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5956 &MaskV[0]); 5957 5958 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5959 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5960 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5961 NewV.getOperand(0), 5962 getShufflePSHUFHWImmediate(SVOp), DAG); 5963 } 5964 } 5965 5966 // In case BestHi & BestLo were both -1, which means each quadword has a word 5967 // from each of the four input quadwords, calculate the InOrder bitvector now 5968 // before falling through to the insert/extract cleanup. 5969 if (BestLoQuad == -1 && BestHiQuad == -1) { 5970 NewV = V1; 5971 for (int i = 0; i != 8; ++i) 5972 if (MaskVals[i] < 0 || MaskVals[i] == i) 5973 InOrder.set(i); 5974 } 5975 5976 // The other elements are put in the right place using pextrw and pinsrw. 5977 for (unsigned i = 0; i != 8; ++i) { 5978 if (InOrder[i]) 5979 continue; 5980 int EltIdx = MaskVals[i]; 5981 if (EltIdx < 0) 5982 continue; 5983 SDValue ExtOp = (EltIdx < 8) ? 5984 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5985 DAG.getIntPtrConstant(EltIdx)) : 5986 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5987 DAG.getIntPtrConstant(EltIdx - 8)); 5988 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5989 DAG.getIntPtrConstant(i)); 5990 } 5991 return NewV; 5992} 5993 5994// v16i8 shuffles - Prefer shuffles in the following order: 5995// 1. [ssse3] 1 x pshufb 5996// 2. [ssse3] 2 x pshufb + 1 x por 5997// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5998static 5999SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 6000 SelectionDAG &DAG, 6001 const X86TargetLowering &TLI) { 6002 SDValue V1 = SVOp->getOperand(0); 6003 SDValue V2 = SVOp->getOperand(1); 6004 DebugLoc dl = SVOp->getDebugLoc(); 6005 ArrayRef<int> MaskVals = SVOp->getMask(); 6006 6007 // Promote splats to a larger type which usually leads to more efficient code. 6008 // FIXME: Is this true if pshufb is available? 6009 if (SVOp->isSplat()) 6010 return PromoteSplat(SVOp, DAG); 6011 6012 // If we have SSSE3, case 1 is generated when all result bytes come from 6013 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 6014 // present, fall back to case 3. 6015 6016 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 6017 if (TLI.getSubtarget()->hasSSSE3()) { 6018 SmallVector<SDValue,16> pshufbMask; 6019 6020 // If all result elements are from one input vector, then only translate 6021 // undef mask values to 0x80 (zero out result) in the pshufb mask. 6022 // 6023 // Otherwise, we have elements from both input vectors, and must zero out 6024 // elements that come from V2 in the first mask, and V1 in the second mask 6025 // so that we can OR them together. 6026 for (unsigned i = 0; i != 16; ++i) { 6027 int EltIdx = MaskVals[i]; 6028 if (EltIdx < 0 || EltIdx >= 16) 6029 EltIdx = 0x80; 6030 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6031 } 6032 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 6033 DAG.getNode(ISD::BUILD_VECTOR, dl, 6034 MVT::v16i8, &pshufbMask[0], 16)); 6035 6036 // As PSHUFB will zero elements with negative indices, it's safe to ignore 6037 // the 2nd operand if it's undefined or zero. 6038 if (V2.getOpcode() == ISD::UNDEF || 6039 ISD::isBuildVectorAllZeros(V2.getNode())) 6040 return V1; 6041 6042 // Calculate the shuffle mask for the second input, shuffle it, and 6043 // OR it with the first shuffled input. 6044 pshufbMask.clear(); 6045 for (unsigned i = 0; i != 16; ++i) { 6046 int EltIdx = MaskVals[i]; 6047 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16; 6048 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6049 } 6050 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 6051 DAG.getNode(ISD::BUILD_VECTOR, dl, 6052 MVT::v16i8, &pshufbMask[0], 16)); 6053 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 6054 } 6055 6056 // No SSSE3 - Calculate in place words and then fix all out of place words 6057 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 6058 // the 16 different words that comprise the two doublequadword input vectors. 6059 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 6060 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 6061 SDValue NewV = V1; 6062 for (int i = 0; i != 8; ++i) { 6063 int Elt0 = MaskVals[i*2]; 6064 int Elt1 = MaskVals[i*2+1]; 6065 6066 // This word of the result is all undef, skip it. 6067 if (Elt0 < 0 && Elt1 < 0) 6068 continue; 6069 6070 // This word of the result is already in the correct place, skip it. 6071 if ((Elt0 == i*2) && (Elt1 == i*2+1)) 6072 continue; 6073 6074 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 6075 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 6076 SDValue InsElt; 6077 6078 // If Elt0 and Elt1 are defined, are consecutive, and can be load 6079 // using a single extract together, load it and store it. 6080 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 6081 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6082 DAG.getIntPtrConstant(Elt1 / 2)); 6083 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6084 DAG.getIntPtrConstant(i)); 6085 continue; 6086 } 6087 6088 // If Elt1 is defined, extract it from the appropriate source. If the 6089 // source byte is not also odd, shift the extracted word left 8 bits 6090 // otherwise clear the bottom 8 bits if we need to do an or. 6091 if (Elt1 >= 0) { 6092 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6093 DAG.getIntPtrConstant(Elt1 / 2)); 6094 if ((Elt1 & 1) == 0) 6095 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 6096 DAG.getConstant(8, 6097 TLI.getShiftAmountTy(InsElt.getValueType()))); 6098 else if (Elt0 >= 0) 6099 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 6100 DAG.getConstant(0xFF00, MVT::i16)); 6101 } 6102 // If Elt0 is defined, extract it from the appropriate source. If the 6103 // source byte is not also even, shift the extracted word right 8 bits. If 6104 // Elt1 was also defined, OR the extracted values together before 6105 // inserting them in the result. 6106 if (Elt0 >= 0) { 6107 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 6108 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 6109 if ((Elt0 & 1) != 0) 6110 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 6111 DAG.getConstant(8, 6112 TLI.getShiftAmountTy(InsElt0.getValueType()))); 6113 else if (Elt1 >= 0) 6114 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 6115 DAG.getConstant(0x00FF, MVT::i16)); 6116 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 6117 : InsElt0; 6118 } 6119 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6120 DAG.getIntPtrConstant(i)); 6121 } 6122 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 6123} 6124 6125// v32i8 shuffles - Translate to VPSHUFB if possible. 6126static 6127SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp, 6128 const X86Subtarget *Subtarget, 6129 SelectionDAG &DAG) { 6130 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6131 SDValue V1 = SVOp->getOperand(0); 6132 SDValue V2 = SVOp->getOperand(1); 6133 DebugLoc dl = SVOp->getDebugLoc(); 6134 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end()); 6135 6136 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6137 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode()); 6138 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode()); 6139 6140 // VPSHUFB may be generated if 6141 // (1) one of input vector is undefined or zeroinitializer. 6142 // The mask value 0x80 puts 0 in the corresponding slot of the vector. 6143 // And (2) the mask indexes don't cross the 128-bit lane. 6144 if (VT != MVT::v32i8 || !Subtarget->hasInt256() || 6145 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero)) 6146 return SDValue(); 6147 6148 if (V1IsAllZero && !V2IsAllZero) { 6149 CommuteVectorShuffleMask(MaskVals, 32); 6150 V1 = V2; 6151 } 6152 SmallVector<SDValue, 32> pshufbMask; 6153 for (unsigned i = 0; i != 32; i++) { 6154 int EltIdx = MaskVals[i]; 6155 if (EltIdx < 0 || EltIdx >= 32) 6156 EltIdx = 0x80; 6157 else { 6158 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16)) 6159 // Cross lane is not allowed. 6160 return SDValue(); 6161 EltIdx &= 0xf; 6162 } 6163 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6164 } 6165 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1, 6166 DAG.getNode(ISD::BUILD_VECTOR, dl, 6167 MVT::v32i8, &pshufbMask[0], 32)); 6168} 6169 6170/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 6171/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 6172/// done when every pair / quad of shuffle mask elements point to elements in 6173/// the right sequence. e.g. 6174/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 6175static 6176SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 6177 SelectionDAG &DAG) { 6178 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6179 DebugLoc dl = SVOp->getDebugLoc(); 6180 unsigned NumElems = VT.getVectorNumElements(); 6181 MVT NewVT; 6182 unsigned Scale; 6183 switch (VT.SimpleTy) { 6184 default: llvm_unreachable("Unexpected!"); 6185 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break; 6186 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break; 6187 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break; 6188 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break; 6189 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; 6190 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; 6191 } 6192 6193 SmallVector<int, 8> MaskVec; 6194 for (unsigned i = 0; i != NumElems; i += Scale) { 6195 int StartIdx = -1; 6196 for (unsigned j = 0; j != Scale; ++j) { 6197 int EltIdx = SVOp->getMaskElt(i+j); 6198 if (EltIdx < 0) 6199 continue; 6200 if (StartIdx < 0) 6201 StartIdx = (EltIdx / Scale); 6202 if (EltIdx != (int)(StartIdx*Scale + j)) 6203 return SDValue(); 6204 } 6205 MaskVec.push_back(StartIdx); 6206 } 6207 6208 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0)); 6209 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); 6210 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 6211} 6212 6213/// getVZextMovL - Return a zero-extending vector move low node. 6214/// 6215static SDValue getVZextMovL(MVT VT, EVT OpVT, 6216 SDValue SrcOp, SelectionDAG &DAG, 6217 const X86Subtarget *Subtarget, DebugLoc dl) { 6218 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 6219 LoadSDNode *LD = NULL; 6220 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 6221 LD = dyn_cast<LoadSDNode>(SrcOp); 6222 if (!LD) { 6223 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 6224 // instead. 6225 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 6226 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 6227 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 6228 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 6229 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 6230 // PR2108 6231 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 6232 return DAG.getNode(ISD::BITCAST, dl, VT, 6233 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6234 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6235 OpVT, 6236 SrcOp.getOperand(0) 6237 .getOperand(0)))); 6238 } 6239 } 6240 } 6241 6242 return DAG.getNode(ISD::BITCAST, dl, VT, 6243 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6244 DAG.getNode(ISD::BITCAST, dl, 6245 OpVT, SrcOp))); 6246} 6247 6248/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 6249/// which could not be matched by any known target speficic shuffle 6250static SDValue 6251LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6252 6253 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG); 6254 if (NewOp.getNode()) 6255 return NewOp; 6256 6257 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6258 6259 unsigned NumElems = VT.getVectorNumElements(); 6260 unsigned NumLaneElems = NumElems / 2; 6261 6262 DebugLoc dl = SVOp->getDebugLoc(); 6263 MVT EltVT = VT.getVectorElementType(); 6264 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 6265 SDValue Output[2]; 6266 6267 SmallVector<int, 16> Mask; 6268 for (unsigned l = 0; l < 2; ++l) { 6269 // Build a shuffle mask for the output, discovering on the fly which 6270 // input vectors to use as shuffle operands (recorded in InputUsed). 6271 // If building a suitable shuffle vector proves too hard, then bail 6272 // out with UseBuildVector set. 6273 bool UseBuildVector = false; 6274 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 6275 unsigned LaneStart = l * NumLaneElems; 6276 for (unsigned i = 0; i != NumLaneElems; ++i) { 6277 // The mask element. This indexes into the input. 6278 int Idx = SVOp->getMaskElt(i+LaneStart); 6279 if (Idx < 0) { 6280 // the mask element does not index into any input vector. 6281 Mask.push_back(-1); 6282 continue; 6283 } 6284 6285 // The input vector this mask element indexes into. 6286 int Input = Idx / NumLaneElems; 6287 6288 // Turn the index into an offset from the start of the input vector. 6289 Idx -= Input * NumLaneElems; 6290 6291 // Find or create a shuffle vector operand to hold this input. 6292 unsigned OpNo; 6293 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 6294 if (InputUsed[OpNo] == Input) 6295 // This input vector is already an operand. 6296 break; 6297 if (InputUsed[OpNo] < 0) { 6298 // Create a new operand for this input vector. 6299 InputUsed[OpNo] = Input; 6300 break; 6301 } 6302 } 6303 6304 if (OpNo >= array_lengthof(InputUsed)) { 6305 // More than two input vectors used! Give up on trying to create a 6306 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 6307 UseBuildVector = true; 6308 break; 6309 } 6310 6311 // Add the mask index for the new shuffle vector. 6312 Mask.push_back(Idx + OpNo * NumLaneElems); 6313 } 6314 6315 if (UseBuildVector) { 6316 SmallVector<SDValue, 16> SVOps; 6317 for (unsigned i = 0; i != NumLaneElems; ++i) { 6318 // The mask element. This indexes into the input. 6319 int Idx = SVOp->getMaskElt(i+LaneStart); 6320 if (Idx < 0) { 6321 SVOps.push_back(DAG.getUNDEF(EltVT)); 6322 continue; 6323 } 6324 6325 // The input vector this mask element indexes into. 6326 int Input = Idx / NumElems; 6327 6328 // Turn the index into an offset from the start of the input vector. 6329 Idx -= Input * NumElems; 6330 6331 // Extract the vector element by hand. 6332 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 6333 SVOp->getOperand(Input), 6334 DAG.getIntPtrConstant(Idx))); 6335 } 6336 6337 // Construct the output using a BUILD_VECTOR. 6338 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0], 6339 SVOps.size()); 6340 } else if (InputUsed[0] < 0) { 6341 // No input vectors were used! The result is undefined. 6342 Output[l] = DAG.getUNDEF(NVT); 6343 } else { 6344 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6345 (InputUsed[0] % 2) * NumLaneElems, 6346 DAG, dl); 6347 // If only one input was used, use an undefined vector for the other. 6348 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6349 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6350 (InputUsed[1] % 2) * NumLaneElems, DAG, dl); 6351 // At least one input vector was used. Create a new shuffle vector. 6352 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6353 } 6354 6355 Mask.clear(); 6356 } 6357 6358 // Concatenate the result back 6359 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]); 6360} 6361 6362/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6363/// 4 elements, and match them with several different shuffle types. 6364static SDValue 6365LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6366 SDValue V1 = SVOp->getOperand(0); 6367 SDValue V2 = SVOp->getOperand(1); 6368 DebugLoc dl = SVOp->getDebugLoc(); 6369 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6370 6371 assert(VT.is128BitVector() && "Unsupported vector size"); 6372 6373 std::pair<int, int> Locs[4]; 6374 int Mask1[] = { -1, -1, -1, -1 }; 6375 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6376 6377 unsigned NumHi = 0; 6378 unsigned NumLo = 0; 6379 for (unsigned i = 0; i != 4; ++i) { 6380 int Idx = PermMask[i]; 6381 if (Idx < 0) { 6382 Locs[i] = std::make_pair(-1, -1); 6383 } else { 6384 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6385 if (Idx < 4) { 6386 Locs[i] = std::make_pair(0, NumLo); 6387 Mask1[NumLo] = Idx; 6388 NumLo++; 6389 } else { 6390 Locs[i] = std::make_pair(1, NumHi); 6391 if (2+NumHi < 4) 6392 Mask1[2+NumHi] = Idx; 6393 NumHi++; 6394 } 6395 } 6396 } 6397 6398 if (NumLo <= 2 && NumHi <= 2) { 6399 // If no more than two elements come from either vector. This can be 6400 // implemented with two shuffles. First shuffle gather the elements. 6401 // The second shuffle, which takes the first shuffle as both of its 6402 // vector operands, put the elements into the right order. 6403 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6404 6405 int Mask2[] = { -1, -1, -1, -1 }; 6406 6407 for (unsigned i = 0; i != 4; ++i) 6408 if (Locs[i].first != -1) { 6409 unsigned Idx = (i < 2) ? 0 : 4; 6410 Idx += Locs[i].first * 2 + Locs[i].second; 6411 Mask2[i] = Idx; 6412 } 6413 6414 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6415 } 6416 6417 if (NumLo == 3 || NumHi == 3) { 6418 // Otherwise, we must have three elements from one vector, call it X, and 6419 // one element from the other, call it Y. First, use a shufps to build an 6420 // intermediate vector with the one element from Y and the element from X 6421 // that will be in the same half in the final destination (the indexes don't 6422 // matter). Then, use a shufps to build the final vector, taking the half 6423 // containing the element from Y from the intermediate, and the other half 6424 // from X. 6425 if (NumHi == 3) { 6426 // Normalize it so the 3 elements come from V1. 6427 CommuteVectorShuffleMask(PermMask, 4); 6428 std::swap(V1, V2); 6429 } 6430 6431 // Find the element from V2. 6432 unsigned HiIndex; 6433 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6434 int Val = PermMask[HiIndex]; 6435 if (Val < 0) 6436 continue; 6437 if (Val >= 4) 6438 break; 6439 } 6440 6441 Mask1[0] = PermMask[HiIndex]; 6442 Mask1[1] = -1; 6443 Mask1[2] = PermMask[HiIndex^1]; 6444 Mask1[3] = -1; 6445 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6446 6447 if (HiIndex >= 2) { 6448 Mask1[0] = PermMask[0]; 6449 Mask1[1] = PermMask[1]; 6450 Mask1[2] = HiIndex & 1 ? 6 : 4; 6451 Mask1[3] = HiIndex & 1 ? 4 : 6; 6452 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6453 } 6454 6455 Mask1[0] = HiIndex & 1 ? 2 : 0; 6456 Mask1[1] = HiIndex & 1 ? 0 : 2; 6457 Mask1[2] = PermMask[2]; 6458 Mask1[3] = PermMask[3]; 6459 if (Mask1[2] >= 0) 6460 Mask1[2] += 4; 6461 if (Mask1[3] >= 0) 6462 Mask1[3] += 4; 6463 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6464 } 6465 6466 // Break it into (shuffle shuffle_hi, shuffle_lo). 6467 int LoMask[] = { -1, -1, -1, -1 }; 6468 int HiMask[] = { -1, -1, -1, -1 }; 6469 6470 int *MaskPtr = LoMask; 6471 unsigned MaskIdx = 0; 6472 unsigned LoIdx = 0; 6473 unsigned HiIdx = 2; 6474 for (unsigned i = 0; i != 4; ++i) { 6475 if (i == 2) { 6476 MaskPtr = HiMask; 6477 MaskIdx = 1; 6478 LoIdx = 0; 6479 HiIdx = 2; 6480 } 6481 int Idx = PermMask[i]; 6482 if (Idx < 0) { 6483 Locs[i] = std::make_pair(-1, -1); 6484 } else if (Idx < 4) { 6485 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6486 MaskPtr[LoIdx] = Idx; 6487 LoIdx++; 6488 } else { 6489 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6490 MaskPtr[HiIdx] = Idx; 6491 HiIdx++; 6492 } 6493 } 6494 6495 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6496 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6497 int MaskOps[] = { -1, -1, -1, -1 }; 6498 for (unsigned i = 0; i != 4; ++i) 6499 if (Locs[i].first != -1) 6500 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6501 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6502} 6503 6504static bool MayFoldVectorLoad(SDValue V) { 6505 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6506 V = V.getOperand(0); 6507 6508 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6509 V = V.getOperand(0); 6510 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6511 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6512 // BUILD_VECTOR (load), undef 6513 V = V.getOperand(0); 6514 6515 return MayFoldLoad(V); 6516} 6517 6518static 6519SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6520 EVT VT = Op.getValueType(); 6521 6522 // Canonizalize to v2f64. 6523 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6524 return DAG.getNode(ISD::BITCAST, dl, VT, 6525 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6526 V1, DAG)); 6527} 6528 6529static 6530SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6531 bool HasSSE2) { 6532 SDValue V1 = Op.getOperand(0); 6533 SDValue V2 = Op.getOperand(1); 6534 EVT VT = Op.getValueType(); 6535 6536 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6537 6538 if (HasSSE2 && VT == MVT::v2f64) 6539 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6540 6541 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6542 return DAG.getNode(ISD::BITCAST, dl, VT, 6543 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6544 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6545 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6546} 6547 6548static 6549SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6550 SDValue V1 = Op.getOperand(0); 6551 SDValue V2 = Op.getOperand(1); 6552 EVT VT = Op.getValueType(); 6553 6554 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6555 "unsupported shuffle type"); 6556 6557 if (V2.getOpcode() == ISD::UNDEF) 6558 V2 = V1; 6559 6560 // v4i32 or v4f32 6561 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6562} 6563 6564static 6565SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6566 SDValue V1 = Op.getOperand(0); 6567 SDValue V2 = Op.getOperand(1); 6568 EVT VT = Op.getValueType(); 6569 unsigned NumElems = VT.getVectorNumElements(); 6570 6571 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6572 // operand of these instructions is only memory, so check if there's a 6573 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6574 // same masks. 6575 bool CanFoldLoad = false; 6576 6577 // Trivial case, when V2 comes from a load. 6578 if (MayFoldVectorLoad(V2)) 6579 CanFoldLoad = true; 6580 6581 // When V1 is a load, it can be folded later into a store in isel, example: 6582 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6583 // turns into: 6584 // (MOVLPSmr addr:$src1, VR128:$src2) 6585 // So, recognize this potential and also use MOVLPS or MOVLPD 6586 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6587 CanFoldLoad = true; 6588 6589 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6590 if (CanFoldLoad) { 6591 if (HasSSE2 && NumElems == 2) 6592 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6593 6594 if (NumElems == 4) 6595 // If we don't care about the second element, proceed to use movss. 6596 if (SVOp->getMaskElt(1) != -1) 6597 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6598 } 6599 6600 // movl and movlp will both match v2i64, but v2i64 is never matched by 6601 // movl earlier because we make it strict to avoid messing with the movlp load 6602 // folding logic (see the code above getMOVLP call). Match it here then, 6603 // this is horrible, but will stay like this until we move all shuffle 6604 // matching to x86 specific nodes. Note that for the 1st condition all 6605 // types are matched with movsd. 6606 if (HasSSE2) { 6607 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6608 // as to remove this logic from here, as much as possible 6609 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6610 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6611 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6612 } 6613 6614 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6615 6616 // Invert the operand order and use SHUFPS to match it. 6617 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6618 getShuffleSHUFImmediate(SVOp), DAG); 6619} 6620 6621// Reduce a vector shuffle to zext. 6622SDValue 6623X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const { 6624 // PMOVZX is only available from SSE41. 6625 if (!Subtarget->hasSSE41()) 6626 return SDValue(); 6627 6628 EVT VT = Op.getValueType(); 6629 6630 // Only AVX2 support 256-bit vector integer extending. 6631 if (!Subtarget->hasInt256() && VT.is256BitVector()) 6632 return SDValue(); 6633 6634 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6635 DebugLoc DL = Op.getDebugLoc(); 6636 SDValue V1 = Op.getOperand(0); 6637 SDValue V2 = Op.getOperand(1); 6638 unsigned NumElems = VT.getVectorNumElements(); 6639 6640 // Extending is an unary operation and the element type of the source vector 6641 // won't be equal to or larger than i64. 6642 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() || 6643 VT.getVectorElementType() == MVT::i64) 6644 return SDValue(); 6645 6646 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4. 6647 unsigned Shift = 1; // Start from 2, i.e. 1 << 1. 6648 while ((1U << Shift) < NumElems) { 6649 if (SVOp->getMaskElt(1U << Shift) == 1) 6650 break; 6651 Shift += 1; 6652 // The maximal ratio is 8, i.e. from i8 to i64. 6653 if (Shift > 3) 6654 return SDValue(); 6655 } 6656 6657 // Check the shuffle mask. 6658 unsigned Mask = (1U << Shift) - 1; 6659 for (unsigned i = 0; i != NumElems; ++i) { 6660 int EltIdx = SVOp->getMaskElt(i); 6661 if ((i & Mask) != 0 && EltIdx != -1) 6662 return SDValue(); 6663 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift)) 6664 return SDValue(); 6665 } 6666 6667 LLVMContext *Context = DAG.getContext(); 6668 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift; 6669 EVT NeVT = EVT::getIntegerVT(*Context, NBits); 6670 EVT NVT = EVT::getVectorVT(*Context, NeVT, NumElems >> Shift); 6671 6672 if (!isTypeLegal(NVT)) 6673 return SDValue(); 6674 6675 // Simplify the operand as it's prepared to be fed into shuffle. 6676 unsigned SignificantBits = NVT.getSizeInBits() >> Shift; 6677 if (V1.getOpcode() == ISD::BITCAST && 6678 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 6679 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && 6680 V1.getOperand(0) 6681 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) { 6682 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x) 6683 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0); 6684 ConstantSDNode *CIdx = 6685 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1)); 6686 // If it's foldable, i.e. normal load with single use, we will let code 6687 // selection to fold it. Otherwise, we will short the conversion sequence. 6688 if (CIdx && CIdx->getZExtValue() == 0 && 6689 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) { 6690 if (V.getValueSizeInBits() > V1.getValueSizeInBits()) { 6691 // The "ext_vec_elt" node is wider than the result node. 6692 // In this case we should extract subvector from V. 6693 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)). 6694 unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits(); 6695 EVT FullVT = V.getValueType(); 6696 EVT SubVecVT = EVT::getVectorVT(*Context, 6697 FullVT.getVectorElementType(), 6698 FullVT.getVectorNumElements()/Ratio); 6699 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V, 6700 DAG.getIntPtrConstant(0)); 6701 } 6702 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V); 6703 } 6704 } 6705 6706 return DAG.getNode(ISD::BITCAST, DL, VT, 6707 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1)); 6708} 6709 6710SDValue 6711X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6713 MVT VT = Op.getValueType().getSimpleVT(); 6714 DebugLoc dl = Op.getDebugLoc(); 6715 SDValue V1 = Op.getOperand(0); 6716 SDValue V2 = Op.getOperand(1); 6717 6718 if (isZeroShuffle(SVOp)) 6719 return getZeroVector(VT, Subtarget, DAG, dl); 6720 6721 // Handle splat operations 6722 if (SVOp->isSplat()) { 6723 // Use vbroadcast whenever the splat comes from a foldable load 6724 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6725 if (Broadcast.getNode()) 6726 return Broadcast; 6727 } 6728 6729 // Check integer expanding shuffles. 6730 SDValue NewOp = LowerVectorIntExtend(Op, DAG); 6731 if (NewOp.getNode()) 6732 return NewOp; 6733 6734 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6735 // do it! 6736 if (VT == MVT::v8i16 || VT == MVT::v16i8 || 6737 VT == MVT::v16i16 || VT == MVT::v32i8) { 6738 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 6739 if (NewOp.getNode()) 6740 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6741 } else if ((VT == MVT::v4i32 || 6742 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6743 // FIXME: Figure out a cleaner way to do this. 6744 // Try to make use of movq to zero out the top part. 6745 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6746 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 6747 if (NewOp.getNode()) { 6748 MVT NewVT = NewOp.getValueType().getSimpleVT(); 6749 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6750 NewVT, true, false)) 6751 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6752 DAG, Subtarget, dl); 6753 } 6754 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6755 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 6756 if (NewOp.getNode()) { 6757 MVT NewVT = NewOp.getValueType().getSimpleVT(); 6758 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6759 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6760 DAG, Subtarget, dl); 6761 } 6762 } 6763 } 6764 return SDValue(); 6765} 6766 6767SDValue 6768X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6769 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6770 SDValue V1 = Op.getOperand(0); 6771 SDValue V2 = Op.getOperand(1); 6772 MVT VT = Op.getValueType().getSimpleVT(); 6773 DebugLoc dl = Op.getDebugLoc(); 6774 unsigned NumElems = VT.getVectorNumElements(); 6775 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6776 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6777 bool V1IsSplat = false; 6778 bool V2IsSplat = false; 6779 bool HasSSE2 = Subtarget->hasSSE2(); 6780 bool HasFp256 = Subtarget->hasFp256(); 6781 bool HasInt256 = Subtarget->hasInt256(); 6782 MachineFunction &MF = DAG.getMachineFunction(); 6783 bool OptForSize = MF.getFunction()->getAttributes(). 6784 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize); 6785 6786 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6787 6788 if (V1IsUndef && V2IsUndef) 6789 return DAG.getUNDEF(VT); 6790 6791 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6792 6793 // Vector shuffle lowering takes 3 steps: 6794 // 6795 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6796 // narrowing and commutation of operands should be handled. 6797 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6798 // shuffle nodes. 6799 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6800 // so the shuffle can be broken into other shuffles and the legalizer can 6801 // try the lowering again. 6802 // 6803 // The general idea is that no vector_shuffle operation should be left to 6804 // be matched during isel, all of them must be converted to a target specific 6805 // node here. 6806 6807 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6808 // narrowing and commutation of operands should be handled. The actual code 6809 // doesn't include all of those, work in progress... 6810 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6811 if (NewOp.getNode()) 6812 return NewOp; 6813 6814 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6815 6816 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6817 // unpckh_undef). Only use pshufd if speed is more important than size. 6818 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256)) 6819 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6820 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256)) 6821 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6822 6823 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6824 V2IsUndef && MayFoldVectorLoad(V1)) 6825 return getMOVDDup(Op, dl, V1, DAG); 6826 6827 if (isMOVHLPS_v_undef_Mask(M, VT)) 6828 return getMOVHighToLow(Op, dl, DAG); 6829 6830 // Use to match splats 6831 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef && 6832 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6833 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6834 6835 if (isPSHUFDMask(M, VT)) { 6836 // The actual implementation will match the mask in the if above and then 6837 // during isel it can match several different instructions, not only pshufd 6838 // as its name says, sad but true, emulate the behavior for now... 6839 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6840 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6841 6842 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6843 6844 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6845 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6846 6847 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6848 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, 6849 DAG); 6850 6851 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6852 TargetMask, DAG); 6853 } 6854 6855 // Check if this can be converted into a logical shift. 6856 bool isLeft = false; 6857 unsigned ShAmt = 0; 6858 SDValue ShVal; 6859 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6860 if (isShift && ShVal.hasOneUse()) { 6861 // If the shifted value has multiple uses, it may be cheaper to use 6862 // v_set0 + movlhps or movhlps, etc. 6863 MVT EltVT = VT.getVectorElementType(); 6864 ShAmt *= EltVT.getSizeInBits(); 6865 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6866 } 6867 6868 if (isMOVLMask(M, VT)) { 6869 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6870 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6871 if (!isMOVLPMask(M, VT)) { 6872 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6873 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6874 6875 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6876 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6877 } 6878 } 6879 6880 // FIXME: fold these into legal mask. 6881 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256)) 6882 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6883 6884 if (isMOVHLPSMask(M, VT)) 6885 return getMOVHighToLow(Op, dl, DAG); 6886 6887 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6888 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6889 6890 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6891 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6892 6893 if (isMOVLPMask(M, VT)) 6894 return getMOVLP(Op, dl, DAG, HasSSE2); 6895 6896 if (ShouldXformToMOVHLPS(M, VT) || 6897 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6898 return CommuteVectorShuffle(SVOp, DAG); 6899 6900 if (isShift) { 6901 // No better options. Use a vshldq / vsrldq. 6902 MVT EltVT = VT.getVectorElementType(); 6903 ShAmt *= EltVT.getSizeInBits(); 6904 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6905 } 6906 6907 bool Commuted = false; 6908 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6909 // 1,1,1,1 -> v8i16 though. 6910 V1IsSplat = isSplatVector(V1.getNode()); 6911 V2IsSplat = isSplatVector(V2.getNode()); 6912 6913 // Canonicalize the splat or undef, if present, to be on the RHS. 6914 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6915 CommuteVectorShuffleMask(M, NumElems); 6916 std::swap(V1, V2); 6917 std::swap(V1IsSplat, V2IsSplat); 6918 Commuted = true; 6919 } 6920 6921 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6922 // Shuffling low element of v1 into undef, just return v1. 6923 if (V2IsUndef) 6924 return V1; 6925 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6926 // the instruction selector will not match, so get a canonical MOVL with 6927 // swapped operands to undo the commute. 6928 return getMOVL(DAG, dl, VT, V2, V1); 6929 } 6930 6931 if (isUNPCKLMask(M, VT, HasInt256)) 6932 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6933 6934 if (isUNPCKHMask(M, VT, HasInt256)) 6935 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6936 6937 if (V2IsSplat) { 6938 // Normalize mask so all entries that point to V2 points to its first 6939 // element then try to match unpck{h|l} again. If match, return a 6940 // new vector_shuffle with the corrected mask.p 6941 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6942 NormalizeMask(NewMask, NumElems); 6943 if (isUNPCKLMask(NewMask, VT, HasInt256, true)) 6944 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6945 if (isUNPCKHMask(NewMask, VT, HasInt256, true)) 6946 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6947 } 6948 6949 if (Commuted) { 6950 // Commute is back and try unpck* again. 6951 // FIXME: this seems wrong. 6952 CommuteVectorShuffleMask(M, NumElems); 6953 std::swap(V1, V2); 6954 std::swap(V1IsSplat, V2IsSplat); 6955 Commuted = false; 6956 6957 if (isUNPCKLMask(M, VT, HasInt256)) 6958 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6959 6960 if (isUNPCKHMask(M, VT, HasInt256)) 6961 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6962 } 6963 6964 // Normalize the node to match x86 shuffle ops if needed 6965 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true))) 6966 return CommuteVectorShuffle(SVOp, DAG); 6967 6968 // The checks below are all present in isShuffleMaskLegal, but they are 6969 // inlined here right now to enable us to directly emit target specific 6970 // nodes, and remove one by one until they don't return Op anymore. 6971 6972 if (isPALIGNRMask(M, VT, Subtarget)) 6973 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2, 6974 getShufflePALIGNRImmediate(SVOp), 6975 DAG); 6976 6977 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6978 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6979 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6980 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6981 } 6982 6983 if (isPSHUFHWMask(M, VT, HasInt256)) 6984 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6985 getShufflePSHUFHWImmediate(SVOp), 6986 DAG); 6987 6988 if (isPSHUFLWMask(M, VT, HasInt256)) 6989 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6990 getShufflePSHUFLWImmediate(SVOp), 6991 DAG); 6992 6993 if (isSHUFPMask(M, VT, HasFp256)) 6994 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6995 getShuffleSHUFImmediate(SVOp), DAG); 6996 6997 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256)) 6998 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6999 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256)) 7000 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 7001 7002 //===--------------------------------------------------------------------===// 7003 // Generate target specific nodes for 128 or 256-bit shuffles only 7004 // supported in the AVX instruction set. 7005 // 7006 7007 // Handle VMOVDDUPY permutations 7008 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256)) 7009 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 7010 7011 // Handle VPERMILPS/D* permutations 7012 if (isVPERMILPMask(M, VT, HasFp256)) { 7013 if (HasInt256 && VT == MVT::v8i32) 7014 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 7015 getShuffleSHUFImmediate(SVOp), DAG); 7016 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 7017 getShuffleSHUFImmediate(SVOp), DAG); 7018 } 7019 7020 // Handle VPERM2F128/VPERM2I128 permutations 7021 if (isVPERM2X128Mask(M, VT, HasFp256)) 7022 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 7023 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 7024 7025 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG); 7026 if (BlendOp.getNode()) 7027 return BlendOp; 7028 7029 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { 7030 SmallVector<SDValue, 8> permclMask; 7031 for (unsigned i = 0; i != 8; ++i) { 7032 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); 7033 } 7034 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, 7035 &permclMask[0], 8); 7036 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 7037 return DAG.getNode(X86ISD::VPERMV, dl, VT, 7038 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 7039 } 7040 7041 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64)) 7042 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, 7043 getShuffleCLImmediate(SVOp), DAG); 7044 7045 //===--------------------------------------------------------------------===// 7046 // Since no target specific shuffle was selected for this generic one, 7047 // lower it into other known shuffles. FIXME: this isn't true yet, but 7048 // this is the plan. 7049 // 7050 7051 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 7052 if (VT == MVT::v8i16) { 7053 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG); 7054 if (NewOp.getNode()) 7055 return NewOp; 7056 } 7057 7058 if (VT == MVT::v16i8) { 7059 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 7060 if (NewOp.getNode()) 7061 return NewOp; 7062 } 7063 7064 if (VT == MVT::v32i8) { 7065 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG); 7066 if (NewOp.getNode()) 7067 return NewOp; 7068 } 7069 7070 // Handle all 128-bit wide vectors with 4 elements, and match them with 7071 // several different shuffle types. 7072 if (NumElems == 4 && VT.is128BitVector()) 7073 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 7074 7075 // Handle general 256-bit shuffles 7076 if (VT.is256BitVector()) 7077 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 7078 7079 return SDValue(); 7080} 7081 7082static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { 7083 MVT VT = Op.getValueType().getSimpleVT(); 7084 DebugLoc dl = Op.getDebugLoc(); 7085 7086 if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector()) 7087 return SDValue(); 7088 7089 if (VT.getSizeInBits() == 8) { 7090 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 7091 Op.getOperand(0), Op.getOperand(1)); 7092 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 7093 DAG.getValueType(VT)); 7094 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7095 } 7096 7097 if (VT.getSizeInBits() == 16) { 7098 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7099 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 7100 if (Idx == 0) 7101 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7102 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7103 DAG.getNode(ISD::BITCAST, dl, 7104 MVT::v4i32, 7105 Op.getOperand(0)), 7106 Op.getOperand(1))); 7107 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 7108 Op.getOperand(0), Op.getOperand(1)); 7109 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 7110 DAG.getValueType(VT)); 7111 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7112 } 7113 7114 if (VT == MVT::f32) { 7115 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 7116 // the result back to FR32 register. It's only worth matching if the 7117 // result has a single use which is a store or a bitcast to i32. And in 7118 // the case of a store, it's not worth it if the index is a constant 0, 7119 // because a MOVSSmr can be used instead, which is smaller and faster. 7120 if (!Op.hasOneUse()) 7121 return SDValue(); 7122 SDNode *User = *Op.getNode()->use_begin(); 7123 if ((User->getOpcode() != ISD::STORE || 7124 (isa<ConstantSDNode>(Op.getOperand(1)) && 7125 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 7126 (User->getOpcode() != ISD::BITCAST || 7127 User->getValueType(0) != MVT::i32)) 7128 return SDValue(); 7129 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7130 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 7131 Op.getOperand(0)), 7132 Op.getOperand(1)); 7133 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 7134 } 7135 7136 if (VT == MVT::i32 || VT == MVT::i64) { 7137 // ExtractPS/pextrq works with constant index. 7138 if (isa<ConstantSDNode>(Op.getOperand(1))) 7139 return Op; 7140 } 7141 return SDValue(); 7142} 7143 7144SDValue 7145X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 7146 SelectionDAG &DAG) const { 7147 if (!isa<ConstantSDNode>(Op.getOperand(1))) 7148 return SDValue(); 7149 7150 SDValue Vec = Op.getOperand(0); 7151 MVT VecVT = Vec.getValueType().getSimpleVT(); 7152 7153 // If this is a 256-bit vector result, first extract the 128-bit vector and 7154 // then extract the element from the 128-bit vector. 7155 if (VecVT.is256BitVector()) { 7156 DebugLoc dl = Op.getNode()->getDebugLoc(); 7157 unsigned NumElems = VecVT.getVectorNumElements(); 7158 SDValue Idx = Op.getOperand(1); 7159 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7160 7161 // Get the 128-bit vector. 7162 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl); 7163 7164 if (IdxVal >= NumElems/2) 7165 IdxVal -= NumElems/2; 7166 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 7167 DAG.getConstant(IdxVal, MVT::i32)); 7168 } 7169 7170 assert(VecVT.is128BitVector() && "Unexpected vector length"); 7171 7172 if (Subtarget->hasSSE41()) { 7173 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 7174 if (Res.getNode()) 7175 return Res; 7176 } 7177 7178 MVT VT = Op.getValueType().getSimpleVT(); 7179 DebugLoc dl = Op.getDebugLoc(); 7180 // TODO: handle v16i8. 7181 if (VT.getSizeInBits() == 16) { 7182 SDValue Vec = Op.getOperand(0); 7183 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7184 if (Idx == 0) 7185 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7186 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7187 DAG.getNode(ISD::BITCAST, dl, 7188 MVT::v4i32, Vec), 7189 Op.getOperand(1))); 7190 // Transform it so it match pextrw which produces a 32-bit result. 7191 MVT EltVT = MVT::i32; 7192 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 7193 Op.getOperand(0), Op.getOperand(1)); 7194 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 7195 DAG.getValueType(VT)); 7196 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7197 } 7198 7199 if (VT.getSizeInBits() == 32) { 7200 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7201 if (Idx == 0) 7202 return Op; 7203 7204 // SHUFPS the element to the lowest double word, then movss. 7205 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 7206 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT(); 7207 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7208 DAG.getUNDEF(VVT), Mask); 7209 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7210 DAG.getIntPtrConstant(0)); 7211 } 7212 7213 if (VT.getSizeInBits() == 64) { 7214 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 7215 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 7216 // to match extract_elt for f64. 7217 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7218 if (Idx == 0) 7219 return Op; 7220 7221 // UNPCKHPD the element to the lowest double word, then movsd. 7222 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 7223 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 7224 int Mask[2] = { 1, -1 }; 7225 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT(); 7226 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7227 DAG.getUNDEF(VVT), Mask); 7228 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7229 DAG.getIntPtrConstant(0)); 7230 } 7231 7232 return SDValue(); 7233} 7234 7235static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { 7236 MVT VT = Op.getValueType().getSimpleVT(); 7237 MVT EltVT = VT.getVectorElementType(); 7238 DebugLoc dl = Op.getDebugLoc(); 7239 7240 SDValue N0 = Op.getOperand(0); 7241 SDValue N1 = Op.getOperand(1); 7242 SDValue N2 = Op.getOperand(2); 7243 7244 if (!VT.is128BitVector()) 7245 return SDValue(); 7246 7247 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 7248 isa<ConstantSDNode>(N2)) { 7249 unsigned Opc; 7250 if (VT == MVT::v8i16) 7251 Opc = X86ISD::PINSRW; 7252 else if (VT == MVT::v16i8) 7253 Opc = X86ISD::PINSRB; 7254 else 7255 Opc = X86ISD::PINSRB; 7256 7257 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 7258 // argument. 7259 if (N1.getValueType() != MVT::i32) 7260 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7261 if (N2.getValueType() != MVT::i32) 7262 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7263 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7264 } 7265 7266 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7267 // Bits [7:6] of the constant are the source select. This will always be 7268 // zero here. The DAG Combiner may combine an extract_elt index into these 7269 // bits. For example (insert (extract, 3), 2) could be matched by putting 7270 // the '3' into bits [7:6] of X86ISD::INSERTPS. 7271 // Bits [5:4] of the constant are the destination select. This is the 7272 // value of the incoming immediate. 7273 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 7274 // combine either bitwise AND or insert of float 0.0 to set these bits. 7275 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7276 // Create this as a scalar to vector.. 7277 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 7278 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7279 } 7280 7281 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) { 7282 // PINSR* works with constant index. 7283 return Op; 7284 } 7285 return SDValue(); 7286} 7287 7288SDValue 7289X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7290 MVT VT = Op.getValueType().getSimpleVT(); 7291 MVT EltVT = VT.getVectorElementType(); 7292 7293 DebugLoc dl = Op.getDebugLoc(); 7294 SDValue N0 = Op.getOperand(0); 7295 SDValue N1 = Op.getOperand(1); 7296 SDValue N2 = Op.getOperand(2); 7297 7298 // If this is a 256-bit vector result, first extract the 128-bit vector, 7299 // insert the element into the extracted half and then place it back. 7300 if (VT.is256BitVector()) { 7301 if (!isa<ConstantSDNode>(N2)) 7302 return SDValue(); 7303 7304 // Get the desired 128-bit vector half. 7305 unsigned NumElems = VT.getVectorNumElements(); 7306 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7307 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl); 7308 7309 // Insert the element into the desired half. 7310 bool Upper = IdxVal >= NumElems/2; 7311 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1, 7312 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32)); 7313 7314 // Insert the changed part back to the 256-bit vector 7315 return Insert128BitVector(N0, V, IdxVal, DAG, dl); 7316 } 7317 7318 if (Subtarget->hasSSE41()) 7319 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7320 7321 if (EltVT == MVT::i8) 7322 return SDValue(); 7323 7324 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7325 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7326 // as its second argument. 7327 if (N1.getValueType() != MVT::i32) 7328 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7329 if (N2.getValueType() != MVT::i32) 7330 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7331 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7332 } 7333 return SDValue(); 7334} 7335 7336static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 7337 LLVMContext *Context = DAG.getContext(); 7338 DebugLoc dl = Op.getDebugLoc(); 7339 MVT OpVT = Op.getValueType().getSimpleVT(); 7340 7341 // If this is a 256-bit vector result, first insert into a 128-bit 7342 // vector and then insert into the 256-bit vector. 7343 if (!OpVT.is128BitVector()) { 7344 // Insert into a 128-bit vector. 7345 EVT VT128 = EVT::getVectorVT(*Context, 7346 OpVT.getVectorElementType(), 7347 OpVT.getVectorNumElements() / 2); 7348 7349 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7350 7351 // Insert the 128-bit vector. 7352 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); 7353 } 7354 7355 if (OpVT == MVT::v1i64 && 7356 Op.getOperand(0).getValueType() == MVT::i64) 7357 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7358 7359 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7360 assert(OpVT.is128BitVector() && "Expected an SSE type!"); 7361 return DAG.getNode(ISD::BITCAST, dl, OpVT, 7362 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7363} 7364 7365// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7366// a simple subregister reference or explicit instructions to grab 7367// upper bits of a vector. 7368static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, 7369 SelectionDAG &DAG) { 7370 if (Subtarget->hasFp256()) { 7371 DebugLoc dl = Op.getNode()->getDebugLoc(); 7372 SDValue Vec = Op.getNode()->getOperand(0); 7373 SDValue Idx = Op.getNode()->getOperand(1); 7374 7375 if (Op.getNode()->getValueType(0).is128BitVector() && 7376 Vec.getNode()->getValueType(0).is256BitVector() && 7377 isa<ConstantSDNode>(Idx)) { 7378 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7379 return Extract128BitVector(Vec, IdxVal, DAG, dl); 7380 } 7381 } 7382 return SDValue(); 7383} 7384 7385// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7386// simple superregister reference or explicit instructions to insert 7387// the upper bits of a vector. 7388static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, 7389 SelectionDAG &DAG) { 7390 if (Subtarget->hasFp256()) { 7391 DebugLoc dl = Op.getNode()->getDebugLoc(); 7392 SDValue Vec = Op.getNode()->getOperand(0); 7393 SDValue SubVec = Op.getNode()->getOperand(1); 7394 SDValue Idx = Op.getNode()->getOperand(2); 7395 7396 if (Op.getNode()->getValueType(0).is256BitVector() && 7397 SubVec.getNode()->getValueType(0).is128BitVector() && 7398 isa<ConstantSDNode>(Idx)) { 7399 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7400 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); 7401 } 7402 } 7403 return SDValue(); 7404} 7405 7406// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7407// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7408// one of the above mentioned nodes. It has to be wrapped because otherwise 7409// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7410// be used to form addressing mode. These wrapped nodes will be selected 7411// into MOV32ri. 7412SDValue 7413X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7414 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7415 7416 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7417 // global base reg. 7418 unsigned char OpFlag = 0; 7419 unsigned WrapperKind = X86ISD::Wrapper; 7420 CodeModel::Model M = getTargetMachine().getCodeModel(); 7421 7422 if (Subtarget->isPICStyleRIPRel() && 7423 (M == CodeModel::Small || M == CodeModel::Kernel)) 7424 WrapperKind = X86ISD::WrapperRIP; 7425 else if (Subtarget->isPICStyleGOT()) 7426 OpFlag = X86II::MO_GOTOFF; 7427 else if (Subtarget->isPICStyleStubPIC()) 7428 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7429 7430 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7431 CP->getAlignment(), 7432 CP->getOffset(), OpFlag); 7433 DebugLoc DL = CP->getDebugLoc(); 7434 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7435 // With PIC, the address is actually $g + Offset. 7436 if (OpFlag) { 7437 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7438 DAG.getNode(X86ISD::GlobalBaseReg, 7439 DebugLoc(), getPointerTy()), 7440 Result); 7441 } 7442 7443 return Result; 7444} 7445 7446SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7447 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7448 7449 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7450 // global base reg. 7451 unsigned char OpFlag = 0; 7452 unsigned WrapperKind = X86ISD::Wrapper; 7453 CodeModel::Model M = getTargetMachine().getCodeModel(); 7454 7455 if (Subtarget->isPICStyleRIPRel() && 7456 (M == CodeModel::Small || M == CodeModel::Kernel)) 7457 WrapperKind = X86ISD::WrapperRIP; 7458 else if (Subtarget->isPICStyleGOT()) 7459 OpFlag = X86II::MO_GOTOFF; 7460 else if (Subtarget->isPICStyleStubPIC()) 7461 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7462 7463 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7464 OpFlag); 7465 DebugLoc DL = JT->getDebugLoc(); 7466 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7467 7468 // With PIC, the address is actually $g + Offset. 7469 if (OpFlag) 7470 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7471 DAG.getNode(X86ISD::GlobalBaseReg, 7472 DebugLoc(), getPointerTy()), 7473 Result); 7474 7475 return Result; 7476} 7477 7478SDValue 7479X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7480 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7481 7482 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7483 // global base reg. 7484 unsigned char OpFlag = 0; 7485 unsigned WrapperKind = X86ISD::Wrapper; 7486 CodeModel::Model M = getTargetMachine().getCodeModel(); 7487 7488 if (Subtarget->isPICStyleRIPRel() && 7489 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7490 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7491 OpFlag = X86II::MO_GOTPCREL; 7492 WrapperKind = X86ISD::WrapperRIP; 7493 } else if (Subtarget->isPICStyleGOT()) { 7494 OpFlag = X86II::MO_GOT; 7495 } else if (Subtarget->isPICStyleStubPIC()) { 7496 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7497 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7498 OpFlag = X86II::MO_DARWIN_NONLAZY; 7499 } 7500 7501 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7502 7503 DebugLoc DL = Op.getDebugLoc(); 7504 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7505 7506 // With PIC, the address is actually $g + Offset. 7507 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7508 !Subtarget->is64Bit()) { 7509 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7510 DAG.getNode(X86ISD::GlobalBaseReg, 7511 DebugLoc(), getPointerTy()), 7512 Result); 7513 } 7514 7515 // For symbols that require a load from a stub to get the address, emit the 7516 // load. 7517 if (isGlobalStubReference(OpFlag)) 7518 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7519 MachinePointerInfo::getGOT(), false, false, false, 0); 7520 7521 return Result; 7522} 7523 7524SDValue 7525X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7526 // Create the TargetBlockAddressAddress node. 7527 unsigned char OpFlags = 7528 Subtarget->ClassifyBlockAddressReference(); 7529 CodeModel::Model M = getTargetMachine().getCodeModel(); 7530 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7531 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset(); 7532 DebugLoc dl = Op.getDebugLoc(); 7533 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset, 7534 OpFlags); 7535 7536 if (Subtarget->isPICStyleRIPRel() && 7537 (M == CodeModel::Small || M == CodeModel::Kernel)) 7538 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7539 else 7540 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7541 7542 // With PIC, the address is actually $g + Offset. 7543 if (isGlobalRelativeToPICBase(OpFlags)) { 7544 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7545 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7546 Result); 7547 } 7548 7549 return Result; 7550} 7551 7552SDValue 7553X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7554 int64_t Offset, SelectionDAG &DAG) const { 7555 // Create the TargetGlobalAddress node, folding in the constant 7556 // offset if it is legal. 7557 unsigned char OpFlags = 7558 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7559 CodeModel::Model M = getTargetMachine().getCodeModel(); 7560 SDValue Result; 7561 if (OpFlags == X86II::MO_NO_FLAG && 7562 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7563 // A direct static reference to a global. 7564 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7565 Offset = 0; 7566 } else { 7567 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7568 } 7569 7570 if (Subtarget->isPICStyleRIPRel() && 7571 (M == CodeModel::Small || M == CodeModel::Kernel)) 7572 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7573 else 7574 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7575 7576 // With PIC, the address is actually $g + Offset. 7577 if (isGlobalRelativeToPICBase(OpFlags)) { 7578 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7579 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7580 Result); 7581 } 7582 7583 // For globals that require a load from a stub to get the address, emit the 7584 // load. 7585 if (isGlobalStubReference(OpFlags)) 7586 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7587 MachinePointerInfo::getGOT(), false, false, false, 0); 7588 7589 // If there was a non-zero offset that we didn't fold, create an explicit 7590 // addition for it. 7591 if (Offset != 0) 7592 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7593 DAG.getConstant(Offset, getPointerTy())); 7594 7595 return Result; 7596} 7597 7598SDValue 7599X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7600 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7601 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7602 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7603} 7604 7605static SDValue 7606GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7607 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7608 unsigned char OperandFlags, bool LocalDynamic = false) { 7609 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7610 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7611 DebugLoc dl = GA->getDebugLoc(); 7612 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7613 GA->getValueType(0), 7614 GA->getOffset(), 7615 OperandFlags); 7616 7617 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR 7618 : X86ISD::TLSADDR; 7619 7620 if (InFlag) { 7621 SDValue Ops[] = { Chain, TGA, *InFlag }; 7622 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3); 7623 } else { 7624 SDValue Ops[] = { Chain, TGA }; 7625 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2); 7626 } 7627 7628 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7629 MFI->setAdjustsStack(true); 7630 7631 SDValue Flag = Chain.getValue(1); 7632 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7633} 7634 7635// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7636static SDValue 7637LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7638 const EVT PtrVT) { 7639 SDValue InFlag; 7640 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7641 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7642 DAG.getNode(X86ISD::GlobalBaseReg, 7643 DebugLoc(), PtrVT), InFlag); 7644 InFlag = Chain.getValue(1); 7645 7646 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7647} 7648 7649// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7650static SDValue 7651LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7652 const EVT PtrVT) { 7653 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7654 X86::RAX, X86II::MO_TLSGD); 7655} 7656 7657static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA, 7658 SelectionDAG &DAG, 7659 const EVT PtrVT, 7660 bool is64Bit) { 7661 DebugLoc dl = GA->getDebugLoc(); 7662 7663 // Get the start address of the TLS block for this module. 7664 X86MachineFunctionInfo* MFI = DAG.getMachineFunction() 7665 .getInfo<X86MachineFunctionInfo>(); 7666 MFI->incNumLocalDynamicTLSAccesses(); 7667 7668 SDValue Base; 7669 if (is64Bit) { 7670 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX, 7671 X86II::MO_TLSLD, /*LocalDynamic=*/true); 7672 } else { 7673 SDValue InFlag; 7674 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7675 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag); 7676 InFlag = Chain.getValue(1); 7677 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, 7678 X86II::MO_TLSLDM, /*LocalDynamic=*/true); 7679 } 7680 7681 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations 7682 // of Base. 7683 7684 // Build x@dtpoff. 7685 unsigned char OperandFlags = X86II::MO_DTPOFF; 7686 unsigned WrapperKind = X86ISD::Wrapper; 7687 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7688 GA->getValueType(0), 7689 GA->getOffset(), OperandFlags); 7690 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7691 7692 // Add x@dtpoff with the base. 7693 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base); 7694} 7695 7696// Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model. 7697static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7698 const EVT PtrVT, TLSModel::Model model, 7699 bool is64Bit, bool isPIC) { 7700 DebugLoc dl = GA->getDebugLoc(); 7701 7702 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7703 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7704 is64Bit ? 257 : 256)); 7705 7706 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7707 DAG.getIntPtrConstant(0), 7708 MachinePointerInfo(Ptr), 7709 false, false, false, 0); 7710 7711 unsigned char OperandFlags = 0; 7712 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7713 // initialexec. 7714 unsigned WrapperKind = X86ISD::Wrapper; 7715 if (model == TLSModel::LocalExec) { 7716 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7717 } else if (model == TLSModel::InitialExec) { 7718 if (is64Bit) { 7719 OperandFlags = X86II::MO_GOTTPOFF; 7720 WrapperKind = X86ISD::WrapperRIP; 7721 } else { 7722 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF; 7723 } 7724 } else { 7725 llvm_unreachable("Unexpected model"); 7726 } 7727 7728 // emit "addl x@ntpoff,%eax" (local exec) 7729 // or "addl x@indntpoff,%eax" (initial exec) 7730 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic) 7731 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7732 GA->getValueType(0), 7733 GA->getOffset(), OperandFlags); 7734 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7735 7736 if (model == TLSModel::InitialExec) { 7737 if (isPIC && !is64Bit) { 7738 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, 7739 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), 7740 Offset); 7741 } 7742 7743 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7744 MachinePointerInfo::getGOT(), false, false, false, 7745 0); 7746 } 7747 7748 // The address of the thread local variable is the add of the thread 7749 // pointer with the offset of the variable. 7750 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7751} 7752 7753SDValue 7754X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7755 7756 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7757 const GlobalValue *GV = GA->getGlobal(); 7758 7759 if (Subtarget->isTargetELF()) { 7760 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7761 7762 switch (model) { 7763 case TLSModel::GeneralDynamic: 7764 if (Subtarget->is64Bit()) 7765 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7766 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7767 case TLSModel::LocalDynamic: 7768 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(), 7769 Subtarget->is64Bit()); 7770 case TLSModel::InitialExec: 7771 case TLSModel::LocalExec: 7772 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7773 Subtarget->is64Bit(), 7774 getTargetMachine().getRelocationModel() == Reloc::PIC_); 7775 } 7776 llvm_unreachable("Unknown TLS model."); 7777 } 7778 7779 if (Subtarget->isTargetDarwin()) { 7780 // Darwin only has one model of TLS. Lower to that. 7781 unsigned char OpFlag = 0; 7782 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7783 X86ISD::WrapperRIP : X86ISD::Wrapper; 7784 7785 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7786 // global base reg. 7787 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7788 !Subtarget->is64Bit(); 7789 if (PIC32) 7790 OpFlag = X86II::MO_TLVP_PIC_BASE; 7791 else 7792 OpFlag = X86II::MO_TLVP; 7793 DebugLoc DL = Op.getDebugLoc(); 7794 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7795 GA->getValueType(0), 7796 GA->getOffset(), OpFlag); 7797 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7798 7799 // With PIC32, the address is actually $g + Offset. 7800 if (PIC32) 7801 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7802 DAG.getNode(X86ISD::GlobalBaseReg, 7803 DebugLoc(), getPointerTy()), 7804 Offset); 7805 7806 // Lowering the machine isd will make sure everything is in the right 7807 // location. 7808 SDValue Chain = DAG.getEntryNode(); 7809 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7810 SDValue Args[] = { Chain, Offset }; 7811 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7812 7813 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7814 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7815 MFI->setAdjustsStack(true); 7816 7817 // And our return value (tls address) is in the standard call return value 7818 // location. 7819 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7820 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7821 Chain.getValue(1)); 7822 } 7823 7824 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) { 7825 // Just use the implicit TLS architecture 7826 // Need to generate someting similar to: 7827 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7828 // ; from TEB 7829 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7830 // mov rcx, qword [rdx+rcx*8] 7831 // mov eax, .tls$:tlsvar 7832 // [rax+rcx] contains the address 7833 // Windows 64bit: gs:0x58 7834 // Windows 32bit: fs:__tls_array 7835 7836 // If GV is an alias then use the aliasee for determining 7837 // thread-localness. 7838 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7839 GV = GA->resolveAliasedGlobal(false); 7840 DebugLoc dl = GA->getDebugLoc(); 7841 SDValue Chain = DAG.getEntryNode(); 7842 7843 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7844 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly 7845 // use its literal value of 0x2C. 7846 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7847 ? Type::getInt8PtrTy(*DAG.getContext(), 7848 256) 7849 : Type::getInt32PtrTy(*DAG.getContext(), 7850 257)); 7851 7852 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) : 7853 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) : 7854 DAG.getExternalSymbol("_tls_array", getPointerTy())); 7855 7856 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray, 7857 MachinePointerInfo(Ptr), 7858 false, false, false, 0); 7859 7860 // Load the _tls_index variable 7861 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7862 if (Subtarget->is64Bit()) 7863 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7864 IDX, MachinePointerInfo(), MVT::i32, 7865 false, false, 0); 7866 else 7867 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7868 false, false, false, 0); 7869 7870 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7871 getPointerTy()); 7872 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7873 7874 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7875 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7876 false, false, false, 0); 7877 7878 // Get the offset of start of .tls section 7879 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7880 GA->getValueType(0), 7881 GA->getOffset(), X86II::MO_SECREL); 7882 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7883 7884 // The address of the thread local variable is the add of the thread 7885 // pointer with the offset of the variable. 7886 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7887 } 7888 7889 llvm_unreachable("TLS not implemented for this target."); 7890} 7891 7892/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7893/// and take a 2 x i32 value to shift plus a shift amount. 7894SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7895 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7896 EVT VT = Op.getValueType(); 7897 unsigned VTBits = VT.getSizeInBits(); 7898 DebugLoc dl = Op.getDebugLoc(); 7899 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7900 SDValue ShOpLo = Op.getOperand(0); 7901 SDValue ShOpHi = Op.getOperand(1); 7902 SDValue ShAmt = Op.getOperand(2); 7903 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7904 DAG.getConstant(VTBits - 1, MVT::i8)) 7905 : DAG.getConstant(0, VT); 7906 7907 SDValue Tmp2, Tmp3; 7908 if (Op.getOpcode() == ISD::SHL_PARTS) { 7909 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7910 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7911 } else { 7912 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7913 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7914 } 7915 7916 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7917 DAG.getConstant(VTBits, MVT::i8)); 7918 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7919 AndNode, DAG.getConstant(0, MVT::i8)); 7920 7921 SDValue Hi, Lo; 7922 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7923 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7924 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7925 7926 if (Op.getOpcode() == ISD::SHL_PARTS) { 7927 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7928 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7929 } else { 7930 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7931 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7932 } 7933 7934 SDValue Ops[2] = { Lo, Hi }; 7935 return DAG.getMergeValues(Ops, 2, dl); 7936} 7937 7938SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7939 SelectionDAG &DAG) const { 7940 EVT SrcVT = Op.getOperand(0).getValueType(); 7941 7942 if (SrcVT.isVector()) 7943 return SDValue(); 7944 7945 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7946 "Unknown SINT_TO_FP to lower!"); 7947 7948 // These are really Legal; return the operand so the caller accepts it as 7949 // Legal. 7950 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7951 return Op; 7952 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7953 Subtarget->is64Bit()) { 7954 return Op; 7955 } 7956 7957 DebugLoc dl = Op.getDebugLoc(); 7958 unsigned Size = SrcVT.getSizeInBits()/8; 7959 MachineFunction &MF = DAG.getMachineFunction(); 7960 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7961 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7962 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7963 StackSlot, 7964 MachinePointerInfo::getFixedStack(SSFI), 7965 false, false, 0); 7966 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7967} 7968 7969SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7970 SDValue StackSlot, 7971 SelectionDAG &DAG) const { 7972 // Build the FILD 7973 DebugLoc DL = Op.getDebugLoc(); 7974 SDVTList Tys; 7975 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7976 if (useSSE) 7977 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7978 else 7979 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7980 7981 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7982 7983 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7984 MachineMemOperand *MMO; 7985 if (FI) { 7986 int SSFI = FI->getIndex(); 7987 MMO = 7988 DAG.getMachineFunction() 7989 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7990 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7991 } else { 7992 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7993 StackSlot = StackSlot.getOperand(1); 7994 } 7995 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7996 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7997 X86ISD::FILD, DL, 7998 Tys, Ops, array_lengthof(Ops), 7999 SrcVT, MMO); 8000 8001 if (useSSE) { 8002 Chain = Result.getValue(1); 8003 SDValue InFlag = Result.getValue(2); 8004 8005 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 8006 // shouldn't be necessary except that RFP cannot be live across 8007 // multiple blocks. When stackifier is fixed, they can be uncoupled. 8008 MachineFunction &MF = DAG.getMachineFunction(); 8009 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 8010 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 8011 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8012 Tys = DAG.getVTList(MVT::Other); 8013 SDValue Ops[] = { 8014 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 8015 }; 8016 MachineMemOperand *MMO = 8017 DAG.getMachineFunction() 8018 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8019 MachineMemOperand::MOStore, SSFISize, SSFISize); 8020 8021 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 8022 Ops, array_lengthof(Ops), 8023 Op.getValueType(), MMO); 8024 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 8025 MachinePointerInfo::getFixedStack(SSFI), 8026 false, false, false, 0); 8027 } 8028 8029 return Result; 8030} 8031 8032// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 8033SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 8034 SelectionDAG &DAG) const { 8035 // This algorithm is not obvious. Here it is what we're trying to output: 8036 /* 8037 movq %rax, %xmm0 8038 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 8039 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 8040 #ifdef __SSE3__ 8041 haddpd %xmm0, %xmm0 8042 #else 8043 pshufd $0x4e, %xmm0, %xmm1 8044 addpd %xmm1, %xmm0 8045 #endif 8046 */ 8047 8048 DebugLoc dl = Op.getDebugLoc(); 8049 LLVMContext *Context = DAG.getContext(); 8050 8051 // Build some magic constants. 8052 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 8053 Constant *C0 = ConstantDataVector::get(*Context, CV0); 8054 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 8055 8056 SmallVector<Constant*,2> CV1; 8057 CV1.push_back( 8058 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble, 8059 APInt(64, 0x4330000000000000ULL)))); 8060 CV1.push_back( 8061 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble, 8062 APInt(64, 0x4530000000000000ULL)))); 8063 Constant *C1 = ConstantVector::get(CV1); 8064 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 8065 8066 // Load the 64-bit value into an XMM register. 8067 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 8068 Op.getOperand(0)); 8069 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 8070 MachinePointerInfo::getConstantPool(), 8071 false, false, false, 16); 8072 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 8073 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 8074 CLod0); 8075 8076 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 8077 MachinePointerInfo::getConstantPool(), 8078 false, false, false, 16); 8079 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 8080 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 8081 SDValue Result; 8082 8083 if (Subtarget->hasSSE3()) { 8084 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 8085 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 8086 } else { 8087 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 8088 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 8089 S2F, 0x4E, DAG); 8090 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 8091 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 8092 Sub); 8093 } 8094 8095 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 8096 DAG.getIntPtrConstant(0)); 8097} 8098 8099// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 8100SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 8101 SelectionDAG &DAG) const { 8102 DebugLoc dl = Op.getDebugLoc(); 8103 // FP constant to bias correct the final result. 8104 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 8105 MVT::f64); 8106 8107 // Load the 32-bit value into an XMM register. 8108 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 8109 Op.getOperand(0)); 8110 8111 // Zero out the upper parts of the register. 8112 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 8113 8114 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 8115 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 8116 DAG.getIntPtrConstant(0)); 8117 8118 // Or the load with the bias. 8119 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 8120 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8121 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 8122 MVT::v2f64, Load)), 8123 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8124 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 8125 MVT::v2f64, Bias))); 8126 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 8127 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 8128 DAG.getIntPtrConstant(0)); 8129 8130 // Subtract the bias. 8131 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 8132 8133 // Handle final rounding. 8134 EVT DestVT = Op.getValueType(); 8135 8136 if (DestVT.bitsLT(MVT::f64)) 8137 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 8138 DAG.getIntPtrConstant(0)); 8139 if (DestVT.bitsGT(MVT::f64)) 8140 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 8141 8142 // Handle final rounding. 8143 return Sub; 8144} 8145 8146SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op, 8147 SelectionDAG &DAG) const { 8148 SDValue N0 = Op.getOperand(0); 8149 EVT SVT = N0.getValueType(); 8150 DebugLoc dl = Op.getDebugLoc(); 8151 8152 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 || 8153 SVT == MVT::v8i8 || SVT == MVT::v8i16) && 8154 "Custom UINT_TO_FP is not supported!"); 8155 8156 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, 8157 SVT.getVectorNumElements()); 8158 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), 8159 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0)); 8160} 8161 8162SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 8163 SelectionDAG &DAG) const { 8164 SDValue N0 = Op.getOperand(0); 8165 DebugLoc dl = Op.getDebugLoc(); 8166 8167 if (Op.getValueType().isVector()) 8168 return lowerUINT_TO_FP_vec(Op, DAG); 8169 8170 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 8171 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 8172 // the optimization here. 8173 if (DAG.SignBitIsZero(N0)) 8174 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 8175 8176 EVT SrcVT = N0.getValueType(); 8177 EVT DstVT = Op.getValueType(); 8178 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 8179 return LowerUINT_TO_FP_i64(Op, DAG); 8180 if (SrcVT == MVT::i32 && X86ScalarSSEf64) 8181 return LowerUINT_TO_FP_i32(Op, DAG); 8182 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 8183 return SDValue(); 8184 8185 // Make a 64-bit buffer, and use it to build an FILD. 8186 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 8187 if (SrcVT == MVT::i32) { 8188 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 8189 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 8190 getPointerTy(), StackSlot, WordOff); 8191 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8192 StackSlot, MachinePointerInfo(), 8193 false, false, 0); 8194 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 8195 OffsetSlot, MachinePointerInfo(), 8196 false, false, 0); 8197 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 8198 return Fild; 8199 } 8200 8201 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 8202 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8203 StackSlot, MachinePointerInfo(), 8204 false, false, 0); 8205 // For i64 source, we need to add the appropriate power of 2 if the input 8206 // was negative. This is the same as the optimization in 8207 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 8208 // we must be careful to do the computation in x87 extended precision, not 8209 // in SSE. (The generic code can't know it's OK to do this, or how to.) 8210 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 8211 MachineMemOperand *MMO = 8212 DAG.getMachineFunction() 8213 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8214 MachineMemOperand::MOLoad, 8, 8); 8215 8216 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 8217 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 8218 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 8219 MVT::i64, MMO); 8220 8221 APInt FF(32, 0x5F800000ULL); 8222 8223 // Check whether the sign bit is set. 8224 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 8225 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 8226 ISD::SETLT); 8227 8228 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 8229 SDValue FudgePtr = DAG.getConstantPool( 8230 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 8231 getPointerTy()); 8232 8233 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 8234 SDValue Zero = DAG.getIntPtrConstant(0); 8235 SDValue Four = DAG.getIntPtrConstant(4); 8236 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 8237 Zero, Four); 8238 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 8239 8240 // Load the value out, extending it from f32 to f80. 8241 // FIXME: Avoid the extend by constructing the right constant pool? 8242 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 8243 FudgePtr, MachinePointerInfo::getConstantPool(), 8244 MVT::f32, false, false, 4); 8245 // Extend everything to 80 bits to force it to be done on x87. 8246 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 8247 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 8248} 8249 8250std::pair<SDValue,SDValue> 8251X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 8252 bool IsSigned, bool IsReplace) const { 8253 DebugLoc DL = Op.getDebugLoc(); 8254 8255 EVT DstTy = Op.getValueType(); 8256 8257 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 8258 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 8259 DstTy = MVT::i64; 8260 } 8261 8262 assert(DstTy.getSimpleVT() <= MVT::i64 && 8263 DstTy.getSimpleVT() >= MVT::i16 && 8264 "Unknown FP_TO_INT to lower!"); 8265 8266 // These are really Legal. 8267 if (DstTy == MVT::i32 && 8268 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8269 return std::make_pair(SDValue(), SDValue()); 8270 if (Subtarget->is64Bit() && 8271 DstTy == MVT::i64 && 8272 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8273 return std::make_pair(SDValue(), SDValue()); 8274 8275 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 8276 // stack slot, or into the FTOL runtime function. 8277 MachineFunction &MF = DAG.getMachineFunction(); 8278 unsigned MemSize = DstTy.getSizeInBits()/8; 8279 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8280 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8281 8282 unsigned Opc; 8283 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 8284 Opc = X86ISD::WIN_FTOL; 8285 else 8286 switch (DstTy.getSimpleVT().SimpleTy) { 8287 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 8288 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 8289 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 8290 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 8291 } 8292 8293 SDValue Chain = DAG.getEntryNode(); 8294 SDValue Value = Op.getOperand(0); 8295 EVT TheVT = Op.getOperand(0).getValueType(); 8296 // FIXME This causes a redundant load/store if the SSE-class value is already 8297 // in memory, such as if it is on the callstack. 8298 if (isScalarFPTypeInSSEReg(TheVT)) { 8299 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 8300 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 8301 MachinePointerInfo::getFixedStack(SSFI), 8302 false, false, 0); 8303 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 8304 SDValue Ops[] = { 8305 Chain, StackSlot, DAG.getValueType(TheVT) 8306 }; 8307 8308 MachineMemOperand *MMO = 8309 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8310 MachineMemOperand::MOLoad, MemSize, MemSize); 8311 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 8312 DstTy, MMO); 8313 Chain = Value.getValue(1); 8314 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8315 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8316 } 8317 8318 MachineMemOperand *MMO = 8319 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8320 MachineMemOperand::MOStore, MemSize, MemSize); 8321 8322 if (Opc != X86ISD::WIN_FTOL) { 8323 // Build the FP_TO_INT*_IN_MEM 8324 SDValue Ops[] = { Chain, Value, StackSlot }; 8325 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 8326 Ops, 3, DstTy, MMO); 8327 return std::make_pair(FIST, StackSlot); 8328 } else { 8329 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 8330 DAG.getVTList(MVT::Other, MVT::Glue), 8331 Chain, Value); 8332 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 8333 MVT::i32, ftol.getValue(1)); 8334 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 8335 MVT::i32, eax.getValue(2)); 8336 SDValue Ops[] = { eax, edx }; 8337 SDValue pair = IsReplace 8338 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 8339 : DAG.getMergeValues(Ops, 2, DL); 8340 return std::make_pair(pair, SDValue()); 8341 } 8342} 8343 8344static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG, 8345 const X86Subtarget *Subtarget) { 8346 MVT VT = Op->getValueType(0).getSimpleVT(); 8347 SDValue In = Op->getOperand(0); 8348 MVT InVT = In.getValueType().getSimpleVT(); 8349 DebugLoc dl = Op->getDebugLoc(); 8350 8351 // Optimize vectors in AVX mode: 8352 // 8353 // v8i16 -> v8i32 8354 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 8355 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 8356 // Concat upper and lower parts. 8357 // 8358 // v4i32 -> v4i64 8359 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 8360 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 8361 // Concat upper and lower parts. 8362 // 8363 8364 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) && 8365 ((VT != MVT::v4i64) || (InVT != MVT::v4i32))) 8366 return SDValue(); 8367 8368 if (Subtarget->hasInt256()) 8369 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In); 8370 8371 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl); 8372 SDValue Undef = DAG.getUNDEF(InVT); 8373 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND; 8374 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); 8375 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); 8376 8377 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(), 8378 VT.getVectorNumElements()/2); 8379 8380 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 8381 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 8382 8383 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 8384} 8385 8386SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op, 8387 SelectionDAG &DAG) const { 8388 if (Subtarget->hasFp256()) { 8389 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget); 8390 if (Res.getNode()) 8391 return Res; 8392 } 8393 8394 return SDValue(); 8395} 8396SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op, 8397 SelectionDAG &DAG) const { 8398 DebugLoc DL = Op.getDebugLoc(); 8399 MVT VT = Op.getValueType().getSimpleVT(); 8400 SDValue In = Op.getOperand(0); 8401 MVT SVT = In.getValueType().getSimpleVT(); 8402 8403 if (Subtarget->hasFp256()) { 8404 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget); 8405 if (Res.getNode()) 8406 return Res; 8407 } 8408 8409 if (!VT.is256BitVector() || !SVT.is128BitVector() || 8410 VT.getVectorNumElements() != SVT.getVectorNumElements()) 8411 return SDValue(); 8412 8413 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!"); 8414 8415 // AVX2 has better support of integer extending. 8416 if (Subtarget->hasInt256()) 8417 return DAG.getNode(X86ISD::VZEXT, DL, VT, In); 8418 8419 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In); 8420 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1}; 8421 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, 8422 DAG.getVectorShuffle(MVT::v8i16, DL, In, 8423 DAG.getUNDEF(MVT::v8i16), 8424 &Mask[0])); 8425 8426 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi); 8427} 8428 8429SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const { 8430 DebugLoc DL = Op.getDebugLoc(); 8431 MVT VT = Op.getValueType().getSimpleVT(); 8432 SDValue In = Op.getOperand(0); 8433 MVT SVT = In.getValueType().getSimpleVT(); 8434 8435 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) { 8436 // On AVX2, v4i64 -> v4i32 becomes VPERMD. 8437 if (Subtarget->hasInt256()) { 8438 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1}; 8439 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In); 8440 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32), 8441 ShufMask); 8442 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In, 8443 DAG.getIntPtrConstant(0)); 8444 } 8445 8446 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS. 8447 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 8448 DAG.getIntPtrConstant(0)); 8449 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 8450 DAG.getIntPtrConstant(2)); 8451 8452 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo); 8453 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi); 8454 8455 // The PSHUFD mask: 8456 static const int ShufMask1[] = {0, 2, 0, 0}; 8457 SDValue Undef = DAG.getUNDEF(VT); 8458 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1); 8459 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1); 8460 8461 // The MOVLHPS mask: 8462 static const int ShufMask2[] = {0, 1, 4, 5}; 8463 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2); 8464 } 8465 8466 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) { 8467 // On AVX2, v8i32 -> v8i16 becomed PSHUFB. 8468 if (Subtarget->hasInt256()) { 8469 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In); 8470 8471 SmallVector<SDValue,32> pshufbMask; 8472 for (unsigned i = 0; i < 2; ++i) { 8473 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8)); 8474 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8)); 8475 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8)); 8476 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8)); 8477 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8)); 8478 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8)); 8479 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8)); 8480 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8)); 8481 for (unsigned j = 0; j < 8; ++j) 8482 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 8483 } 8484 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, 8485 &pshufbMask[0], 32); 8486 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV); 8487 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In); 8488 8489 static const int ShufMask[] = {0, 2, -1, -1}; 8490 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64), 8491 &ShufMask[0]); 8492 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 8493 DAG.getIntPtrConstant(0)); 8494 return DAG.getNode(ISD::BITCAST, DL, VT, In); 8495 } 8496 8497 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In, 8498 DAG.getIntPtrConstant(0)); 8499 8500 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In, 8501 DAG.getIntPtrConstant(4)); 8502 8503 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo); 8504 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi); 8505 8506 // The PSHUFB mask: 8507 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 8508 -1, -1, -1, -1, -1, -1, -1, -1}; 8509 8510 SDValue Undef = DAG.getUNDEF(MVT::v16i8); 8511 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1); 8512 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1); 8513 8514 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo); 8515 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi); 8516 8517 // The MOVLHPS Mask: 8518 static const int ShufMask2[] = {0, 1, 4, 5}; 8519 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2); 8520 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res); 8521 } 8522 8523 // Handle truncation of V256 to V128 using shuffles. 8524 if (!VT.is128BitVector() || !SVT.is256BitVector()) 8525 return SDValue(); 8526 8527 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() && 8528 "Invalid op"); 8529 assert(Subtarget->hasFp256() && "256-bit vector without AVX!"); 8530 8531 unsigned NumElems = VT.getVectorNumElements(); 8532 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 8533 NumElems * 2); 8534 8535 SmallVector<int, 16> MaskVec(NumElems * 2, -1); 8536 // Prepare truncation shuffle mask 8537 for (unsigned i = 0; i != NumElems; ++i) 8538 MaskVec[i] = i * 2; 8539 SDValue V = DAG.getVectorShuffle(NVT, DL, 8540 DAG.getNode(ISD::BITCAST, DL, NVT, In), 8541 DAG.getUNDEF(NVT), &MaskVec[0]); 8542 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, 8543 DAG.getIntPtrConstant(0)); 8544} 8545 8546SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 8547 SelectionDAG &DAG) const { 8548 MVT VT = Op.getValueType().getSimpleVT(); 8549 if (VT.isVector()) { 8550 if (VT == MVT::v8i16) 8551 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), VT, 8552 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(), 8553 MVT::v8i32, Op.getOperand(0))); 8554 return SDValue(); 8555 } 8556 8557 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 8558 /*IsSigned=*/ true, /*IsReplace=*/ false); 8559 SDValue FIST = Vals.first, StackSlot = Vals.second; 8560 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 8561 if (FIST.getNode() == 0) return Op; 8562 8563 if (StackSlot.getNode()) 8564 // Load the result. 8565 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8566 FIST, StackSlot, MachinePointerInfo(), 8567 false, false, false, 0); 8568 8569 // The node is the result. 8570 return FIST; 8571} 8572 8573SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 8574 SelectionDAG &DAG) const { 8575 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 8576 /*IsSigned=*/ false, /*IsReplace=*/ false); 8577 SDValue FIST = Vals.first, StackSlot = Vals.second; 8578 assert(FIST.getNode() && "Unexpected failure"); 8579 8580 if (StackSlot.getNode()) 8581 // Load the result. 8582 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8583 FIST, StackSlot, MachinePointerInfo(), 8584 false, false, false, 0); 8585 8586 // The node is the result. 8587 return FIST; 8588} 8589 8590static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) { 8591 DebugLoc DL = Op.getDebugLoc(); 8592 MVT VT = Op.getValueType().getSimpleVT(); 8593 SDValue In = Op.getOperand(0); 8594 MVT SVT = In.getValueType().getSimpleVT(); 8595 8596 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!"); 8597 8598 return DAG.getNode(X86ISD::VFPEXT, DL, VT, 8599 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32, 8600 In, DAG.getUNDEF(SVT))); 8601} 8602 8603SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 8604 LLVMContext *Context = DAG.getContext(); 8605 DebugLoc dl = Op.getDebugLoc(); 8606 MVT VT = Op.getValueType().getSimpleVT(); 8607 MVT EltVT = VT; 8608 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 8609 if (VT.isVector()) { 8610 EltVT = VT.getVectorElementType(); 8611 NumElts = VT.getVectorNumElements(); 8612 } 8613 Constant *C; 8614 if (EltVT == MVT::f64) 8615 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble, 8616 APInt(64, ~(1ULL << 63)))); 8617 else 8618 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle, 8619 APInt(32, ~(1U << 31)))); 8620 C = ConstantVector::getSplat(NumElts, C); 8621 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy()); 8622 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8623 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8624 MachinePointerInfo::getConstantPool(), 8625 false, false, false, Alignment); 8626 if (VT.isVector()) { 8627 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8628 return DAG.getNode(ISD::BITCAST, dl, VT, 8629 DAG.getNode(ISD::AND, dl, ANDVT, 8630 DAG.getNode(ISD::BITCAST, dl, ANDVT, 8631 Op.getOperand(0)), 8632 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask))); 8633 } 8634 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 8635} 8636 8637SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 8638 LLVMContext *Context = DAG.getContext(); 8639 DebugLoc dl = Op.getDebugLoc(); 8640 MVT VT = Op.getValueType().getSimpleVT(); 8641 MVT EltVT = VT; 8642 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 8643 if (VT.isVector()) { 8644 EltVT = VT.getVectorElementType(); 8645 NumElts = VT.getVectorNumElements(); 8646 } 8647 Constant *C; 8648 if (EltVT == MVT::f64) 8649 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble, 8650 APInt(64, 1ULL << 63))); 8651 else 8652 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle, 8653 APInt(32, 1U << 31))); 8654 C = ConstantVector::getSplat(NumElts, C); 8655 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy()); 8656 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8657 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8658 MachinePointerInfo::getConstantPool(), 8659 false, false, false, Alignment); 8660 if (VT.isVector()) { 8661 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8662 return DAG.getNode(ISD::BITCAST, dl, VT, 8663 DAG.getNode(ISD::XOR, dl, XORVT, 8664 DAG.getNode(ISD::BITCAST, dl, XORVT, 8665 Op.getOperand(0)), 8666 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 8667 } 8668 8669 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8670} 8671 8672SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8673 LLVMContext *Context = DAG.getContext(); 8674 SDValue Op0 = Op.getOperand(0); 8675 SDValue Op1 = Op.getOperand(1); 8676 DebugLoc dl = Op.getDebugLoc(); 8677 MVT VT = Op.getValueType().getSimpleVT(); 8678 MVT SrcVT = Op1.getValueType().getSimpleVT(); 8679 8680 // If second operand is smaller, extend it first. 8681 if (SrcVT.bitsLT(VT)) { 8682 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8683 SrcVT = VT; 8684 } 8685 // And if it is bigger, shrink it first. 8686 if (SrcVT.bitsGT(VT)) { 8687 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8688 SrcVT = VT; 8689 } 8690 8691 // At this point the operands and the result should have the same 8692 // type, and that won't be f80 since that is not custom lowered. 8693 8694 // First get the sign bit of second operand. 8695 SmallVector<Constant*,4> CV; 8696 if (SrcVT == MVT::f64) { 8697 const fltSemantics &Sem = APFloat::IEEEdouble; 8698 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63)))); 8699 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0)))); 8700 } else { 8701 const fltSemantics &Sem = APFloat::IEEEsingle; 8702 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31)))); 8703 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 8704 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 8705 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 8706 } 8707 Constant *C = ConstantVector::get(CV); 8708 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8709 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8710 MachinePointerInfo::getConstantPool(), 8711 false, false, false, 16); 8712 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8713 8714 // Shift sign bit right or left if the two operands have different types. 8715 if (SrcVT.bitsGT(VT)) { 8716 // Op0 is MVT::f32, Op1 is MVT::f64. 8717 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8718 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8719 DAG.getConstant(32, MVT::i32)); 8720 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8721 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8722 DAG.getIntPtrConstant(0)); 8723 } 8724 8725 // Clear first operand sign bit. 8726 CV.clear(); 8727 if (VT == MVT::f64) { 8728 const fltSemantics &Sem = APFloat::IEEEdouble; 8729 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, 8730 APInt(64, ~(1ULL << 63))))); 8731 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0)))); 8732 } else { 8733 const fltSemantics &Sem = APFloat::IEEEsingle; 8734 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, 8735 APInt(32, ~(1U << 31))))); 8736 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 8737 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 8738 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0)))); 8739 } 8740 C = ConstantVector::get(CV); 8741 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8742 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8743 MachinePointerInfo::getConstantPool(), 8744 false, false, false, 16); 8745 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8746 8747 // Or the value with the sign bit. 8748 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8749} 8750 8751static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) { 8752 SDValue N0 = Op.getOperand(0); 8753 DebugLoc dl = Op.getDebugLoc(); 8754 MVT VT = Op.getValueType().getSimpleVT(); 8755 8756 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8757 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8758 DAG.getConstant(1, VT)); 8759 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8760} 8761 8762// LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able. 8763// 8764SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, 8765 SelectionDAG &DAG) const { 8766 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree."); 8767 8768 if (!Subtarget->hasSSE41()) 8769 return SDValue(); 8770 8771 if (!Op->hasOneUse()) 8772 return SDValue(); 8773 8774 SDNode *N = Op.getNode(); 8775 DebugLoc DL = N->getDebugLoc(); 8776 8777 SmallVector<SDValue, 8> Opnds; 8778 DenseMap<SDValue, unsigned> VecInMap; 8779 EVT VT = MVT::Other; 8780 8781 // Recognize a special case where a vector is casted into wide integer to 8782 // test all 0s. 8783 Opnds.push_back(N->getOperand(0)); 8784 Opnds.push_back(N->getOperand(1)); 8785 8786 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) { 8787 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot; 8788 // BFS traverse all OR'd operands. 8789 if (I->getOpcode() == ISD::OR) { 8790 Opnds.push_back(I->getOperand(0)); 8791 Opnds.push_back(I->getOperand(1)); 8792 // Re-evaluate the number of nodes to be traversed. 8793 e += 2; // 2 more nodes (LHS and RHS) are pushed. 8794 continue; 8795 } 8796 8797 // Quit if a non-EXTRACT_VECTOR_ELT 8798 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 8799 return SDValue(); 8800 8801 // Quit if without a constant index. 8802 SDValue Idx = I->getOperand(1); 8803 if (!isa<ConstantSDNode>(Idx)) 8804 return SDValue(); 8805 8806 SDValue ExtractedFromVec = I->getOperand(0); 8807 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec); 8808 if (M == VecInMap.end()) { 8809 VT = ExtractedFromVec.getValueType(); 8810 // Quit if not 128/256-bit vector. 8811 if (!VT.is128BitVector() && !VT.is256BitVector()) 8812 return SDValue(); 8813 // Quit if not the same type. 8814 if (VecInMap.begin() != VecInMap.end() && 8815 VT != VecInMap.begin()->first.getValueType()) 8816 return SDValue(); 8817 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first; 8818 } 8819 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue(); 8820 } 8821 8822 assert((VT.is128BitVector() || VT.is256BitVector()) && 8823 "Not extracted from 128-/256-bit vector."); 8824 8825 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U; 8826 SmallVector<SDValue, 8> VecIns; 8827 8828 for (DenseMap<SDValue, unsigned>::const_iterator 8829 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) { 8830 // Quit if not all elements are used. 8831 if (I->second != FullMask) 8832 return SDValue(); 8833 VecIns.push_back(I->first); 8834 } 8835 8836 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8837 8838 // Cast all vectors into TestVT for PTEST. 8839 for (unsigned i = 0, e = VecIns.size(); i < e; ++i) 8840 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]); 8841 8842 // If more than one full vectors are evaluated, OR them first before PTEST. 8843 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) { 8844 // Each iteration will OR 2 nodes and append the result until there is only 8845 // 1 node left, i.e. the final OR'd value of all vectors. 8846 SDValue LHS = VecIns[Slot]; 8847 SDValue RHS = VecIns[Slot + 1]; 8848 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS)); 8849 } 8850 8851 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32, 8852 VecIns.back(), VecIns.back()); 8853} 8854 8855/// Emit nodes that will be selected as "test Op0,Op0", or something 8856/// equivalent. 8857SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8858 SelectionDAG &DAG) const { 8859 DebugLoc dl = Op.getDebugLoc(); 8860 8861 // CF and OF aren't always set the way we want. Determine which 8862 // of these we need. 8863 bool NeedCF = false; 8864 bool NeedOF = false; 8865 switch (X86CC) { 8866 default: break; 8867 case X86::COND_A: case X86::COND_AE: 8868 case X86::COND_B: case X86::COND_BE: 8869 NeedCF = true; 8870 break; 8871 case X86::COND_G: case X86::COND_GE: 8872 case X86::COND_L: case X86::COND_LE: 8873 case X86::COND_O: case X86::COND_NO: 8874 NeedOF = true; 8875 break; 8876 } 8877 8878 // See if we can use the EFLAGS value from the operand instead of 8879 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8880 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8881 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8882 // Emit a CMP with 0, which is the TEST pattern. 8883 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8884 DAG.getConstant(0, Op.getValueType())); 8885 8886 unsigned Opcode = 0; 8887 unsigned NumOperands = 0; 8888 8889 // Truncate operations may prevent the merge of the SETCC instruction 8890 // and the arithmetic intruction before it. Attempt to truncate the operands 8891 // of the arithmetic instruction and use a reduced bit-width instruction. 8892 bool NeedTruncation = false; 8893 SDValue ArithOp = Op; 8894 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) { 8895 SDValue Arith = Op->getOperand(0); 8896 // Both the trunc and the arithmetic op need to have one user each. 8897 if (Arith->hasOneUse()) 8898 switch (Arith.getOpcode()) { 8899 default: break; 8900 case ISD::ADD: 8901 case ISD::SUB: 8902 case ISD::AND: 8903 case ISD::OR: 8904 case ISD::XOR: { 8905 NeedTruncation = true; 8906 ArithOp = Arith; 8907 } 8908 } 8909 } 8910 8911 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation 8912 // which may be the result of a CAST. We use the variable 'Op', which is the 8913 // non-casted variable when we check for possible users. 8914 switch (ArithOp.getOpcode()) { 8915 case ISD::ADD: 8916 // Due to an isel shortcoming, be conservative if this add is likely to be 8917 // selected as part of a load-modify-store instruction. When the root node 8918 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8919 // uses of other nodes in the match, such as the ADD in this case. This 8920 // leads to the ADD being left around and reselected, with the result being 8921 // two adds in the output. Alas, even if none our users are stores, that 8922 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8923 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8924 // climbing the DAG back to the root, and it doesn't seem to be worth the 8925 // effort. 8926 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8927 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8928 if (UI->getOpcode() != ISD::CopyToReg && 8929 UI->getOpcode() != ISD::SETCC && 8930 UI->getOpcode() != ISD::STORE) 8931 goto default_case; 8932 8933 if (ConstantSDNode *C = 8934 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) { 8935 // An add of one will be selected as an INC. 8936 if (C->getAPIntValue() == 1) { 8937 Opcode = X86ISD::INC; 8938 NumOperands = 1; 8939 break; 8940 } 8941 8942 // An add of negative one (subtract of one) will be selected as a DEC. 8943 if (C->getAPIntValue().isAllOnesValue()) { 8944 Opcode = X86ISD::DEC; 8945 NumOperands = 1; 8946 break; 8947 } 8948 } 8949 8950 // Otherwise use a regular EFLAGS-setting add. 8951 Opcode = X86ISD::ADD; 8952 NumOperands = 2; 8953 break; 8954 case ISD::AND: { 8955 // If the primary and result isn't used, don't bother using X86ISD::AND, 8956 // because a TEST instruction will be better. 8957 bool NonFlagUse = false; 8958 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8959 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8960 SDNode *User = *UI; 8961 unsigned UOpNo = UI.getOperandNo(); 8962 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8963 // Look pass truncate. 8964 UOpNo = User->use_begin().getOperandNo(); 8965 User = *User->use_begin(); 8966 } 8967 8968 if (User->getOpcode() != ISD::BRCOND && 8969 User->getOpcode() != ISD::SETCC && 8970 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) { 8971 NonFlagUse = true; 8972 break; 8973 } 8974 } 8975 8976 if (!NonFlagUse) 8977 break; 8978 } 8979 // FALL THROUGH 8980 case ISD::SUB: 8981 case ISD::OR: 8982 case ISD::XOR: 8983 // Due to the ISEL shortcoming noted above, be conservative if this op is 8984 // likely to be selected as part of a load-modify-store instruction. 8985 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8986 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8987 if (UI->getOpcode() == ISD::STORE) 8988 goto default_case; 8989 8990 // Otherwise use a regular EFLAGS-setting instruction. 8991 switch (ArithOp.getOpcode()) { 8992 default: llvm_unreachable("unexpected operator!"); 8993 case ISD::SUB: Opcode = X86ISD::SUB; break; 8994 case ISD::XOR: Opcode = X86ISD::XOR; break; 8995 case ISD::AND: Opcode = X86ISD::AND; break; 8996 case ISD::OR: { 8997 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) { 8998 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG); 8999 if (EFLAGS.getNode()) 9000 return EFLAGS; 9001 } 9002 Opcode = X86ISD::OR; 9003 break; 9004 } 9005 } 9006 9007 NumOperands = 2; 9008 break; 9009 case X86ISD::ADD: 9010 case X86ISD::SUB: 9011 case X86ISD::INC: 9012 case X86ISD::DEC: 9013 case X86ISD::OR: 9014 case X86ISD::XOR: 9015 case X86ISD::AND: 9016 return SDValue(Op.getNode(), 1); 9017 default: 9018 default_case: 9019 break; 9020 } 9021 9022 // If we found that truncation is beneficial, perform the truncation and 9023 // update 'Op'. 9024 if (NeedTruncation) { 9025 EVT VT = Op.getValueType(); 9026 SDValue WideVal = Op->getOperand(0); 9027 EVT WideVT = WideVal.getValueType(); 9028 unsigned ConvertedOp = 0; 9029 // Use a target machine opcode to prevent further DAGCombine 9030 // optimizations that may separate the arithmetic operations 9031 // from the setcc node. 9032 switch (WideVal.getOpcode()) { 9033 default: break; 9034 case ISD::ADD: ConvertedOp = X86ISD::ADD; break; 9035 case ISD::SUB: ConvertedOp = X86ISD::SUB; break; 9036 case ISD::AND: ConvertedOp = X86ISD::AND; break; 9037 case ISD::OR: ConvertedOp = X86ISD::OR; break; 9038 case ISD::XOR: ConvertedOp = X86ISD::XOR; break; 9039 } 9040 9041 if (ConvertedOp) { 9042 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9043 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { 9044 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0)); 9045 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1)); 9046 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1); 9047 } 9048 } 9049 } 9050 9051 if (Opcode == 0) 9052 // Emit a CMP with 0, which is the TEST pattern. 9053 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 9054 DAG.getConstant(0, Op.getValueType())); 9055 9056 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 9057 SmallVector<SDValue, 4> Ops; 9058 for (unsigned i = 0; i != NumOperands; ++i) 9059 Ops.push_back(Op.getOperand(i)); 9060 9061 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 9062 DAG.ReplaceAllUsesWith(Op, New); 9063 return SDValue(New.getNode(), 1); 9064} 9065 9066/// Emit nodes that will be selected as "cmp Op0,Op1", or something 9067/// equivalent. 9068SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 9069 SelectionDAG &DAG) const { 9070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 9071 if (C->getAPIntValue() == 0) 9072 return EmitTest(Op0, X86CC, DAG); 9073 9074 DebugLoc dl = Op0.getDebugLoc(); 9075 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 || 9076 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) { 9077 // Use SUB instead of CMP to enable CSE between SUB and CMP. 9078 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32); 9079 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, 9080 Op0, Op1); 9081 return SDValue(Sub.getNode(), 1); 9082 } 9083 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 9084} 9085 9086/// Convert a comparison if required by the subtarget. 9087SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp, 9088 SelectionDAG &DAG) const { 9089 // If the subtarget does not support the FUCOMI instruction, floating-point 9090 // comparisons have to be converted. 9091 if (Subtarget->hasCMov() || 9092 Cmp.getOpcode() != X86ISD::CMP || 9093 !Cmp.getOperand(0).getValueType().isFloatingPoint() || 9094 !Cmp.getOperand(1).getValueType().isFloatingPoint()) 9095 return Cmp; 9096 9097 // The instruction selector will select an FUCOM instruction instead of 9098 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence 9099 // build an SDNode sequence that transfers the result from FPSW into EFLAGS: 9100 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8)))) 9101 DebugLoc dl = Cmp.getDebugLoc(); 9102 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp); 9103 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW); 9104 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, 9105 DAG.getConstant(8, MVT::i8)); 9106 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); 9107 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); 9108} 9109 9110static bool isAllOnes(SDValue V) { 9111 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 9112 return C && C->isAllOnesValue(); 9113} 9114 9115/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 9116/// if it's possible. 9117SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 9118 DebugLoc dl, SelectionDAG &DAG) const { 9119 SDValue Op0 = And.getOperand(0); 9120 SDValue Op1 = And.getOperand(1); 9121 if (Op0.getOpcode() == ISD::TRUNCATE) 9122 Op0 = Op0.getOperand(0); 9123 if (Op1.getOpcode() == ISD::TRUNCATE) 9124 Op1 = Op1.getOperand(0); 9125 9126 SDValue LHS, RHS; 9127 if (Op1.getOpcode() == ISD::SHL) 9128 std::swap(Op0, Op1); 9129 if (Op0.getOpcode() == ISD::SHL) { 9130 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 9131 if (And00C->getZExtValue() == 1) { 9132 // If we looked past a truncate, check that it's only truncating away 9133 // known zeros. 9134 unsigned BitWidth = Op0.getValueSizeInBits(); 9135 unsigned AndBitWidth = And.getValueSizeInBits(); 9136 if (BitWidth > AndBitWidth) { 9137 APInt Zeros, Ones; 9138 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 9139 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 9140 return SDValue(); 9141 } 9142 LHS = Op1; 9143 RHS = Op0.getOperand(1); 9144 } 9145 } else if (Op1.getOpcode() == ISD::Constant) { 9146 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 9147 uint64_t AndRHSVal = AndRHS->getZExtValue(); 9148 SDValue AndLHS = Op0; 9149 9150 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 9151 LHS = AndLHS.getOperand(0); 9152 RHS = AndLHS.getOperand(1); 9153 } 9154 9155 // Use BT if the immediate can't be encoded in a TEST instruction. 9156 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 9157 LHS = AndLHS; 9158 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 9159 } 9160 } 9161 9162 if (LHS.getNode()) { 9163 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip 9164 // the condition code later. 9165 bool Invert = false; 9166 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) { 9167 Invert = true; 9168 LHS = LHS.getOperand(0); 9169 } 9170 9171 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 9172 // instruction. Since the shift amount is in-range-or-undefined, we know 9173 // that doing a bittest on the i32 value is ok. We extend to i32 because 9174 // the encoding for the i16 version is larger than the i32 version. 9175 // Also promote i16 to i32 for performance / code size reason. 9176 if (LHS.getValueType() == MVT::i8 || 9177 LHS.getValueType() == MVT::i16) 9178 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 9179 9180 // If the operand types disagree, extend the shift amount to match. Since 9181 // BT ignores high bits (like shifts) we can use anyextend. 9182 if (LHS.getValueType() != RHS.getValueType()) 9183 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 9184 9185 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 9186 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 9187 // Flip the condition if the LHS was a not instruction 9188 if (Invert) 9189 Cond = X86::GetOppositeBranchCondition(Cond); 9190 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9191 DAG.getConstant(Cond, MVT::i8), BT); 9192 } 9193 9194 return SDValue(); 9195} 9196 9197// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 9198// ones, and then concatenate the result back. 9199static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 9200 MVT VT = Op.getValueType().getSimpleVT(); 9201 9202 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC && 9203 "Unsupported value type for operation"); 9204 9205 unsigned NumElems = VT.getVectorNumElements(); 9206 DebugLoc dl = Op.getDebugLoc(); 9207 SDValue CC = Op.getOperand(2); 9208 9209 // Extract the LHS vectors 9210 SDValue LHS = Op.getOperand(0); 9211 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 9212 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 9213 9214 // Extract the RHS vectors 9215 SDValue RHS = Op.getOperand(1); 9216 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 9217 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 9218 9219 // Issue the operation on the smaller types and concatenate the result back 9220 MVT EltVT = VT.getVectorElementType(); 9221 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9222 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9223 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 9224 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 9225} 9226 9227static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget, 9228 SelectionDAG &DAG) { 9229 SDValue Cond; 9230 SDValue Op0 = Op.getOperand(0); 9231 SDValue Op1 = Op.getOperand(1); 9232 SDValue CC = Op.getOperand(2); 9233 MVT VT = Op.getValueType().getSimpleVT(); 9234 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 9235 bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint(); 9236 DebugLoc dl = Op.getDebugLoc(); 9237 9238 if (isFP) { 9239#ifndef NDEBUG 9240 MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT(); 9241 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 9242#endif 9243 9244 unsigned SSECC; 9245 bool Swap = false; 9246 9247 // SSE Condition code mapping: 9248 // 0 - EQ 9249 // 1 - LT 9250 // 2 - LE 9251 // 3 - UNORD 9252 // 4 - NEQ 9253 // 5 - NLT 9254 // 6 - NLE 9255 // 7 - ORD 9256 switch (SetCCOpcode) { 9257 default: llvm_unreachable("Unexpected SETCC condition"); 9258 case ISD::SETOEQ: 9259 case ISD::SETEQ: SSECC = 0; break; 9260 case ISD::SETOGT: 9261 case ISD::SETGT: Swap = true; // Fallthrough 9262 case ISD::SETLT: 9263 case ISD::SETOLT: SSECC = 1; break; 9264 case ISD::SETOGE: 9265 case ISD::SETGE: Swap = true; // Fallthrough 9266 case ISD::SETLE: 9267 case ISD::SETOLE: SSECC = 2; break; 9268 case ISD::SETUO: SSECC = 3; break; 9269 case ISD::SETUNE: 9270 case ISD::SETNE: SSECC = 4; break; 9271 case ISD::SETULE: Swap = true; // Fallthrough 9272 case ISD::SETUGE: SSECC = 5; break; 9273 case ISD::SETULT: Swap = true; // Fallthrough 9274 case ISD::SETUGT: SSECC = 6; break; 9275 case ISD::SETO: SSECC = 7; break; 9276 case ISD::SETUEQ: 9277 case ISD::SETONE: SSECC = 8; break; 9278 } 9279 if (Swap) 9280 std::swap(Op0, Op1); 9281 9282 // In the two special cases we can't handle, emit two comparisons. 9283 if (SSECC == 8) { 9284 unsigned CC0, CC1; 9285 unsigned CombineOpc; 9286 if (SetCCOpcode == ISD::SETUEQ) { 9287 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR; 9288 } else { 9289 assert(SetCCOpcode == ISD::SETONE); 9290 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND; 9291 } 9292 9293 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 9294 DAG.getConstant(CC0, MVT::i8)); 9295 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 9296 DAG.getConstant(CC1, MVT::i8)); 9297 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1); 9298 } 9299 // Handle all other FP comparisons here. 9300 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 9301 DAG.getConstant(SSECC, MVT::i8)); 9302 } 9303 9304 // Break 256-bit integer vector compare into smaller ones. 9305 if (VT.is256BitVector() && !Subtarget->hasInt256()) 9306 return Lower256IntVSETCC(Op, DAG); 9307 9308 // We are handling one of the integer comparisons here. Since SSE only has 9309 // GT and EQ comparisons for integer, swapping operands and multiple 9310 // operations may be required for some comparisons. 9311 unsigned Opc; 9312 bool Swap = false, Invert = false, FlipSigns = false; 9313 9314 switch (SetCCOpcode) { 9315 default: llvm_unreachable("Unexpected SETCC condition"); 9316 case ISD::SETNE: Invert = true; 9317 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 9318 case ISD::SETLT: Swap = true; 9319 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 9320 case ISD::SETGE: Swap = true; 9321 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 9322 case ISD::SETULT: Swap = true; 9323 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 9324 case ISD::SETUGE: Swap = true; 9325 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 9326 } 9327 if (Swap) 9328 std::swap(Op0, Op1); 9329 9330 // Check that the operation in question is available (most are plain SSE2, 9331 // but PCMPGTQ and PCMPEQQ have different requirements). 9332 if (VT == MVT::v2i64) { 9333 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) 9334 return SDValue(); 9335 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) { 9336 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with 9337 // pcmpeqd + pshufd + pand. 9338 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!"); 9339 9340 // First cast everything to the right type, 9341 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0); 9342 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); 9343 9344 // Do the compare. 9345 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1); 9346 9347 // Make sure the lower and upper halves are both all-ones. 9348 const int Mask[] = { 1, 0, 3, 2 }; 9349 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask); 9350 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf); 9351 9352 if (Invert) 9353 Result = DAG.getNOT(dl, Result, MVT::v4i32); 9354 9355 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 9356 } 9357 } 9358 9359 // Since SSE has no unsigned integer comparisons, we need to flip the sign 9360 // bits of the inputs before performing those operations. 9361 if (FlipSigns) { 9362 EVT EltVT = VT.getVectorElementType(); 9363 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 9364 EltVT); 9365 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 9366 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 9367 SignBits.size()); 9368 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 9369 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 9370 } 9371 9372 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 9373 9374 // If the logical-not of the result is required, perform that now. 9375 if (Invert) 9376 Result = DAG.getNOT(dl, Result, VT); 9377 9378 return Result; 9379} 9380 9381SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 9382 9383 MVT VT = Op.getValueType().getSimpleVT(); 9384 9385 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG); 9386 9387 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer"); 9388 SDValue Op0 = Op.getOperand(0); 9389 SDValue Op1 = Op.getOperand(1); 9390 DebugLoc dl = Op.getDebugLoc(); 9391 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 9392 9393 // Optimize to BT if possible. 9394 // Lower (X & (1 << N)) == 0 to BT(X, N). 9395 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 9396 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 9397 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 9398 Op1.getOpcode() == ISD::Constant && 9399 cast<ConstantSDNode>(Op1)->isNullValue() && 9400 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 9401 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 9402 if (NewSetCC.getNode()) 9403 return NewSetCC; 9404 } 9405 9406 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 9407 // these. 9408 if (Op1.getOpcode() == ISD::Constant && 9409 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 9410 cast<ConstantSDNode>(Op1)->isNullValue()) && 9411 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 9412 9413 // If the input is a setcc, then reuse the input setcc or use a new one with 9414 // the inverted condition. 9415 if (Op0.getOpcode() == X86ISD::SETCC) { 9416 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 9417 bool Invert = (CC == ISD::SETNE) ^ 9418 cast<ConstantSDNode>(Op1)->isNullValue(); 9419 if (!Invert) return Op0; 9420 9421 CCode = X86::GetOppositeBranchCondition(CCode); 9422 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9423 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 9424 } 9425 } 9426 9427 bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint(); 9428 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 9429 if (X86CC == X86::COND_INVALID) 9430 return SDValue(); 9431 9432 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 9433 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 9434 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9435 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 9436} 9437 9438// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 9439static bool isX86LogicalCmp(SDValue Op) { 9440 unsigned Opc = Op.getNode()->getOpcode(); 9441 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI || 9442 Opc == X86ISD::SAHF) 9443 return true; 9444 if (Op.getResNo() == 1 && 9445 (Opc == X86ISD::ADD || 9446 Opc == X86ISD::SUB || 9447 Opc == X86ISD::ADC || 9448 Opc == X86ISD::SBB || 9449 Opc == X86ISD::SMUL || 9450 Opc == X86ISD::UMUL || 9451 Opc == X86ISD::INC || 9452 Opc == X86ISD::DEC || 9453 Opc == X86ISD::OR || 9454 Opc == X86ISD::XOR || 9455 Opc == X86ISD::AND)) 9456 return true; 9457 9458 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 9459 return true; 9460 9461 return false; 9462} 9463 9464static bool isZero(SDValue V) { 9465 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 9466 return C && C->isNullValue(); 9467} 9468 9469static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) { 9470 if (V.getOpcode() != ISD::TRUNCATE) 9471 return false; 9472 9473 SDValue VOp0 = V.getOperand(0); 9474 unsigned InBits = VOp0.getValueSizeInBits(); 9475 unsigned Bits = V.getValueSizeInBits(); 9476 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits)); 9477} 9478 9479SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 9480 bool addTest = true; 9481 SDValue Cond = Op.getOperand(0); 9482 SDValue Op1 = Op.getOperand(1); 9483 SDValue Op2 = Op.getOperand(2); 9484 DebugLoc DL = Op.getDebugLoc(); 9485 SDValue CC; 9486 9487 if (Cond.getOpcode() == ISD::SETCC) { 9488 SDValue NewCond = LowerSETCC(Cond, DAG); 9489 if (NewCond.getNode()) 9490 Cond = NewCond; 9491 } 9492 9493 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 9494 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 9495 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 9496 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 9497 if (Cond.getOpcode() == X86ISD::SETCC && 9498 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 9499 isZero(Cond.getOperand(1).getOperand(1))) { 9500 SDValue Cmp = Cond.getOperand(1); 9501 9502 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 9503 9504 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 9505 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 9506 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 9507 9508 SDValue CmpOp0 = Cmp.getOperand(0); 9509 // Apply further optimizations for special cases 9510 // (select (x != 0), -1, 0) -> neg & sbb 9511 // (select (x == 0), 0, -1) -> neg & sbb 9512 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y)) 9513 if (YC->isNullValue() && 9514 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) { 9515 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32); 9516 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs, 9517 DAG.getConstant(0, CmpOp0.getValueType()), 9518 CmpOp0); 9519 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9520 DAG.getConstant(X86::COND_B, MVT::i8), 9521 SDValue(Neg.getNode(), 1)); 9522 return Res; 9523 } 9524 9525 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 9526 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 9527 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9528 9529 SDValue Res = // Res = 0 or -1. 9530 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9531 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 9532 9533 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 9534 Res = DAG.getNOT(DL, Res, Res.getValueType()); 9535 9536 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 9537 if (N2C == 0 || !N2C->isNullValue()) 9538 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 9539 return Res; 9540 } 9541 } 9542 9543 // Look past (and (setcc_carry (cmp ...)), 1). 9544 if (Cond.getOpcode() == ISD::AND && 9545 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 9546 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 9547 if (C && C->getAPIntValue() == 1) 9548 Cond = Cond.getOperand(0); 9549 } 9550 9551 // If condition flag is set by a X86ISD::CMP, then use it as the condition 9552 // setting operand in place of the X86ISD::SETCC. 9553 unsigned CondOpcode = Cond.getOpcode(); 9554 if (CondOpcode == X86ISD::SETCC || 9555 CondOpcode == X86ISD::SETCC_CARRY) { 9556 CC = Cond.getOperand(0); 9557 9558 SDValue Cmp = Cond.getOperand(1); 9559 unsigned Opc = Cmp.getOpcode(); 9560 MVT VT = Op.getValueType().getSimpleVT(); 9561 9562 bool IllegalFPCMov = false; 9563 if (VT.isFloatingPoint() && !VT.isVector() && 9564 !isScalarFPTypeInSSEReg(VT)) // FPStack? 9565 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 9566 9567 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 9568 Opc == X86ISD::BT) { // FIXME 9569 Cond = Cmp; 9570 addTest = false; 9571 } 9572 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 9573 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 9574 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 9575 Cond.getOperand(0).getValueType() != MVT::i8)) { 9576 SDValue LHS = Cond.getOperand(0); 9577 SDValue RHS = Cond.getOperand(1); 9578 unsigned X86Opcode; 9579 unsigned X86Cond; 9580 SDVTList VTs; 9581 switch (CondOpcode) { 9582 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 9583 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 9584 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 9585 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 9586 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 9587 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 9588 default: llvm_unreachable("unexpected overflowing operator"); 9589 } 9590 if (CondOpcode == ISD::UMULO) 9591 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 9592 MVT::i32); 9593 else 9594 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 9595 9596 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 9597 9598 if (CondOpcode == ISD::UMULO) 9599 Cond = X86Op.getValue(2); 9600 else 9601 Cond = X86Op.getValue(1); 9602 9603 CC = DAG.getConstant(X86Cond, MVT::i8); 9604 addTest = false; 9605 } 9606 9607 if (addTest) { 9608 // Look pass the truncate if the high bits are known zero. 9609 if (isTruncWithZeroHighBitsInput(Cond, DAG)) 9610 Cond = Cond.getOperand(0); 9611 9612 // We know the result of AND is compared against zero. Try to match 9613 // it to BT. 9614 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9615 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 9616 if (NewSetCC.getNode()) { 9617 CC = NewSetCC.getOperand(0); 9618 Cond = NewSetCC.getOperand(1); 9619 addTest = false; 9620 } 9621 } 9622 } 9623 9624 if (addTest) { 9625 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9626 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9627 } 9628 9629 // a < b ? -1 : 0 -> RES = ~setcc_carry 9630 // a < b ? 0 : -1 -> RES = setcc_carry 9631 // a >= b ? -1 : 0 -> RES = setcc_carry 9632 // a >= b ? 0 : -1 -> RES = ~setcc_carry 9633 if (Cond.getOpcode() == X86ISD::SUB) { 9634 Cond = ConvertCmpIfNecessary(Cond, DAG); 9635 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 9636 9637 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 9638 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 9639 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9640 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 9641 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 9642 return DAG.getNOT(DL, Res, Res.getValueType()); 9643 return Res; 9644 } 9645 } 9646 9647 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate 9648 // widen the cmov and push the truncate through. This avoids introducing a new 9649 // branch during isel and doesn't add any extensions. 9650 if (Op.getValueType() == MVT::i8 && 9651 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) { 9652 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0); 9653 if (T1.getValueType() == T2.getValueType() && 9654 // Blacklist CopyFromReg to avoid partial register stalls. 9655 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){ 9656 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue); 9657 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond); 9658 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov); 9659 } 9660 } 9661 9662 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 9663 // condition is true. 9664 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 9665 SDValue Ops[] = { Op2, Op1, CC, Cond }; 9666 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 9667} 9668 9669SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op, 9670 SelectionDAG &DAG) const { 9671 MVT VT = Op->getValueType(0).getSimpleVT(); 9672 SDValue In = Op->getOperand(0); 9673 MVT InVT = In.getValueType().getSimpleVT(); 9674 DebugLoc dl = Op->getDebugLoc(); 9675 9676 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) && 9677 (VT != MVT::v8i32 || InVT != MVT::v8i16)) 9678 return SDValue(); 9679 9680 if (Subtarget->hasInt256()) 9681 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In); 9682 9683 // Optimize vectors in AVX mode 9684 // Sign extend v8i16 to v8i32 and 9685 // v4i32 to v4i64 9686 // 9687 // Divide input vector into two parts 9688 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 9689 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 9690 // concat the vectors to original VT 9691 9692 unsigned NumElems = InVT.getVectorNumElements(); 9693 SDValue Undef = DAG.getUNDEF(InVT); 9694 9695 SmallVector<int,8> ShufMask1(NumElems, -1); 9696 for (unsigned i = 0; i != NumElems/2; ++i) 9697 ShufMask1[i] = i; 9698 9699 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]); 9700 9701 SmallVector<int,8> ShufMask2(NumElems, -1); 9702 for (unsigned i = 0; i != NumElems/2; ++i) 9703 ShufMask2[i] = i + NumElems/2; 9704 9705 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]); 9706 9707 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(), 9708 VT.getVectorNumElements()/2); 9709 9710 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 9711 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 9712 9713 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 9714} 9715 9716// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 9717// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 9718// from the AND / OR. 9719static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 9720 Opc = Op.getOpcode(); 9721 if (Opc != ISD::OR && Opc != ISD::AND) 9722 return false; 9723 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 9724 Op.getOperand(0).hasOneUse() && 9725 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 9726 Op.getOperand(1).hasOneUse()); 9727} 9728 9729// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 9730// 1 and that the SETCC node has a single use. 9731static bool isXor1OfSetCC(SDValue Op) { 9732 if (Op.getOpcode() != ISD::XOR) 9733 return false; 9734 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 9735 if (N1C && N1C->getAPIntValue() == 1) { 9736 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 9737 Op.getOperand(0).hasOneUse(); 9738 } 9739 return false; 9740} 9741 9742SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 9743 bool addTest = true; 9744 SDValue Chain = Op.getOperand(0); 9745 SDValue Cond = Op.getOperand(1); 9746 SDValue Dest = Op.getOperand(2); 9747 DebugLoc dl = Op.getDebugLoc(); 9748 SDValue CC; 9749 bool Inverted = false; 9750 9751 if (Cond.getOpcode() == ISD::SETCC) { 9752 // Check for setcc([su]{add,sub,mul}o == 0). 9753 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 9754 isa<ConstantSDNode>(Cond.getOperand(1)) && 9755 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 9756 Cond.getOperand(0).getResNo() == 1 && 9757 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 9758 Cond.getOperand(0).getOpcode() == ISD::UADDO || 9759 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 9760 Cond.getOperand(0).getOpcode() == ISD::USUBO || 9761 Cond.getOperand(0).getOpcode() == ISD::SMULO || 9762 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 9763 Inverted = true; 9764 Cond = Cond.getOperand(0); 9765 } else { 9766 SDValue NewCond = LowerSETCC(Cond, DAG); 9767 if (NewCond.getNode()) 9768 Cond = NewCond; 9769 } 9770 } 9771#if 0 9772 // FIXME: LowerXALUO doesn't handle these!! 9773 else if (Cond.getOpcode() == X86ISD::ADD || 9774 Cond.getOpcode() == X86ISD::SUB || 9775 Cond.getOpcode() == X86ISD::SMUL || 9776 Cond.getOpcode() == X86ISD::UMUL) 9777 Cond = LowerXALUO(Cond, DAG); 9778#endif 9779 9780 // Look pass (and (setcc_carry (cmp ...)), 1). 9781 if (Cond.getOpcode() == ISD::AND && 9782 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 9783 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 9784 if (C && C->getAPIntValue() == 1) 9785 Cond = Cond.getOperand(0); 9786 } 9787 9788 // If condition flag is set by a X86ISD::CMP, then use it as the condition 9789 // setting operand in place of the X86ISD::SETCC. 9790 unsigned CondOpcode = Cond.getOpcode(); 9791 if (CondOpcode == X86ISD::SETCC || 9792 CondOpcode == X86ISD::SETCC_CARRY) { 9793 CC = Cond.getOperand(0); 9794 9795 SDValue Cmp = Cond.getOperand(1); 9796 unsigned Opc = Cmp.getOpcode(); 9797 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 9798 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 9799 Cond = Cmp; 9800 addTest = false; 9801 } else { 9802 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 9803 default: break; 9804 case X86::COND_O: 9805 case X86::COND_B: 9806 // These can only come from an arithmetic instruction with overflow, 9807 // e.g. SADDO, UADDO. 9808 Cond = Cond.getNode()->getOperand(1); 9809 addTest = false; 9810 break; 9811 } 9812 } 9813 } 9814 CondOpcode = Cond.getOpcode(); 9815 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 9816 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 9817 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 9818 Cond.getOperand(0).getValueType() != MVT::i8)) { 9819 SDValue LHS = Cond.getOperand(0); 9820 SDValue RHS = Cond.getOperand(1); 9821 unsigned X86Opcode; 9822 unsigned X86Cond; 9823 SDVTList VTs; 9824 switch (CondOpcode) { 9825 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 9826 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 9827 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 9828 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 9829 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 9830 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 9831 default: llvm_unreachable("unexpected overflowing operator"); 9832 } 9833 if (Inverted) 9834 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 9835 if (CondOpcode == ISD::UMULO) 9836 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 9837 MVT::i32); 9838 else 9839 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 9840 9841 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 9842 9843 if (CondOpcode == ISD::UMULO) 9844 Cond = X86Op.getValue(2); 9845 else 9846 Cond = X86Op.getValue(1); 9847 9848 CC = DAG.getConstant(X86Cond, MVT::i8); 9849 addTest = false; 9850 } else { 9851 unsigned CondOpc; 9852 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 9853 SDValue Cmp = Cond.getOperand(0).getOperand(1); 9854 if (CondOpc == ISD::OR) { 9855 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 9856 // two branches instead of an explicit OR instruction with a 9857 // separate test. 9858 if (Cmp == Cond.getOperand(1).getOperand(1) && 9859 isX86LogicalCmp(Cmp)) { 9860 CC = Cond.getOperand(0).getOperand(0); 9861 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9862 Chain, Dest, CC, Cmp); 9863 CC = Cond.getOperand(1).getOperand(0); 9864 Cond = Cmp; 9865 addTest = false; 9866 } 9867 } else { // ISD::AND 9868 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 9869 // two branches instead of an explicit AND instruction with a 9870 // separate test. However, we only do this if this block doesn't 9871 // have a fall-through edge, because this requires an explicit 9872 // jmp when the condition is false. 9873 if (Cmp == Cond.getOperand(1).getOperand(1) && 9874 isX86LogicalCmp(Cmp) && 9875 Op.getNode()->hasOneUse()) { 9876 X86::CondCode CCode = 9877 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9878 CCode = X86::GetOppositeBranchCondition(CCode); 9879 CC = DAG.getConstant(CCode, MVT::i8); 9880 SDNode *User = *Op.getNode()->use_begin(); 9881 // Look for an unconditional branch following this conditional branch. 9882 // We need this because we need to reverse the successors in order 9883 // to implement FCMP_OEQ. 9884 if (User->getOpcode() == ISD::BR) { 9885 SDValue FalseBB = User->getOperand(1); 9886 SDNode *NewBR = 9887 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9888 assert(NewBR == User); 9889 (void)NewBR; 9890 Dest = FalseBB; 9891 9892 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9893 Chain, Dest, CC, Cmp); 9894 X86::CondCode CCode = 9895 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 9896 CCode = X86::GetOppositeBranchCondition(CCode); 9897 CC = DAG.getConstant(CCode, MVT::i8); 9898 Cond = Cmp; 9899 addTest = false; 9900 } 9901 } 9902 } 9903 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 9904 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 9905 // It should be transformed during dag combiner except when the condition 9906 // is set by a arithmetics with overflow node. 9907 X86::CondCode CCode = 9908 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9909 CCode = X86::GetOppositeBranchCondition(CCode); 9910 CC = DAG.getConstant(CCode, MVT::i8); 9911 Cond = Cond.getOperand(0).getOperand(1); 9912 addTest = false; 9913 } else if (Cond.getOpcode() == ISD::SETCC && 9914 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 9915 // For FCMP_OEQ, we can emit 9916 // two branches instead of an explicit AND instruction with a 9917 // separate test. However, we only do this if this block doesn't 9918 // have a fall-through edge, because this requires an explicit 9919 // jmp when the condition is false. 9920 if (Op.getNode()->hasOneUse()) { 9921 SDNode *User = *Op.getNode()->use_begin(); 9922 // Look for an unconditional branch following this conditional branch. 9923 // We need this because we need to reverse the successors in order 9924 // to implement FCMP_OEQ. 9925 if (User->getOpcode() == ISD::BR) { 9926 SDValue FalseBB = User->getOperand(1); 9927 SDNode *NewBR = 9928 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9929 assert(NewBR == User); 9930 (void)NewBR; 9931 Dest = FalseBB; 9932 9933 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9934 Cond.getOperand(0), Cond.getOperand(1)); 9935 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9936 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9937 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9938 Chain, Dest, CC, Cmp); 9939 CC = DAG.getConstant(X86::COND_P, MVT::i8); 9940 Cond = Cmp; 9941 addTest = false; 9942 } 9943 } 9944 } else if (Cond.getOpcode() == ISD::SETCC && 9945 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 9946 // For FCMP_UNE, we can emit 9947 // two branches instead of an explicit AND instruction with a 9948 // separate test. However, we only do this if this block doesn't 9949 // have a fall-through edge, because this requires an explicit 9950 // jmp when the condition is false. 9951 if (Op.getNode()->hasOneUse()) { 9952 SDNode *User = *Op.getNode()->use_begin(); 9953 // Look for an unconditional branch following this conditional branch. 9954 // We need this because we need to reverse the successors in order 9955 // to implement FCMP_UNE. 9956 if (User->getOpcode() == ISD::BR) { 9957 SDValue FalseBB = User->getOperand(1); 9958 SDNode *NewBR = 9959 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9960 assert(NewBR == User); 9961 (void)NewBR; 9962 9963 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9964 Cond.getOperand(0), Cond.getOperand(1)); 9965 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9966 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9967 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9968 Chain, Dest, CC, Cmp); 9969 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 9970 Cond = Cmp; 9971 addTest = false; 9972 Dest = FalseBB; 9973 } 9974 } 9975 } 9976 } 9977 9978 if (addTest) { 9979 // Look pass the truncate if the high bits are known zero. 9980 if (isTruncWithZeroHighBitsInput(Cond, DAG)) 9981 Cond = Cond.getOperand(0); 9982 9983 // We know the result of AND is compared against zero. Try to match 9984 // it to BT. 9985 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9986 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 9987 if (NewSetCC.getNode()) { 9988 CC = NewSetCC.getOperand(0); 9989 Cond = NewSetCC.getOperand(1); 9990 addTest = false; 9991 } 9992 } 9993 } 9994 9995 if (addTest) { 9996 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9997 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9998 } 9999 Cond = ConvertCmpIfNecessary(Cond, DAG); 10000 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 10001 Chain, Dest, CC, Cond); 10002} 10003 10004// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 10005// Calls to _alloca is needed to probe the stack when allocating more than 4k 10006// bytes in one go. Touching the stack at 4K increments is necessary to ensure 10007// that the guard pages used by the OS virtual memory manager are allocated in 10008// correct sequence. 10009SDValue 10010X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 10011 SelectionDAG &DAG) const { 10012 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 10013 getTargetMachine().Options.EnableSegmentedStacks) && 10014 "This should be used only on Windows targets or when segmented stacks " 10015 "are being used"); 10016 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 10017 DebugLoc dl = Op.getDebugLoc(); 10018 10019 // Get the inputs. 10020 SDValue Chain = Op.getOperand(0); 10021 SDValue Size = Op.getOperand(1); 10022 // FIXME: Ensure alignment here 10023 10024 bool Is64Bit = Subtarget->is64Bit(); 10025 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 10026 10027 if (getTargetMachine().Options.EnableSegmentedStacks) { 10028 MachineFunction &MF = DAG.getMachineFunction(); 10029 MachineRegisterInfo &MRI = MF.getRegInfo(); 10030 10031 if (Is64Bit) { 10032 // The 64 bit implementation of segmented stacks needs to clobber both r10 10033 // r11. This makes it impossible to use it along with nested parameters. 10034 const Function *F = MF.getFunction(); 10035 10036 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 10037 I != E; ++I) 10038 if (I->hasNestAttr()) 10039 report_fatal_error("Cannot use segmented stacks with functions that " 10040 "have nested arguments."); 10041 } 10042 10043 const TargetRegisterClass *AddrRegClass = 10044 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 10045 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 10046 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 10047 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 10048 DAG.getRegister(Vreg, SPTy)); 10049 SDValue Ops1[2] = { Value, Chain }; 10050 return DAG.getMergeValues(Ops1, 2, dl); 10051 } else { 10052 SDValue Flag; 10053 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 10054 10055 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 10056 Flag = Chain.getValue(1); 10057 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 10058 10059 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 10060 Flag = Chain.getValue(1); 10061 10062 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(), 10063 SPTy).getValue(1); 10064 10065 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 10066 return DAG.getMergeValues(Ops1, 2, dl); 10067 } 10068} 10069 10070SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 10071 MachineFunction &MF = DAG.getMachineFunction(); 10072 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 10073 10074 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 10075 DebugLoc DL = Op.getDebugLoc(); 10076 10077 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 10078 // vastart just stores the address of the VarArgsFrameIndex slot into the 10079 // memory location argument. 10080 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 10081 getPointerTy()); 10082 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 10083 MachinePointerInfo(SV), false, false, 0); 10084 } 10085 10086 // __va_list_tag: 10087 // gp_offset (0 - 6 * 8) 10088 // fp_offset (48 - 48 + 8 * 16) 10089 // overflow_arg_area (point to parameters coming in memory). 10090 // reg_save_area 10091 SmallVector<SDValue, 8> MemOps; 10092 SDValue FIN = Op.getOperand(1); 10093 // Store gp_offset 10094 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 10095 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 10096 MVT::i32), 10097 FIN, MachinePointerInfo(SV), false, false, 0); 10098 MemOps.push_back(Store); 10099 10100 // Store fp_offset 10101 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10102 FIN, DAG.getIntPtrConstant(4)); 10103 Store = DAG.getStore(Op.getOperand(0), DL, 10104 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 10105 MVT::i32), 10106 FIN, MachinePointerInfo(SV, 4), false, false, 0); 10107 MemOps.push_back(Store); 10108 10109 // Store ptr to overflow_arg_area 10110 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10111 FIN, DAG.getIntPtrConstant(4)); 10112 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 10113 getPointerTy()); 10114 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 10115 MachinePointerInfo(SV, 8), 10116 false, false, 0); 10117 MemOps.push_back(Store); 10118 10119 // Store ptr to reg_save_area. 10120 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10121 FIN, DAG.getIntPtrConstant(8)); 10122 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 10123 getPointerTy()); 10124 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 10125 MachinePointerInfo(SV, 16), false, false, 0); 10126 MemOps.push_back(Store); 10127 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 10128 &MemOps[0], MemOps.size()); 10129} 10130 10131SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 10132 assert(Subtarget->is64Bit() && 10133 "LowerVAARG only handles 64-bit va_arg!"); 10134 assert((Subtarget->isTargetLinux() || 10135 Subtarget->isTargetDarwin()) && 10136 "Unhandled target in LowerVAARG"); 10137 assert(Op.getNode()->getNumOperands() == 4); 10138 SDValue Chain = Op.getOperand(0); 10139 SDValue SrcPtr = Op.getOperand(1); 10140 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 10141 unsigned Align = Op.getConstantOperandVal(3); 10142 DebugLoc dl = Op.getDebugLoc(); 10143 10144 EVT ArgVT = Op.getNode()->getValueType(0); 10145 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 10146 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy); 10147 uint8_t ArgMode; 10148 10149 // Decide which area this value should be read from. 10150 // TODO: Implement the AMD64 ABI in its entirety. This simple 10151 // selection mechanism works only for the basic types. 10152 if (ArgVT == MVT::f80) { 10153 llvm_unreachable("va_arg for f80 not yet implemented"); 10154 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 10155 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 10156 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 10157 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 10158 } else { 10159 llvm_unreachable("Unhandled argument type in LowerVAARG"); 10160 } 10161 10162 if (ArgMode == 2) { 10163 // Sanity Check: Make sure using fp_offset makes sense. 10164 assert(!getTargetMachine().Options.UseSoftFloat && 10165 !(DAG.getMachineFunction() 10166 .getFunction()->getAttributes() 10167 .hasAttribute(AttributeSet::FunctionIndex, 10168 Attribute::NoImplicitFloat)) && 10169 Subtarget->hasSSE1()); 10170 } 10171 10172 // Insert VAARG_64 node into the DAG 10173 // VAARG_64 returns two values: Variable Argument Address, Chain 10174 SmallVector<SDValue, 11> InstOps; 10175 InstOps.push_back(Chain); 10176 InstOps.push_back(SrcPtr); 10177 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 10178 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 10179 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 10180 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 10181 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 10182 VTs, &InstOps[0], InstOps.size(), 10183 MVT::i64, 10184 MachinePointerInfo(SV), 10185 /*Align=*/0, 10186 /*Volatile=*/false, 10187 /*ReadMem=*/true, 10188 /*WriteMem=*/true); 10189 Chain = VAARG.getValue(1); 10190 10191 // Load the next argument and return it 10192 return DAG.getLoad(ArgVT, dl, 10193 Chain, 10194 VAARG, 10195 MachinePointerInfo(), 10196 false, false, false, 0); 10197} 10198 10199static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget, 10200 SelectionDAG &DAG) { 10201 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 10202 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 10203 SDValue Chain = Op.getOperand(0); 10204 SDValue DstPtr = Op.getOperand(1); 10205 SDValue SrcPtr = Op.getOperand(2); 10206 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 10207 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 10208 DebugLoc DL = Op.getDebugLoc(); 10209 10210 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 10211 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 10212 false, 10213 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 10214} 10215 10216// getTargetVShiftNode - Handle vector element shifts where the shift amount 10217// may or may not be a constant. Takes immediate version of shift as input. 10218static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 10219 SDValue SrcOp, SDValue ShAmt, 10220 SelectionDAG &DAG) { 10221 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 10222 10223 if (isa<ConstantSDNode>(ShAmt)) { 10224 // Constant may be a TargetConstant. Use a regular constant. 10225 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 10226 switch (Opc) { 10227 default: llvm_unreachable("Unknown target vector shift node"); 10228 case X86ISD::VSHLI: 10229 case X86ISD::VSRLI: 10230 case X86ISD::VSRAI: 10231 return DAG.getNode(Opc, dl, VT, SrcOp, 10232 DAG.getConstant(ShiftAmt, MVT::i32)); 10233 } 10234 } 10235 10236 // Change opcode to non-immediate version 10237 switch (Opc) { 10238 default: llvm_unreachable("Unknown target vector shift node"); 10239 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 10240 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 10241 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 10242 } 10243 10244 // Need to build a vector containing shift amount 10245 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 10246 SDValue ShOps[4]; 10247 ShOps[0] = ShAmt; 10248 ShOps[1] = DAG.getConstant(0, MVT::i32); 10249 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32); 10250 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 10251 10252 // The return type has to be a 128-bit type with the same element 10253 // type as the input type. 10254 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10255 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits()); 10256 10257 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt); 10258 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 10259} 10260 10261static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 10262 DebugLoc dl = Op.getDebugLoc(); 10263 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10264 switch (IntNo) { 10265 default: return SDValue(); // Don't custom lower most intrinsics. 10266 // Comparison intrinsics. 10267 case Intrinsic::x86_sse_comieq_ss: 10268 case Intrinsic::x86_sse_comilt_ss: 10269 case Intrinsic::x86_sse_comile_ss: 10270 case Intrinsic::x86_sse_comigt_ss: 10271 case Intrinsic::x86_sse_comige_ss: 10272 case Intrinsic::x86_sse_comineq_ss: 10273 case Intrinsic::x86_sse_ucomieq_ss: 10274 case Intrinsic::x86_sse_ucomilt_ss: 10275 case Intrinsic::x86_sse_ucomile_ss: 10276 case Intrinsic::x86_sse_ucomigt_ss: 10277 case Intrinsic::x86_sse_ucomige_ss: 10278 case Intrinsic::x86_sse_ucomineq_ss: 10279 case Intrinsic::x86_sse2_comieq_sd: 10280 case Intrinsic::x86_sse2_comilt_sd: 10281 case Intrinsic::x86_sse2_comile_sd: 10282 case Intrinsic::x86_sse2_comigt_sd: 10283 case Intrinsic::x86_sse2_comige_sd: 10284 case Intrinsic::x86_sse2_comineq_sd: 10285 case Intrinsic::x86_sse2_ucomieq_sd: 10286 case Intrinsic::x86_sse2_ucomilt_sd: 10287 case Intrinsic::x86_sse2_ucomile_sd: 10288 case Intrinsic::x86_sse2_ucomigt_sd: 10289 case Intrinsic::x86_sse2_ucomige_sd: 10290 case Intrinsic::x86_sse2_ucomineq_sd: { 10291 unsigned Opc; 10292 ISD::CondCode CC; 10293 switch (IntNo) { 10294 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10295 case Intrinsic::x86_sse_comieq_ss: 10296 case Intrinsic::x86_sse2_comieq_sd: 10297 Opc = X86ISD::COMI; 10298 CC = ISD::SETEQ; 10299 break; 10300 case Intrinsic::x86_sse_comilt_ss: 10301 case Intrinsic::x86_sse2_comilt_sd: 10302 Opc = X86ISD::COMI; 10303 CC = ISD::SETLT; 10304 break; 10305 case Intrinsic::x86_sse_comile_ss: 10306 case Intrinsic::x86_sse2_comile_sd: 10307 Opc = X86ISD::COMI; 10308 CC = ISD::SETLE; 10309 break; 10310 case Intrinsic::x86_sse_comigt_ss: 10311 case Intrinsic::x86_sse2_comigt_sd: 10312 Opc = X86ISD::COMI; 10313 CC = ISD::SETGT; 10314 break; 10315 case Intrinsic::x86_sse_comige_ss: 10316 case Intrinsic::x86_sse2_comige_sd: 10317 Opc = X86ISD::COMI; 10318 CC = ISD::SETGE; 10319 break; 10320 case Intrinsic::x86_sse_comineq_ss: 10321 case Intrinsic::x86_sse2_comineq_sd: 10322 Opc = X86ISD::COMI; 10323 CC = ISD::SETNE; 10324 break; 10325 case Intrinsic::x86_sse_ucomieq_ss: 10326 case Intrinsic::x86_sse2_ucomieq_sd: 10327 Opc = X86ISD::UCOMI; 10328 CC = ISD::SETEQ; 10329 break; 10330 case Intrinsic::x86_sse_ucomilt_ss: 10331 case Intrinsic::x86_sse2_ucomilt_sd: 10332 Opc = X86ISD::UCOMI; 10333 CC = ISD::SETLT; 10334 break; 10335 case Intrinsic::x86_sse_ucomile_ss: 10336 case Intrinsic::x86_sse2_ucomile_sd: 10337 Opc = X86ISD::UCOMI; 10338 CC = ISD::SETLE; 10339 break; 10340 case Intrinsic::x86_sse_ucomigt_ss: 10341 case Intrinsic::x86_sse2_ucomigt_sd: 10342 Opc = X86ISD::UCOMI; 10343 CC = ISD::SETGT; 10344 break; 10345 case Intrinsic::x86_sse_ucomige_ss: 10346 case Intrinsic::x86_sse2_ucomige_sd: 10347 Opc = X86ISD::UCOMI; 10348 CC = ISD::SETGE; 10349 break; 10350 case Intrinsic::x86_sse_ucomineq_ss: 10351 case Intrinsic::x86_sse2_ucomineq_sd: 10352 Opc = X86ISD::UCOMI; 10353 CC = ISD::SETNE; 10354 break; 10355 } 10356 10357 SDValue LHS = Op.getOperand(1); 10358 SDValue RHS = Op.getOperand(2); 10359 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 10360 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 10361 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 10362 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 10363 DAG.getConstant(X86CC, MVT::i8), Cond); 10364 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10365 } 10366 10367 // Arithmetic intrinsics. 10368 case Intrinsic::x86_sse2_pmulu_dq: 10369 case Intrinsic::x86_avx2_pmulu_dq: 10370 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 10371 Op.getOperand(1), Op.getOperand(2)); 10372 10373 // SSE2/AVX2 sub with unsigned saturation intrinsics 10374 case Intrinsic::x86_sse2_psubus_b: 10375 case Intrinsic::x86_sse2_psubus_w: 10376 case Intrinsic::x86_avx2_psubus_b: 10377 case Intrinsic::x86_avx2_psubus_w: 10378 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(), 10379 Op.getOperand(1), Op.getOperand(2)); 10380 10381 // SSE3/AVX horizontal add/sub intrinsics 10382 case Intrinsic::x86_sse3_hadd_ps: 10383 case Intrinsic::x86_sse3_hadd_pd: 10384 case Intrinsic::x86_avx_hadd_ps_256: 10385 case Intrinsic::x86_avx_hadd_pd_256: 10386 case Intrinsic::x86_sse3_hsub_ps: 10387 case Intrinsic::x86_sse3_hsub_pd: 10388 case Intrinsic::x86_avx_hsub_ps_256: 10389 case Intrinsic::x86_avx_hsub_pd_256: 10390 case Intrinsic::x86_ssse3_phadd_w_128: 10391 case Intrinsic::x86_ssse3_phadd_d_128: 10392 case Intrinsic::x86_avx2_phadd_w: 10393 case Intrinsic::x86_avx2_phadd_d: 10394 case Intrinsic::x86_ssse3_phsub_w_128: 10395 case Intrinsic::x86_ssse3_phsub_d_128: 10396 case Intrinsic::x86_avx2_phsub_w: 10397 case Intrinsic::x86_avx2_phsub_d: { 10398 unsigned Opcode; 10399 switch (IntNo) { 10400 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10401 case Intrinsic::x86_sse3_hadd_ps: 10402 case Intrinsic::x86_sse3_hadd_pd: 10403 case Intrinsic::x86_avx_hadd_ps_256: 10404 case Intrinsic::x86_avx_hadd_pd_256: 10405 Opcode = X86ISD::FHADD; 10406 break; 10407 case Intrinsic::x86_sse3_hsub_ps: 10408 case Intrinsic::x86_sse3_hsub_pd: 10409 case Intrinsic::x86_avx_hsub_ps_256: 10410 case Intrinsic::x86_avx_hsub_pd_256: 10411 Opcode = X86ISD::FHSUB; 10412 break; 10413 case Intrinsic::x86_ssse3_phadd_w_128: 10414 case Intrinsic::x86_ssse3_phadd_d_128: 10415 case Intrinsic::x86_avx2_phadd_w: 10416 case Intrinsic::x86_avx2_phadd_d: 10417 Opcode = X86ISD::HADD; 10418 break; 10419 case Intrinsic::x86_ssse3_phsub_w_128: 10420 case Intrinsic::x86_ssse3_phsub_d_128: 10421 case Intrinsic::x86_avx2_phsub_w: 10422 case Intrinsic::x86_avx2_phsub_d: 10423 Opcode = X86ISD::HSUB; 10424 break; 10425 } 10426 return DAG.getNode(Opcode, dl, Op.getValueType(), 10427 Op.getOperand(1), Op.getOperand(2)); 10428 } 10429 10430 // SSE2/SSE41/AVX2 integer max/min intrinsics. 10431 case Intrinsic::x86_sse2_pmaxu_b: 10432 case Intrinsic::x86_sse41_pmaxuw: 10433 case Intrinsic::x86_sse41_pmaxud: 10434 case Intrinsic::x86_avx2_pmaxu_b: 10435 case Intrinsic::x86_avx2_pmaxu_w: 10436 case Intrinsic::x86_avx2_pmaxu_d: 10437 case Intrinsic::x86_sse2_pminu_b: 10438 case Intrinsic::x86_sse41_pminuw: 10439 case Intrinsic::x86_sse41_pminud: 10440 case Intrinsic::x86_avx2_pminu_b: 10441 case Intrinsic::x86_avx2_pminu_w: 10442 case Intrinsic::x86_avx2_pminu_d: 10443 case Intrinsic::x86_sse41_pmaxsb: 10444 case Intrinsic::x86_sse2_pmaxs_w: 10445 case Intrinsic::x86_sse41_pmaxsd: 10446 case Intrinsic::x86_avx2_pmaxs_b: 10447 case Intrinsic::x86_avx2_pmaxs_w: 10448 case Intrinsic::x86_avx2_pmaxs_d: 10449 case Intrinsic::x86_sse41_pminsb: 10450 case Intrinsic::x86_sse2_pmins_w: 10451 case Intrinsic::x86_sse41_pminsd: 10452 case Intrinsic::x86_avx2_pmins_b: 10453 case Intrinsic::x86_avx2_pmins_w: 10454 case Intrinsic::x86_avx2_pmins_d: { 10455 unsigned Opcode; 10456 switch (IntNo) { 10457 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10458 case Intrinsic::x86_sse2_pmaxu_b: 10459 case Intrinsic::x86_sse41_pmaxuw: 10460 case Intrinsic::x86_sse41_pmaxud: 10461 case Intrinsic::x86_avx2_pmaxu_b: 10462 case Intrinsic::x86_avx2_pmaxu_w: 10463 case Intrinsic::x86_avx2_pmaxu_d: 10464 Opcode = X86ISD::UMAX; 10465 break; 10466 case Intrinsic::x86_sse2_pminu_b: 10467 case Intrinsic::x86_sse41_pminuw: 10468 case Intrinsic::x86_sse41_pminud: 10469 case Intrinsic::x86_avx2_pminu_b: 10470 case Intrinsic::x86_avx2_pminu_w: 10471 case Intrinsic::x86_avx2_pminu_d: 10472 Opcode = X86ISD::UMIN; 10473 break; 10474 case Intrinsic::x86_sse41_pmaxsb: 10475 case Intrinsic::x86_sse2_pmaxs_w: 10476 case Intrinsic::x86_sse41_pmaxsd: 10477 case Intrinsic::x86_avx2_pmaxs_b: 10478 case Intrinsic::x86_avx2_pmaxs_w: 10479 case Intrinsic::x86_avx2_pmaxs_d: 10480 Opcode = X86ISD::SMAX; 10481 break; 10482 case Intrinsic::x86_sse41_pminsb: 10483 case Intrinsic::x86_sse2_pmins_w: 10484 case Intrinsic::x86_sse41_pminsd: 10485 case Intrinsic::x86_avx2_pmins_b: 10486 case Intrinsic::x86_avx2_pmins_w: 10487 case Intrinsic::x86_avx2_pmins_d: 10488 Opcode = X86ISD::SMIN; 10489 break; 10490 } 10491 return DAG.getNode(Opcode, dl, Op.getValueType(), 10492 Op.getOperand(1), Op.getOperand(2)); 10493 } 10494 10495 // SSE/SSE2/AVX floating point max/min intrinsics. 10496 case Intrinsic::x86_sse_max_ps: 10497 case Intrinsic::x86_sse2_max_pd: 10498 case Intrinsic::x86_avx_max_ps_256: 10499 case Intrinsic::x86_avx_max_pd_256: 10500 case Intrinsic::x86_sse_min_ps: 10501 case Intrinsic::x86_sse2_min_pd: 10502 case Intrinsic::x86_avx_min_ps_256: 10503 case Intrinsic::x86_avx_min_pd_256: { 10504 unsigned Opcode; 10505 switch (IntNo) { 10506 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10507 case Intrinsic::x86_sse_max_ps: 10508 case Intrinsic::x86_sse2_max_pd: 10509 case Intrinsic::x86_avx_max_ps_256: 10510 case Intrinsic::x86_avx_max_pd_256: 10511 Opcode = X86ISD::FMAX; 10512 break; 10513 case Intrinsic::x86_sse_min_ps: 10514 case Intrinsic::x86_sse2_min_pd: 10515 case Intrinsic::x86_avx_min_ps_256: 10516 case Intrinsic::x86_avx_min_pd_256: 10517 Opcode = X86ISD::FMIN; 10518 break; 10519 } 10520 return DAG.getNode(Opcode, dl, Op.getValueType(), 10521 Op.getOperand(1), Op.getOperand(2)); 10522 } 10523 10524 // AVX2 variable shift intrinsics 10525 case Intrinsic::x86_avx2_psllv_d: 10526 case Intrinsic::x86_avx2_psllv_q: 10527 case Intrinsic::x86_avx2_psllv_d_256: 10528 case Intrinsic::x86_avx2_psllv_q_256: 10529 case Intrinsic::x86_avx2_psrlv_d: 10530 case Intrinsic::x86_avx2_psrlv_q: 10531 case Intrinsic::x86_avx2_psrlv_d_256: 10532 case Intrinsic::x86_avx2_psrlv_q_256: 10533 case Intrinsic::x86_avx2_psrav_d: 10534 case Intrinsic::x86_avx2_psrav_d_256: { 10535 unsigned Opcode; 10536 switch (IntNo) { 10537 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10538 case Intrinsic::x86_avx2_psllv_d: 10539 case Intrinsic::x86_avx2_psllv_q: 10540 case Intrinsic::x86_avx2_psllv_d_256: 10541 case Intrinsic::x86_avx2_psllv_q_256: 10542 Opcode = ISD::SHL; 10543 break; 10544 case Intrinsic::x86_avx2_psrlv_d: 10545 case Intrinsic::x86_avx2_psrlv_q: 10546 case Intrinsic::x86_avx2_psrlv_d_256: 10547 case Intrinsic::x86_avx2_psrlv_q_256: 10548 Opcode = ISD::SRL; 10549 break; 10550 case Intrinsic::x86_avx2_psrav_d: 10551 case Intrinsic::x86_avx2_psrav_d_256: 10552 Opcode = ISD::SRA; 10553 break; 10554 } 10555 return DAG.getNode(Opcode, dl, Op.getValueType(), 10556 Op.getOperand(1), Op.getOperand(2)); 10557 } 10558 10559 case Intrinsic::x86_ssse3_pshuf_b_128: 10560 case Intrinsic::x86_avx2_pshuf_b: 10561 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 10562 Op.getOperand(1), Op.getOperand(2)); 10563 10564 case Intrinsic::x86_ssse3_psign_b_128: 10565 case Intrinsic::x86_ssse3_psign_w_128: 10566 case Intrinsic::x86_ssse3_psign_d_128: 10567 case Intrinsic::x86_avx2_psign_b: 10568 case Intrinsic::x86_avx2_psign_w: 10569 case Intrinsic::x86_avx2_psign_d: 10570 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 10571 Op.getOperand(1), Op.getOperand(2)); 10572 10573 case Intrinsic::x86_sse41_insertps: 10574 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 10575 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 10576 10577 case Intrinsic::x86_avx_vperm2f128_ps_256: 10578 case Intrinsic::x86_avx_vperm2f128_pd_256: 10579 case Intrinsic::x86_avx_vperm2f128_si_256: 10580 case Intrinsic::x86_avx2_vperm2i128: 10581 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 10582 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 10583 10584 case Intrinsic::x86_avx2_permd: 10585 case Intrinsic::x86_avx2_permps: 10586 // Operands intentionally swapped. Mask is last operand to intrinsic, 10587 // but second operand for node/intruction. 10588 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 10589 Op.getOperand(2), Op.getOperand(1)); 10590 10591 case Intrinsic::x86_sse_sqrt_ps: 10592 case Intrinsic::x86_sse2_sqrt_pd: 10593 case Intrinsic::x86_avx_sqrt_ps_256: 10594 case Intrinsic::x86_avx_sqrt_pd_256: 10595 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1)); 10596 10597 // ptest and testp intrinsics. The intrinsic these come from are designed to 10598 // return an integer value, not just an instruction so lower it to the ptest 10599 // or testp pattern and a setcc for the result. 10600 case Intrinsic::x86_sse41_ptestz: 10601 case Intrinsic::x86_sse41_ptestc: 10602 case Intrinsic::x86_sse41_ptestnzc: 10603 case Intrinsic::x86_avx_ptestz_256: 10604 case Intrinsic::x86_avx_ptestc_256: 10605 case Intrinsic::x86_avx_ptestnzc_256: 10606 case Intrinsic::x86_avx_vtestz_ps: 10607 case Intrinsic::x86_avx_vtestc_ps: 10608 case Intrinsic::x86_avx_vtestnzc_ps: 10609 case Intrinsic::x86_avx_vtestz_pd: 10610 case Intrinsic::x86_avx_vtestc_pd: 10611 case Intrinsic::x86_avx_vtestnzc_pd: 10612 case Intrinsic::x86_avx_vtestz_ps_256: 10613 case Intrinsic::x86_avx_vtestc_ps_256: 10614 case Intrinsic::x86_avx_vtestnzc_ps_256: 10615 case Intrinsic::x86_avx_vtestz_pd_256: 10616 case Intrinsic::x86_avx_vtestc_pd_256: 10617 case Intrinsic::x86_avx_vtestnzc_pd_256: { 10618 bool IsTestPacked = false; 10619 unsigned X86CC; 10620 switch (IntNo) { 10621 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 10622 case Intrinsic::x86_avx_vtestz_ps: 10623 case Intrinsic::x86_avx_vtestz_pd: 10624 case Intrinsic::x86_avx_vtestz_ps_256: 10625 case Intrinsic::x86_avx_vtestz_pd_256: 10626 IsTestPacked = true; // Fallthrough 10627 case Intrinsic::x86_sse41_ptestz: 10628 case Intrinsic::x86_avx_ptestz_256: 10629 // ZF = 1 10630 X86CC = X86::COND_E; 10631 break; 10632 case Intrinsic::x86_avx_vtestc_ps: 10633 case Intrinsic::x86_avx_vtestc_pd: 10634 case Intrinsic::x86_avx_vtestc_ps_256: 10635 case Intrinsic::x86_avx_vtestc_pd_256: 10636 IsTestPacked = true; // Fallthrough 10637 case Intrinsic::x86_sse41_ptestc: 10638 case Intrinsic::x86_avx_ptestc_256: 10639 // CF = 1 10640 X86CC = X86::COND_B; 10641 break; 10642 case Intrinsic::x86_avx_vtestnzc_ps: 10643 case Intrinsic::x86_avx_vtestnzc_pd: 10644 case Intrinsic::x86_avx_vtestnzc_ps_256: 10645 case Intrinsic::x86_avx_vtestnzc_pd_256: 10646 IsTestPacked = true; // Fallthrough 10647 case Intrinsic::x86_sse41_ptestnzc: 10648 case Intrinsic::x86_avx_ptestnzc_256: 10649 // ZF and CF = 0 10650 X86CC = X86::COND_A; 10651 break; 10652 } 10653 10654 SDValue LHS = Op.getOperand(1); 10655 SDValue RHS = Op.getOperand(2); 10656 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 10657 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 10658 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 10659 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 10660 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10661 } 10662 10663 // SSE/AVX shift intrinsics 10664 case Intrinsic::x86_sse2_psll_w: 10665 case Intrinsic::x86_sse2_psll_d: 10666 case Intrinsic::x86_sse2_psll_q: 10667 case Intrinsic::x86_avx2_psll_w: 10668 case Intrinsic::x86_avx2_psll_d: 10669 case Intrinsic::x86_avx2_psll_q: 10670 case Intrinsic::x86_sse2_psrl_w: 10671 case Intrinsic::x86_sse2_psrl_d: 10672 case Intrinsic::x86_sse2_psrl_q: 10673 case Intrinsic::x86_avx2_psrl_w: 10674 case Intrinsic::x86_avx2_psrl_d: 10675 case Intrinsic::x86_avx2_psrl_q: 10676 case Intrinsic::x86_sse2_psra_w: 10677 case Intrinsic::x86_sse2_psra_d: 10678 case Intrinsic::x86_avx2_psra_w: 10679 case Intrinsic::x86_avx2_psra_d: { 10680 unsigned Opcode; 10681 switch (IntNo) { 10682 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10683 case Intrinsic::x86_sse2_psll_w: 10684 case Intrinsic::x86_sse2_psll_d: 10685 case Intrinsic::x86_sse2_psll_q: 10686 case Intrinsic::x86_avx2_psll_w: 10687 case Intrinsic::x86_avx2_psll_d: 10688 case Intrinsic::x86_avx2_psll_q: 10689 Opcode = X86ISD::VSHL; 10690 break; 10691 case Intrinsic::x86_sse2_psrl_w: 10692 case Intrinsic::x86_sse2_psrl_d: 10693 case Intrinsic::x86_sse2_psrl_q: 10694 case Intrinsic::x86_avx2_psrl_w: 10695 case Intrinsic::x86_avx2_psrl_d: 10696 case Intrinsic::x86_avx2_psrl_q: 10697 Opcode = X86ISD::VSRL; 10698 break; 10699 case Intrinsic::x86_sse2_psra_w: 10700 case Intrinsic::x86_sse2_psra_d: 10701 case Intrinsic::x86_avx2_psra_w: 10702 case Intrinsic::x86_avx2_psra_d: 10703 Opcode = X86ISD::VSRA; 10704 break; 10705 } 10706 return DAG.getNode(Opcode, dl, Op.getValueType(), 10707 Op.getOperand(1), Op.getOperand(2)); 10708 } 10709 10710 // SSE/AVX immediate shift intrinsics 10711 case Intrinsic::x86_sse2_pslli_w: 10712 case Intrinsic::x86_sse2_pslli_d: 10713 case Intrinsic::x86_sse2_pslli_q: 10714 case Intrinsic::x86_avx2_pslli_w: 10715 case Intrinsic::x86_avx2_pslli_d: 10716 case Intrinsic::x86_avx2_pslli_q: 10717 case Intrinsic::x86_sse2_psrli_w: 10718 case Intrinsic::x86_sse2_psrli_d: 10719 case Intrinsic::x86_sse2_psrli_q: 10720 case Intrinsic::x86_avx2_psrli_w: 10721 case Intrinsic::x86_avx2_psrli_d: 10722 case Intrinsic::x86_avx2_psrli_q: 10723 case Intrinsic::x86_sse2_psrai_w: 10724 case Intrinsic::x86_sse2_psrai_d: 10725 case Intrinsic::x86_avx2_psrai_w: 10726 case Intrinsic::x86_avx2_psrai_d: { 10727 unsigned Opcode; 10728 switch (IntNo) { 10729 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10730 case Intrinsic::x86_sse2_pslli_w: 10731 case Intrinsic::x86_sse2_pslli_d: 10732 case Intrinsic::x86_sse2_pslli_q: 10733 case Intrinsic::x86_avx2_pslli_w: 10734 case Intrinsic::x86_avx2_pslli_d: 10735 case Intrinsic::x86_avx2_pslli_q: 10736 Opcode = X86ISD::VSHLI; 10737 break; 10738 case Intrinsic::x86_sse2_psrli_w: 10739 case Intrinsic::x86_sse2_psrli_d: 10740 case Intrinsic::x86_sse2_psrli_q: 10741 case Intrinsic::x86_avx2_psrli_w: 10742 case Intrinsic::x86_avx2_psrli_d: 10743 case Intrinsic::x86_avx2_psrli_q: 10744 Opcode = X86ISD::VSRLI; 10745 break; 10746 case Intrinsic::x86_sse2_psrai_w: 10747 case Intrinsic::x86_sse2_psrai_d: 10748 case Intrinsic::x86_avx2_psrai_w: 10749 case Intrinsic::x86_avx2_psrai_d: 10750 Opcode = X86ISD::VSRAI; 10751 break; 10752 } 10753 return getTargetVShiftNode(Opcode, dl, Op.getValueType(), 10754 Op.getOperand(1), Op.getOperand(2), DAG); 10755 } 10756 10757 case Intrinsic::x86_sse42_pcmpistria128: 10758 case Intrinsic::x86_sse42_pcmpestria128: 10759 case Intrinsic::x86_sse42_pcmpistric128: 10760 case Intrinsic::x86_sse42_pcmpestric128: 10761 case Intrinsic::x86_sse42_pcmpistrio128: 10762 case Intrinsic::x86_sse42_pcmpestrio128: 10763 case Intrinsic::x86_sse42_pcmpistris128: 10764 case Intrinsic::x86_sse42_pcmpestris128: 10765 case Intrinsic::x86_sse42_pcmpistriz128: 10766 case Intrinsic::x86_sse42_pcmpestriz128: { 10767 unsigned Opcode; 10768 unsigned X86CC; 10769 switch (IntNo) { 10770 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10771 case Intrinsic::x86_sse42_pcmpistria128: 10772 Opcode = X86ISD::PCMPISTRI; 10773 X86CC = X86::COND_A; 10774 break; 10775 case Intrinsic::x86_sse42_pcmpestria128: 10776 Opcode = X86ISD::PCMPESTRI; 10777 X86CC = X86::COND_A; 10778 break; 10779 case Intrinsic::x86_sse42_pcmpistric128: 10780 Opcode = X86ISD::PCMPISTRI; 10781 X86CC = X86::COND_B; 10782 break; 10783 case Intrinsic::x86_sse42_pcmpestric128: 10784 Opcode = X86ISD::PCMPESTRI; 10785 X86CC = X86::COND_B; 10786 break; 10787 case Intrinsic::x86_sse42_pcmpistrio128: 10788 Opcode = X86ISD::PCMPISTRI; 10789 X86CC = X86::COND_O; 10790 break; 10791 case Intrinsic::x86_sse42_pcmpestrio128: 10792 Opcode = X86ISD::PCMPESTRI; 10793 X86CC = X86::COND_O; 10794 break; 10795 case Intrinsic::x86_sse42_pcmpistris128: 10796 Opcode = X86ISD::PCMPISTRI; 10797 X86CC = X86::COND_S; 10798 break; 10799 case Intrinsic::x86_sse42_pcmpestris128: 10800 Opcode = X86ISD::PCMPESTRI; 10801 X86CC = X86::COND_S; 10802 break; 10803 case Intrinsic::x86_sse42_pcmpistriz128: 10804 Opcode = X86ISD::PCMPISTRI; 10805 X86CC = X86::COND_E; 10806 break; 10807 case Intrinsic::x86_sse42_pcmpestriz128: 10808 Opcode = X86ISD::PCMPESTRI; 10809 X86CC = X86::COND_E; 10810 break; 10811 } 10812 SmallVector<SDValue, 5> NewOps; 10813 NewOps.append(Op->op_begin()+1, Op->op_end()); 10814 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 10815 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); 10816 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 10817 DAG.getConstant(X86CC, MVT::i8), 10818 SDValue(PCMP.getNode(), 1)); 10819 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10820 } 10821 10822 case Intrinsic::x86_sse42_pcmpistri128: 10823 case Intrinsic::x86_sse42_pcmpestri128: { 10824 unsigned Opcode; 10825 if (IntNo == Intrinsic::x86_sse42_pcmpistri128) 10826 Opcode = X86ISD::PCMPISTRI; 10827 else 10828 Opcode = X86ISD::PCMPESTRI; 10829 10830 SmallVector<SDValue, 5> NewOps; 10831 NewOps.append(Op->op_begin()+1, Op->op_end()); 10832 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 10833 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); 10834 } 10835 case Intrinsic::x86_fma_vfmadd_ps: 10836 case Intrinsic::x86_fma_vfmadd_pd: 10837 case Intrinsic::x86_fma_vfmsub_ps: 10838 case Intrinsic::x86_fma_vfmsub_pd: 10839 case Intrinsic::x86_fma_vfnmadd_ps: 10840 case Intrinsic::x86_fma_vfnmadd_pd: 10841 case Intrinsic::x86_fma_vfnmsub_ps: 10842 case Intrinsic::x86_fma_vfnmsub_pd: 10843 case Intrinsic::x86_fma_vfmaddsub_ps: 10844 case Intrinsic::x86_fma_vfmaddsub_pd: 10845 case Intrinsic::x86_fma_vfmsubadd_ps: 10846 case Intrinsic::x86_fma_vfmsubadd_pd: 10847 case Intrinsic::x86_fma_vfmadd_ps_256: 10848 case Intrinsic::x86_fma_vfmadd_pd_256: 10849 case Intrinsic::x86_fma_vfmsub_ps_256: 10850 case Intrinsic::x86_fma_vfmsub_pd_256: 10851 case Intrinsic::x86_fma_vfnmadd_ps_256: 10852 case Intrinsic::x86_fma_vfnmadd_pd_256: 10853 case Intrinsic::x86_fma_vfnmsub_ps_256: 10854 case Intrinsic::x86_fma_vfnmsub_pd_256: 10855 case Intrinsic::x86_fma_vfmaddsub_ps_256: 10856 case Intrinsic::x86_fma_vfmaddsub_pd_256: 10857 case Intrinsic::x86_fma_vfmsubadd_ps_256: 10858 case Intrinsic::x86_fma_vfmsubadd_pd_256: { 10859 unsigned Opc; 10860 switch (IntNo) { 10861 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10862 case Intrinsic::x86_fma_vfmadd_ps: 10863 case Intrinsic::x86_fma_vfmadd_pd: 10864 case Intrinsic::x86_fma_vfmadd_ps_256: 10865 case Intrinsic::x86_fma_vfmadd_pd_256: 10866 Opc = X86ISD::FMADD; 10867 break; 10868 case Intrinsic::x86_fma_vfmsub_ps: 10869 case Intrinsic::x86_fma_vfmsub_pd: 10870 case Intrinsic::x86_fma_vfmsub_ps_256: 10871 case Intrinsic::x86_fma_vfmsub_pd_256: 10872 Opc = X86ISD::FMSUB; 10873 break; 10874 case Intrinsic::x86_fma_vfnmadd_ps: 10875 case Intrinsic::x86_fma_vfnmadd_pd: 10876 case Intrinsic::x86_fma_vfnmadd_ps_256: 10877 case Intrinsic::x86_fma_vfnmadd_pd_256: 10878 Opc = X86ISD::FNMADD; 10879 break; 10880 case Intrinsic::x86_fma_vfnmsub_ps: 10881 case Intrinsic::x86_fma_vfnmsub_pd: 10882 case Intrinsic::x86_fma_vfnmsub_ps_256: 10883 case Intrinsic::x86_fma_vfnmsub_pd_256: 10884 Opc = X86ISD::FNMSUB; 10885 break; 10886 case Intrinsic::x86_fma_vfmaddsub_ps: 10887 case Intrinsic::x86_fma_vfmaddsub_pd: 10888 case Intrinsic::x86_fma_vfmaddsub_ps_256: 10889 case Intrinsic::x86_fma_vfmaddsub_pd_256: 10890 Opc = X86ISD::FMADDSUB; 10891 break; 10892 case Intrinsic::x86_fma_vfmsubadd_ps: 10893 case Intrinsic::x86_fma_vfmsubadd_pd: 10894 case Intrinsic::x86_fma_vfmsubadd_ps_256: 10895 case Intrinsic::x86_fma_vfmsubadd_pd_256: 10896 Opc = X86ISD::FMSUBADD; 10897 break; 10898 } 10899 10900 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1), 10901 Op.getOperand(2), Op.getOperand(3)); 10902 } 10903 } 10904} 10905 10906static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) { 10907 DebugLoc dl = Op.getDebugLoc(); 10908 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10909 switch (IntNo) { 10910 default: return SDValue(); // Don't custom lower most intrinsics. 10911 10912 // RDRAND intrinsics. 10913 case Intrinsic::x86_rdrand_16: 10914 case Intrinsic::x86_rdrand_32: 10915 case Intrinsic::x86_rdrand_64: { 10916 // Emit the node with the right value type. 10917 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other); 10918 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0)); 10919 10920 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise 10921 // return the value from Rand, which is always 0, casted to i32. 10922 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)), 10923 DAG.getConstant(1, Op->getValueType(1)), 10924 DAG.getConstant(X86::COND_B, MVT::i32), 10925 SDValue(Result.getNode(), 1) }; 10926 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, 10927 DAG.getVTList(Op->getValueType(1), MVT::Glue), 10928 Ops, 4); 10929 10930 // Return { result, isValid, chain }. 10931 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid, 10932 SDValue(Result.getNode(), 2)); 10933 } 10934 10935 // XTEST intrinsics. 10936 case Intrinsic::x86_xtest: { 10937 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other); 10938 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0)); 10939 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 10940 DAG.getConstant(X86::COND_NE, MVT::i8), 10941 InTrans); 10942 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC); 10943 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), 10944 Ret, SDValue(InTrans.getNode(), 1)); 10945 } 10946 } 10947} 10948 10949SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 10950 SelectionDAG &DAG) const { 10951 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 10952 MFI->setReturnAddressIsTaken(true); 10953 10954 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10955 DebugLoc dl = Op.getDebugLoc(); 10956 EVT PtrVT = getPointerTy(); 10957 10958 if (Depth > 0) { 10959 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 10960 SDValue Offset = 10961 DAG.getConstant(RegInfo->getSlotSize(), PtrVT); 10962 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 10963 DAG.getNode(ISD::ADD, dl, PtrVT, 10964 FrameAddr, Offset), 10965 MachinePointerInfo(), false, false, false, 0); 10966 } 10967 10968 // Just load the return address. 10969 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 10970 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 10971 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 10972} 10973 10974SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 10975 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 10976 MFI->setFrameAddressIsTaken(true); 10977 10978 EVT VT = Op.getValueType(); 10979 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 10980 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10981 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 10982 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 10983 while (Depth--) 10984 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 10985 MachinePointerInfo(), 10986 false, false, false, 0); 10987 return FrameAddr; 10988} 10989 10990SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 10991 SelectionDAG &DAG) const { 10992 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize()); 10993} 10994 10995SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 10996 SDValue Chain = Op.getOperand(0); 10997 SDValue Offset = Op.getOperand(1); 10998 SDValue Handler = Op.getOperand(2); 10999 DebugLoc dl = Op.getDebugLoc(); 11000 11001 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 11002 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 11003 getPointerTy()); 11004 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 11005 11006 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 11007 DAG.getIntPtrConstant(RegInfo->getSlotSize())); 11008 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 11009 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 11010 false, false, 0); 11011 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 11012 11013 return DAG.getNode(X86ISD::EH_RETURN, dl, 11014 MVT::Other, 11015 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 11016} 11017 11018SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op, 11019 SelectionDAG &DAG) const { 11020 DebugLoc DL = Op.getDebugLoc(); 11021 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL, 11022 DAG.getVTList(MVT::i32, MVT::Other), 11023 Op.getOperand(0), Op.getOperand(1)); 11024} 11025 11026SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op, 11027 SelectionDAG &DAG) const { 11028 DebugLoc DL = Op.getDebugLoc(); 11029 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other, 11030 Op.getOperand(0), Op.getOperand(1)); 11031} 11032 11033static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) { 11034 return Op.getOperand(0); 11035} 11036 11037SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 11038 SelectionDAG &DAG) const { 11039 SDValue Root = Op.getOperand(0); 11040 SDValue Trmp = Op.getOperand(1); // trampoline 11041 SDValue FPtr = Op.getOperand(2); // nested function 11042 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 11043 DebugLoc dl = Op.getDebugLoc(); 11044 11045 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 11046 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 11047 11048 if (Subtarget->is64Bit()) { 11049 SDValue OutChains[6]; 11050 11051 // Large code-model. 11052 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 11053 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 11054 11055 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7; 11056 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7; 11057 11058 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 11059 11060 // Load the pointer to the nested function into R11. 11061 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 11062 SDValue Addr = Trmp; 11063 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 11064 Addr, MachinePointerInfo(TrmpAddr), 11065 false, false, 0); 11066 11067 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11068 DAG.getConstant(2, MVT::i64)); 11069 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 11070 MachinePointerInfo(TrmpAddr, 2), 11071 false, false, 2); 11072 11073 // Load the 'nest' parameter value into R10. 11074 // R10 is specified in X86CallingConv.td 11075 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 11076 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11077 DAG.getConstant(10, MVT::i64)); 11078 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 11079 Addr, MachinePointerInfo(TrmpAddr, 10), 11080 false, false, 0); 11081 11082 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11083 DAG.getConstant(12, MVT::i64)); 11084 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 11085 MachinePointerInfo(TrmpAddr, 12), 11086 false, false, 2); 11087 11088 // Jump to the nested function. 11089 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 11090 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11091 DAG.getConstant(20, MVT::i64)); 11092 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 11093 Addr, MachinePointerInfo(TrmpAddr, 20), 11094 false, false, 0); 11095 11096 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 11097 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11098 DAG.getConstant(22, MVT::i64)); 11099 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 11100 MachinePointerInfo(TrmpAddr, 22), 11101 false, false, 0); 11102 11103 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 11104 } else { 11105 const Function *Func = 11106 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 11107 CallingConv::ID CC = Func->getCallingConv(); 11108 unsigned NestReg; 11109 11110 switch (CC) { 11111 default: 11112 llvm_unreachable("Unsupported calling convention"); 11113 case CallingConv::C: 11114 case CallingConv::X86_StdCall: { 11115 // Pass 'nest' parameter in ECX. 11116 // Must be kept in sync with X86CallingConv.td 11117 NestReg = X86::ECX; 11118 11119 // Check that ECX wasn't needed by an 'inreg' parameter. 11120 FunctionType *FTy = Func->getFunctionType(); 11121 const AttributeSet &Attrs = Func->getAttributes(); 11122 11123 if (!Attrs.isEmpty() && !Func->isVarArg()) { 11124 unsigned InRegCount = 0; 11125 unsigned Idx = 1; 11126 11127 for (FunctionType::param_iterator I = FTy->param_begin(), 11128 E = FTy->param_end(); I != E; ++I, ++Idx) 11129 if (Attrs.hasAttribute(Idx, Attribute::InReg)) 11130 // FIXME: should only count parameters that are lowered to integers. 11131 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 11132 11133 if (InRegCount > 2) { 11134 report_fatal_error("Nest register in use - reduce number of inreg" 11135 " parameters!"); 11136 } 11137 } 11138 break; 11139 } 11140 case CallingConv::X86_FastCall: 11141 case CallingConv::X86_ThisCall: 11142 case CallingConv::Fast: 11143 // Pass 'nest' parameter in EAX. 11144 // Must be kept in sync with X86CallingConv.td 11145 NestReg = X86::EAX; 11146 break; 11147 } 11148 11149 SDValue OutChains[4]; 11150 SDValue Addr, Disp; 11151 11152 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 11153 DAG.getConstant(10, MVT::i32)); 11154 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 11155 11156 // This is storing the opcode for MOV32ri. 11157 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 11158 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7; 11159 OutChains[0] = DAG.getStore(Root, dl, 11160 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 11161 Trmp, MachinePointerInfo(TrmpAddr), 11162 false, false, 0); 11163 11164 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 11165 DAG.getConstant(1, MVT::i32)); 11166 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 11167 MachinePointerInfo(TrmpAddr, 1), 11168 false, false, 1); 11169 11170 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 11171 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 11172 DAG.getConstant(5, MVT::i32)); 11173 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 11174 MachinePointerInfo(TrmpAddr, 5), 11175 false, false, 1); 11176 11177 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 11178 DAG.getConstant(6, MVT::i32)); 11179 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 11180 MachinePointerInfo(TrmpAddr, 6), 11181 false, false, 1); 11182 11183 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 11184 } 11185} 11186 11187SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 11188 SelectionDAG &DAG) const { 11189 /* 11190 The rounding mode is in bits 11:10 of FPSR, and has the following 11191 settings: 11192 00 Round to nearest 11193 01 Round to -inf 11194 10 Round to +inf 11195 11 Round to 0 11196 11197 FLT_ROUNDS, on the other hand, expects the following: 11198 -1 Undefined 11199 0 Round to 0 11200 1 Round to nearest 11201 2 Round to +inf 11202 3 Round to -inf 11203 11204 To perform the conversion, we do: 11205 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 11206 */ 11207 11208 MachineFunction &MF = DAG.getMachineFunction(); 11209 const TargetMachine &TM = MF.getTarget(); 11210 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 11211 unsigned StackAlignment = TFI.getStackAlignment(); 11212 EVT VT = Op.getValueType(); 11213 DebugLoc DL = Op.getDebugLoc(); 11214 11215 // Save FP Control Word to stack slot 11216 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 11217 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 11218 11219 MachineMemOperand *MMO = 11220 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 11221 MachineMemOperand::MOStore, 2, 2); 11222 11223 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 11224 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 11225 DAG.getVTList(MVT::Other), 11226 Ops, 2, MVT::i16, MMO); 11227 11228 // Load FP Control Word from stack slot 11229 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 11230 MachinePointerInfo(), false, false, false, 0); 11231 11232 // Transform as necessary 11233 SDValue CWD1 = 11234 DAG.getNode(ISD::SRL, DL, MVT::i16, 11235 DAG.getNode(ISD::AND, DL, MVT::i16, 11236 CWD, DAG.getConstant(0x800, MVT::i16)), 11237 DAG.getConstant(11, MVT::i8)); 11238 SDValue CWD2 = 11239 DAG.getNode(ISD::SRL, DL, MVT::i16, 11240 DAG.getNode(ISD::AND, DL, MVT::i16, 11241 CWD, DAG.getConstant(0x400, MVT::i16)), 11242 DAG.getConstant(9, MVT::i8)); 11243 11244 SDValue RetVal = 11245 DAG.getNode(ISD::AND, DL, MVT::i16, 11246 DAG.getNode(ISD::ADD, DL, MVT::i16, 11247 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 11248 DAG.getConstant(1, MVT::i16)), 11249 DAG.getConstant(3, MVT::i16)); 11250 11251 return DAG.getNode((VT.getSizeInBits() < 16 ? 11252 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 11253} 11254 11255static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 11256 EVT VT = Op.getValueType(); 11257 EVT OpVT = VT; 11258 unsigned NumBits = VT.getSizeInBits(); 11259 DebugLoc dl = Op.getDebugLoc(); 11260 11261 Op = Op.getOperand(0); 11262 if (VT == MVT::i8) { 11263 // Zero extend to i32 since there is not an i8 bsr. 11264 OpVT = MVT::i32; 11265 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 11266 } 11267 11268 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 11269 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 11270 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 11271 11272 // If src is zero (i.e. bsr sets ZF), returns NumBits. 11273 SDValue Ops[] = { 11274 Op, 11275 DAG.getConstant(NumBits+NumBits-1, OpVT), 11276 DAG.getConstant(X86::COND_E, MVT::i8), 11277 Op.getValue(1) 11278 }; 11279 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 11280 11281 // Finally xor with NumBits-1. 11282 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 11283 11284 if (VT == MVT::i8) 11285 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 11286 return Op; 11287} 11288 11289static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) { 11290 EVT VT = Op.getValueType(); 11291 EVT OpVT = VT; 11292 unsigned NumBits = VT.getSizeInBits(); 11293 DebugLoc dl = Op.getDebugLoc(); 11294 11295 Op = Op.getOperand(0); 11296 if (VT == MVT::i8) { 11297 // Zero extend to i32 since there is not an i8 bsr. 11298 OpVT = MVT::i32; 11299 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 11300 } 11301 11302 // Issue a bsr (scan bits in reverse). 11303 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 11304 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 11305 11306 // And xor with NumBits-1. 11307 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 11308 11309 if (VT == MVT::i8) 11310 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 11311 return Op; 11312} 11313 11314static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 11315 EVT VT = Op.getValueType(); 11316 unsigned NumBits = VT.getSizeInBits(); 11317 DebugLoc dl = Op.getDebugLoc(); 11318 Op = Op.getOperand(0); 11319 11320 // Issue a bsf (scan bits forward) which also sets EFLAGS. 11321 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 11322 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 11323 11324 // If src is zero (i.e. bsf sets ZF), returns NumBits. 11325 SDValue Ops[] = { 11326 Op, 11327 DAG.getConstant(NumBits, VT), 11328 DAG.getConstant(X86::COND_E, MVT::i8), 11329 Op.getValue(1) 11330 }; 11331 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 11332} 11333 11334// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 11335// ones, and then concatenate the result back. 11336static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 11337 EVT VT = Op.getValueType(); 11338 11339 assert(VT.is256BitVector() && VT.isInteger() && 11340 "Unsupported value type for operation"); 11341 11342 unsigned NumElems = VT.getVectorNumElements(); 11343 DebugLoc dl = Op.getDebugLoc(); 11344 11345 // Extract the LHS vectors 11346 SDValue LHS = Op.getOperand(0); 11347 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 11348 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 11349 11350 // Extract the RHS vectors 11351 SDValue RHS = Op.getOperand(1); 11352 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 11353 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 11354 11355 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 11356 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 11357 11358 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 11359 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 11360 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 11361} 11362 11363static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) { 11364 assert(Op.getValueType().is256BitVector() && 11365 Op.getValueType().isInteger() && 11366 "Only handle AVX 256-bit vector integer operation"); 11367 return Lower256IntArith(Op, DAG); 11368} 11369 11370static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) { 11371 assert(Op.getValueType().is256BitVector() && 11372 Op.getValueType().isInteger() && 11373 "Only handle AVX 256-bit vector integer operation"); 11374 return Lower256IntArith(Op, DAG); 11375} 11376 11377static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget, 11378 SelectionDAG &DAG) { 11379 DebugLoc dl = Op.getDebugLoc(); 11380 EVT VT = Op.getValueType(); 11381 11382 // Decompose 256-bit ops into smaller 128-bit ops. 11383 if (VT.is256BitVector() && !Subtarget->hasInt256()) 11384 return Lower256IntArith(Op, DAG); 11385 11386 SDValue A = Op.getOperand(0); 11387 SDValue B = Op.getOperand(1); 11388 11389 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle. 11390 if (VT == MVT::v4i32) { 11391 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() && 11392 "Should not custom lower when pmuldq is available!"); 11393 11394 // Extract the odd parts. 11395 const int UnpackMask[] = { 1, -1, 3, -1 }; 11396 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask); 11397 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask); 11398 11399 // Multiply the even parts. 11400 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B); 11401 // Now multiply odd parts. 11402 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds); 11403 11404 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens); 11405 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds); 11406 11407 // Merge the two vectors back together with a shuffle. This expands into 2 11408 // shuffles. 11409 const int ShufMask[] = { 0, 4, 2, 6 }; 11410 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask); 11411 } 11412 11413 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 11414 "Only know how to lower V2I64/V4I64 multiply"); 11415 11416 // Ahi = psrlqi(a, 32); 11417 // Bhi = psrlqi(b, 32); 11418 // 11419 // AloBlo = pmuludq(a, b); 11420 // AloBhi = pmuludq(a, Bhi); 11421 // AhiBlo = pmuludq(Ahi, b); 11422 11423 // AloBhi = psllqi(AloBhi, 32); 11424 // AhiBlo = psllqi(AhiBlo, 32); 11425 // return AloBlo + AloBhi + AhiBlo; 11426 11427 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 11428 11429 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 11430 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 11431 11432 // Bit cast to 32-bit vectors for MULUDQ 11433 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 11434 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 11435 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 11436 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 11437 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 11438 11439 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 11440 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 11441 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 11442 11443 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 11444 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 11445 11446 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 11447 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 11448} 11449 11450SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const { 11451 EVT VT = Op.getValueType(); 11452 EVT EltTy = VT.getVectorElementType(); 11453 unsigned NumElts = VT.getVectorNumElements(); 11454 SDValue N0 = Op.getOperand(0); 11455 DebugLoc dl = Op.getDebugLoc(); 11456 11457 // Lower sdiv X, pow2-const. 11458 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1)); 11459 if (!C) 11460 return SDValue(); 11461 11462 APInt SplatValue, SplatUndef; 11463 unsigned MinSplatBits; 11464 bool HasAnyUndefs; 11465 if (!C->isConstantSplat(SplatValue, SplatUndef, MinSplatBits, HasAnyUndefs)) 11466 return SDValue(); 11467 11468 if ((SplatValue != 0) && 11469 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) { 11470 unsigned lg2 = SplatValue.countTrailingZeros(); 11471 // Splat the sign bit. 11472 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32); 11473 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG); 11474 // Add (N0 < 0) ? abs2 - 1 : 0; 11475 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32); 11476 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG); 11477 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL); 11478 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32); 11479 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG); 11480 11481 // If we're dividing by a positive value, we're done. Otherwise, we must 11482 // negate the result. 11483 if (SplatValue.isNonNegative()) 11484 return SRA; 11485 11486 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy)); 11487 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts); 11488 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA); 11489 } 11490 return SDValue(); 11491} 11492 11493static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG, 11494 const X86Subtarget *Subtarget) { 11495 EVT VT = Op.getValueType(); 11496 DebugLoc dl = Op.getDebugLoc(); 11497 SDValue R = Op.getOperand(0); 11498 SDValue Amt = Op.getOperand(1); 11499 11500 // Optimize shl/srl/sra with constant shift amount. 11501 if (isSplatVector(Amt.getNode())) { 11502 SDValue SclrAmt = Amt->getOperand(0); 11503 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 11504 uint64_t ShiftAmt = C->getZExtValue(); 11505 11506 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 11507 (Subtarget->hasInt256() && 11508 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 11509 if (Op.getOpcode() == ISD::SHL) 11510 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 11511 DAG.getConstant(ShiftAmt, MVT::i32)); 11512 if (Op.getOpcode() == ISD::SRL) 11513 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 11514 DAG.getConstant(ShiftAmt, MVT::i32)); 11515 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 11516 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 11517 DAG.getConstant(ShiftAmt, MVT::i32)); 11518 } 11519 11520 if (VT == MVT::v16i8) { 11521 if (Op.getOpcode() == ISD::SHL) { 11522 // Make a large shift. 11523 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 11524 DAG.getConstant(ShiftAmt, MVT::i32)); 11525 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 11526 // Zero out the rightmost bits. 11527 SmallVector<SDValue, 16> V(16, 11528 DAG.getConstant(uint8_t(-1U << ShiftAmt), 11529 MVT::i8)); 11530 return DAG.getNode(ISD::AND, dl, VT, SHL, 11531 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 11532 } 11533 if (Op.getOpcode() == ISD::SRL) { 11534 // Make a large shift. 11535 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 11536 DAG.getConstant(ShiftAmt, MVT::i32)); 11537 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 11538 // Zero out the leftmost bits. 11539 SmallVector<SDValue, 16> V(16, 11540 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 11541 MVT::i8)); 11542 return DAG.getNode(ISD::AND, dl, VT, SRL, 11543 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 11544 } 11545 if (Op.getOpcode() == ISD::SRA) { 11546 if (ShiftAmt == 7) { 11547 // R s>> 7 === R s< 0 11548 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 11549 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 11550 } 11551 11552 // R s>> a === ((R u>> a) ^ m) - m 11553 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 11554 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 11555 MVT::i8)); 11556 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 11557 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 11558 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 11559 return Res; 11560 } 11561 llvm_unreachable("Unknown shift opcode."); 11562 } 11563 11564 if (Subtarget->hasInt256() && VT == MVT::v32i8) { 11565 if (Op.getOpcode() == ISD::SHL) { 11566 // Make a large shift. 11567 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 11568 DAG.getConstant(ShiftAmt, MVT::i32)); 11569 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 11570 // Zero out the rightmost bits. 11571 SmallVector<SDValue, 32> V(32, 11572 DAG.getConstant(uint8_t(-1U << ShiftAmt), 11573 MVT::i8)); 11574 return DAG.getNode(ISD::AND, dl, VT, SHL, 11575 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 11576 } 11577 if (Op.getOpcode() == ISD::SRL) { 11578 // Make a large shift. 11579 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 11580 DAG.getConstant(ShiftAmt, MVT::i32)); 11581 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 11582 // Zero out the leftmost bits. 11583 SmallVector<SDValue, 32> V(32, 11584 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 11585 MVT::i8)); 11586 return DAG.getNode(ISD::AND, dl, VT, SRL, 11587 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 11588 } 11589 if (Op.getOpcode() == ISD::SRA) { 11590 if (ShiftAmt == 7) { 11591 // R s>> 7 === R s< 0 11592 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 11593 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 11594 } 11595 11596 // R s>> a === ((R u>> a) ^ m) - m 11597 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 11598 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 11599 MVT::i8)); 11600 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 11601 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 11602 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 11603 return Res; 11604 } 11605 llvm_unreachable("Unknown shift opcode."); 11606 } 11607 } 11608 } 11609 11610 // Special case in 32-bit mode, where i64 is expanded into high and low parts. 11611 if (!Subtarget->is64Bit() && 11612 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) && 11613 Amt.getOpcode() == ISD::BITCAST && 11614 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { 11615 Amt = Amt.getOperand(0); 11616 unsigned Ratio = Amt.getValueType().getVectorNumElements() / 11617 VT.getVectorNumElements(); 11618 unsigned RatioInLog2 = Log2_32_Ceil(Ratio); 11619 uint64_t ShiftAmt = 0; 11620 for (unsigned i = 0; i != Ratio; ++i) { 11621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i)); 11622 if (C == 0) 11623 return SDValue(); 11624 // 6 == Log2(64) 11625 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2))); 11626 } 11627 // Check remaining shift amounts. 11628 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) { 11629 uint64_t ShAmt = 0; 11630 for (unsigned j = 0; j != Ratio; ++j) { 11631 ConstantSDNode *C = 11632 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j)); 11633 if (C == 0) 11634 return SDValue(); 11635 // 6 == Log2(64) 11636 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2))); 11637 } 11638 if (ShAmt != ShiftAmt) 11639 return SDValue(); 11640 } 11641 switch (Op.getOpcode()) { 11642 default: 11643 llvm_unreachable("Unknown shift opcode!"); 11644 case ISD::SHL: 11645 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 11646 DAG.getConstant(ShiftAmt, MVT::i32)); 11647 case ISD::SRL: 11648 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 11649 DAG.getConstant(ShiftAmt, MVT::i32)); 11650 case ISD::SRA: 11651 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 11652 DAG.getConstant(ShiftAmt, MVT::i32)); 11653 } 11654 } 11655 11656 return SDValue(); 11657} 11658 11659static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG, 11660 const X86Subtarget* Subtarget) { 11661 EVT VT = Op.getValueType(); 11662 DebugLoc dl = Op.getDebugLoc(); 11663 SDValue R = Op.getOperand(0); 11664 SDValue Amt = Op.getOperand(1); 11665 11666 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) || 11667 VT == MVT::v4i32 || VT == MVT::v8i16 || 11668 (Subtarget->hasInt256() && 11669 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) || 11670 VT == MVT::v8i32 || VT == MVT::v16i16))) { 11671 SDValue BaseShAmt; 11672 EVT EltVT = VT.getVectorElementType(); 11673 11674 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 11675 unsigned NumElts = VT.getVectorNumElements(); 11676 unsigned i, j; 11677 for (i = 0; i != NumElts; ++i) { 11678 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF) 11679 continue; 11680 break; 11681 } 11682 for (j = i; j != NumElts; ++j) { 11683 SDValue Arg = Amt.getOperand(j); 11684 if (Arg.getOpcode() == ISD::UNDEF) continue; 11685 if (Arg != Amt.getOperand(i)) 11686 break; 11687 } 11688 if (i != NumElts && j == NumElts) 11689 BaseShAmt = Amt.getOperand(i); 11690 } else { 11691 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR) 11692 Amt = Amt.getOperand(0); 11693 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE && 11694 cast<ShuffleVectorSDNode>(Amt)->isSplat()) { 11695 SDValue InVec = Amt.getOperand(0); 11696 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 11697 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 11698 unsigned i = 0; 11699 for (; i != NumElts; ++i) { 11700 SDValue Arg = InVec.getOperand(i); 11701 if (Arg.getOpcode() == ISD::UNDEF) continue; 11702 BaseShAmt = Arg; 11703 break; 11704 } 11705 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 11706 if (ConstantSDNode *C = 11707 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 11708 unsigned SplatIdx = 11709 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex(); 11710 if (C->getZExtValue() == SplatIdx) 11711 BaseShAmt = InVec.getOperand(1); 11712 } 11713 } 11714 if (BaseShAmt.getNode() == 0) 11715 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt, 11716 DAG.getIntPtrConstant(0)); 11717 } 11718 } 11719 11720 if (BaseShAmt.getNode()) { 11721 if (EltVT.bitsGT(MVT::i32)) 11722 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt); 11723 else if (EltVT.bitsLT(MVT::i32)) 11724 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt); 11725 11726 switch (Op.getOpcode()) { 11727 default: 11728 llvm_unreachable("Unknown shift opcode!"); 11729 case ISD::SHL: 11730 switch (VT.getSimpleVT().SimpleTy) { 11731 default: return SDValue(); 11732 case MVT::v2i64: 11733 case MVT::v4i32: 11734 case MVT::v8i16: 11735 case MVT::v4i64: 11736 case MVT::v8i32: 11737 case MVT::v16i16: 11738 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG); 11739 } 11740 case ISD::SRA: 11741 switch (VT.getSimpleVT().SimpleTy) { 11742 default: return SDValue(); 11743 case MVT::v4i32: 11744 case MVT::v8i16: 11745 case MVT::v8i32: 11746 case MVT::v16i16: 11747 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG); 11748 } 11749 case ISD::SRL: 11750 switch (VT.getSimpleVT().SimpleTy) { 11751 default: return SDValue(); 11752 case MVT::v2i64: 11753 case MVT::v4i32: 11754 case MVT::v8i16: 11755 case MVT::v4i64: 11756 case MVT::v8i32: 11757 case MVT::v16i16: 11758 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG); 11759 } 11760 } 11761 } 11762 } 11763 11764 // Special case in 32-bit mode, where i64 is expanded into high and low parts. 11765 if (!Subtarget->is64Bit() && 11766 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) && 11767 Amt.getOpcode() == ISD::BITCAST && 11768 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { 11769 Amt = Amt.getOperand(0); 11770 unsigned Ratio = Amt.getValueType().getVectorNumElements() / 11771 VT.getVectorNumElements(); 11772 std::vector<SDValue> Vals(Ratio); 11773 for (unsigned i = 0; i != Ratio; ++i) 11774 Vals[i] = Amt.getOperand(i); 11775 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) { 11776 for (unsigned j = 0; j != Ratio; ++j) 11777 if (Vals[j] != Amt.getOperand(i + j)) 11778 return SDValue(); 11779 } 11780 switch (Op.getOpcode()) { 11781 default: 11782 llvm_unreachable("Unknown shift opcode!"); 11783 case ISD::SHL: 11784 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1)); 11785 case ISD::SRL: 11786 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1)); 11787 case ISD::SRA: 11788 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1)); 11789 } 11790 } 11791 11792 return SDValue(); 11793} 11794 11795SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 11796 11797 EVT VT = Op.getValueType(); 11798 DebugLoc dl = Op.getDebugLoc(); 11799 SDValue R = Op.getOperand(0); 11800 SDValue Amt = Op.getOperand(1); 11801 SDValue V; 11802 11803 if (!Subtarget->hasSSE2()) 11804 return SDValue(); 11805 11806 V = LowerScalarImmediateShift(Op, DAG, Subtarget); 11807 if (V.getNode()) 11808 return V; 11809 11810 V = LowerScalarVariableShift(Op, DAG, Subtarget); 11811 if (V.getNode()) 11812 return V; 11813 11814 // AVX2 has VPSLLV/VPSRAV/VPSRLV. 11815 if (Subtarget->hasInt256()) { 11816 if (Op.getOpcode() == ISD::SRL && 11817 (VT == MVT::v2i64 || VT == MVT::v4i32 || 11818 VT == MVT::v4i64 || VT == MVT::v8i32)) 11819 return Op; 11820 if (Op.getOpcode() == ISD::SHL && 11821 (VT == MVT::v2i64 || VT == MVT::v4i32 || 11822 VT == MVT::v4i64 || VT == MVT::v8i32)) 11823 return Op; 11824 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32)) 11825 return Op; 11826 } 11827 11828 // Lower SHL with variable shift amount. 11829 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 11830 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT)); 11831 11832 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT)); 11833 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 11834 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 11835 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 11836 } 11837 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 11838 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 11839 11840 // a = a << 5; 11841 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT)); 11842 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 11843 11844 // Turn 'a' into a mask suitable for VSELECT 11845 SDValue VSelM = DAG.getConstant(0x80, VT); 11846 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 11847 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 11848 11849 SDValue CM1 = DAG.getConstant(0x0f, VT); 11850 SDValue CM2 = DAG.getConstant(0x3f, VT); 11851 11852 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 11853 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 11854 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 11855 DAG.getConstant(4, MVT::i32), DAG); 11856 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 11857 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 11858 11859 // a += a 11860 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 11861 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 11862 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 11863 11864 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 11865 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 11866 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 11867 DAG.getConstant(2, MVT::i32), DAG); 11868 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 11869 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 11870 11871 // a += a 11872 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 11873 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 11874 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 11875 11876 // return VSELECT(r, r+r, a); 11877 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 11878 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 11879 return R; 11880 } 11881 11882 // Decompose 256-bit shifts into smaller 128-bit shifts. 11883 if (VT.is256BitVector()) { 11884 unsigned NumElems = VT.getVectorNumElements(); 11885 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 11886 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 11887 11888 // Extract the two vectors 11889 SDValue V1 = Extract128BitVector(R, 0, DAG, dl); 11890 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); 11891 11892 // Recreate the shift amount vectors 11893 SDValue Amt1, Amt2; 11894 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 11895 // Constant shift amount 11896 SmallVector<SDValue, 4> Amt1Csts; 11897 SmallVector<SDValue, 4> Amt2Csts; 11898 for (unsigned i = 0; i != NumElems/2; ++i) 11899 Amt1Csts.push_back(Amt->getOperand(i)); 11900 for (unsigned i = NumElems/2; i != NumElems; ++i) 11901 Amt2Csts.push_back(Amt->getOperand(i)); 11902 11903 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 11904 &Amt1Csts[0], NumElems/2); 11905 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 11906 &Amt2Csts[0], NumElems/2); 11907 } else { 11908 // Variable shift amount 11909 Amt1 = Extract128BitVector(Amt, 0, DAG, dl); 11910 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl); 11911 } 11912 11913 // Issue new vector shifts for the smaller types 11914 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 11915 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 11916 11917 // Concatenate the result back 11918 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 11919 } 11920 11921 return SDValue(); 11922} 11923 11924static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) { 11925 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 11926 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 11927 // looks for this combo and may remove the "setcc" instruction if the "setcc" 11928 // has only one use. 11929 SDNode *N = Op.getNode(); 11930 SDValue LHS = N->getOperand(0); 11931 SDValue RHS = N->getOperand(1); 11932 unsigned BaseOp = 0; 11933 unsigned Cond = 0; 11934 DebugLoc DL = Op.getDebugLoc(); 11935 switch (Op.getOpcode()) { 11936 default: llvm_unreachable("Unknown ovf instruction!"); 11937 case ISD::SADDO: 11938 // A subtract of one will be selected as a INC. Note that INC doesn't 11939 // set CF, so we can't do this for UADDO. 11940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 11941 if (C->isOne()) { 11942 BaseOp = X86ISD::INC; 11943 Cond = X86::COND_O; 11944 break; 11945 } 11946 BaseOp = X86ISD::ADD; 11947 Cond = X86::COND_O; 11948 break; 11949 case ISD::UADDO: 11950 BaseOp = X86ISD::ADD; 11951 Cond = X86::COND_B; 11952 break; 11953 case ISD::SSUBO: 11954 // A subtract of one will be selected as a DEC. Note that DEC doesn't 11955 // set CF, so we can't do this for USUBO. 11956 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 11957 if (C->isOne()) { 11958 BaseOp = X86ISD::DEC; 11959 Cond = X86::COND_O; 11960 break; 11961 } 11962 BaseOp = X86ISD::SUB; 11963 Cond = X86::COND_O; 11964 break; 11965 case ISD::USUBO: 11966 BaseOp = X86ISD::SUB; 11967 Cond = X86::COND_B; 11968 break; 11969 case ISD::SMULO: 11970 BaseOp = X86ISD::SMUL; 11971 Cond = X86::COND_O; 11972 break; 11973 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 11974 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 11975 MVT::i32); 11976 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 11977 11978 SDValue SetCC = 11979 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11980 DAG.getConstant(X86::COND_O, MVT::i32), 11981 SDValue(Sum.getNode(), 2)); 11982 11983 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 11984 } 11985 } 11986 11987 // Also sets EFLAGS. 11988 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 11989 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 11990 11991 SDValue SetCC = 11992 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 11993 DAG.getConstant(Cond, MVT::i32), 11994 SDValue(Sum.getNode(), 1)); 11995 11996 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 11997} 11998 11999SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 12000 SelectionDAG &DAG) const { 12001 DebugLoc dl = Op.getDebugLoc(); 12002 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 12003 EVT VT = Op.getValueType(); 12004 12005 if (!Subtarget->hasSSE2() || !VT.isVector()) 12006 return SDValue(); 12007 12008 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 12009 ExtraVT.getScalarType().getSizeInBits(); 12010 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 12011 12012 switch (VT.getSimpleVT().SimpleTy) { 12013 default: return SDValue(); 12014 case MVT::v8i32: 12015 case MVT::v16i16: 12016 if (!Subtarget->hasFp256()) 12017 return SDValue(); 12018 if (!Subtarget->hasInt256()) { 12019 // needs to be split 12020 unsigned NumElems = VT.getVectorNumElements(); 12021 12022 // Extract the LHS vectors 12023 SDValue LHS = Op.getOperand(0); 12024 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 12025 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 12026 12027 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 12028 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 12029 12030 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 12031 unsigned ExtraNumElems = ExtraVT.getVectorNumElements(); 12032 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 12033 ExtraNumElems/2); 12034 SDValue Extra = DAG.getValueType(ExtraVT); 12035 12036 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 12037 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 12038 12039 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2); 12040 } 12041 // fall through 12042 case MVT::v4i32: 12043 case MVT::v8i16: { 12044 // (sext (vzext x)) -> (vsext x) 12045 SDValue Op0 = Op.getOperand(0); 12046 SDValue Op00 = Op0.getOperand(0); 12047 SDValue Tmp1; 12048 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT. 12049 if (Op0.getOpcode() == ISD::BITCAST && 12050 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) 12051 Tmp1 = LowerVectorIntExtend(Op00, DAG); 12052 if (Tmp1.getNode()) { 12053 SDValue Tmp1Op0 = Tmp1.getOperand(0); 12054 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT && 12055 "This optimization is invalid without a VZEXT."); 12056 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0)); 12057 } 12058 12059 // If the above didn't work, then just use Shift-Left + Shift-Right. 12060 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG); 12061 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 12062 } 12063 } 12064} 12065 12066static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget, 12067 SelectionDAG &DAG) { 12068 DebugLoc dl = Op.getDebugLoc(); 12069 12070 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 12071 // There isn't any reason to disable it if the target processor supports it. 12072 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 12073 SDValue Chain = Op.getOperand(0); 12074 SDValue Zero = DAG.getConstant(0, MVT::i32); 12075 SDValue Ops[] = { 12076 DAG.getRegister(X86::ESP, MVT::i32), // Base 12077 DAG.getTargetConstant(1, MVT::i8), // Scale 12078 DAG.getRegister(0, MVT::i32), // Index 12079 DAG.getTargetConstant(0, MVT::i32), // Disp 12080 DAG.getRegister(0, MVT::i32), // Segment. 12081 Zero, 12082 Chain 12083 }; 12084 SDNode *Res = 12085 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 12086 array_lengthof(Ops)); 12087 return SDValue(Res, 0); 12088 } 12089 12090 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 12091 if (!isDev) 12092 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 12093 12094 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 12095 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 12096 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 12097 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 12098 12099 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 12100 if (!Op1 && !Op2 && !Op3 && Op4) 12101 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 12102 12103 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 12104 if (Op1 && !Op2 && !Op3 && !Op4) 12105 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 12106 12107 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 12108 // (MFENCE)>; 12109 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 12110} 12111 12112static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget, 12113 SelectionDAG &DAG) { 12114 DebugLoc dl = Op.getDebugLoc(); 12115 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 12116 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 12117 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 12118 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 12119 12120 // The only fence that needs an instruction is a sequentially-consistent 12121 // cross-thread fence. 12122 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 12123 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 12124 // no-sse2). There isn't any reason to disable it if the target processor 12125 // supports it. 12126 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 12127 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 12128 12129 SDValue Chain = Op.getOperand(0); 12130 SDValue Zero = DAG.getConstant(0, MVT::i32); 12131 SDValue Ops[] = { 12132 DAG.getRegister(X86::ESP, MVT::i32), // Base 12133 DAG.getTargetConstant(1, MVT::i8), // Scale 12134 DAG.getRegister(0, MVT::i32), // Index 12135 DAG.getTargetConstant(0, MVT::i32), // Disp 12136 DAG.getRegister(0, MVT::i32), // Segment. 12137 Zero, 12138 Chain 12139 }; 12140 SDNode *Res = 12141 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 12142 array_lengthof(Ops)); 12143 return SDValue(Res, 0); 12144 } 12145 12146 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 12147 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 12148} 12149 12150static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget, 12151 SelectionDAG &DAG) { 12152 EVT T = Op.getValueType(); 12153 DebugLoc DL = Op.getDebugLoc(); 12154 unsigned Reg = 0; 12155 unsigned size = 0; 12156 switch(T.getSimpleVT().SimpleTy) { 12157 default: llvm_unreachable("Invalid value type!"); 12158 case MVT::i8: Reg = X86::AL; size = 1; break; 12159 case MVT::i16: Reg = X86::AX; size = 2; break; 12160 case MVT::i32: Reg = X86::EAX; size = 4; break; 12161 case MVT::i64: 12162 assert(Subtarget->is64Bit() && "Node not type legal!"); 12163 Reg = X86::RAX; size = 8; 12164 break; 12165 } 12166 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 12167 Op.getOperand(2), SDValue()); 12168 SDValue Ops[] = { cpIn.getValue(0), 12169 Op.getOperand(1), 12170 Op.getOperand(3), 12171 DAG.getTargetConstant(size, MVT::i8), 12172 cpIn.getValue(1) }; 12173 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 12174 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 12175 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 12176 Ops, 5, T, MMO); 12177 SDValue cpOut = 12178 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 12179 return cpOut; 12180} 12181 12182static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget, 12183 SelectionDAG &DAG) { 12184 assert(Subtarget->is64Bit() && "Result not type legalized?"); 12185 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 12186 SDValue TheChain = Op.getOperand(0); 12187 DebugLoc dl = Op.getDebugLoc(); 12188 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 12189 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 12190 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 12191 rax.getValue(2)); 12192 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 12193 DAG.getConstant(32, MVT::i8)); 12194 SDValue Ops[] = { 12195 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 12196 rdx.getValue(1) 12197 }; 12198 return DAG.getMergeValues(Ops, 2, dl); 12199} 12200 12201SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const { 12202 EVT SrcVT = Op.getOperand(0).getValueType(); 12203 EVT DstVT = Op.getValueType(); 12204 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 12205 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 12206 assert((DstVT == MVT::i64 || 12207 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 12208 "Unexpected custom BITCAST"); 12209 // i64 <=> MMX conversions are Legal. 12210 if (SrcVT==MVT::i64 && DstVT.isVector()) 12211 return Op; 12212 if (DstVT==MVT::i64 && SrcVT.isVector()) 12213 return Op; 12214 // MMX <=> MMX conversions are Legal. 12215 if (SrcVT.isVector() && DstVT.isVector()) 12216 return Op; 12217 // All other conversions need to be expanded. 12218 return SDValue(); 12219} 12220 12221static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 12222 SDNode *Node = Op.getNode(); 12223 DebugLoc dl = Node->getDebugLoc(); 12224 EVT T = Node->getValueType(0); 12225 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 12226 DAG.getConstant(0, T), Node->getOperand(2)); 12227 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 12228 cast<AtomicSDNode>(Node)->getMemoryVT(), 12229 Node->getOperand(0), 12230 Node->getOperand(1), negOp, 12231 cast<AtomicSDNode>(Node)->getSrcValue(), 12232 cast<AtomicSDNode>(Node)->getAlignment(), 12233 cast<AtomicSDNode>(Node)->getOrdering(), 12234 cast<AtomicSDNode>(Node)->getSynchScope()); 12235} 12236 12237static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 12238 SDNode *Node = Op.getNode(); 12239 DebugLoc dl = Node->getDebugLoc(); 12240 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 12241 12242 // Convert seq_cst store -> xchg 12243 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 12244 // FIXME: On 32-bit, store -> fist or movq would be more efficient 12245 // (The only way to get a 16-byte store is cmpxchg16b) 12246 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 12247 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 12248 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 12249 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 12250 cast<AtomicSDNode>(Node)->getMemoryVT(), 12251 Node->getOperand(0), 12252 Node->getOperand(1), Node->getOperand(2), 12253 cast<AtomicSDNode>(Node)->getMemOperand(), 12254 cast<AtomicSDNode>(Node)->getOrdering(), 12255 cast<AtomicSDNode>(Node)->getSynchScope()); 12256 return Swap.getValue(1); 12257 } 12258 // Other atomic stores have a simple pattern. 12259 return Op; 12260} 12261 12262static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 12263 EVT VT = Op.getNode()->getValueType(0); 12264 12265 // Let legalize expand this if it isn't a legal type yet. 12266 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 12267 return SDValue(); 12268 12269 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 12270 12271 unsigned Opc; 12272 bool ExtraOp = false; 12273 switch (Op.getOpcode()) { 12274 default: llvm_unreachable("Invalid code"); 12275 case ISD::ADDC: Opc = X86ISD::ADD; break; 12276 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 12277 case ISD::SUBC: Opc = X86ISD::SUB; break; 12278 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 12279 } 12280 12281 if (!ExtraOp) 12282 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 12283 Op.getOperand(1)); 12284 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 12285 Op.getOperand(1), Op.getOperand(2)); 12286} 12287 12288SDValue X86TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const { 12289 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit()); 12290 12291 // For MacOSX, we want to call an alternative entry point: __sincos_stret, 12292 // which returns the values in two XMM registers. 12293 DebugLoc dl = Op.getDebugLoc(); 12294 SDValue Arg = Op.getOperand(0); 12295 EVT ArgVT = Arg.getValueType(); 12296 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 12297 12298 ArgListTy Args; 12299 ArgListEntry Entry; 12300 12301 Entry.Node = Arg; 12302 Entry.Ty = ArgTy; 12303 Entry.isSExt = false; 12304 Entry.isZExt = false; 12305 Args.push_back(Entry); 12306 12307 // Only optimize x86_64 for now. i386 is a bit messy. For f32, 12308 // the small struct {f32, f32} is returned in (eax, edx). For f64, 12309 // the results are returned via SRet in memory. 12310 const char *LibcallName = (ArgVT == MVT::f64) 12311 ? "__sincos_stret" : "__sincosf_stret"; 12312 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy()); 12313 12314 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL); 12315 TargetLowering:: 12316 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, 12317 false, false, false, false, 0, 12318 CallingConv::C, /*isTaillCall=*/false, 12319 /*doesNotRet=*/false, /*isReturnValueUsed*/true, 12320 Callee, Args, DAG, dl); 12321 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 12322 return CallResult.first; 12323} 12324 12325/// LowerOperation - Provide custom lowering hooks for some operations. 12326/// 12327SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 12328 switch (Op.getOpcode()) { 12329 default: llvm_unreachable("Should not custom lower this!"); 12330 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 12331 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG); 12332 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG); 12333 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG); 12334 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 12335 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 12336 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 12337 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 12338 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 12339 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 12340 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 12341 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG); 12342 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG); 12343 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 12344 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 12345 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 12346 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 12347 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 12348 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 12349 case ISD::SHL_PARTS: 12350 case ISD::SRA_PARTS: 12351 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 12352 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 12353 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 12354 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG); 12355 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG); 12356 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 12357 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG); 12358 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 12359 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 12360 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); 12361 case ISD::FABS: return LowerFABS(Op, DAG); 12362 case ISD::FNEG: return LowerFNEG(Op, DAG); 12363 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 12364 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 12365 case ISD::SETCC: return LowerSETCC(Op, DAG); 12366 case ISD::SELECT: return LowerSELECT(Op, DAG); 12367 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 12368 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 12369 case ISD::VASTART: return LowerVASTART(Op, DAG); 12370 case ISD::VAARG: return LowerVAARG(Op, DAG); 12371 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG); 12372 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 12373 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 12374 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 12375 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 12376 case ISD::FRAME_TO_ARGS_OFFSET: 12377 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 12378 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 12379 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 12380 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG); 12381 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG); 12382 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 12383 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 12384 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 12385 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 12386 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 12387 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 12388 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG); 12389 case ISD::SRA: 12390 case ISD::SRL: 12391 case ISD::SHL: return LowerShift(Op, DAG); 12392 case ISD::SADDO: 12393 case ISD::UADDO: 12394 case ISD::SSUBO: 12395 case ISD::USUBO: 12396 case ISD::SMULO: 12397 case ISD::UMULO: return LowerXALUO(Op, DAG); 12398 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG); 12399 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 12400 case ISD::ADDC: 12401 case ISD::ADDE: 12402 case ISD::SUBC: 12403 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 12404 case ISD::ADD: return LowerADD(Op, DAG); 12405 case ISD::SUB: return LowerSUB(Op, DAG); 12406 case ISD::SDIV: return LowerSDIV(Op, DAG); 12407 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); 12408 } 12409} 12410 12411static void ReplaceATOMIC_LOAD(SDNode *Node, 12412 SmallVectorImpl<SDValue> &Results, 12413 SelectionDAG &DAG) { 12414 DebugLoc dl = Node->getDebugLoc(); 12415 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 12416 12417 // Convert wide load -> cmpxchg8b/cmpxchg16b 12418 // FIXME: On 32-bit, load -> fild or movq would be more efficient 12419 // (The only way to get a 16-byte load is cmpxchg16b) 12420 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 12421 SDValue Zero = DAG.getConstant(0, VT); 12422 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 12423 Node->getOperand(0), 12424 Node->getOperand(1), Zero, Zero, 12425 cast<AtomicSDNode>(Node)->getMemOperand(), 12426 cast<AtomicSDNode>(Node)->getOrdering(), 12427 cast<AtomicSDNode>(Node)->getSynchScope()); 12428 Results.push_back(Swap.getValue(0)); 12429 Results.push_back(Swap.getValue(1)); 12430} 12431 12432static void 12433ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 12434 SelectionDAG &DAG, unsigned NewOp) { 12435 DebugLoc dl = Node->getDebugLoc(); 12436 assert (Node->getValueType(0) == MVT::i64 && 12437 "Only know how to expand i64 atomics"); 12438 12439 SDValue Chain = Node->getOperand(0); 12440 SDValue In1 = Node->getOperand(1); 12441 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 12442 Node->getOperand(2), DAG.getIntPtrConstant(0)); 12443 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 12444 Node->getOperand(2), DAG.getIntPtrConstant(1)); 12445 SDValue Ops[] = { Chain, In1, In2L, In2H }; 12446 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 12447 SDValue Result = 12448 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 12449 cast<MemSDNode>(Node)->getMemOperand()); 12450 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 12451 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 12452 Results.push_back(Result.getValue(2)); 12453} 12454 12455/// ReplaceNodeResults - Replace a node with an illegal result type 12456/// with a new node built out of custom code. 12457void X86TargetLowering::ReplaceNodeResults(SDNode *N, 12458 SmallVectorImpl<SDValue>&Results, 12459 SelectionDAG &DAG) const { 12460 DebugLoc dl = N->getDebugLoc(); 12461 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12462 switch (N->getOpcode()) { 12463 default: 12464 llvm_unreachable("Do not know how to custom type legalize this operation!"); 12465 case ISD::SIGN_EXTEND_INREG: 12466 case ISD::ADDC: 12467 case ISD::ADDE: 12468 case ISD::SUBC: 12469 case ISD::SUBE: 12470 // We don't want to expand or promote these. 12471 return; 12472 case ISD::FP_TO_SINT: 12473 case ISD::FP_TO_UINT: { 12474 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 12475 12476 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 12477 return; 12478 12479 std::pair<SDValue,SDValue> Vals = 12480 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 12481 SDValue FIST = Vals.first, StackSlot = Vals.second; 12482 if (FIST.getNode() != 0) { 12483 EVT VT = N->getValueType(0); 12484 // Return a load from the stack slot. 12485 if (StackSlot.getNode() != 0) 12486 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 12487 MachinePointerInfo(), 12488 false, false, false, 0)); 12489 else 12490 Results.push_back(FIST); 12491 } 12492 return; 12493 } 12494 case ISD::UINT_TO_FP: { 12495 assert(Subtarget->hasSSE2() && "Requires at least SSE2!"); 12496 if (N->getOperand(0).getValueType() != MVT::v2i32 || 12497 N->getValueType(0) != MVT::v2f32) 12498 return; 12499 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, 12500 N->getOperand(0)); 12501 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 12502 MVT::f64); 12503 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias); 12504 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn, 12505 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias)); 12506 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or); 12507 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias); 12508 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub)); 12509 return; 12510 } 12511 case ISD::FP_ROUND: { 12512 if (!TLI.isTypeLegal(N->getOperand(0).getValueType())) 12513 return; 12514 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0)); 12515 Results.push_back(V); 12516 return; 12517 } 12518 case ISD::READCYCLECOUNTER: { 12519 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 12520 SDValue TheChain = N->getOperand(0); 12521 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 12522 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 12523 rd.getValue(1)); 12524 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 12525 eax.getValue(2)); 12526 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 12527 SDValue Ops[] = { eax, edx }; 12528 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 12529 Results.push_back(edx.getValue(1)); 12530 return; 12531 } 12532 case ISD::ATOMIC_CMP_SWAP: { 12533 EVT T = N->getValueType(0); 12534 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 12535 bool Regs64bit = T == MVT::i128; 12536 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 12537 SDValue cpInL, cpInH; 12538 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 12539 DAG.getConstant(0, HalfT)); 12540 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 12541 DAG.getConstant(1, HalfT)); 12542 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 12543 Regs64bit ? X86::RAX : X86::EAX, 12544 cpInL, SDValue()); 12545 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 12546 Regs64bit ? X86::RDX : X86::EDX, 12547 cpInH, cpInL.getValue(1)); 12548 SDValue swapInL, swapInH; 12549 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 12550 DAG.getConstant(0, HalfT)); 12551 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 12552 DAG.getConstant(1, HalfT)); 12553 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 12554 Regs64bit ? X86::RBX : X86::EBX, 12555 swapInL, cpInH.getValue(1)); 12556 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 12557 Regs64bit ? X86::RCX : X86::ECX, 12558 swapInH, swapInL.getValue(1)); 12559 SDValue Ops[] = { swapInH.getValue(0), 12560 N->getOperand(1), 12561 swapInH.getValue(1) }; 12562 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 12563 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 12564 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 12565 X86ISD::LCMPXCHG8_DAG; 12566 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 12567 Ops, 3, T, MMO); 12568 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 12569 Regs64bit ? X86::RAX : X86::EAX, 12570 HalfT, Result.getValue(1)); 12571 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 12572 Regs64bit ? X86::RDX : X86::EDX, 12573 HalfT, cpOutL.getValue(2)); 12574 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 12575 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 12576 Results.push_back(cpOutH.getValue(1)); 12577 return; 12578 } 12579 case ISD::ATOMIC_LOAD_ADD: 12580 case ISD::ATOMIC_LOAD_AND: 12581 case ISD::ATOMIC_LOAD_NAND: 12582 case ISD::ATOMIC_LOAD_OR: 12583 case ISD::ATOMIC_LOAD_SUB: 12584 case ISD::ATOMIC_LOAD_XOR: 12585 case ISD::ATOMIC_LOAD_MAX: 12586 case ISD::ATOMIC_LOAD_MIN: 12587 case ISD::ATOMIC_LOAD_UMAX: 12588 case ISD::ATOMIC_LOAD_UMIN: 12589 case ISD::ATOMIC_SWAP: { 12590 unsigned Opc; 12591 switch (N->getOpcode()) { 12592 default: llvm_unreachable("Unexpected opcode"); 12593 case ISD::ATOMIC_LOAD_ADD: 12594 Opc = X86ISD::ATOMADD64_DAG; 12595 break; 12596 case ISD::ATOMIC_LOAD_AND: 12597 Opc = X86ISD::ATOMAND64_DAG; 12598 break; 12599 case ISD::ATOMIC_LOAD_NAND: 12600 Opc = X86ISD::ATOMNAND64_DAG; 12601 break; 12602 case ISD::ATOMIC_LOAD_OR: 12603 Opc = X86ISD::ATOMOR64_DAG; 12604 break; 12605 case ISD::ATOMIC_LOAD_SUB: 12606 Opc = X86ISD::ATOMSUB64_DAG; 12607 break; 12608 case ISD::ATOMIC_LOAD_XOR: 12609 Opc = X86ISD::ATOMXOR64_DAG; 12610 break; 12611 case ISD::ATOMIC_LOAD_MAX: 12612 Opc = X86ISD::ATOMMAX64_DAG; 12613 break; 12614 case ISD::ATOMIC_LOAD_MIN: 12615 Opc = X86ISD::ATOMMIN64_DAG; 12616 break; 12617 case ISD::ATOMIC_LOAD_UMAX: 12618 Opc = X86ISD::ATOMUMAX64_DAG; 12619 break; 12620 case ISD::ATOMIC_LOAD_UMIN: 12621 Opc = X86ISD::ATOMUMIN64_DAG; 12622 break; 12623 case ISD::ATOMIC_SWAP: 12624 Opc = X86ISD::ATOMSWAP64_DAG; 12625 break; 12626 } 12627 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc); 12628 return; 12629 } 12630 case ISD::ATOMIC_LOAD: 12631 ReplaceATOMIC_LOAD(N, Results, DAG); 12632 } 12633} 12634 12635const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 12636 switch (Opcode) { 12637 default: return NULL; 12638 case X86ISD::BSF: return "X86ISD::BSF"; 12639 case X86ISD::BSR: return "X86ISD::BSR"; 12640 case X86ISD::SHLD: return "X86ISD::SHLD"; 12641 case X86ISD::SHRD: return "X86ISD::SHRD"; 12642 case X86ISD::FAND: return "X86ISD::FAND"; 12643 case X86ISD::FOR: return "X86ISD::FOR"; 12644 case X86ISD::FXOR: return "X86ISD::FXOR"; 12645 case X86ISD::FSRL: return "X86ISD::FSRL"; 12646 case X86ISD::FILD: return "X86ISD::FILD"; 12647 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 12648 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 12649 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 12650 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 12651 case X86ISD::FLD: return "X86ISD::FLD"; 12652 case X86ISD::FST: return "X86ISD::FST"; 12653 case X86ISD::CALL: return "X86ISD::CALL"; 12654 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 12655 case X86ISD::BT: return "X86ISD::BT"; 12656 case X86ISD::CMP: return "X86ISD::CMP"; 12657 case X86ISD::COMI: return "X86ISD::COMI"; 12658 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 12659 case X86ISD::SETCC: return "X86ISD::SETCC"; 12660 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 12661 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 12662 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 12663 case X86ISD::CMOV: return "X86ISD::CMOV"; 12664 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 12665 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 12666 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 12667 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 12668 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 12669 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 12670 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 12671 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 12672 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 12673 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 12674 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 12675 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 12676 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 12677 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 12678 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 12679 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 12680 case X86ISD::BLENDI: return "X86ISD::BLENDI"; 12681 case X86ISD::SUBUS: return "X86ISD::SUBUS"; 12682 case X86ISD::HADD: return "X86ISD::HADD"; 12683 case X86ISD::HSUB: return "X86ISD::HSUB"; 12684 case X86ISD::FHADD: return "X86ISD::FHADD"; 12685 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 12686 case X86ISD::UMAX: return "X86ISD::UMAX"; 12687 case X86ISD::UMIN: return "X86ISD::UMIN"; 12688 case X86ISD::SMAX: return "X86ISD::SMAX"; 12689 case X86ISD::SMIN: return "X86ISD::SMIN"; 12690 case X86ISD::FMAX: return "X86ISD::FMAX"; 12691 case X86ISD::FMIN: return "X86ISD::FMIN"; 12692 case X86ISD::FMAXC: return "X86ISD::FMAXC"; 12693 case X86ISD::FMINC: return "X86ISD::FMINC"; 12694 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 12695 case X86ISD::FRCP: return "X86ISD::FRCP"; 12696 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 12697 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR"; 12698 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 12699 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP"; 12700 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP"; 12701 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 12702 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 12703 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 12704 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r"; 12705 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 12706 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 12707 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 12708 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 12709 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 12710 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 12711 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 12712 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 12713 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 12714 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL"; 12715 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 12716 case X86ISD::VZEXT: return "X86ISD::VZEXT"; 12717 case X86ISD::VSEXT: return "X86ISD::VSEXT"; 12718 case X86ISD::VFPEXT: return "X86ISD::VFPEXT"; 12719 case X86ISD::VFPROUND: return "X86ISD::VFPROUND"; 12720 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 12721 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 12722 case X86ISD::VSHL: return "X86ISD::VSHL"; 12723 case X86ISD::VSRL: return "X86ISD::VSRL"; 12724 case X86ISD::VSRA: return "X86ISD::VSRA"; 12725 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 12726 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 12727 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 12728 case X86ISD::CMPP: return "X86ISD::CMPP"; 12729 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 12730 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 12731 case X86ISD::ADD: return "X86ISD::ADD"; 12732 case X86ISD::SUB: return "X86ISD::SUB"; 12733 case X86ISD::ADC: return "X86ISD::ADC"; 12734 case X86ISD::SBB: return "X86ISD::SBB"; 12735 case X86ISD::SMUL: return "X86ISD::SMUL"; 12736 case X86ISD::UMUL: return "X86ISD::UMUL"; 12737 case X86ISD::INC: return "X86ISD::INC"; 12738 case X86ISD::DEC: return "X86ISD::DEC"; 12739 case X86ISD::OR: return "X86ISD::OR"; 12740 case X86ISD::XOR: return "X86ISD::XOR"; 12741 case X86ISD::AND: return "X86ISD::AND"; 12742 case X86ISD::BLSI: return "X86ISD::BLSI"; 12743 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 12744 case X86ISD::BLSR: return "X86ISD::BLSR"; 12745 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 12746 case X86ISD::PTEST: return "X86ISD::PTEST"; 12747 case X86ISD::TESTP: return "X86ISD::TESTP"; 12748 case X86ISD::PALIGNR: return "X86ISD::PALIGNR"; 12749 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 12750 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 12751 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 12752 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 12753 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 12754 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 12755 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 12756 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 12757 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 12758 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 12759 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 12760 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 12761 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 12762 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 12763 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 12764 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 12765 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 12766 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 12767 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 12768 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 12769 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 12770 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 12771 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 12772 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 12773 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 12774 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 12775 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 12776 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 12777 case X86ISD::SAHF: return "X86ISD::SAHF"; 12778 case X86ISD::RDRAND: return "X86ISD::RDRAND"; 12779 case X86ISD::FMADD: return "X86ISD::FMADD"; 12780 case X86ISD::FMSUB: return "X86ISD::FMSUB"; 12781 case X86ISD::FNMADD: return "X86ISD::FNMADD"; 12782 case X86ISD::FNMSUB: return "X86ISD::FNMSUB"; 12783 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB"; 12784 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD"; 12785 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI"; 12786 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI"; 12787 case X86ISD::XTEST: return "X86ISD::XTEST"; 12788 } 12789} 12790 12791// isLegalAddressingMode - Return true if the addressing mode represented 12792// by AM is legal for this target, for a load/store of the specified type. 12793bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 12794 Type *Ty) const { 12795 // X86 supports extremely general addressing modes. 12796 CodeModel::Model M = getTargetMachine().getCodeModel(); 12797 Reloc::Model R = getTargetMachine().getRelocationModel(); 12798 12799 // X86 allows a sign-extended 32-bit immediate field as a displacement. 12800 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 12801 return false; 12802 12803 if (AM.BaseGV) { 12804 unsigned GVFlags = 12805 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 12806 12807 // If a reference to this global requires an extra load, we can't fold it. 12808 if (isGlobalStubReference(GVFlags)) 12809 return false; 12810 12811 // If BaseGV requires a register for the PIC base, we cannot also have a 12812 // BaseReg specified. 12813 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 12814 return false; 12815 12816 // If lower 4G is not available, then we must use rip-relative addressing. 12817 if ((M != CodeModel::Small || R != Reloc::Static) && 12818 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 12819 return false; 12820 } 12821 12822 switch (AM.Scale) { 12823 case 0: 12824 case 1: 12825 case 2: 12826 case 4: 12827 case 8: 12828 // These scales always work. 12829 break; 12830 case 3: 12831 case 5: 12832 case 9: 12833 // These scales are formed with basereg+scalereg. Only accept if there is 12834 // no basereg yet. 12835 if (AM.HasBaseReg) 12836 return false; 12837 break; 12838 default: // Other stuff never works. 12839 return false; 12840 } 12841 12842 return true; 12843} 12844 12845bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 12846 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 12847 return false; 12848 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 12849 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 12850 return NumBits1 > NumBits2; 12851} 12852 12853bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const { 12854 return isInt<32>(Imm); 12855} 12856 12857bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const { 12858 // Can also use sub to handle negated immediates. 12859 return isInt<32>(Imm); 12860} 12861 12862bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 12863 if (!VT1.isInteger() || !VT2.isInteger()) 12864 return false; 12865 unsigned NumBits1 = VT1.getSizeInBits(); 12866 unsigned NumBits2 = VT2.getSizeInBits(); 12867 return NumBits1 > NumBits2; 12868} 12869 12870bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 12871 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 12872 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 12873} 12874 12875bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 12876 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 12877 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 12878} 12879 12880bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 12881 EVT VT1 = Val.getValueType(); 12882 if (isZExtFree(VT1, VT2)) 12883 return true; 12884 12885 if (Val.getOpcode() != ISD::LOAD) 12886 return false; 12887 12888 if (!VT1.isSimple() || !VT1.isInteger() || 12889 !VT2.isSimple() || !VT2.isInteger()) 12890 return false; 12891 12892 switch (VT1.getSimpleVT().SimpleTy) { 12893 default: break; 12894 case MVT::i8: 12895 case MVT::i16: 12896 case MVT::i32: 12897 // X86 has 8, 16, and 32-bit zero-extending loads. 12898 return true; 12899 } 12900 12901 return false; 12902} 12903 12904bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 12905 // i16 instructions are longer (0x66 prefix) and potentially slower. 12906 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 12907} 12908 12909/// isShuffleMaskLegal - Targets can use this to indicate that they only 12910/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 12911/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 12912/// are assumed to be legal. 12913bool 12914X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 12915 EVT VT) const { 12916 // Very little shuffling can be done for 64-bit vectors right now. 12917 if (VT.getSizeInBits() == 64) 12918 return false; 12919 12920 // FIXME: pshufb, blends, shifts. 12921 return (VT.getVectorNumElements() == 2 || 12922 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 12923 isMOVLMask(M, VT) || 12924 isSHUFPMask(M, VT, Subtarget->hasFp256()) || 12925 isPSHUFDMask(M, VT) || 12926 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) || 12927 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) || 12928 isPALIGNRMask(M, VT, Subtarget) || 12929 isUNPCKLMask(M, VT, Subtarget->hasInt256()) || 12930 isUNPCKHMask(M, VT, Subtarget->hasInt256()) || 12931 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) || 12932 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256())); 12933} 12934 12935bool 12936X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 12937 EVT VT) const { 12938 unsigned NumElts = VT.getVectorNumElements(); 12939 // FIXME: This collection of masks seems suspect. 12940 if (NumElts == 2) 12941 return true; 12942 if (NumElts == 4 && VT.is128BitVector()) { 12943 return (isMOVLMask(Mask, VT) || 12944 isCommutedMOVLMask(Mask, VT, true) || 12945 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) || 12946 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true)); 12947 } 12948 return false; 12949} 12950 12951//===----------------------------------------------------------------------===// 12952// X86 Scheduler Hooks 12953//===----------------------------------------------------------------------===// 12954 12955/// Utility function to emit xbegin specifying the start of an RTM region. 12956static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB, 12957 const TargetInstrInfo *TII) { 12958 DebugLoc DL = MI->getDebugLoc(); 12959 12960 const BasicBlock *BB = MBB->getBasicBlock(); 12961 MachineFunction::iterator I = MBB; 12962 ++I; 12963 12964 // For the v = xbegin(), we generate 12965 // 12966 // thisMBB: 12967 // xbegin sinkMBB 12968 // 12969 // mainMBB: 12970 // eax = -1 12971 // 12972 // sinkMBB: 12973 // v = eax 12974 12975 MachineBasicBlock *thisMBB = MBB; 12976 MachineFunction *MF = MBB->getParent(); 12977 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 12978 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 12979 MF->insert(I, mainMBB); 12980 MF->insert(I, sinkMBB); 12981 12982 // Transfer the remainder of BB and its successor edges to sinkMBB. 12983 sinkMBB->splice(sinkMBB->begin(), MBB, 12984 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 12985 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 12986 12987 // thisMBB: 12988 // xbegin sinkMBB 12989 // # fallthrough to mainMBB 12990 // # abortion to sinkMBB 12991 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB); 12992 thisMBB->addSuccessor(mainMBB); 12993 thisMBB->addSuccessor(sinkMBB); 12994 12995 // mainMBB: 12996 // EAX = -1 12997 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1); 12998 mainMBB->addSuccessor(sinkMBB); 12999 13000 // sinkMBB: 13001 // EAX is live into the sinkMBB 13002 sinkMBB->addLiveIn(X86::EAX); 13003 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 13004 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 13005 .addReg(X86::EAX); 13006 13007 MI->eraseFromParent(); 13008 return sinkMBB; 13009} 13010 13011// Get CMPXCHG opcode for the specified data type. 13012static unsigned getCmpXChgOpcode(EVT VT) { 13013 switch (VT.getSimpleVT().SimpleTy) { 13014 case MVT::i8: return X86::LCMPXCHG8; 13015 case MVT::i16: return X86::LCMPXCHG16; 13016 case MVT::i32: return X86::LCMPXCHG32; 13017 case MVT::i64: return X86::LCMPXCHG64; 13018 default: 13019 break; 13020 } 13021 llvm_unreachable("Invalid operand size!"); 13022} 13023 13024// Get LOAD opcode for the specified data type. 13025static unsigned getLoadOpcode(EVT VT) { 13026 switch (VT.getSimpleVT().SimpleTy) { 13027 case MVT::i8: return X86::MOV8rm; 13028 case MVT::i16: return X86::MOV16rm; 13029 case MVT::i32: return X86::MOV32rm; 13030 case MVT::i64: return X86::MOV64rm; 13031 default: 13032 break; 13033 } 13034 llvm_unreachable("Invalid operand size!"); 13035} 13036 13037// Get opcode of the non-atomic one from the specified atomic instruction. 13038static unsigned getNonAtomicOpcode(unsigned Opc) { 13039 switch (Opc) { 13040 case X86::ATOMAND8: return X86::AND8rr; 13041 case X86::ATOMAND16: return X86::AND16rr; 13042 case X86::ATOMAND32: return X86::AND32rr; 13043 case X86::ATOMAND64: return X86::AND64rr; 13044 case X86::ATOMOR8: return X86::OR8rr; 13045 case X86::ATOMOR16: return X86::OR16rr; 13046 case X86::ATOMOR32: return X86::OR32rr; 13047 case X86::ATOMOR64: return X86::OR64rr; 13048 case X86::ATOMXOR8: return X86::XOR8rr; 13049 case X86::ATOMXOR16: return X86::XOR16rr; 13050 case X86::ATOMXOR32: return X86::XOR32rr; 13051 case X86::ATOMXOR64: return X86::XOR64rr; 13052 } 13053 llvm_unreachable("Unhandled atomic-load-op opcode!"); 13054} 13055 13056// Get opcode of the non-atomic one from the specified atomic instruction with 13057// extra opcode. 13058static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc, 13059 unsigned &ExtraOpc) { 13060 switch (Opc) { 13061 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr; 13062 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr; 13063 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr; 13064 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr; 13065 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr; 13066 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr; 13067 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr; 13068 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr; 13069 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr; 13070 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr; 13071 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr; 13072 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr; 13073 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr; 13074 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr; 13075 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr; 13076 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr; 13077 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr; 13078 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr; 13079 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr; 13080 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr; 13081 } 13082 llvm_unreachable("Unhandled atomic-load-op opcode!"); 13083} 13084 13085// Get opcode of the non-atomic one from the specified atomic instruction for 13086// 64-bit data type on 32-bit target. 13087static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) { 13088 switch (Opc) { 13089 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr; 13090 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr; 13091 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr; 13092 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr; 13093 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr; 13094 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr; 13095 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr; 13096 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr; 13097 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr; 13098 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr; 13099 } 13100 llvm_unreachable("Unhandled atomic-load-op opcode!"); 13101} 13102 13103// Get opcode of the non-atomic one from the specified atomic instruction for 13104// 64-bit data type on 32-bit target with extra opcode. 13105static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc, 13106 unsigned &HiOpc, 13107 unsigned &ExtraOpc) { 13108 switch (Opc) { 13109 case X86::ATOMNAND6432: 13110 ExtraOpc = X86::NOT32r; 13111 HiOpc = X86::AND32rr; 13112 return X86::AND32rr; 13113 } 13114 llvm_unreachable("Unhandled atomic-load-op opcode!"); 13115} 13116 13117// Get pseudo CMOV opcode from the specified data type. 13118static unsigned getPseudoCMOVOpc(EVT VT) { 13119 switch (VT.getSimpleVT().SimpleTy) { 13120 case MVT::i8: return X86::CMOV_GR8; 13121 case MVT::i16: return X86::CMOV_GR16; 13122 case MVT::i32: return X86::CMOV_GR32; 13123 default: 13124 break; 13125 } 13126 llvm_unreachable("Unknown CMOV opcode!"); 13127} 13128 13129// EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions. 13130// They will be translated into a spin-loop or compare-exchange loop from 13131// 13132// ... 13133// dst = atomic-fetch-op MI.addr, MI.val 13134// ... 13135// 13136// to 13137// 13138// ... 13139// t1 = LOAD MI.addr 13140// loop: 13141// t4 = phi(t1, t3 / loop) 13142// t2 = OP MI.val, t4 13143// EAX = t4 13144// LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined] 13145// t3 = EAX 13146// JNE loop 13147// sink: 13148// dst = t3 13149// ... 13150MachineBasicBlock * 13151X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI, 13152 MachineBasicBlock *MBB) const { 13153 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13154 DebugLoc DL = MI->getDebugLoc(); 13155 13156 MachineFunction *MF = MBB->getParent(); 13157 MachineRegisterInfo &MRI = MF->getRegInfo(); 13158 13159 const BasicBlock *BB = MBB->getBasicBlock(); 13160 MachineFunction::iterator I = MBB; 13161 ++I; 13162 13163 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 && 13164 "Unexpected number of operands"); 13165 13166 assert(MI->hasOneMemOperand() && 13167 "Expected atomic-load-op to have one memoperand"); 13168 13169 // Memory Reference 13170 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 13171 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 13172 13173 unsigned DstReg, SrcReg; 13174 unsigned MemOpndSlot; 13175 13176 unsigned CurOp = 0; 13177 13178 DstReg = MI->getOperand(CurOp++).getReg(); 13179 MemOpndSlot = CurOp; 13180 CurOp += X86::AddrNumOperands; 13181 SrcReg = MI->getOperand(CurOp++).getReg(); 13182 13183 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 13184 MVT::SimpleValueType VT = *RC->vt_begin(); 13185 unsigned t1 = MRI.createVirtualRegister(RC); 13186 unsigned t2 = MRI.createVirtualRegister(RC); 13187 unsigned t3 = MRI.createVirtualRegister(RC); 13188 unsigned t4 = MRI.createVirtualRegister(RC); 13189 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT); 13190 13191 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT); 13192 unsigned LOADOpc = getLoadOpcode(VT); 13193 13194 // For the atomic load-arith operator, we generate 13195 // 13196 // thisMBB: 13197 // t1 = LOAD [MI.addr] 13198 // mainMBB: 13199 // t4 = phi(t1 / thisMBB, t3 / mainMBB) 13200 // t1 = OP MI.val, EAX 13201 // EAX = t4 13202 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] 13203 // t3 = EAX 13204 // JNE mainMBB 13205 // sinkMBB: 13206 // dst = t3 13207 13208 MachineBasicBlock *thisMBB = MBB; 13209 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 13210 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 13211 MF->insert(I, mainMBB); 13212 MF->insert(I, sinkMBB); 13213 13214 MachineInstrBuilder MIB; 13215 13216 // Transfer the remainder of BB and its successor edges to sinkMBB. 13217 sinkMBB->splice(sinkMBB->begin(), MBB, 13218 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 13219 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 13220 13221 // thisMBB: 13222 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1); 13223 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 13224 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 13225 if (NewMO.isReg()) 13226 NewMO.setIsKill(false); 13227 MIB.addOperand(NewMO); 13228 } 13229 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) { 13230 unsigned flags = (*MMOI)->getFlags(); 13231 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad; 13232 MachineMemOperand *MMO = 13233 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags, 13234 (*MMOI)->getSize(), 13235 (*MMOI)->getBaseAlignment(), 13236 (*MMOI)->getTBAAInfo(), 13237 (*MMOI)->getRanges()); 13238 MIB.addMemOperand(MMO); 13239 } 13240 13241 thisMBB->addSuccessor(mainMBB); 13242 13243 // mainMBB: 13244 MachineBasicBlock *origMainMBB = mainMBB; 13245 13246 // Add a PHI. 13247 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4) 13248 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB); 13249 13250 unsigned Opc = MI->getOpcode(); 13251 switch (Opc) { 13252 default: 13253 llvm_unreachable("Unhandled atomic-load-op opcode!"); 13254 case X86::ATOMAND8: 13255 case X86::ATOMAND16: 13256 case X86::ATOMAND32: 13257 case X86::ATOMAND64: 13258 case X86::ATOMOR8: 13259 case X86::ATOMOR16: 13260 case X86::ATOMOR32: 13261 case X86::ATOMOR64: 13262 case X86::ATOMXOR8: 13263 case X86::ATOMXOR16: 13264 case X86::ATOMXOR32: 13265 case X86::ATOMXOR64: { 13266 unsigned ARITHOpc = getNonAtomicOpcode(Opc); 13267 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg) 13268 .addReg(t4); 13269 break; 13270 } 13271 case X86::ATOMNAND8: 13272 case X86::ATOMNAND16: 13273 case X86::ATOMNAND32: 13274 case X86::ATOMNAND64: { 13275 unsigned Tmp = MRI.createVirtualRegister(RC); 13276 unsigned NOTOpc; 13277 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc); 13278 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg) 13279 .addReg(t4); 13280 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp); 13281 break; 13282 } 13283 case X86::ATOMMAX8: 13284 case X86::ATOMMAX16: 13285 case X86::ATOMMAX32: 13286 case X86::ATOMMAX64: 13287 case X86::ATOMMIN8: 13288 case X86::ATOMMIN16: 13289 case X86::ATOMMIN32: 13290 case X86::ATOMMIN64: 13291 case X86::ATOMUMAX8: 13292 case X86::ATOMUMAX16: 13293 case X86::ATOMUMAX32: 13294 case X86::ATOMUMAX64: 13295 case X86::ATOMUMIN8: 13296 case X86::ATOMUMIN16: 13297 case X86::ATOMUMIN32: 13298 case X86::ATOMUMIN64: { 13299 unsigned CMPOpc; 13300 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc); 13301 13302 BuildMI(mainMBB, DL, TII->get(CMPOpc)) 13303 .addReg(SrcReg) 13304 .addReg(t4); 13305 13306 if (Subtarget->hasCMov()) { 13307 if (VT != MVT::i8) { 13308 // Native support 13309 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2) 13310 .addReg(SrcReg) 13311 .addReg(t4); 13312 } else { 13313 // Promote i8 to i32 to use CMOV32 13314 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 13315 const TargetRegisterClass *RC32 = 13316 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit); 13317 unsigned SrcReg32 = MRI.createVirtualRegister(RC32); 13318 unsigned AccReg32 = MRI.createVirtualRegister(RC32); 13319 unsigned Tmp = MRI.createVirtualRegister(RC32); 13320 13321 unsigned Undef = MRI.createVirtualRegister(RC32); 13322 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef); 13323 13324 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32) 13325 .addReg(Undef) 13326 .addReg(SrcReg) 13327 .addImm(X86::sub_8bit); 13328 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32) 13329 .addReg(Undef) 13330 .addReg(t4) 13331 .addImm(X86::sub_8bit); 13332 13333 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp) 13334 .addReg(SrcReg32) 13335 .addReg(AccReg32); 13336 13337 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2) 13338 .addReg(Tmp, 0, X86::sub_8bit); 13339 } 13340 } else { 13341 // Use pseudo select and lower them. 13342 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && 13343 "Invalid atomic-load-op transformation!"); 13344 unsigned SelOpc = getPseudoCMOVOpc(VT); 13345 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc); 13346 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!"); 13347 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2) 13348 .addReg(SrcReg).addReg(t4) 13349 .addImm(CC); 13350 mainMBB = EmitLoweredSelect(MIB, mainMBB); 13351 // Replace the original PHI node as mainMBB is changed after CMOV 13352 // lowering. 13353 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4) 13354 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB); 13355 Phi->eraseFromParent(); 13356 } 13357 break; 13358 } 13359 } 13360 13361 // Copy PhyReg back from virtual register. 13362 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg) 13363 .addReg(t4); 13364 13365 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc)); 13366 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 13367 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 13368 if (NewMO.isReg()) 13369 NewMO.setIsKill(false); 13370 MIB.addOperand(NewMO); 13371 } 13372 MIB.addReg(t2); 13373 MIB.setMemRefs(MMOBegin, MMOEnd); 13374 13375 // Copy PhyReg back to virtual register. 13376 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3) 13377 .addReg(PhyReg); 13378 13379 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB); 13380 13381 mainMBB->addSuccessor(origMainMBB); 13382 mainMBB->addSuccessor(sinkMBB); 13383 13384 // sinkMBB: 13385 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 13386 TII->get(TargetOpcode::COPY), DstReg) 13387 .addReg(t3); 13388 13389 MI->eraseFromParent(); 13390 return sinkMBB; 13391} 13392 13393// EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic 13394// instructions. They will be translated into a spin-loop or compare-exchange 13395// loop from 13396// 13397// ... 13398// dst = atomic-fetch-op MI.addr, MI.val 13399// ... 13400// 13401// to 13402// 13403// ... 13404// t1L = LOAD [MI.addr + 0] 13405// t1H = LOAD [MI.addr + 4] 13406// loop: 13407// t4L = phi(t1L, t3L / loop) 13408// t4H = phi(t1H, t3H / loop) 13409// t2L = OP MI.val.lo, t4L 13410// t2H = OP MI.val.hi, t4H 13411// EAX = t4L 13412// EDX = t4H 13413// EBX = t2L 13414// ECX = t2H 13415// LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined] 13416// t3L = EAX 13417// t3H = EDX 13418// JNE loop 13419// sink: 13420// dstL = t3L 13421// dstH = t3H 13422// ... 13423MachineBasicBlock * 13424X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI, 13425 MachineBasicBlock *MBB) const { 13426 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13427 DebugLoc DL = MI->getDebugLoc(); 13428 13429 MachineFunction *MF = MBB->getParent(); 13430 MachineRegisterInfo &MRI = MF->getRegInfo(); 13431 13432 const BasicBlock *BB = MBB->getBasicBlock(); 13433 MachineFunction::iterator I = MBB; 13434 ++I; 13435 13436 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 && 13437 "Unexpected number of operands"); 13438 13439 assert(MI->hasOneMemOperand() && 13440 "Expected atomic-load-op32 to have one memoperand"); 13441 13442 // Memory Reference 13443 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 13444 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 13445 13446 unsigned DstLoReg, DstHiReg; 13447 unsigned SrcLoReg, SrcHiReg; 13448 unsigned MemOpndSlot; 13449 13450 unsigned CurOp = 0; 13451 13452 DstLoReg = MI->getOperand(CurOp++).getReg(); 13453 DstHiReg = MI->getOperand(CurOp++).getReg(); 13454 MemOpndSlot = CurOp; 13455 CurOp += X86::AddrNumOperands; 13456 SrcLoReg = MI->getOperand(CurOp++).getReg(); 13457 SrcHiReg = MI->getOperand(CurOp++).getReg(); 13458 13459 const TargetRegisterClass *RC = &X86::GR32RegClass; 13460 const TargetRegisterClass *RC8 = &X86::GR8RegClass; 13461 13462 unsigned t1L = MRI.createVirtualRegister(RC); 13463 unsigned t1H = MRI.createVirtualRegister(RC); 13464 unsigned t2L = MRI.createVirtualRegister(RC); 13465 unsigned t2H = MRI.createVirtualRegister(RC); 13466 unsigned t3L = MRI.createVirtualRegister(RC); 13467 unsigned t3H = MRI.createVirtualRegister(RC); 13468 unsigned t4L = MRI.createVirtualRegister(RC); 13469 unsigned t4H = MRI.createVirtualRegister(RC); 13470 13471 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B; 13472 unsigned LOADOpc = X86::MOV32rm; 13473 13474 // For the atomic load-arith operator, we generate 13475 // 13476 // thisMBB: 13477 // t1L = LOAD [MI.addr + 0] 13478 // t1H = LOAD [MI.addr + 4] 13479 // mainMBB: 13480 // t4L = phi(t1L / thisMBB, t3L / mainMBB) 13481 // t4H = phi(t1H / thisMBB, t3H / mainMBB) 13482 // t2L = OP MI.val.lo, t4L 13483 // t2H = OP MI.val.hi, t4H 13484 // EBX = t2L 13485 // ECX = t2H 13486 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined] 13487 // t3L = EAX 13488 // t3H = EDX 13489 // JNE loop 13490 // sinkMBB: 13491 // dstL = t3L 13492 // dstH = t3H 13493 13494 MachineBasicBlock *thisMBB = MBB; 13495 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 13496 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 13497 MF->insert(I, mainMBB); 13498 MF->insert(I, sinkMBB); 13499 13500 MachineInstrBuilder MIB; 13501 13502 // Transfer the remainder of BB and its successor edges to sinkMBB. 13503 sinkMBB->splice(sinkMBB->begin(), MBB, 13504 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 13505 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 13506 13507 // thisMBB: 13508 // Lo 13509 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L); 13510 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 13511 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 13512 if (NewMO.isReg()) 13513 NewMO.setIsKill(false); 13514 MIB.addOperand(NewMO); 13515 } 13516 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) { 13517 unsigned flags = (*MMOI)->getFlags(); 13518 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad; 13519 MachineMemOperand *MMO = 13520 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags, 13521 (*MMOI)->getSize(), 13522 (*MMOI)->getBaseAlignment(), 13523 (*MMOI)->getTBAAInfo(), 13524 (*MMOI)->getRanges()); 13525 MIB.addMemOperand(MMO); 13526 }; 13527 MachineInstr *LowMI = MIB; 13528 13529 // Hi 13530 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H); 13531 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 13532 if (i == X86::AddrDisp) { 13533 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32) 13534 } else { 13535 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 13536 if (NewMO.isReg()) 13537 NewMO.setIsKill(false); 13538 MIB.addOperand(NewMO); 13539 } 13540 } 13541 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end()); 13542 13543 thisMBB->addSuccessor(mainMBB); 13544 13545 // mainMBB: 13546 MachineBasicBlock *origMainMBB = mainMBB; 13547 13548 // Add PHIs. 13549 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L) 13550 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB); 13551 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H) 13552 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB); 13553 13554 unsigned Opc = MI->getOpcode(); 13555 switch (Opc) { 13556 default: 13557 llvm_unreachable("Unhandled atomic-load-op6432 opcode!"); 13558 case X86::ATOMAND6432: 13559 case X86::ATOMOR6432: 13560 case X86::ATOMXOR6432: 13561 case X86::ATOMADD6432: 13562 case X86::ATOMSUB6432: { 13563 unsigned HiOpc; 13564 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 13565 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L) 13566 .addReg(SrcLoReg); 13567 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H) 13568 .addReg(SrcHiReg); 13569 break; 13570 } 13571 case X86::ATOMNAND6432: { 13572 unsigned HiOpc, NOTOpc; 13573 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc); 13574 unsigned TmpL = MRI.createVirtualRegister(RC); 13575 unsigned TmpH = MRI.createVirtualRegister(RC); 13576 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg) 13577 .addReg(t4L); 13578 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg) 13579 .addReg(t4H); 13580 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL); 13581 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH); 13582 break; 13583 } 13584 case X86::ATOMMAX6432: 13585 case X86::ATOMMIN6432: 13586 case X86::ATOMUMAX6432: 13587 case X86::ATOMUMIN6432: { 13588 unsigned HiOpc; 13589 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 13590 unsigned cL = MRI.createVirtualRegister(RC8); 13591 unsigned cH = MRI.createVirtualRegister(RC8); 13592 unsigned cL32 = MRI.createVirtualRegister(RC); 13593 unsigned cH32 = MRI.createVirtualRegister(RC); 13594 unsigned cc = MRI.createVirtualRegister(RC); 13595 // cl := cmp src_lo, lo 13596 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr)) 13597 .addReg(SrcLoReg).addReg(t4L); 13598 BuildMI(mainMBB, DL, TII->get(LoOpc), cL); 13599 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL); 13600 // ch := cmp src_hi, hi 13601 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr)) 13602 .addReg(SrcHiReg).addReg(t4H); 13603 BuildMI(mainMBB, DL, TII->get(HiOpc), cH); 13604 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH); 13605 // cc := if (src_hi == hi) ? cl : ch; 13606 if (Subtarget->hasCMov()) { 13607 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc) 13608 .addReg(cH32).addReg(cL32); 13609 } else { 13610 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc) 13611 .addReg(cH32).addReg(cL32) 13612 .addImm(X86::COND_E); 13613 mainMBB = EmitLoweredSelect(MIB, mainMBB); 13614 } 13615 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc); 13616 if (Subtarget->hasCMov()) { 13617 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L) 13618 .addReg(SrcLoReg).addReg(t4L); 13619 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H) 13620 .addReg(SrcHiReg).addReg(t4H); 13621 } else { 13622 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L) 13623 .addReg(SrcLoReg).addReg(t4L) 13624 .addImm(X86::COND_NE); 13625 mainMBB = EmitLoweredSelect(MIB, mainMBB); 13626 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the 13627 // 2nd CMOV lowering. 13628 mainMBB->addLiveIn(X86::EFLAGS); 13629 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H) 13630 .addReg(SrcHiReg).addReg(t4H) 13631 .addImm(X86::COND_NE); 13632 mainMBB = EmitLoweredSelect(MIB, mainMBB); 13633 // Replace the original PHI node as mainMBB is changed after CMOV 13634 // lowering. 13635 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L) 13636 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB); 13637 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H) 13638 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB); 13639 PhiL->eraseFromParent(); 13640 PhiH->eraseFromParent(); 13641 } 13642 break; 13643 } 13644 case X86::ATOMSWAP6432: { 13645 unsigned HiOpc; 13646 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 13647 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg); 13648 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg); 13649 break; 13650 } 13651 } 13652 13653 // Copy EDX:EAX back from HiReg:LoReg 13654 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L); 13655 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H); 13656 // Copy ECX:EBX from t1H:t1L 13657 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L); 13658 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H); 13659 13660 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc)); 13661 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 13662 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i); 13663 if (NewMO.isReg()) 13664 NewMO.setIsKill(false); 13665 MIB.addOperand(NewMO); 13666 } 13667 MIB.setMemRefs(MMOBegin, MMOEnd); 13668 13669 // Copy EDX:EAX back to t3H:t3L 13670 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX); 13671 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX); 13672 13673 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB); 13674 13675 mainMBB->addSuccessor(origMainMBB); 13676 mainMBB->addSuccessor(sinkMBB); 13677 13678 // sinkMBB: 13679 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 13680 TII->get(TargetOpcode::COPY), DstLoReg) 13681 .addReg(t3L); 13682 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 13683 TII->get(TargetOpcode::COPY), DstHiReg) 13684 .addReg(t3H); 13685 13686 MI->eraseFromParent(); 13687 return sinkMBB; 13688} 13689 13690// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 13691// or XMM0_V32I8 in AVX all of this code can be replaced with that 13692// in the .td file. 13693static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB, 13694 const TargetInstrInfo *TII) { 13695 unsigned Opc; 13696 switch (MI->getOpcode()) { 13697 default: llvm_unreachable("illegal opcode!"); 13698 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break; 13699 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break; 13700 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break; 13701 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break; 13702 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break; 13703 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break; 13704 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break; 13705 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break; 13706 } 13707 13708 DebugLoc dl = MI->getDebugLoc(); 13709 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 13710 13711 unsigned NumArgs = MI->getNumOperands(); 13712 for (unsigned i = 1; i < NumArgs; ++i) { 13713 MachineOperand &Op = MI->getOperand(i); 13714 if (!(Op.isReg() && Op.isImplicit())) 13715 MIB.addOperand(Op); 13716 } 13717 if (MI->hasOneMemOperand()) 13718 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 13719 13720 BuildMI(*BB, MI, dl, 13721 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 13722 .addReg(X86::XMM0); 13723 13724 MI->eraseFromParent(); 13725 return BB; 13726} 13727 13728// FIXME: Custom handling because TableGen doesn't support multiple implicit 13729// defs in an instruction pattern 13730static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB, 13731 const TargetInstrInfo *TII) { 13732 unsigned Opc; 13733 switch (MI->getOpcode()) { 13734 default: llvm_unreachable("illegal opcode!"); 13735 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break; 13736 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break; 13737 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break; 13738 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break; 13739 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break; 13740 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break; 13741 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break; 13742 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break; 13743 } 13744 13745 DebugLoc dl = MI->getDebugLoc(); 13746 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 13747 13748 unsigned NumArgs = MI->getNumOperands(); // remove the results 13749 for (unsigned i = 1; i < NumArgs; ++i) { 13750 MachineOperand &Op = MI->getOperand(i); 13751 if (!(Op.isReg() && Op.isImplicit())) 13752 MIB.addOperand(Op); 13753 } 13754 if (MI->hasOneMemOperand()) 13755 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 13756 13757 BuildMI(*BB, MI, dl, 13758 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 13759 .addReg(X86::ECX); 13760 13761 MI->eraseFromParent(); 13762 return BB; 13763} 13764 13765static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB, 13766 const TargetInstrInfo *TII, 13767 const X86Subtarget* Subtarget) { 13768 DebugLoc dl = MI->getDebugLoc(); 13769 13770 // Address into RAX/EAX, other two args into ECX, EDX. 13771 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 13772 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 13773 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 13774 for (int i = 0; i < X86::AddrNumOperands; ++i) 13775 MIB.addOperand(MI->getOperand(i)); 13776 13777 unsigned ValOps = X86::AddrNumOperands; 13778 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 13779 .addReg(MI->getOperand(ValOps).getReg()); 13780 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 13781 .addReg(MI->getOperand(ValOps+1).getReg()); 13782 13783 // The instruction doesn't actually take any operands though. 13784 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 13785 13786 MI->eraseFromParent(); // The pseudo is gone now. 13787 return BB; 13788} 13789 13790MachineBasicBlock * 13791X86TargetLowering::EmitVAARG64WithCustomInserter( 13792 MachineInstr *MI, 13793 MachineBasicBlock *MBB) const { 13794 // Emit va_arg instruction on X86-64. 13795 13796 // Operands to this pseudo-instruction: 13797 // 0 ) Output : destination address (reg) 13798 // 1-5) Input : va_list address (addr, i64mem) 13799 // 6 ) ArgSize : Size (in bytes) of vararg type 13800 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 13801 // 8 ) Align : Alignment of type 13802 // 9 ) EFLAGS (implicit-def) 13803 13804 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 13805 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 13806 13807 unsigned DestReg = MI->getOperand(0).getReg(); 13808 MachineOperand &Base = MI->getOperand(1); 13809 MachineOperand &Scale = MI->getOperand(2); 13810 MachineOperand &Index = MI->getOperand(3); 13811 MachineOperand &Disp = MI->getOperand(4); 13812 MachineOperand &Segment = MI->getOperand(5); 13813 unsigned ArgSize = MI->getOperand(6).getImm(); 13814 unsigned ArgMode = MI->getOperand(7).getImm(); 13815 unsigned Align = MI->getOperand(8).getImm(); 13816 13817 // Memory Reference 13818 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 13819 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 13820 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 13821 13822 // Machine Information 13823 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13824 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 13825 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 13826 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 13827 DebugLoc DL = MI->getDebugLoc(); 13828 13829 // struct va_list { 13830 // i32 gp_offset 13831 // i32 fp_offset 13832 // i64 overflow_area (address) 13833 // i64 reg_save_area (address) 13834 // } 13835 // sizeof(va_list) = 24 13836 // alignment(va_list) = 8 13837 13838 unsigned TotalNumIntRegs = 6; 13839 unsigned TotalNumXMMRegs = 8; 13840 bool UseGPOffset = (ArgMode == 1); 13841 bool UseFPOffset = (ArgMode == 2); 13842 unsigned MaxOffset = TotalNumIntRegs * 8 + 13843 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 13844 13845 /* Align ArgSize to a multiple of 8 */ 13846 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 13847 bool NeedsAlign = (Align > 8); 13848 13849 MachineBasicBlock *thisMBB = MBB; 13850 MachineBasicBlock *overflowMBB; 13851 MachineBasicBlock *offsetMBB; 13852 MachineBasicBlock *endMBB; 13853 13854 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 13855 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 13856 unsigned OffsetReg = 0; 13857 13858 if (!UseGPOffset && !UseFPOffset) { 13859 // If we only pull from the overflow region, we don't create a branch. 13860 // We don't need to alter control flow. 13861 OffsetDestReg = 0; // unused 13862 OverflowDestReg = DestReg; 13863 13864 offsetMBB = NULL; 13865 overflowMBB = thisMBB; 13866 endMBB = thisMBB; 13867 } else { 13868 // First emit code to check if gp_offset (or fp_offset) is below the bound. 13869 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 13870 // If not, pull from overflow_area. (branch to overflowMBB) 13871 // 13872 // thisMBB 13873 // | . 13874 // | . 13875 // offsetMBB overflowMBB 13876 // | . 13877 // | . 13878 // endMBB 13879 13880 // Registers for the PHI in endMBB 13881 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 13882 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 13883 13884 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 13885 MachineFunction *MF = MBB->getParent(); 13886 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13887 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13888 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13889 13890 MachineFunction::iterator MBBIter = MBB; 13891 ++MBBIter; 13892 13893 // Insert the new basic blocks 13894 MF->insert(MBBIter, offsetMBB); 13895 MF->insert(MBBIter, overflowMBB); 13896 MF->insert(MBBIter, endMBB); 13897 13898 // Transfer the remainder of MBB and its successor edges to endMBB. 13899 endMBB->splice(endMBB->begin(), thisMBB, 13900 llvm::next(MachineBasicBlock::iterator(MI)), 13901 thisMBB->end()); 13902 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 13903 13904 // Make offsetMBB and overflowMBB successors of thisMBB 13905 thisMBB->addSuccessor(offsetMBB); 13906 thisMBB->addSuccessor(overflowMBB); 13907 13908 // endMBB is a successor of both offsetMBB and overflowMBB 13909 offsetMBB->addSuccessor(endMBB); 13910 overflowMBB->addSuccessor(endMBB); 13911 13912 // Load the offset value into a register 13913 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 13914 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 13915 .addOperand(Base) 13916 .addOperand(Scale) 13917 .addOperand(Index) 13918 .addDisp(Disp, UseFPOffset ? 4 : 0) 13919 .addOperand(Segment) 13920 .setMemRefs(MMOBegin, MMOEnd); 13921 13922 // Check if there is enough room left to pull this argument. 13923 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 13924 .addReg(OffsetReg) 13925 .addImm(MaxOffset + 8 - ArgSizeA8); 13926 13927 // Branch to "overflowMBB" if offset >= max 13928 // Fall through to "offsetMBB" otherwise 13929 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 13930 .addMBB(overflowMBB); 13931 } 13932 13933 // In offsetMBB, emit code to use the reg_save_area. 13934 if (offsetMBB) { 13935 assert(OffsetReg != 0); 13936 13937 // Read the reg_save_area address. 13938 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 13939 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 13940 .addOperand(Base) 13941 .addOperand(Scale) 13942 .addOperand(Index) 13943 .addDisp(Disp, 16) 13944 .addOperand(Segment) 13945 .setMemRefs(MMOBegin, MMOEnd); 13946 13947 // Zero-extend the offset 13948 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 13949 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 13950 .addImm(0) 13951 .addReg(OffsetReg) 13952 .addImm(X86::sub_32bit); 13953 13954 // Add the offset to the reg_save_area to get the final address. 13955 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 13956 .addReg(OffsetReg64) 13957 .addReg(RegSaveReg); 13958 13959 // Compute the offset for the next argument 13960 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 13961 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 13962 .addReg(OffsetReg) 13963 .addImm(UseFPOffset ? 16 : 8); 13964 13965 // Store it back into the va_list. 13966 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 13967 .addOperand(Base) 13968 .addOperand(Scale) 13969 .addOperand(Index) 13970 .addDisp(Disp, UseFPOffset ? 4 : 0) 13971 .addOperand(Segment) 13972 .addReg(NextOffsetReg) 13973 .setMemRefs(MMOBegin, MMOEnd); 13974 13975 // Jump to endMBB 13976 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 13977 .addMBB(endMBB); 13978 } 13979 13980 // 13981 // Emit code to use overflow area 13982 // 13983 13984 // Load the overflow_area address into a register. 13985 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 13986 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 13987 .addOperand(Base) 13988 .addOperand(Scale) 13989 .addOperand(Index) 13990 .addDisp(Disp, 8) 13991 .addOperand(Segment) 13992 .setMemRefs(MMOBegin, MMOEnd); 13993 13994 // If we need to align it, do so. Otherwise, just copy the address 13995 // to OverflowDestReg. 13996 if (NeedsAlign) { 13997 // Align the overflow address 13998 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 13999 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 14000 14001 // aligned_addr = (addr + (align-1)) & ~(align-1) 14002 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 14003 .addReg(OverflowAddrReg) 14004 .addImm(Align-1); 14005 14006 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 14007 .addReg(TmpReg) 14008 .addImm(~(uint64_t)(Align-1)); 14009 } else { 14010 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 14011 .addReg(OverflowAddrReg); 14012 } 14013 14014 // Compute the next overflow address after this argument. 14015 // (the overflow address should be kept 8-byte aligned) 14016 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 14017 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 14018 .addReg(OverflowDestReg) 14019 .addImm(ArgSizeA8); 14020 14021 // Store the new overflow address. 14022 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 14023 .addOperand(Base) 14024 .addOperand(Scale) 14025 .addOperand(Index) 14026 .addDisp(Disp, 8) 14027 .addOperand(Segment) 14028 .addReg(NextAddrReg) 14029 .setMemRefs(MMOBegin, MMOEnd); 14030 14031 // If we branched, emit the PHI to the front of endMBB. 14032 if (offsetMBB) { 14033 BuildMI(*endMBB, endMBB->begin(), DL, 14034 TII->get(X86::PHI), DestReg) 14035 .addReg(OffsetDestReg).addMBB(offsetMBB) 14036 .addReg(OverflowDestReg).addMBB(overflowMBB); 14037 } 14038 14039 // Erase the pseudo instruction 14040 MI->eraseFromParent(); 14041 14042 return endMBB; 14043} 14044 14045MachineBasicBlock * 14046X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 14047 MachineInstr *MI, 14048 MachineBasicBlock *MBB) const { 14049 // Emit code to save XMM registers to the stack. The ABI says that the 14050 // number of registers to save is given in %al, so it's theoretically 14051 // possible to do an indirect jump trick to avoid saving all of them, 14052 // however this code takes a simpler approach and just executes all 14053 // of the stores if %al is non-zero. It's less code, and it's probably 14054 // easier on the hardware branch predictor, and stores aren't all that 14055 // expensive anyway. 14056 14057 // Create the new basic blocks. One block contains all the XMM stores, 14058 // and one block is the final destination regardless of whether any 14059 // stores were performed. 14060 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 14061 MachineFunction *F = MBB->getParent(); 14062 MachineFunction::iterator MBBIter = MBB; 14063 ++MBBIter; 14064 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 14065 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 14066 F->insert(MBBIter, XMMSaveMBB); 14067 F->insert(MBBIter, EndMBB); 14068 14069 // Transfer the remainder of MBB and its successor edges to EndMBB. 14070 EndMBB->splice(EndMBB->begin(), MBB, 14071 llvm::next(MachineBasicBlock::iterator(MI)), 14072 MBB->end()); 14073 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 14074 14075 // The original block will now fall through to the XMM save block. 14076 MBB->addSuccessor(XMMSaveMBB); 14077 // The XMMSaveMBB will fall through to the end block. 14078 XMMSaveMBB->addSuccessor(EndMBB); 14079 14080 // Now add the instructions. 14081 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14082 DebugLoc DL = MI->getDebugLoc(); 14083 14084 unsigned CountReg = MI->getOperand(0).getReg(); 14085 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 14086 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 14087 14088 if (!Subtarget->isTargetWin64()) { 14089 // If %al is 0, branch around the XMM save block. 14090 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 14091 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 14092 MBB->addSuccessor(EndMBB); 14093 } 14094 14095 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr; 14096 // In the XMM save block, save all the XMM argument registers. 14097 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 14098 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 14099 MachineMemOperand *MMO = 14100 F->getMachineMemOperand( 14101 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 14102 MachineMemOperand::MOStore, 14103 /*Size=*/16, /*Align=*/16); 14104 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 14105 .addFrameIndex(RegSaveFrameIndex) 14106 .addImm(/*Scale=*/1) 14107 .addReg(/*IndexReg=*/0) 14108 .addImm(/*Disp=*/Offset) 14109 .addReg(/*Segment=*/0) 14110 .addReg(MI->getOperand(i).getReg()) 14111 .addMemOperand(MMO); 14112 } 14113 14114 MI->eraseFromParent(); // The pseudo instruction is gone now. 14115 14116 return EndMBB; 14117} 14118 14119// The EFLAGS operand of SelectItr might be missing a kill marker 14120// because there were multiple uses of EFLAGS, and ISel didn't know 14121// which to mark. Figure out whether SelectItr should have had a 14122// kill marker, and set it if it should. Returns the correct kill 14123// marker value. 14124static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 14125 MachineBasicBlock* BB, 14126 const TargetRegisterInfo* TRI) { 14127 // Scan forward through BB for a use/def of EFLAGS. 14128 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 14129 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 14130 const MachineInstr& mi = *miI; 14131 if (mi.readsRegister(X86::EFLAGS)) 14132 return false; 14133 if (mi.definesRegister(X86::EFLAGS)) 14134 break; // Should have kill-flag - update below. 14135 } 14136 14137 // If we hit the end of the block, check whether EFLAGS is live into a 14138 // successor. 14139 if (miI == BB->end()) { 14140 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 14141 sEnd = BB->succ_end(); 14142 sItr != sEnd; ++sItr) { 14143 MachineBasicBlock* succ = *sItr; 14144 if (succ->isLiveIn(X86::EFLAGS)) 14145 return false; 14146 } 14147 } 14148 14149 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 14150 // out. SelectMI should have a kill flag on EFLAGS. 14151 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 14152 return true; 14153} 14154 14155MachineBasicBlock * 14156X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 14157 MachineBasicBlock *BB) const { 14158 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14159 DebugLoc DL = MI->getDebugLoc(); 14160 14161 // To "insert" a SELECT_CC instruction, we actually have to insert the 14162 // diamond control-flow pattern. The incoming instruction knows the 14163 // destination vreg to set, the condition code register to branch on, the 14164 // true/false values to select between, and a branch opcode to use. 14165 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 14166 MachineFunction::iterator It = BB; 14167 ++It; 14168 14169 // thisMBB: 14170 // ... 14171 // TrueVal = ... 14172 // cmpTY ccX, r1, r2 14173 // bCC copy1MBB 14174 // fallthrough --> copy0MBB 14175 MachineBasicBlock *thisMBB = BB; 14176 MachineFunction *F = BB->getParent(); 14177 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 14178 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 14179 F->insert(It, copy0MBB); 14180 F->insert(It, sinkMBB); 14181 14182 // If the EFLAGS register isn't dead in the terminator, then claim that it's 14183 // live into the sink and copy blocks. 14184 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 14185 if (!MI->killsRegister(X86::EFLAGS) && 14186 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 14187 copy0MBB->addLiveIn(X86::EFLAGS); 14188 sinkMBB->addLiveIn(X86::EFLAGS); 14189 } 14190 14191 // Transfer the remainder of BB and its successor edges to sinkMBB. 14192 sinkMBB->splice(sinkMBB->begin(), BB, 14193 llvm::next(MachineBasicBlock::iterator(MI)), 14194 BB->end()); 14195 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 14196 14197 // Add the true and fallthrough blocks as its successors. 14198 BB->addSuccessor(copy0MBB); 14199 BB->addSuccessor(sinkMBB); 14200 14201 // Create the conditional branch instruction. 14202 unsigned Opc = 14203 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 14204 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 14205 14206 // copy0MBB: 14207 // %FalseValue = ... 14208 // # fallthrough to sinkMBB 14209 copy0MBB->addSuccessor(sinkMBB); 14210 14211 // sinkMBB: 14212 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 14213 // ... 14214 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 14215 TII->get(X86::PHI), MI->getOperand(0).getReg()) 14216 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 14217 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 14218 14219 MI->eraseFromParent(); // The pseudo instruction is gone now. 14220 return sinkMBB; 14221} 14222 14223MachineBasicBlock * 14224X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 14225 bool Is64Bit) const { 14226 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14227 DebugLoc DL = MI->getDebugLoc(); 14228 MachineFunction *MF = BB->getParent(); 14229 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 14230 14231 assert(getTargetMachine().Options.EnableSegmentedStacks); 14232 14233 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 14234 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 14235 14236 // BB: 14237 // ... [Till the alloca] 14238 // If stacklet is not large enough, jump to mallocMBB 14239 // 14240 // bumpMBB: 14241 // Allocate by subtracting from RSP 14242 // Jump to continueMBB 14243 // 14244 // mallocMBB: 14245 // Allocate by call to runtime 14246 // 14247 // continueMBB: 14248 // ... 14249 // [rest of original BB] 14250 // 14251 14252 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 14253 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 14254 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 14255 14256 MachineRegisterInfo &MRI = MF->getRegInfo(); 14257 const TargetRegisterClass *AddrRegClass = 14258 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 14259 14260 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 14261 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 14262 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 14263 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 14264 sizeVReg = MI->getOperand(1).getReg(), 14265 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 14266 14267 MachineFunction::iterator MBBIter = BB; 14268 ++MBBIter; 14269 14270 MF->insert(MBBIter, bumpMBB); 14271 MF->insert(MBBIter, mallocMBB); 14272 MF->insert(MBBIter, continueMBB); 14273 14274 continueMBB->splice(continueMBB->begin(), BB, llvm::next 14275 (MachineBasicBlock::iterator(MI)), BB->end()); 14276 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 14277 14278 // Add code to the main basic block to check if the stack limit has been hit, 14279 // and if so, jump to mallocMBB otherwise to bumpMBB. 14280 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 14281 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 14282 .addReg(tmpSPVReg).addReg(sizeVReg); 14283 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 14284 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 14285 .addReg(SPLimitVReg); 14286 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 14287 14288 // bumpMBB simply decreases the stack pointer, since we know the current 14289 // stacklet has enough space. 14290 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 14291 .addReg(SPLimitVReg); 14292 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 14293 .addReg(SPLimitVReg); 14294 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 14295 14296 // Calls into a routine in libgcc to allocate more space from the heap. 14297 const uint32_t *RegMask = 14298 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 14299 if (Is64Bit) { 14300 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 14301 .addReg(sizeVReg); 14302 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 14303 .addExternalSymbol("__morestack_allocate_stack_space") 14304 .addRegMask(RegMask) 14305 .addReg(X86::RDI, RegState::Implicit) 14306 .addReg(X86::RAX, RegState::ImplicitDefine); 14307 } else { 14308 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 14309 .addImm(12); 14310 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 14311 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 14312 .addExternalSymbol("__morestack_allocate_stack_space") 14313 .addRegMask(RegMask) 14314 .addReg(X86::EAX, RegState::ImplicitDefine); 14315 } 14316 14317 if (!Is64Bit) 14318 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 14319 .addImm(16); 14320 14321 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 14322 .addReg(Is64Bit ? X86::RAX : X86::EAX); 14323 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 14324 14325 // Set up the CFG correctly. 14326 BB->addSuccessor(bumpMBB); 14327 BB->addSuccessor(mallocMBB); 14328 mallocMBB->addSuccessor(continueMBB); 14329 bumpMBB->addSuccessor(continueMBB); 14330 14331 // Take care of the PHI nodes. 14332 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 14333 MI->getOperand(0).getReg()) 14334 .addReg(mallocPtrVReg).addMBB(mallocMBB) 14335 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 14336 14337 // Delete the original pseudo instruction. 14338 MI->eraseFromParent(); 14339 14340 // And we're done. 14341 return continueMBB; 14342} 14343 14344MachineBasicBlock * 14345X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 14346 MachineBasicBlock *BB) const { 14347 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14348 DebugLoc DL = MI->getDebugLoc(); 14349 14350 assert(!Subtarget->isTargetEnvMacho()); 14351 14352 // The lowering is pretty easy: we're just emitting the call to _alloca. The 14353 // non-trivial part is impdef of ESP. 14354 14355 if (Subtarget->isTargetWin64()) { 14356 if (Subtarget->isTargetCygMing()) { 14357 // ___chkstk(Mingw64): 14358 // Clobbers R10, R11, RAX and EFLAGS. 14359 // Updates RSP. 14360 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 14361 .addExternalSymbol("___chkstk") 14362 .addReg(X86::RAX, RegState::Implicit) 14363 .addReg(X86::RSP, RegState::Implicit) 14364 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 14365 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 14366 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 14367 } else { 14368 // __chkstk(MSVCRT): does not update stack pointer. 14369 // Clobbers R10, R11 and EFLAGS. 14370 // FIXME: RAX(allocated size) might be reused and not killed. 14371 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 14372 .addExternalSymbol("__chkstk") 14373 .addReg(X86::RAX, RegState::Implicit) 14374 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 14375 // RAX has the offset to subtracted from RSP. 14376 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 14377 .addReg(X86::RSP) 14378 .addReg(X86::RAX); 14379 } 14380 } else { 14381 const char *StackProbeSymbol = 14382 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 14383 14384 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 14385 .addExternalSymbol(StackProbeSymbol) 14386 .addReg(X86::EAX, RegState::Implicit) 14387 .addReg(X86::ESP, RegState::Implicit) 14388 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 14389 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 14390 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 14391 } 14392 14393 MI->eraseFromParent(); // The pseudo instruction is gone now. 14394 return BB; 14395} 14396 14397MachineBasicBlock * 14398X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 14399 MachineBasicBlock *BB) const { 14400 // This is pretty easy. We're taking the value that we received from 14401 // our load from the relocation, sticking it in either RDI (x86-64) 14402 // or EAX and doing an indirect call. The return value will then 14403 // be in the normal return register. 14404 const X86InstrInfo *TII 14405 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 14406 DebugLoc DL = MI->getDebugLoc(); 14407 MachineFunction *F = BB->getParent(); 14408 14409 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 14410 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 14411 14412 // Get a register mask for the lowered call. 14413 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 14414 // proper register mask. 14415 const uint32_t *RegMask = 14416 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 14417 if (Subtarget->is64Bit()) { 14418 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 14419 TII->get(X86::MOV64rm), X86::RDI) 14420 .addReg(X86::RIP) 14421 .addImm(0).addReg(0) 14422 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 14423 MI->getOperand(3).getTargetFlags()) 14424 .addReg(0); 14425 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 14426 addDirectMem(MIB, X86::RDI); 14427 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 14428 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 14429 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 14430 TII->get(X86::MOV32rm), X86::EAX) 14431 .addReg(0) 14432 .addImm(0).addReg(0) 14433 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 14434 MI->getOperand(3).getTargetFlags()) 14435 .addReg(0); 14436 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 14437 addDirectMem(MIB, X86::EAX); 14438 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 14439 } else { 14440 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 14441 TII->get(X86::MOV32rm), X86::EAX) 14442 .addReg(TII->getGlobalBaseReg(F)) 14443 .addImm(0).addReg(0) 14444 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 14445 MI->getOperand(3).getTargetFlags()) 14446 .addReg(0); 14447 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 14448 addDirectMem(MIB, X86::EAX); 14449 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 14450 } 14451 14452 MI->eraseFromParent(); // The pseudo instruction is gone now. 14453 return BB; 14454} 14455 14456MachineBasicBlock * 14457X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, 14458 MachineBasicBlock *MBB) const { 14459 DebugLoc DL = MI->getDebugLoc(); 14460 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14461 14462 MachineFunction *MF = MBB->getParent(); 14463 MachineRegisterInfo &MRI = MF->getRegInfo(); 14464 14465 const BasicBlock *BB = MBB->getBasicBlock(); 14466 MachineFunction::iterator I = MBB; 14467 ++I; 14468 14469 // Memory Reference 14470 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 14471 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 14472 14473 unsigned DstReg; 14474 unsigned MemOpndSlot = 0; 14475 14476 unsigned CurOp = 0; 14477 14478 DstReg = MI->getOperand(CurOp++).getReg(); 14479 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 14480 assert(RC->hasType(MVT::i32) && "Invalid destination!"); 14481 unsigned mainDstReg = MRI.createVirtualRegister(RC); 14482 unsigned restoreDstReg = MRI.createVirtualRegister(RC); 14483 14484 MemOpndSlot = CurOp; 14485 14486 MVT PVT = getPointerTy(); 14487 assert((PVT == MVT::i64 || PVT == MVT::i32) && 14488 "Invalid Pointer Size!"); 14489 14490 // For v = setjmp(buf), we generate 14491 // 14492 // thisMBB: 14493 // buf[LabelOffset] = restoreMBB 14494 // SjLjSetup restoreMBB 14495 // 14496 // mainMBB: 14497 // v_main = 0 14498 // 14499 // sinkMBB: 14500 // v = phi(main, restore) 14501 // 14502 // restoreMBB: 14503 // v_restore = 1 14504 14505 MachineBasicBlock *thisMBB = MBB; 14506 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 14507 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 14508 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB); 14509 MF->insert(I, mainMBB); 14510 MF->insert(I, sinkMBB); 14511 MF->push_back(restoreMBB); 14512 14513 MachineInstrBuilder MIB; 14514 14515 // Transfer the remainder of BB and its successor edges to sinkMBB. 14516 sinkMBB->splice(sinkMBB->begin(), MBB, 14517 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 14518 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 14519 14520 // thisMBB: 14521 unsigned PtrStoreOpc = 0; 14522 unsigned LabelReg = 0; 14523 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 14524 Reloc::Model RM = getTargetMachine().getRelocationModel(); 14525 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) && 14526 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC); 14527 14528 // Prepare IP either in reg or imm. 14529 if (!UseImmLabel) { 14530 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr; 14531 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); 14532 LabelReg = MRI.createVirtualRegister(PtrRC); 14533 if (Subtarget->is64Bit()) { 14534 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg) 14535 .addReg(X86::RIP) 14536 .addImm(0) 14537 .addReg(0) 14538 .addMBB(restoreMBB) 14539 .addReg(0); 14540 } else { 14541 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII); 14542 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg) 14543 .addReg(XII->getGlobalBaseReg(MF)) 14544 .addImm(0) 14545 .addReg(0) 14546 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference()) 14547 .addReg(0); 14548 } 14549 } else 14550 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi; 14551 // Store IP 14552 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc)); 14553 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14554 if (i == X86::AddrDisp) 14555 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset); 14556 else 14557 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 14558 } 14559 if (!UseImmLabel) 14560 MIB.addReg(LabelReg); 14561 else 14562 MIB.addMBB(restoreMBB); 14563 MIB.setMemRefs(MMOBegin, MMOEnd); 14564 // Setup 14565 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup)) 14566 .addMBB(restoreMBB); 14567 MIB.addRegMask(RegInfo->getNoPreservedMask()); 14568 thisMBB->addSuccessor(mainMBB); 14569 thisMBB->addSuccessor(restoreMBB); 14570 14571 // mainMBB: 14572 // EAX = 0 14573 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg); 14574 mainMBB->addSuccessor(sinkMBB); 14575 14576 // sinkMBB: 14577 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 14578 TII->get(X86::PHI), DstReg) 14579 .addReg(mainDstReg).addMBB(mainMBB) 14580 .addReg(restoreDstReg).addMBB(restoreMBB); 14581 14582 // restoreMBB: 14583 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1); 14584 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB); 14585 restoreMBB->addSuccessor(sinkMBB); 14586 14587 MI->eraseFromParent(); 14588 return sinkMBB; 14589} 14590 14591MachineBasicBlock * 14592X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, 14593 MachineBasicBlock *MBB) const { 14594 DebugLoc DL = MI->getDebugLoc(); 14595 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14596 14597 MachineFunction *MF = MBB->getParent(); 14598 MachineRegisterInfo &MRI = MF->getRegInfo(); 14599 14600 // Memory Reference 14601 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 14602 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 14603 14604 MVT PVT = getPointerTy(); 14605 assert((PVT == MVT::i64 || PVT == MVT::i32) && 14606 "Invalid Pointer Size!"); 14607 14608 const TargetRegisterClass *RC = 14609 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass; 14610 unsigned Tmp = MRI.createVirtualRegister(RC); 14611 // Since FP is only updated here but NOT referenced, it's treated as GPR. 14612 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP; 14613 unsigned SP = RegInfo->getStackRegister(); 14614 14615 MachineInstrBuilder MIB; 14616 14617 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 14618 const int64_t SPOffset = 2 * PVT.getStoreSize(); 14619 14620 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm; 14621 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r; 14622 14623 // Reload FP 14624 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP); 14625 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 14626 MIB.addOperand(MI->getOperand(i)); 14627 MIB.setMemRefs(MMOBegin, MMOEnd); 14628 // Reload IP 14629 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp); 14630 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14631 if (i == X86::AddrDisp) 14632 MIB.addDisp(MI->getOperand(i), LabelOffset); 14633 else 14634 MIB.addOperand(MI->getOperand(i)); 14635 } 14636 MIB.setMemRefs(MMOBegin, MMOEnd); 14637 // Reload SP 14638 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP); 14639 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14640 if (i == X86::AddrDisp) 14641 MIB.addDisp(MI->getOperand(i), SPOffset); 14642 else 14643 MIB.addOperand(MI->getOperand(i)); 14644 } 14645 MIB.setMemRefs(MMOBegin, MMOEnd); 14646 // Jump 14647 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp); 14648 14649 MI->eraseFromParent(); 14650 return MBB; 14651} 14652 14653MachineBasicBlock * 14654X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 14655 MachineBasicBlock *BB) const { 14656 switch (MI->getOpcode()) { 14657 default: llvm_unreachable("Unexpected instr type to insert"); 14658 case X86::TAILJMPd64: 14659 case X86::TAILJMPr64: 14660 case X86::TAILJMPm64: 14661 llvm_unreachable("TAILJMP64 would not be touched here."); 14662 case X86::TCRETURNdi64: 14663 case X86::TCRETURNri64: 14664 case X86::TCRETURNmi64: 14665 return BB; 14666 case X86::WIN_ALLOCA: 14667 return EmitLoweredWinAlloca(MI, BB); 14668 case X86::SEG_ALLOCA_32: 14669 return EmitLoweredSegAlloca(MI, BB, false); 14670 case X86::SEG_ALLOCA_64: 14671 return EmitLoweredSegAlloca(MI, BB, true); 14672 case X86::TLSCall_32: 14673 case X86::TLSCall_64: 14674 return EmitLoweredTLSCall(MI, BB); 14675 case X86::CMOV_GR8: 14676 case X86::CMOV_FR32: 14677 case X86::CMOV_FR64: 14678 case X86::CMOV_V4F32: 14679 case X86::CMOV_V2F64: 14680 case X86::CMOV_V2I64: 14681 case X86::CMOV_V8F32: 14682 case X86::CMOV_V4F64: 14683 case X86::CMOV_V4I64: 14684 case X86::CMOV_GR16: 14685 case X86::CMOV_GR32: 14686 case X86::CMOV_RFP32: 14687 case X86::CMOV_RFP64: 14688 case X86::CMOV_RFP80: 14689 return EmitLoweredSelect(MI, BB); 14690 14691 case X86::FP32_TO_INT16_IN_MEM: 14692 case X86::FP32_TO_INT32_IN_MEM: 14693 case X86::FP32_TO_INT64_IN_MEM: 14694 case X86::FP64_TO_INT16_IN_MEM: 14695 case X86::FP64_TO_INT32_IN_MEM: 14696 case X86::FP64_TO_INT64_IN_MEM: 14697 case X86::FP80_TO_INT16_IN_MEM: 14698 case X86::FP80_TO_INT32_IN_MEM: 14699 case X86::FP80_TO_INT64_IN_MEM: { 14700 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14701 DebugLoc DL = MI->getDebugLoc(); 14702 14703 // Change the floating point control register to use "round towards zero" 14704 // mode when truncating to an integer value. 14705 MachineFunction *F = BB->getParent(); 14706 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 14707 addFrameReference(BuildMI(*BB, MI, DL, 14708 TII->get(X86::FNSTCW16m)), CWFrameIdx); 14709 14710 // Load the old value of the high byte of the control word... 14711 unsigned OldCW = 14712 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass); 14713 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 14714 CWFrameIdx); 14715 14716 // Set the high part to be round to zero... 14717 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 14718 .addImm(0xC7F); 14719 14720 // Reload the modified control word now... 14721 addFrameReference(BuildMI(*BB, MI, DL, 14722 TII->get(X86::FLDCW16m)), CWFrameIdx); 14723 14724 // Restore the memory image of control word to original value 14725 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 14726 .addReg(OldCW); 14727 14728 // Get the X86 opcode to use. 14729 unsigned Opc; 14730 switch (MI->getOpcode()) { 14731 default: llvm_unreachable("illegal opcode!"); 14732 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 14733 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 14734 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 14735 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 14736 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 14737 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 14738 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 14739 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 14740 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 14741 } 14742 14743 X86AddressMode AM; 14744 MachineOperand &Op = MI->getOperand(0); 14745 if (Op.isReg()) { 14746 AM.BaseType = X86AddressMode::RegBase; 14747 AM.Base.Reg = Op.getReg(); 14748 } else { 14749 AM.BaseType = X86AddressMode::FrameIndexBase; 14750 AM.Base.FrameIndex = Op.getIndex(); 14751 } 14752 Op = MI->getOperand(1); 14753 if (Op.isImm()) 14754 AM.Scale = Op.getImm(); 14755 Op = MI->getOperand(2); 14756 if (Op.isImm()) 14757 AM.IndexReg = Op.getImm(); 14758 Op = MI->getOperand(3); 14759 if (Op.isGlobal()) { 14760 AM.GV = Op.getGlobal(); 14761 } else { 14762 AM.Disp = Op.getImm(); 14763 } 14764 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 14765 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 14766 14767 // Reload the original control word now. 14768 addFrameReference(BuildMI(*BB, MI, DL, 14769 TII->get(X86::FLDCW16m)), CWFrameIdx); 14770 14771 MI->eraseFromParent(); // The pseudo instruction is gone now. 14772 return BB; 14773 } 14774 // String/text processing lowering. 14775 case X86::PCMPISTRM128REG: 14776 case X86::VPCMPISTRM128REG: 14777 case X86::PCMPISTRM128MEM: 14778 case X86::VPCMPISTRM128MEM: 14779 case X86::PCMPESTRM128REG: 14780 case X86::VPCMPESTRM128REG: 14781 case X86::PCMPESTRM128MEM: 14782 case X86::VPCMPESTRM128MEM: 14783 assert(Subtarget->hasSSE42() && 14784 "Target must have SSE4.2 or AVX features enabled"); 14785 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo()); 14786 14787 // String/text processing lowering. 14788 case X86::PCMPISTRIREG: 14789 case X86::VPCMPISTRIREG: 14790 case X86::PCMPISTRIMEM: 14791 case X86::VPCMPISTRIMEM: 14792 case X86::PCMPESTRIREG: 14793 case X86::VPCMPESTRIREG: 14794 case X86::PCMPESTRIMEM: 14795 case X86::VPCMPESTRIMEM: 14796 assert(Subtarget->hasSSE42() && 14797 "Target must have SSE4.2 or AVX features enabled"); 14798 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo()); 14799 14800 // Thread synchronization. 14801 case X86::MONITOR: 14802 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget); 14803 14804 // xbegin 14805 case X86::XBEGIN: 14806 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo()); 14807 14808 // Atomic Lowering. 14809 case X86::ATOMAND8: 14810 case X86::ATOMAND16: 14811 case X86::ATOMAND32: 14812 case X86::ATOMAND64: 14813 // Fall through 14814 case X86::ATOMOR8: 14815 case X86::ATOMOR16: 14816 case X86::ATOMOR32: 14817 case X86::ATOMOR64: 14818 // Fall through 14819 case X86::ATOMXOR16: 14820 case X86::ATOMXOR8: 14821 case X86::ATOMXOR32: 14822 case X86::ATOMXOR64: 14823 // Fall through 14824 case X86::ATOMNAND8: 14825 case X86::ATOMNAND16: 14826 case X86::ATOMNAND32: 14827 case X86::ATOMNAND64: 14828 // Fall through 14829 case X86::ATOMMAX8: 14830 case X86::ATOMMAX16: 14831 case X86::ATOMMAX32: 14832 case X86::ATOMMAX64: 14833 // Fall through 14834 case X86::ATOMMIN8: 14835 case X86::ATOMMIN16: 14836 case X86::ATOMMIN32: 14837 case X86::ATOMMIN64: 14838 // Fall through 14839 case X86::ATOMUMAX8: 14840 case X86::ATOMUMAX16: 14841 case X86::ATOMUMAX32: 14842 case X86::ATOMUMAX64: 14843 // Fall through 14844 case X86::ATOMUMIN8: 14845 case X86::ATOMUMIN16: 14846 case X86::ATOMUMIN32: 14847 case X86::ATOMUMIN64: 14848 return EmitAtomicLoadArith(MI, BB); 14849 14850 // This group does 64-bit operations on a 32-bit host. 14851 case X86::ATOMAND6432: 14852 case X86::ATOMOR6432: 14853 case X86::ATOMXOR6432: 14854 case X86::ATOMNAND6432: 14855 case X86::ATOMADD6432: 14856 case X86::ATOMSUB6432: 14857 case X86::ATOMMAX6432: 14858 case X86::ATOMMIN6432: 14859 case X86::ATOMUMAX6432: 14860 case X86::ATOMUMIN6432: 14861 case X86::ATOMSWAP6432: 14862 return EmitAtomicLoadArith6432(MI, BB); 14863 14864 case X86::VASTART_SAVE_XMM_REGS: 14865 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 14866 14867 case X86::VAARG_64: 14868 return EmitVAARG64WithCustomInserter(MI, BB); 14869 14870 case X86::EH_SjLj_SetJmp32: 14871 case X86::EH_SjLj_SetJmp64: 14872 return emitEHSjLjSetJmp(MI, BB); 14873 14874 case X86::EH_SjLj_LongJmp32: 14875 case X86::EH_SjLj_LongJmp64: 14876 return emitEHSjLjLongJmp(MI, BB); 14877 } 14878} 14879 14880//===----------------------------------------------------------------------===// 14881// X86 Optimization Hooks 14882//===----------------------------------------------------------------------===// 14883 14884void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 14885 APInt &KnownZero, 14886 APInt &KnownOne, 14887 const SelectionDAG &DAG, 14888 unsigned Depth) const { 14889 unsigned BitWidth = KnownZero.getBitWidth(); 14890 unsigned Opc = Op.getOpcode(); 14891 assert((Opc >= ISD::BUILTIN_OP_END || 14892 Opc == ISD::INTRINSIC_WO_CHAIN || 14893 Opc == ISD::INTRINSIC_W_CHAIN || 14894 Opc == ISD::INTRINSIC_VOID) && 14895 "Should use MaskedValueIsZero if you don't know whether Op" 14896 " is a target node!"); 14897 14898 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 14899 switch (Opc) { 14900 default: break; 14901 case X86ISD::ADD: 14902 case X86ISD::SUB: 14903 case X86ISD::ADC: 14904 case X86ISD::SBB: 14905 case X86ISD::SMUL: 14906 case X86ISD::UMUL: 14907 case X86ISD::INC: 14908 case X86ISD::DEC: 14909 case X86ISD::OR: 14910 case X86ISD::XOR: 14911 case X86ISD::AND: 14912 // These nodes' second result is a boolean. 14913 if (Op.getResNo() == 0) 14914 break; 14915 // Fallthrough 14916 case X86ISD::SETCC: 14917 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 14918 break; 14919 case ISD::INTRINSIC_WO_CHAIN: { 14920 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 14921 unsigned NumLoBits = 0; 14922 switch (IntId) { 14923 default: break; 14924 case Intrinsic::x86_sse_movmsk_ps: 14925 case Intrinsic::x86_avx_movmsk_ps_256: 14926 case Intrinsic::x86_sse2_movmsk_pd: 14927 case Intrinsic::x86_avx_movmsk_pd_256: 14928 case Intrinsic::x86_mmx_pmovmskb: 14929 case Intrinsic::x86_sse2_pmovmskb_128: 14930 case Intrinsic::x86_avx2_pmovmskb: { 14931 // High bits of movmskp{s|d}, pmovmskb are known zero. 14932 switch (IntId) { 14933 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 14934 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 14935 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 14936 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 14937 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 14938 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 14939 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 14940 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 14941 } 14942 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 14943 break; 14944 } 14945 } 14946 break; 14947 } 14948 } 14949} 14950 14951unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 14952 unsigned Depth) const { 14953 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 14954 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 14955 return Op.getValueType().getScalarType().getSizeInBits(); 14956 14957 // Fallback case. 14958 return 1; 14959} 14960 14961/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 14962/// node is a GlobalAddress + offset. 14963bool X86TargetLowering::isGAPlusOffset(SDNode *N, 14964 const GlobalValue* &GA, 14965 int64_t &Offset) const { 14966 if (N->getOpcode() == X86ISD::Wrapper) { 14967 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 14968 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 14969 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 14970 return true; 14971 } 14972 } 14973 return TargetLowering::isGAPlusOffset(N, GA, Offset); 14974} 14975 14976/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 14977/// same as extracting the high 128-bit part of 256-bit vector and then 14978/// inserting the result into the low part of a new 256-bit vector 14979static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 14980 EVT VT = SVOp->getValueType(0); 14981 unsigned NumElems = VT.getVectorNumElements(); 14982 14983 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 14984 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j) 14985 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 14986 SVOp->getMaskElt(j) >= 0) 14987 return false; 14988 14989 return true; 14990} 14991 14992/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 14993/// same as extracting the low 128-bit part of 256-bit vector and then 14994/// inserting the result into the high part of a new 256-bit vector 14995static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 14996 EVT VT = SVOp->getValueType(0); 14997 unsigned NumElems = VT.getVectorNumElements(); 14998 14999 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 15000 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j) 15001 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 15002 SVOp->getMaskElt(j) >= 0) 15003 return false; 15004 15005 return true; 15006} 15007 15008/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 15009static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 15010 TargetLowering::DAGCombinerInfo &DCI, 15011 const X86Subtarget* Subtarget) { 15012 DebugLoc dl = N->getDebugLoc(); 15013 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 15014 SDValue V1 = SVOp->getOperand(0); 15015 SDValue V2 = SVOp->getOperand(1); 15016 EVT VT = SVOp->getValueType(0); 15017 unsigned NumElems = VT.getVectorNumElements(); 15018 15019 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 15020 V2.getOpcode() == ISD::CONCAT_VECTORS) { 15021 // 15022 // 0,0,0,... 15023 // | 15024 // V UNDEF BUILD_VECTOR UNDEF 15025 // \ / \ / 15026 // CONCAT_VECTOR CONCAT_VECTOR 15027 // \ / 15028 // \ / 15029 // RESULT: V + zero extended 15030 // 15031 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 15032 V2.getOperand(1).getOpcode() != ISD::UNDEF || 15033 V1.getOperand(1).getOpcode() != ISD::UNDEF) 15034 return SDValue(); 15035 15036 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 15037 return SDValue(); 15038 15039 // To match the shuffle mask, the first half of the mask should 15040 // be exactly the first vector, and all the rest a splat with the 15041 // first element of the second one. 15042 for (unsigned i = 0; i != NumElems/2; ++i) 15043 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 15044 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 15045 return SDValue(); 15046 15047 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 15048 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 15049 if (Ld->hasNUsesOfValue(1, 0)) { 15050 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 15051 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 15052 SDValue ResNode = 15053 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 15054 Ld->getMemoryVT(), 15055 Ld->getPointerInfo(), 15056 Ld->getAlignment(), 15057 false/*isVolatile*/, true/*ReadMem*/, 15058 false/*WriteMem*/); 15059 15060 // Make sure the newly-created LOAD is in the same position as Ld in 15061 // terms of dependency. We create a TokenFactor for Ld and ResNode, 15062 // and update uses of Ld's output chain to use the TokenFactor. 15063 if (Ld->hasAnyUseOfValue(1)) { 15064 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 15065 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1)); 15066 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain); 15067 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1), 15068 SDValue(ResNode.getNode(), 1)); 15069 } 15070 15071 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 15072 } 15073 } 15074 15075 // Emit a zeroed vector and insert the desired subvector on its 15076 // first half. 15077 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 15078 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl); 15079 return DCI.CombineTo(N, InsV); 15080 } 15081 15082 //===--------------------------------------------------------------------===// 15083 // Combine some shuffles into subvector extracts and inserts: 15084 // 15085 15086 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 15087 if (isShuffleHigh128VectorInsertLow(SVOp)) { 15088 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl); 15089 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl); 15090 return DCI.CombineTo(N, InsV); 15091 } 15092 15093 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 15094 if (isShuffleLow128VectorInsertHigh(SVOp)) { 15095 SDValue V = Extract128BitVector(V1, 0, DAG, dl); 15096 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl); 15097 return DCI.CombineTo(N, InsV); 15098 } 15099 15100 return SDValue(); 15101} 15102 15103/// PerformShuffleCombine - Performs several different shuffle combines. 15104static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 15105 TargetLowering::DAGCombinerInfo &DCI, 15106 const X86Subtarget *Subtarget) { 15107 DebugLoc dl = N->getDebugLoc(); 15108 EVT VT = N->getValueType(0); 15109 15110 // Don't create instructions with illegal types after legalize types has run. 15111 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15112 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 15113 return SDValue(); 15114 15115 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 15116 if (Subtarget->hasFp256() && VT.is256BitVector() && 15117 N->getOpcode() == ISD::VECTOR_SHUFFLE) 15118 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 15119 15120 // Only handle 128 wide vector from here on. 15121 if (!VT.is128BitVector()) 15122 return SDValue(); 15123 15124 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 15125 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 15126 // consecutive, non-overlapping, and in the right order. 15127 SmallVector<SDValue, 16> Elts; 15128 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 15129 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 15130 15131 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 15132} 15133 15134/// PerformTruncateCombine - Converts truncate operation to 15135/// a sequence of vector shuffle operations. 15136/// It is possible when we truncate 256-bit vector to 128-bit vector 15137static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 15138 TargetLowering::DAGCombinerInfo &DCI, 15139 const X86Subtarget *Subtarget) { 15140 return SDValue(); 15141} 15142 15143/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 15144/// specific shuffle of a load can be folded into a single element load. 15145/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 15146/// shuffles have been customed lowered so we need to handle those here. 15147static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 15148 TargetLowering::DAGCombinerInfo &DCI) { 15149 if (DCI.isBeforeLegalizeOps()) 15150 return SDValue(); 15151 15152 SDValue InVec = N->getOperand(0); 15153 SDValue EltNo = N->getOperand(1); 15154 15155 if (!isa<ConstantSDNode>(EltNo)) 15156 return SDValue(); 15157 15158 EVT VT = InVec.getValueType(); 15159 15160 bool HasShuffleIntoBitcast = false; 15161 if (InVec.getOpcode() == ISD::BITCAST) { 15162 // Don't duplicate a load with other uses. 15163 if (!InVec.hasOneUse()) 15164 return SDValue(); 15165 EVT BCVT = InVec.getOperand(0).getValueType(); 15166 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 15167 return SDValue(); 15168 InVec = InVec.getOperand(0); 15169 HasShuffleIntoBitcast = true; 15170 } 15171 15172 if (!isTargetShuffle(InVec.getOpcode())) 15173 return SDValue(); 15174 15175 // Don't duplicate a load with other uses. 15176 if (!InVec.hasOneUse()) 15177 return SDValue(); 15178 15179 SmallVector<int, 16> ShuffleMask; 15180 bool UnaryShuffle; 15181 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask, 15182 UnaryShuffle)) 15183 return SDValue(); 15184 15185 // Select the input vector, guarding against out of range extract vector. 15186 unsigned NumElems = VT.getVectorNumElements(); 15187 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 15188 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 15189 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 15190 : InVec.getOperand(1); 15191 15192 // If inputs to shuffle are the same for both ops, then allow 2 uses 15193 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 15194 15195 if (LdNode.getOpcode() == ISD::BITCAST) { 15196 // Don't duplicate a load with other uses. 15197 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 15198 return SDValue(); 15199 15200 AllowedUses = 1; // only allow 1 load use if we have a bitcast 15201 LdNode = LdNode.getOperand(0); 15202 } 15203 15204 if (!ISD::isNormalLoad(LdNode.getNode())) 15205 return SDValue(); 15206 15207 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 15208 15209 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 15210 return SDValue(); 15211 15212 if (HasShuffleIntoBitcast) { 15213 // If there's a bitcast before the shuffle, check if the load type and 15214 // alignment is valid. 15215 unsigned Align = LN0->getAlignment(); 15216 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15217 unsigned NewAlign = TLI.getDataLayout()-> 15218 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 15219 15220 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 15221 return SDValue(); 15222 } 15223 15224 // All checks match so transform back to vector_shuffle so that DAG combiner 15225 // can finish the job 15226 DebugLoc dl = N->getDebugLoc(); 15227 15228 // Create shuffle node taking into account the case that its a unary shuffle 15229 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 15230 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 15231 InVec.getOperand(0), Shuffle, 15232 &ShuffleMask[0]); 15233 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 15234 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 15235 EltNo); 15236} 15237 15238/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 15239/// generation and convert it from being a bunch of shuffles and extracts 15240/// to a simple store and scalar loads to extract the elements. 15241static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 15242 TargetLowering::DAGCombinerInfo &DCI) { 15243 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 15244 if (NewOp.getNode()) 15245 return NewOp; 15246 15247 SDValue InputVector = N->getOperand(0); 15248 // Detect whether we are trying to convert from mmx to i32 and the bitcast 15249 // from mmx to v2i32 has a single usage. 15250 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST && 15251 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx && 15252 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32) 15253 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(), 15254 N->getValueType(0), 15255 InputVector.getNode()->getOperand(0)); 15256 15257 // Only operate on vectors of 4 elements, where the alternative shuffling 15258 // gets to be more expensive. 15259 if (InputVector.getValueType() != MVT::v4i32) 15260 return SDValue(); 15261 15262 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 15263 // single use which is a sign-extend or zero-extend, and all elements are 15264 // used. 15265 SmallVector<SDNode *, 4> Uses; 15266 unsigned ExtractedElements = 0; 15267 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 15268 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 15269 if (UI.getUse().getResNo() != InputVector.getResNo()) 15270 return SDValue(); 15271 15272 SDNode *Extract = *UI; 15273 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 15274 return SDValue(); 15275 15276 if (Extract->getValueType(0) != MVT::i32) 15277 return SDValue(); 15278 if (!Extract->hasOneUse()) 15279 return SDValue(); 15280 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 15281 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 15282 return SDValue(); 15283 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 15284 return SDValue(); 15285 15286 // Record which element was extracted. 15287 ExtractedElements |= 15288 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 15289 15290 Uses.push_back(Extract); 15291 } 15292 15293 // If not all the elements were used, this may not be worthwhile. 15294 if (ExtractedElements != 15) 15295 return SDValue(); 15296 15297 // Ok, we've now decided to do the transformation. 15298 DebugLoc dl = InputVector.getDebugLoc(); 15299 15300 // Store the value to a temporary stack slot. 15301 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 15302 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 15303 MachinePointerInfo(), false, false, 0); 15304 15305 // Replace each use (extract) with a load of the appropriate element. 15306 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 15307 UE = Uses.end(); UI != UE; ++UI) { 15308 SDNode *Extract = *UI; 15309 15310 // cOMpute the element's address. 15311 SDValue Idx = Extract->getOperand(1); 15312 unsigned EltSize = 15313 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 15314 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 15315 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15316 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 15317 15318 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 15319 StackPtr, OffsetVal); 15320 15321 // Load the scalar. 15322 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 15323 ScalarAddr, MachinePointerInfo(), 15324 false, false, false, 0); 15325 15326 // Replace the exact with the load. 15327 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 15328 } 15329 15330 // The replacement was made in place; don't return anything. 15331 return SDValue(); 15332} 15333 15334/// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match. 15335static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, 15336 SDValue RHS, SelectionDAG &DAG, 15337 const X86Subtarget *Subtarget) { 15338 if (!VT.isVector()) 15339 return 0; 15340 15341 switch (VT.getSimpleVT().SimpleTy) { 15342 default: return 0; 15343 case MVT::v32i8: 15344 case MVT::v16i16: 15345 case MVT::v8i32: 15346 if (!Subtarget->hasAVX2()) 15347 return 0; 15348 case MVT::v16i8: 15349 case MVT::v8i16: 15350 case MVT::v4i32: 15351 if (!Subtarget->hasSSE2()) 15352 return 0; 15353 } 15354 15355 // SSE2 has only a small subset of the operations. 15356 bool hasUnsigned = Subtarget->hasSSE41() || 15357 (Subtarget->hasSSE2() && VT == MVT::v16i8); 15358 bool hasSigned = Subtarget->hasSSE41() || 15359 (Subtarget->hasSSE2() && VT == MVT::v8i16); 15360 15361 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 15362 15363 // Check for x CC y ? x : y. 15364 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 15365 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 15366 switch (CC) { 15367 default: break; 15368 case ISD::SETULT: 15369 case ISD::SETULE: 15370 return hasUnsigned ? X86ISD::UMIN : 0; 15371 case ISD::SETUGT: 15372 case ISD::SETUGE: 15373 return hasUnsigned ? X86ISD::UMAX : 0; 15374 case ISD::SETLT: 15375 case ISD::SETLE: 15376 return hasSigned ? X86ISD::SMIN : 0; 15377 case ISD::SETGT: 15378 case ISD::SETGE: 15379 return hasSigned ? X86ISD::SMAX : 0; 15380 } 15381 // Check for x CC y ? y : x -- a min/max with reversed arms. 15382 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 15383 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 15384 switch (CC) { 15385 default: break; 15386 case ISD::SETULT: 15387 case ISD::SETULE: 15388 return hasUnsigned ? X86ISD::UMAX : 0; 15389 case ISD::SETUGT: 15390 case ISD::SETUGE: 15391 return hasUnsigned ? X86ISD::UMIN : 0; 15392 case ISD::SETLT: 15393 case ISD::SETLE: 15394 return hasSigned ? X86ISD::SMAX : 0; 15395 case ISD::SETGT: 15396 case ISD::SETGE: 15397 return hasSigned ? X86ISD::SMIN : 0; 15398 } 15399 } 15400 15401 return 0; 15402} 15403 15404/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 15405/// nodes. 15406static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 15407 TargetLowering::DAGCombinerInfo &DCI, 15408 const X86Subtarget *Subtarget) { 15409 DebugLoc DL = N->getDebugLoc(); 15410 SDValue Cond = N->getOperand(0); 15411 // Get the LHS/RHS of the select. 15412 SDValue LHS = N->getOperand(1); 15413 SDValue RHS = N->getOperand(2); 15414 EVT VT = LHS.getValueType(); 15415 15416 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 15417 // instructions match the semantics of the common C idiom x<y?x:y but not 15418 // x<=y?x:y, because of how they handle negative zero (which can be 15419 // ignored in unsafe-math mode). 15420 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 15421 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 15422 (Subtarget->hasSSE2() || 15423 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 15424 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 15425 15426 unsigned Opcode = 0; 15427 // Check for x CC y ? x : y. 15428 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 15429 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 15430 switch (CC) { 15431 default: break; 15432 case ISD::SETULT: 15433 // Converting this to a min would handle NaNs incorrectly, and swapping 15434 // the operands would cause it to handle comparisons between positive 15435 // and negative zero incorrectly. 15436 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 15437 if (!DAG.getTarget().Options.UnsafeFPMath && 15438 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 15439 break; 15440 std::swap(LHS, RHS); 15441 } 15442 Opcode = X86ISD::FMIN; 15443 break; 15444 case ISD::SETOLE: 15445 // Converting this to a min would handle comparisons between positive 15446 // and negative zero incorrectly. 15447 if (!DAG.getTarget().Options.UnsafeFPMath && 15448 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 15449 break; 15450 Opcode = X86ISD::FMIN; 15451 break; 15452 case ISD::SETULE: 15453 // Converting this to a min would handle both negative zeros and NaNs 15454 // incorrectly, but we can swap the operands to fix both. 15455 std::swap(LHS, RHS); 15456 case ISD::SETOLT: 15457 case ISD::SETLT: 15458 case ISD::SETLE: 15459 Opcode = X86ISD::FMIN; 15460 break; 15461 15462 case ISD::SETOGE: 15463 // Converting this to a max would handle comparisons between positive 15464 // and negative zero incorrectly. 15465 if (!DAG.getTarget().Options.UnsafeFPMath && 15466 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 15467 break; 15468 Opcode = X86ISD::FMAX; 15469 break; 15470 case ISD::SETUGT: 15471 // Converting this to a max would handle NaNs incorrectly, and swapping 15472 // the operands would cause it to handle comparisons between positive 15473 // and negative zero incorrectly. 15474 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 15475 if (!DAG.getTarget().Options.UnsafeFPMath && 15476 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 15477 break; 15478 std::swap(LHS, RHS); 15479 } 15480 Opcode = X86ISD::FMAX; 15481 break; 15482 case ISD::SETUGE: 15483 // Converting this to a max would handle both negative zeros and NaNs 15484 // incorrectly, but we can swap the operands to fix both. 15485 std::swap(LHS, RHS); 15486 case ISD::SETOGT: 15487 case ISD::SETGT: 15488 case ISD::SETGE: 15489 Opcode = X86ISD::FMAX; 15490 break; 15491 } 15492 // Check for x CC y ? y : x -- a min/max with reversed arms. 15493 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 15494 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 15495 switch (CC) { 15496 default: break; 15497 case ISD::SETOGE: 15498 // Converting this to a min would handle comparisons between positive 15499 // and negative zero incorrectly, and swapping the operands would 15500 // cause it to handle NaNs incorrectly. 15501 if (!DAG.getTarget().Options.UnsafeFPMath && 15502 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 15503 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 15504 break; 15505 std::swap(LHS, RHS); 15506 } 15507 Opcode = X86ISD::FMIN; 15508 break; 15509 case ISD::SETUGT: 15510 // Converting this to a min would handle NaNs incorrectly. 15511 if (!DAG.getTarget().Options.UnsafeFPMath && 15512 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 15513 break; 15514 Opcode = X86ISD::FMIN; 15515 break; 15516 case ISD::SETUGE: 15517 // Converting this to a min would handle both negative zeros and NaNs 15518 // incorrectly, but we can swap the operands to fix both. 15519 std::swap(LHS, RHS); 15520 case ISD::SETOGT: 15521 case ISD::SETGT: 15522 case ISD::SETGE: 15523 Opcode = X86ISD::FMIN; 15524 break; 15525 15526 case ISD::SETULT: 15527 // Converting this to a max would handle NaNs incorrectly. 15528 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 15529 break; 15530 Opcode = X86ISD::FMAX; 15531 break; 15532 case ISD::SETOLE: 15533 // Converting this to a max would handle comparisons between positive 15534 // and negative zero incorrectly, and swapping the operands would 15535 // cause it to handle NaNs incorrectly. 15536 if (!DAG.getTarget().Options.UnsafeFPMath && 15537 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 15538 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 15539 break; 15540 std::swap(LHS, RHS); 15541 } 15542 Opcode = X86ISD::FMAX; 15543 break; 15544 case ISD::SETULE: 15545 // Converting this to a max would handle both negative zeros and NaNs 15546 // incorrectly, but we can swap the operands to fix both. 15547 std::swap(LHS, RHS); 15548 case ISD::SETOLT: 15549 case ISD::SETLT: 15550 case ISD::SETLE: 15551 Opcode = X86ISD::FMAX; 15552 break; 15553 } 15554 } 15555 15556 if (Opcode) 15557 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 15558 } 15559 15560 // If this is a select between two integer constants, try to do some 15561 // optimizations. 15562 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 15563 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 15564 // Don't do this for crazy integer types. 15565 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 15566 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 15567 // so that TrueC (the true value) is larger than FalseC. 15568 bool NeedsCondInvert = false; 15569 15570 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 15571 // Efficiently invertible. 15572 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 15573 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 15574 isa<ConstantSDNode>(Cond.getOperand(1))))) { 15575 NeedsCondInvert = true; 15576 std::swap(TrueC, FalseC); 15577 } 15578 15579 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 15580 if (FalseC->getAPIntValue() == 0 && 15581 TrueC->getAPIntValue().isPowerOf2()) { 15582 if (NeedsCondInvert) // Invert the condition if needed. 15583 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 15584 DAG.getConstant(1, Cond.getValueType())); 15585 15586 // Zero extend the condition if needed. 15587 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 15588 15589 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 15590 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 15591 DAG.getConstant(ShAmt, MVT::i8)); 15592 } 15593 15594 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 15595 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 15596 if (NeedsCondInvert) // Invert the condition if needed. 15597 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 15598 DAG.getConstant(1, Cond.getValueType())); 15599 15600 // Zero extend the condition if needed. 15601 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 15602 FalseC->getValueType(0), Cond); 15603 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 15604 SDValue(FalseC, 0)); 15605 } 15606 15607 // Optimize cases that will turn into an LEA instruction. This requires 15608 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 15609 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 15610 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 15611 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 15612 15613 bool isFastMultiplier = false; 15614 if (Diff < 10) { 15615 switch ((unsigned char)Diff) { 15616 default: break; 15617 case 1: // result = add base, cond 15618 case 2: // result = lea base( , cond*2) 15619 case 3: // result = lea base(cond, cond*2) 15620 case 4: // result = lea base( , cond*4) 15621 case 5: // result = lea base(cond, cond*4) 15622 case 8: // result = lea base( , cond*8) 15623 case 9: // result = lea base(cond, cond*8) 15624 isFastMultiplier = true; 15625 break; 15626 } 15627 } 15628 15629 if (isFastMultiplier) { 15630 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 15631 if (NeedsCondInvert) // Invert the condition if needed. 15632 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 15633 DAG.getConstant(1, Cond.getValueType())); 15634 15635 // Zero extend the condition if needed. 15636 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 15637 Cond); 15638 // Scale the condition by the difference. 15639 if (Diff != 1) 15640 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 15641 DAG.getConstant(Diff, Cond.getValueType())); 15642 15643 // Add the base if non-zero. 15644 if (FalseC->getAPIntValue() != 0) 15645 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 15646 SDValue(FalseC, 0)); 15647 return Cond; 15648 } 15649 } 15650 } 15651 } 15652 15653 // Canonicalize max and min: 15654 // (x > y) ? x : y -> (x >= y) ? x : y 15655 // (x < y) ? x : y -> (x <= y) ? x : y 15656 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 15657 // the need for an extra compare 15658 // against zero. e.g. 15659 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 15660 // subl %esi, %edi 15661 // testl %edi, %edi 15662 // movl $0, %eax 15663 // cmovgl %edi, %eax 15664 // => 15665 // xorl %eax, %eax 15666 // subl %esi, $edi 15667 // cmovsl %eax, %edi 15668 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 15669 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 15670 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 15671 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 15672 switch (CC) { 15673 default: break; 15674 case ISD::SETLT: 15675 case ISD::SETGT: { 15676 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 15677 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 15678 Cond.getOperand(0), Cond.getOperand(1), NewCC); 15679 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 15680 } 15681 } 15682 } 15683 15684 // Match VSELECTs into subs with unsigned saturation. 15685 if (!DCI.isBeforeLegalize() && 15686 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC && 15687 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors. 15688 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) || 15689 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) { 15690 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 15691 15692 // Check if one of the arms of the VSELECT is a zero vector. If it's on the 15693 // left side invert the predicate to simplify logic below. 15694 SDValue Other; 15695 if (ISD::isBuildVectorAllZeros(LHS.getNode())) { 15696 Other = RHS; 15697 CC = ISD::getSetCCInverse(CC, true); 15698 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) { 15699 Other = LHS; 15700 } 15701 15702 if (Other.getNode() && Other->getNumOperands() == 2 && 15703 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) { 15704 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1); 15705 SDValue CondRHS = Cond->getOperand(1); 15706 15707 // Look for a general sub with unsigned saturation first. 15708 // x >= y ? x-y : 0 --> subus x, y 15709 // x > y ? x-y : 0 --> subus x, y 15710 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) && 15711 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS)) 15712 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS); 15713 15714 // If the RHS is a constant we have to reverse the const canonicalization. 15715 // x > C-1 ? x+-C : 0 --> subus x, C 15716 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD && 15717 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) { 15718 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue(); 15719 if (CondRHS.getConstantOperandVal(0) == -A-1) 15720 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, 15721 DAG.getConstant(-A, VT)); 15722 } 15723 15724 // Another special case: If C was a sign bit, the sub has been 15725 // canonicalized into a xor. 15726 // FIXME: Would it be better to use ComputeMaskedBits to determine whether 15727 // it's safe to decanonicalize the xor? 15728 // x s< 0 ? x^C : 0 --> subus x, C 15729 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR && 15730 ISD::isBuildVectorAllZeros(CondRHS.getNode()) && 15731 isSplatVector(OpRHS.getNode())) { 15732 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue(); 15733 if (A.isSignBit()) 15734 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS); 15735 } 15736 } 15737 } 15738 15739 // Try to match a min/max vector operation. 15740 if (!DCI.isBeforeLegalize() && 15741 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) 15742 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget)) 15743 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS); 15744 15745 // If we know that this node is legal then we know that it is going to be 15746 // matched by one of the SSE/AVX BLEND instructions. These instructions only 15747 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 15748 // to simplify previous instructions. 15749 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15750 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 15751 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) { 15752 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 15753 15754 // Don't optimize vector selects that map to mask-registers. 15755 if (BitWidth == 1) 15756 return SDValue(); 15757 15758 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 15759 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 15760 15761 APInt KnownZero, KnownOne; 15762 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 15763 DCI.isBeforeLegalizeOps()); 15764 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 15765 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 15766 DCI.CommitTargetLoweringOpt(TLO); 15767 } 15768 15769 return SDValue(); 15770} 15771 15772// Check whether a boolean test is testing a boolean value generated by 15773// X86ISD::SETCC. If so, return the operand of that SETCC and proper condition 15774// code. 15775// 15776// Simplify the following patterns: 15777// (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or 15778// (Op (CMP (SETCC Cond EFLAGS) 0) NEQ) 15779// to (Op EFLAGS Cond) 15780// 15781// (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or 15782// (Op (CMP (SETCC Cond EFLAGS) 1) NEQ) 15783// to (Op EFLAGS !Cond) 15784// 15785// where Op could be BRCOND or CMOV. 15786// 15787static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) { 15788 // Quit if not CMP and SUB with its value result used. 15789 if (Cmp.getOpcode() != X86ISD::CMP && 15790 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0))) 15791 return SDValue(); 15792 15793 // Quit if not used as a boolean value. 15794 if (CC != X86::COND_E && CC != X86::COND_NE) 15795 return SDValue(); 15796 15797 // Check CMP operands. One of them should be 0 or 1 and the other should be 15798 // an SetCC or extended from it. 15799 SDValue Op1 = Cmp.getOperand(0); 15800 SDValue Op2 = Cmp.getOperand(1); 15801 15802 SDValue SetCC; 15803 const ConstantSDNode* C = 0; 15804 bool needOppositeCond = (CC == X86::COND_E); 15805 15806 if ((C = dyn_cast<ConstantSDNode>(Op1))) 15807 SetCC = Op2; 15808 else if ((C = dyn_cast<ConstantSDNode>(Op2))) 15809 SetCC = Op1; 15810 else // Quit if all operands are not constants. 15811 return SDValue(); 15812 15813 if (C->getZExtValue() == 1) 15814 needOppositeCond = !needOppositeCond; 15815 else if (C->getZExtValue() != 0) 15816 // Quit if the constant is neither 0 or 1. 15817 return SDValue(); 15818 15819 // Skip 'zext' node. 15820 if (SetCC.getOpcode() == ISD::ZERO_EXTEND) 15821 SetCC = SetCC.getOperand(0); 15822 15823 switch (SetCC.getOpcode()) { 15824 case X86ISD::SETCC: 15825 // Set the condition code or opposite one if necessary. 15826 CC = X86::CondCode(SetCC.getConstantOperandVal(0)); 15827 if (needOppositeCond) 15828 CC = X86::GetOppositeBranchCondition(CC); 15829 return SetCC.getOperand(1); 15830 case X86ISD::CMOV: { 15831 // Check whether false/true value has canonical one, i.e. 0 or 1. 15832 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0)); 15833 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1)); 15834 // Quit if true value is not a constant. 15835 if (!TVal) 15836 return SDValue(); 15837 // Quit if false value is not a constant. 15838 if (!FVal) { 15839 // A special case for rdrand, where 0 is set if false cond is found. 15840 SDValue Op = SetCC.getOperand(0); 15841 if (Op.getOpcode() != X86ISD::RDRAND) 15842 return SDValue(); 15843 } 15844 // Quit if false value is not the constant 0 or 1. 15845 bool FValIsFalse = true; 15846 if (FVal && FVal->getZExtValue() != 0) { 15847 if (FVal->getZExtValue() != 1) 15848 return SDValue(); 15849 // If FVal is 1, opposite cond is needed. 15850 needOppositeCond = !needOppositeCond; 15851 FValIsFalse = false; 15852 } 15853 // Quit if TVal is not the constant opposite of FVal. 15854 if (FValIsFalse && TVal->getZExtValue() != 1) 15855 return SDValue(); 15856 if (!FValIsFalse && TVal->getZExtValue() != 0) 15857 return SDValue(); 15858 CC = X86::CondCode(SetCC.getConstantOperandVal(2)); 15859 if (needOppositeCond) 15860 CC = X86::GetOppositeBranchCondition(CC); 15861 return SetCC.getOperand(3); 15862 } 15863 } 15864 15865 return SDValue(); 15866} 15867 15868/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 15869static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 15870 TargetLowering::DAGCombinerInfo &DCI, 15871 const X86Subtarget *Subtarget) { 15872 DebugLoc DL = N->getDebugLoc(); 15873 15874 // If the flag operand isn't dead, don't touch this CMOV. 15875 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 15876 return SDValue(); 15877 15878 SDValue FalseOp = N->getOperand(0); 15879 SDValue TrueOp = N->getOperand(1); 15880 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 15881 SDValue Cond = N->getOperand(3); 15882 15883 if (CC == X86::COND_E || CC == X86::COND_NE) { 15884 switch (Cond.getOpcode()) { 15885 default: break; 15886 case X86ISD::BSR: 15887 case X86ISD::BSF: 15888 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 15889 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 15890 return (CC == X86::COND_E) ? FalseOp : TrueOp; 15891 } 15892 } 15893 15894 SDValue Flags; 15895 15896 Flags = checkBoolTestSetCCCombine(Cond, CC); 15897 if (Flags.getNode() && 15898 // Extra check as FCMOV only supports a subset of X86 cond. 15899 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) { 15900 SDValue Ops[] = { FalseOp, TrueOp, 15901 DAG.getConstant(CC, MVT::i8), Flags }; 15902 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), 15903 Ops, array_lengthof(Ops)); 15904 } 15905 15906 // If this is a select between two integer constants, try to do some 15907 // optimizations. Note that the operands are ordered the opposite of SELECT 15908 // operands. 15909 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 15910 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 15911 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 15912 // larger than FalseC (the false value). 15913 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 15914 CC = X86::GetOppositeBranchCondition(CC); 15915 std::swap(TrueC, FalseC); 15916 std::swap(TrueOp, FalseOp); 15917 } 15918 15919 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 15920 // This is efficient for any integer data type (including i8/i16) and 15921 // shift amount. 15922 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 15923 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 15924 DAG.getConstant(CC, MVT::i8), Cond); 15925 15926 // Zero extend the condition if needed. 15927 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 15928 15929 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 15930 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 15931 DAG.getConstant(ShAmt, MVT::i8)); 15932 if (N->getNumValues() == 2) // Dead flag value? 15933 return DCI.CombineTo(N, Cond, SDValue()); 15934 return Cond; 15935 } 15936 15937 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 15938 // for any integer data type, including i8/i16. 15939 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 15940 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 15941 DAG.getConstant(CC, MVT::i8), Cond); 15942 15943 // Zero extend the condition if needed. 15944 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 15945 FalseC->getValueType(0), Cond); 15946 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 15947 SDValue(FalseC, 0)); 15948 15949 if (N->getNumValues() == 2) // Dead flag value? 15950 return DCI.CombineTo(N, Cond, SDValue()); 15951 return Cond; 15952 } 15953 15954 // Optimize cases that will turn into an LEA instruction. This requires 15955 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 15956 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 15957 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 15958 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 15959 15960 bool isFastMultiplier = false; 15961 if (Diff < 10) { 15962 switch ((unsigned char)Diff) { 15963 default: break; 15964 case 1: // result = add base, cond 15965 case 2: // result = lea base( , cond*2) 15966 case 3: // result = lea base(cond, cond*2) 15967 case 4: // result = lea base( , cond*4) 15968 case 5: // result = lea base(cond, cond*4) 15969 case 8: // result = lea base( , cond*8) 15970 case 9: // result = lea base(cond, cond*8) 15971 isFastMultiplier = true; 15972 break; 15973 } 15974 } 15975 15976 if (isFastMultiplier) { 15977 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 15978 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 15979 DAG.getConstant(CC, MVT::i8), Cond); 15980 // Zero extend the condition if needed. 15981 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 15982 Cond); 15983 // Scale the condition by the difference. 15984 if (Diff != 1) 15985 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 15986 DAG.getConstant(Diff, Cond.getValueType())); 15987 15988 // Add the base if non-zero. 15989 if (FalseC->getAPIntValue() != 0) 15990 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 15991 SDValue(FalseC, 0)); 15992 if (N->getNumValues() == 2) // Dead flag value? 15993 return DCI.CombineTo(N, Cond, SDValue()); 15994 return Cond; 15995 } 15996 } 15997 } 15998 } 15999 16000 // Handle these cases: 16001 // (select (x != c), e, c) -> select (x != c), e, x), 16002 // (select (x == c), c, e) -> select (x == c), x, e) 16003 // where the c is an integer constant, and the "select" is the combination 16004 // of CMOV and CMP. 16005 // 16006 // The rationale for this change is that the conditional-move from a constant 16007 // needs two instructions, however, conditional-move from a register needs 16008 // only one instruction. 16009 // 16010 // CAVEAT: By replacing a constant with a symbolic value, it may obscure 16011 // some instruction-combining opportunities. This opt needs to be 16012 // postponed as late as possible. 16013 // 16014 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { 16015 // the DCI.xxxx conditions are provided to postpone the optimization as 16016 // late as possible. 16017 16018 ConstantSDNode *CmpAgainst = 0; 16019 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) && 16020 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) && 16021 !isa<ConstantSDNode>(Cond.getOperand(0))) { 16022 16023 if (CC == X86::COND_NE && 16024 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) { 16025 CC = X86::GetOppositeBranchCondition(CC); 16026 std::swap(TrueOp, FalseOp); 16027 } 16028 16029 if (CC == X86::COND_E && 16030 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) { 16031 SDValue Ops[] = { FalseOp, Cond.getOperand(0), 16032 DAG.getConstant(CC, MVT::i8), Cond }; 16033 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops, 16034 array_lengthof(Ops)); 16035 } 16036 } 16037 } 16038 16039 return SDValue(); 16040} 16041 16042/// PerformMulCombine - Optimize a single multiply with constant into two 16043/// in order to implement it with two cheaper instructions, e.g. 16044/// LEA + SHL, LEA + LEA. 16045static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 16046 TargetLowering::DAGCombinerInfo &DCI) { 16047 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 16048 return SDValue(); 16049 16050 EVT VT = N->getValueType(0); 16051 if (VT != MVT::i64) 16052 return SDValue(); 16053 16054 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 16055 if (!C) 16056 return SDValue(); 16057 uint64_t MulAmt = C->getZExtValue(); 16058 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 16059 return SDValue(); 16060 16061 uint64_t MulAmt1 = 0; 16062 uint64_t MulAmt2 = 0; 16063 if ((MulAmt % 9) == 0) { 16064 MulAmt1 = 9; 16065 MulAmt2 = MulAmt / 9; 16066 } else if ((MulAmt % 5) == 0) { 16067 MulAmt1 = 5; 16068 MulAmt2 = MulAmt / 5; 16069 } else if ((MulAmt % 3) == 0) { 16070 MulAmt1 = 3; 16071 MulAmt2 = MulAmt / 3; 16072 } 16073 if (MulAmt2 && 16074 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 16075 DebugLoc DL = N->getDebugLoc(); 16076 16077 if (isPowerOf2_64(MulAmt2) && 16078 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 16079 // If second multiplifer is pow2, issue it first. We want the multiply by 16080 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 16081 // is an add. 16082 std::swap(MulAmt1, MulAmt2); 16083 16084 SDValue NewMul; 16085 if (isPowerOf2_64(MulAmt1)) 16086 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 16087 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 16088 else 16089 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 16090 DAG.getConstant(MulAmt1, VT)); 16091 16092 if (isPowerOf2_64(MulAmt2)) 16093 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 16094 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 16095 else 16096 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 16097 DAG.getConstant(MulAmt2, VT)); 16098 16099 // Do not add new nodes to DAG combiner worklist. 16100 DCI.CombineTo(N, NewMul, false); 16101 } 16102 return SDValue(); 16103} 16104 16105static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 16106 SDValue N0 = N->getOperand(0); 16107 SDValue N1 = N->getOperand(1); 16108 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 16109 EVT VT = N0.getValueType(); 16110 16111 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 16112 // since the result of setcc_c is all zero's or all ones. 16113 if (VT.isInteger() && !VT.isVector() && 16114 N1C && N0.getOpcode() == ISD::AND && 16115 N0.getOperand(1).getOpcode() == ISD::Constant) { 16116 SDValue N00 = N0.getOperand(0); 16117 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 16118 ((N00.getOpcode() == ISD::ANY_EXTEND || 16119 N00.getOpcode() == ISD::ZERO_EXTEND) && 16120 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 16121 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 16122 APInt ShAmt = N1C->getAPIntValue(); 16123 Mask = Mask.shl(ShAmt); 16124 if (Mask != 0) 16125 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 16126 N00, DAG.getConstant(Mask, VT)); 16127 } 16128 } 16129 16130 // Hardware support for vector shifts is sparse which makes us scalarize the 16131 // vector operations in many cases. Also, on sandybridge ADD is faster than 16132 // shl. 16133 // (shl V, 1) -> add V,V 16134 if (isSplatVector(N1.getNode())) { 16135 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 16136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 16137 // We shift all of the values by one. In many cases we do not have 16138 // hardware support for this operation. This is better expressed as an ADD 16139 // of two values. 16140 if (N1C && (1 == N1C->getZExtValue())) { 16141 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 16142 } 16143 } 16144 16145 return SDValue(); 16146} 16147 16148/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 16149/// when possible. 16150static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 16151 TargetLowering::DAGCombinerInfo &DCI, 16152 const X86Subtarget *Subtarget) { 16153 if (N->getOpcode() == ISD::SHL) { 16154 SDValue V = PerformSHLCombine(N, DAG); 16155 if (V.getNode()) return V; 16156 } 16157 16158 return SDValue(); 16159} 16160 16161// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 16162// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 16163// and friends. Likewise for OR -> CMPNEQSS. 16164static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 16165 TargetLowering::DAGCombinerInfo &DCI, 16166 const X86Subtarget *Subtarget) { 16167 unsigned opcode; 16168 16169 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 16170 // we're requiring SSE2 for both. 16171 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 16172 SDValue N0 = N->getOperand(0); 16173 SDValue N1 = N->getOperand(1); 16174 SDValue CMP0 = N0->getOperand(1); 16175 SDValue CMP1 = N1->getOperand(1); 16176 DebugLoc DL = N->getDebugLoc(); 16177 16178 // The SETCCs should both refer to the same CMP. 16179 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 16180 return SDValue(); 16181 16182 SDValue CMP00 = CMP0->getOperand(0); 16183 SDValue CMP01 = CMP0->getOperand(1); 16184 EVT VT = CMP00.getValueType(); 16185 16186 if (VT == MVT::f32 || VT == MVT::f64) { 16187 bool ExpectingFlags = false; 16188 // Check for any users that want flags: 16189 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 16190 !ExpectingFlags && UI != UE; ++UI) 16191 switch (UI->getOpcode()) { 16192 default: 16193 case ISD::BR_CC: 16194 case ISD::BRCOND: 16195 case ISD::SELECT: 16196 ExpectingFlags = true; 16197 break; 16198 case ISD::CopyToReg: 16199 case ISD::SIGN_EXTEND: 16200 case ISD::ZERO_EXTEND: 16201 case ISD::ANY_EXTEND: 16202 break; 16203 } 16204 16205 if (!ExpectingFlags) { 16206 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 16207 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 16208 16209 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 16210 X86::CondCode tmp = cc0; 16211 cc0 = cc1; 16212 cc1 = tmp; 16213 } 16214 16215 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 16216 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 16217 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 16218 X86ISD::NodeType NTOperator = is64BitFP ? 16219 X86ISD::FSETCCsd : X86ISD::FSETCCss; 16220 // FIXME: need symbolic constants for these magic numbers. 16221 // See X86ATTInstPrinter.cpp:printSSECC(). 16222 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 16223 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 16224 DAG.getConstant(x86cc, MVT::i8)); 16225 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 16226 OnesOrZeroesF); 16227 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 16228 DAG.getConstant(1, MVT::i32)); 16229 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 16230 return OneBitOfTruth; 16231 } 16232 } 16233 } 16234 } 16235 return SDValue(); 16236} 16237 16238/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 16239/// so it can be folded inside ANDNP. 16240static bool CanFoldXORWithAllOnes(const SDNode *N) { 16241 EVT VT = N->getValueType(0); 16242 16243 // Match direct AllOnes for 128 and 256-bit vectors 16244 if (ISD::isBuildVectorAllOnes(N)) 16245 return true; 16246 16247 // Look through a bit convert. 16248 if (N->getOpcode() == ISD::BITCAST) 16249 N = N->getOperand(0).getNode(); 16250 16251 // Sometimes the operand may come from a insert_subvector building a 256-bit 16252 // allones vector 16253 if (VT.is256BitVector() && 16254 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 16255 SDValue V1 = N->getOperand(0); 16256 SDValue V2 = N->getOperand(1); 16257 16258 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 16259 V1.getOperand(0).getOpcode() == ISD::UNDEF && 16260 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 16261 ISD::isBuildVectorAllOnes(V2.getNode())) 16262 return true; 16263 } 16264 16265 return false; 16266} 16267 16268// On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized 16269// register. In most cases we actually compare or select YMM-sized registers 16270// and mixing the two types creates horrible code. This method optimizes 16271// some of the transition sequences. 16272static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG, 16273 TargetLowering::DAGCombinerInfo &DCI, 16274 const X86Subtarget *Subtarget) { 16275 EVT VT = N->getValueType(0); 16276 if (!VT.is256BitVector()) 16277 return SDValue(); 16278 16279 assert((N->getOpcode() == ISD::ANY_EXTEND || 16280 N->getOpcode() == ISD::ZERO_EXTEND || 16281 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node"); 16282 16283 SDValue Narrow = N->getOperand(0); 16284 EVT NarrowVT = Narrow->getValueType(0); 16285 if (!NarrowVT.is128BitVector()) 16286 return SDValue(); 16287 16288 if (Narrow->getOpcode() != ISD::XOR && 16289 Narrow->getOpcode() != ISD::AND && 16290 Narrow->getOpcode() != ISD::OR) 16291 return SDValue(); 16292 16293 SDValue N0 = Narrow->getOperand(0); 16294 SDValue N1 = Narrow->getOperand(1); 16295 DebugLoc DL = Narrow->getDebugLoc(); 16296 16297 // The Left side has to be a trunc. 16298 if (N0.getOpcode() != ISD::TRUNCATE) 16299 return SDValue(); 16300 16301 // The type of the truncated inputs. 16302 EVT WideVT = N0->getOperand(0)->getValueType(0); 16303 if (WideVT != VT) 16304 return SDValue(); 16305 16306 // The right side has to be a 'trunc' or a constant vector. 16307 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE; 16308 bool RHSConst = (isSplatVector(N1.getNode()) && 16309 isa<ConstantSDNode>(N1->getOperand(0))); 16310 if (!RHSTrunc && !RHSConst) 16311 return SDValue(); 16312 16313 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16314 16315 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT)) 16316 return SDValue(); 16317 16318 // Set N0 and N1 to hold the inputs to the new wide operation. 16319 N0 = N0->getOperand(0); 16320 if (RHSConst) { 16321 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(), 16322 N1->getOperand(0)); 16323 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1); 16324 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size()); 16325 } else if (RHSTrunc) { 16326 N1 = N1->getOperand(0); 16327 } 16328 16329 // Generate the wide operation. 16330 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1); 16331 unsigned Opcode = N->getOpcode(); 16332 switch (Opcode) { 16333 case ISD::ANY_EXTEND: 16334 return Op; 16335 case ISD::ZERO_EXTEND: { 16336 unsigned InBits = NarrowVT.getScalarType().getSizeInBits(); 16337 APInt Mask = APInt::getAllOnesValue(InBits); 16338 Mask = Mask.zext(VT.getScalarType().getSizeInBits()); 16339 return DAG.getNode(ISD::AND, DL, VT, 16340 Op, DAG.getConstant(Mask, VT)); 16341 } 16342 case ISD::SIGN_EXTEND: 16343 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, 16344 Op, DAG.getValueType(NarrowVT)); 16345 default: 16346 llvm_unreachable("Unexpected opcode"); 16347 } 16348} 16349 16350static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 16351 TargetLowering::DAGCombinerInfo &DCI, 16352 const X86Subtarget *Subtarget) { 16353 EVT VT = N->getValueType(0); 16354 if (DCI.isBeforeLegalizeOps()) 16355 return SDValue(); 16356 16357 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 16358 if (R.getNode()) 16359 return R; 16360 16361 // Create BLSI, and BLSR instructions 16362 // BLSI is X & (-X) 16363 // BLSR is X & (X-1) 16364 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 16365 SDValue N0 = N->getOperand(0); 16366 SDValue N1 = N->getOperand(1); 16367 DebugLoc DL = N->getDebugLoc(); 16368 16369 // Check LHS for neg 16370 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 16371 isZero(N0.getOperand(0))) 16372 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 16373 16374 // Check RHS for neg 16375 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 16376 isZero(N1.getOperand(0))) 16377 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 16378 16379 // Check LHS for X-1 16380 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 16381 isAllOnes(N0.getOperand(1))) 16382 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 16383 16384 // Check RHS for X-1 16385 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 16386 isAllOnes(N1.getOperand(1))) 16387 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 16388 16389 return SDValue(); 16390 } 16391 16392 // Want to form ANDNP nodes: 16393 // 1) In the hopes of then easily combining them with OR and AND nodes 16394 // to form PBLEND/PSIGN. 16395 // 2) To match ANDN packed intrinsics 16396 if (VT != MVT::v2i64 && VT != MVT::v4i64) 16397 return SDValue(); 16398 16399 SDValue N0 = N->getOperand(0); 16400 SDValue N1 = N->getOperand(1); 16401 DebugLoc DL = N->getDebugLoc(); 16402 16403 // Check LHS for vnot 16404 if (N0.getOpcode() == ISD::XOR && 16405 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 16406 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 16407 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 16408 16409 // Check RHS for vnot 16410 if (N1.getOpcode() == ISD::XOR && 16411 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 16412 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 16413 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 16414 16415 return SDValue(); 16416} 16417 16418static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 16419 TargetLowering::DAGCombinerInfo &DCI, 16420 const X86Subtarget *Subtarget) { 16421 EVT VT = N->getValueType(0); 16422 if (DCI.isBeforeLegalizeOps()) 16423 return SDValue(); 16424 16425 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 16426 if (R.getNode()) 16427 return R; 16428 16429 SDValue N0 = N->getOperand(0); 16430 SDValue N1 = N->getOperand(1); 16431 16432 // look for psign/blend 16433 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 16434 if (!Subtarget->hasSSSE3() || 16435 (VT == MVT::v4i64 && !Subtarget->hasInt256())) 16436 return SDValue(); 16437 16438 // Canonicalize pandn to RHS 16439 if (N0.getOpcode() == X86ISD::ANDNP) 16440 std::swap(N0, N1); 16441 // or (and (m, y), (pandn m, x)) 16442 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 16443 SDValue Mask = N1.getOperand(0); 16444 SDValue X = N1.getOperand(1); 16445 SDValue Y; 16446 if (N0.getOperand(0) == Mask) 16447 Y = N0.getOperand(1); 16448 if (N0.getOperand(1) == Mask) 16449 Y = N0.getOperand(0); 16450 16451 // Check to see if the mask appeared in both the AND and ANDNP and 16452 if (!Y.getNode()) 16453 return SDValue(); 16454 16455 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 16456 // Look through mask bitcast. 16457 if (Mask.getOpcode() == ISD::BITCAST) 16458 Mask = Mask.getOperand(0); 16459 if (X.getOpcode() == ISD::BITCAST) 16460 X = X.getOperand(0); 16461 if (Y.getOpcode() == ISD::BITCAST) 16462 Y = Y.getOperand(0); 16463 16464 EVT MaskVT = Mask.getValueType(); 16465 16466 // Validate that the Mask operand is a vector sra node. 16467 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 16468 // there is no psrai.b 16469 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 16470 unsigned SraAmt = ~0; 16471 if (Mask.getOpcode() == ISD::SRA) { 16472 SDValue Amt = Mask.getOperand(1); 16473 if (isSplatVector(Amt.getNode())) { 16474 SDValue SclrAmt = Amt->getOperand(0); 16475 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) 16476 SraAmt = C->getZExtValue(); 16477 } 16478 } else if (Mask.getOpcode() == X86ISD::VSRAI) { 16479 SDValue SraC = Mask.getOperand(1); 16480 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 16481 } 16482 if ((SraAmt + 1) != EltBits) 16483 return SDValue(); 16484 16485 DebugLoc DL = N->getDebugLoc(); 16486 16487 // Now we know we at least have a plendvb with the mask val. See if 16488 // we can form a psignb/w/d. 16489 // psign = x.type == y.type == mask.type && y = sub(0, x); 16490 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 16491 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 16492 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 16493 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 16494 "Unsupported VT for PSIGN"); 16495 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 16496 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 16497 } 16498 // PBLENDVB only available on SSE 4.1 16499 if (!Subtarget->hasSSE41()) 16500 return SDValue(); 16501 16502 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 16503 16504 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 16505 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 16506 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 16507 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 16508 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 16509 } 16510 } 16511 16512 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 16513 return SDValue(); 16514 16515 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 16516 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 16517 std::swap(N0, N1); 16518 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 16519 return SDValue(); 16520 if (!N0.hasOneUse() || !N1.hasOneUse()) 16521 return SDValue(); 16522 16523 SDValue ShAmt0 = N0.getOperand(1); 16524 if (ShAmt0.getValueType() != MVT::i8) 16525 return SDValue(); 16526 SDValue ShAmt1 = N1.getOperand(1); 16527 if (ShAmt1.getValueType() != MVT::i8) 16528 return SDValue(); 16529 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 16530 ShAmt0 = ShAmt0.getOperand(0); 16531 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 16532 ShAmt1 = ShAmt1.getOperand(0); 16533 16534 DebugLoc DL = N->getDebugLoc(); 16535 unsigned Opc = X86ISD::SHLD; 16536 SDValue Op0 = N0.getOperand(0); 16537 SDValue Op1 = N1.getOperand(0); 16538 if (ShAmt0.getOpcode() == ISD::SUB) { 16539 Opc = X86ISD::SHRD; 16540 std::swap(Op0, Op1); 16541 std::swap(ShAmt0, ShAmt1); 16542 } 16543 16544 unsigned Bits = VT.getSizeInBits(); 16545 if (ShAmt1.getOpcode() == ISD::SUB) { 16546 SDValue Sum = ShAmt1.getOperand(0); 16547 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 16548 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 16549 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 16550 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 16551 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 16552 return DAG.getNode(Opc, DL, VT, 16553 Op0, Op1, 16554 DAG.getNode(ISD::TRUNCATE, DL, 16555 MVT::i8, ShAmt0)); 16556 } 16557 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 16558 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 16559 if (ShAmt0C && 16560 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 16561 return DAG.getNode(Opc, DL, VT, 16562 N0.getOperand(0), N1.getOperand(0), 16563 DAG.getNode(ISD::TRUNCATE, DL, 16564 MVT::i8, ShAmt0)); 16565 } 16566 16567 return SDValue(); 16568} 16569 16570// Generate NEG and CMOV for integer abs. 16571static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) { 16572 EVT VT = N->getValueType(0); 16573 16574 // Since X86 does not have CMOV for 8-bit integer, we don't convert 16575 // 8-bit integer abs to NEG and CMOV. 16576 if (VT.isInteger() && VT.getSizeInBits() == 8) 16577 return SDValue(); 16578 16579 SDValue N0 = N->getOperand(0); 16580 SDValue N1 = N->getOperand(1); 16581 DebugLoc DL = N->getDebugLoc(); 16582 16583 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1) 16584 // and change it to SUB and CMOV. 16585 if (VT.isInteger() && N->getOpcode() == ISD::XOR && 16586 N0.getOpcode() == ISD::ADD && 16587 N0.getOperand(1) == N1 && 16588 N1.getOpcode() == ISD::SRA && 16589 N1.getOperand(0) == N0.getOperand(0)) 16590 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 16591 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) { 16592 // Generate SUB & CMOV. 16593 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32), 16594 DAG.getConstant(0, VT), N0.getOperand(0)); 16595 16596 SDValue Ops[] = { N0.getOperand(0), Neg, 16597 DAG.getConstant(X86::COND_GE, MVT::i8), 16598 SDValue(Neg.getNode(), 1) }; 16599 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), 16600 Ops, array_lengthof(Ops)); 16601 } 16602 return SDValue(); 16603} 16604 16605// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 16606static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 16607 TargetLowering::DAGCombinerInfo &DCI, 16608 const X86Subtarget *Subtarget) { 16609 EVT VT = N->getValueType(0); 16610 if (DCI.isBeforeLegalizeOps()) 16611 return SDValue(); 16612 16613 if (Subtarget->hasCMov()) { 16614 SDValue RV = performIntegerAbsCombine(N, DAG); 16615 if (RV.getNode()) 16616 return RV; 16617 } 16618 16619 // Try forming BMI if it is available. 16620 if (!Subtarget->hasBMI()) 16621 return SDValue(); 16622 16623 if (VT != MVT::i32 && VT != MVT::i64) 16624 return SDValue(); 16625 16626 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 16627 16628 // Create BLSMSK instructions by finding X ^ (X-1) 16629 SDValue N0 = N->getOperand(0); 16630 SDValue N1 = N->getOperand(1); 16631 DebugLoc DL = N->getDebugLoc(); 16632 16633 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 16634 isAllOnes(N0.getOperand(1))) 16635 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 16636 16637 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 16638 isAllOnes(N1.getOperand(1))) 16639 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 16640 16641 return SDValue(); 16642} 16643 16644/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 16645static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 16646 TargetLowering::DAGCombinerInfo &DCI, 16647 const X86Subtarget *Subtarget) { 16648 LoadSDNode *Ld = cast<LoadSDNode>(N); 16649 EVT RegVT = Ld->getValueType(0); 16650 EVT MemVT = Ld->getMemoryVT(); 16651 DebugLoc dl = Ld->getDebugLoc(); 16652 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16653 unsigned RegSz = RegVT.getSizeInBits(); 16654 16655 // On Sandybridge unaligned 256bit loads are inefficient. 16656 ISD::LoadExtType Ext = Ld->getExtensionType(); 16657 unsigned Alignment = Ld->getAlignment(); 16658 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8; 16659 if (RegVT.is256BitVector() && !Subtarget->hasInt256() && 16660 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) { 16661 unsigned NumElems = RegVT.getVectorNumElements(); 16662 if (NumElems < 2) 16663 return SDValue(); 16664 16665 SDValue Ptr = Ld->getBasePtr(); 16666 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy()); 16667 16668 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 16669 NumElems/2); 16670 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr, 16671 Ld->getPointerInfo(), Ld->isVolatile(), 16672 Ld->isNonTemporal(), Ld->isInvariant(), 16673 Alignment); 16674 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 16675 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr, 16676 Ld->getPointerInfo(), Ld->isVolatile(), 16677 Ld->isNonTemporal(), Ld->isInvariant(), 16678 std::min(16U, Alignment)); 16679 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 16680 Load1.getValue(1), 16681 Load2.getValue(1)); 16682 16683 SDValue NewVec = DAG.getUNDEF(RegVT); 16684 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl); 16685 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl); 16686 return DCI.CombineTo(N, NewVec, TF, true); 16687 } 16688 16689 // If this is a vector EXT Load then attempt to optimize it using a 16690 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the 16691 // expansion is still better than scalar code. 16692 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll 16693 // emit a shuffle and a arithmetic shift. 16694 // TODO: It is possible to support ZExt by zeroing the undef values 16695 // during the shuffle phase or after the shuffle. 16696 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() && 16697 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) { 16698 assert(MemVT != RegVT && "Cannot extend to the same type"); 16699 assert(MemVT.isVector() && "Must load a vector from memory"); 16700 16701 unsigned NumElems = RegVT.getVectorNumElements(); 16702 unsigned MemSz = MemVT.getSizeInBits(); 16703 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 16704 16705 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) 16706 return SDValue(); 16707 16708 // All sizes must be a power of two. 16709 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) 16710 return SDValue(); 16711 16712 // Attempt to load the original value using scalar loads. 16713 // Find the largest scalar type that divides the total loaded size. 16714 MVT SclrLoadTy = MVT::i8; 16715 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 16716 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 16717 MVT Tp = (MVT::SimpleValueType)tp; 16718 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) { 16719 SclrLoadTy = Tp; 16720 } 16721 } 16722 16723 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 16724 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 && 16725 (64 <= MemSz)) 16726 SclrLoadTy = MVT::f64; 16727 16728 // Calculate the number of scalar loads that we need to perform 16729 // in order to load our vector from memory. 16730 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits(); 16731 if (Ext == ISD::SEXTLOAD && NumLoads > 1) 16732 return SDValue(); 16733 16734 unsigned loadRegZize = RegSz; 16735 if (Ext == ISD::SEXTLOAD && RegSz == 256) 16736 loadRegZize /= 2; 16737 16738 // Represent our vector as a sequence of elements which are the 16739 // largest scalar that we can load. 16740 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 16741 loadRegZize/SclrLoadTy.getSizeInBits()); 16742 16743 // Represent the data using the same element type that is stored in 16744 // memory. In practice, we ''widen'' MemVT. 16745 EVT WideVecVT = 16746 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 16747 loadRegZize/MemVT.getScalarType().getSizeInBits()); 16748 16749 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() && 16750 "Invalid vector type"); 16751 16752 // We can't shuffle using an illegal type. 16753 if (!TLI.isTypeLegal(WideVecVT)) 16754 return SDValue(); 16755 16756 SmallVector<SDValue, 8> Chains; 16757 SDValue Ptr = Ld->getBasePtr(); 16758 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8, 16759 TLI.getPointerTy()); 16760 SDValue Res = DAG.getUNDEF(LoadUnitVecVT); 16761 16762 for (unsigned i = 0; i < NumLoads; ++i) { 16763 // Perform a single load. 16764 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 16765 Ptr, Ld->getPointerInfo(), 16766 Ld->isVolatile(), Ld->isNonTemporal(), 16767 Ld->isInvariant(), Ld->getAlignment()); 16768 Chains.push_back(ScalarLoad.getValue(1)); 16769 // Create the first element type using SCALAR_TO_VECTOR in order to avoid 16770 // another round of DAGCombining. 16771 if (i == 0) 16772 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad); 16773 else 16774 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res, 16775 ScalarLoad, DAG.getIntPtrConstant(i)); 16776 16777 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 16778 } 16779 16780 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 16781 Chains.size()); 16782 16783 // Bitcast the loaded value to a vector of the original element type, in 16784 // the size of the target vector type. 16785 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res); 16786 unsigned SizeRatio = RegSz/MemSz; 16787 16788 if (Ext == ISD::SEXTLOAD) { 16789 // If we have SSE4.1 we can directly emit a VSEXT node. 16790 if (Subtarget->hasSSE41()) { 16791 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec); 16792 return DCI.CombineTo(N, Sext, TF, true); 16793 } 16794 16795 // Otherwise we'll shuffle the small elements in the high bits of the 16796 // larger type and perform an arithmetic shift. If the shift is not legal 16797 // it's better to scalarize. 16798 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT)) 16799 return SDValue(); 16800 16801 // Redistribute the loaded elements into the different locations. 16802 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 16803 for (unsigned i = 0; i != NumElems; ++i) 16804 ShuffleVec[i*SizeRatio + SizeRatio-1] = i; 16805 16806 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 16807 DAG.getUNDEF(WideVecVT), 16808 &ShuffleVec[0]); 16809 16810 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 16811 16812 // Build the arithmetic shift. 16813 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() - 16814 MemVT.getVectorElementType().getSizeInBits(); 16815 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff, 16816 DAG.getConstant(Amt, RegVT)); 16817 16818 return DCI.CombineTo(N, Shuff, TF, true); 16819 } 16820 16821 // Redistribute the loaded elements into the different locations. 16822 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 16823 for (unsigned i = 0; i != NumElems; ++i) 16824 ShuffleVec[i*SizeRatio] = i; 16825 16826 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 16827 DAG.getUNDEF(WideVecVT), 16828 &ShuffleVec[0]); 16829 16830 // Bitcast to the requested type. 16831 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 16832 // Replace the original load with the new sequence 16833 // and return the new chain. 16834 return DCI.CombineTo(N, Shuff, TF, true); 16835 } 16836 16837 return SDValue(); 16838} 16839 16840/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 16841static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 16842 const X86Subtarget *Subtarget) { 16843 StoreSDNode *St = cast<StoreSDNode>(N); 16844 EVT VT = St->getValue().getValueType(); 16845 EVT StVT = St->getMemoryVT(); 16846 DebugLoc dl = St->getDebugLoc(); 16847 SDValue StoredVal = St->getOperand(1); 16848 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16849 16850 // If we are saving a concatenation of two XMM registers, perform two stores. 16851 // On Sandy Bridge, 256-bit memory operations are executed by two 16852 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit 16853 // memory operation. 16854 unsigned Alignment = St->getAlignment(); 16855 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8; 16856 if (VT.is256BitVector() && !Subtarget->hasInt256() && 16857 StVT == VT && !IsAligned) { 16858 unsigned NumElems = VT.getVectorNumElements(); 16859 if (NumElems < 2) 16860 return SDValue(); 16861 16862 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl); 16863 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl); 16864 16865 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 16866 SDValue Ptr0 = St->getBasePtr(); 16867 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 16868 16869 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 16870 St->getPointerInfo(), St->isVolatile(), 16871 St->isNonTemporal(), Alignment); 16872 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 16873 St->getPointerInfo(), St->isVolatile(), 16874 St->isNonTemporal(), 16875 std::min(16U, Alignment)); 16876 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 16877 } 16878 16879 // Optimize trunc store (of multiple scalars) to shuffle and store. 16880 // First, pack all of the elements in one place. Next, store to memory 16881 // in fewer chunks. 16882 if (St->isTruncatingStore() && VT.isVector()) { 16883 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16884 unsigned NumElems = VT.getVectorNumElements(); 16885 assert(StVT != VT && "Cannot truncate to the same type"); 16886 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 16887 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 16888 16889 // From, To sizes and ElemCount must be pow of two 16890 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 16891 // We are going to use the original vector elt for storing. 16892 // Accumulated smaller vector elements must be a multiple of the store size. 16893 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 16894 16895 unsigned SizeRatio = FromSz / ToSz; 16896 16897 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 16898 16899 // Create a type on which we perform the shuffle 16900 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 16901 StVT.getScalarType(), NumElems*SizeRatio); 16902 16903 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 16904 16905 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 16906 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 16907 for (unsigned i = 0; i != NumElems; ++i) 16908 ShuffleVec[i] = i * SizeRatio; 16909 16910 // Can't shuffle using an illegal type. 16911 if (!TLI.isTypeLegal(WideVecVT)) 16912 return SDValue(); 16913 16914 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 16915 DAG.getUNDEF(WideVecVT), 16916 &ShuffleVec[0]); 16917 // At this point all of the data is stored at the bottom of the 16918 // register. We now need to save it to mem. 16919 16920 // Find the largest store unit 16921 MVT StoreType = MVT::i8; 16922 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 16923 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 16924 MVT Tp = (MVT::SimpleValueType)tp; 16925 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz) 16926 StoreType = Tp; 16927 } 16928 16929 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 16930 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 && 16931 (64 <= NumElems * ToSz)) 16932 StoreType = MVT::f64; 16933 16934 // Bitcast the original vector into a vector of store-size units 16935 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 16936 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits()); 16937 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 16938 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 16939 SmallVector<SDValue, 8> Chains; 16940 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 16941 TLI.getPointerTy()); 16942 SDValue Ptr = St->getBasePtr(); 16943 16944 // Perform one or more big stores into memory. 16945 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) { 16946 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 16947 StoreType, ShuffWide, 16948 DAG.getIntPtrConstant(i)); 16949 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 16950 St->getPointerInfo(), St->isVolatile(), 16951 St->isNonTemporal(), St->getAlignment()); 16952 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 16953 Chains.push_back(Ch); 16954 } 16955 16956 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 16957 Chains.size()); 16958 } 16959 16960 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 16961 // the FP state in cases where an emms may be missing. 16962 // A preferable solution to the general problem is to figure out the right 16963 // places to insert EMMS. This qualifies as a quick hack. 16964 16965 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 16966 if (VT.getSizeInBits() != 64) 16967 return SDValue(); 16968 16969 const Function *F = DAG.getMachineFunction().getFunction(); 16970 bool NoImplicitFloatOps = F->getAttributes(). 16971 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 16972 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 16973 && Subtarget->hasSSE2(); 16974 if ((VT.isVector() || 16975 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 16976 isa<LoadSDNode>(St->getValue()) && 16977 !cast<LoadSDNode>(St->getValue())->isVolatile() && 16978 St->getChain().hasOneUse() && !St->isVolatile()) { 16979 SDNode* LdVal = St->getValue().getNode(); 16980 LoadSDNode *Ld = 0; 16981 int TokenFactorIndex = -1; 16982 SmallVector<SDValue, 8> Ops; 16983 SDNode* ChainVal = St->getChain().getNode(); 16984 // Must be a store of a load. We currently handle two cases: the load 16985 // is a direct child, and it's under an intervening TokenFactor. It is 16986 // possible to dig deeper under nested TokenFactors. 16987 if (ChainVal == LdVal) 16988 Ld = cast<LoadSDNode>(St->getChain()); 16989 else if (St->getValue().hasOneUse() && 16990 ChainVal->getOpcode() == ISD::TokenFactor) { 16991 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 16992 if (ChainVal->getOperand(i).getNode() == LdVal) { 16993 TokenFactorIndex = i; 16994 Ld = cast<LoadSDNode>(St->getValue()); 16995 } else 16996 Ops.push_back(ChainVal->getOperand(i)); 16997 } 16998 } 16999 17000 if (!Ld || !ISD::isNormalLoad(Ld)) 17001 return SDValue(); 17002 17003 // If this is not the MMX case, i.e. we are just turning i64 load/store 17004 // into f64 load/store, avoid the transformation if there are multiple 17005 // uses of the loaded value. 17006 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 17007 return SDValue(); 17008 17009 DebugLoc LdDL = Ld->getDebugLoc(); 17010 DebugLoc StDL = N->getDebugLoc(); 17011 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 17012 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 17013 // pair instead. 17014 if (Subtarget->is64Bit() || F64IsLegal) { 17015 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 17016 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 17017 Ld->getPointerInfo(), Ld->isVolatile(), 17018 Ld->isNonTemporal(), Ld->isInvariant(), 17019 Ld->getAlignment()); 17020 SDValue NewChain = NewLd.getValue(1); 17021 if (TokenFactorIndex != -1) { 17022 Ops.push_back(NewChain); 17023 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 17024 Ops.size()); 17025 } 17026 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 17027 St->getPointerInfo(), 17028 St->isVolatile(), St->isNonTemporal(), 17029 St->getAlignment()); 17030 } 17031 17032 // Otherwise, lower to two pairs of 32-bit loads / stores. 17033 SDValue LoAddr = Ld->getBasePtr(); 17034 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 17035 DAG.getConstant(4, MVT::i32)); 17036 17037 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 17038 Ld->getPointerInfo(), 17039 Ld->isVolatile(), Ld->isNonTemporal(), 17040 Ld->isInvariant(), Ld->getAlignment()); 17041 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 17042 Ld->getPointerInfo().getWithOffset(4), 17043 Ld->isVolatile(), Ld->isNonTemporal(), 17044 Ld->isInvariant(), 17045 MinAlign(Ld->getAlignment(), 4)); 17046 17047 SDValue NewChain = LoLd.getValue(1); 17048 if (TokenFactorIndex != -1) { 17049 Ops.push_back(LoLd); 17050 Ops.push_back(HiLd); 17051 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 17052 Ops.size()); 17053 } 17054 17055 LoAddr = St->getBasePtr(); 17056 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 17057 DAG.getConstant(4, MVT::i32)); 17058 17059 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 17060 St->getPointerInfo(), 17061 St->isVolatile(), St->isNonTemporal(), 17062 St->getAlignment()); 17063 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 17064 St->getPointerInfo().getWithOffset(4), 17065 St->isVolatile(), 17066 St->isNonTemporal(), 17067 MinAlign(St->getAlignment(), 4)); 17068 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 17069 } 17070 return SDValue(); 17071} 17072 17073/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 17074/// and return the operands for the horizontal operation in LHS and RHS. A 17075/// horizontal operation performs the binary operation on successive elements 17076/// of its first operand, then on successive elements of its second operand, 17077/// returning the resulting values in a vector. For example, if 17078/// A = < float a0, float a1, float a2, float a3 > 17079/// and 17080/// B = < float b0, float b1, float b2, float b3 > 17081/// then the result of doing a horizontal operation on A and B is 17082/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 17083/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 17084/// A horizontal-op B, for some already available A and B, and if so then LHS is 17085/// set to A, RHS to B, and the routine returns 'true'. 17086/// Note that the binary operation should have the property that if one of the 17087/// operands is UNDEF then the result is UNDEF. 17088static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 17089 // Look for the following pattern: if 17090 // A = < float a0, float a1, float a2, float a3 > 17091 // B = < float b0, float b1, float b2, float b3 > 17092 // and 17093 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 17094 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 17095 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 17096 // which is A horizontal-op B. 17097 17098 // At least one of the operands should be a vector shuffle. 17099 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 17100 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 17101 return false; 17102 17103 EVT VT = LHS.getValueType(); 17104 17105 assert((VT.is128BitVector() || VT.is256BitVector()) && 17106 "Unsupported vector type for horizontal add/sub"); 17107 17108 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 17109 // operate independently on 128-bit lanes. 17110 unsigned NumElts = VT.getVectorNumElements(); 17111 unsigned NumLanes = VT.getSizeInBits()/128; 17112 unsigned NumLaneElts = NumElts / NumLanes; 17113 assert((NumLaneElts % 2 == 0) && 17114 "Vector type should have an even number of elements in each lane"); 17115 unsigned HalfLaneElts = NumLaneElts/2; 17116 17117 // View LHS in the form 17118 // LHS = VECTOR_SHUFFLE A, B, LMask 17119 // If LHS is not a shuffle then pretend it is the shuffle 17120 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 17121 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 17122 // type VT. 17123 SDValue A, B; 17124 SmallVector<int, 16> LMask(NumElts); 17125 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 17126 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 17127 A = LHS.getOperand(0); 17128 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 17129 B = LHS.getOperand(1); 17130 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 17131 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 17132 } else { 17133 if (LHS.getOpcode() != ISD::UNDEF) 17134 A = LHS; 17135 for (unsigned i = 0; i != NumElts; ++i) 17136 LMask[i] = i; 17137 } 17138 17139 // Likewise, view RHS in the form 17140 // RHS = VECTOR_SHUFFLE C, D, RMask 17141 SDValue C, D; 17142 SmallVector<int, 16> RMask(NumElts); 17143 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 17144 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 17145 C = RHS.getOperand(0); 17146 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 17147 D = RHS.getOperand(1); 17148 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 17149 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 17150 } else { 17151 if (RHS.getOpcode() != ISD::UNDEF) 17152 C = RHS; 17153 for (unsigned i = 0; i != NumElts; ++i) 17154 RMask[i] = i; 17155 } 17156 17157 // Check that the shuffles are both shuffling the same vectors. 17158 if (!(A == C && B == D) && !(A == D && B == C)) 17159 return false; 17160 17161 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 17162 if (!A.getNode() && !B.getNode()) 17163 return false; 17164 17165 // If A and B occur in reverse order in RHS, then "swap" them (which means 17166 // rewriting the mask). 17167 if (A != C) 17168 CommuteVectorShuffleMask(RMask, NumElts); 17169 17170 // At this point LHS and RHS are equivalent to 17171 // LHS = VECTOR_SHUFFLE A, B, LMask 17172 // RHS = VECTOR_SHUFFLE A, B, RMask 17173 // Check that the masks correspond to performing a horizontal operation. 17174 for (unsigned i = 0; i != NumElts; ++i) { 17175 int LIdx = LMask[i], RIdx = RMask[i]; 17176 17177 // Ignore any UNDEF components. 17178 if (LIdx < 0 || RIdx < 0 || 17179 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 17180 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 17181 continue; 17182 17183 // Check that successive elements are being operated on. If not, this is 17184 // not a horizontal operation. 17185 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 17186 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 17187 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 17188 if (!(LIdx == Index && RIdx == Index + 1) && 17189 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 17190 return false; 17191 } 17192 17193 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 17194 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 17195 return true; 17196} 17197 17198/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 17199static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 17200 const X86Subtarget *Subtarget) { 17201 EVT VT = N->getValueType(0); 17202 SDValue LHS = N->getOperand(0); 17203 SDValue RHS = N->getOperand(1); 17204 17205 // Try to synthesize horizontal adds from adds of shuffles. 17206 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 17207 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 17208 isHorizontalBinOp(LHS, RHS, true)) 17209 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 17210 return SDValue(); 17211} 17212 17213/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 17214static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 17215 const X86Subtarget *Subtarget) { 17216 EVT VT = N->getValueType(0); 17217 SDValue LHS = N->getOperand(0); 17218 SDValue RHS = N->getOperand(1); 17219 17220 // Try to synthesize horizontal subs from subs of shuffles. 17221 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 17222 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 17223 isHorizontalBinOp(LHS, RHS, false)) 17224 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 17225 return SDValue(); 17226} 17227 17228/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 17229/// X86ISD::FXOR nodes. 17230static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 17231 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 17232 // F[X]OR(0.0, x) -> x 17233 // F[X]OR(x, 0.0) -> x 17234 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 17235 if (C->getValueAPF().isPosZero()) 17236 return N->getOperand(1); 17237 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 17238 if (C->getValueAPF().isPosZero()) 17239 return N->getOperand(0); 17240 return SDValue(); 17241} 17242 17243/// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and 17244/// X86ISD::FMAX nodes. 17245static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) { 17246 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX); 17247 17248 // Only perform optimizations if UnsafeMath is used. 17249 if (!DAG.getTarget().Options.UnsafeFPMath) 17250 return SDValue(); 17251 17252 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes 17253 // into FMINC and FMAXC, which are Commutative operations. 17254 unsigned NewOp = 0; 17255 switch (N->getOpcode()) { 17256 default: llvm_unreachable("unknown opcode"); 17257 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break; 17258 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break; 17259 } 17260 17261 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0), 17262 N->getOperand(0), N->getOperand(1)); 17263} 17264 17265/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 17266static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 17267 // FAND(0.0, x) -> 0.0 17268 // FAND(x, 0.0) -> 0.0 17269 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 17270 if (C->getValueAPF().isPosZero()) 17271 return N->getOperand(0); 17272 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 17273 if (C->getValueAPF().isPosZero()) 17274 return N->getOperand(1); 17275 return SDValue(); 17276} 17277 17278static SDValue PerformBTCombine(SDNode *N, 17279 SelectionDAG &DAG, 17280 TargetLowering::DAGCombinerInfo &DCI) { 17281 // BT ignores high bits in the bit index operand. 17282 SDValue Op1 = N->getOperand(1); 17283 if (Op1.hasOneUse()) { 17284 unsigned BitWidth = Op1.getValueSizeInBits(); 17285 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 17286 APInt KnownZero, KnownOne; 17287 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 17288 !DCI.isBeforeLegalizeOps()); 17289 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 17290 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 17291 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 17292 DCI.CommitTargetLoweringOpt(TLO); 17293 } 17294 return SDValue(); 17295} 17296 17297static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 17298 SDValue Op = N->getOperand(0); 17299 if (Op.getOpcode() == ISD::BITCAST) 17300 Op = Op.getOperand(0); 17301 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 17302 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 17303 VT.getVectorElementType().getSizeInBits() == 17304 OpVT.getVectorElementType().getSizeInBits()) { 17305 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 17306 } 17307 return SDValue(); 17308} 17309 17310static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG, 17311 const X86Subtarget *Subtarget) { 17312 EVT VT = N->getValueType(0); 17313 if (!VT.isVector()) 17314 return SDValue(); 17315 17316 SDValue N0 = N->getOperand(0); 17317 SDValue N1 = N->getOperand(1); 17318 EVT ExtraVT = cast<VTSDNode>(N1)->getVT(); 17319 DebugLoc dl = N->getDebugLoc(); 17320 17321 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the 17322 // both SSE and AVX2 since there is no sign-extended shift right 17323 // operation on a vector with 64-bit elements. 17324 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> 17325 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) 17326 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND || 17327 N0.getOpcode() == ISD::SIGN_EXTEND)) { 17328 SDValue N00 = N0.getOperand(0); 17329 17330 // EXTLOAD has a better solution on AVX2, 17331 // it may be replaced with X86ISD::VSEXT node. 17332 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256()) 17333 if (!ISD::isNormalLoad(N00.getNode())) 17334 return SDValue(); 17335 17336 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) { 17337 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, 17338 N00, N1); 17339 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp); 17340 } 17341 } 17342 return SDValue(); 17343} 17344 17345static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 17346 TargetLowering::DAGCombinerInfo &DCI, 17347 const X86Subtarget *Subtarget) { 17348 if (!DCI.isBeforeLegalizeOps()) 17349 return SDValue(); 17350 17351 if (!Subtarget->hasFp256()) 17352 return SDValue(); 17353 17354 EVT VT = N->getValueType(0); 17355 if (VT.isVector() && VT.getSizeInBits() == 256) { 17356 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); 17357 if (R.getNode()) 17358 return R; 17359 } 17360 17361 return SDValue(); 17362} 17363 17364static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG, 17365 const X86Subtarget* Subtarget) { 17366 DebugLoc dl = N->getDebugLoc(); 17367 EVT VT = N->getValueType(0); 17368 17369 // Let legalize expand this if it isn't a legal type yet. 17370 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 17371 return SDValue(); 17372 17373 EVT ScalarVT = VT.getScalarType(); 17374 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || 17375 (!Subtarget->hasFMA() && !Subtarget->hasFMA4())) 17376 return SDValue(); 17377 17378 SDValue A = N->getOperand(0); 17379 SDValue B = N->getOperand(1); 17380 SDValue C = N->getOperand(2); 17381 17382 bool NegA = (A.getOpcode() == ISD::FNEG); 17383 bool NegB = (B.getOpcode() == ISD::FNEG); 17384 bool NegC = (C.getOpcode() == ISD::FNEG); 17385 17386 // Negative multiplication when NegA xor NegB 17387 bool NegMul = (NegA != NegB); 17388 if (NegA) 17389 A = A.getOperand(0); 17390 if (NegB) 17391 B = B.getOperand(0); 17392 if (NegC) 17393 C = C.getOperand(0); 17394 17395 unsigned Opcode; 17396 if (!NegMul) 17397 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB; 17398 else 17399 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB; 17400 17401 return DAG.getNode(Opcode, dl, VT, A, B, C); 17402} 17403 17404static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 17405 TargetLowering::DAGCombinerInfo &DCI, 17406 const X86Subtarget *Subtarget) { 17407 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 17408 // (and (i32 x86isd::setcc_carry), 1) 17409 // This eliminates the zext. This transformation is necessary because 17410 // ISD::SETCC is always legalized to i8. 17411 DebugLoc dl = N->getDebugLoc(); 17412 SDValue N0 = N->getOperand(0); 17413 EVT VT = N->getValueType(0); 17414 17415 if (N0.getOpcode() == ISD::AND && 17416 N0.hasOneUse() && 17417 N0.getOperand(0).hasOneUse()) { 17418 SDValue N00 = N0.getOperand(0); 17419 if (N00.getOpcode() == X86ISD::SETCC_CARRY) { 17420 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 17421 if (!C || C->getZExtValue() != 1) 17422 return SDValue(); 17423 return DAG.getNode(ISD::AND, dl, VT, 17424 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 17425 N00.getOperand(0), N00.getOperand(1)), 17426 DAG.getConstant(1, VT)); 17427 } 17428 } 17429 17430 if (VT.is256BitVector()) { 17431 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); 17432 if (R.getNode()) 17433 return R; 17434 } 17435 17436 return SDValue(); 17437} 17438 17439// Optimize x == -y --> x+y == 0 17440// x != -y --> x+y != 0 17441static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) { 17442 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 17443 SDValue LHS = N->getOperand(0); 17444 SDValue RHS = N->getOperand(1); 17445 17446 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) 17447 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0))) 17448 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) { 17449 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 17450 LHS.getValueType(), RHS, LHS.getOperand(1)); 17451 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 17452 addV, DAG.getConstant(0, addV.getValueType()), CC); 17453 } 17454 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) 17455 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0))) 17456 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) { 17457 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 17458 RHS.getValueType(), LHS, RHS.getOperand(1)); 17459 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 17460 addV, DAG.getConstant(0, addV.getValueType()), CC); 17461 } 17462 return SDValue(); 17463} 17464 17465// Helper function of PerformSETCCCombine. It is to materialize "setb reg" 17466// as "sbb reg,reg", since it can be extended without zext and produces 17467// an all-ones bit which is more useful than 0/1 in some cases. 17468static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) { 17469 return DAG.getNode(ISD::AND, DL, MVT::i8, 17470 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 17471 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS), 17472 DAG.getConstant(1, MVT::i8)); 17473} 17474 17475// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 17476static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG, 17477 TargetLowering::DAGCombinerInfo &DCI, 17478 const X86Subtarget *Subtarget) { 17479 DebugLoc DL = N->getDebugLoc(); 17480 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0)); 17481 SDValue EFLAGS = N->getOperand(1); 17482 17483 if (CC == X86::COND_A) { 17484 // Try to convert COND_A into COND_B in an attempt to facilitate 17485 // materializing "setb reg". 17486 // 17487 // Do not flip "e > c", where "c" is a constant, because Cmp instruction 17488 // cannot take an immediate as its first operand. 17489 // 17490 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() && 17491 EFLAGS.getValueType().isInteger() && 17492 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) { 17493 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(), 17494 EFLAGS.getNode()->getVTList(), 17495 EFLAGS.getOperand(1), EFLAGS.getOperand(0)); 17496 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo()); 17497 return MaterializeSETB(DL, NewEFLAGS, DAG); 17498 } 17499 } 17500 17501 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 17502 // a zext and produces an all-ones bit which is more useful than 0/1 in some 17503 // cases. 17504 if (CC == X86::COND_B) 17505 return MaterializeSETB(DL, EFLAGS, DAG); 17506 17507 SDValue Flags; 17508 17509 Flags = checkBoolTestSetCCCombine(EFLAGS, CC); 17510 if (Flags.getNode()) { 17511 SDValue Cond = DAG.getConstant(CC, MVT::i8); 17512 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags); 17513 } 17514 17515 return SDValue(); 17516} 17517 17518// Optimize branch condition evaluation. 17519// 17520static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG, 17521 TargetLowering::DAGCombinerInfo &DCI, 17522 const X86Subtarget *Subtarget) { 17523 DebugLoc DL = N->getDebugLoc(); 17524 SDValue Chain = N->getOperand(0); 17525 SDValue Dest = N->getOperand(1); 17526 SDValue EFLAGS = N->getOperand(3); 17527 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2)); 17528 17529 SDValue Flags; 17530 17531 Flags = checkBoolTestSetCCCombine(EFLAGS, CC); 17532 if (Flags.getNode()) { 17533 SDValue Cond = DAG.getConstant(CC, MVT::i8); 17534 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond, 17535 Flags); 17536 } 17537 17538 return SDValue(); 17539} 17540 17541static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 17542 const X86TargetLowering *XTLI) { 17543 SDValue Op0 = N->getOperand(0); 17544 EVT InVT = Op0->getValueType(0); 17545 17546 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 17547 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 17548 DebugLoc dl = N->getDebugLoc(); 17549 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 17550 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); 17551 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 17552 } 17553 17554 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 17555 // a 32-bit target where SSE doesn't support i64->FP operations. 17556 if (Op0.getOpcode() == ISD::LOAD) { 17557 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 17558 EVT VT = Ld->getValueType(0); 17559 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 17560 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 17561 !XTLI->getSubtarget()->is64Bit() && 17562 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 17563 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 17564 Ld->getChain(), Op0, DAG); 17565 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 17566 return FILDChain; 17567 } 17568 } 17569 return SDValue(); 17570} 17571 17572// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 17573static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 17574 X86TargetLowering::DAGCombinerInfo &DCI) { 17575 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 17576 // the result is either zero or one (depending on the input carry bit). 17577 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 17578 if (X86::isZeroNode(N->getOperand(0)) && 17579 X86::isZeroNode(N->getOperand(1)) && 17580 // We don't have a good way to replace an EFLAGS use, so only do this when 17581 // dead right now. 17582 SDValue(N, 1).use_empty()) { 17583 DebugLoc DL = N->getDebugLoc(); 17584 EVT VT = N->getValueType(0); 17585 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 17586 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 17587 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 17588 DAG.getConstant(X86::COND_B,MVT::i8), 17589 N->getOperand(2)), 17590 DAG.getConstant(1, VT)); 17591 return DCI.CombineTo(N, Res1, CarryOut); 17592 } 17593 17594 return SDValue(); 17595} 17596 17597// fold (add Y, (sete X, 0)) -> adc 0, Y 17598// (add Y, (setne X, 0)) -> sbb -1, Y 17599// (sub (sete X, 0), Y) -> sbb 0, Y 17600// (sub (setne X, 0), Y) -> adc -1, Y 17601static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 17602 DebugLoc DL = N->getDebugLoc(); 17603 17604 // Look through ZExts. 17605 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 17606 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 17607 return SDValue(); 17608 17609 SDValue SetCC = Ext.getOperand(0); 17610 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 17611 return SDValue(); 17612 17613 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 17614 if (CC != X86::COND_E && CC != X86::COND_NE) 17615 return SDValue(); 17616 17617 SDValue Cmp = SetCC.getOperand(1); 17618 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 17619 !X86::isZeroNode(Cmp.getOperand(1)) || 17620 !Cmp.getOperand(0).getValueType().isInteger()) 17621 return SDValue(); 17622 17623 SDValue CmpOp0 = Cmp.getOperand(0); 17624 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 17625 DAG.getConstant(1, CmpOp0.getValueType())); 17626 17627 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 17628 if (CC == X86::COND_NE) 17629 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 17630 DL, OtherVal.getValueType(), OtherVal, 17631 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 17632 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 17633 DL, OtherVal.getValueType(), OtherVal, 17634 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 17635} 17636 17637/// PerformADDCombine - Do target-specific dag combines on integer adds. 17638static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 17639 const X86Subtarget *Subtarget) { 17640 EVT VT = N->getValueType(0); 17641 SDValue Op0 = N->getOperand(0); 17642 SDValue Op1 = N->getOperand(1); 17643 17644 // Try to synthesize horizontal adds from adds of shuffles. 17645 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 17646 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 17647 isHorizontalBinOp(Op0, Op1, true)) 17648 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 17649 17650 return OptimizeConditionalInDecrement(N, DAG); 17651} 17652 17653static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 17654 const X86Subtarget *Subtarget) { 17655 SDValue Op0 = N->getOperand(0); 17656 SDValue Op1 = N->getOperand(1); 17657 17658 // X86 can't encode an immediate LHS of a sub. See if we can push the 17659 // negation into a preceding instruction. 17660 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 17661 // If the RHS of the sub is a XOR with one use and a constant, invert the 17662 // immediate. Then add one to the LHS of the sub so we can turn 17663 // X-Y -> X+~Y+1, saving one register. 17664 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 17665 isa<ConstantSDNode>(Op1.getOperand(1))) { 17666 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 17667 EVT VT = Op0.getValueType(); 17668 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 17669 Op1.getOperand(0), 17670 DAG.getConstant(~XorC, VT)); 17671 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 17672 DAG.getConstant(C->getAPIntValue()+1, VT)); 17673 } 17674 } 17675 17676 // Try to synthesize horizontal adds from adds of shuffles. 17677 EVT VT = N->getValueType(0); 17678 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 17679 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 17680 isHorizontalBinOp(Op0, Op1, true)) 17681 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 17682 17683 return OptimizeConditionalInDecrement(N, DAG); 17684} 17685 17686/// performVZEXTCombine - Performs build vector combines 17687static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG, 17688 TargetLowering::DAGCombinerInfo &DCI, 17689 const X86Subtarget *Subtarget) { 17690 // (vzext (bitcast (vzext (x)) -> (vzext x) 17691 SDValue In = N->getOperand(0); 17692 while (In.getOpcode() == ISD::BITCAST) 17693 In = In.getOperand(0); 17694 17695 if (In.getOpcode() != X86ISD::VZEXT) 17696 return SDValue(); 17697 17698 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0), 17699 In.getOperand(0)); 17700} 17701 17702SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 17703 DAGCombinerInfo &DCI) const { 17704 SelectionDAG &DAG = DCI.DAG; 17705 switch (N->getOpcode()) { 17706 default: break; 17707 case ISD::EXTRACT_VECTOR_ELT: 17708 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 17709 case ISD::VSELECT: 17710 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 17711 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget); 17712 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 17713 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 17714 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 17715 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 17716 case ISD::SHL: 17717 case ISD::SRA: 17718 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 17719 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 17720 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 17721 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 17722 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget); 17723 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 17724 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 17725 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 17726 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 17727 case X86ISD::FXOR: 17728 case X86ISD::FOR: return PerformFORCombine(N, DAG); 17729 case X86ISD::FMIN: 17730 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG); 17731 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 17732 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 17733 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 17734 case ISD::ANY_EXTEND: 17735 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); 17736 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 17737 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget); 17738 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget); 17739 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); 17740 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget); 17741 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget); 17742 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget); 17743 case X86ISD::SHUFP: // Handle all target specific shuffles 17744 case X86ISD::PALIGNR: 17745 case X86ISD::UNPCKH: 17746 case X86ISD::UNPCKL: 17747 case X86ISD::MOVHLPS: 17748 case X86ISD::MOVLHPS: 17749 case X86ISD::PSHUFD: 17750 case X86ISD::PSHUFHW: 17751 case X86ISD::PSHUFLW: 17752 case X86ISD::MOVSS: 17753 case X86ISD::MOVSD: 17754 case X86ISD::VPERMILP: 17755 case X86ISD::VPERM2X128: 17756 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 17757 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget); 17758 } 17759 17760 return SDValue(); 17761} 17762 17763/// isTypeDesirableForOp - Return true if the target has native support for 17764/// the specified value type and it is 'desirable' to use the type for the 17765/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 17766/// instruction encodings are longer and some i16 instructions are slow. 17767bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 17768 if (!isTypeLegal(VT)) 17769 return false; 17770 if (VT != MVT::i16) 17771 return true; 17772 17773 switch (Opc) { 17774 default: 17775 return true; 17776 case ISD::LOAD: 17777 case ISD::SIGN_EXTEND: 17778 case ISD::ZERO_EXTEND: 17779 case ISD::ANY_EXTEND: 17780 case ISD::SHL: 17781 case ISD::SRL: 17782 case ISD::SUB: 17783 case ISD::ADD: 17784 case ISD::MUL: 17785 case ISD::AND: 17786 case ISD::OR: 17787 case ISD::XOR: 17788 return false; 17789 } 17790} 17791 17792/// IsDesirableToPromoteOp - This method query the target whether it is 17793/// beneficial for dag combiner to promote the specified node. If true, it 17794/// should return the desired promotion type by reference. 17795bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 17796 EVT VT = Op.getValueType(); 17797 if (VT != MVT::i16) 17798 return false; 17799 17800 bool Promote = false; 17801 bool Commute = false; 17802 switch (Op.getOpcode()) { 17803 default: break; 17804 case ISD::LOAD: { 17805 LoadSDNode *LD = cast<LoadSDNode>(Op); 17806 // If the non-extending load has a single use and it's not live out, then it 17807 // might be folded. 17808 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 17809 Op.hasOneUse()*/) { 17810 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 17811 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 17812 // The only case where we'd want to promote LOAD (rather then it being 17813 // promoted as an operand is when it's only use is liveout. 17814 if (UI->getOpcode() != ISD::CopyToReg) 17815 return false; 17816 } 17817 } 17818 Promote = true; 17819 break; 17820 } 17821 case ISD::SIGN_EXTEND: 17822 case ISD::ZERO_EXTEND: 17823 case ISD::ANY_EXTEND: 17824 Promote = true; 17825 break; 17826 case ISD::SHL: 17827 case ISD::SRL: { 17828 SDValue N0 = Op.getOperand(0); 17829 // Look out for (store (shl (load), x)). 17830 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 17831 return false; 17832 Promote = true; 17833 break; 17834 } 17835 case ISD::ADD: 17836 case ISD::MUL: 17837 case ISD::AND: 17838 case ISD::OR: 17839 case ISD::XOR: 17840 Commute = true; 17841 // fallthrough 17842 case ISD::SUB: { 17843 SDValue N0 = Op.getOperand(0); 17844 SDValue N1 = Op.getOperand(1); 17845 if (!Commute && MayFoldLoad(N1)) 17846 return false; 17847 // Avoid disabling potential load folding opportunities. 17848 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 17849 return false; 17850 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 17851 return false; 17852 Promote = true; 17853 } 17854 } 17855 17856 PVT = MVT::i32; 17857 return Promote; 17858} 17859 17860//===----------------------------------------------------------------------===// 17861// X86 Inline Assembly Support 17862//===----------------------------------------------------------------------===// 17863 17864namespace { 17865 // Helper to match a string separated by whitespace. 17866 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 17867 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 17868 17869 for (unsigned i = 0, e = args.size(); i != e; ++i) { 17870 StringRef piece(*args[i]); 17871 if (!s.startswith(piece)) // Check if the piece matches. 17872 return false; 17873 17874 s = s.substr(piece.size()); 17875 StringRef::size_type pos = s.find_first_not_of(" \t"); 17876 if (pos == 0) // We matched a prefix. 17877 return false; 17878 17879 s = s.substr(pos); 17880 } 17881 17882 return s.empty(); 17883 } 17884 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 17885} 17886 17887bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 17888 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 17889 17890 std::string AsmStr = IA->getAsmString(); 17891 17892 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 17893 if (!Ty || Ty->getBitWidth() % 16 != 0) 17894 return false; 17895 17896 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 17897 SmallVector<StringRef, 4> AsmPieces; 17898 SplitString(AsmStr, AsmPieces, ";\n"); 17899 17900 switch (AsmPieces.size()) { 17901 default: return false; 17902 case 1: 17903 // FIXME: this should verify that we are targeting a 486 or better. If not, 17904 // we will turn this bswap into something that will be lowered to logical 17905 // ops instead of emitting the bswap asm. For now, we don't support 486 or 17906 // lower so don't worry about this. 17907 // bswap $0 17908 if (matchAsm(AsmPieces[0], "bswap", "$0") || 17909 matchAsm(AsmPieces[0], "bswapl", "$0") || 17910 matchAsm(AsmPieces[0], "bswapq", "$0") || 17911 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 17912 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 17913 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 17914 // No need to check constraints, nothing other than the equivalent of 17915 // "=r,0" would be valid here. 17916 return IntrinsicLowering::LowerToByteSwap(CI); 17917 } 17918 17919 // rorw $$8, ${0:w} --> llvm.bswap.i16 17920 if (CI->getType()->isIntegerTy(16) && 17921 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 17922 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 17923 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 17924 AsmPieces.clear(); 17925 const std::string &ConstraintsStr = IA->getConstraintString(); 17926 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 17927 array_pod_sort(AsmPieces.begin(), AsmPieces.end()); 17928 if (AsmPieces.size() == 4 && 17929 AsmPieces[0] == "~{cc}" && 17930 AsmPieces[1] == "~{dirflag}" && 17931 AsmPieces[2] == "~{flags}" && 17932 AsmPieces[3] == "~{fpsr}") 17933 return IntrinsicLowering::LowerToByteSwap(CI); 17934 } 17935 break; 17936 case 3: 17937 if (CI->getType()->isIntegerTy(32) && 17938 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 17939 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 17940 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 17941 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 17942 AsmPieces.clear(); 17943 const std::string &ConstraintsStr = IA->getConstraintString(); 17944 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 17945 array_pod_sort(AsmPieces.begin(), AsmPieces.end()); 17946 if (AsmPieces.size() == 4 && 17947 AsmPieces[0] == "~{cc}" && 17948 AsmPieces[1] == "~{dirflag}" && 17949 AsmPieces[2] == "~{flags}" && 17950 AsmPieces[3] == "~{fpsr}") 17951 return IntrinsicLowering::LowerToByteSwap(CI); 17952 } 17953 17954 if (CI->getType()->isIntegerTy(64)) { 17955 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 17956 if (Constraints.size() >= 2 && 17957 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 17958 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 17959 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 17960 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 17961 matchAsm(AsmPieces[1], "bswap", "%edx") && 17962 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 17963 return IntrinsicLowering::LowerToByteSwap(CI); 17964 } 17965 } 17966 break; 17967 } 17968 return false; 17969} 17970 17971/// getConstraintType - Given a constraint letter, return the type of 17972/// constraint it is for this target. 17973X86TargetLowering::ConstraintType 17974X86TargetLowering::getConstraintType(const std::string &Constraint) const { 17975 if (Constraint.size() == 1) { 17976 switch (Constraint[0]) { 17977 case 'R': 17978 case 'q': 17979 case 'Q': 17980 case 'f': 17981 case 't': 17982 case 'u': 17983 case 'y': 17984 case 'x': 17985 case 'Y': 17986 case 'l': 17987 return C_RegisterClass; 17988 case 'a': 17989 case 'b': 17990 case 'c': 17991 case 'd': 17992 case 'S': 17993 case 'D': 17994 case 'A': 17995 return C_Register; 17996 case 'I': 17997 case 'J': 17998 case 'K': 17999 case 'L': 18000 case 'M': 18001 case 'N': 18002 case 'G': 18003 case 'C': 18004 case 'e': 18005 case 'Z': 18006 return C_Other; 18007 default: 18008 break; 18009 } 18010 } 18011 return TargetLowering::getConstraintType(Constraint); 18012} 18013 18014/// Examine constraint type and operand type and determine a weight value. 18015/// This object must already have been set up with the operand type 18016/// and the current alternative constraint selected. 18017TargetLowering::ConstraintWeight 18018 X86TargetLowering::getSingleConstraintMatchWeight( 18019 AsmOperandInfo &info, const char *constraint) const { 18020 ConstraintWeight weight = CW_Invalid; 18021 Value *CallOperandVal = info.CallOperandVal; 18022 // If we don't have a value, we can't do a match, 18023 // but allow it at the lowest weight. 18024 if (CallOperandVal == NULL) 18025 return CW_Default; 18026 Type *type = CallOperandVal->getType(); 18027 // Look at the constraint type. 18028 switch (*constraint) { 18029 default: 18030 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 18031 case 'R': 18032 case 'q': 18033 case 'Q': 18034 case 'a': 18035 case 'b': 18036 case 'c': 18037 case 'd': 18038 case 'S': 18039 case 'D': 18040 case 'A': 18041 if (CallOperandVal->getType()->isIntegerTy()) 18042 weight = CW_SpecificReg; 18043 break; 18044 case 'f': 18045 case 't': 18046 case 'u': 18047 if (type->isFloatingPointTy()) 18048 weight = CW_SpecificReg; 18049 break; 18050 case 'y': 18051 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 18052 weight = CW_SpecificReg; 18053 break; 18054 case 'x': 18055 case 'Y': 18056 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 18057 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256())) 18058 weight = CW_Register; 18059 break; 18060 case 'I': 18061 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 18062 if (C->getZExtValue() <= 31) 18063 weight = CW_Constant; 18064 } 18065 break; 18066 case 'J': 18067 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 18068 if (C->getZExtValue() <= 63) 18069 weight = CW_Constant; 18070 } 18071 break; 18072 case 'K': 18073 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 18074 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 18075 weight = CW_Constant; 18076 } 18077 break; 18078 case 'L': 18079 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 18080 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 18081 weight = CW_Constant; 18082 } 18083 break; 18084 case 'M': 18085 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 18086 if (C->getZExtValue() <= 3) 18087 weight = CW_Constant; 18088 } 18089 break; 18090 case 'N': 18091 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 18092 if (C->getZExtValue() <= 0xff) 18093 weight = CW_Constant; 18094 } 18095 break; 18096 case 'G': 18097 case 'C': 18098 if (dyn_cast<ConstantFP>(CallOperandVal)) { 18099 weight = CW_Constant; 18100 } 18101 break; 18102 case 'e': 18103 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 18104 if ((C->getSExtValue() >= -0x80000000LL) && 18105 (C->getSExtValue() <= 0x7fffffffLL)) 18106 weight = CW_Constant; 18107 } 18108 break; 18109 case 'Z': 18110 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 18111 if (C->getZExtValue() <= 0xffffffff) 18112 weight = CW_Constant; 18113 } 18114 break; 18115 } 18116 return weight; 18117} 18118 18119/// LowerXConstraint - try to replace an X constraint, which matches anything, 18120/// with another that has more specific requirements based on the type of the 18121/// corresponding operand. 18122const char *X86TargetLowering:: 18123LowerXConstraint(EVT ConstraintVT) const { 18124 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 18125 // 'f' like normal targets. 18126 if (ConstraintVT.isFloatingPoint()) { 18127 if (Subtarget->hasSSE2()) 18128 return "Y"; 18129 if (Subtarget->hasSSE1()) 18130 return "x"; 18131 } 18132 18133 return TargetLowering::LowerXConstraint(ConstraintVT); 18134} 18135 18136/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 18137/// vector. If it is invalid, don't add anything to Ops. 18138void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 18139 std::string &Constraint, 18140 std::vector<SDValue>&Ops, 18141 SelectionDAG &DAG) const { 18142 SDValue Result(0, 0); 18143 18144 // Only support length 1 constraints for now. 18145 if (Constraint.length() > 1) return; 18146 18147 char ConstraintLetter = Constraint[0]; 18148 switch (ConstraintLetter) { 18149 default: break; 18150 case 'I': 18151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 18152 if (C->getZExtValue() <= 31) { 18153 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 18154 break; 18155 } 18156 } 18157 return; 18158 case 'J': 18159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 18160 if (C->getZExtValue() <= 63) { 18161 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 18162 break; 18163 } 18164 } 18165 return; 18166 case 'K': 18167 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 18168 if (isInt<8>(C->getSExtValue())) { 18169 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 18170 break; 18171 } 18172 } 18173 return; 18174 case 'N': 18175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 18176 if (C->getZExtValue() <= 255) { 18177 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 18178 break; 18179 } 18180 } 18181 return; 18182 case 'e': { 18183 // 32-bit signed value 18184 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 18185 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 18186 C->getSExtValue())) { 18187 // Widen to 64 bits here to get it sign extended. 18188 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 18189 break; 18190 } 18191 // FIXME gcc accepts some relocatable values here too, but only in certain 18192 // memory models; it's complicated. 18193 } 18194 return; 18195 } 18196 case 'Z': { 18197 // 32-bit unsigned value 18198 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 18199 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 18200 C->getZExtValue())) { 18201 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 18202 break; 18203 } 18204 } 18205 // FIXME gcc accepts some relocatable values here too, but only in certain 18206 // memory models; it's complicated. 18207 return; 18208 } 18209 case 'i': { 18210 // Literal immediates are always ok. 18211 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 18212 // Widen to 64 bits here to get it sign extended. 18213 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 18214 break; 18215 } 18216 18217 // In any sort of PIC mode addresses need to be computed at runtime by 18218 // adding in a register or some sort of table lookup. These can't 18219 // be used as immediates. 18220 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 18221 return; 18222 18223 // If we are in non-pic codegen mode, we allow the address of a global (with 18224 // an optional displacement) to be used with 'i'. 18225 GlobalAddressSDNode *GA = 0; 18226 int64_t Offset = 0; 18227 18228 // Match either (GA), (GA+C), (GA+C1+C2), etc. 18229 while (1) { 18230 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 18231 Offset += GA->getOffset(); 18232 break; 18233 } else if (Op.getOpcode() == ISD::ADD) { 18234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 18235 Offset += C->getZExtValue(); 18236 Op = Op.getOperand(0); 18237 continue; 18238 } 18239 } else if (Op.getOpcode() == ISD::SUB) { 18240 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 18241 Offset += -C->getZExtValue(); 18242 Op = Op.getOperand(0); 18243 continue; 18244 } 18245 } 18246 18247 // Otherwise, this isn't something we can handle, reject it. 18248 return; 18249 } 18250 18251 const GlobalValue *GV = GA->getGlobal(); 18252 // If we require an extra load to get this address, as in PIC mode, we 18253 // can't accept it. 18254 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 18255 getTargetMachine()))) 18256 return; 18257 18258 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 18259 GA->getValueType(0), Offset); 18260 break; 18261 } 18262 } 18263 18264 if (Result.getNode()) { 18265 Ops.push_back(Result); 18266 return; 18267 } 18268 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 18269} 18270 18271std::pair<unsigned, const TargetRegisterClass*> 18272X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 18273 EVT VT) const { 18274 // First, see if this is a constraint that directly corresponds to an LLVM 18275 // register class. 18276 if (Constraint.size() == 1) { 18277 // GCC Constraint Letters 18278 switch (Constraint[0]) { 18279 default: break; 18280 // TODO: Slight differences here in allocation order and leaving 18281 // RIP in the class. Do they matter any more here than they do 18282 // in the normal allocation? 18283 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 18284 if (Subtarget->is64Bit()) { 18285 if (VT == MVT::i32 || VT == MVT::f32) 18286 return std::make_pair(0U, &X86::GR32RegClass); 18287 if (VT == MVT::i16) 18288 return std::make_pair(0U, &X86::GR16RegClass); 18289 if (VT == MVT::i8 || VT == MVT::i1) 18290 return std::make_pair(0U, &X86::GR8RegClass); 18291 if (VT == MVT::i64 || VT == MVT::f64) 18292 return std::make_pair(0U, &X86::GR64RegClass); 18293 break; 18294 } 18295 // 32-bit fallthrough 18296 case 'Q': // Q_REGS 18297 if (VT == MVT::i32 || VT == MVT::f32) 18298 return std::make_pair(0U, &X86::GR32_ABCDRegClass); 18299 if (VT == MVT::i16) 18300 return std::make_pair(0U, &X86::GR16_ABCDRegClass); 18301 if (VT == MVT::i8 || VT == MVT::i1) 18302 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass); 18303 if (VT == MVT::i64) 18304 return std::make_pair(0U, &X86::GR64_ABCDRegClass); 18305 break; 18306 case 'r': // GENERAL_REGS 18307 case 'l': // INDEX_REGS 18308 if (VT == MVT::i8 || VT == MVT::i1) 18309 return std::make_pair(0U, &X86::GR8RegClass); 18310 if (VT == MVT::i16) 18311 return std::make_pair(0U, &X86::GR16RegClass); 18312 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 18313 return std::make_pair(0U, &X86::GR32RegClass); 18314 return std::make_pair(0U, &X86::GR64RegClass); 18315 case 'R': // LEGACY_REGS 18316 if (VT == MVT::i8 || VT == MVT::i1) 18317 return std::make_pair(0U, &X86::GR8_NOREXRegClass); 18318 if (VT == MVT::i16) 18319 return std::make_pair(0U, &X86::GR16_NOREXRegClass); 18320 if (VT == MVT::i32 || !Subtarget->is64Bit()) 18321 return std::make_pair(0U, &X86::GR32_NOREXRegClass); 18322 return std::make_pair(0U, &X86::GR64_NOREXRegClass); 18323 case 'f': // FP Stack registers. 18324 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 18325 // value to the correct fpstack register class. 18326 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 18327 return std::make_pair(0U, &X86::RFP32RegClass); 18328 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 18329 return std::make_pair(0U, &X86::RFP64RegClass); 18330 return std::make_pair(0U, &X86::RFP80RegClass); 18331 case 'y': // MMX_REGS if MMX allowed. 18332 if (!Subtarget->hasMMX()) break; 18333 return std::make_pair(0U, &X86::VR64RegClass); 18334 case 'Y': // SSE_REGS if SSE2 allowed 18335 if (!Subtarget->hasSSE2()) break; 18336 // FALL THROUGH. 18337 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 18338 if (!Subtarget->hasSSE1()) break; 18339 18340 switch (VT.getSimpleVT().SimpleTy) { 18341 default: break; 18342 // Scalar SSE types. 18343 case MVT::f32: 18344 case MVT::i32: 18345 return std::make_pair(0U, &X86::FR32RegClass); 18346 case MVT::f64: 18347 case MVT::i64: 18348 return std::make_pair(0U, &X86::FR64RegClass); 18349 // Vector types. 18350 case MVT::v16i8: 18351 case MVT::v8i16: 18352 case MVT::v4i32: 18353 case MVT::v2i64: 18354 case MVT::v4f32: 18355 case MVT::v2f64: 18356 return std::make_pair(0U, &X86::VR128RegClass); 18357 // AVX types. 18358 case MVT::v32i8: 18359 case MVT::v16i16: 18360 case MVT::v8i32: 18361 case MVT::v4i64: 18362 case MVT::v8f32: 18363 case MVT::v4f64: 18364 return std::make_pair(0U, &X86::VR256RegClass); 18365 } 18366 break; 18367 } 18368 } 18369 18370 // Use the default implementation in TargetLowering to convert the register 18371 // constraint into a member of a register class. 18372 std::pair<unsigned, const TargetRegisterClass*> Res; 18373 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 18374 18375 // Not found as a standard register? 18376 if (Res.second == 0) { 18377 // Map st(0) -> st(7) -> ST0 18378 if (Constraint.size() == 7 && Constraint[0] == '{' && 18379 tolower(Constraint[1]) == 's' && 18380 tolower(Constraint[2]) == 't' && 18381 Constraint[3] == '(' && 18382 (Constraint[4] >= '0' && Constraint[4] <= '7') && 18383 Constraint[5] == ')' && 18384 Constraint[6] == '}') { 18385 18386 Res.first = X86::ST0+Constraint[4]-'0'; 18387 Res.second = &X86::RFP80RegClass; 18388 return Res; 18389 } 18390 18391 // GCC allows "st(0)" to be called just plain "st". 18392 if (StringRef("{st}").equals_lower(Constraint)) { 18393 Res.first = X86::ST0; 18394 Res.second = &X86::RFP80RegClass; 18395 return Res; 18396 } 18397 18398 // flags -> EFLAGS 18399 if (StringRef("{flags}").equals_lower(Constraint)) { 18400 Res.first = X86::EFLAGS; 18401 Res.second = &X86::CCRRegClass; 18402 return Res; 18403 } 18404 18405 // 'A' means EAX + EDX. 18406 if (Constraint == "A") { 18407 Res.first = X86::EAX; 18408 Res.second = &X86::GR32_ADRegClass; 18409 return Res; 18410 } 18411 return Res; 18412 } 18413 18414 // Otherwise, check to see if this is a register class of the wrong value 18415 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 18416 // turn into {ax},{dx}. 18417 if (Res.second->hasType(VT)) 18418 return Res; // Correct type already, nothing to do. 18419 18420 // All of the single-register GCC register classes map their values onto 18421 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 18422 // really want an 8-bit or 32-bit register, map to the appropriate register 18423 // class and return the appropriate register. 18424 if (Res.second == &X86::GR16RegClass) { 18425 if (VT == MVT::i8 || VT == MVT::i1) { 18426 unsigned DestReg = 0; 18427 switch (Res.first) { 18428 default: break; 18429 case X86::AX: DestReg = X86::AL; break; 18430 case X86::DX: DestReg = X86::DL; break; 18431 case X86::CX: DestReg = X86::CL; break; 18432 case X86::BX: DestReg = X86::BL; break; 18433 } 18434 if (DestReg) { 18435 Res.first = DestReg; 18436 Res.second = &X86::GR8RegClass; 18437 } 18438 } else if (VT == MVT::i32 || VT == MVT::f32) { 18439 unsigned DestReg = 0; 18440 switch (Res.first) { 18441 default: break; 18442 case X86::AX: DestReg = X86::EAX; break; 18443 case X86::DX: DestReg = X86::EDX; break; 18444 case X86::CX: DestReg = X86::ECX; break; 18445 case X86::BX: DestReg = X86::EBX; break; 18446 case X86::SI: DestReg = X86::ESI; break; 18447 case X86::DI: DestReg = X86::EDI; break; 18448 case X86::BP: DestReg = X86::EBP; break; 18449 case X86::SP: DestReg = X86::ESP; break; 18450 } 18451 if (DestReg) { 18452 Res.first = DestReg; 18453 Res.second = &X86::GR32RegClass; 18454 } 18455 } else if (VT == MVT::i64 || VT == MVT::f64) { 18456 unsigned DestReg = 0; 18457 switch (Res.first) { 18458 default: break; 18459 case X86::AX: DestReg = X86::RAX; break; 18460 case X86::DX: DestReg = X86::RDX; break; 18461 case X86::CX: DestReg = X86::RCX; break; 18462 case X86::BX: DestReg = X86::RBX; break; 18463 case X86::SI: DestReg = X86::RSI; break; 18464 case X86::DI: DestReg = X86::RDI; break; 18465 case X86::BP: DestReg = X86::RBP; break; 18466 case X86::SP: DestReg = X86::RSP; break; 18467 } 18468 if (DestReg) { 18469 Res.first = DestReg; 18470 Res.second = &X86::GR64RegClass; 18471 } 18472 } 18473 } else if (Res.second == &X86::FR32RegClass || 18474 Res.second == &X86::FR64RegClass || 18475 Res.second == &X86::VR128RegClass) { 18476 // Handle references to XMM physical registers that got mapped into the 18477 // wrong class. This can happen with constraints like {xmm0} where the 18478 // target independent register mapper will just pick the first match it can 18479 // find, ignoring the required type. 18480 18481 if (VT == MVT::f32 || VT == MVT::i32) 18482 Res.second = &X86::FR32RegClass; 18483 else if (VT == MVT::f64 || VT == MVT::i64) 18484 Res.second = &X86::FR64RegClass; 18485 else if (X86::VR128RegClass.hasType(VT)) 18486 Res.second = &X86::VR128RegClass; 18487 else if (X86::VR256RegClass.hasType(VT)) 18488 Res.second = &X86::VR256RegClass; 18489 } 18490 18491 return Res; 18492} 18493