X86ISelLowering.cpp revision f238f50aaf8a68f16dcc43a017aa32cbb73e938e
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/SmallSet.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/VectorExtras.h" 47#include "llvm/Support/CallSite.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/Dwarf.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/MathExtras.h" 52#include "llvm/Support/raw_ostream.h" 53#include "llvm/Target/TargetOptions.h" 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63static SDValue Insert128BitVector(SDValue Result, 64 SDValue Vec, 65 SDValue Idx, 66 SelectionDAG &DAG, 67 DebugLoc dl); 68 69static SDValue Extract128BitVector(SDValue Vec, 70 SDValue Idx, 71 SelectionDAG &DAG, 72 DebugLoc dl); 73 74/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 75/// sets things up to match to an AVX VEXTRACTF128 instruction or a 76/// simple subregister reference. Idx is an index in the 128 bits we 77/// want. It need not be aligned to a 128-bit bounday. That makes 78/// lowering EXTRACT_VECTOR_ELT operations easier. 79static SDValue Extract128BitVector(SDValue Vec, 80 SDValue Idx, 81 SelectionDAG &DAG, 82 DebugLoc dl) { 83 EVT VT = Vec.getValueType(); 84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 85 EVT ElVT = VT.getVectorElementType(); 86 int Factor = VT.getSizeInBits()/128; 87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 88 VT.getVectorNumElements()/Factor); 89 90 // Extract from UNDEF is UNDEF. 91 if (Vec.getOpcode() == ISD::UNDEF) 92 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 93 94 if (isa<ConstantSDNode>(Idx)) { 95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 96 97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 98 // we can match to VEXTRACTF128. 99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 100 101 // This is the index of the first element of the 128-bit chunk 102 // we want. 103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 104 * ElemsPerChunk); 105 106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 108 VecIdx); 109 110 return Result; 111 } 112 113 return SDValue(); 114} 115 116/// Generate a DAG to put 128-bits into a vector > 128 bits. This 117/// sets things up to match to an AVX VINSERTF128 instruction or a 118/// simple superregister reference. Idx is an index in the 128 bits 119/// we want. It need not be aligned to a 128-bit bounday. That makes 120/// lowering INSERT_VECTOR_ELT operations easier. 121static SDValue Insert128BitVector(SDValue Result, 122 SDValue Vec, 123 SDValue Idx, 124 SelectionDAG &DAG, 125 DebugLoc dl) { 126 if (isa<ConstantSDNode>(Idx)) { 127 EVT VT = Vec.getValueType(); 128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 129 130 EVT ElVT = VT.getVectorElementType(); 131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 132 EVT ResultVT = Result.getValueType(); 133 134 // Insert the relevant 128 bits. 135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 136 137 // This is the index of the first element of the 128-bit chunk 138 // we want. 139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 140 * ElemsPerChunk); 141 142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 144 VecIdx); 145 return Result; 146 } 147 148 return SDValue(); 149} 150 151static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 bool is64Bit = Subtarget->is64Bit(); 154 155 if (Subtarget->isTargetEnvMacho()) { 156 if (is64Bit) 157 return new X8664_MachoTargetObjectFile(); 158 return new TargetLoweringObjectFileMachO(); 159 } 160 161 if (Subtarget->isTargetELF()) 162 return new TargetLoweringObjectFileELF(); 163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 164 return new TargetLoweringObjectFileCOFF(); 165 llvm_unreachable("unknown subtarget type"); 166} 167 168X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 169 : TargetLowering(TM, createTLOF(TM)) { 170 Subtarget = &TM.getSubtarget<X86Subtarget>(); 171 X86ScalarSSEf64 = Subtarget->hasXMMInt(); 172 X86ScalarSSEf32 = Subtarget->hasXMM(); 173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 174 175 RegInfo = TM.getRegisterInfo(); 176 TD = getTargetData(); 177 178 // Set up the TargetLowering object. 179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 180 181 // X86 is weird, it always uses i8 for shift amounts and setcc results. 182 setBooleanContents(ZeroOrOneBooleanContent); 183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 185 186 // For 64-bit since we have so many registers use the ILP scheduler, for 187 // 32-bit code use the register pressure specific scheduling. 188 if (Subtarget->is64Bit()) 189 setSchedulingPreference(Sched::ILP); 190 else 191 setSchedulingPreference(Sched::RegPressure); 192 setStackPointerRegisterToSaveRestore(X86StackPtr); 193 194 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 195 // Setup Windows compiler runtime calls. 196 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 197 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 198 setLibcallName(RTLIB::SREM_I64, "_allrem"); 199 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 200 setLibcallName(RTLIB::MUL_I64, "_allmul"); 201 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 208 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 209 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 210 } 211 212 if (Subtarget->isTargetDarwin()) { 213 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 214 setUseUnderscoreSetJmp(false); 215 setUseUnderscoreLongJmp(false); 216 } else if (Subtarget->isTargetMingw()) { 217 // MS runtime is weird: it exports _setjmp, but longjmp! 218 setUseUnderscoreSetJmp(true); 219 setUseUnderscoreLongJmp(false); 220 } else { 221 setUseUnderscoreSetJmp(true); 222 setUseUnderscoreLongJmp(true); 223 } 224 225 // Set up the register classes. 226 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 227 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 228 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 229 if (Subtarget->is64Bit()) 230 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 231 232 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 233 234 // We don't accept any truncstore of integer registers. 235 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 236 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 237 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 238 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 239 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 240 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 241 242 // SETOEQ and SETUNE require checking two conditions. 243 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 244 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 245 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 248 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 249 250 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 251 // operation. 252 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 253 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 254 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 255 256 if (Subtarget->is64Bit()) { 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 258 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 259 } else if (!UseSoftFloat) { 260 // We have an algorithm for SSE2->double, and we turn this into a 261 // 64-bit FILD followed by conditional FADD for other targets. 262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 263 // We have an algorithm for SSE2, and we turn this into a 64-bit 264 // FILD for other targets. 265 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 266 } 267 268 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 269 // this operation. 270 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 271 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 272 273 if (!UseSoftFloat) { 274 // SSE has no i16 to fp conversion, only i32 275 if (X86ScalarSSEf32) { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 // f32 and f64 cases are Legal, f80 case is not 278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 279 } else { 280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 281 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 282 } 283 } else { 284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 286 } 287 288 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 289 // are Legal, f80 is custom lowered. 290 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 291 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 292 293 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 294 // this operation. 295 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 297 298 if (X86ScalarSSEf32) { 299 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 300 // f32 and f64 cases are Legal, f80 case is not 301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 302 } else { 303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 304 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 305 } 306 307 // Handle FP_TO_UINT by promoting the destination to a larger signed 308 // conversion. 309 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 310 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 311 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 312 313 if (Subtarget->is64Bit()) { 314 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 316 } else if (!UseSoftFloat) { 317 // Since AVX is a superset of SSE3, only check for SSE here. 318 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 319 // Expand FP_TO_UINT into a select. 320 // FIXME: We would like to use a Custom expander here eventually to do 321 // the optimal thing for SSE vs. the default expansion in the legalizer. 322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 323 else 324 // With SSE3 we can use fisttpll to convert to a signed i64; without 325 // SSE, we're stuck with a fistpll. 326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 327 } 328 329 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 330 if (!X86ScalarSSEf64) { 331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 333 if (Subtarget->is64Bit()) { 334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 335 // Without SSE, i64->f64 goes through memory. 336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 337 } 338 } 339 340 // Scalar integer divide and remainder are lowered to use operations that 341 // produce two results, to match the available instructions. This exposes 342 // the two-result form to trivial CSE, which is able to combine x/y and x%y 343 // into a single instruction. 344 // 345 // Scalar integer multiply-high is also lowered to use two-result 346 // operations, to match the available instructions. However, plain multiply 347 // (low) operations are left as Legal, as there are single-result 348 // instructions for this in x86. Using the two-result multiply instructions 349 // when both high and low results are needed must be arranged by dagcombine. 350 for (unsigned i = 0, e = 4; i != e; ++i) { 351 MVT VT = IntVTs[i]; 352 setOperationAction(ISD::MULHS, VT, Expand); 353 setOperationAction(ISD::MULHU, VT, Expand); 354 setOperationAction(ISD::SDIV, VT, Expand); 355 setOperationAction(ISD::UDIV, VT, Expand); 356 setOperationAction(ISD::SREM, VT, Expand); 357 setOperationAction(ISD::UREM, VT, Expand); 358 359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 360 setOperationAction(ISD::ADDC, VT, Custom); 361 setOperationAction(ISD::ADDE, VT, Custom); 362 setOperationAction(ISD::SUBC, VT, Custom); 363 setOperationAction(ISD::SUBE, VT, Custom); 364 } 365 366 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 367 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 368 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 370 if (Subtarget->is64Bit()) 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 376 setOperationAction(ISD::FREM , MVT::f32 , Expand); 377 setOperationAction(ISD::FREM , MVT::f64 , Expand); 378 setOperationAction(ISD::FREM , MVT::f80 , Expand); 379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 380 381 if (Subtarget->hasBMI()) { 382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 383 } else { 384 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 385 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 386 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 387 if (Subtarget->is64Bit()) 388 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 389 } 390 391 if (Subtarget->hasLZCNT()) { 392 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 393 } else { 394 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 395 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 396 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 397 if (Subtarget->is64Bit()) 398 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 399 } 400 401 if (Subtarget->hasPOPCNT()) { 402 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 403 } else { 404 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 405 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 406 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 407 if (Subtarget->is64Bit()) 408 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 409 } 410 411 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 412 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 413 414 // These should be promoted to a larger select which is supported. 415 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 416 // X86 wants to expand cmov itself. 417 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 418 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 419 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 420 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 421 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 422 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 423 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 424 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 425 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 426 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 427 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 428 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 429 if (Subtarget->is64Bit()) { 430 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 431 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 432 } 433 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 434 435 // Darwin ABI issue. 436 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 437 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 438 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 439 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 440 if (Subtarget->is64Bit()) 441 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 442 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 443 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 444 if (Subtarget->is64Bit()) { 445 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 446 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 447 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 448 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 449 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 450 } 451 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 452 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 453 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 454 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 455 if (Subtarget->is64Bit()) { 456 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 457 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 458 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 459 } 460 461 if (Subtarget->hasXMM()) 462 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 463 464 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 465 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 466 467 // On X86 and X86-64, atomic operations are lowered to locked instructions. 468 // Locked instructions, in turn, have implicit fence semantics (all memory 469 // operations are flushed before issuing the locked instruction, and they 470 // are not buffered), so we can fold away the common pattern of 471 // fence-atomic-fence. 472 setShouldFoldAtomicFences(true); 473 474 // Expand certain atomics 475 for (unsigned i = 0, e = 4; i != e; ++i) { 476 MVT VT = IntVTs[i]; 477 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 478 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 479 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 480 } 481 482 if (!Subtarget->is64Bit()) { 483 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 484 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 485 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 486 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 487 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 488 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 489 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 490 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 491 } 492 493 if (Subtarget->hasCmpxchg16b()) { 494 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 495 } 496 497 // FIXME - use subtarget debug flags 498 if (!Subtarget->isTargetDarwin() && 499 !Subtarget->isTargetELF() && 500 !Subtarget->isTargetCygMing()) { 501 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 502 } 503 504 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 505 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 506 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 507 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 508 if (Subtarget->is64Bit()) { 509 setExceptionPointerRegister(X86::RAX); 510 setExceptionSelectorRegister(X86::RDX); 511 } else { 512 setExceptionPointerRegister(X86::EAX); 513 setExceptionSelectorRegister(X86::EDX); 514 } 515 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 516 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 517 518 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 519 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 520 521 setOperationAction(ISD::TRAP, MVT::Other, Legal); 522 523 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 524 setOperationAction(ISD::VASTART , MVT::Other, Custom); 525 setOperationAction(ISD::VAEND , MVT::Other, Expand); 526 if (Subtarget->is64Bit()) { 527 setOperationAction(ISD::VAARG , MVT::Other, Custom); 528 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 529 } else { 530 setOperationAction(ISD::VAARG , MVT::Other, Expand); 531 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 532 } 533 534 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 535 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 536 537 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 538 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 539 MVT::i64 : MVT::i32, Custom); 540 else if (EnableSegmentedStacks) 541 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 542 MVT::i64 : MVT::i32, Custom); 543 else 544 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 545 MVT::i64 : MVT::i32, Expand); 546 547 if (!UseSoftFloat && X86ScalarSSEf64) { 548 // f32 and f64 use SSE. 549 // Set up the FP register classes. 550 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 551 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 552 553 // Use ANDPD to simulate FABS. 554 setOperationAction(ISD::FABS , MVT::f64, Custom); 555 setOperationAction(ISD::FABS , MVT::f32, Custom); 556 557 // Use XORP to simulate FNEG. 558 setOperationAction(ISD::FNEG , MVT::f64, Custom); 559 setOperationAction(ISD::FNEG , MVT::f32, Custom); 560 561 // Use ANDPD and ORPD to simulate FCOPYSIGN. 562 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 563 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 564 565 // Lower this to FGETSIGNx86 plus an AND. 566 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 567 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 568 569 // We don't support sin/cos/fmod 570 setOperationAction(ISD::FSIN , MVT::f64, Expand); 571 setOperationAction(ISD::FCOS , MVT::f64, Expand); 572 setOperationAction(ISD::FSIN , MVT::f32, Expand); 573 setOperationAction(ISD::FCOS , MVT::f32, Expand); 574 575 // Expand FP immediates into loads from the stack, except for the special 576 // cases we handle. 577 addLegalFPImmediate(APFloat(+0.0)); // xorpd 578 addLegalFPImmediate(APFloat(+0.0f)); // xorps 579 } else if (!UseSoftFloat && X86ScalarSSEf32) { 580 // Use SSE for f32, x87 for f64. 581 // Set up the FP register classes. 582 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 583 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 584 585 // Use ANDPS to simulate FABS. 586 setOperationAction(ISD::FABS , MVT::f32, Custom); 587 588 // Use XORP to simulate FNEG. 589 setOperationAction(ISD::FNEG , MVT::f32, Custom); 590 591 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 592 593 // Use ANDPS and ORPS to simulate FCOPYSIGN. 594 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 595 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 596 597 // We don't support sin/cos/fmod 598 setOperationAction(ISD::FSIN , MVT::f32, Expand); 599 setOperationAction(ISD::FCOS , MVT::f32, Expand); 600 601 // Special cases we handle for FP constants. 602 addLegalFPImmediate(APFloat(+0.0f)); // xorps 603 addLegalFPImmediate(APFloat(+0.0)); // FLD0 604 addLegalFPImmediate(APFloat(+1.0)); // FLD1 605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 607 608 if (!UnsafeFPMath) { 609 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 610 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 611 } 612 } else if (!UseSoftFloat) { 613 // f32 and f64 in x87. 614 // Set up the FP register classes. 615 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 616 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 617 618 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 619 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 620 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 621 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 622 623 if (!UnsafeFPMath) { 624 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 625 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 626 } 627 addLegalFPImmediate(APFloat(+0.0)); // FLD0 628 addLegalFPImmediate(APFloat(+1.0)); // FLD1 629 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 630 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 631 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 632 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 633 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 634 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 635 } 636 637 // We don't support FMA. 638 setOperationAction(ISD::FMA, MVT::f64, Expand); 639 setOperationAction(ISD::FMA, MVT::f32, Expand); 640 641 // Long double always uses X87. 642 if (!UseSoftFloat) { 643 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 644 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 645 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 646 { 647 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 648 addLegalFPImmediate(TmpFlt); // FLD0 649 TmpFlt.changeSign(); 650 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 651 652 bool ignored; 653 APFloat TmpFlt2(+1.0); 654 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 655 &ignored); 656 addLegalFPImmediate(TmpFlt2); // FLD1 657 TmpFlt2.changeSign(); 658 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 659 } 660 661 if (!UnsafeFPMath) { 662 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 663 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 664 } 665 666 setOperationAction(ISD::FMA, MVT::f80, Expand); 667 } 668 669 // Always use a library call for pow. 670 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 671 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 672 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 673 674 setOperationAction(ISD::FLOG, MVT::f80, Expand); 675 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 676 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 677 setOperationAction(ISD::FEXP, MVT::f80, Expand); 678 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 679 680 // First set operation action for all vector types to either promote 681 // (for widening) or expand (for scalarization). Then we will selectively 682 // turn on ones that can be effectively codegen'd. 683 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 684 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 685 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 686 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 687 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 688 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 689 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 690 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 691 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 692 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 693 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 694 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 695 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 696 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 697 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 698 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 699 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 700 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 701 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 702 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 703 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 704 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 705 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 706 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 735 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 740 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 741 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 742 setTruncStoreAction((MVT::SimpleValueType)VT, 743 (MVT::SimpleValueType)InnerVT, Expand); 744 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 745 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 746 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 747 } 748 749 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 750 // with -msoft-float, disable use of MMX as well. 751 if (!UseSoftFloat && Subtarget->hasMMX()) { 752 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 753 // No operations on x86mmx supported, everything uses intrinsics. 754 } 755 756 // MMX-sized vectors (other than x86mmx) are expected to be expanded 757 // into smaller operations. 758 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 759 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 760 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 761 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 762 setOperationAction(ISD::AND, MVT::v8i8, Expand); 763 setOperationAction(ISD::AND, MVT::v4i16, Expand); 764 setOperationAction(ISD::AND, MVT::v2i32, Expand); 765 setOperationAction(ISD::AND, MVT::v1i64, Expand); 766 setOperationAction(ISD::OR, MVT::v8i8, Expand); 767 setOperationAction(ISD::OR, MVT::v4i16, Expand); 768 setOperationAction(ISD::OR, MVT::v2i32, Expand); 769 setOperationAction(ISD::OR, MVT::v1i64, Expand); 770 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 771 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 772 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 773 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 774 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 775 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 777 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 779 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 780 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 781 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 782 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 783 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 784 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 785 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 786 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 787 788 if (!UseSoftFloat && Subtarget->hasXMM()) { 789 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 790 791 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 792 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 793 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 794 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 795 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 796 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 797 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 798 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 799 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 800 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 801 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 802 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 803 } 804 805 if (!UseSoftFloat && Subtarget->hasXMMInt()) { 806 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 807 808 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 809 // registers cannot be used even for integer operations. 810 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 811 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 812 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 813 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 814 815 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 816 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 817 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 818 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 819 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 820 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 821 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 822 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 823 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 824 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 825 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 831 832 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 833 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 834 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 835 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 836 837 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 842 843 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 844 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 845 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 846 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 847 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 848 849 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 850 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 851 EVT VT = (MVT::SimpleValueType)i; 852 // Do not attempt to custom lower non-power-of-2 vectors 853 if (!isPowerOf2_32(VT.getVectorNumElements())) 854 continue; 855 // Do not attempt to custom lower non-128-bit vectors 856 if (!VT.is128BitVector()) 857 continue; 858 setOperationAction(ISD::BUILD_VECTOR, 859 VT.getSimpleVT().SimpleTy, Custom); 860 setOperationAction(ISD::VECTOR_SHUFFLE, 861 VT.getSimpleVT().SimpleTy, Custom); 862 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 863 VT.getSimpleVT().SimpleTy, Custom); 864 } 865 866 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 867 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 868 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 869 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 871 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 872 873 if (Subtarget->is64Bit()) { 874 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 876 } 877 878 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 879 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 880 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 881 EVT VT = SVT; 882 883 // Do not attempt to promote non-128-bit vectors 884 if (!VT.is128BitVector()) 885 continue; 886 887 setOperationAction(ISD::AND, SVT, Promote); 888 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 889 setOperationAction(ISD::OR, SVT, Promote); 890 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 891 setOperationAction(ISD::XOR, SVT, Promote); 892 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 893 setOperationAction(ISD::LOAD, SVT, Promote); 894 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 895 setOperationAction(ISD::SELECT, SVT, Promote); 896 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 897 } 898 899 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 900 901 // Custom lower v2i64 and v2f64 selects. 902 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 903 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 904 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 905 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 906 907 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 908 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 909 } 910 911 if (Subtarget->hasSSE41orAVX()) { 912 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 913 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 914 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 915 setOperationAction(ISD::FRINT, MVT::f32, Legal); 916 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 917 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 918 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 919 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 920 setOperationAction(ISD::FRINT, MVT::f64, Legal); 921 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 922 923 // FIXME: Do we need to handle scalar-to-vector here? 924 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 925 926 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 927 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 928 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 929 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 930 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 931 932 // i8 and i16 vectors are custom , because the source register and source 933 // source memory operand types are not the same width. f32 vectors are 934 // custom since the immediate controlling the insert encodes additional 935 // information. 936 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 937 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 938 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 939 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 940 941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 942 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 945 946 // FIXME: these should be Legal but thats only for the case where 947 // the index is constant. For now custom expand to deal with that 948 if (Subtarget->is64Bit()) { 949 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 951 } 952 } 953 954 if (Subtarget->hasXMMInt()) { 955 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 956 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 957 958 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 959 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 960 961 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 962 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 963 964 if (Subtarget->hasAVX2()) { 965 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 966 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 967 968 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 969 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 970 971 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 972 } else { 973 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 974 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 975 976 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 977 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 978 979 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 980 } 981 } 982 983 if (Subtarget->hasSSE42orAVX()) 984 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 985 986 if (!UseSoftFloat && Subtarget->hasAVX()) { 987 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 988 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 989 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 990 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 991 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 992 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 993 994 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 995 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 996 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 997 998 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 999 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1000 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1001 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1002 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1003 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1004 1005 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1006 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1007 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1008 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1009 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1010 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1011 1012 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1013 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1014 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1015 1016 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1017 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1018 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1019 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1020 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1021 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1022 1023 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1024 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1025 1026 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1027 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1028 1029 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1030 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1031 1032 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1033 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1034 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1035 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1036 1037 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1038 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1039 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1040 1041 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1042 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1043 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1044 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1045 1046 if (Subtarget->hasAVX2()) { 1047 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1048 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1049 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1050 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1051 1052 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1053 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1054 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1055 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1056 1057 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1058 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1059 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1060 // Don't lower v32i8 because there is no 128-bit byte mul 1061 1062 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1063 1064 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1065 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1066 1067 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1068 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1069 1070 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1071 } else { 1072 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1073 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1074 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1075 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1076 1077 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1078 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1079 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1080 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1081 1082 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1083 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1084 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1085 // Don't lower v32i8 because there is no 128-bit byte mul 1086 1087 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1088 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1089 1090 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1091 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1092 1093 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1094 } 1095 1096 // Custom lower several nodes for 256-bit types. 1097 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1098 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1099 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1100 EVT VT = SVT; 1101 1102 // Extract subvector is special because the value type 1103 // (result) is 128-bit but the source is 256-bit wide. 1104 if (VT.is128BitVector()) 1105 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1106 1107 // Do not attempt to custom lower other non-256-bit vectors 1108 if (!VT.is256BitVector()) 1109 continue; 1110 1111 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1112 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1113 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1114 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1115 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1116 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1117 } 1118 1119 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1120 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1121 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1122 EVT VT = SVT; 1123 1124 // Do not attempt to promote non-256-bit vectors 1125 if (!VT.is256BitVector()) 1126 continue; 1127 1128 setOperationAction(ISD::AND, SVT, Promote); 1129 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1130 setOperationAction(ISD::OR, SVT, Promote); 1131 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1132 setOperationAction(ISD::XOR, SVT, Promote); 1133 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1134 setOperationAction(ISD::LOAD, SVT, Promote); 1135 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1136 setOperationAction(ISD::SELECT, SVT, Promote); 1137 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1138 } 1139 } 1140 1141 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1142 // of this type with custom code. 1143 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1144 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1145 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom); 1146 } 1147 1148 // We want to custom lower some of our intrinsics. 1149 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1150 1151 1152 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1153 // handle type legalization for these operations here. 1154 // 1155 // FIXME: We really should do custom legalization for addition and 1156 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1157 // than generic legalization for 64-bit multiplication-with-overflow, though. 1158 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1159 // Add/Sub/Mul with overflow operations are custom lowered. 1160 MVT VT = IntVTs[i]; 1161 setOperationAction(ISD::SADDO, VT, Custom); 1162 setOperationAction(ISD::UADDO, VT, Custom); 1163 setOperationAction(ISD::SSUBO, VT, Custom); 1164 setOperationAction(ISD::USUBO, VT, Custom); 1165 setOperationAction(ISD::SMULO, VT, Custom); 1166 setOperationAction(ISD::UMULO, VT, Custom); 1167 } 1168 1169 // There are no 8-bit 3-address imul/mul instructions 1170 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1171 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1172 1173 if (!Subtarget->is64Bit()) { 1174 // These libcalls are not available in 32-bit. 1175 setLibcallName(RTLIB::SHL_I128, 0); 1176 setLibcallName(RTLIB::SRL_I128, 0); 1177 setLibcallName(RTLIB::SRA_I128, 0); 1178 } 1179 1180 // We have target-specific dag combine patterns for the following nodes: 1181 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1182 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1183 setTargetDAGCombine(ISD::BUILD_VECTOR); 1184 setTargetDAGCombine(ISD::VSELECT); 1185 setTargetDAGCombine(ISD::SELECT); 1186 setTargetDAGCombine(ISD::SHL); 1187 setTargetDAGCombine(ISD::SRA); 1188 setTargetDAGCombine(ISD::SRL); 1189 setTargetDAGCombine(ISD::OR); 1190 setTargetDAGCombine(ISD::AND); 1191 setTargetDAGCombine(ISD::ADD); 1192 setTargetDAGCombine(ISD::FADD); 1193 setTargetDAGCombine(ISD::FSUB); 1194 setTargetDAGCombine(ISD::SUB); 1195 setTargetDAGCombine(ISD::LOAD); 1196 setTargetDAGCombine(ISD::STORE); 1197 setTargetDAGCombine(ISD::ZERO_EXTEND); 1198 setTargetDAGCombine(ISD::SINT_TO_FP); 1199 if (Subtarget->is64Bit()) 1200 setTargetDAGCombine(ISD::MUL); 1201 if (Subtarget->hasBMI()) 1202 setTargetDAGCombine(ISD::XOR); 1203 1204 computeRegisterProperties(); 1205 1206 // On Darwin, -Os means optimize for size without hurting performance, 1207 // do not reduce the limit. 1208 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1209 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1210 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1211 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1212 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1213 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1214 setPrefLoopAlignment(16); 1215 benefitFromCodePlacementOpt = true; 1216 1217 setPrefFunctionAlignment(4); 1218} 1219 1220 1221EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1222 if (!VT.isVector()) return MVT::i8; 1223 return VT.changeVectorElementTypeToInteger(); 1224} 1225 1226 1227/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1228/// the desired ByVal argument alignment. 1229static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1230 if (MaxAlign == 16) 1231 return; 1232 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1233 if (VTy->getBitWidth() == 128) 1234 MaxAlign = 16; 1235 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1236 unsigned EltAlign = 0; 1237 getMaxByValAlign(ATy->getElementType(), EltAlign); 1238 if (EltAlign > MaxAlign) 1239 MaxAlign = EltAlign; 1240 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1241 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1242 unsigned EltAlign = 0; 1243 getMaxByValAlign(STy->getElementType(i), EltAlign); 1244 if (EltAlign > MaxAlign) 1245 MaxAlign = EltAlign; 1246 if (MaxAlign == 16) 1247 break; 1248 } 1249 } 1250 return; 1251} 1252 1253/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1254/// function arguments in the caller parameter area. For X86, aggregates 1255/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1256/// are at 4-byte boundaries. 1257unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1258 if (Subtarget->is64Bit()) { 1259 // Max of 8 and alignment of type. 1260 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1261 if (TyAlign > 8) 1262 return TyAlign; 1263 return 8; 1264 } 1265 1266 unsigned Align = 4; 1267 if (Subtarget->hasXMM()) 1268 getMaxByValAlign(Ty, Align); 1269 return Align; 1270} 1271 1272/// getOptimalMemOpType - Returns the target specific optimal type for load 1273/// and store operations as a result of memset, memcpy, and memmove 1274/// lowering. If DstAlign is zero that means it's safe to destination 1275/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1276/// means there isn't a need to check it against alignment requirement, 1277/// probably because the source does not need to be loaded. If 1278/// 'IsZeroVal' is true, that means it's safe to return a 1279/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1280/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1281/// constant so it does not need to be loaded. 1282/// It returns EVT::Other if the type should be determined using generic 1283/// target-independent logic. 1284EVT 1285X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1286 unsigned DstAlign, unsigned SrcAlign, 1287 bool IsZeroVal, 1288 bool MemcpyStrSrc, 1289 MachineFunction &MF) const { 1290 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1291 // linux. This is because the stack realignment code can't handle certain 1292 // cases like PR2962. This should be removed when PR2962 is fixed. 1293 const Function *F = MF.getFunction(); 1294 if (IsZeroVal && 1295 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1296 if (Size >= 16 && 1297 (Subtarget->isUnalignedMemAccessFast() || 1298 ((DstAlign == 0 || DstAlign >= 16) && 1299 (SrcAlign == 0 || SrcAlign >= 16))) && 1300 Subtarget->getStackAlignment() >= 16) { 1301 if (Subtarget->hasAVX() && 1302 Subtarget->getStackAlignment() >= 32) 1303 return MVT::v8f32; 1304 if (Subtarget->hasXMMInt()) 1305 return MVT::v4i32; 1306 if (Subtarget->hasXMM()) 1307 return MVT::v4f32; 1308 } else if (!MemcpyStrSrc && Size >= 8 && 1309 !Subtarget->is64Bit() && 1310 Subtarget->getStackAlignment() >= 8 && 1311 Subtarget->hasXMMInt()) { 1312 // Do not use f64 to lower memcpy if source is string constant. It's 1313 // better to use i32 to avoid the loads. 1314 return MVT::f64; 1315 } 1316 } 1317 if (Subtarget->is64Bit() && Size >= 8) 1318 return MVT::i64; 1319 return MVT::i32; 1320} 1321 1322/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1323/// current function. The returned value is a member of the 1324/// MachineJumpTableInfo::JTEntryKind enum. 1325unsigned X86TargetLowering::getJumpTableEncoding() const { 1326 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1327 // symbol. 1328 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1329 Subtarget->isPICStyleGOT()) 1330 return MachineJumpTableInfo::EK_Custom32; 1331 1332 // Otherwise, use the normal jump table encoding heuristics. 1333 return TargetLowering::getJumpTableEncoding(); 1334} 1335 1336const MCExpr * 1337X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1338 const MachineBasicBlock *MBB, 1339 unsigned uid,MCContext &Ctx) const{ 1340 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1341 Subtarget->isPICStyleGOT()); 1342 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1343 // entries. 1344 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1345 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1346} 1347 1348/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1349/// jumptable. 1350SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1351 SelectionDAG &DAG) const { 1352 if (!Subtarget->is64Bit()) 1353 // This doesn't have DebugLoc associated with it, but is not really the 1354 // same as a Register. 1355 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1356 return Table; 1357} 1358 1359/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1360/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1361/// MCExpr. 1362const MCExpr *X86TargetLowering:: 1363getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1364 MCContext &Ctx) const { 1365 // X86-64 uses RIP relative addressing based on the jump table label. 1366 if (Subtarget->isPICStyleRIPRel()) 1367 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1368 1369 // Otherwise, the reference is relative to the PIC base. 1370 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1371} 1372 1373// FIXME: Why this routine is here? Move to RegInfo! 1374std::pair<const TargetRegisterClass*, uint8_t> 1375X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1376 const TargetRegisterClass *RRC = 0; 1377 uint8_t Cost = 1; 1378 switch (VT.getSimpleVT().SimpleTy) { 1379 default: 1380 return TargetLowering::findRepresentativeClass(VT); 1381 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1382 RRC = (Subtarget->is64Bit() 1383 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1384 break; 1385 case MVT::x86mmx: 1386 RRC = X86::VR64RegisterClass; 1387 break; 1388 case MVT::f32: case MVT::f64: 1389 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1390 case MVT::v4f32: case MVT::v2f64: 1391 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1392 case MVT::v4f64: 1393 RRC = X86::VR128RegisterClass; 1394 break; 1395 } 1396 return std::make_pair(RRC, Cost); 1397} 1398 1399bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1400 unsigned &Offset) const { 1401 if (!Subtarget->isTargetLinux()) 1402 return false; 1403 1404 if (Subtarget->is64Bit()) { 1405 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1406 Offset = 0x28; 1407 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1408 AddressSpace = 256; 1409 else 1410 AddressSpace = 257; 1411 } else { 1412 // %gs:0x14 on i386 1413 Offset = 0x14; 1414 AddressSpace = 256; 1415 } 1416 return true; 1417} 1418 1419 1420//===----------------------------------------------------------------------===// 1421// Return Value Calling Convention Implementation 1422//===----------------------------------------------------------------------===// 1423 1424#include "X86GenCallingConv.inc" 1425 1426bool 1427X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1428 MachineFunction &MF, bool isVarArg, 1429 const SmallVectorImpl<ISD::OutputArg> &Outs, 1430 LLVMContext &Context) const { 1431 SmallVector<CCValAssign, 16> RVLocs; 1432 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1433 RVLocs, Context); 1434 return CCInfo.CheckReturn(Outs, RetCC_X86); 1435} 1436 1437SDValue 1438X86TargetLowering::LowerReturn(SDValue Chain, 1439 CallingConv::ID CallConv, bool isVarArg, 1440 const SmallVectorImpl<ISD::OutputArg> &Outs, 1441 const SmallVectorImpl<SDValue> &OutVals, 1442 DebugLoc dl, SelectionDAG &DAG) const { 1443 MachineFunction &MF = DAG.getMachineFunction(); 1444 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1445 1446 SmallVector<CCValAssign, 16> RVLocs; 1447 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1448 RVLocs, *DAG.getContext()); 1449 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1450 1451 // Add the regs to the liveout set for the function. 1452 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1453 for (unsigned i = 0; i != RVLocs.size(); ++i) 1454 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1455 MRI.addLiveOut(RVLocs[i].getLocReg()); 1456 1457 SDValue Flag; 1458 1459 SmallVector<SDValue, 6> RetOps; 1460 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1461 // Operand #1 = Bytes To Pop 1462 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1463 MVT::i16)); 1464 1465 // Copy the result values into the output registers. 1466 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1467 CCValAssign &VA = RVLocs[i]; 1468 assert(VA.isRegLoc() && "Can only return in registers!"); 1469 SDValue ValToCopy = OutVals[i]; 1470 EVT ValVT = ValToCopy.getValueType(); 1471 1472 // If this is x86-64, and we disabled SSE, we can't return FP values, 1473 // or SSE or MMX vectors. 1474 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1475 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1476 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1477 report_fatal_error("SSE register return with SSE disabled"); 1478 } 1479 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1480 // llvm-gcc has never done it right and no one has noticed, so this 1481 // should be OK for now. 1482 if (ValVT == MVT::f64 && 1483 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1484 report_fatal_error("SSE2 register return with SSE2 disabled"); 1485 1486 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1487 // the RET instruction and handled by the FP Stackifier. 1488 if (VA.getLocReg() == X86::ST0 || 1489 VA.getLocReg() == X86::ST1) { 1490 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1491 // change the value to the FP stack register class. 1492 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1493 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1494 RetOps.push_back(ValToCopy); 1495 // Don't emit a copytoreg. 1496 continue; 1497 } 1498 1499 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1500 // which is returned in RAX / RDX. 1501 if (Subtarget->is64Bit()) { 1502 if (ValVT == MVT::x86mmx) { 1503 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1504 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1505 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1506 ValToCopy); 1507 // If we don't have SSE2 available, convert to v4f32 so the generated 1508 // register is legal. 1509 if (!Subtarget->hasXMMInt()) 1510 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1511 } 1512 } 1513 } 1514 1515 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1516 Flag = Chain.getValue(1); 1517 } 1518 1519 // The x86-64 ABI for returning structs by value requires that we copy 1520 // the sret argument into %rax for the return. We saved the argument into 1521 // a virtual register in the entry block, so now we copy the value out 1522 // and into %rax. 1523 if (Subtarget->is64Bit() && 1524 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1525 MachineFunction &MF = DAG.getMachineFunction(); 1526 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1527 unsigned Reg = FuncInfo->getSRetReturnReg(); 1528 assert(Reg && 1529 "SRetReturnReg should have been set in LowerFormalArguments()."); 1530 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1531 1532 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1533 Flag = Chain.getValue(1); 1534 1535 // RAX now acts like a return value. 1536 MRI.addLiveOut(X86::RAX); 1537 } 1538 1539 RetOps[0] = Chain; // Update chain. 1540 1541 // Add the flag if we have it. 1542 if (Flag.getNode()) 1543 RetOps.push_back(Flag); 1544 1545 return DAG.getNode(X86ISD::RET_FLAG, dl, 1546 MVT::Other, &RetOps[0], RetOps.size()); 1547} 1548 1549bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1550 if (N->getNumValues() != 1) 1551 return false; 1552 if (!N->hasNUsesOfValue(1, 0)) 1553 return false; 1554 1555 SDNode *Copy = *N->use_begin(); 1556 if (Copy->getOpcode() != ISD::CopyToReg && 1557 Copy->getOpcode() != ISD::FP_EXTEND) 1558 return false; 1559 1560 bool HasRet = false; 1561 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1562 UI != UE; ++UI) { 1563 if (UI->getOpcode() != X86ISD::RET_FLAG) 1564 return false; 1565 HasRet = true; 1566 } 1567 1568 return HasRet; 1569} 1570 1571EVT 1572X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1573 ISD::NodeType ExtendKind) const { 1574 MVT ReturnMVT; 1575 // TODO: Is this also valid on 32-bit? 1576 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1577 ReturnMVT = MVT::i8; 1578 else 1579 ReturnMVT = MVT::i32; 1580 1581 EVT MinVT = getRegisterType(Context, ReturnMVT); 1582 return VT.bitsLT(MinVT) ? MinVT : VT; 1583} 1584 1585/// LowerCallResult - Lower the result values of a call into the 1586/// appropriate copies out of appropriate physical registers. 1587/// 1588SDValue 1589X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1590 CallingConv::ID CallConv, bool isVarArg, 1591 const SmallVectorImpl<ISD::InputArg> &Ins, 1592 DebugLoc dl, SelectionDAG &DAG, 1593 SmallVectorImpl<SDValue> &InVals) const { 1594 1595 // Assign locations to each value returned by this call. 1596 SmallVector<CCValAssign, 16> RVLocs; 1597 bool Is64Bit = Subtarget->is64Bit(); 1598 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1599 getTargetMachine(), RVLocs, *DAG.getContext()); 1600 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1601 1602 // Copy all of the result registers out of their specified physreg. 1603 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1604 CCValAssign &VA = RVLocs[i]; 1605 EVT CopyVT = VA.getValVT(); 1606 1607 // If this is x86-64, and we disabled SSE, we can't return FP values 1608 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1609 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1610 report_fatal_error("SSE register return with SSE disabled"); 1611 } 1612 1613 SDValue Val; 1614 1615 // If this is a call to a function that returns an fp value on the floating 1616 // point stack, we must guarantee the the value is popped from the stack, so 1617 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1618 // if the return value is not used. We use the FpPOP_RETVAL instruction 1619 // instead. 1620 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1621 // If we prefer to use the value in xmm registers, copy it out as f80 and 1622 // use a truncate to move it from fp stack reg to xmm reg. 1623 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1624 SDValue Ops[] = { Chain, InFlag }; 1625 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1626 MVT::Other, MVT::Glue, Ops, 2), 1); 1627 Val = Chain.getValue(0); 1628 1629 // Round the f80 to the right size, which also moves it to the appropriate 1630 // xmm register. 1631 if (CopyVT != VA.getValVT()) 1632 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1633 // This truncation won't change the value. 1634 DAG.getIntPtrConstant(1)); 1635 } else { 1636 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1637 CopyVT, InFlag).getValue(1); 1638 Val = Chain.getValue(0); 1639 } 1640 InFlag = Chain.getValue(2); 1641 InVals.push_back(Val); 1642 } 1643 1644 return Chain; 1645} 1646 1647 1648//===----------------------------------------------------------------------===// 1649// C & StdCall & Fast Calling Convention implementation 1650//===----------------------------------------------------------------------===// 1651// StdCall calling convention seems to be standard for many Windows' API 1652// routines and around. It differs from C calling convention just a little: 1653// callee should clean up the stack, not caller. Symbols should be also 1654// decorated in some fancy way :) It doesn't support any vector arguments. 1655// For info on fast calling convention see Fast Calling Convention (tail call) 1656// implementation LowerX86_32FastCCCallTo. 1657 1658/// CallIsStructReturn - Determines whether a call uses struct return 1659/// semantics. 1660static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1661 if (Outs.empty()) 1662 return false; 1663 1664 return Outs[0].Flags.isSRet(); 1665} 1666 1667/// ArgsAreStructReturn - Determines whether a function uses struct 1668/// return semantics. 1669static bool 1670ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1671 if (Ins.empty()) 1672 return false; 1673 1674 return Ins[0].Flags.isSRet(); 1675} 1676 1677/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1678/// by "Src" to address "Dst" with size and alignment information specified by 1679/// the specific parameter attribute. The copy will be passed as a byval 1680/// function parameter. 1681static SDValue 1682CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1683 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1684 DebugLoc dl) { 1685 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1686 1687 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1688 /*isVolatile*/false, /*AlwaysInline=*/true, 1689 MachinePointerInfo(), MachinePointerInfo()); 1690} 1691 1692/// IsTailCallConvention - Return true if the calling convention is one that 1693/// supports tail call optimization. 1694static bool IsTailCallConvention(CallingConv::ID CC) { 1695 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1696} 1697 1698bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1699 if (!CI->isTailCall()) 1700 return false; 1701 1702 CallSite CS(CI); 1703 CallingConv::ID CalleeCC = CS.getCallingConv(); 1704 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1705 return false; 1706 1707 return true; 1708} 1709 1710/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1711/// a tailcall target by changing its ABI. 1712static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1713 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1714} 1715 1716SDValue 1717X86TargetLowering::LowerMemArgument(SDValue Chain, 1718 CallingConv::ID CallConv, 1719 const SmallVectorImpl<ISD::InputArg> &Ins, 1720 DebugLoc dl, SelectionDAG &DAG, 1721 const CCValAssign &VA, 1722 MachineFrameInfo *MFI, 1723 unsigned i) const { 1724 // Create the nodes corresponding to a load from this parameter slot. 1725 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1726 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1727 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1728 EVT ValVT; 1729 1730 // If value is passed by pointer we have address passed instead of the value 1731 // itself. 1732 if (VA.getLocInfo() == CCValAssign::Indirect) 1733 ValVT = VA.getLocVT(); 1734 else 1735 ValVT = VA.getValVT(); 1736 1737 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1738 // changed with more analysis. 1739 // In case of tail call optimization mark all arguments mutable. Since they 1740 // could be overwritten by lowering of arguments in case of a tail call. 1741 if (Flags.isByVal()) { 1742 unsigned Bytes = Flags.getByValSize(); 1743 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1744 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1745 return DAG.getFrameIndex(FI, getPointerTy()); 1746 } else { 1747 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1748 VA.getLocMemOffset(), isImmutable); 1749 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1750 return DAG.getLoad(ValVT, dl, Chain, FIN, 1751 MachinePointerInfo::getFixedStack(FI), 1752 false, false, false, 0); 1753 } 1754} 1755 1756SDValue 1757X86TargetLowering::LowerFormalArguments(SDValue Chain, 1758 CallingConv::ID CallConv, 1759 bool isVarArg, 1760 const SmallVectorImpl<ISD::InputArg> &Ins, 1761 DebugLoc dl, 1762 SelectionDAG &DAG, 1763 SmallVectorImpl<SDValue> &InVals) 1764 const { 1765 MachineFunction &MF = DAG.getMachineFunction(); 1766 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1767 1768 const Function* Fn = MF.getFunction(); 1769 if (Fn->hasExternalLinkage() && 1770 Subtarget->isTargetCygMing() && 1771 Fn->getName() == "main") 1772 FuncInfo->setForceFramePointer(true); 1773 1774 MachineFrameInfo *MFI = MF.getFrameInfo(); 1775 bool Is64Bit = Subtarget->is64Bit(); 1776 bool IsWin64 = Subtarget->isTargetWin64(); 1777 1778 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1779 "Var args not supported with calling convention fastcc or ghc"); 1780 1781 // Assign locations to all of the incoming arguments. 1782 SmallVector<CCValAssign, 16> ArgLocs; 1783 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1784 ArgLocs, *DAG.getContext()); 1785 1786 // Allocate shadow area for Win64 1787 if (IsWin64) { 1788 CCInfo.AllocateStack(32, 8); 1789 } 1790 1791 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1792 1793 unsigned LastVal = ~0U; 1794 SDValue ArgValue; 1795 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1796 CCValAssign &VA = ArgLocs[i]; 1797 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1798 // places. 1799 assert(VA.getValNo() != LastVal && 1800 "Don't support value assigned to multiple locs yet"); 1801 (void)LastVal; 1802 LastVal = VA.getValNo(); 1803 1804 if (VA.isRegLoc()) { 1805 EVT RegVT = VA.getLocVT(); 1806 TargetRegisterClass *RC = NULL; 1807 if (RegVT == MVT::i32) 1808 RC = X86::GR32RegisterClass; 1809 else if (Is64Bit && RegVT == MVT::i64) 1810 RC = X86::GR64RegisterClass; 1811 else if (RegVT == MVT::f32) 1812 RC = X86::FR32RegisterClass; 1813 else if (RegVT == MVT::f64) 1814 RC = X86::FR64RegisterClass; 1815 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1816 RC = X86::VR256RegisterClass; 1817 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1818 RC = X86::VR128RegisterClass; 1819 else if (RegVT == MVT::x86mmx) 1820 RC = X86::VR64RegisterClass; 1821 else 1822 llvm_unreachable("Unknown argument type!"); 1823 1824 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1825 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1826 1827 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1828 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1829 // right size. 1830 if (VA.getLocInfo() == CCValAssign::SExt) 1831 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1832 DAG.getValueType(VA.getValVT())); 1833 else if (VA.getLocInfo() == CCValAssign::ZExt) 1834 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1835 DAG.getValueType(VA.getValVT())); 1836 else if (VA.getLocInfo() == CCValAssign::BCvt) 1837 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1838 1839 if (VA.isExtInLoc()) { 1840 // Handle MMX values passed in XMM regs. 1841 if (RegVT.isVector()) { 1842 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1843 ArgValue); 1844 } else 1845 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1846 } 1847 } else { 1848 assert(VA.isMemLoc()); 1849 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1850 } 1851 1852 // If value is passed via pointer - do a load. 1853 if (VA.getLocInfo() == CCValAssign::Indirect) 1854 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1855 MachinePointerInfo(), false, false, false, 0); 1856 1857 InVals.push_back(ArgValue); 1858 } 1859 1860 // The x86-64 ABI for returning structs by value requires that we copy 1861 // the sret argument into %rax for the return. Save the argument into 1862 // a virtual register so that we can access it from the return points. 1863 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1864 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1865 unsigned Reg = FuncInfo->getSRetReturnReg(); 1866 if (!Reg) { 1867 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1868 FuncInfo->setSRetReturnReg(Reg); 1869 } 1870 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1871 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1872 } 1873 1874 unsigned StackSize = CCInfo.getNextStackOffset(); 1875 // Align stack specially for tail calls. 1876 if (FuncIsMadeTailCallSafe(CallConv)) 1877 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1878 1879 // If the function takes variable number of arguments, make a frame index for 1880 // the start of the first vararg value... for expansion of llvm.va_start. 1881 if (isVarArg) { 1882 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1883 CallConv != CallingConv::X86_ThisCall)) { 1884 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1885 } 1886 if (Is64Bit) { 1887 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1888 1889 // FIXME: We should really autogenerate these arrays 1890 static const unsigned GPR64ArgRegsWin64[] = { 1891 X86::RCX, X86::RDX, X86::R8, X86::R9 1892 }; 1893 static const unsigned GPR64ArgRegs64Bit[] = { 1894 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1895 }; 1896 static const unsigned XMMArgRegs64Bit[] = { 1897 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1898 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1899 }; 1900 const unsigned *GPR64ArgRegs; 1901 unsigned NumXMMRegs = 0; 1902 1903 if (IsWin64) { 1904 // The XMM registers which might contain var arg parameters are shadowed 1905 // in their paired GPR. So we only need to save the GPR to their home 1906 // slots. 1907 TotalNumIntRegs = 4; 1908 GPR64ArgRegs = GPR64ArgRegsWin64; 1909 } else { 1910 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1911 GPR64ArgRegs = GPR64ArgRegs64Bit; 1912 1913 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1914 } 1915 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1916 TotalNumIntRegs); 1917 1918 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1919 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1920 "SSE register cannot be used when SSE is disabled!"); 1921 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1922 "SSE register cannot be used when SSE is disabled!"); 1923 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM()) 1924 // Kernel mode asks for SSE to be disabled, so don't push them 1925 // on the stack. 1926 TotalNumXMMRegs = 0; 1927 1928 if (IsWin64) { 1929 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1930 // Get to the caller-allocated home save location. Add 8 to account 1931 // for the return address. 1932 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1933 FuncInfo->setRegSaveFrameIndex( 1934 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1935 // Fixup to set vararg frame on shadow area (4 x i64). 1936 if (NumIntRegs < 4) 1937 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1938 } else { 1939 // For X86-64, if there are vararg parameters that are passed via 1940 // registers, then we must store them to their spots on the stack so they 1941 // may be loaded by deferencing the result of va_next. 1942 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1943 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1944 FuncInfo->setRegSaveFrameIndex( 1945 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1946 false)); 1947 } 1948 1949 // Store the integer parameter registers. 1950 SmallVector<SDValue, 8> MemOps; 1951 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1952 getPointerTy()); 1953 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1954 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1955 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1956 DAG.getIntPtrConstant(Offset)); 1957 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1958 X86::GR64RegisterClass); 1959 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1960 SDValue Store = 1961 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1962 MachinePointerInfo::getFixedStack( 1963 FuncInfo->getRegSaveFrameIndex(), Offset), 1964 false, false, 0); 1965 MemOps.push_back(Store); 1966 Offset += 8; 1967 } 1968 1969 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1970 // Now store the XMM (fp + vector) parameter registers. 1971 SmallVector<SDValue, 11> SaveXMMOps; 1972 SaveXMMOps.push_back(Chain); 1973 1974 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1975 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1976 SaveXMMOps.push_back(ALVal); 1977 1978 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1979 FuncInfo->getRegSaveFrameIndex())); 1980 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1981 FuncInfo->getVarArgsFPOffset())); 1982 1983 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1984 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1985 X86::VR128RegisterClass); 1986 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1987 SaveXMMOps.push_back(Val); 1988 } 1989 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1990 MVT::Other, 1991 &SaveXMMOps[0], SaveXMMOps.size())); 1992 } 1993 1994 if (!MemOps.empty()) 1995 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1996 &MemOps[0], MemOps.size()); 1997 } 1998 } 1999 2000 // Some CCs need callee pop. 2001 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) { 2002 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2003 } else { 2004 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2005 // If this is an sret function, the return should pop the hidden pointer. 2006 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 2007 FuncInfo->setBytesToPopOnReturn(4); 2008 } 2009 2010 if (!Is64Bit) { 2011 // RegSaveFrameIndex is X86-64 only. 2012 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2013 if (CallConv == CallingConv::X86_FastCall || 2014 CallConv == CallingConv::X86_ThisCall) 2015 // fastcc functions can't have varargs. 2016 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2017 } 2018 2019 FuncInfo->setArgumentStackSize(StackSize); 2020 2021 return Chain; 2022} 2023 2024SDValue 2025X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2026 SDValue StackPtr, SDValue Arg, 2027 DebugLoc dl, SelectionDAG &DAG, 2028 const CCValAssign &VA, 2029 ISD::ArgFlagsTy Flags) const { 2030 unsigned LocMemOffset = VA.getLocMemOffset(); 2031 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2032 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2033 if (Flags.isByVal()) 2034 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2035 2036 return DAG.getStore(Chain, dl, Arg, PtrOff, 2037 MachinePointerInfo::getStack(LocMemOffset), 2038 false, false, 0); 2039} 2040 2041/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2042/// optimization is performed and it is required. 2043SDValue 2044X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2045 SDValue &OutRetAddr, SDValue Chain, 2046 bool IsTailCall, bool Is64Bit, 2047 int FPDiff, DebugLoc dl) const { 2048 // Adjust the Return address stack slot. 2049 EVT VT = getPointerTy(); 2050 OutRetAddr = getReturnAddressFrameIndex(DAG); 2051 2052 // Load the "old" Return address. 2053 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2054 false, false, false, 0); 2055 return SDValue(OutRetAddr.getNode(), 1); 2056} 2057 2058/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2059/// optimization is performed and it is required (FPDiff!=0). 2060static SDValue 2061EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2062 SDValue Chain, SDValue RetAddrFrIdx, 2063 bool Is64Bit, int FPDiff, DebugLoc dl) { 2064 // Store the return address to the appropriate stack slot. 2065 if (!FPDiff) return Chain; 2066 // Calculate the new stack slot for the return address. 2067 int SlotSize = Is64Bit ? 8 : 4; 2068 int NewReturnAddrFI = 2069 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2070 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2071 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2072 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2073 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2074 false, false, 0); 2075 return Chain; 2076} 2077 2078SDValue 2079X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2080 CallingConv::ID CallConv, bool isVarArg, 2081 bool &isTailCall, 2082 const SmallVectorImpl<ISD::OutputArg> &Outs, 2083 const SmallVectorImpl<SDValue> &OutVals, 2084 const SmallVectorImpl<ISD::InputArg> &Ins, 2085 DebugLoc dl, SelectionDAG &DAG, 2086 SmallVectorImpl<SDValue> &InVals) const { 2087 MachineFunction &MF = DAG.getMachineFunction(); 2088 bool Is64Bit = Subtarget->is64Bit(); 2089 bool IsWin64 = Subtarget->isTargetWin64(); 2090 bool IsStructRet = CallIsStructReturn(Outs); 2091 bool IsSibcall = false; 2092 2093 if (isTailCall) { 2094 // Check if it's really possible to do a tail call. 2095 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2096 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2097 Outs, OutVals, Ins, DAG); 2098 2099 // Sibcalls are automatically detected tailcalls which do not require 2100 // ABI changes. 2101 if (!GuaranteedTailCallOpt && isTailCall) 2102 IsSibcall = true; 2103 2104 if (isTailCall) 2105 ++NumTailCalls; 2106 } 2107 2108 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2109 "Var args not supported with calling convention fastcc or ghc"); 2110 2111 // Analyze operands of the call, assigning locations to each operand. 2112 SmallVector<CCValAssign, 16> ArgLocs; 2113 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2114 ArgLocs, *DAG.getContext()); 2115 2116 // Allocate shadow area for Win64 2117 if (IsWin64) { 2118 CCInfo.AllocateStack(32, 8); 2119 } 2120 2121 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2122 2123 // Get a count of how many bytes are to be pushed on the stack. 2124 unsigned NumBytes = CCInfo.getNextStackOffset(); 2125 if (IsSibcall) 2126 // This is a sibcall. The memory operands are available in caller's 2127 // own caller's stack. 2128 NumBytes = 0; 2129 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 2130 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2131 2132 int FPDiff = 0; 2133 if (isTailCall && !IsSibcall) { 2134 // Lower arguments at fp - stackoffset + fpdiff. 2135 unsigned NumBytesCallerPushed = 2136 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2137 FPDiff = NumBytesCallerPushed - NumBytes; 2138 2139 // Set the delta of movement of the returnaddr stackslot. 2140 // But only set if delta is greater than previous delta. 2141 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2142 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2143 } 2144 2145 if (!IsSibcall) 2146 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2147 2148 SDValue RetAddrFrIdx; 2149 // Load return address for tail calls. 2150 if (isTailCall && FPDiff) 2151 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2152 Is64Bit, FPDiff, dl); 2153 2154 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2155 SmallVector<SDValue, 8> MemOpChains; 2156 SDValue StackPtr; 2157 2158 // Walk the register/memloc assignments, inserting copies/loads. In the case 2159 // of tail call optimization arguments are handle later. 2160 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2161 CCValAssign &VA = ArgLocs[i]; 2162 EVT RegVT = VA.getLocVT(); 2163 SDValue Arg = OutVals[i]; 2164 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2165 bool isByVal = Flags.isByVal(); 2166 2167 // Promote the value if needed. 2168 switch (VA.getLocInfo()) { 2169 default: llvm_unreachable("Unknown loc info!"); 2170 case CCValAssign::Full: break; 2171 case CCValAssign::SExt: 2172 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2173 break; 2174 case CCValAssign::ZExt: 2175 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2176 break; 2177 case CCValAssign::AExt: 2178 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2179 // Special case: passing MMX values in XMM registers. 2180 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2181 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2182 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2183 } else 2184 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2185 break; 2186 case CCValAssign::BCvt: 2187 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2188 break; 2189 case CCValAssign::Indirect: { 2190 // Store the argument. 2191 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2192 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2193 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2194 MachinePointerInfo::getFixedStack(FI), 2195 false, false, 0); 2196 Arg = SpillSlot; 2197 break; 2198 } 2199 } 2200 2201 if (VA.isRegLoc()) { 2202 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2203 if (isVarArg && IsWin64) { 2204 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2205 // shadow reg if callee is a varargs function. 2206 unsigned ShadowReg = 0; 2207 switch (VA.getLocReg()) { 2208 case X86::XMM0: ShadowReg = X86::RCX; break; 2209 case X86::XMM1: ShadowReg = X86::RDX; break; 2210 case X86::XMM2: ShadowReg = X86::R8; break; 2211 case X86::XMM3: ShadowReg = X86::R9; break; 2212 } 2213 if (ShadowReg) 2214 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2215 } 2216 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2217 assert(VA.isMemLoc()); 2218 if (StackPtr.getNode() == 0) 2219 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2220 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2221 dl, DAG, VA, Flags)); 2222 } 2223 } 2224 2225 if (!MemOpChains.empty()) 2226 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2227 &MemOpChains[0], MemOpChains.size()); 2228 2229 // Build a sequence of copy-to-reg nodes chained together with token chain 2230 // and flag operands which copy the outgoing args into registers. 2231 SDValue InFlag; 2232 // Tail call byval lowering might overwrite argument registers so in case of 2233 // tail call optimization the copies to registers are lowered later. 2234 if (!isTailCall) 2235 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2236 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2237 RegsToPass[i].second, InFlag); 2238 InFlag = Chain.getValue(1); 2239 } 2240 2241 if (Subtarget->isPICStyleGOT()) { 2242 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2243 // GOT pointer. 2244 if (!isTailCall) { 2245 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2246 DAG.getNode(X86ISD::GlobalBaseReg, 2247 DebugLoc(), getPointerTy()), 2248 InFlag); 2249 InFlag = Chain.getValue(1); 2250 } else { 2251 // If we are tail calling and generating PIC/GOT style code load the 2252 // address of the callee into ECX. The value in ecx is used as target of 2253 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2254 // for tail calls on PIC/GOT architectures. Normally we would just put the 2255 // address of GOT into ebx and then call target@PLT. But for tail calls 2256 // ebx would be restored (since ebx is callee saved) before jumping to the 2257 // target@PLT. 2258 2259 // Note: The actual moving to ECX is done further down. 2260 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2261 if (G && !G->getGlobal()->hasHiddenVisibility() && 2262 !G->getGlobal()->hasProtectedVisibility()) 2263 Callee = LowerGlobalAddress(Callee, DAG); 2264 else if (isa<ExternalSymbolSDNode>(Callee)) 2265 Callee = LowerExternalSymbol(Callee, DAG); 2266 } 2267 } 2268 2269 if (Is64Bit && isVarArg && !IsWin64) { 2270 // From AMD64 ABI document: 2271 // For calls that may call functions that use varargs or stdargs 2272 // (prototype-less calls or calls to functions containing ellipsis (...) in 2273 // the declaration) %al is used as hidden argument to specify the number 2274 // of SSE registers used. The contents of %al do not need to match exactly 2275 // the number of registers, but must be an ubound on the number of SSE 2276 // registers used and is in the range 0 - 8 inclusive. 2277 2278 // Count the number of XMM registers allocated. 2279 static const unsigned XMMArgRegs[] = { 2280 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2281 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2282 }; 2283 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2284 assert((Subtarget->hasXMM() || !NumXMMRegs) 2285 && "SSE registers cannot be used when SSE is disabled"); 2286 2287 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2288 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2289 InFlag = Chain.getValue(1); 2290 } 2291 2292 2293 // For tail calls lower the arguments to the 'real' stack slot. 2294 if (isTailCall) { 2295 // Force all the incoming stack arguments to be loaded from the stack 2296 // before any new outgoing arguments are stored to the stack, because the 2297 // outgoing stack slots may alias the incoming argument stack slots, and 2298 // the alias isn't otherwise explicit. This is slightly more conservative 2299 // than necessary, because it means that each store effectively depends 2300 // on every argument instead of just those arguments it would clobber. 2301 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2302 2303 SmallVector<SDValue, 8> MemOpChains2; 2304 SDValue FIN; 2305 int FI = 0; 2306 // Do not flag preceding copytoreg stuff together with the following stuff. 2307 InFlag = SDValue(); 2308 if (GuaranteedTailCallOpt) { 2309 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2310 CCValAssign &VA = ArgLocs[i]; 2311 if (VA.isRegLoc()) 2312 continue; 2313 assert(VA.isMemLoc()); 2314 SDValue Arg = OutVals[i]; 2315 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2316 // Create frame index. 2317 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2318 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2319 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2320 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2321 2322 if (Flags.isByVal()) { 2323 // Copy relative to framepointer. 2324 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2325 if (StackPtr.getNode() == 0) 2326 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2327 getPointerTy()); 2328 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2329 2330 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2331 ArgChain, 2332 Flags, DAG, dl)); 2333 } else { 2334 // Store relative to framepointer. 2335 MemOpChains2.push_back( 2336 DAG.getStore(ArgChain, dl, Arg, FIN, 2337 MachinePointerInfo::getFixedStack(FI), 2338 false, false, 0)); 2339 } 2340 } 2341 } 2342 2343 if (!MemOpChains2.empty()) 2344 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2345 &MemOpChains2[0], MemOpChains2.size()); 2346 2347 // Copy arguments to their registers. 2348 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2349 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2350 RegsToPass[i].second, InFlag); 2351 InFlag = Chain.getValue(1); 2352 } 2353 InFlag =SDValue(); 2354 2355 // Store the return address to the appropriate stack slot. 2356 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2357 FPDiff, dl); 2358 } 2359 2360 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2361 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2362 // In the 64-bit large code model, we have to make all calls 2363 // through a register, since the call instruction's 32-bit 2364 // pc-relative offset may not be large enough to hold the whole 2365 // address. 2366 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2367 // If the callee is a GlobalAddress node (quite common, every direct call 2368 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2369 // it. 2370 2371 // We should use extra load for direct calls to dllimported functions in 2372 // non-JIT mode. 2373 const GlobalValue *GV = G->getGlobal(); 2374 if (!GV->hasDLLImportLinkage()) { 2375 unsigned char OpFlags = 0; 2376 bool ExtraLoad = false; 2377 unsigned WrapperKind = ISD::DELETED_NODE; 2378 2379 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2380 // external symbols most go through the PLT in PIC mode. If the symbol 2381 // has hidden or protected visibility, or if it is static or local, then 2382 // we don't need to use the PLT - we can directly call it. 2383 if (Subtarget->isTargetELF() && 2384 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2385 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2386 OpFlags = X86II::MO_PLT; 2387 } else if (Subtarget->isPICStyleStubAny() && 2388 (GV->isDeclaration() || GV->isWeakForLinker()) && 2389 (!Subtarget->getTargetTriple().isMacOSX() || 2390 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2391 // PC-relative references to external symbols should go through $stub, 2392 // unless we're building with the leopard linker or later, which 2393 // automatically synthesizes these stubs. 2394 OpFlags = X86II::MO_DARWIN_STUB; 2395 } else if (Subtarget->isPICStyleRIPRel() && 2396 isa<Function>(GV) && 2397 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2398 // If the function is marked as non-lazy, generate an indirect call 2399 // which loads from the GOT directly. This avoids runtime overhead 2400 // at the cost of eager binding (and one extra byte of encoding). 2401 OpFlags = X86II::MO_GOTPCREL; 2402 WrapperKind = X86ISD::WrapperRIP; 2403 ExtraLoad = true; 2404 } 2405 2406 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2407 G->getOffset(), OpFlags); 2408 2409 // Add a wrapper if needed. 2410 if (WrapperKind != ISD::DELETED_NODE) 2411 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2412 // Add extra indirection if needed. 2413 if (ExtraLoad) 2414 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2415 MachinePointerInfo::getGOT(), 2416 false, false, false, 0); 2417 } 2418 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2419 unsigned char OpFlags = 0; 2420 2421 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2422 // external symbols should go through the PLT. 2423 if (Subtarget->isTargetELF() && 2424 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2425 OpFlags = X86II::MO_PLT; 2426 } else if (Subtarget->isPICStyleStubAny() && 2427 (!Subtarget->getTargetTriple().isMacOSX() || 2428 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2429 // PC-relative references to external symbols should go through $stub, 2430 // unless we're building with the leopard linker or later, which 2431 // automatically synthesizes these stubs. 2432 OpFlags = X86II::MO_DARWIN_STUB; 2433 } 2434 2435 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2436 OpFlags); 2437 } 2438 2439 // Returns a chain & a flag for retval copy to use. 2440 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2441 SmallVector<SDValue, 8> Ops; 2442 2443 if (!IsSibcall && isTailCall) { 2444 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2445 DAG.getIntPtrConstant(0, true), InFlag); 2446 InFlag = Chain.getValue(1); 2447 } 2448 2449 Ops.push_back(Chain); 2450 Ops.push_back(Callee); 2451 2452 if (isTailCall) 2453 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2454 2455 // Add argument registers to the end of the list so that they are known live 2456 // into the call. 2457 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2458 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2459 RegsToPass[i].second.getValueType())); 2460 2461 // Add an implicit use GOT pointer in EBX. 2462 if (!isTailCall && Subtarget->isPICStyleGOT()) 2463 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2464 2465 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2466 if (Is64Bit && isVarArg && !IsWin64) 2467 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2468 2469 if (InFlag.getNode()) 2470 Ops.push_back(InFlag); 2471 2472 if (isTailCall) { 2473 // We used to do: 2474 //// If this is the first return lowered for this function, add the regs 2475 //// to the liveout set for the function. 2476 // This isn't right, although it's probably harmless on x86; liveouts 2477 // should be computed from returns not tail calls. Consider a void 2478 // function making a tail call to a function returning int. 2479 return DAG.getNode(X86ISD::TC_RETURN, dl, 2480 NodeTys, &Ops[0], Ops.size()); 2481 } 2482 2483 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2484 InFlag = Chain.getValue(1); 2485 2486 // Create the CALLSEQ_END node. 2487 unsigned NumBytesForCalleeToPush; 2488 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) 2489 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2490 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2491 // If this is a call to a struct-return function, the callee 2492 // pops the hidden struct pointer, so we have to push it back. 2493 // This is common for Darwin/X86, Linux & Mingw32 targets. 2494 NumBytesForCalleeToPush = 4; 2495 else 2496 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2497 2498 // Returns a flag for retval copy to use. 2499 if (!IsSibcall) { 2500 Chain = DAG.getCALLSEQ_END(Chain, 2501 DAG.getIntPtrConstant(NumBytes, true), 2502 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2503 true), 2504 InFlag); 2505 InFlag = Chain.getValue(1); 2506 } 2507 2508 // Handle result values, copying them out of physregs into vregs that we 2509 // return. 2510 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2511 Ins, dl, DAG, InVals); 2512} 2513 2514 2515//===----------------------------------------------------------------------===// 2516// Fast Calling Convention (tail call) implementation 2517//===----------------------------------------------------------------------===// 2518 2519// Like std call, callee cleans arguments, convention except that ECX is 2520// reserved for storing the tail called function address. Only 2 registers are 2521// free for argument passing (inreg). Tail call optimization is performed 2522// provided: 2523// * tailcallopt is enabled 2524// * caller/callee are fastcc 2525// On X86_64 architecture with GOT-style position independent code only local 2526// (within module) calls are supported at the moment. 2527// To keep the stack aligned according to platform abi the function 2528// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2529// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2530// If a tail called function callee has more arguments than the caller the 2531// caller needs to make sure that there is room to move the RETADDR to. This is 2532// achieved by reserving an area the size of the argument delta right after the 2533// original REtADDR, but before the saved framepointer or the spilled registers 2534// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2535// stack layout: 2536// arg1 2537// arg2 2538// RETADDR 2539// [ new RETADDR 2540// move area ] 2541// (possible EBP) 2542// ESI 2543// EDI 2544// local1 .. 2545 2546/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2547/// for a 16 byte align requirement. 2548unsigned 2549X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2550 SelectionDAG& DAG) const { 2551 MachineFunction &MF = DAG.getMachineFunction(); 2552 const TargetMachine &TM = MF.getTarget(); 2553 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2554 unsigned StackAlignment = TFI.getStackAlignment(); 2555 uint64_t AlignMask = StackAlignment - 1; 2556 int64_t Offset = StackSize; 2557 uint64_t SlotSize = TD->getPointerSize(); 2558 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2559 // Number smaller than 12 so just add the difference. 2560 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2561 } else { 2562 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2563 Offset = ((~AlignMask) & Offset) + StackAlignment + 2564 (StackAlignment-SlotSize); 2565 } 2566 return Offset; 2567} 2568 2569/// MatchingStackOffset - Return true if the given stack call argument is 2570/// already available in the same position (relatively) of the caller's 2571/// incoming argument stack. 2572static 2573bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2574 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2575 const X86InstrInfo *TII) { 2576 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2577 int FI = INT_MAX; 2578 if (Arg.getOpcode() == ISD::CopyFromReg) { 2579 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2580 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2581 return false; 2582 MachineInstr *Def = MRI->getVRegDef(VR); 2583 if (!Def) 2584 return false; 2585 if (!Flags.isByVal()) { 2586 if (!TII->isLoadFromStackSlot(Def, FI)) 2587 return false; 2588 } else { 2589 unsigned Opcode = Def->getOpcode(); 2590 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2591 Def->getOperand(1).isFI()) { 2592 FI = Def->getOperand(1).getIndex(); 2593 Bytes = Flags.getByValSize(); 2594 } else 2595 return false; 2596 } 2597 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2598 if (Flags.isByVal()) 2599 // ByVal argument is passed in as a pointer but it's now being 2600 // dereferenced. e.g. 2601 // define @foo(%struct.X* %A) { 2602 // tail call @bar(%struct.X* byval %A) 2603 // } 2604 return false; 2605 SDValue Ptr = Ld->getBasePtr(); 2606 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2607 if (!FINode) 2608 return false; 2609 FI = FINode->getIndex(); 2610 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2611 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2612 FI = FINode->getIndex(); 2613 Bytes = Flags.getByValSize(); 2614 } else 2615 return false; 2616 2617 assert(FI != INT_MAX); 2618 if (!MFI->isFixedObjectIndex(FI)) 2619 return false; 2620 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2621} 2622 2623/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2624/// for tail call optimization. Targets which want to do tail call 2625/// optimization should implement this function. 2626bool 2627X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2628 CallingConv::ID CalleeCC, 2629 bool isVarArg, 2630 bool isCalleeStructRet, 2631 bool isCallerStructRet, 2632 const SmallVectorImpl<ISD::OutputArg> &Outs, 2633 const SmallVectorImpl<SDValue> &OutVals, 2634 const SmallVectorImpl<ISD::InputArg> &Ins, 2635 SelectionDAG& DAG) const { 2636 if (!IsTailCallConvention(CalleeCC) && 2637 CalleeCC != CallingConv::C) 2638 return false; 2639 2640 // If -tailcallopt is specified, make fastcc functions tail-callable. 2641 const MachineFunction &MF = DAG.getMachineFunction(); 2642 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2643 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2644 bool CCMatch = CallerCC == CalleeCC; 2645 2646 if (GuaranteedTailCallOpt) { 2647 if (IsTailCallConvention(CalleeCC) && CCMatch) 2648 return true; 2649 return false; 2650 } 2651 2652 // Look for obvious safe cases to perform tail call optimization that do not 2653 // require ABI changes. This is what gcc calls sibcall. 2654 2655 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2656 // emit a special epilogue. 2657 if (RegInfo->needsStackRealignment(MF)) 2658 return false; 2659 2660 // Also avoid sibcall optimization if either caller or callee uses struct 2661 // return semantics. 2662 if (isCalleeStructRet || isCallerStructRet) 2663 return false; 2664 2665 // An stdcall caller is expected to clean up its arguments; the callee 2666 // isn't going to do that. 2667 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2668 return false; 2669 2670 // Do not sibcall optimize vararg calls unless all arguments are passed via 2671 // registers. 2672 if (isVarArg && !Outs.empty()) { 2673 2674 // Optimizing for varargs on Win64 is unlikely to be safe without 2675 // additional testing. 2676 if (Subtarget->isTargetWin64()) 2677 return false; 2678 2679 SmallVector<CCValAssign, 16> ArgLocs; 2680 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2681 getTargetMachine(), ArgLocs, *DAG.getContext()); 2682 2683 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2684 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2685 if (!ArgLocs[i].isRegLoc()) 2686 return false; 2687 } 2688 2689 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2690 // Therefore if it's not used by the call it is not safe to optimize this into 2691 // a sibcall. 2692 bool Unused = false; 2693 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2694 if (!Ins[i].Used) { 2695 Unused = true; 2696 break; 2697 } 2698 } 2699 if (Unused) { 2700 SmallVector<CCValAssign, 16> RVLocs; 2701 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2702 getTargetMachine(), RVLocs, *DAG.getContext()); 2703 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2704 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2705 CCValAssign &VA = RVLocs[i]; 2706 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2707 return false; 2708 } 2709 } 2710 2711 // If the calling conventions do not match, then we'd better make sure the 2712 // results are returned in the same way as what the caller expects. 2713 if (!CCMatch) { 2714 SmallVector<CCValAssign, 16> RVLocs1; 2715 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2716 getTargetMachine(), RVLocs1, *DAG.getContext()); 2717 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2718 2719 SmallVector<CCValAssign, 16> RVLocs2; 2720 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2721 getTargetMachine(), RVLocs2, *DAG.getContext()); 2722 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2723 2724 if (RVLocs1.size() != RVLocs2.size()) 2725 return false; 2726 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2727 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2728 return false; 2729 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2730 return false; 2731 if (RVLocs1[i].isRegLoc()) { 2732 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2733 return false; 2734 } else { 2735 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2736 return false; 2737 } 2738 } 2739 } 2740 2741 // If the callee takes no arguments then go on to check the results of the 2742 // call. 2743 if (!Outs.empty()) { 2744 // Check if stack adjustment is needed. For now, do not do this if any 2745 // argument is passed on the stack. 2746 SmallVector<CCValAssign, 16> ArgLocs; 2747 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2748 getTargetMachine(), ArgLocs, *DAG.getContext()); 2749 2750 // Allocate shadow area for Win64 2751 if (Subtarget->isTargetWin64()) { 2752 CCInfo.AllocateStack(32, 8); 2753 } 2754 2755 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2756 if (CCInfo.getNextStackOffset()) { 2757 MachineFunction &MF = DAG.getMachineFunction(); 2758 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2759 return false; 2760 2761 // Check if the arguments are already laid out in the right way as 2762 // the caller's fixed stack objects. 2763 MachineFrameInfo *MFI = MF.getFrameInfo(); 2764 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2765 const X86InstrInfo *TII = 2766 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2767 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2768 CCValAssign &VA = ArgLocs[i]; 2769 SDValue Arg = OutVals[i]; 2770 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2771 if (VA.getLocInfo() == CCValAssign::Indirect) 2772 return false; 2773 if (!VA.isRegLoc()) { 2774 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2775 MFI, MRI, TII)) 2776 return false; 2777 } 2778 } 2779 } 2780 2781 // If the tailcall address may be in a register, then make sure it's 2782 // possible to register allocate for it. In 32-bit, the call address can 2783 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2784 // callee-saved registers are restored. These happen to be the same 2785 // registers used to pass 'inreg' arguments so watch out for those. 2786 if (!Subtarget->is64Bit() && 2787 !isa<GlobalAddressSDNode>(Callee) && 2788 !isa<ExternalSymbolSDNode>(Callee)) { 2789 unsigned NumInRegs = 0; 2790 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2791 CCValAssign &VA = ArgLocs[i]; 2792 if (!VA.isRegLoc()) 2793 continue; 2794 unsigned Reg = VA.getLocReg(); 2795 switch (Reg) { 2796 default: break; 2797 case X86::EAX: case X86::EDX: case X86::ECX: 2798 if (++NumInRegs == 3) 2799 return false; 2800 break; 2801 } 2802 } 2803 } 2804 } 2805 2806 return true; 2807} 2808 2809FastISel * 2810X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2811 return X86::createFastISel(funcInfo); 2812} 2813 2814 2815//===----------------------------------------------------------------------===// 2816// Other Lowering Hooks 2817//===----------------------------------------------------------------------===// 2818 2819static bool MayFoldLoad(SDValue Op) { 2820 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2821} 2822 2823static bool MayFoldIntoStore(SDValue Op) { 2824 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2825} 2826 2827static bool isTargetShuffle(unsigned Opcode) { 2828 switch(Opcode) { 2829 default: return false; 2830 case X86ISD::PSHUFD: 2831 case X86ISD::PSHUFHW: 2832 case X86ISD::PSHUFLW: 2833 case X86ISD::SHUFPD: 2834 case X86ISD::PALIGN: 2835 case X86ISD::SHUFPS: 2836 case X86ISD::MOVLHPS: 2837 case X86ISD::MOVLHPD: 2838 case X86ISD::MOVHLPS: 2839 case X86ISD::MOVLPS: 2840 case X86ISD::MOVLPD: 2841 case X86ISD::MOVSHDUP: 2842 case X86ISD::MOVSLDUP: 2843 case X86ISD::MOVDDUP: 2844 case X86ISD::MOVSS: 2845 case X86ISD::MOVSD: 2846 case X86ISD::UNPCKLPS: 2847 case X86ISD::UNPCKLPD: 2848 case X86ISD::VUNPCKLPSY: 2849 case X86ISD::VUNPCKLPDY: 2850 case X86ISD::PUNPCKLWD: 2851 case X86ISD::PUNPCKLBW: 2852 case X86ISD::PUNPCKLDQ: 2853 case X86ISD::PUNPCKLQDQ: 2854 case X86ISD::VPUNPCKLWDY: 2855 case X86ISD::VPUNPCKLBWY: 2856 case X86ISD::VPUNPCKLDQY: 2857 case X86ISD::VPUNPCKLQDQY: 2858 case X86ISD::UNPCKHPS: 2859 case X86ISD::UNPCKHPD: 2860 case X86ISD::VUNPCKHPSY: 2861 case X86ISD::VUNPCKHPDY: 2862 case X86ISD::PUNPCKHWD: 2863 case X86ISD::PUNPCKHBW: 2864 case X86ISD::PUNPCKHDQ: 2865 case X86ISD::PUNPCKHQDQ: 2866 case X86ISD::VPUNPCKHWDY: 2867 case X86ISD::VPUNPCKHBWY: 2868 case X86ISD::VPUNPCKHDQY: 2869 case X86ISD::VPUNPCKHQDQY: 2870 case X86ISD::VPERMILPS: 2871 case X86ISD::VPERMILPSY: 2872 case X86ISD::VPERMILPD: 2873 case X86ISD::VPERMILPDY: 2874 case X86ISD::VPERM2F128: 2875 return true; 2876 } 2877 return false; 2878} 2879 2880static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2881 SDValue V1, SelectionDAG &DAG) { 2882 switch(Opc) { 2883 default: llvm_unreachable("Unknown x86 shuffle node"); 2884 case X86ISD::MOVSHDUP: 2885 case X86ISD::MOVSLDUP: 2886 case X86ISD::MOVDDUP: 2887 return DAG.getNode(Opc, dl, VT, V1); 2888 } 2889 2890 return SDValue(); 2891} 2892 2893static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2894 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2895 switch(Opc) { 2896 default: llvm_unreachable("Unknown x86 shuffle node"); 2897 case X86ISD::PSHUFD: 2898 case X86ISD::PSHUFHW: 2899 case X86ISD::PSHUFLW: 2900 case X86ISD::VPERMILPS: 2901 case X86ISD::VPERMILPSY: 2902 case X86ISD::VPERMILPD: 2903 case X86ISD::VPERMILPDY: 2904 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2905 } 2906 2907 return SDValue(); 2908} 2909 2910static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2911 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2912 switch(Opc) { 2913 default: llvm_unreachable("Unknown x86 shuffle node"); 2914 case X86ISD::PALIGN: 2915 case X86ISD::SHUFPD: 2916 case X86ISD::SHUFPS: 2917 case X86ISD::VPERM2F128: 2918 return DAG.getNode(Opc, dl, VT, V1, V2, 2919 DAG.getConstant(TargetMask, MVT::i8)); 2920 } 2921 return SDValue(); 2922} 2923 2924static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2925 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2926 switch(Opc) { 2927 default: llvm_unreachable("Unknown x86 shuffle node"); 2928 case X86ISD::MOVLHPS: 2929 case X86ISD::MOVLHPD: 2930 case X86ISD::MOVHLPS: 2931 case X86ISD::MOVLPS: 2932 case X86ISD::MOVLPD: 2933 case X86ISD::MOVSS: 2934 case X86ISD::MOVSD: 2935 case X86ISD::UNPCKLPS: 2936 case X86ISD::UNPCKLPD: 2937 case X86ISD::VUNPCKLPSY: 2938 case X86ISD::VUNPCKLPDY: 2939 case X86ISD::PUNPCKLWD: 2940 case X86ISD::PUNPCKLBW: 2941 case X86ISD::PUNPCKLDQ: 2942 case X86ISD::PUNPCKLQDQ: 2943 case X86ISD::VPUNPCKLWDY: 2944 case X86ISD::VPUNPCKLBWY: 2945 case X86ISD::VPUNPCKLDQY: 2946 case X86ISD::VPUNPCKLQDQY: 2947 case X86ISD::UNPCKHPS: 2948 case X86ISD::UNPCKHPD: 2949 case X86ISD::VUNPCKHPSY: 2950 case X86ISD::VUNPCKHPDY: 2951 case X86ISD::PUNPCKHWD: 2952 case X86ISD::PUNPCKHBW: 2953 case X86ISD::PUNPCKHDQ: 2954 case X86ISD::PUNPCKHQDQ: 2955 case X86ISD::VPUNPCKHWDY: 2956 case X86ISD::VPUNPCKHBWY: 2957 case X86ISD::VPUNPCKHDQY: 2958 case X86ISD::VPUNPCKHQDQY: 2959 return DAG.getNode(Opc, dl, VT, V1, V2); 2960 } 2961 return SDValue(); 2962} 2963 2964SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2965 MachineFunction &MF = DAG.getMachineFunction(); 2966 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2967 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2968 2969 if (ReturnAddrIndex == 0) { 2970 // Set up a frame object for the return address. 2971 uint64_t SlotSize = TD->getPointerSize(); 2972 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2973 false); 2974 FuncInfo->setRAIndex(ReturnAddrIndex); 2975 } 2976 2977 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2978} 2979 2980 2981bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2982 bool hasSymbolicDisplacement) { 2983 // Offset should fit into 32 bit immediate field. 2984 if (!isInt<32>(Offset)) 2985 return false; 2986 2987 // If we don't have a symbolic displacement - we don't have any extra 2988 // restrictions. 2989 if (!hasSymbolicDisplacement) 2990 return true; 2991 2992 // FIXME: Some tweaks might be needed for medium code model. 2993 if (M != CodeModel::Small && M != CodeModel::Kernel) 2994 return false; 2995 2996 // For small code model we assume that latest object is 16MB before end of 31 2997 // bits boundary. We may also accept pretty large negative constants knowing 2998 // that all objects are in the positive half of address space. 2999 if (M == CodeModel::Small && Offset < 16*1024*1024) 3000 return true; 3001 3002 // For kernel code model we know that all object resist in the negative half 3003 // of 32bits address space. We may not accept negative offsets, since they may 3004 // be just off and we may accept pretty large positive ones. 3005 if (M == CodeModel::Kernel && Offset > 0) 3006 return true; 3007 3008 return false; 3009} 3010 3011/// isCalleePop - Determines whether the callee is required to pop its 3012/// own arguments. Callee pop is necessary to support tail calls. 3013bool X86::isCalleePop(CallingConv::ID CallingConv, 3014 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3015 if (IsVarArg) 3016 return false; 3017 3018 switch (CallingConv) { 3019 default: 3020 return false; 3021 case CallingConv::X86_StdCall: 3022 return !is64Bit; 3023 case CallingConv::X86_FastCall: 3024 return !is64Bit; 3025 case CallingConv::X86_ThisCall: 3026 return !is64Bit; 3027 case CallingConv::Fast: 3028 return TailCallOpt; 3029 case CallingConv::GHC: 3030 return TailCallOpt; 3031 } 3032} 3033 3034/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3035/// specific condition code, returning the condition code and the LHS/RHS of the 3036/// comparison to make. 3037static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3038 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3039 if (!isFP) { 3040 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3041 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3042 // X > -1 -> X == 0, jump !sign. 3043 RHS = DAG.getConstant(0, RHS.getValueType()); 3044 return X86::COND_NS; 3045 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3046 // X < 0 -> X == 0, jump on sign. 3047 return X86::COND_S; 3048 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3049 // X < 1 -> X <= 0 3050 RHS = DAG.getConstant(0, RHS.getValueType()); 3051 return X86::COND_LE; 3052 } 3053 } 3054 3055 switch (SetCCOpcode) { 3056 default: llvm_unreachable("Invalid integer condition!"); 3057 case ISD::SETEQ: return X86::COND_E; 3058 case ISD::SETGT: return X86::COND_G; 3059 case ISD::SETGE: return X86::COND_GE; 3060 case ISD::SETLT: return X86::COND_L; 3061 case ISD::SETLE: return X86::COND_LE; 3062 case ISD::SETNE: return X86::COND_NE; 3063 case ISD::SETULT: return X86::COND_B; 3064 case ISD::SETUGT: return X86::COND_A; 3065 case ISD::SETULE: return X86::COND_BE; 3066 case ISD::SETUGE: return X86::COND_AE; 3067 } 3068 } 3069 3070 // First determine if it is required or is profitable to flip the operands. 3071 3072 // If LHS is a foldable load, but RHS is not, flip the condition. 3073 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3074 !ISD::isNON_EXTLoad(RHS.getNode())) { 3075 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3076 std::swap(LHS, RHS); 3077 } 3078 3079 switch (SetCCOpcode) { 3080 default: break; 3081 case ISD::SETOLT: 3082 case ISD::SETOLE: 3083 case ISD::SETUGT: 3084 case ISD::SETUGE: 3085 std::swap(LHS, RHS); 3086 break; 3087 } 3088 3089 // On a floating point condition, the flags are set as follows: 3090 // ZF PF CF op 3091 // 0 | 0 | 0 | X > Y 3092 // 0 | 0 | 1 | X < Y 3093 // 1 | 0 | 0 | X == Y 3094 // 1 | 1 | 1 | unordered 3095 switch (SetCCOpcode) { 3096 default: llvm_unreachable("Condcode should be pre-legalized away"); 3097 case ISD::SETUEQ: 3098 case ISD::SETEQ: return X86::COND_E; 3099 case ISD::SETOLT: // flipped 3100 case ISD::SETOGT: 3101 case ISD::SETGT: return X86::COND_A; 3102 case ISD::SETOLE: // flipped 3103 case ISD::SETOGE: 3104 case ISD::SETGE: return X86::COND_AE; 3105 case ISD::SETUGT: // flipped 3106 case ISD::SETULT: 3107 case ISD::SETLT: return X86::COND_B; 3108 case ISD::SETUGE: // flipped 3109 case ISD::SETULE: 3110 case ISD::SETLE: return X86::COND_BE; 3111 case ISD::SETONE: 3112 case ISD::SETNE: return X86::COND_NE; 3113 case ISD::SETUO: return X86::COND_P; 3114 case ISD::SETO: return X86::COND_NP; 3115 case ISD::SETOEQ: 3116 case ISD::SETUNE: return X86::COND_INVALID; 3117 } 3118} 3119 3120/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3121/// code. Current x86 isa includes the following FP cmov instructions: 3122/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3123static bool hasFPCMov(unsigned X86CC) { 3124 switch (X86CC) { 3125 default: 3126 return false; 3127 case X86::COND_B: 3128 case X86::COND_BE: 3129 case X86::COND_E: 3130 case X86::COND_P: 3131 case X86::COND_A: 3132 case X86::COND_AE: 3133 case X86::COND_NE: 3134 case X86::COND_NP: 3135 return true; 3136 } 3137} 3138 3139/// isFPImmLegal - Returns true if the target can instruction select the 3140/// specified FP immediate natively. If false, the legalizer will 3141/// materialize the FP immediate as a load from a constant pool. 3142bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3143 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3144 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3145 return true; 3146 } 3147 return false; 3148} 3149 3150/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3151/// the specified range (L, H]. 3152static bool isUndefOrInRange(int Val, int Low, int Hi) { 3153 return (Val < 0) || (Val >= Low && Val < Hi); 3154} 3155 3156/// isUndefOrInRange - Return true if every element in Mask, begining 3157/// from position Pos and ending in Pos+Size, falls within the specified 3158/// range (L, L+Pos]. or is undef. 3159static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask, 3160 int Pos, int Size, int Low, int Hi) { 3161 for (int i = Pos, e = Pos+Size; i != e; ++i) 3162 if (!isUndefOrInRange(Mask[i], Low, Hi)) 3163 return false; 3164 return true; 3165} 3166 3167/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3168/// specified value. 3169static bool isUndefOrEqual(int Val, int CmpVal) { 3170 if (Val < 0 || Val == CmpVal) 3171 return true; 3172 return false; 3173} 3174 3175/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3176/// from position Pos and ending in Pos+Size, falls within the specified 3177/// sequential range (L, L+Pos]. or is undef. 3178static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask, 3179 int Pos, int Size, int Low) { 3180 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3181 if (!isUndefOrEqual(Mask[i], Low)) 3182 return false; 3183 return true; 3184} 3185 3186/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3187/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3188/// the second operand. 3189static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3190 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3191 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3192 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3193 return (Mask[0] < 2 && Mask[1] < 2); 3194 return false; 3195} 3196 3197bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3198 SmallVector<int, 8> M; 3199 N->getMask(M); 3200 return ::isPSHUFDMask(M, N->getValueType(0)); 3201} 3202 3203/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3204/// is suitable for input to PSHUFHW. 3205static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3206 if (VT != MVT::v8i16) 3207 return false; 3208 3209 // Lower quadword copied in order or undef. 3210 for (int i = 0; i != 4; ++i) 3211 if (Mask[i] >= 0 && Mask[i] != i) 3212 return false; 3213 3214 // Upper quadword shuffled. 3215 for (int i = 4; i != 8; ++i) 3216 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3217 return false; 3218 3219 return true; 3220} 3221 3222bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3223 SmallVector<int, 8> M; 3224 N->getMask(M); 3225 return ::isPSHUFHWMask(M, N->getValueType(0)); 3226} 3227 3228/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3229/// is suitable for input to PSHUFLW. 3230static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3231 if (VT != MVT::v8i16) 3232 return false; 3233 3234 // Upper quadword copied in order. 3235 for (int i = 4; i != 8; ++i) 3236 if (Mask[i] >= 0 && Mask[i] != i) 3237 return false; 3238 3239 // Lower quadword shuffled. 3240 for (int i = 0; i != 4; ++i) 3241 if (Mask[i] >= 4) 3242 return false; 3243 3244 return true; 3245} 3246 3247bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3248 SmallVector<int, 8> M; 3249 N->getMask(M); 3250 return ::isPSHUFLWMask(M, N->getValueType(0)); 3251} 3252 3253/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3254/// is suitable for input to PALIGNR. 3255static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3256 bool hasSSSE3OrAVX) { 3257 int i, e = VT.getVectorNumElements(); 3258 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64) 3259 return false; 3260 3261 // Do not handle v2i64 / v2f64 shuffles with palignr. 3262 if (e < 4 || !hasSSSE3OrAVX) 3263 return false; 3264 3265 for (i = 0; i != e; ++i) 3266 if (Mask[i] >= 0) 3267 break; 3268 3269 // All undef, not a palignr. 3270 if (i == e) 3271 return false; 3272 3273 // Make sure we're shifting in the right direction. 3274 if (Mask[i] <= i) 3275 return false; 3276 3277 int s = Mask[i] - i; 3278 3279 // Check the rest of the elements to see if they are consecutive. 3280 for (++i; i != e; ++i) { 3281 int m = Mask[i]; 3282 if (m >= 0 && m != s+i) 3283 return false; 3284 } 3285 return true; 3286} 3287 3288/// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand 3289/// specifies a shuffle of elements that is suitable for input to 256-bit 3290/// VSHUFPSY. 3291static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3292 const X86Subtarget *Subtarget) { 3293 int NumElems = VT.getVectorNumElements(); 3294 3295 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3296 return false; 3297 3298 if (NumElems != 8) 3299 return false; 3300 3301 // VSHUFPSY divides the resulting vector into 4 chunks. 3302 // The sources are also splitted into 4 chunks, and each destination 3303 // chunk must come from a different source chunk. 3304 // 3305 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3306 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3307 // 3308 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3309 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3310 // 3311 int QuarterSize = NumElems/4; 3312 int HalfSize = QuarterSize*2; 3313 for (int i = 0; i < QuarterSize; ++i) 3314 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3315 return false; 3316 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3317 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3318 return false; 3319 3320 // The mask of the second half must be the same as the first but with 3321 // the appropriate offsets. This works in the same way as VPERMILPS 3322 // works with masks. 3323 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) { 3324 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3325 return false; 3326 int FstHalfIdx = i-HalfSize; 3327 if (Mask[FstHalfIdx] < 0) 3328 continue; 3329 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3330 return false; 3331 } 3332 for (int i = QuarterSize*3; i < NumElems; ++i) { 3333 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3334 return false; 3335 int FstHalfIdx = i-HalfSize; 3336 if (Mask[FstHalfIdx] < 0) 3337 continue; 3338 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3339 return false; 3340 3341 } 3342 3343 return true; 3344} 3345 3346/// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle 3347/// the specified VECTOR_MASK mask with VSHUFPSY instruction. 3348static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) { 3349 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3350 EVT VT = SVOp->getValueType(0); 3351 int NumElems = VT.getVectorNumElements(); 3352 3353 assert(NumElems == 8 && VT.getSizeInBits() == 256 && 3354 "Only supports v8i32 and v8f32 types"); 3355 3356 int HalfSize = NumElems/2; 3357 unsigned Mask = 0; 3358 for (int i = 0; i != NumElems ; ++i) { 3359 if (SVOp->getMaskElt(i) < 0) 3360 continue; 3361 // The mask of the first half must be equal to the second one. 3362 unsigned Shamt = (i%HalfSize)*2; 3363 unsigned Elt = SVOp->getMaskElt(i) % HalfSize; 3364 Mask |= Elt << Shamt; 3365 } 3366 3367 return Mask; 3368} 3369 3370/// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand 3371/// specifies a shuffle of elements that is suitable for input to 256-bit 3372/// VSHUFPDY. This shuffle doesn't have the same restriction as the PS 3373/// version and the mask of the second half isn't binded with the first 3374/// one. 3375static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3376 const X86Subtarget *Subtarget) { 3377 int NumElems = VT.getVectorNumElements(); 3378 3379 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3380 return false; 3381 3382 if (NumElems != 4) 3383 return false; 3384 3385 // VSHUFPSY divides the resulting vector into 4 chunks. 3386 // The sources are also splitted into 4 chunks, and each destination 3387 // chunk must come from a different source chunk. 3388 // 3389 // SRC1 => X3 X2 X1 X0 3390 // SRC2 => Y3 Y2 Y1 Y0 3391 // 3392 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0 3393 // 3394 int QuarterSize = NumElems/4; 3395 int HalfSize = QuarterSize*2; 3396 for (int i = 0; i < QuarterSize; ++i) 3397 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3398 return false; 3399 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3400 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3401 return false; 3402 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) 3403 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3404 return false; 3405 for (int i = QuarterSize*3; i < NumElems; ++i) 3406 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3407 return false; 3408 3409 return true; 3410} 3411 3412/// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle 3413/// the specified VECTOR_MASK mask with VSHUFPDY instruction. 3414static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) { 3415 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3416 EVT VT = SVOp->getValueType(0); 3417 int NumElems = VT.getVectorNumElements(); 3418 3419 assert(NumElems == 4 && VT.getSizeInBits() == 256 && 3420 "Only supports v4i64 and v4f64 types"); 3421 3422 int HalfSize = NumElems/2; 3423 unsigned Mask = 0; 3424 for (int i = 0; i != NumElems ; ++i) { 3425 if (SVOp->getMaskElt(i) < 0) 3426 continue; 3427 int Elt = SVOp->getMaskElt(i) % HalfSize; 3428 Mask |= Elt << i; 3429 } 3430 3431 return Mask; 3432} 3433 3434/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3435/// the two vector operands have swapped position. 3436static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3437 unsigned NumElems = VT.getVectorNumElements(); 3438 for (unsigned i = 0; i != NumElems; ++i) { 3439 int idx = Mask[i]; 3440 if (idx < 0) 3441 continue; 3442 else if (idx < (int)NumElems) 3443 Mask[i] = idx + NumElems; 3444 else 3445 Mask[i] = idx - NumElems; 3446 } 3447} 3448 3449/// isCommutedVSHUFP() - Return true if swapping operands will 3450/// allow to use the "vshufpd" or "vshufps" instruction 3451/// for 256-bit vectors 3452static bool isCommutedVSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT, 3453 const X86Subtarget *Subtarget) { 3454 3455 unsigned NumElems = VT.getVectorNumElements(); 3456 if ((VT.getSizeInBits() != 256) || ((NumElems != 4) && (NumElems != 8))) 3457 return false; 3458 3459 SmallVector<int, 8> CommutedMask; 3460 for (unsigned i = 0; i < NumElems; ++i) 3461 CommutedMask.push_back(Mask[i]); 3462 3463 CommuteVectorShuffleMask(CommutedMask, VT); 3464 return (NumElems == 4) ? isVSHUFPDYMask(CommutedMask, VT, Subtarget): 3465 isVSHUFPSYMask(CommutedMask, VT, Subtarget); 3466} 3467 3468 3469/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3470/// specifies a shuffle of elements that is suitable for input to 128-bit 3471/// SHUFPS and SHUFPD. 3472static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3473 int NumElems = VT.getVectorNumElements(); 3474 3475 if (VT.getSizeInBits() != 128) 3476 return false; 3477 3478 if (NumElems != 2 && NumElems != 4) 3479 return false; 3480 3481 int Half = NumElems / 2; 3482 for (int i = 0; i < Half; ++i) 3483 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3484 return false; 3485 for (int i = Half; i < NumElems; ++i) 3486 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3487 return false; 3488 3489 return true; 3490} 3491 3492bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3493 SmallVector<int, 8> M; 3494 N->getMask(M); 3495 return ::isSHUFPMask(M, N->getValueType(0)); 3496} 3497 3498/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 3499/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 3500/// half elements to come from vector 1 (which would equal the dest.) and 3501/// the upper half to come from vector 2. 3502static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3503 int NumElems = VT.getVectorNumElements(); 3504 3505 if (NumElems != 2 && NumElems != 4) 3506 return false; 3507 3508 int Half = NumElems / 2; 3509 for (int i = 0; i < Half; ++i) 3510 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3511 return false; 3512 for (int i = Half; i < NumElems; ++i) 3513 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3514 return false; 3515 return true; 3516} 3517 3518static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3519 SmallVector<int, 8> M; 3520 N->getMask(M); 3521 return isCommutedSHUFPMask(M, N->getValueType(0)); 3522} 3523 3524/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3525/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3526bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3527 EVT VT = N->getValueType(0); 3528 unsigned NumElems = VT.getVectorNumElements(); 3529 3530 if (VT.getSizeInBits() != 128) 3531 return false; 3532 3533 if (NumElems != 4) 3534 return false; 3535 3536 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3537 return isUndefOrEqual(N->getMaskElt(0), 6) && 3538 isUndefOrEqual(N->getMaskElt(1), 7) && 3539 isUndefOrEqual(N->getMaskElt(2), 2) && 3540 isUndefOrEqual(N->getMaskElt(3), 3); 3541} 3542 3543/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3544/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3545/// <2, 3, 2, 3> 3546bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3547 EVT VT = N->getValueType(0); 3548 unsigned NumElems = VT.getVectorNumElements(); 3549 3550 if (VT.getSizeInBits() != 128) 3551 return false; 3552 3553 if (NumElems != 4) 3554 return false; 3555 3556 return isUndefOrEqual(N->getMaskElt(0), 2) && 3557 isUndefOrEqual(N->getMaskElt(1), 3) && 3558 isUndefOrEqual(N->getMaskElt(2), 2) && 3559 isUndefOrEqual(N->getMaskElt(3), 3); 3560} 3561 3562/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3563/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3564bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3565 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3566 3567 if (NumElems != 2 && NumElems != 4) 3568 return false; 3569 3570 for (unsigned i = 0; i < NumElems/2; ++i) 3571 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3572 return false; 3573 3574 for (unsigned i = NumElems/2; i < NumElems; ++i) 3575 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3576 return false; 3577 3578 return true; 3579} 3580 3581/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3582/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3583bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3584 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3585 3586 if ((NumElems != 2 && NumElems != 4) 3587 || N->getValueType(0).getSizeInBits() > 128) 3588 return false; 3589 3590 for (unsigned i = 0; i < NumElems/2; ++i) 3591 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3592 return false; 3593 3594 for (unsigned i = 0; i < NumElems/2; ++i) 3595 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3596 return false; 3597 3598 return true; 3599} 3600 3601/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3602/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3603static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3604 bool HasAVX2, bool V2IsSplat = false) { 3605 int NumElts = VT.getVectorNumElements(); 3606 3607 assert((VT.is128BitVector() || VT.is256BitVector()) && 3608 "Unsupported vector type for unpckh"); 3609 3610 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3611 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3612 return false; 3613 3614 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3615 // independently on 128-bit lanes. 3616 unsigned NumLanes = VT.getSizeInBits()/128; 3617 unsigned NumLaneElts = NumElts/NumLanes; 3618 3619 unsigned Start = 0; 3620 unsigned End = NumLaneElts; 3621 for (unsigned s = 0; s < NumLanes; ++s) { 3622 for (unsigned i = Start, j = s * NumLaneElts; 3623 i != End; 3624 i += 2, ++j) { 3625 int BitI = Mask[i]; 3626 int BitI1 = Mask[i+1]; 3627 if (!isUndefOrEqual(BitI, j)) 3628 return false; 3629 if (V2IsSplat) { 3630 if (!isUndefOrEqual(BitI1, NumElts)) 3631 return false; 3632 } else { 3633 if (!isUndefOrEqual(BitI1, j + NumElts)) 3634 return false; 3635 } 3636 } 3637 // Process the next 128 bits. 3638 Start += NumLaneElts; 3639 End += NumLaneElts; 3640 } 3641 3642 return true; 3643} 3644 3645bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3646 SmallVector<int, 8> M; 3647 N->getMask(M); 3648 return ::isUNPCKLMask(M, N->getValueType(0), HasAVX2, V2IsSplat); 3649} 3650 3651/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3652/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3653static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3654 bool HasAVX2, bool V2IsSplat = false) { 3655 int NumElts = VT.getVectorNumElements(); 3656 3657 assert((VT.is128BitVector() || VT.is256BitVector()) && 3658 "Unsupported vector type for unpckh"); 3659 3660 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3661 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3662 return false; 3663 3664 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3665 // independently on 128-bit lanes. 3666 unsigned NumLanes = VT.getSizeInBits()/128; 3667 unsigned NumLaneElts = NumElts/NumLanes; 3668 3669 unsigned Start = 0; 3670 unsigned End = NumLaneElts; 3671 for (unsigned l = 0; l != NumLanes; ++l) { 3672 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2; 3673 i != End; i += 2, ++j) { 3674 int BitI = Mask[i]; 3675 int BitI1 = Mask[i+1]; 3676 if (!isUndefOrEqual(BitI, j)) 3677 return false; 3678 if (V2IsSplat) { 3679 if (isUndefOrEqual(BitI1, NumElts)) 3680 return false; 3681 } else { 3682 if (!isUndefOrEqual(BitI1, j+NumElts)) 3683 return false; 3684 } 3685 } 3686 // Process the next 128 bits. 3687 Start += NumLaneElts; 3688 End += NumLaneElts; 3689 } 3690 return true; 3691} 3692 3693bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3694 SmallVector<int, 8> M; 3695 N->getMask(M); 3696 return ::isUNPCKHMask(M, N->getValueType(0), HasAVX2, V2IsSplat); 3697} 3698 3699/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3700/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3701/// <0, 0, 1, 1> 3702static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3703 int NumElems = VT.getVectorNumElements(); 3704 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3705 return false; 3706 3707 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3708 // FIXME: Need a better way to get rid of this, there's no latency difference 3709 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3710 // the former later. We should also remove the "_undef" special mask. 3711 if (NumElems == 4 && VT.getSizeInBits() == 256) 3712 return false; 3713 3714 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3715 // independently on 128-bit lanes. 3716 unsigned NumLanes = VT.getSizeInBits() / 128; 3717 unsigned NumLaneElts = NumElems / NumLanes; 3718 3719 for (unsigned s = 0; s < NumLanes; ++s) { 3720 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts; 3721 i != NumLaneElts * (s + 1); 3722 i += 2, ++j) { 3723 int BitI = Mask[i]; 3724 int BitI1 = Mask[i+1]; 3725 3726 if (!isUndefOrEqual(BitI, j)) 3727 return false; 3728 if (!isUndefOrEqual(BitI1, j)) 3729 return false; 3730 } 3731 } 3732 3733 return true; 3734} 3735 3736bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3737 SmallVector<int, 8> M; 3738 N->getMask(M); 3739 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3740} 3741 3742/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3743/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3744/// <2, 2, 3, 3> 3745static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3746 int NumElems = VT.getVectorNumElements(); 3747 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3748 return false; 3749 3750 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3751 int BitI = Mask[i]; 3752 int BitI1 = Mask[i+1]; 3753 if (!isUndefOrEqual(BitI, j)) 3754 return false; 3755 if (!isUndefOrEqual(BitI1, j)) 3756 return false; 3757 } 3758 return true; 3759} 3760 3761bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3762 SmallVector<int, 8> M; 3763 N->getMask(M); 3764 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3765} 3766 3767/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3768/// specifies a shuffle of elements that is suitable for input to MOVSS, 3769/// MOVSD, and MOVD, i.e. setting the lowest element. 3770static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3771 if (VT.getVectorElementType().getSizeInBits() < 32) 3772 return false; 3773 3774 int NumElts = VT.getVectorNumElements(); 3775 3776 if (!isUndefOrEqual(Mask[0], NumElts)) 3777 return false; 3778 3779 for (int i = 1; i < NumElts; ++i) 3780 if (!isUndefOrEqual(Mask[i], i)) 3781 return false; 3782 3783 return true; 3784} 3785 3786bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3787 SmallVector<int, 8> M; 3788 N->getMask(M); 3789 return ::isMOVLMask(M, N->getValueType(0)); 3790} 3791 3792/// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered 3793/// as permutations between 128-bit chunks or halves. As an example: this 3794/// shuffle bellow: 3795/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3796/// The first half comes from the second half of V1 and the second half from the 3797/// the second half of V2. 3798static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3799 const X86Subtarget *Subtarget) { 3800 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3801 return false; 3802 3803 // The shuffle result is divided into half A and half B. In total the two 3804 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3805 // B must come from C, D, E or F. 3806 int HalfSize = VT.getVectorNumElements()/2; 3807 bool MatchA = false, MatchB = false; 3808 3809 // Check if A comes from one of C, D, E, F. 3810 for (int Half = 0; Half < 4; ++Half) { 3811 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3812 MatchA = true; 3813 break; 3814 } 3815 } 3816 3817 // Check if B comes from one of C, D, E, F. 3818 for (int Half = 0; Half < 4; ++Half) { 3819 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3820 MatchB = true; 3821 break; 3822 } 3823 } 3824 3825 return MatchA && MatchB; 3826} 3827 3828/// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle 3829/// the specified VECTOR_MASK mask with VPERM2F128 instructions. 3830static unsigned getShuffleVPERM2F128Immediate(SDNode *N) { 3831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3832 EVT VT = SVOp->getValueType(0); 3833 3834 int HalfSize = VT.getVectorNumElements()/2; 3835 3836 int FstHalf = 0, SndHalf = 0; 3837 for (int i = 0; i < HalfSize; ++i) { 3838 if (SVOp->getMaskElt(i) > 0) { 3839 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3840 break; 3841 } 3842 } 3843 for (int i = HalfSize; i < HalfSize*2; ++i) { 3844 if (SVOp->getMaskElt(i) > 0) { 3845 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3846 break; 3847 } 3848 } 3849 3850 return (FstHalf | (SndHalf << 4)); 3851} 3852 3853/// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand 3854/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3855/// Note that VPERMIL mask matching is different depending whether theunderlying 3856/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3857/// to the same elements of the low, but to the higher half of the source. 3858/// In VPERMILPD the two lanes could be shuffled independently of each other 3859/// with the same restriction that lanes can't be crossed. 3860static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT, 3861 const X86Subtarget *Subtarget) { 3862 int NumElts = VT.getVectorNumElements(); 3863 int NumLanes = VT.getSizeInBits()/128; 3864 3865 if (!Subtarget->hasAVX()) 3866 return false; 3867 3868 // Only match 256-bit with 64-bit types 3869 if (VT.getSizeInBits() != 256 || NumElts != 4) 3870 return false; 3871 3872 // The mask on the high lane is independent of the low. Both can match 3873 // any element in inside its own lane, but can't cross. 3874 int LaneSize = NumElts/NumLanes; 3875 for (int l = 0; l < NumLanes; ++l) 3876 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3877 int LaneStart = l*LaneSize; 3878 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize)) 3879 return false; 3880 } 3881 3882 return true; 3883} 3884 3885/// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand 3886/// specifies a shuffle of elements that is suitable for input to VPERMILPS*. 3887/// Note that VPERMIL mask matching is different depending whether theunderlying 3888/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3889/// to the same elements of the low, but to the higher half of the source. 3890/// In VPERMILPD the two lanes could be shuffled independently of each other 3891/// with the same restriction that lanes can't be crossed. 3892static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT, 3893 const X86Subtarget *Subtarget) { 3894 unsigned NumElts = VT.getVectorNumElements(); 3895 unsigned NumLanes = VT.getSizeInBits()/128; 3896 3897 if (!Subtarget->hasAVX()) 3898 return false; 3899 3900 // Only match 256-bit with 32-bit types 3901 if (VT.getSizeInBits() != 256 || NumElts != 8) 3902 return false; 3903 3904 // The mask on the high lane should be the same as the low. Actually, 3905 // they can differ if any of the corresponding index in a lane is undef 3906 // and the other stays in range. 3907 int LaneSize = NumElts/NumLanes; 3908 for (int i = 0; i < LaneSize; ++i) { 3909 int HighElt = i+LaneSize; 3910 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts); 3911 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize); 3912 3913 if (!HighValid || !LowValid) 3914 return false; 3915 if (Mask[i] < 0 || Mask[HighElt] < 0) 3916 continue; 3917 if (Mask[HighElt]-Mask[i] != LaneSize) 3918 return false; 3919 } 3920 3921 return true; 3922} 3923 3924/// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle 3925/// the specified VECTOR_MASK mask with VPERMILPS* instructions. 3926static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { 3927 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3928 EVT VT = SVOp->getValueType(0); 3929 3930 int NumElts = VT.getVectorNumElements(); 3931 int NumLanes = VT.getSizeInBits()/128; 3932 int LaneSize = NumElts/NumLanes; 3933 3934 // Although the mask is equal for both lanes do it twice to get the cases 3935 // where a mask will match because the same mask element is undef on the 3936 // first half but valid on the second. This would get pathological cases 3937 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3938 unsigned Mask = 0; 3939 for (int l = 0; l < NumLanes; ++l) { 3940 for (int i = 0; i < LaneSize; ++i) { 3941 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize)); 3942 if (MaskElt < 0) 3943 continue; 3944 if (MaskElt >= LaneSize) 3945 MaskElt -= LaneSize; 3946 Mask |= MaskElt << (i*2); 3947 } 3948 } 3949 3950 return Mask; 3951} 3952 3953/// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle 3954/// the specified VECTOR_MASK mask with VPERMILPD* instructions. 3955static unsigned getShuffleVPERMILPDImmediate(SDNode *N) { 3956 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3957 EVT VT = SVOp->getValueType(0); 3958 3959 int NumElts = VT.getVectorNumElements(); 3960 int NumLanes = VT.getSizeInBits()/128; 3961 3962 unsigned Mask = 0; 3963 int LaneSize = NumElts/NumLanes; 3964 for (int l = 0; l < NumLanes; ++l) 3965 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3966 int MaskElt = SVOp->getMaskElt(i); 3967 if (MaskElt < 0) 3968 continue; 3969 Mask |= (MaskElt-l*LaneSize) << i; 3970 } 3971 3972 return Mask; 3973} 3974 3975/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3976/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3977/// element of vector 2 and the other elements to come from vector 1 in order. 3978static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3979 bool V2IsSplat = false, bool V2IsUndef = false) { 3980 int NumOps = VT.getVectorNumElements(); 3981 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3982 return false; 3983 3984 if (!isUndefOrEqual(Mask[0], 0)) 3985 return false; 3986 3987 for (int i = 1; i < NumOps; ++i) 3988 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3989 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3990 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3991 return false; 3992 3993 return true; 3994} 3995 3996static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3997 bool V2IsUndef = false) { 3998 SmallVector<int, 8> M; 3999 N->getMask(M); 4000 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 4001} 4002 4003/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 4004/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 4005/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 4006bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 4007 const X86Subtarget *Subtarget) { 4008 if (!Subtarget->hasSSE3orAVX()) 4009 return false; 4010 4011 // The second vector must be undef 4012 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 4013 return false; 4014 4015 EVT VT = N->getValueType(0); 4016 unsigned NumElems = VT.getVectorNumElements(); 4017 4018 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 4019 (VT.getSizeInBits() == 256 && NumElems != 8)) 4020 return false; 4021 4022 // "i+1" is the value the indexed mask element must have 4023 for (unsigned i = 0; i < NumElems; i += 2) 4024 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 4025 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 4026 return false; 4027 4028 return true; 4029} 4030 4031/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 4032/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 4033/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 4034bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 4035 const X86Subtarget *Subtarget) { 4036 if (!Subtarget->hasSSE3orAVX()) 4037 return false; 4038 4039 // The second vector must be undef 4040 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 4041 return false; 4042 4043 EVT VT = N->getValueType(0); 4044 unsigned NumElems = VT.getVectorNumElements(); 4045 4046 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 4047 (VT.getSizeInBits() == 256 && NumElems != 8)) 4048 return false; 4049 4050 // "i" is the value the indexed mask element must have 4051 for (unsigned i = 0; i < NumElems; i += 2) 4052 if (!isUndefOrEqual(N->getMaskElt(i), i) || 4053 !isUndefOrEqual(N->getMaskElt(i+1), i)) 4054 return false; 4055 4056 return true; 4057} 4058 4059/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 4060/// specifies a shuffle of elements that is suitable for input to 256-bit 4061/// version of MOVDDUP. 4062static bool isMOVDDUPYMask(ShuffleVectorSDNode *N, 4063 const X86Subtarget *Subtarget) { 4064 EVT VT = N->getValueType(0); 4065 int NumElts = VT.getVectorNumElements(); 4066 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF; 4067 4068 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 || 4069 !V2IsUndef || NumElts != 4) 4070 return false; 4071 4072 for (int i = 0; i != NumElts/2; ++i) 4073 if (!isUndefOrEqual(N->getMaskElt(i), 0)) 4074 return false; 4075 for (int i = NumElts/2; i != NumElts; ++i) 4076 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2)) 4077 return false; 4078 return true; 4079} 4080 4081/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 4082/// specifies a shuffle of elements that is suitable for input to 128-bit 4083/// version of MOVDDUP. 4084bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 4085 EVT VT = N->getValueType(0); 4086 4087 if (VT.getSizeInBits() != 128) 4088 return false; 4089 4090 int e = VT.getVectorNumElements() / 2; 4091 for (int i = 0; i < e; ++i) 4092 if (!isUndefOrEqual(N->getMaskElt(i), i)) 4093 return false; 4094 for (int i = 0; i < e; ++i) 4095 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 4096 return false; 4097 return true; 4098} 4099 4100/// isVEXTRACTF128Index - Return true if the specified 4101/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 4102/// suitable for input to VEXTRACTF128. 4103bool X86::isVEXTRACTF128Index(SDNode *N) { 4104 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4105 return false; 4106 4107 // The index should be aligned on a 128-bit boundary. 4108 uint64_t Index = 4109 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4110 4111 unsigned VL = N->getValueType(0).getVectorNumElements(); 4112 unsigned VBits = N->getValueType(0).getSizeInBits(); 4113 unsigned ElSize = VBits / VL; 4114 bool Result = (Index * ElSize) % 128 == 0; 4115 4116 return Result; 4117} 4118 4119/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 4120/// operand specifies a subvector insert that is suitable for input to 4121/// VINSERTF128. 4122bool X86::isVINSERTF128Index(SDNode *N) { 4123 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4124 return false; 4125 4126 // The index should be aligned on a 128-bit boundary. 4127 uint64_t Index = 4128 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4129 4130 unsigned VL = N->getValueType(0).getVectorNumElements(); 4131 unsigned VBits = N->getValueType(0).getSizeInBits(); 4132 unsigned ElSize = VBits / VL; 4133 bool Result = (Index * ElSize) % 128 == 0; 4134 4135 return Result; 4136} 4137 4138/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 4139/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 4140unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 4141 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4142 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 4143 4144 unsigned Shift = (NumOperands == 4) ? 2 : 1; 4145 unsigned Mask = 0; 4146 for (int i = 0; i < NumOperands; ++i) { 4147 int Val = SVOp->getMaskElt(NumOperands-i-1); 4148 if (Val < 0) Val = 0; 4149 if (Val >= NumOperands) Val -= NumOperands; 4150 Mask |= Val; 4151 if (i != NumOperands - 1) 4152 Mask <<= Shift; 4153 } 4154 return Mask; 4155} 4156 4157/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4158/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4159unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 4160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4161 unsigned Mask = 0; 4162 // 8 nodes, but we only care about the last 4. 4163 for (unsigned i = 7; i >= 4; --i) { 4164 int Val = SVOp->getMaskElt(i); 4165 if (Val >= 0) 4166 Mask |= (Val - 4); 4167 if (i != 4) 4168 Mask <<= 2; 4169 } 4170 return Mask; 4171} 4172 4173/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4174/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4175unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 4176 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4177 unsigned Mask = 0; 4178 // 8 nodes, but we only care about the first 4. 4179 for (int i = 3; i >= 0; --i) { 4180 int Val = SVOp->getMaskElt(i); 4181 if (Val >= 0) 4182 Mask |= Val; 4183 if (i != 0) 4184 Mask <<= 2; 4185 } 4186 return Mask; 4187} 4188 4189/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4190/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4191unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 4192 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4193 EVT VVT = N->getValueType(0); 4194 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 4195 int Val = 0; 4196 4197 unsigned i, e; 4198 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 4199 Val = SVOp->getMaskElt(i); 4200 if (Val >= 0) 4201 break; 4202 } 4203 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4204 return (Val - i) * EltSize; 4205} 4206 4207/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4208/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4209/// instructions. 4210unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4211 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4212 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4213 4214 uint64_t Index = 4215 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4216 4217 EVT VecVT = N->getOperand(0).getValueType(); 4218 EVT ElVT = VecVT.getVectorElementType(); 4219 4220 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4221 return Index / NumElemsPerChunk; 4222} 4223 4224/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4225/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4226/// instructions. 4227unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4228 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4229 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4230 4231 uint64_t Index = 4232 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4233 4234 EVT VecVT = N->getValueType(0); 4235 EVT ElVT = VecVT.getVectorElementType(); 4236 4237 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4238 return Index / NumElemsPerChunk; 4239} 4240 4241/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4242/// constant +0.0. 4243bool X86::isZeroNode(SDValue Elt) { 4244 return ((isa<ConstantSDNode>(Elt) && 4245 cast<ConstantSDNode>(Elt)->isNullValue()) || 4246 (isa<ConstantFPSDNode>(Elt) && 4247 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4248} 4249 4250/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4251/// their permute mask. 4252static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4253 SelectionDAG &DAG) { 4254 EVT VT = SVOp->getValueType(0); 4255 unsigned NumElems = VT.getVectorNumElements(); 4256 SmallVector<int, 8> MaskVec; 4257 4258 for (unsigned i = 0; i != NumElems; ++i) { 4259 int idx = SVOp->getMaskElt(i); 4260 if (idx < 0) 4261 MaskVec.push_back(idx); 4262 else if (idx < (int)NumElems) 4263 MaskVec.push_back(idx + NumElems); 4264 else 4265 MaskVec.push_back(idx - NumElems); 4266 } 4267 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4268 SVOp->getOperand(0), &MaskVec[0]); 4269} 4270 4271/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4272/// match movhlps. The lower half elements should come from upper half of 4273/// V1 (and in order), and the upper half elements should come from the upper 4274/// half of V2 (and in order). 4275static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4276 EVT VT = Op->getValueType(0); 4277 if (VT.getSizeInBits() != 128) 4278 return false; 4279 if (VT.getVectorNumElements() != 4) 4280 return false; 4281 for (unsigned i = 0, e = 2; i != e; ++i) 4282 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4283 return false; 4284 for (unsigned i = 2; i != 4; ++i) 4285 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4286 return false; 4287 return true; 4288} 4289 4290/// isScalarLoadToVector - Returns true if the node is a scalar load that 4291/// is promoted to a vector. It also returns the LoadSDNode by reference if 4292/// required. 4293static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4294 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4295 return false; 4296 N = N->getOperand(0).getNode(); 4297 if (!ISD::isNON_EXTLoad(N)) 4298 return false; 4299 if (LD) 4300 *LD = cast<LoadSDNode>(N); 4301 return true; 4302} 4303 4304// Test whether the given value is a vector value which will be legalized 4305// into a load. 4306static bool WillBeConstantPoolLoad(SDNode *N) { 4307 if (N->getOpcode() != ISD::BUILD_VECTOR) 4308 return false; 4309 4310 // Check for any non-constant elements. 4311 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4312 switch (N->getOperand(i).getNode()->getOpcode()) { 4313 case ISD::UNDEF: 4314 case ISD::ConstantFP: 4315 case ISD::Constant: 4316 break; 4317 default: 4318 return false; 4319 } 4320 4321 // Vectors of all-zeros and all-ones are materialized with special 4322 // instructions rather than being loaded. 4323 return !ISD::isBuildVectorAllZeros(N) && 4324 !ISD::isBuildVectorAllOnes(N); 4325} 4326 4327/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4328/// match movlp{s|d}. The lower half elements should come from lower half of 4329/// V1 (and in order), and the upper half elements should come from the upper 4330/// half of V2 (and in order). And since V1 will become the source of the 4331/// MOVLP, it must be either a vector load or a scalar load to vector. 4332static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4333 ShuffleVectorSDNode *Op) { 4334 EVT VT = Op->getValueType(0); 4335 if (VT.getSizeInBits() != 128) 4336 return false; 4337 4338 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4339 return false; 4340 // Is V2 is a vector load, don't do this transformation. We will try to use 4341 // load folding shufps op. 4342 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4343 return false; 4344 4345 unsigned NumElems = VT.getVectorNumElements(); 4346 4347 if (NumElems != 2 && NumElems != 4) 4348 return false; 4349 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4350 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4351 return false; 4352 for (unsigned i = NumElems/2; i != NumElems; ++i) 4353 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4354 return false; 4355 return true; 4356} 4357 4358/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4359/// all the same. 4360static bool isSplatVector(SDNode *N) { 4361 if (N->getOpcode() != ISD::BUILD_VECTOR) 4362 return false; 4363 4364 SDValue SplatValue = N->getOperand(0); 4365 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4366 if (N->getOperand(i) != SplatValue) 4367 return false; 4368 return true; 4369} 4370 4371/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4372/// to an zero vector. 4373/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4374static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4375 SDValue V1 = N->getOperand(0); 4376 SDValue V2 = N->getOperand(1); 4377 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4378 for (unsigned i = 0; i != NumElems; ++i) { 4379 int Idx = N->getMaskElt(i); 4380 if (Idx >= (int)NumElems) { 4381 unsigned Opc = V2.getOpcode(); 4382 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4383 continue; 4384 if (Opc != ISD::BUILD_VECTOR || 4385 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4386 return false; 4387 } else if (Idx >= 0) { 4388 unsigned Opc = V1.getOpcode(); 4389 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4390 continue; 4391 if (Opc != ISD::BUILD_VECTOR || 4392 !X86::isZeroNode(V1.getOperand(Idx))) 4393 return false; 4394 } 4395 } 4396 return true; 4397} 4398 4399/// getZeroVector - Returns a vector of specified type with all zero elements. 4400/// 4401static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG, 4402 DebugLoc dl) { 4403 assert(VT.isVector() && "Expected a vector type"); 4404 4405 // Always build SSE zero vectors as <4 x i32> bitcasted 4406 // to their dest type. This ensures they get CSE'd. 4407 SDValue Vec; 4408 if (VT.getSizeInBits() == 128) { // SSE 4409 if (HasXMMInt) { // SSE2 4410 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4411 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4412 } else { // SSE1 4413 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4414 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4415 } 4416 } else if (VT.getSizeInBits() == 256) { // AVX 4417 // 256-bit logic and arithmetic instructions in AVX are 4418 // all floating-point, no support for integer ops. Default 4419 // to emitting fp zeroed vectors then. 4420 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4421 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4422 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4423 } 4424 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4425} 4426 4427/// getOnesVector - Returns a vector of specified type with all bits set. 4428/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4429/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4430/// Then bitcast to their original type, ensuring they get CSE'd. 4431static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4432 DebugLoc dl) { 4433 assert(VT.isVector() && "Expected a vector type"); 4434 assert((VT.is128BitVector() || VT.is256BitVector()) 4435 && "Expected a 128-bit or 256-bit vector type"); 4436 4437 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4438 SDValue Vec; 4439 if (VT.getSizeInBits() == 256) { 4440 if (HasAVX2) { // AVX2 4441 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4442 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4443 } else { // AVX 4444 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4445 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4446 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4447 Vec = Insert128BitVector(InsV, Vec, 4448 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4449 } 4450 } else { 4451 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4452 } 4453 4454 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4455} 4456 4457/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4458/// that point to V2 points to its first element. 4459static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4460 EVT VT = SVOp->getValueType(0); 4461 unsigned NumElems = VT.getVectorNumElements(); 4462 4463 bool Changed = false; 4464 SmallVector<int, 8> MaskVec; 4465 SVOp->getMask(MaskVec); 4466 4467 for (unsigned i = 0; i != NumElems; ++i) { 4468 if (MaskVec[i] > (int)NumElems) { 4469 MaskVec[i] = NumElems; 4470 Changed = true; 4471 } 4472 } 4473 if (Changed) 4474 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4475 SVOp->getOperand(1), &MaskVec[0]); 4476 return SDValue(SVOp, 0); 4477} 4478 4479/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4480/// operation of specified width. 4481static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4482 SDValue V2) { 4483 unsigned NumElems = VT.getVectorNumElements(); 4484 SmallVector<int, 8> Mask; 4485 Mask.push_back(NumElems); 4486 for (unsigned i = 1; i != NumElems; ++i) 4487 Mask.push_back(i); 4488 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4489} 4490 4491/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4492static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4493 SDValue V2) { 4494 unsigned NumElems = VT.getVectorNumElements(); 4495 SmallVector<int, 8> Mask; 4496 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4497 Mask.push_back(i); 4498 Mask.push_back(i + NumElems); 4499 } 4500 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4501} 4502 4503/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4504static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4505 SDValue V2) { 4506 unsigned NumElems = VT.getVectorNumElements(); 4507 unsigned Half = NumElems/2; 4508 SmallVector<int, 8> Mask; 4509 for (unsigned i = 0; i != Half; ++i) { 4510 Mask.push_back(i + Half); 4511 Mask.push_back(i + NumElems + Half); 4512 } 4513 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4514} 4515 4516// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4517// a generic shuffle instruction because the target has no such instructions. 4518// Generate shuffles which repeat i16 and i8 several times until they can be 4519// represented by v4f32 and then be manipulated by target suported shuffles. 4520static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4521 EVT VT = V.getValueType(); 4522 int NumElems = VT.getVectorNumElements(); 4523 DebugLoc dl = V.getDebugLoc(); 4524 4525 while (NumElems > 4) { 4526 if (EltNo < NumElems/2) { 4527 V = getUnpackl(DAG, dl, VT, V, V); 4528 } else { 4529 V = getUnpackh(DAG, dl, VT, V, V); 4530 EltNo -= NumElems/2; 4531 } 4532 NumElems >>= 1; 4533 } 4534 return V; 4535} 4536 4537/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4538static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4539 EVT VT = V.getValueType(); 4540 DebugLoc dl = V.getDebugLoc(); 4541 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4542 && "Vector size not supported"); 4543 4544 if (VT.getSizeInBits() == 128) { 4545 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4546 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4547 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4548 &SplatMask[0]); 4549 } else { 4550 // To use VPERMILPS to splat scalars, the second half of indicies must 4551 // refer to the higher part, which is a duplication of the lower one, 4552 // because VPERMILPS can only handle in-lane permutations. 4553 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4554 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4555 4556 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4557 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4558 &SplatMask[0]); 4559 } 4560 4561 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4562} 4563 4564/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4565static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4566 EVT SrcVT = SV->getValueType(0); 4567 SDValue V1 = SV->getOperand(0); 4568 DebugLoc dl = SV->getDebugLoc(); 4569 4570 int EltNo = SV->getSplatIndex(); 4571 int NumElems = SrcVT.getVectorNumElements(); 4572 unsigned Size = SrcVT.getSizeInBits(); 4573 4574 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4575 "Unknown how to promote splat for type"); 4576 4577 // Extract the 128-bit part containing the splat element and update 4578 // the splat element index when it refers to the higher register. 4579 if (Size == 256) { 4580 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0; 4581 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4582 if (Idx > 0) 4583 EltNo -= NumElems/2; 4584 } 4585 4586 // All i16 and i8 vector types can't be used directly by a generic shuffle 4587 // instruction because the target has no such instruction. Generate shuffles 4588 // which repeat i16 and i8 several times until they fit in i32, and then can 4589 // be manipulated by target suported shuffles. 4590 EVT EltVT = SrcVT.getVectorElementType(); 4591 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4592 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4593 4594 // Recreate the 256-bit vector and place the same 128-bit vector 4595 // into the low and high part. This is necessary because we want 4596 // to use VPERM* to shuffle the vectors 4597 if (Size == 256) { 4598 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4599 DAG.getConstant(0, MVT::i32), DAG, dl); 4600 V1 = Insert128BitVector(InsV, V1, 4601 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4602 } 4603 4604 return getLegalSplat(DAG, V1, EltNo); 4605} 4606 4607/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4608/// vector of zero or undef vector. This produces a shuffle where the low 4609/// element of V2 is swizzled into the zero/undef vector, landing at element 4610/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4611static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4612 bool isZero, bool HasXMMInt, 4613 SelectionDAG &DAG) { 4614 EVT VT = V2.getValueType(); 4615 SDValue V1 = isZero 4616 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4617 unsigned NumElems = VT.getVectorNumElements(); 4618 SmallVector<int, 16> MaskVec; 4619 for (unsigned i = 0; i != NumElems; ++i) 4620 // If this is the insertion idx, put the low elt of V2 here. 4621 MaskVec.push_back(i == Idx ? NumElems : i); 4622 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4623} 4624 4625/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4626/// element of the result of the vector shuffle. 4627static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4628 unsigned Depth) { 4629 if (Depth == 6) 4630 return SDValue(); // Limit search depth. 4631 4632 SDValue V = SDValue(N, 0); 4633 EVT VT = V.getValueType(); 4634 unsigned Opcode = V.getOpcode(); 4635 4636 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4637 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4638 Index = SV->getMaskElt(Index); 4639 4640 if (Index < 0) 4641 return DAG.getUNDEF(VT.getVectorElementType()); 4642 4643 int NumElems = VT.getVectorNumElements(); 4644 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4645 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4646 } 4647 4648 // Recurse into target specific vector shuffles to find scalars. 4649 if (isTargetShuffle(Opcode)) { 4650 int NumElems = VT.getVectorNumElements(); 4651 SmallVector<unsigned, 16> ShuffleMask; 4652 SDValue ImmN; 4653 4654 switch(Opcode) { 4655 case X86ISD::SHUFPS: 4656 case X86ISD::SHUFPD: 4657 ImmN = N->getOperand(N->getNumOperands()-1); 4658 DecodeSHUFPSMask(NumElems, 4659 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4660 ShuffleMask); 4661 break; 4662 case X86ISD::PUNPCKHBW: 4663 case X86ISD::PUNPCKHWD: 4664 case X86ISD::PUNPCKHDQ: 4665 case X86ISD::PUNPCKHQDQ: 4666 case X86ISD::VPUNPCKHBWY: 4667 case X86ISD::VPUNPCKHWDY: 4668 case X86ISD::VPUNPCKHDQY: 4669 case X86ISD::VPUNPCKHQDQY: 4670 DecodePUNPCKHMask(NumElems, ShuffleMask); 4671 break; 4672 case X86ISD::UNPCKHPS: 4673 case X86ISD::UNPCKHPD: 4674 case X86ISD::VUNPCKHPSY: 4675 case X86ISD::VUNPCKHPDY: 4676 DecodeUNPCKHPMask(VT, ShuffleMask); 4677 break; 4678 case X86ISD::PUNPCKLBW: 4679 case X86ISD::PUNPCKLWD: 4680 case X86ISD::PUNPCKLDQ: 4681 case X86ISD::PUNPCKLQDQ: 4682 case X86ISD::VPUNPCKLBWY: 4683 case X86ISD::VPUNPCKLWDY: 4684 case X86ISD::VPUNPCKLDQY: 4685 case X86ISD::VPUNPCKLQDQY: 4686 DecodePUNPCKLMask(VT, ShuffleMask); 4687 break; 4688 case X86ISD::UNPCKLPS: 4689 case X86ISD::UNPCKLPD: 4690 case X86ISD::VUNPCKLPSY: 4691 case X86ISD::VUNPCKLPDY: 4692 DecodeUNPCKLPMask(VT, ShuffleMask); 4693 break; 4694 case X86ISD::MOVHLPS: 4695 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4696 break; 4697 case X86ISD::MOVLHPS: 4698 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4699 break; 4700 case X86ISD::PSHUFD: 4701 ImmN = N->getOperand(N->getNumOperands()-1); 4702 DecodePSHUFMask(NumElems, 4703 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4704 ShuffleMask); 4705 break; 4706 case X86ISD::PSHUFHW: 4707 ImmN = N->getOperand(N->getNumOperands()-1); 4708 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4709 ShuffleMask); 4710 break; 4711 case X86ISD::PSHUFLW: 4712 ImmN = N->getOperand(N->getNumOperands()-1); 4713 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4714 ShuffleMask); 4715 break; 4716 case X86ISD::MOVSS: 4717 case X86ISD::MOVSD: { 4718 // The index 0 always comes from the first element of the second source, 4719 // this is why MOVSS and MOVSD are used in the first place. The other 4720 // elements come from the other positions of the first source vector. 4721 unsigned OpNum = (Index == 0) ? 1 : 0; 4722 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4723 Depth+1); 4724 } 4725 case X86ISD::VPERMILPS: 4726 ImmN = N->getOperand(N->getNumOperands()-1); 4727 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4728 ShuffleMask); 4729 break; 4730 case X86ISD::VPERMILPSY: 4731 ImmN = N->getOperand(N->getNumOperands()-1); 4732 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4733 ShuffleMask); 4734 break; 4735 case X86ISD::VPERMILPD: 4736 ImmN = N->getOperand(N->getNumOperands()-1); 4737 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4738 ShuffleMask); 4739 break; 4740 case X86ISD::VPERMILPDY: 4741 ImmN = N->getOperand(N->getNumOperands()-1); 4742 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4743 ShuffleMask); 4744 break; 4745 case X86ISD::VPERM2F128: 4746 ImmN = N->getOperand(N->getNumOperands()-1); 4747 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4748 ShuffleMask); 4749 break; 4750 case X86ISD::MOVDDUP: 4751 case X86ISD::MOVLHPD: 4752 case X86ISD::MOVLPD: 4753 case X86ISD::MOVLPS: 4754 case X86ISD::MOVSHDUP: 4755 case X86ISD::MOVSLDUP: 4756 case X86ISD::PALIGN: 4757 return SDValue(); // Not yet implemented. 4758 default: 4759 assert(0 && "unknown target shuffle node"); 4760 return SDValue(); 4761 } 4762 4763 Index = ShuffleMask[Index]; 4764 if (Index < 0) 4765 return DAG.getUNDEF(VT.getVectorElementType()); 4766 4767 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4768 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4769 Depth+1); 4770 } 4771 4772 // Actual nodes that may contain scalar elements 4773 if (Opcode == ISD::BITCAST) { 4774 V = V.getOperand(0); 4775 EVT SrcVT = V.getValueType(); 4776 unsigned NumElems = VT.getVectorNumElements(); 4777 4778 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4779 return SDValue(); 4780 } 4781 4782 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4783 return (Index == 0) ? V.getOperand(0) 4784 : DAG.getUNDEF(VT.getVectorElementType()); 4785 4786 if (V.getOpcode() == ISD::BUILD_VECTOR) 4787 return V.getOperand(Index); 4788 4789 return SDValue(); 4790} 4791 4792/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4793/// shuffle operation which come from a consecutively from a zero. The 4794/// search can start in two different directions, from left or right. 4795static 4796unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4797 bool ZerosFromLeft, SelectionDAG &DAG) { 4798 int i = 0; 4799 4800 while (i < NumElems) { 4801 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4802 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4803 if (!(Elt.getNode() && 4804 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4805 break; 4806 ++i; 4807 } 4808 4809 return i; 4810} 4811 4812/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4813/// MaskE correspond consecutively to elements from one of the vector operands, 4814/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4815static 4816bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4817 int OpIdx, int NumElems, unsigned &OpNum) { 4818 bool SeenV1 = false; 4819 bool SeenV2 = false; 4820 4821 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4822 int Idx = SVOp->getMaskElt(i); 4823 // Ignore undef indicies 4824 if (Idx < 0) 4825 continue; 4826 4827 if (Idx < NumElems) 4828 SeenV1 = true; 4829 else 4830 SeenV2 = true; 4831 4832 // Only accept consecutive elements from the same vector 4833 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4834 return false; 4835 } 4836 4837 OpNum = SeenV1 ? 0 : 1; 4838 return true; 4839} 4840 4841/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4842/// logical left shift of a vector. 4843static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4844 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4845 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4846 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4847 false /* check zeros from right */, DAG); 4848 unsigned OpSrc; 4849 4850 if (!NumZeros) 4851 return false; 4852 4853 // Considering the elements in the mask that are not consecutive zeros, 4854 // check if they consecutively come from only one of the source vectors. 4855 // 4856 // V1 = {X, A, B, C} 0 4857 // \ \ \ / 4858 // vector_shuffle V1, V2 <1, 2, 3, X> 4859 // 4860 if (!isShuffleMaskConsecutive(SVOp, 4861 0, // Mask Start Index 4862 NumElems-NumZeros-1, // Mask End Index 4863 NumZeros, // Where to start looking in the src vector 4864 NumElems, // Number of elements in vector 4865 OpSrc)) // Which source operand ? 4866 return false; 4867 4868 isLeft = false; 4869 ShAmt = NumZeros; 4870 ShVal = SVOp->getOperand(OpSrc); 4871 return true; 4872} 4873 4874/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4875/// logical left shift of a vector. 4876static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4877 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4878 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4879 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4880 true /* check zeros from left */, DAG); 4881 unsigned OpSrc; 4882 4883 if (!NumZeros) 4884 return false; 4885 4886 // Considering the elements in the mask that are not consecutive zeros, 4887 // check if they consecutively come from only one of the source vectors. 4888 // 4889 // 0 { A, B, X, X } = V2 4890 // / \ / / 4891 // vector_shuffle V1, V2 <X, X, 4, 5> 4892 // 4893 if (!isShuffleMaskConsecutive(SVOp, 4894 NumZeros, // Mask Start Index 4895 NumElems-1, // Mask End Index 4896 0, // Where to start looking in the src vector 4897 NumElems, // Number of elements in vector 4898 OpSrc)) // Which source operand ? 4899 return false; 4900 4901 isLeft = true; 4902 ShAmt = NumZeros; 4903 ShVal = SVOp->getOperand(OpSrc); 4904 return true; 4905} 4906 4907/// isVectorShift - Returns true if the shuffle can be implemented as a 4908/// logical left or right shift of a vector. 4909static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4910 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4911 // Although the logic below support any bitwidth size, there are no 4912 // shift instructions which handle more than 128-bit vectors. 4913 if (SVOp->getValueType(0).getSizeInBits() > 128) 4914 return false; 4915 4916 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4917 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4918 return true; 4919 4920 return false; 4921} 4922 4923/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4924/// 4925static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4926 unsigned NumNonZero, unsigned NumZero, 4927 SelectionDAG &DAG, 4928 const TargetLowering &TLI) { 4929 if (NumNonZero > 8) 4930 return SDValue(); 4931 4932 DebugLoc dl = Op.getDebugLoc(); 4933 SDValue V(0, 0); 4934 bool First = true; 4935 for (unsigned i = 0; i < 16; ++i) { 4936 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4937 if (ThisIsNonZero && First) { 4938 if (NumZero) 4939 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4940 else 4941 V = DAG.getUNDEF(MVT::v8i16); 4942 First = false; 4943 } 4944 4945 if ((i & 1) != 0) { 4946 SDValue ThisElt(0, 0), LastElt(0, 0); 4947 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4948 if (LastIsNonZero) { 4949 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4950 MVT::i16, Op.getOperand(i-1)); 4951 } 4952 if (ThisIsNonZero) { 4953 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4954 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4955 ThisElt, DAG.getConstant(8, MVT::i8)); 4956 if (LastIsNonZero) 4957 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4958 } else 4959 ThisElt = LastElt; 4960 4961 if (ThisElt.getNode()) 4962 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4963 DAG.getIntPtrConstant(i/2)); 4964 } 4965 } 4966 4967 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4968} 4969 4970/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4971/// 4972static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4973 unsigned NumNonZero, unsigned NumZero, 4974 SelectionDAG &DAG, 4975 const TargetLowering &TLI) { 4976 if (NumNonZero > 4) 4977 return SDValue(); 4978 4979 DebugLoc dl = Op.getDebugLoc(); 4980 SDValue V(0, 0); 4981 bool First = true; 4982 for (unsigned i = 0; i < 8; ++i) { 4983 bool isNonZero = (NonZeros & (1 << i)) != 0; 4984 if (isNonZero) { 4985 if (First) { 4986 if (NumZero) 4987 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4988 else 4989 V = DAG.getUNDEF(MVT::v8i16); 4990 First = false; 4991 } 4992 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4993 MVT::v8i16, V, Op.getOperand(i), 4994 DAG.getIntPtrConstant(i)); 4995 } 4996 } 4997 4998 return V; 4999} 5000 5001/// getVShift - Return a vector logical shift node. 5002/// 5003static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 5004 unsigned NumBits, SelectionDAG &DAG, 5005 const TargetLowering &TLI, DebugLoc dl) { 5006 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 5007 EVT ShVT = MVT::v2i64; 5008 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 5009 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 5010 return DAG.getNode(ISD::BITCAST, dl, VT, 5011 DAG.getNode(Opc, dl, ShVT, SrcOp, 5012 DAG.getConstant(NumBits, 5013 TLI.getShiftAmountTy(SrcOp.getValueType())))); 5014} 5015 5016SDValue 5017X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 5018 SelectionDAG &DAG) const { 5019 5020 // Check if the scalar load can be widened into a vector load. And if 5021 // the address is "base + cst" see if the cst can be "absorbed" into 5022 // the shuffle mask. 5023 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 5024 SDValue Ptr = LD->getBasePtr(); 5025 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 5026 return SDValue(); 5027 EVT PVT = LD->getValueType(0); 5028 if (PVT != MVT::i32 && PVT != MVT::f32) 5029 return SDValue(); 5030 5031 int FI = -1; 5032 int64_t Offset = 0; 5033 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 5034 FI = FINode->getIndex(); 5035 Offset = 0; 5036 } else if (DAG.isBaseWithConstantOffset(Ptr) && 5037 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 5038 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 5039 Offset = Ptr.getConstantOperandVal(1); 5040 Ptr = Ptr.getOperand(0); 5041 } else { 5042 return SDValue(); 5043 } 5044 5045 // FIXME: 256-bit vector instructions don't require a strict alignment, 5046 // improve this code to support it better. 5047 unsigned RequiredAlign = VT.getSizeInBits()/8; 5048 SDValue Chain = LD->getChain(); 5049 // Make sure the stack object alignment is at least 16 or 32. 5050 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5051 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 5052 if (MFI->isFixedObjectIndex(FI)) { 5053 // Can't change the alignment. FIXME: It's possible to compute 5054 // the exact stack offset and reference FI + adjust offset instead. 5055 // If someone *really* cares about this. That's the way to implement it. 5056 return SDValue(); 5057 } else { 5058 MFI->setObjectAlignment(FI, RequiredAlign); 5059 } 5060 } 5061 5062 // (Offset % 16 or 32) must be multiple of 4. Then address is then 5063 // Ptr + (Offset & ~15). 5064 if (Offset < 0) 5065 return SDValue(); 5066 if ((Offset % RequiredAlign) & 3) 5067 return SDValue(); 5068 int64_t StartOffset = Offset & ~(RequiredAlign-1); 5069 if (StartOffset) 5070 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 5071 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 5072 5073 int EltNo = (Offset - StartOffset) >> 2; 5074 int NumElems = VT.getVectorNumElements(); 5075 5076 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 5077 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 5078 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 5079 LD->getPointerInfo().getWithOffset(StartOffset), 5080 false, false, false, 0); 5081 5082 // Canonicalize it to a v4i32 or v8i32 shuffle. 5083 SmallVector<int, 8> Mask; 5084 for (int i = 0; i < NumElems; ++i) 5085 Mask.push_back(EltNo); 5086 5087 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 5088 return DAG.getNode(ISD::BITCAST, dl, NVT, 5089 DAG.getVectorShuffle(CanonVT, dl, V1, 5090 DAG.getUNDEF(CanonVT),&Mask[0])); 5091 } 5092 5093 return SDValue(); 5094} 5095 5096/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 5097/// vector of type 'VT', see if the elements can be replaced by a single large 5098/// load which has the same value as a build_vector whose operands are 'elts'. 5099/// 5100/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 5101/// 5102/// FIXME: we'd also like to handle the case where the last elements are zero 5103/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 5104/// There's even a handy isZeroNode for that purpose. 5105static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 5106 DebugLoc &DL, SelectionDAG &DAG) { 5107 EVT EltVT = VT.getVectorElementType(); 5108 unsigned NumElems = Elts.size(); 5109 5110 LoadSDNode *LDBase = NULL; 5111 unsigned LastLoadedElt = -1U; 5112 5113 // For each element in the initializer, see if we've found a load or an undef. 5114 // If we don't find an initial load element, or later load elements are 5115 // non-consecutive, bail out. 5116 for (unsigned i = 0; i < NumElems; ++i) { 5117 SDValue Elt = Elts[i]; 5118 5119 if (!Elt.getNode() || 5120 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 5121 return SDValue(); 5122 if (!LDBase) { 5123 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 5124 return SDValue(); 5125 LDBase = cast<LoadSDNode>(Elt.getNode()); 5126 LastLoadedElt = i; 5127 continue; 5128 } 5129 if (Elt.getOpcode() == ISD::UNDEF) 5130 continue; 5131 5132 LoadSDNode *LD = cast<LoadSDNode>(Elt); 5133 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 5134 return SDValue(); 5135 LastLoadedElt = i; 5136 } 5137 5138 // If we have found an entire vector of loads and undefs, then return a large 5139 // load of the entire vector width starting at the base pointer. If we found 5140 // consecutive loads for the low half, generate a vzext_load node. 5141 if (LastLoadedElt == NumElems - 1) { 5142 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 5143 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5144 LDBase->getPointerInfo(), 5145 LDBase->isVolatile(), LDBase->isNonTemporal(), 5146 LDBase->isInvariant(), 0); 5147 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5148 LDBase->getPointerInfo(), 5149 LDBase->isVolatile(), LDBase->isNonTemporal(), 5150 LDBase->isInvariant(), LDBase->getAlignment()); 5151 } else if (NumElems == 4 && LastLoadedElt == 1 && 5152 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 5153 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 5154 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 5155 SDValue ResNode = 5156 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 5157 LDBase->getPointerInfo(), 5158 LDBase->getAlignment(), 5159 false/*isVolatile*/, true/*ReadMem*/, 5160 false/*WriteMem*/); 5161 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 5162 } 5163 return SDValue(); 5164} 5165 5166/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 5167/// a vbroadcast node. We support two patterns: 5168/// 1. A splat BUILD_VECTOR which uses a single scalar load. 5169/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 5170/// a scalar load. 5171/// The scalar load node is returned when a pattern is found, 5172/// or SDValue() otherwise. 5173static SDValue isVectorBroadcast(SDValue &Op, bool hasAVX2) { 5174 EVT VT = Op.getValueType(); 5175 SDValue V = Op; 5176 5177 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5178 V = V.getOperand(0); 5179 5180 //A suspected load to be broadcasted. 5181 SDValue Ld; 5182 5183 switch (V.getOpcode()) { 5184 default: 5185 // Unknown pattern found. 5186 return SDValue(); 5187 5188 case ISD::BUILD_VECTOR: { 5189 // The BUILD_VECTOR node must be a splat. 5190 if (!isSplatVector(V.getNode())) 5191 return SDValue(); 5192 5193 Ld = V.getOperand(0); 5194 5195 // The suspected load node has several users. Make sure that all 5196 // of its users are from the BUILD_VECTOR node. 5197 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 5198 return SDValue(); 5199 break; 5200 } 5201 5202 case ISD::VECTOR_SHUFFLE: { 5203 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5204 5205 // Shuffles must have a splat mask where the first element is 5206 // broadcasted. 5207 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 5208 return SDValue(); 5209 5210 SDValue Sc = Op.getOperand(0); 5211 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 5212 return SDValue(); 5213 5214 Ld = Sc.getOperand(0); 5215 5216 // The scalar_to_vector node and the suspected 5217 // load node must have exactly one user. 5218 if (!Sc.hasOneUse() || !Ld.hasOneUse()) 5219 return SDValue(); 5220 break; 5221 } 5222 } 5223 5224 // The scalar source must be a normal load. 5225 if (!ISD::isNormalLoad(Ld.getNode())) 5226 return SDValue(); 5227 5228 bool Is256 = VT.getSizeInBits() == 256; 5229 bool Is128 = VT.getSizeInBits() == 128; 5230 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5231 5232 if (hasAVX2) { 5233 // VBroadcast to YMM 5234 if (Is256 && (ScalarSize == 8 || ScalarSize == 16 || 5235 ScalarSize == 32 || ScalarSize == 64 )) 5236 return Ld; 5237 5238 // VBroadcast to XMM 5239 if (Is128 && (ScalarSize == 8 || ScalarSize == 32 || 5240 ScalarSize == 16 || ScalarSize == 64 )) 5241 return Ld; 5242 } 5243 5244 // VBroadcast to YMM 5245 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 5246 return Ld; 5247 5248 // VBroadcast to XMM 5249 if (Is128 && (ScalarSize == 32)) 5250 return Ld; 5251 5252 5253 // Unsupported broadcast. 5254 return SDValue(); 5255} 5256 5257SDValue 5258X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5259 DebugLoc dl = Op.getDebugLoc(); 5260 5261 EVT VT = Op.getValueType(); 5262 EVT ExtVT = VT.getVectorElementType(); 5263 unsigned NumElems = Op.getNumOperands(); 5264 5265 // Vectors containing all zeros can be matched by pxor and xorps later 5266 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5267 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5268 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5269 if (Op.getValueType() == MVT::v4i32 || 5270 Op.getValueType() == MVT::v8i32) 5271 return Op; 5272 5273 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl); 5274 } 5275 5276 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5277 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5278 // vpcmpeqd on 256-bit vectors. 5279 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5280 if (Op.getValueType() == MVT::v4i32 || 5281 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2())) 5282 return Op; 5283 5284 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl); 5285 } 5286 5287 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2()); 5288 if (Subtarget->hasAVX() && LD.getNode()) 5289 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 5290 5291 unsigned EVTBits = ExtVT.getSizeInBits(); 5292 5293 unsigned NumZero = 0; 5294 unsigned NumNonZero = 0; 5295 unsigned NonZeros = 0; 5296 bool IsAllConstants = true; 5297 SmallSet<SDValue, 8> Values; 5298 for (unsigned i = 0; i < NumElems; ++i) { 5299 SDValue Elt = Op.getOperand(i); 5300 if (Elt.getOpcode() == ISD::UNDEF) 5301 continue; 5302 Values.insert(Elt); 5303 if (Elt.getOpcode() != ISD::Constant && 5304 Elt.getOpcode() != ISD::ConstantFP) 5305 IsAllConstants = false; 5306 if (X86::isZeroNode(Elt)) 5307 NumZero++; 5308 else { 5309 NonZeros |= (1 << i); 5310 NumNonZero++; 5311 } 5312 } 5313 5314 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5315 if (NumNonZero == 0) 5316 return DAG.getUNDEF(VT); 5317 5318 // Special case for single non-zero, non-undef, element. 5319 if (NumNonZero == 1) { 5320 unsigned Idx = CountTrailingZeros_32(NonZeros); 5321 SDValue Item = Op.getOperand(Idx); 5322 5323 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5324 // the value are obviously zero, truncate the value to i32 and do the 5325 // insertion that way. Only do this if the value is non-constant or if the 5326 // value is a constant being inserted into element 0. It is cheaper to do 5327 // a constant pool load than it is to do a movd + shuffle. 5328 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5329 (!IsAllConstants || Idx == 0)) { 5330 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5331 // Handle SSE only. 5332 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5333 EVT VecVT = MVT::v4i32; 5334 unsigned VecElts = 4; 5335 5336 // Truncate the value (which may itself be a constant) to i32, and 5337 // convert it to a vector with movd (S2V+shuffle to zero extend). 5338 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5339 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5340 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5341 Subtarget->hasXMMInt(), DAG); 5342 5343 // Now we have our 32-bit value zero extended in the low element of 5344 // a vector. If Idx != 0, swizzle it into place. 5345 if (Idx != 0) { 5346 SmallVector<int, 4> Mask; 5347 Mask.push_back(Idx); 5348 for (unsigned i = 1; i != VecElts; ++i) 5349 Mask.push_back(i); 5350 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5351 DAG.getUNDEF(Item.getValueType()), 5352 &Mask[0]); 5353 } 5354 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 5355 } 5356 } 5357 5358 // If we have a constant or non-constant insertion into the low element of 5359 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5360 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5361 // depending on what the source datatype is. 5362 if (Idx == 0) { 5363 if (NumZero == 0) { 5364 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5365 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5366 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5367 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5368 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5369 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), 5370 DAG); 5371 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5372 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5373 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5374 EVT MiddleVT = MVT::v4i32; 5375 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 5376 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5377 Subtarget->hasXMMInt(), DAG); 5378 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5379 } 5380 } 5381 5382 // Is it a vector logical left shift? 5383 if (NumElems == 2 && Idx == 1 && 5384 X86::isZeroNode(Op.getOperand(0)) && 5385 !X86::isZeroNode(Op.getOperand(1))) { 5386 unsigned NumBits = VT.getSizeInBits(); 5387 return getVShift(true, VT, 5388 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5389 VT, Op.getOperand(1)), 5390 NumBits/2, DAG, *this, dl); 5391 } 5392 5393 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5394 return SDValue(); 5395 5396 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5397 // is a non-constant being inserted into an element other than the low one, 5398 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5399 // movd/movss) to move this into the low element, then shuffle it into 5400 // place. 5401 if (EVTBits == 32) { 5402 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5403 5404 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5405 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 5406 Subtarget->hasXMMInt(), DAG); 5407 SmallVector<int, 8> MaskVec; 5408 for (unsigned i = 0; i < NumElems; i++) 5409 MaskVec.push_back(i == Idx ? 0 : 1); 5410 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5411 } 5412 } 5413 5414 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5415 if (Values.size() == 1) { 5416 if (EVTBits == 32) { 5417 // Instead of a shuffle like this: 5418 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5419 // Check if it's possible to issue this instead. 5420 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5421 unsigned Idx = CountTrailingZeros_32(NonZeros); 5422 SDValue Item = Op.getOperand(Idx); 5423 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5424 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5425 } 5426 return SDValue(); 5427 } 5428 5429 // A vector full of immediates; various special cases are already 5430 // handled, so this is best done with a single constant-pool load. 5431 if (IsAllConstants) 5432 return SDValue(); 5433 5434 // For AVX-length vectors, build the individual 128-bit pieces and use 5435 // shuffles to put them in place. 5436 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5437 SmallVector<SDValue, 32> V; 5438 for (unsigned i = 0; i < NumElems; ++i) 5439 V.push_back(Op.getOperand(i)); 5440 5441 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5442 5443 // Build both the lower and upper subvector. 5444 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5445 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5446 NumElems/2); 5447 5448 // Recreate the wider vector with the lower and upper part. 5449 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5450 DAG.getConstant(0, MVT::i32), DAG, dl); 5451 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5452 DAG, dl); 5453 } 5454 5455 // Let legalizer expand 2-wide build_vectors. 5456 if (EVTBits == 64) { 5457 if (NumNonZero == 1) { 5458 // One half is zero or undef. 5459 unsigned Idx = CountTrailingZeros_32(NonZeros); 5460 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5461 Op.getOperand(Idx)); 5462 return getShuffleVectorZeroOrUndef(V2, Idx, true, 5463 Subtarget->hasXMMInt(), DAG); 5464 } 5465 return SDValue(); 5466 } 5467 5468 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5469 if (EVTBits == 8 && NumElems == 16) { 5470 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5471 *this); 5472 if (V.getNode()) return V; 5473 } 5474 5475 if (EVTBits == 16 && NumElems == 8) { 5476 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5477 *this); 5478 if (V.getNode()) return V; 5479 } 5480 5481 // If element VT is == 32 bits, turn it into a number of shuffles. 5482 SmallVector<SDValue, 8> V; 5483 V.resize(NumElems); 5484 if (NumElems == 4 && NumZero > 0) { 5485 for (unsigned i = 0; i < 4; ++i) { 5486 bool isZero = !(NonZeros & (1 << i)); 5487 if (isZero) 5488 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 5489 else 5490 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5491 } 5492 5493 for (unsigned i = 0; i < 2; ++i) { 5494 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5495 default: break; 5496 case 0: 5497 V[i] = V[i*2]; // Must be a zero vector. 5498 break; 5499 case 1: 5500 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5501 break; 5502 case 2: 5503 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5504 break; 5505 case 3: 5506 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5507 break; 5508 } 5509 } 5510 5511 SmallVector<int, 8> MaskVec; 5512 bool Reverse = (NonZeros & 0x3) == 2; 5513 for (unsigned i = 0; i < 2; ++i) 5514 MaskVec.push_back(Reverse ? 1-i : i); 5515 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5516 for (unsigned i = 0; i < 2; ++i) 5517 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5518 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5519 } 5520 5521 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5522 // Check for a build vector of consecutive loads. 5523 for (unsigned i = 0; i < NumElems; ++i) 5524 V[i] = Op.getOperand(i); 5525 5526 // Check for elements which are consecutive loads. 5527 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5528 if (LD.getNode()) 5529 return LD; 5530 5531 // For SSE 4.1, use insertps to put the high elements into the low element. 5532 if (getSubtarget()->hasSSE41orAVX()) { 5533 SDValue Result; 5534 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5535 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5536 else 5537 Result = DAG.getUNDEF(VT); 5538 5539 for (unsigned i = 1; i < NumElems; ++i) { 5540 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5541 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5542 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5543 } 5544 return Result; 5545 } 5546 5547 // Otherwise, expand into a number of unpckl*, start by extending each of 5548 // our (non-undef) elements to the full vector width with the element in the 5549 // bottom slot of the vector (which generates no code for SSE). 5550 for (unsigned i = 0; i < NumElems; ++i) { 5551 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5552 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5553 else 5554 V[i] = DAG.getUNDEF(VT); 5555 } 5556 5557 // Next, we iteratively mix elements, e.g. for v4f32: 5558 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5559 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5560 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5561 unsigned EltStride = NumElems >> 1; 5562 while (EltStride != 0) { 5563 for (unsigned i = 0; i < EltStride; ++i) { 5564 // If V[i+EltStride] is undef and this is the first round of mixing, 5565 // then it is safe to just drop this shuffle: V[i] is already in the 5566 // right place, the one element (since it's the first round) being 5567 // inserted as undef can be dropped. This isn't safe for successive 5568 // rounds because they will permute elements within both vectors. 5569 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5570 EltStride == NumElems/2) 5571 continue; 5572 5573 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5574 } 5575 EltStride >>= 1; 5576 } 5577 return V[0]; 5578 } 5579 return SDValue(); 5580} 5581 5582// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5583// them in a MMX register. This is better than doing a stack convert. 5584static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5585 DebugLoc dl = Op.getDebugLoc(); 5586 EVT ResVT = Op.getValueType(); 5587 5588 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5589 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5590 int Mask[2]; 5591 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5592 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5593 InVec = Op.getOperand(1); 5594 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5595 unsigned NumElts = ResVT.getVectorNumElements(); 5596 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5597 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5598 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5599 } else { 5600 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5601 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5602 Mask[0] = 0; Mask[1] = 2; 5603 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5604 } 5605 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5606} 5607 5608// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5609// to create 256-bit vectors from two other 128-bit ones. 5610static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5611 DebugLoc dl = Op.getDebugLoc(); 5612 EVT ResVT = Op.getValueType(); 5613 5614 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5615 5616 SDValue V1 = Op.getOperand(0); 5617 SDValue V2 = Op.getOperand(1); 5618 unsigned NumElems = ResVT.getVectorNumElements(); 5619 5620 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5621 DAG.getConstant(0, MVT::i32), DAG, dl); 5622 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5623 DAG, dl); 5624} 5625 5626SDValue 5627X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5628 EVT ResVT = Op.getValueType(); 5629 5630 assert(Op.getNumOperands() == 2); 5631 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5632 "Unsupported CONCAT_VECTORS for value type"); 5633 5634 // We support concatenate two MMX registers and place them in a MMX register. 5635 // This is better than doing a stack convert. 5636 if (ResVT.is128BitVector()) 5637 return LowerMMXCONCAT_VECTORS(Op, DAG); 5638 5639 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5640 // from two other 128-bit ones. 5641 return LowerAVXCONCAT_VECTORS(Op, DAG); 5642} 5643 5644// v8i16 shuffles - Prefer shuffles in the following order: 5645// 1. [all] pshuflw, pshufhw, optional move 5646// 2. [ssse3] 1 x pshufb 5647// 3. [ssse3] 2 x pshufb + 1 x por 5648// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5649SDValue 5650X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5651 SelectionDAG &DAG) const { 5652 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5653 SDValue V1 = SVOp->getOperand(0); 5654 SDValue V2 = SVOp->getOperand(1); 5655 DebugLoc dl = SVOp->getDebugLoc(); 5656 SmallVector<int, 8> MaskVals; 5657 5658 // Determine if more than 1 of the words in each of the low and high quadwords 5659 // of the result come from the same quadword of one of the two inputs. Undef 5660 // mask values count as coming from any quadword, for better codegen. 5661 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5662 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5663 BitVector InputQuads(4); 5664 for (unsigned i = 0; i < 8; ++i) { 5665 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5666 int EltIdx = SVOp->getMaskElt(i); 5667 MaskVals.push_back(EltIdx); 5668 if (EltIdx < 0) { 5669 ++Quad[0]; 5670 ++Quad[1]; 5671 ++Quad[2]; 5672 ++Quad[3]; 5673 continue; 5674 } 5675 ++Quad[EltIdx / 4]; 5676 InputQuads.set(EltIdx / 4); 5677 } 5678 5679 int BestLoQuad = -1; 5680 unsigned MaxQuad = 1; 5681 for (unsigned i = 0; i < 4; ++i) { 5682 if (LoQuad[i] > MaxQuad) { 5683 BestLoQuad = i; 5684 MaxQuad = LoQuad[i]; 5685 } 5686 } 5687 5688 int BestHiQuad = -1; 5689 MaxQuad = 1; 5690 for (unsigned i = 0; i < 4; ++i) { 5691 if (HiQuad[i] > MaxQuad) { 5692 BestHiQuad = i; 5693 MaxQuad = HiQuad[i]; 5694 } 5695 } 5696 5697 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5698 // of the two input vectors, shuffle them into one input vector so only a 5699 // single pshufb instruction is necessary. If There are more than 2 input 5700 // quads, disable the next transformation since it does not help SSSE3. 5701 bool V1Used = InputQuads[0] || InputQuads[1]; 5702 bool V2Used = InputQuads[2] || InputQuads[3]; 5703 if (Subtarget->hasSSSE3orAVX()) { 5704 if (InputQuads.count() == 2 && V1Used && V2Used) { 5705 BestLoQuad = InputQuads.find_first(); 5706 BestHiQuad = InputQuads.find_next(BestLoQuad); 5707 } 5708 if (InputQuads.count() > 2) { 5709 BestLoQuad = -1; 5710 BestHiQuad = -1; 5711 } 5712 } 5713 5714 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5715 // the shuffle mask. If a quad is scored as -1, that means that it contains 5716 // words from all 4 input quadwords. 5717 SDValue NewV; 5718 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5719 SmallVector<int, 8> MaskV; 5720 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5721 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5722 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5723 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5724 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5725 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5726 5727 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5728 // source words for the shuffle, to aid later transformations. 5729 bool AllWordsInNewV = true; 5730 bool InOrder[2] = { true, true }; 5731 for (unsigned i = 0; i != 8; ++i) { 5732 int idx = MaskVals[i]; 5733 if (idx != (int)i) 5734 InOrder[i/4] = false; 5735 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5736 continue; 5737 AllWordsInNewV = false; 5738 break; 5739 } 5740 5741 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5742 if (AllWordsInNewV) { 5743 for (int i = 0; i != 8; ++i) { 5744 int idx = MaskVals[i]; 5745 if (idx < 0) 5746 continue; 5747 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5748 if ((idx != i) && idx < 4) 5749 pshufhw = false; 5750 if ((idx != i) && idx > 3) 5751 pshuflw = false; 5752 } 5753 V1 = NewV; 5754 V2Used = false; 5755 BestLoQuad = 0; 5756 BestHiQuad = 1; 5757 } 5758 5759 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5760 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5761 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5762 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5763 unsigned TargetMask = 0; 5764 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5765 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5766 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5767 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5768 V1 = NewV.getOperand(0); 5769 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5770 } 5771 } 5772 5773 // If we have SSSE3, and all words of the result are from 1 input vector, 5774 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5775 // is present, fall back to case 4. 5776 if (Subtarget->hasSSSE3orAVX()) { 5777 SmallVector<SDValue,16> pshufbMask; 5778 5779 // If we have elements from both input vectors, set the high bit of the 5780 // shuffle mask element to zero out elements that come from V2 in the V1 5781 // mask, and elements that come from V1 in the V2 mask, so that the two 5782 // results can be OR'd together. 5783 bool TwoInputs = V1Used && V2Used; 5784 for (unsigned i = 0; i != 8; ++i) { 5785 int EltIdx = MaskVals[i] * 2; 5786 if (TwoInputs && (EltIdx >= 16)) { 5787 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5788 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5789 continue; 5790 } 5791 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5792 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5793 } 5794 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5795 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5796 DAG.getNode(ISD::BUILD_VECTOR, dl, 5797 MVT::v16i8, &pshufbMask[0], 16)); 5798 if (!TwoInputs) 5799 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5800 5801 // Calculate the shuffle mask for the second input, shuffle it, and 5802 // OR it with the first shuffled input. 5803 pshufbMask.clear(); 5804 for (unsigned i = 0; i != 8; ++i) { 5805 int EltIdx = MaskVals[i] * 2; 5806 if (EltIdx < 16) { 5807 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5808 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5809 continue; 5810 } 5811 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5812 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5813 } 5814 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5815 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5816 DAG.getNode(ISD::BUILD_VECTOR, dl, 5817 MVT::v16i8, &pshufbMask[0], 16)); 5818 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5819 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5820 } 5821 5822 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5823 // and update MaskVals with new element order. 5824 BitVector InOrder(8); 5825 if (BestLoQuad >= 0) { 5826 SmallVector<int, 8> MaskV; 5827 for (int i = 0; i != 4; ++i) { 5828 int idx = MaskVals[i]; 5829 if (idx < 0) { 5830 MaskV.push_back(-1); 5831 InOrder.set(i); 5832 } else if ((idx / 4) == BestLoQuad) { 5833 MaskV.push_back(idx & 3); 5834 InOrder.set(i); 5835 } else { 5836 MaskV.push_back(-1); 5837 } 5838 } 5839 for (unsigned i = 4; i != 8; ++i) 5840 MaskV.push_back(i); 5841 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5842 &MaskV[0]); 5843 5844 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX()) 5845 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5846 NewV.getOperand(0), 5847 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5848 DAG); 5849 } 5850 5851 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5852 // and update MaskVals with the new element order. 5853 if (BestHiQuad >= 0) { 5854 SmallVector<int, 8> MaskV; 5855 for (unsigned i = 0; i != 4; ++i) 5856 MaskV.push_back(i); 5857 for (unsigned i = 4; i != 8; ++i) { 5858 int idx = MaskVals[i]; 5859 if (idx < 0) { 5860 MaskV.push_back(-1); 5861 InOrder.set(i); 5862 } else if ((idx / 4) == BestHiQuad) { 5863 MaskV.push_back((idx & 3) + 4); 5864 InOrder.set(i); 5865 } else { 5866 MaskV.push_back(-1); 5867 } 5868 } 5869 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5870 &MaskV[0]); 5871 5872 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX()) 5873 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5874 NewV.getOperand(0), 5875 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5876 DAG); 5877 } 5878 5879 // In case BestHi & BestLo were both -1, which means each quadword has a word 5880 // from each of the four input quadwords, calculate the InOrder bitvector now 5881 // before falling through to the insert/extract cleanup. 5882 if (BestLoQuad == -1 && BestHiQuad == -1) { 5883 NewV = V1; 5884 for (int i = 0; i != 8; ++i) 5885 if (MaskVals[i] < 0 || MaskVals[i] == i) 5886 InOrder.set(i); 5887 } 5888 5889 // The other elements are put in the right place using pextrw and pinsrw. 5890 for (unsigned i = 0; i != 8; ++i) { 5891 if (InOrder[i]) 5892 continue; 5893 int EltIdx = MaskVals[i]; 5894 if (EltIdx < 0) 5895 continue; 5896 SDValue ExtOp = (EltIdx < 8) 5897 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5898 DAG.getIntPtrConstant(EltIdx)) 5899 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5900 DAG.getIntPtrConstant(EltIdx - 8)); 5901 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5902 DAG.getIntPtrConstant(i)); 5903 } 5904 return NewV; 5905} 5906 5907// v16i8 shuffles - Prefer shuffles in the following order: 5908// 1. [ssse3] 1 x pshufb 5909// 2. [ssse3] 2 x pshufb + 1 x por 5910// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5911static 5912SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5913 SelectionDAG &DAG, 5914 const X86TargetLowering &TLI) { 5915 SDValue V1 = SVOp->getOperand(0); 5916 SDValue V2 = SVOp->getOperand(1); 5917 DebugLoc dl = SVOp->getDebugLoc(); 5918 SmallVector<int, 16> MaskVals; 5919 SVOp->getMask(MaskVals); 5920 5921 // If we have SSSE3, case 1 is generated when all result bytes come from 5922 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5923 // present, fall back to case 3. 5924 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5925 bool V1Only = true; 5926 bool V2Only = true; 5927 for (unsigned i = 0; i < 16; ++i) { 5928 int EltIdx = MaskVals[i]; 5929 if (EltIdx < 0) 5930 continue; 5931 if (EltIdx < 16) 5932 V2Only = false; 5933 else 5934 V1Only = false; 5935 } 5936 5937 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5938 if (TLI.getSubtarget()->hasSSSE3orAVX()) { 5939 SmallVector<SDValue,16> pshufbMask; 5940 5941 // If all result elements are from one input vector, then only translate 5942 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5943 // 5944 // Otherwise, we have elements from both input vectors, and must zero out 5945 // elements that come from V2 in the first mask, and V1 in the second mask 5946 // so that we can OR them together. 5947 bool TwoInputs = !(V1Only || V2Only); 5948 for (unsigned i = 0; i != 16; ++i) { 5949 int EltIdx = MaskVals[i]; 5950 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5951 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5952 continue; 5953 } 5954 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5955 } 5956 // If all the elements are from V2, assign it to V1 and return after 5957 // building the first pshufb. 5958 if (V2Only) 5959 V1 = V2; 5960 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5961 DAG.getNode(ISD::BUILD_VECTOR, dl, 5962 MVT::v16i8, &pshufbMask[0], 16)); 5963 if (!TwoInputs) 5964 return V1; 5965 5966 // Calculate the shuffle mask for the second input, shuffle it, and 5967 // OR it with the first shuffled input. 5968 pshufbMask.clear(); 5969 for (unsigned i = 0; i != 16; ++i) { 5970 int EltIdx = MaskVals[i]; 5971 if (EltIdx < 16) { 5972 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5973 continue; 5974 } 5975 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5976 } 5977 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5978 DAG.getNode(ISD::BUILD_VECTOR, dl, 5979 MVT::v16i8, &pshufbMask[0], 16)); 5980 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5981 } 5982 5983 // No SSSE3 - Calculate in place words and then fix all out of place words 5984 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5985 // the 16 different words that comprise the two doublequadword input vectors. 5986 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5987 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5988 SDValue NewV = V2Only ? V2 : V1; 5989 for (int i = 0; i != 8; ++i) { 5990 int Elt0 = MaskVals[i*2]; 5991 int Elt1 = MaskVals[i*2+1]; 5992 5993 // This word of the result is all undef, skip it. 5994 if (Elt0 < 0 && Elt1 < 0) 5995 continue; 5996 5997 // This word of the result is already in the correct place, skip it. 5998 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5999 continue; 6000 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 6001 continue; 6002 6003 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 6004 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 6005 SDValue InsElt; 6006 6007 // If Elt0 and Elt1 are defined, are consecutive, and can be load 6008 // using a single extract together, load it and store it. 6009 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 6010 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6011 DAG.getIntPtrConstant(Elt1 / 2)); 6012 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6013 DAG.getIntPtrConstant(i)); 6014 continue; 6015 } 6016 6017 // If Elt1 is defined, extract it from the appropriate source. If the 6018 // source byte is not also odd, shift the extracted word left 8 bits 6019 // otherwise clear the bottom 8 bits if we need to do an or. 6020 if (Elt1 >= 0) { 6021 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6022 DAG.getIntPtrConstant(Elt1 / 2)); 6023 if ((Elt1 & 1) == 0) 6024 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 6025 DAG.getConstant(8, 6026 TLI.getShiftAmountTy(InsElt.getValueType()))); 6027 else if (Elt0 >= 0) 6028 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 6029 DAG.getConstant(0xFF00, MVT::i16)); 6030 } 6031 // If Elt0 is defined, extract it from the appropriate source. If the 6032 // source byte is not also even, shift the extracted word right 8 bits. If 6033 // Elt1 was also defined, OR the extracted values together before 6034 // inserting them in the result. 6035 if (Elt0 >= 0) { 6036 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 6037 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 6038 if ((Elt0 & 1) != 0) 6039 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 6040 DAG.getConstant(8, 6041 TLI.getShiftAmountTy(InsElt0.getValueType()))); 6042 else if (Elt1 >= 0) 6043 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 6044 DAG.getConstant(0x00FF, MVT::i16)); 6045 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 6046 : InsElt0; 6047 } 6048 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6049 DAG.getIntPtrConstant(i)); 6050 } 6051 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 6052} 6053 6054/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 6055/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 6056/// done when every pair / quad of shuffle mask elements point to elements in 6057/// the right sequence. e.g. 6058/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 6059static 6060SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 6061 SelectionDAG &DAG, DebugLoc dl) { 6062 EVT VT = SVOp->getValueType(0); 6063 SDValue V1 = SVOp->getOperand(0); 6064 SDValue V2 = SVOp->getOperand(1); 6065 unsigned NumElems = VT.getVectorNumElements(); 6066 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 6067 EVT NewVT; 6068 switch (VT.getSimpleVT().SimpleTy) { 6069 default: assert(false && "Unexpected!"); 6070 case MVT::v4f32: NewVT = MVT::v2f64; break; 6071 case MVT::v4i32: NewVT = MVT::v2i64; break; 6072 case MVT::v8i16: NewVT = MVT::v4i32; break; 6073 case MVT::v16i8: NewVT = MVT::v4i32; break; 6074 } 6075 6076 int Scale = NumElems / NewWidth; 6077 SmallVector<int, 8> MaskVec; 6078 for (unsigned i = 0; i < NumElems; i += Scale) { 6079 int StartIdx = -1; 6080 for (int j = 0; j < Scale; ++j) { 6081 int EltIdx = SVOp->getMaskElt(i+j); 6082 if (EltIdx < 0) 6083 continue; 6084 if (StartIdx == -1) 6085 StartIdx = EltIdx - (EltIdx % Scale); 6086 if (EltIdx != StartIdx + j) 6087 return SDValue(); 6088 } 6089 if (StartIdx == -1) 6090 MaskVec.push_back(-1); 6091 else 6092 MaskVec.push_back(StartIdx / Scale); 6093 } 6094 6095 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 6096 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 6097 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 6098} 6099 6100/// getVZextMovL - Return a zero-extending vector move low node. 6101/// 6102static SDValue getVZextMovL(EVT VT, EVT OpVT, 6103 SDValue SrcOp, SelectionDAG &DAG, 6104 const X86Subtarget *Subtarget, DebugLoc dl) { 6105 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 6106 LoadSDNode *LD = NULL; 6107 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 6108 LD = dyn_cast<LoadSDNode>(SrcOp); 6109 if (!LD) { 6110 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 6111 // instead. 6112 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 6113 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 6114 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 6115 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 6116 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 6117 // PR2108 6118 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 6119 return DAG.getNode(ISD::BITCAST, dl, VT, 6120 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6121 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6122 OpVT, 6123 SrcOp.getOperand(0) 6124 .getOperand(0)))); 6125 } 6126 } 6127 } 6128 6129 return DAG.getNode(ISD::BITCAST, dl, VT, 6130 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6131 DAG.getNode(ISD::BITCAST, dl, 6132 OpVT, SrcOp))); 6133} 6134 6135/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector 6136/// shuffle node referes to only one lane in the sources. 6137static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) { 6138 EVT VT = SVOp->getValueType(0); 6139 int NumElems = VT.getVectorNumElements(); 6140 int HalfSize = NumElems/2; 6141 SmallVector<int, 16> M; 6142 SVOp->getMask(M); 6143 bool MatchA = false, MatchB = false; 6144 6145 for (int l = 0; l < NumElems*2; l += HalfSize) { 6146 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) { 6147 MatchA = true; 6148 break; 6149 } 6150 } 6151 6152 for (int l = 0; l < NumElems*2; l += HalfSize) { 6153 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) { 6154 MatchB = true; 6155 break; 6156 } 6157 } 6158 6159 return MatchA && MatchB; 6160} 6161 6162/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 6163/// which could not be matched by any known target speficic shuffle 6164static SDValue 6165LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6166 if (areShuffleHalvesWithinDisjointLanes(SVOp)) { 6167 // If each half of a vector shuffle node referes to only one lane in the 6168 // source vectors, extract each used 128-bit lane and shuffle them using 6169 // 128-bit shuffles. Then, concatenate the results. Otherwise leave 6170 // the work to the legalizer. 6171 DebugLoc dl = SVOp->getDebugLoc(); 6172 EVT VT = SVOp->getValueType(0); 6173 int NumElems = VT.getVectorNumElements(); 6174 int HalfSize = NumElems/2; 6175 6176 // Extract the reference for each half 6177 int FstVecExtractIdx = 0, SndVecExtractIdx = 0; 6178 int FstVecOpNum = 0, SndVecOpNum = 0; 6179 for (int i = 0; i < HalfSize; ++i) { 6180 int Elt = SVOp->getMaskElt(i); 6181 if (SVOp->getMaskElt(i) < 0) 6182 continue; 6183 FstVecOpNum = Elt/NumElems; 6184 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 6185 break; 6186 } 6187 for (int i = HalfSize; i < NumElems; ++i) { 6188 int Elt = SVOp->getMaskElt(i); 6189 if (SVOp->getMaskElt(i) < 0) 6190 continue; 6191 SndVecOpNum = Elt/NumElems; 6192 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 6193 break; 6194 } 6195 6196 // Extract the subvectors 6197 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum), 6198 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl); 6199 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum), 6200 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl); 6201 6202 // Generate 128-bit shuffles 6203 SmallVector<int, 16> MaskV1, MaskV2; 6204 for (int i = 0; i < HalfSize; ++i) { 6205 int Elt = SVOp->getMaskElt(i); 6206 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6207 } 6208 for (int i = HalfSize; i < NumElems; ++i) { 6209 int Elt = SVOp->getMaskElt(i); 6210 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6211 } 6212 6213 EVT NVT = V1.getValueType(); 6214 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]); 6215 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]); 6216 6217 // Concatenate the result back 6218 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1, 6219 DAG.getConstant(0, MVT::i32), DAG, dl); 6220 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 6221 DAG, dl); 6222 } 6223 6224 return SDValue(); 6225} 6226 6227/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6228/// 4 elements, and match them with several different shuffle types. 6229static SDValue 6230LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6231 SDValue V1 = SVOp->getOperand(0); 6232 SDValue V2 = SVOp->getOperand(1); 6233 DebugLoc dl = SVOp->getDebugLoc(); 6234 EVT VT = SVOp->getValueType(0); 6235 6236 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6237 6238 SmallVector<std::pair<int, int>, 8> Locs; 6239 Locs.resize(4); 6240 SmallVector<int, 8> Mask1(4U, -1); 6241 SmallVector<int, 8> PermMask; 6242 SVOp->getMask(PermMask); 6243 6244 unsigned NumHi = 0; 6245 unsigned NumLo = 0; 6246 for (unsigned i = 0; i != 4; ++i) { 6247 int Idx = PermMask[i]; 6248 if (Idx < 0) { 6249 Locs[i] = std::make_pair(-1, -1); 6250 } else { 6251 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6252 if (Idx < 4) { 6253 Locs[i] = std::make_pair(0, NumLo); 6254 Mask1[NumLo] = Idx; 6255 NumLo++; 6256 } else { 6257 Locs[i] = std::make_pair(1, NumHi); 6258 if (2+NumHi < 4) 6259 Mask1[2+NumHi] = Idx; 6260 NumHi++; 6261 } 6262 } 6263 } 6264 6265 if (NumLo <= 2 && NumHi <= 2) { 6266 // If no more than two elements come from either vector. This can be 6267 // implemented with two shuffles. First shuffle gather the elements. 6268 // The second shuffle, which takes the first shuffle as both of its 6269 // vector operands, put the elements into the right order. 6270 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6271 6272 SmallVector<int, 8> Mask2(4U, -1); 6273 6274 for (unsigned i = 0; i != 4; ++i) { 6275 if (Locs[i].first == -1) 6276 continue; 6277 else { 6278 unsigned Idx = (i < 2) ? 0 : 4; 6279 Idx += Locs[i].first * 2 + Locs[i].second; 6280 Mask2[i] = Idx; 6281 } 6282 } 6283 6284 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6285 } else if (NumLo == 3 || NumHi == 3) { 6286 // Otherwise, we must have three elements from one vector, call it X, and 6287 // one element from the other, call it Y. First, use a shufps to build an 6288 // intermediate vector with the one element from Y and the element from X 6289 // that will be in the same half in the final destination (the indexes don't 6290 // matter). Then, use a shufps to build the final vector, taking the half 6291 // containing the element from Y from the intermediate, and the other half 6292 // from X. 6293 if (NumHi == 3) { 6294 // Normalize it so the 3 elements come from V1. 6295 CommuteVectorShuffleMask(PermMask, VT); 6296 std::swap(V1, V2); 6297 } 6298 6299 // Find the element from V2. 6300 unsigned HiIndex; 6301 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6302 int Val = PermMask[HiIndex]; 6303 if (Val < 0) 6304 continue; 6305 if (Val >= 4) 6306 break; 6307 } 6308 6309 Mask1[0] = PermMask[HiIndex]; 6310 Mask1[1] = -1; 6311 Mask1[2] = PermMask[HiIndex^1]; 6312 Mask1[3] = -1; 6313 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6314 6315 if (HiIndex >= 2) { 6316 Mask1[0] = PermMask[0]; 6317 Mask1[1] = PermMask[1]; 6318 Mask1[2] = HiIndex & 1 ? 6 : 4; 6319 Mask1[3] = HiIndex & 1 ? 4 : 6; 6320 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6321 } else { 6322 Mask1[0] = HiIndex & 1 ? 2 : 0; 6323 Mask1[1] = HiIndex & 1 ? 0 : 2; 6324 Mask1[2] = PermMask[2]; 6325 Mask1[3] = PermMask[3]; 6326 if (Mask1[2] >= 0) 6327 Mask1[2] += 4; 6328 if (Mask1[3] >= 0) 6329 Mask1[3] += 4; 6330 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6331 } 6332 } 6333 6334 // Break it into (shuffle shuffle_hi, shuffle_lo). 6335 Locs.clear(); 6336 Locs.resize(4); 6337 SmallVector<int,8> LoMask(4U, -1); 6338 SmallVector<int,8> HiMask(4U, -1); 6339 6340 SmallVector<int,8> *MaskPtr = &LoMask; 6341 unsigned MaskIdx = 0; 6342 unsigned LoIdx = 0; 6343 unsigned HiIdx = 2; 6344 for (unsigned i = 0; i != 4; ++i) { 6345 if (i == 2) { 6346 MaskPtr = &HiMask; 6347 MaskIdx = 1; 6348 LoIdx = 0; 6349 HiIdx = 2; 6350 } 6351 int Idx = PermMask[i]; 6352 if (Idx < 0) { 6353 Locs[i] = std::make_pair(-1, -1); 6354 } else if (Idx < 4) { 6355 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6356 (*MaskPtr)[LoIdx] = Idx; 6357 LoIdx++; 6358 } else { 6359 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6360 (*MaskPtr)[HiIdx] = Idx; 6361 HiIdx++; 6362 } 6363 } 6364 6365 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6366 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6367 SmallVector<int, 8> MaskOps; 6368 for (unsigned i = 0; i != 4; ++i) { 6369 if (Locs[i].first == -1) { 6370 MaskOps.push_back(-1); 6371 } else { 6372 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6373 MaskOps.push_back(Idx); 6374 } 6375 } 6376 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6377} 6378 6379static bool MayFoldVectorLoad(SDValue V) { 6380 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6381 V = V.getOperand(0); 6382 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6383 V = V.getOperand(0); 6384 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6385 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6386 // BUILD_VECTOR (load), undef 6387 V = V.getOperand(0); 6388 if (MayFoldLoad(V)) 6389 return true; 6390 return false; 6391} 6392 6393// FIXME: the version above should always be used. Since there's 6394// a bug where several vector shuffles can't be folded because the 6395// DAG is not updated during lowering and a node claims to have two 6396// uses while it only has one, use this version, and let isel match 6397// another instruction if the load really happens to have more than 6398// one use. Remove this version after this bug get fixed. 6399// rdar://8434668, PR8156 6400static bool RelaxedMayFoldVectorLoad(SDValue V) { 6401 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6402 V = V.getOperand(0); 6403 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6404 V = V.getOperand(0); 6405 if (ISD::isNormalLoad(V.getNode())) 6406 return true; 6407 return false; 6408} 6409 6410/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6411/// a vector extract, and if both can be later optimized into a single load. 6412/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6413/// here because otherwise a target specific shuffle node is going to be 6414/// emitted for this shuffle, and the optimization not done. 6415/// FIXME: This is probably not the best approach, but fix the problem 6416/// until the right path is decided. 6417static 6418bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6419 const TargetLowering &TLI) { 6420 EVT VT = V.getValueType(); 6421 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6422 6423 // Be sure that the vector shuffle is present in a pattern like this: 6424 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6425 if (!V.hasOneUse()) 6426 return false; 6427 6428 SDNode *N = *V.getNode()->use_begin(); 6429 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6430 return false; 6431 6432 SDValue EltNo = N->getOperand(1); 6433 if (!isa<ConstantSDNode>(EltNo)) 6434 return false; 6435 6436 // If the bit convert changed the number of elements, it is unsafe 6437 // to examine the mask. 6438 bool HasShuffleIntoBitcast = false; 6439 if (V.getOpcode() == ISD::BITCAST) { 6440 EVT SrcVT = V.getOperand(0).getValueType(); 6441 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6442 return false; 6443 V = V.getOperand(0); 6444 HasShuffleIntoBitcast = true; 6445 } 6446 6447 // Select the input vector, guarding against out of range extract vector. 6448 unsigned NumElems = VT.getVectorNumElements(); 6449 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6450 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6451 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6452 6453 // Skip one more bit_convert if necessary 6454 if (V.getOpcode() == ISD::BITCAST) 6455 V = V.getOperand(0); 6456 6457 if (ISD::isNormalLoad(V.getNode())) { 6458 // Is the original load suitable? 6459 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6460 6461 // FIXME: avoid the multi-use bug that is preventing lots of 6462 // of foldings to be detected, this is still wrong of course, but 6463 // give the temporary desired behavior, and if it happens that 6464 // the load has real more uses, during isel it will not fold, and 6465 // will generate poor code. 6466 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 6467 return false; 6468 6469 if (!HasShuffleIntoBitcast) 6470 return true; 6471 6472 // If there's a bitcast before the shuffle, check if the load type and 6473 // alignment is valid. 6474 unsigned Align = LN0->getAlignment(); 6475 unsigned NewAlign = 6476 TLI.getTargetData()->getABITypeAlignment( 6477 VT.getTypeForEVT(*DAG.getContext())); 6478 6479 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6480 return false; 6481 } 6482 6483 return true; 6484} 6485 6486static 6487SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6488 EVT VT = Op.getValueType(); 6489 6490 // Canonizalize to v2f64. 6491 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6492 return DAG.getNode(ISD::BITCAST, dl, VT, 6493 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6494 V1, DAG)); 6495} 6496 6497static 6498SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6499 bool HasXMMInt) { 6500 SDValue V1 = Op.getOperand(0); 6501 SDValue V2 = Op.getOperand(1); 6502 EVT VT = Op.getValueType(); 6503 6504 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6505 6506 if (HasXMMInt && VT == MVT::v2f64) 6507 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6508 6509 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6510 return DAG.getNode(ISD::BITCAST, dl, VT, 6511 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6512 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6513 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6514} 6515 6516static 6517SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6518 SDValue V1 = Op.getOperand(0); 6519 SDValue V2 = Op.getOperand(1); 6520 EVT VT = Op.getValueType(); 6521 6522 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6523 "unsupported shuffle type"); 6524 6525 if (V2.getOpcode() == ISD::UNDEF) 6526 V2 = V1; 6527 6528 // v4i32 or v4f32 6529 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6530} 6531 6532static inline unsigned getSHUFPOpcode(EVT VT) { 6533 switch(VT.getSimpleVT().SimpleTy) { 6534 case MVT::v8i32: // Use fp unit for int unpack. 6535 case MVT::v8f32: 6536 case MVT::v4i32: // Use fp unit for int unpack. 6537 case MVT::v4f32: return X86ISD::SHUFPS; 6538 case MVT::v4i64: // Use fp unit for int unpack. 6539 case MVT::v4f64: 6540 case MVT::v2i64: // Use fp unit for int unpack. 6541 case MVT::v2f64: return X86ISD::SHUFPD; 6542 default: 6543 llvm_unreachable("Unknown type for shufp*"); 6544 } 6545 return 0; 6546} 6547 6548static 6549SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) { 6550 SDValue V1 = Op.getOperand(0); 6551 SDValue V2 = Op.getOperand(1); 6552 EVT VT = Op.getValueType(); 6553 unsigned NumElems = VT.getVectorNumElements(); 6554 6555 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6556 // operand of these instructions is only memory, so check if there's a 6557 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6558 // same masks. 6559 bool CanFoldLoad = false; 6560 6561 // Trivial case, when V2 comes from a load. 6562 if (MayFoldVectorLoad(V2)) 6563 CanFoldLoad = true; 6564 6565 // When V1 is a load, it can be folded later into a store in isel, example: 6566 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6567 // turns into: 6568 // (MOVLPSmr addr:$src1, VR128:$src2) 6569 // So, recognize this potential and also use MOVLPS or MOVLPD 6570 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6571 CanFoldLoad = true; 6572 6573 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6574 if (CanFoldLoad) { 6575 if (HasXMMInt && NumElems == 2) 6576 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6577 6578 if (NumElems == 4) 6579 // If we don't care about the second element, procede to use movss. 6580 if (SVOp->getMaskElt(1) != -1) 6581 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6582 } 6583 6584 // movl and movlp will both match v2i64, but v2i64 is never matched by 6585 // movl earlier because we make it strict to avoid messing with the movlp load 6586 // folding logic (see the code above getMOVLP call). Match it here then, 6587 // this is horrible, but will stay like this until we move all shuffle 6588 // matching to x86 specific nodes. Note that for the 1st condition all 6589 // types are matched with movsd. 6590 if (HasXMMInt) { 6591 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6592 // as to remove this logic from here, as much as possible 6593 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6594 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6595 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6596 } 6597 6598 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6599 6600 // Invert the operand order and use SHUFPS to match it. 6601 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1, 6602 X86::getShuffleSHUFImmediate(SVOp), DAG); 6603} 6604 6605static inline unsigned getUNPCKLOpcode(EVT VT, bool HasAVX2) { 6606 switch(VT.getSimpleVT().SimpleTy) { 6607 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 6608 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 6609 case MVT::v4f32: return X86ISD::UNPCKLPS; 6610 case MVT::v2f64: return X86ISD::UNPCKLPD; 6611 case MVT::v8i32: 6612 if (HasAVX2) return X86ISD::VPUNPCKLDQY; 6613 // else use fp unit for int unpack. 6614 case MVT::v8f32: return X86ISD::VUNPCKLPSY; 6615 case MVT::v4i64: 6616 if (HasAVX2) return X86ISD::VPUNPCKLQDQY; 6617 // else use fp unit for int unpack. 6618 case MVT::v4f64: return X86ISD::VUNPCKLPDY; 6619 case MVT::v16i8: return X86ISD::PUNPCKLBW; 6620 case MVT::v8i16: return X86ISD::PUNPCKLWD; 6621 case MVT::v16i16: return X86ISD::VPUNPCKLWDY; 6622 case MVT::v32i8: return X86ISD::VPUNPCKLBWY; 6623 default: 6624 llvm_unreachable("Unknown type for unpckl"); 6625 } 6626 return 0; 6627} 6628 6629static inline unsigned getUNPCKHOpcode(EVT VT, bool HasAVX2) { 6630 switch(VT.getSimpleVT().SimpleTy) { 6631 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 6632 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 6633 case MVT::v4f32: return X86ISD::UNPCKHPS; 6634 case MVT::v2f64: return X86ISD::UNPCKHPD; 6635 case MVT::v8i32: 6636 if (HasAVX2) return X86ISD::VPUNPCKHDQY; 6637 // else use fp unit for int unpack. 6638 case MVT::v8f32: return X86ISD::VUNPCKHPSY; 6639 case MVT::v4i64: 6640 if (HasAVX2) return X86ISD::VPUNPCKHQDQY; 6641 // else use fp unit for int unpack. 6642 case MVT::v4f64: return X86ISD::VUNPCKHPDY; 6643 case MVT::v16i8: return X86ISD::PUNPCKHBW; 6644 case MVT::v8i16: return X86ISD::PUNPCKHWD; 6645 case MVT::v16i16: return X86ISD::VPUNPCKHWDY; 6646 case MVT::v32i8: return X86ISD::VPUNPCKHBWY; 6647 default: 6648 llvm_unreachable("Unknown type for unpckh"); 6649 } 6650 return 0; 6651} 6652 6653static inline unsigned getVPERMILOpcode(EVT VT) { 6654 switch(VT.getSimpleVT().SimpleTy) { 6655 case MVT::v4i32: 6656 case MVT::v4f32: return X86ISD::VPERMILPS; 6657 case MVT::v2i64: 6658 case MVT::v2f64: return X86ISD::VPERMILPD; 6659 case MVT::v8i32: 6660 case MVT::v8f32: return X86ISD::VPERMILPSY; 6661 case MVT::v4i64: 6662 case MVT::v4f64: return X86ISD::VPERMILPDY; 6663 default: 6664 llvm_unreachable("Unknown type for vpermil"); 6665 } 6666 return 0; 6667} 6668 6669static 6670SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6671 const TargetLowering &TLI, 6672 const X86Subtarget *Subtarget) { 6673 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6674 EVT VT = Op.getValueType(); 6675 DebugLoc dl = Op.getDebugLoc(); 6676 SDValue V1 = Op.getOperand(0); 6677 SDValue V2 = Op.getOperand(1); 6678 6679 if (isZeroShuffle(SVOp)) 6680 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 6681 6682 // Handle splat operations 6683 if (SVOp->isSplat()) { 6684 unsigned NumElem = VT.getVectorNumElements(); 6685 int Size = VT.getSizeInBits(); 6686 // Special case, this is the only place now where it's allowed to return 6687 // a vector_shuffle operation without using a target specific node, because 6688 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6689 // this be moved to DAGCombine instead? 6690 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6691 return Op; 6692 6693 // Use vbroadcast whenever the splat comes from a foldable load 6694 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2()); 6695 if (Subtarget->hasAVX() && LD.getNode()) 6696 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 6697 6698 // Handle splats by matching through known shuffle masks 6699 if ((Size == 128 && NumElem <= 4) || 6700 (Size == 256 && NumElem < 8)) 6701 return SDValue(); 6702 6703 // All remaning splats are promoted to target supported vector shuffles. 6704 return PromoteSplat(SVOp, DAG); 6705 } 6706 6707 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6708 // do it! 6709 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6710 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6711 if (NewOp.getNode()) 6712 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6713 } else if ((VT == MVT::v4i32 || 6714 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) { 6715 // FIXME: Figure out a cleaner way to do this. 6716 // Try to make use of movq to zero out the top part. 6717 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6718 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6719 if (NewOp.getNode()) { 6720 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6721 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6722 DAG, Subtarget, dl); 6723 } 6724 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6725 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6726 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6727 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6728 DAG, Subtarget, dl); 6729 } 6730 } 6731 return SDValue(); 6732} 6733 6734SDValue 6735X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6736 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6737 SDValue V1 = Op.getOperand(0); 6738 SDValue V2 = Op.getOperand(1); 6739 EVT VT = Op.getValueType(); 6740 DebugLoc dl = Op.getDebugLoc(); 6741 unsigned NumElems = VT.getVectorNumElements(); 6742 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6743 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6744 bool V1IsSplat = false; 6745 bool V2IsSplat = false; 6746 bool HasXMMInt = Subtarget->hasXMMInt(); 6747 bool HasAVX2 = Subtarget->hasAVX2(); 6748 MachineFunction &MF = DAG.getMachineFunction(); 6749 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6750 6751 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6752 6753 // Vector shuffle lowering takes 3 steps: 6754 // 6755 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6756 // narrowing and commutation of operands should be handled. 6757 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6758 // shuffle nodes. 6759 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6760 // so the shuffle can be broken into other shuffles and the legalizer can 6761 // try the lowering again. 6762 // 6763 // The general idea is that no vector_shuffle operation should be left to 6764 // be matched during isel, all of them must be converted to a target specific 6765 // node here. 6766 6767 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6768 // narrowing and commutation of operands should be handled. The actual code 6769 // doesn't include all of those, work in progress... 6770 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6771 if (NewOp.getNode()) 6772 return NewOp; 6773 6774 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6775 // unpckh_undef). Only use pshufd if speed is more important than size. 6776 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 6777 return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1, 6778 DAG); 6779 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 6780 return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1, 6781 DAG); 6782 6783 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() && 6784 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6785 return getMOVDDup(Op, dl, V1, DAG); 6786 6787 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6788 return getMOVHighToLow(Op, dl, DAG); 6789 6790 // Use to match splats 6791 if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef && 6792 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6793 return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1, 6794 DAG); 6795 6796 if (X86::isPSHUFDMask(SVOp)) { 6797 // The actual implementation will match the mask in the if above and then 6798 // during isel it can match several different instructions, not only pshufd 6799 // as its name says, sad but true, emulate the behavior for now... 6800 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6801 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6802 6803 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6804 6805 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6806 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6807 6808 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1, 6809 TargetMask, DAG); 6810 } 6811 6812 // Check if this can be converted into a logical shift. 6813 bool isLeft = false; 6814 unsigned ShAmt = 0; 6815 SDValue ShVal; 6816 bool isShift = HasXMMInt && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6817 if (isShift && ShVal.hasOneUse()) { 6818 // If the shifted value has multiple uses, it may be cheaper to use 6819 // v_set0 + movlhps or movhlps, etc. 6820 EVT EltVT = VT.getVectorElementType(); 6821 ShAmt *= EltVT.getSizeInBits(); 6822 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6823 } 6824 6825 if (X86::isMOVLMask(SVOp)) { 6826 if (V1IsUndef) 6827 return V2; 6828 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6829 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6830 if (!X86::isMOVLPMask(SVOp)) { 6831 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6832 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6833 6834 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6835 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6836 } 6837 } 6838 6839 // FIXME: fold these into legal mask. 6840 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2)) 6841 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt); 6842 6843 if (X86::isMOVHLPSMask(SVOp)) 6844 return getMOVHighToLow(Op, dl, DAG); 6845 6846 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6847 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6848 6849 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6850 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6851 6852 if (X86::isMOVLPMask(SVOp)) 6853 return getMOVLP(Op, dl, DAG, HasXMMInt); 6854 6855 if (ShouldXformToMOVHLPS(SVOp) || 6856 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6857 return CommuteVectorShuffle(SVOp, DAG); 6858 6859 if (isShift) { 6860 // No better options. Use a vshl / vsrl. 6861 EVT EltVT = VT.getVectorElementType(); 6862 ShAmt *= EltVT.getSizeInBits(); 6863 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6864 } 6865 6866 bool Commuted = false; 6867 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6868 // 1,1,1,1 -> v8i16 though. 6869 V1IsSplat = isSplatVector(V1.getNode()); 6870 V2IsSplat = isSplatVector(V2.getNode()); 6871 6872 // Canonicalize the splat or undef, if present, to be on the RHS. 6873 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 6874 Op = CommuteVectorShuffle(SVOp, DAG); 6875 SVOp = cast<ShuffleVectorSDNode>(Op); 6876 V1 = SVOp->getOperand(0); 6877 V2 = SVOp->getOperand(1); 6878 std::swap(V1IsSplat, V2IsSplat); 6879 std::swap(V1IsUndef, V2IsUndef); 6880 Commuted = true; 6881 } 6882 6883 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 6884 // Shuffling low element of v1 into undef, just return v1. 6885 if (V2IsUndef) 6886 return V1; 6887 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6888 // the instruction selector will not match, so get a canonical MOVL with 6889 // swapped operands to undo the commute. 6890 return getMOVL(DAG, dl, VT, V2, V1); 6891 } 6892 6893 if (X86::isUNPCKLMask(SVOp, HasAVX2)) 6894 return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V2, 6895 DAG); 6896 6897 if (X86::isUNPCKHMask(SVOp, HasAVX2)) 6898 return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V2, 6899 DAG); 6900 6901 if (V2IsSplat) { 6902 // Normalize mask so all entries that point to V2 points to its first 6903 // element then try to match unpck{h|l} again. If match, return a 6904 // new vector_shuffle with the corrected mask. 6905 SDValue NewMask = NormalizeMask(SVOp, DAG); 6906 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6907 if (NSVOp != SVOp) { 6908 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) { 6909 return NewMask; 6910 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) { 6911 return NewMask; 6912 } 6913 } 6914 } 6915 6916 if (Commuted) { 6917 // Commute is back and try unpck* again. 6918 // FIXME: this seems wrong. 6919 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6920 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6921 6922 if (X86::isUNPCKLMask(NewSVOp, HasAVX2)) 6923 return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V2, V1, 6924 DAG); 6925 6926 if (X86::isUNPCKHMask(NewSVOp, HasAVX2)) 6927 return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V2, V1, 6928 DAG); 6929 } 6930 6931 // Normalize the node to match x86 shuffle ops if needed 6932 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 6933 return CommuteVectorShuffle(SVOp, DAG); 6934 6935 // The checks below are all present in isShuffleMaskLegal, but they are 6936 // inlined here right now to enable us to directly emit target specific 6937 // nodes, and remove one by one until they don't return Op anymore. 6938 SmallVector<int, 16> M; 6939 SVOp->getMask(M); 6940 6941 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX())) 6942 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6943 X86::getShufflePALIGNRImmediate(SVOp), 6944 DAG); 6945 6946 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6947 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6948 if (VT == MVT::v2f64) 6949 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); 6950 if (VT == MVT::v2i64) 6951 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 6952 } 6953 6954 if (isPSHUFHWMask(M, VT)) 6955 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6956 X86::getShufflePSHUFHWImmediate(SVOp), 6957 DAG); 6958 6959 if (isPSHUFLWMask(M, VT)) 6960 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6961 X86::getShufflePSHUFLWImmediate(SVOp), 6962 DAG); 6963 6964 if (isSHUFPMask(M, VT)) 6965 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6966 X86::getShuffleSHUFImmediate(SVOp), DAG); 6967 6968 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 6969 return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1, 6970 DAG); 6971 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 6972 return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1, 6973 DAG); 6974 6975 //===--------------------------------------------------------------------===// 6976 // Generate target specific nodes for 128 or 256-bit shuffles only 6977 // supported in the AVX instruction set. 6978 // 6979 6980 // Handle VMOVDDUPY permutations 6981 if (isMOVDDUPYMask(SVOp, Subtarget)) 6982 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6983 6984 // Handle VPERMILPS* permutations 6985 if (isVPERMILPSMask(M, VT, Subtarget)) 6986 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6987 getShuffleVPERMILPSImmediate(SVOp), DAG); 6988 6989 // Handle VPERMILPD* permutations 6990 if (isVPERMILPDMask(M, VT, Subtarget)) 6991 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6992 getShuffleVPERMILPDImmediate(SVOp), DAG); 6993 6994 // Handle VPERM2F128 permutations 6995 if (isVPERM2F128Mask(M, VT, Subtarget)) 6996 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2, 6997 getShuffleVPERM2F128Immediate(SVOp), DAG); 6998 6999 // Handle VSHUFPSY permutations 7000 if (isVSHUFPSYMask(M, VT, Subtarget)) 7001 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 7002 getShuffleVSHUFPSYImmediate(SVOp), DAG); 7003 7004 // Handle VSHUFPDY permutations 7005 if (isVSHUFPDYMask(M, VT, Subtarget)) 7006 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 7007 getShuffleVSHUFPDYImmediate(SVOp), DAG); 7008 7009 // Try to swap operands in the node to match x86 shuffle ops 7010 if (isCommutedVSHUFPMask(M, VT, Subtarget)) { 7011 // Now we need to commute operands. 7012 SVOp = cast<ShuffleVectorSDNode>(CommuteVectorShuffle(SVOp, DAG)); 7013 V1 = SVOp->getOperand(0); 7014 V2 = SVOp->getOperand(1); 7015 unsigned Immediate = (NumElems == 4) ? getShuffleVSHUFPDYImmediate(SVOp): 7016 getShuffleVSHUFPSYImmediate(SVOp); 7017 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, Immediate, DAG); 7018 } 7019 7020 //===--------------------------------------------------------------------===// 7021 // Since no target specific shuffle was selected for this generic one, 7022 // lower it into other known shuffles. FIXME: this isn't true yet, but 7023 // this is the plan. 7024 // 7025 7026 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 7027 if (VT == MVT::v8i16) { 7028 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 7029 if (NewOp.getNode()) 7030 return NewOp; 7031 } 7032 7033 if (VT == MVT::v16i8) { 7034 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 7035 if (NewOp.getNode()) 7036 return NewOp; 7037 } 7038 7039 // Handle all 128-bit wide vectors with 4 elements, and match them with 7040 // several different shuffle types. 7041 if (NumElems == 4 && VT.getSizeInBits() == 128) 7042 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 7043 7044 // Handle general 256-bit shuffles 7045 if (VT.is256BitVector()) 7046 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 7047 7048 return SDValue(); 7049} 7050 7051SDValue 7052X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 7053 SelectionDAG &DAG) const { 7054 EVT VT = Op.getValueType(); 7055 DebugLoc dl = Op.getDebugLoc(); 7056 7057 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 7058 return SDValue(); 7059 7060 if (VT.getSizeInBits() == 8) { 7061 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 7062 Op.getOperand(0), Op.getOperand(1)); 7063 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 7064 DAG.getValueType(VT)); 7065 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7066 } else if (VT.getSizeInBits() == 16) { 7067 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7068 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 7069 if (Idx == 0) 7070 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7071 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7072 DAG.getNode(ISD::BITCAST, dl, 7073 MVT::v4i32, 7074 Op.getOperand(0)), 7075 Op.getOperand(1))); 7076 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 7077 Op.getOperand(0), Op.getOperand(1)); 7078 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 7079 DAG.getValueType(VT)); 7080 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7081 } else if (VT == MVT::f32) { 7082 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 7083 // the result back to FR32 register. It's only worth matching if the 7084 // result has a single use which is a store or a bitcast to i32. And in 7085 // the case of a store, it's not worth it if the index is a constant 0, 7086 // because a MOVSSmr can be used instead, which is smaller and faster. 7087 if (!Op.hasOneUse()) 7088 return SDValue(); 7089 SDNode *User = *Op.getNode()->use_begin(); 7090 if ((User->getOpcode() != ISD::STORE || 7091 (isa<ConstantSDNode>(Op.getOperand(1)) && 7092 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 7093 (User->getOpcode() != ISD::BITCAST || 7094 User->getValueType(0) != MVT::i32)) 7095 return SDValue(); 7096 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7097 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 7098 Op.getOperand(0)), 7099 Op.getOperand(1)); 7100 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 7101 } else if (VT == MVT::i32 || VT == MVT::i64) { 7102 // ExtractPS/pextrq works with constant index. 7103 if (isa<ConstantSDNode>(Op.getOperand(1))) 7104 return Op; 7105 } 7106 return SDValue(); 7107} 7108 7109 7110SDValue 7111X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 7112 SelectionDAG &DAG) const { 7113 if (!isa<ConstantSDNode>(Op.getOperand(1))) 7114 return SDValue(); 7115 7116 SDValue Vec = Op.getOperand(0); 7117 EVT VecVT = Vec.getValueType(); 7118 7119 // If this is a 256-bit vector result, first extract the 128-bit vector and 7120 // then extract the element from the 128-bit vector. 7121 if (VecVT.getSizeInBits() == 256) { 7122 DebugLoc dl = Op.getNode()->getDebugLoc(); 7123 unsigned NumElems = VecVT.getVectorNumElements(); 7124 SDValue Idx = Op.getOperand(1); 7125 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7126 7127 // Get the 128-bit vector. 7128 bool Upper = IdxVal >= NumElems/2; 7129 Vec = Extract128BitVector(Vec, 7130 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 7131 7132 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 7133 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 7134 } 7135 7136 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 7137 7138 if (Subtarget->hasSSE41orAVX()) { 7139 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 7140 if (Res.getNode()) 7141 return Res; 7142 } 7143 7144 EVT VT = Op.getValueType(); 7145 DebugLoc dl = Op.getDebugLoc(); 7146 // TODO: handle v16i8. 7147 if (VT.getSizeInBits() == 16) { 7148 SDValue Vec = Op.getOperand(0); 7149 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7150 if (Idx == 0) 7151 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7152 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7153 DAG.getNode(ISD::BITCAST, dl, 7154 MVT::v4i32, Vec), 7155 Op.getOperand(1))); 7156 // Transform it so it match pextrw which produces a 32-bit result. 7157 EVT EltVT = MVT::i32; 7158 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 7159 Op.getOperand(0), Op.getOperand(1)); 7160 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 7161 DAG.getValueType(VT)); 7162 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7163 } else if (VT.getSizeInBits() == 32) { 7164 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7165 if (Idx == 0) 7166 return Op; 7167 7168 // SHUFPS the element to the lowest double word, then movss. 7169 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 7170 EVT VVT = Op.getOperand(0).getValueType(); 7171 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7172 DAG.getUNDEF(VVT), Mask); 7173 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7174 DAG.getIntPtrConstant(0)); 7175 } else if (VT.getSizeInBits() == 64) { 7176 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 7177 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 7178 // to match extract_elt for f64. 7179 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7180 if (Idx == 0) 7181 return Op; 7182 7183 // UNPCKHPD the element to the lowest double word, then movsd. 7184 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 7185 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 7186 int Mask[2] = { 1, -1 }; 7187 EVT VVT = Op.getOperand(0).getValueType(); 7188 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7189 DAG.getUNDEF(VVT), Mask); 7190 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7191 DAG.getIntPtrConstant(0)); 7192 } 7193 7194 return SDValue(); 7195} 7196 7197SDValue 7198X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 7199 SelectionDAG &DAG) const { 7200 EVT VT = Op.getValueType(); 7201 EVT EltVT = VT.getVectorElementType(); 7202 DebugLoc dl = Op.getDebugLoc(); 7203 7204 SDValue N0 = Op.getOperand(0); 7205 SDValue N1 = Op.getOperand(1); 7206 SDValue N2 = Op.getOperand(2); 7207 7208 if (VT.getSizeInBits() == 256) 7209 return SDValue(); 7210 7211 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 7212 isa<ConstantSDNode>(N2)) { 7213 unsigned Opc; 7214 if (VT == MVT::v8i16) 7215 Opc = X86ISD::PINSRW; 7216 else if (VT == MVT::v16i8) 7217 Opc = X86ISD::PINSRB; 7218 else 7219 Opc = X86ISD::PINSRB; 7220 7221 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 7222 // argument. 7223 if (N1.getValueType() != MVT::i32) 7224 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7225 if (N2.getValueType() != MVT::i32) 7226 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7227 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7228 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7229 // Bits [7:6] of the constant are the source select. This will always be 7230 // zero here. The DAG Combiner may combine an extract_elt index into these 7231 // bits. For example (insert (extract, 3), 2) could be matched by putting 7232 // the '3' into bits [7:6] of X86ISD::INSERTPS. 7233 // Bits [5:4] of the constant are the destination select. This is the 7234 // value of the incoming immediate. 7235 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 7236 // combine either bitwise AND or insert of float 0.0 to set these bits. 7237 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7238 // Create this as a scalar to vector.. 7239 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 7240 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7241 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 7242 isa<ConstantSDNode>(N2)) { 7243 // PINSR* works with constant index. 7244 return Op; 7245 } 7246 return SDValue(); 7247} 7248 7249SDValue 7250X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7251 EVT VT = Op.getValueType(); 7252 EVT EltVT = VT.getVectorElementType(); 7253 7254 DebugLoc dl = Op.getDebugLoc(); 7255 SDValue N0 = Op.getOperand(0); 7256 SDValue N1 = Op.getOperand(1); 7257 SDValue N2 = Op.getOperand(2); 7258 7259 // If this is a 256-bit vector result, first extract the 128-bit vector, 7260 // insert the element into the extracted half and then place it back. 7261 if (VT.getSizeInBits() == 256) { 7262 if (!isa<ConstantSDNode>(N2)) 7263 return SDValue(); 7264 7265 // Get the desired 128-bit vector half. 7266 unsigned NumElems = VT.getVectorNumElements(); 7267 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7268 bool Upper = IdxVal >= NumElems/2; 7269 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 7270 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 7271 7272 // Insert the element into the desired half. 7273 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 7274 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 7275 7276 // Insert the changed part back to the 256-bit vector 7277 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 7278 } 7279 7280 if (Subtarget->hasSSE41orAVX()) 7281 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7282 7283 if (EltVT == MVT::i8) 7284 return SDValue(); 7285 7286 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7287 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7288 // as its second argument. 7289 if (N1.getValueType() != MVT::i32) 7290 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7291 if (N2.getValueType() != MVT::i32) 7292 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7293 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7294 } 7295 return SDValue(); 7296} 7297 7298SDValue 7299X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 7300 LLVMContext *Context = DAG.getContext(); 7301 DebugLoc dl = Op.getDebugLoc(); 7302 EVT OpVT = Op.getValueType(); 7303 7304 // If this is a 256-bit vector result, first insert into a 128-bit 7305 // vector and then insert into the 256-bit vector. 7306 if (OpVT.getSizeInBits() > 128) { 7307 // Insert into a 128-bit vector. 7308 EVT VT128 = EVT::getVectorVT(*Context, 7309 OpVT.getVectorElementType(), 7310 OpVT.getVectorNumElements() / 2); 7311 7312 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7313 7314 // Insert the 128-bit vector. 7315 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7316 DAG.getConstant(0, MVT::i32), 7317 DAG, dl); 7318 } 7319 7320 if (Op.getValueType() == MVT::v1i64 && 7321 Op.getOperand(0).getValueType() == MVT::i64) 7322 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7323 7324 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7325 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7326 "Expected an SSE type!"); 7327 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7328 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7329} 7330 7331// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7332// a simple subregister reference or explicit instructions to grab 7333// upper bits of a vector. 7334SDValue 7335X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7336 if (Subtarget->hasAVX()) { 7337 DebugLoc dl = Op.getNode()->getDebugLoc(); 7338 SDValue Vec = Op.getNode()->getOperand(0); 7339 SDValue Idx = Op.getNode()->getOperand(1); 7340 7341 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7342 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7343 return Extract128BitVector(Vec, Idx, DAG, dl); 7344 } 7345 } 7346 return SDValue(); 7347} 7348 7349// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7350// simple superregister reference or explicit instructions to insert 7351// the upper bits of a vector. 7352SDValue 7353X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7354 if (Subtarget->hasAVX()) { 7355 DebugLoc dl = Op.getNode()->getDebugLoc(); 7356 SDValue Vec = Op.getNode()->getOperand(0); 7357 SDValue SubVec = Op.getNode()->getOperand(1); 7358 SDValue Idx = Op.getNode()->getOperand(2); 7359 7360 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7361 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7362 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7363 } 7364 } 7365 return SDValue(); 7366} 7367 7368// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7369// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7370// one of the above mentioned nodes. It has to be wrapped because otherwise 7371// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7372// be used to form addressing mode. These wrapped nodes will be selected 7373// into MOV32ri. 7374SDValue 7375X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7376 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7377 7378 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7379 // global base reg. 7380 unsigned char OpFlag = 0; 7381 unsigned WrapperKind = X86ISD::Wrapper; 7382 CodeModel::Model M = getTargetMachine().getCodeModel(); 7383 7384 if (Subtarget->isPICStyleRIPRel() && 7385 (M == CodeModel::Small || M == CodeModel::Kernel)) 7386 WrapperKind = X86ISD::WrapperRIP; 7387 else if (Subtarget->isPICStyleGOT()) 7388 OpFlag = X86II::MO_GOTOFF; 7389 else if (Subtarget->isPICStyleStubPIC()) 7390 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7391 7392 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7393 CP->getAlignment(), 7394 CP->getOffset(), OpFlag); 7395 DebugLoc DL = CP->getDebugLoc(); 7396 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7397 // With PIC, the address is actually $g + Offset. 7398 if (OpFlag) { 7399 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7400 DAG.getNode(X86ISD::GlobalBaseReg, 7401 DebugLoc(), getPointerTy()), 7402 Result); 7403 } 7404 7405 return Result; 7406} 7407 7408SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7409 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7410 7411 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7412 // global base reg. 7413 unsigned char OpFlag = 0; 7414 unsigned WrapperKind = X86ISD::Wrapper; 7415 CodeModel::Model M = getTargetMachine().getCodeModel(); 7416 7417 if (Subtarget->isPICStyleRIPRel() && 7418 (M == CodeModel::Small || M == CodeModel::Kernel)) 7419 WrapperKind = X86ISD::WrapperRIP; 7420 else if (Subtarget->isPICStyleGOT()) 7421 OpFlag = X86II::MO_GOTOFF; 7422 else if (Subtarget->isPICStyleStubPIC()) 7423 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7424 7425 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7426 OpFlag); 7427 DebugLoc DL = JT->getDebugLoc(); 7428 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7429 7430 // With PIC, the address is actually $g + Offset. 7431 if (OpFlag) 7432 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7433 DAG.getNode(X86ISD::GlobalBaseReg, 7434 DebugLoc(), getPointerTy()), 7435 Result); 7436 7437 return Result; 7438} 7439 7440SDValue 7441X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7442 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7443 7444 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7445 // global base reg. 7446 unsigned char OpFlag = 0; 7447 unsigned WrapperKind = X86ISD::Wrapper; 7448 CodeModel::Model M = getTargetMachine().getCodeModel(); 7449 7450 if (Subtarget->isPICStyleRIPRel() && 7451 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7452 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7453 OpFlag = X86II::MO_GOTPCREL; 7454 WrapperKind = X86ISD::WrapperRIP; 7455 } else if (Subtarget->isPICStyleGOT()) { 7456 OpFlag = X86II::MO_GOT; 7457 } else if (Subtarget->isPICStyleStubPIC()) { 7458 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7459 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7460 OpFlag = X86II::MO_DARWIN_NONLAZY; 7461 } 7462 7463 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7464 7465 DebugLoc DL = Op.getDebugLoc(); 7466 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7467 7468 7469 // With PIC, the address is actually $g + Offset. 7470 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7471 !Subtarget->is64Bit()) { 7472 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7473 DAG.getNode(X86ISD::GlobalBaseReg, 7474 DebugLoc(), getPointerTy()), 7475 Result); 7476 } 7477 7478 // For symbols that require a load from a stub to get the address, emit the 7479 // load. 7480 if (isGlobalStubReference(OpFlag)) 7481 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7482 MachinePointerInfo::getGOT(), false, false, false, 0); 7483 7484 return Result; 7485} 7486 7487SDValue 7488X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7489 // Create the TargetBlockAddressAddress node. 7490 unsigned char OpFlags = 7491 Subtarget->ClassifyBlockAddressReference(); 7492 CodeModel::Model M = getTargetMachine().getCodeModel(); 7493 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7494 DebugLoc dl = Op.getDebugLoc(); 7495 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7496 /*isTarget=*/true, OpFlags); 7497 7498 if (Subtarget->isPICStyleRIPRel() && 7499 (M == CodeModel::Small || M == CodeModel::Kernel)) 7500 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7501 else 7502 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7503 7504 // With PIC, the address is actually $g + Offset. 7505 if (isGlobalRelativeToPICBase(OpFlags)) { 7506 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7507 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7508 Result); 7509 } 7510 7511 return Result; 7512} 7513 7514SDValue 7515X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7516 int64_t Offset, 7517 SelectionDAG &DAG) const { 7518 // Create the TargetGlobalAddress node, folding in the constant 7519 // offset if it is legal. 7520 unsigned char OpFlags = 7521 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7522 CodeModel::Model M = getTargetMachine().getCodeModel(); 7523 SDValue Result; 7524 if (OpFlags == X86II::MO_NO_FLAG && 7525 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7526 // A direct static reference to a global. 7527 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7528 Offset = 0; 7529 } else { 7530 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7531 } 7532 7533 if (Subtarget->isPICStyleRIPRel() && 7534 (M == CodeModel::Small || M == CodeModel::Kernel)) 7535 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7536 else 7537 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7538 7539 // With PIC, the address is actually $g + Offset. 7540 if (isGlobalRelativeToPICBase(OpFlags)) { 7541 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7542 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7543 Result); 7544 } 7545 7546 // For globals that require a load from a stub to get the address, emit the 7547 // load. 7548 if (isGlobalStubReference(OpFlags)) 7549 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7550 MachinePointerInfo::getGOT(), false, false, false, 0); 7551 7552 // If there was a non-zero offset that we didn't fold, create an explicit 7553 // addition for it. 7554 if (Offset != 0) 7555 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7556 DAG.getConstant(Offset, getPointerTy())); 7557 7558 return Result; 7559} 7560 7561SDValue 7562X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7563 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7564 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7565 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7566} 7567 7568static SDValue 7569GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7570 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7571 unsigned char OperandFlags) { 7572 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7573 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7574 DebugLoc dl = GA->getDebugLoc(); 7575 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7576 GA->getValueType(0), 7577 GA->getOffset(), 7578 OperandFlags); 7579 if (InFlag) { 7580 SDValue Ops[] = { Chain, TGA, *InFlag }; 7581 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7582 } else { 7583 SDValue Ops[] = { Chain, TGA }; 7584 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7585 } 7586 7587 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7588 MFI->setAdjustsStack(true); 7589 7590 SDValue Flag = Chain.getValue(1); 7591 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7592} 7593 7594// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7595static SDValue 7596LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7597 const EVT PtrVT) { 7598 SDValue InFlag; 7599 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7600 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7601 DAG.getNode(X86ISD::GlobalBaseReg, 7602 DebugLoc(), PtrVT), InFlag); 7603 InFlag = Chain.getValue(1); 7604 7605 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7606} 7607 7608// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7609static SDValue 7610LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7611 const EVT PtrVT) { 7612 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7613 X86::RAX, X86II::MO_TLSGD); 7614} 7615 7616// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7617// "local exec" model. 7618static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7619 const EVT PtrVT, TLSModel::Model model, 7620 bool is64Bit) { 7621 DebugLoc dl = GA->getDebugLoc(); 7622 7623 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7624 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7625 is64Bit ? 257 : 256)); 7626 7627 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7628 DAG.getIntPtrConstant(0), 7629 MachinePointerInfo(Ptr), 7630 false, false, false, 0); 7631 7632 unsigned char OperandFlags = 0; 7633 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7634 // initialexec. 7635 unsigned WrapperKind = X86ISD::Wrapper; 7636 if (model == TLSModel::LocalExec) { 7637 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7638 } else if (is64Bit) { 7639 assert(model == TLSModel::InitialExec); 7640 OperandFlags = X86II::MO_GOTTPOFF; 7641 WrapperKind = X86ISD::WrapperRIP; 7642 } else { 7643 assert(model == TLSModel::InitialExec); 7644 OperandFlags = X86II::MO_INDNTPOFF; 7645 } 7646 7647 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7648 // exec) 7649 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7650 GA->getValueType(0), 7651 GA->getOffset(), OperandFlags); 7652 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7653 7654 if (model == TLSModel::InitialExec) 7655 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7656 MachinePointerInfo::getGOT(), false, false, false, 0); 7657 7658 // The address of the thread local variable is the add of the thread 7659 // pointer with the offset of the variable. 7660 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7661} 7662 7663SDValue 7664X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7665 7666 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7667 const GlobalValue *GV = GA->getGlobal(); 7668 7669 if (Subtarget->isTargetELF()) { 7670 // TODO: implement the "local dynamic" model 7671 // TODO: implement the "initial exec"model for pic executables 7672 7673 // If GV is an alias then use the aliasee for determining 7674 // thread-localness. 7675 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7676 GV = GA->resolveAliasedGlobal(false); 7677 7678 TLSModel::Model model 7679 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7680 7681 switch (model) { 7682 case TLSModel::GeneralDynamic: 7683 case TLSModel::LocalDynamic: // not implemented 7684 if (Subtarget->is64Bit()) 7685 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7686 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7687 7688 case TLSModel::InitialExec: 7689 case TLSModel::LocalExec: 7690 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7691 Subtarget->is64Bit()); 7692 } 7693 } else if (Subtarget->isTargetDarwin()) { 7694 // Darwin only has one model of TLS. Lower to that. 7695 unsigned char OpFlag = 0; 7696 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7697 X86ISD::WrapperRIP : X86ISD::Wrapper; 7698 7699 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7700 // global base reg. 7701 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7702 !Subtarget->is64Bit(); 7703 if (PIC32) 7704 OpFlag = X86II::MO_TLVP_PIC_BASE; 7705 else 7706 OpFlag = X86II::MO_TLVP; 7707 DebugLoc DL = Op.getDebugLoc(); 7708 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7709 GA->getValueType(0), 7710 GA->getOffset(), OpFlag); 7711 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7712 7713 // With PIC32, the address is actually $g + Offset. 7714 if (PIC32) 7715 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7716 DAG.getNode(X86ISD::GlobalBaseReg, 7717 DebugLoc(), getPointerTy()), 7718 Offset); 7719 7720 // Lowering the machine isd will make sure everything is in the right 7721 // location. 7722 SDValue Chain = DAG.getEntryNode(); 7723 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7724 SDValue Args[] = { Chain, Offset }; 7725 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7726 7727 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7728 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7729 MFI->setAdjustsStack(true); 7730 7731 // And our return value (tls address) is in the standard call return value 7732 // location. 7733 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7734 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7735 Chain.getValue(1)); 7736 } 7737 7738 assert(false && 7739 "TLS not implemented for this target."); 7740 7741 llvm_unreachable("Unreachable"); 7742 return SDValue(); 7743} 7744 7745 7746/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and 7747/// take a 2 x i32 value to shift plus a shift amount. 7748SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const { 7749 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7750 EVT VT = Op.getValueType(); 7751 unsigned VTBits = VT.getSizeInBits(); 7752 DebugLoc dl = Op.getDebugLoc(); 7753 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7754 SDValue ShOpLo = Op.getOperand(0); 7755 SDValue ShOpHi = Op.getOperand(1); 7756 SDValue ShAmt = Op.getOperand(2); 7757 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7758 DAG.getConstant(VTBits - 1, MVT::i8)) 7759 : DAG.getConstant(0, VT); 7760 7761 SDValue Tmp2, Tmp3; 7762 if (Op.getOpcode() == ISD::SHL_PARTS) { 7763 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7764 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7765 } else { 7766 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7767 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7768 } 7769 7770 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7771 DAG.getConstant(VTBits, MVT::i8)); 7772 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7773 AndNode, DAG.getConstant(0, MVT::i8)); 7774 7775 SDValue Hi, Lo; 7776 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7777 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7778 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7779 7780 if (Op.getOpcode() == ISD::SHL_PARTS) { 7781 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7782 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7783 } else { 7784 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7785 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7786 } 7787 7788 SDValue Ops[2] = { Lo, Hi }; 7789 return DAG.getMergeValues(Ops, 2, dl); 7790} 7791 7792SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7793 SelectionDAG &DAG) const { 7794 EVT SrcVT = Op.getOperand(0).getValueType(); 7795 7796 if (SrcVT.isVector()) 7797 return SDValue(); 7798 7799 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7800 "Unknown SINT_TO_FP to lower!"); 7801 7802 // These are really Legal; return the operand so the caller accepts it as 7803 // Legal. 7804 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7805 return Op; 7806 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7807 Subtarget->is64Bit()) { 7808 return Op; 7809 } 7810 7811 DebugLoc dl = Op.getDebugLoc(); 7812 unsigned Size = SrcVT.getSizeInBits()/8; 7813 MachineFunction &MF = DAG.getMachineFunction(); 7814 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7815 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7816 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7817 StackSlot, 7818 MachinePointerInfo::getFixedStack(SSFI), 7819 false, false, 0); 7820 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7821} 7822 7823SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7824 SDValue StackSlot, 7825 SelectionDAG &DAG) const { 7826 // Build the FILD 7827 DebugLoc DL = Op.getDebugLoc(); 7828 SDVTList Tys; 7829 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7830 if (useSSE) 7831 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7832 else 7833 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7834 7835 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7836 7837 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7838 MachineMemOperand *MMO; 7839 if (FI) { 7840 int SSFI = FI->getIndex(); 7841 MMO = 7842 DAG.getMachineFunction() 7843 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7844 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7845 } else { 7846 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7847 StackSlot = StackSlot.getOperand(1); 7848 } 7849 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7850 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7851 X86ISD::FILD, DL, 7852 Tys, Ops, array_lengthof(Ops), 7853 SrcVT, MMO); 7854 7855 if (useSSE) { 7856 Chain = Result.getValue(1); 7857 SDValue InFlag = Result.getValue(2); 7858 7859 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7860 // shouldn't be necessary except that RFP cannot be live across 7861 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7862 MachineFunction &MF = DAG.getMachineFunction(); 7863 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7864 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7865 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7866 Tys = DAG.getVTList(MVT::Other); 7867 SDValue Ops[] = { 7868 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7869 }; 7870 MachineMemOperand *MMO = 7871 DAG.getMachineFunction() 7872 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7873 MachineMemOperand::MOStore, SSFISize, SSFISize); 7874 7875 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7876 Ops, array_lengthof(Ops), 7877 Op.getValueType(), MMO); 7878 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7879 MachinePointerInfo::getFixedStack(SSFI), 7880 false, false, false, 0); 7881 } 7882 7883 return Result; 7884} 7885 7886// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7887SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7888 SelectionDAG &DAG) const { 7889 // This algorithm is not obvious. Here it is in C code, more or less: 7890 /* 7891 double uint64_to_double( uint32_t hi, uint32_t lo ) { 7892 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 7893 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 7894 7895 // Copy ints to xmm registers. 7896 __m128i xh = _mm_cvtsi32_si128( hi ); 7897 __m128i xl = _mm_cvtsi32_si128( lo ); 7898 7899 // Combine into low half of a single xmm register. 7900 __m128i x = _mm_unpacklo_epi32( xh, xl ); 7901 __m128d d; 7902 double sd; 7903 7904 // Merge in appropriate exponents to give the integer bits the right 7905 // magnitude. 7906 x = _mm_unpacklo_epi32( x, exp ); 7907 7908 // Subtract away the biases to deal with the IEEE-754 double precision 7909 // implicit 1. 7910 d = _mm_sub_pd( (__m128d) x, bias ); 7911 7912 // All conversions up to here are exact. The correctly rounded result is 7913 // calculated using the current rounding mode using the following 7914 // horizontal add. 7915 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 7916 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 7917 // store doesn't really need to be here (except 7918 // maybe to zero the other double) 7919 return sd; 7920 } 7921 */ 7922 7923 DebugLoc dl = Op.getDebugLoc(); 7924 LLVMContext *Context = DAG.getContext(); 7925 7926 // Build some magic constants. 7927 std::vector<Constant*> CV0; 7928 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7929 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7930 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7931 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7932 Constant *C0 = ConstantVector::get(CV0); 7933 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7934 7935 std::vector<Constant*> CV1; 7936 CV1.push_back( 7937 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7938 CV1.push_back( 7939 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7940 Constant *C1 = ConstantVector::get(CV1); 7941 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7942 7943 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7944 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7945 Op.getOperand(0), 7946 DAG.getIntPtrConstant(1))); 7947 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7948 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7949 Op.getOperand(0), 7950 DAG.getIntPtrConstant(0))); 7951 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 7952 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7953 MachinePointerInfo::getConstantPool(), 7954 false, false, false, 16); 7955 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 7956 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 7957 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7958 MachinePointerInfo::getConstantPool(), 7959 false, false, false, 16); 7960 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7961 7962 // Add the halves; easiest way is to swap them into another reg first. 7963 int ShufMask[2] = { 1, -1 }; 7964 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 7965 DAG.getUNDEF(MVT::v2f64), ShufMask); 7966 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 7967 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 7968 DAG.getIntPtrConstant(0)); 7969} 7970 7971// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7972SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7973 SelectionDAG &DAG) const { 7974 DebugLoc dl = Op.getDebugLoc(); 7975 // FP constant to bias correct the final result. 7976 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7977 MVT::f64); 7978 7979 // Load the 32-bit value into an XMM register. 7980 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7981 Op.getOperand(0)); 7982 7983 // Zero out the upper parts of the register. 7984 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(), 7985 DAG); 7986 7987 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7988 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7989 DAG.getIntPtrConstant(0)); 7990 7991 // Or the load with the bias. 7992 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7993 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7994 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7995 MVT::v2f64, Load)), 7996 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7997 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7998 MVT::v2f64, Bias))); 7999 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 8000 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 8001 DAG.getIntPtrConstant(0)); 8002 8003 // Subtract the bias. 8004 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 8005 8006 // Handle final rounding. 8007 EVT DestVT = Op.getValueType(); 8008 8009 if (DestVT.bitsLT(MVT::f64)) { 8010 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 8011 DAG.getIntPtrConstant(0)); 8012 } else if (DestVT.bitsGT(MVT::f64)) { 8013 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 8014 } 8015 8016 // Handle final rounding. 8017 return Sub; 8018} 8019 8020SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 8021 SelectionDAG &DAG) const { 8022 SDValue N0 = Op.getOperand(0); 8023 DebugLoc dl = Op.getDebugLoc(); 8024 8025 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 8026 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 8027 // the optimization here. 8028 if (DAG.SignBitIsZero(N0)) 8029 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 8030 8031 EVT SrcVT = N0.getValueType(); 8032 EVT DstVT = Op.getValueType(); 8033 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 8034 return LowerUINT_TO_FP_i64(Op, DAG); 8035 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 8036 return LowerUINT_TO_FP_i32(Op, DAG); 8037 8038 // Make a 64-bit buffer, and use it to build an FILD. 8039 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 8040 if (SrcVT == MVT::i32) { 8041 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 8042 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 8043 getPointerTy(), StackSlot, WordOff); 8044 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8045 StackSlot, MachinePointerInfo(), 8046 false, false, 0); 8047 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 8048 OffsetSlot, MachinePointerInfo(), 8049 false, false, 0); 8050 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 8051 return Fild; 8052 } 8053 8054 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 8055 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8056 StackSlot, MachinePointerInfo(), 8057 false, false, 0); 8058 // For i64 source, we need to add the appropriate power of 2 if the input 8059 // was negative. This is the same as the optimization in 8060 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 8061 // we must be careful to do the computation in x87 extended precision, not 8062 // in SSE. (The generic code can't know it's OK to do this, or how to.) 8063 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 8064 MachineMemOperand *MMO = 8065 DAG.getMachineFunction() 8066 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8067 MachineMemOperand::MOLoad, 8, 8); 8068 8069 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 8070 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 8071 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 8072 MVT::i64, MMO); 8073 8074 APInt FF(32, 0x5F800000ULL); 8075 8076 // Check whether the sign bit is set. 8077 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 8078 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 8079 ISD::SETLT); 8080 8081 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 8082 SDValue FudgePtr = DAG.getConstantPool( 8083 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 8084 getPointerTy()); 8085 8086 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 8087 SDValue Zero = DAG.getIntPtrConstant(0); 8088 SDValue Four = DAG.getIntPtrConstant(4); 8089 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 8090 Zero, Four); 8091 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 8092 8093 // Load the value out, extending it from f32 to f80. 8094 // FIXME: Avoid the extend by constructing the right constant pool? 8095 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 8096 FudgePtr, MachinePointerInfo::getConstantPool(), 8097 MVT::f32, false, false, 4); 8098 // Extend everything to 80 bits to force it to be done on x87. 8099 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 8100 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 8101} 8102 8103std::pair<SDValue,SDValue> X86TargetLowering:: 8104FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 8105 DebugLoc DL = Op.getDebugLoc(); 8106 8107 EVT DstTy = Op.getValueType(); 8108 8109 if (!IsSigned) { 8110 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 8111 DstTy = MVT::i64; 8112 } 8113 8114 assert(DstTy.getSimpleVT() <= MVT::i64 && 8115 DstTy.getSimpleVT() >= MVT::i16 && 8116 "Unknown FP_TO_SINT to lower!"); 8117 8118 // These are really Legal. 8119 if (DstTy == MVT::i32 && 8120 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8121 return std::make_pair(SDValue(), SDValue()); 8122 if (Subtarget->is64Bit() && 8123 DstTy == MVT::i64 && 8124 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8125 return std::make_pair(SDValue(), SDValue()); 8126 8127 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 8128 // stack slot. 8129 MachineFunction &MF = DAG.getMachineFunction(); 8130 unsigned MemSize = DstTy.getSizeInBits()/8; 8131 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8132 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8133 8134 8135 8136 unsigned Opc; 8137 switch (DstTy.getSimpleVT().SimpleTy) { 8138 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 8139 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 8140 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 8141 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 8142 } 8143 8144 SDValue Chain = DAG.getEntryNode(); 8145 SDValue Value = Op.getOperand(0); 8146 EVT TheVT = Op.getOperand(0).getValueType(); 8147 if (isScalarFPTypeInSSEReg(TheVT)) { 8148 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 8149 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 8150 MachinePointerInfo::getFixedStack(SSFI), 8151 false, false, 0); 8152 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 8153 SDValue Ops[] = { 8154 Chain, StackSlot, DAG.getValueType(TheVT) 8155 }; 8156 8157 MachineMemOperand *MMO = 8158 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8159 MachineMemOperand::MOLoad, MemSize, MemSize); 8160 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 8161 DstTy, MMO); 8162 Chain = Value.getValue(1); 8163 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8164 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8165 } 8166 8167 MachineMemOperand *MMO = 8168 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8169 MachineMemOperand::MOStore, MemSize, MemSize); 8170 8171 // Build the FP_TO_INT*_IN_MEM 8172 SDValue Ops[] = { Chain, Value, StackSlot }; 8173 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 8174 Ops, 3, DstTy, MMO); 8175 8176 return std::make_pair(FIST, StackSlot); 8177} 8178 8179SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 8180 SelectionDAG &DAG) const { 8181 if (Op.getValueType().isVector()) 8182 return SDValue(); 8183 8184 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 8185 SDValue FIST = Vals.first, StackSlot = Vals.second; 8186 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 8187 if (FIST.getNode() == 0) return Op; 8188 8189 // Load the result. 8190 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8191 FIST, StackSlot, MachinePointerInfo(), 8192 false, false, false, 0); 8193} 8194 8195SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 8196 SelectionDAG &DAG) const { 8197 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 8198 SDValue FIST = Vals.first, StackSlot = Vals.second; 8199 assert(FIST.getNode() && "Unexpected failure"); 8200 8201 // Load the result. 8202 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8203 FIST, StackSlot, MachinePointerInfo(), 8204 false, false, false, 0); 8205} 8206 8207SDValue X86TargetLowering::LowerFABS(SDValue Op, 8208 SelectionDAG &DAG) const { 8209 LLVMContext *Context = DAG.getContext(); 8210 DebugLoc dl = Op.getDebugLoc(); 8211 EVT VT = Op.getValueType(); 8212 EVT EltVT = VT; 8213 if (VT.isVector()) 8214 EltVT = VT.getVectorElementType(); 8215 std::vector<Constant*> CV; 8216 if (EltVT == MVT::f64) { 8217 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 8218 CV.push_back(C); 8219 CV.push_back(C); 8220 } else { 8221 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 8222 CV.push_back(C); 8223 CV.push_back(C); 8224 CV.push_back(C); 8225 CV.push_back(C); 8226 } 8227 Constant *C = ConstantVector::get(CV); 8228 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8229 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8230 MachinePointerInfo::getConstantPool(), 8231 false, false, false, 16); 8232 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 8233} 8234 8235SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 8236 LLVMContext *Context = DAG.getContext(); 8237 DebugLoc dl = Op.getDebugLoc(); 8238 EVT VT = Op.getValueType(); 8239 EVT EltVT = VT; 8240 if (VT.isVector()) 8241 EltVT = VT.getVectorElementType(); 8242 std::vector<Constant*> CV; 8243 if (EltVT == MVT::f64) { 8244 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 8245 CV.push_back(C); 8246 CV.push_back(C); 8247 } else { 8248 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 8249 CV.push_back(C); 8250 CV.push_back(C); 8251 CV.push_back(C); 8252 CV.push_back(C); 8253 } 8254 Constant *C = ConstantVector::get(CV); 8255 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8256 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8257 MachinePointerInfo::getConstantPool(), 8258 false, false, false, 16); 8259 if (VT.isVector()) { 8260 return DAG.getNode(ISD::BITCAST, dl, VT, 8261 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 8262 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8263 Op.getOperand(0)), 8264 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 8265 } else { 8266 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8267 } 8268} 8269 8270SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8271 LLVMContext *Context = DAG.getContext(); 8272 SDValue Op0 = Op.getOperand(0); 8273 SDValue Op1 = Op.getOperand(1); 8274 DebugLoc dl = Op.getDebugLoc(); 8275 EVT VT = Op.getValueType(); 8276 EVT SrcVT = Op1.getValueType(); 8277 8278 // If second operand is smaller, extend it first. 8279 if (SrcVT.bitsLT(VT)) { 8280 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8281 SrcVT = VT; 8282 } 8283 // And if it is bigger, shrink it first. 8284 if (SrcVT.bitsGT(VT)) { 8285 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8286 SrcVT = VT; 8287 } 8288 8289 // At this point the operands and the result should have the same 8290 // type, and that won't be f80 since that is not custom lowered. 8291 8292 // First get the sign bit of second operand. 8293 std::vector<Constant*> CV; 8294 if (SrcVT == MVT::f64) { 8295 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8296 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8297 } else { 8298 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8299 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8300 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8301 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8302 } 8303 Constant *C = ConstantVector::get(CV); 8304 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8305 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8306 MachinePointerInfo::getConstantPool(), 8307 false, false, false, 16); 8308 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8309 8310 // Shift sign bit right or left if the two operands have different types. 8311 if (SrcVT.bitsGT(VT)) { 8312 // Op0 is MVT::f32, Op1 is MVT::f64. 8313 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8314 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8315 DAG.getConstant(32, MVT::i32)); 8316 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8317 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8318 DAG.getIntPtrConstant(0)); 8319 } 8320 8321 // Clear first operand sign bit. 8322 CV.clear(); 8323 if (VT == MVT::f64) { 8324 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8325 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8326 } else { 8327 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8328 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8329 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8330 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8331 } 8332 C = ConstantVector::get(CV); 8333 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8334 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8335 MachinePointerInfo::getConstantPool(), 8336 false, false, false, 16); 8337 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8338 8339 // Or the value with the sign bit. 8340 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8341} 8342 8343SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8344 SDValue N0 = Op.getOperand(0); 8345 DebugLoc dl = Op.getDebugLoc(); 8346 EVT VT = Op.getValueType(); 8347 8348 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8349 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8350 DAG.getConstant(1, VT)); 8351 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8352} 8353 8354/// Emit nodes that will be selected as "test Op0,Op0", or something 8355/// equivalent. 8356SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8357 SelectionDAG &DAG) const { 8358 DebugLoc dl = Op.getDebugLoc(); 8359 8360 // CF and OF aren't always set the way we want. Determine which 8361 // of these we need. 8362 bool NeedCF = false; 8363 bool NeedOF = false; 8364 switch (X86CC) { 8365 default: break; 8366 case X86::COND_A: case X86::COND_AE: 8367 case X86::COND_B: case X86::COND_BE: 8368 NeedCF = true; 8369 break; 8370 case X86::COND_G: case X86::COND_GE: 8371 case X86::COND_L: case X86::COND_LE: 8372 case X86::COND_O: case X86::COND_NO: 8373 NeedOF = true; 8374 break; 8375 } 8376 8377 // See if we can use the EFLAGS value from the operand instead of 8378 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8379 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8380 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8381 // Emit a CMP with 0, which is the TEST pattern. 8382 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8383 DAG.getConstant(0, Op.getValueType())); 8384 8385 unsigned Opcode = 0; 8386 unsigned NumOperands = 0; 8387 switch (Op.getNode()->getOpcode()) { 8388 case ISD::ADD: 8389 // Due to an isel shortcoming, be conservative if this add is likely to be 8390 // selected as part of a load-modify-store instruction. When the root node 8391 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8392 // uses of other nodes in the match, such as the ADD in this case. This 8393 // leads to the ADD being left around and reselected, with the result being 8394 // two adds in the output. Alas, even if none our users are stores, that 8395 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8396 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8397 // climbing the DAG back to the root, and it doesn't seem to be worth the 8398 // effort. 8399 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8400 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8401 if (UI->getOpcode() != ISD::CopyToReg && 8402 UI->getOpcode() != ISD::SETCC && 8403 UI->getOpcode() != ISD::STORE) 8404 goto default_case; 8405 8406 if (ConstantSDNode *C = 8407 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8408 // An add of one will be selected as an INC. 8409 if (C->getAPIntValue() == 1) { 8410 Opcode = X86ISD::INC; 8411 NumOperands = 1; 8412 break; 8413 } 8414 8415 // An add of negative one (subtract of one) will be selected as a DEC. 8416 if (C->getAPIntValue().isAllOnesValue()) { 8417 Opcode = X86ISD::DEC; 8418 NumOperands = 1; 8419 break; 8420 } 8421 } 8422 8423 // Otherwise use a regular EFLAGS-setting add. 8424 Opcode = X86ISD::ADD; 8425 NumOperands = 2; 8426 break; 8427 case ISD::AND: { 8428 // If the primary and result isn't used, don't bother using X86ISD::AND, 8429 // because a TEST instruction will be better. 8430 bool NonFlagUse = false; 8431 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8432 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8433 SDNode *User = *UI; 8434 unsigned UOpNo = UI.getOperandNo(); 8435 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8436 // Look pass truncate. 8437 UOpNo = User->use_begin().getOperandNo(); 8438 User = *User->use_begin(); 8439 } 8440 8441 if (User->getOpcode() != ISD::BRCOND && 8442 User->getOpcode() != ISD::SETCC && 8443 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8444 NonFlagUse = true; 8445 break; 8446 } 8447 } 8448 8449 if (!NonFlagUse) 8450 break; 8451 } 8452 // FALL THROUGH 8453 case ISD::SUB: 8454 case ISD::OR: 8455 case ISD::XOR: 8456 // Due to the ISEL shortcoming noted above, be conservative if this op is 8457 // likely to be selected as part of a load-modify-store instruction. 8458 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8459 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8460 if (UI->getOpcode() == ISD::STORE) 8461 goto default_case; 8462 8463 // Otherwise use a regular EFLAGS-setting instruction. 8464 switch (Op.getNode()->getOpcode()) { 8465 default: llvm_unreachable("unexpected operator!"); 8466 case ISD::SUB: Opcode = X86ISD::SUB; break; 8467 case ISD::OR: Opcode = X86ISD::OR; break; 8468 case ISD::XOR: Opcode = X86ISD::XOR; break; 8469 case ISD::AND: Opcode = X86ISD::AND; break; 8470 } 8471 8472 NumOperands = 2; 8473 break; 8474 case X86ISD::ADD: 8475 case X86ISD::SUB: 8476 case X86ISD::INC: 8477 case X86ISD::DEC: 8478 case X86ISD::OR: 8479 case X86ISD::XOR: 8480 case X86ISD::AND: 8481 return SDValue(Op.getNode(), 1); 8482 default: 8483 default_case: 8484 break; 8485 } 8486 8487 if (Opcode == 0) 8488 // Emit a CMP with 0, which is the TEST pattern. 8489 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8490 DAG.getConstant(0, Op.getValueType())); 8491 8492 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8493 SmallVector<SDValue, 4> Ops; 8494 for (unsigned i = 0; i != NumOperands; ++i) 8495 Ops.push_back(Op.getOperand(i)); 8496 8497 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8498 DAG.ReplaceAllUsesWith(Op, New); 8499 return SDValue(New.getNode(), 1); 8500} 8501 8502/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8503/// equivalent. 8504SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8505 SelectionDAG &DAG) const { 8506 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8507 if (C->getAPIntValue() == 0) 8508 return EmitTest(Op0, X86CC, DAG); 8509 8510 DebugLoc dl = Op0.getDebugLoc(); 8511 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8512} 8513 8514/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8515/// if it's possible. 8516SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8517 DebugLoc dl, SelectionDAG &DAG) const { 8518 SDValue Op0 = And.getOperand(0); 8519 SDValue Op1 = And.getOperand(1); 8520 if (Op0.getOpcode() == ISD::TRUNCATE) 8521 Op0 = Op0.getOperand(0); 8522 if (Op1.getOpcode() == ISD::TRUNCATE) 8523 Op1 = Op1.getOperand(0); 8524 8525 SDValue LHS, RHS; 8526 if (Op1.getOpcode() == ISD::SHL) 8527 std::swap(Op0, Op1); 8528 if (Op0.getOpcode() == ISD::SHL) { 8529 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8530 if (And00C->getZExtValue() == 1) { 8531 // If we looked past a truncate, check that it's only truncating away 8532 // known zeros. 8533 unsigned BitWidth = Op0.getValueSizeInBits(); 8534 unsigned AndBitWidth = And.getValueSizeInBits(); 8535 if (BitWidth > AndBitWidth) { 8536 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8537 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8538 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8539 return SDValue(); 8540 } 8541 LHS = Op1; 8542 RHS = Op0.getOperand(1); 8543 } 8544 } else if (Op1.getOpcode() == ISD::Constant) { 8545 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8546 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8547 SDValue AndLHS = Op0; 8548 8549 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8550 LHS = AndLHS.getOperand(0); 8551 RHS = AndLHS.getOperand(1); 8552 } 8553 8554 // Use BT if the immediate can't be encoded in a TEST instruction. 8555 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8556 LHS = AndLHS; 8557 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8558 } 8559 } 8560 8561 if (LHS.getNode()) { 8562 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8563 // instruction. Since the shift amount is in-range-or-undefined, we know 8564 // that doing a bittest on the i32 value is ok. We extend to i32 because 8565 // the encoding for the i16 version is larger than the i32 version. 8566 // Also promote i16 to i32 for performance / code size reason. 8567 if (LHS.getValueType() == MVT::i8 || 8568 LHS.getValueType() == MVT::i16) 8569 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8570 8571 // If the operand types disagree, extend the shift amount to match. Since 8572 // BT ignores high bits (like shifts) we can use anyextend. 8573 if (LHS.getValueType() != RHS.getValueType()) 8574 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8575 8576 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8577 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8578 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8579 DAG.getConstant(Cond, MVT::i8), BT); 8580 } 8581 8582 return SDValue(); 8583} 8584 8585SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8586 8587 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8588 8589 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8590 SDValue Op0 = Op.getOperand(0); 8591 SDValue Op1 = Op.getOperand(1); 8592 DebugLoc dl = Op.getDebugLoc(); 8593 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8594 8595 // Optimize to BT if possible. 8596 // Lower (X & (1 << N)) == 0 to BT(X, N). 8597 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8598 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8599 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8600 Op1.getOpcode() == ISD::Constant && 8601 cast<ConstantSDNode>(Op1)->isNullValue() && 8602 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8603 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8604 if (NewSetCC.getNode()) 8605 return NewSetCC; 8606 } 8607 8608 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8609 // these. 8610 if (Op1.getOpcode() == ISD::Constant && 8611 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8612 cast<ConstantSDNode>(Op1)->isNullValue()) && 8613 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8614 8615 // If the input is a setcc, then reuse the input setcc or use a new one with 8616 // the inverted condition. 8617 if (Op0.getOpcode() == X86ISD::SETCC) { 8618 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8619 bool Invert = (CC == ISD::SETNE) ^ 8620 cast<ConstantSDNode>(Op1)->isNullValue(); 8621 if (!Invert) return Op0; 8622 8623 CCode = X86::GetOppositeBranchCondition(CCode); 8624 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8625 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8626 } 8627 } 8628 8629 bool isFP = Op1.getValueType().isFloatingPoint(); 8630 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8631 if (X86CC == X86::COND_INVALID) 8632 return SDValue(); 8633 8634 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8635 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8636 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8637} 8638 8639// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8640// ones, and then concatenate the result back. 8641static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8642 EVT VT = Op.getValueType(); 8643 8644 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8645 "Unsupported value type for operation"); 8646 8647 int NumElems = VT.getVectorNumElements(); 8648 DebugLoc dl = Op.getDebugLoc(); 8649 SDValue CC = Op.getOperand(2); 8650 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8651 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8652 8653 // Extract the LHS vectors 8654 SDValue LHS = Op.getOperand(0); 8655 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8656 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8657 8658 // Extract the RHS vectors 8659 SDValue RHS = Op.getOperand(1); 8660 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8661 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8662 8663 // Issue the operation on the smaller types and concatenate the result back 8664 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8665 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8666 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8667 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8668 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8669} 8670 8671 8672SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8673 SDValue Cond; 8674 SDValue Op0 = Op.getOperand(0); 8675 SDValue Op1 = Op.getOperand(1); 8676 SDValue CC = Op.getOperand(2); 8677 EVT VT = Op.getValueType(); 8678 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8679 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8680 DebugLoc dl = Op.getDebugLoc(); 8681 8682 if (isFP) { 8683 unsigned SSECC = 8; 8684 EVT EltVT = Op0.getValueType().getVectorElementType(); 8685 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8686 8687 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8688 bool Swap = false; 8689 8690 // SSE Condition code mapping: 8691 // 0 - EQ 8692 // 1 - LT 8693 // 2 - LE 8694 // 3 - UNORD 8695 // 4 - NEQ 8696 // 5 - NLT 8697 // 6 - NLE 8698 // 7 - ORD 8699 switch (SetCCOpcode) { 8700 default: break; 8701 case ISD::SETOEQ: 8702 case ISD::SETEQ: SSECC = 0; break; 8703 case ISD::SETOGT: 8704 case ISD::SETGT: Swap = true; // Fallthrough 8705 case ISD::SETLT: 8706 case ISD::SETOLT: SSECC = 1; break; 8707 case ISD::SETOGE: 8708 case ISD::SETGE: Swap = true; // Fallthrough 8709 case ISD::SETLE: 8710 case ISD::SETOLE: SSECC = 2; break; 8711 case ISD::SETUO: SSECC = 3; break; 8712 case ISD::SETUNE: 8713 case ISD::SETNE: SSECC = 4; break; 8714 case ISD::SETULE: Swap = true; 8715 case ISD::SETUGE: SSECC = 5; break; 8716 case ISD::SETULT: Swap = true; 8717 case ISD::SETUGT: SSECC = 6; break; 8718 case ISD::SETO: SSECC = 7; break; 8719 } 8720 if (Swap) 8721 std::swap(Op0, Op1); 8722 8723 // In the two special cases we can't handle, emit two comparisons. 8724 if (SSECC == 8) { 8725 if (SetCCOpcode == ISD::SETUEQ) { 8726 SDValue UNORD, EQ; 8727 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8728 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8729 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8730 } else if (SetCCOpcode == ISD::SETONE) { 8731 SDValue ORD, NEQ; 8732 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8733 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8734 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8735 } 8736 llvm_unreachable("Illegal FP comparison"); 8737 } 8738 // Handle all other FP comparisons here. 8739 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8740 } 8741 8742 // Break 256-bit integer vector compare into smaller ones. 8743 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8744 return Lower256IntVSETCC(Op, DAG); 8745 8746 // We are handling one of the integer comparisons here. Since SSE only has 8747 // GT and EQ comparisons for integer, swapping operands and multiple 8748 // operations may be required for some comparisons. 8749 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 8750 bool Swap = false, Invert = false, FlipSigns = false; 8751 8752 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 8753 default: break; 8754 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8755 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8756 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8757 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8758 } 8759 8760 switch (SetCCOpcode) { 8761 default: break; 8762 case ISD::SETNE: Invert = true; 8763 case ISD::SETEQ: Opc = EQOpc; break; 8764 case ISD::SETLT: Swap = true; 8765 case ISD::SETGT: Opc = GTOpc; break; 8766 case ISD::SETGE: Swap = true; 8767 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8768 case ISD::SETULT: Swap = true; 8769 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8770 case ISD::SETUGE: Swap = true; 8771 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8772 } 8773 if (Swap) 8774 std::swap(Op0, Op1); 8775 8776 // Check that the operation in question is available (most are plain SSE2, 8777 // but PCMPGTQ and PCMPEQQ have different requirements). 8778 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42orAVX()) 8779 return SDValue(); 8780 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41orAVX()) 8781 return SDValue(); 8782 8783 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8784 // bits of the inputs before performing those operations. 8785 if (FlipSigns) { 8786 EVT EltVT = VT.getVectorElementType(); 8787 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8788 EltVT); 8789 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8790 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8791 SignBits.size()); 8792 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8793 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8794 } 8795 8796 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8797 8798 // If the logical-not of the result is required, perform that now. 8799 if (Invert) 8800 Result = DAG.getNOT(dl, Result, VT); 8801 8802 return Result; 8803} 8804 8805// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8806static bool isX86LogicalCmp(SDValue Op) { 8807 unsigned Opc = Op.getNode()->getOpcode(); 8808 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8809 return true; 8810 if (Op.getResNo() == 1 && 8811 (Opc == X86ISD::ADD || 8812 Opc == X86ISD::SUB || 8813 Opc == X86ISD::ADC || 8814 Opc == X86ISD::SBB || 8815 Opc == X86ISD::SMUL || 8816 Opc == X86ISD::UMUL || 8817 Opc == X86ISD::INC || 8818 Opc == X86ISD::DEC || 8819 Opc == X86ISD::OR || 8820 Opc == X86ISD::XOR || 8821 Opc == X86ISD::AND)) 8822 return true; 8823 8824 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8825 return true; 8826 8827 return false; 8828} 8829 8830static bool isZero(SDValue V) { 8831 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8832 return C && C->isNullValue(); 8833} 8834 8835static bool isAllOnes(SDValue V) { 8836 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8837 return C && C->isAllOnesValue(); 8838} 8839 8840SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8841 bool addTest = true; 8842 SDValue Cond = Op.getOperand(0); 8843 SDValue Op1 = Op.getOperand(1); 8844 SDValue Op2 = Op.getOperand(2); 8845 DebugLoc DL = Op.getDebugLoc(); 8846 SDValue CC; 8847 8848 if (Cond.getOpcode() == ISD::SETCC) { 8849 SDValue NewCond = LowerSETCC(Cond, DAG); 8850 if (NewCond.getNode()) 8851 Cond = NewCond; 8852 } 8853 8854 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8855 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8856 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8857 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8858 if (Cond.getOpcode() == X86ISD::SETCC && 8859 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8860 isZero(Cond.getOperand(1).getOperand(1))) { 8861 SDValue Cmp = Cond.getOperand(1); 8862 8863 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8864 8865 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8866 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8867 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8868 8869 SDValue CmpOp0 = Cmp.getOperand(0); 8870 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8871 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8872 8873 SDValue Res = // Res = 0 or -1. 8874 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8875 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8876 8877 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8878 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8879 8880 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8881 if (N2C == 0 || !N2C->isNullValue()) 8882 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8883 return Res; 8884 } 8885 } 8886 8887 // Look past (and (setcc_carry (cmp ...)), 1). 8888 if (Cond.getOpcode() == ISD::AND && 8889 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8890 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8891 if (C && C->getAPIntValue() == 1) 8892 Cond = Cond.getOperand(0); 8893 } 8894 8895 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8896 // setting operand in place of the X86ISD::SETCC. 8897 unsigned CondOpcode = Cond.getOpcode(); 8898 if (CondOpcode == X86ISD::SETCC || 8899 CondOpcode == X86ISD::SETCC_CARRY) { 8900 CC = Cond.getOperand(0); 8901 8902 SDValue Cmp = Cond.getOperand(1); 8903 unsigned Opc = Cmp.getOpcode(); 8904 EVT VT = Op.getValueType(); 8905 8906 bool IllegalFPCMov = false; 8907 if (VT.isFloatingPoint() && !VT.isVector() && 8908 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8909 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8910 8911 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8912 Opc == X86ISD::BT) { // FIXME 8913 Cond = Cmp; 8914 addTest = false; 8915 } 8916 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8917 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8918 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8919 Cond.getOperand(0).getValueType() != MVT::i8)) { 8920 SDValue LHS = Cond.getOperand(0); 8921 SDValue RHS = Cond.getOperand(1); 8922 unsigned X86Opcode; 8923 unsigned X86Cond; 8924 SDVTList VTs; 8925 switch (CondOpcode) { 8926 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8927 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8928 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8929 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8930 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8931 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8932 default: llvm_unreachable("unexpected overflowing operator"); 8933 } 8934 if (CondOpcode == ISD::UMULO) 8935 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8936 MVT::i32); 8937 else 8938 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8939 8940 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8941 8942 if (CondOpcode == ISD::UMULO) 8943 Cond = X86Op.getValue(2); 8944 else 8945 Cond = X86Op.getValue(1); 8946 8947 CC = DAG.getConstant(X86Cond, MVT::i8); 8948 addTest = false; 8949 } 8950 8951 if (addTest) { 8952 // Look pass the truncate. 8953 if (Cond.getOpcode() == ISD::TRUNCATE) 8954 Cond = Cond.getOperand(0); 8955 8956 // We know the result of AND is compared against zero. Try to match 8957 // it to BT. 8958 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8959 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8960 if (NewSetCC.getNode()) { 8961 CC = NewSetCC.getOperand(0); 8962 Cond = NewSetCC.getOperand(1); 8963 addTest = false; 8964 } 8965 } 8966 } 8967 8968 if (addTest) { 8969 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8970 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8971 } 8972 8973 // a < b ? -1 : 0 -> RES = ~setcc_carry 8974 // a < b ? 0 : -1 -> RES = setcc_carry 8975 // a >= b ? -1 : 0 -> RES = setcc_carry 8976 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8977 if (Cond.getOpcode() == X86ISD::CMP) { 8978 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8979 8980 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8981 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8982 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8983 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8984 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8985 return DAG.getNOT(DL, Res, Res.getValueType()); 8986 return Res; 8987 } 8988 } 8989 8990 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8991 // condition is true. 8992 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8993 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8994 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8995} 8996 8997// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8998// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8999// from the AND / OR. 9000static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 9001 Opc = Op.getOpcode(); 9002 if (Opc != ISD::OR && Opc != ISD::AND) 9003 return false; 9004 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 9005 Op.getOperand(0).hasOneUse() && 9006 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 9007 Op.getOperand(1).hasOneUse()); 9008} 9009 9010// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 9011// 1 and that the SETCC node has a single use. 9012static bool isXor1OfSetCC(SDValue Op) { 9013 if (Op.getOpcode() != ISD::XOR) 9014 return false; 9015 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 9016 if (N1C && N1C->getAPIntValue() == 1) { 9017 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 9018 Op.getOperand(0).hasOneUse(); 9019 } 9020 return false; 9021} 9022 9023SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 9024 bool addTest = true; 9025 SDValue Chain = Op.getOperand(0); 9026 SDValue Cond = Op.getOperand(1); 9027 SDValue Dest = Op.getOperand(2); 9028 DebugLoc dl = Op.getDebugLoc(); 9029 SDValue CC; 9030 bool Inverted = false; 9031 9032 if (Cond.getOpcode() == ISD::SETCC) { 9033 // Check for setcc([su]{add,sub,mul}o == 0). 9034 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 9035 isa<ConstantSDNode>(Cond.getOperand(1)) && 9036 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 9037 Cond.getOperand(0).getResNo() == 1 && 9038 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 9039 Cond.getOperand(0).getOpcode() == ISD::UADDO || 9040 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 9041 Cond.getOperand(0).getOpcode() == ISD::USUBO || 9042 Cond.getOperand(0).getOpcode() == ISD::SMULO || 9043 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 9044 Inverted = true; 9045 Cond = Cond.getOperand(0); 9046 } else { 9047 SDValue NewCond = LowerSETCC(Cond, DAG); 9048 if (NewCond.getNode()) 9049 Cond = NewCond; 9050 } 9051 } 9052#if 0 9053 // FIXME: LowerXALUO doesn't handle these!! 9054 else if (Cond.getOpcode() == X86ISD::ADD || 9055 Cond.getOpcode() == X86ISD::SUB || 9056 Cond.getOpcode() == X86ISD::SMUL || 9057 Cond.getOpcode() == X86ISD::UMUL) 9058 Cond = LowerXALUO(Cond, DAG); 9059#endif 9060 9061 // Look pass (and (setcc_carry (cmp ...)), 1). 9062 if (Cond.getOpcode() == ISD::AND && 9063 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 9064 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 9065 if (C && C->getAPIntValue() == 1) 9066 Cond = Cond.getOperand(0); 9067 } 9068 9069 // If condition flag is set by a X86ISD::CMP, then use it as the condition 9070 // setting operand in place of the X86ISD::SETCC. 9071 unsigned CondOpcode = Cond.getOpcode(); 9072 if (CondOpcode == X86ISD::SETCC || 9073 CondOpcode == X86ISD::SETCC_CARRY) { 9074 CC = Cond.getOperand(0); 9075 9076 SDValue Cmp = Cond.getOperand(1); 9077 unsigned Opc = Cmp.getOpcode(); 9078 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 9079 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 9080 Cond = Cmp; 9081 addTest = false; 9082 } else { 9083 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 9084 default: break; 9085 case X86::COND_O: 9086 case X86::COND_B: 9087 // These can only come from an arithmetic instruction with overflow, 9088 // e.g. SADDO, UADDO. 9089 Cond = Cond.getNode()->getOperand(1); 9090 addTest = false; 9091 break; 9092 } 9093 } 9094 } 9095 CondOpcode = Cond.getOpcode(); 9096 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 9097 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 9098 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 9099 Cond.getOperand(0).getValueType() != MVT::i8)) { 9100 SDValue LHS = Cond.getOperand(0); 9101 SDValue RHS = Cond.getOperand(1); 9102 unsigned X86Opcode; 9103 unsigned X86Cond; 9104 SDVTList VTs; 9105 switch (CondOpcode) { 9106 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 9107 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 9108 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 9109 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 9110 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 9111 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 9112 default: llvm_unreachable("unexpected overflowing operator"); 9113 } 9114 if (Inverted) 9115 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 9116 if (CondOpcode == ISD::UMULO) 9117 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 9118 MVT::i32); 9119 else 9120 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 9121 9122 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 9123 9124 if (CondOpcode == ISD::UMULO) 9125 Cond = X86Op.getValue(2); 9126 else 9127 Cond = X86Op.getValue(1); 9128 9129 CC = DAG.getConstant(X86Cond, MVT::i8); 9130 addTest = false; 9131 } else { 9132 unsigned CondOpc; 9133 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 9134 SDValue Cmp = Cond.getOperand(0).getOperand(1); 9135 if (CondOpc == ISD::OR) { 9136 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 9137 // two branches instead of an explicit OR instruction with a 9138 // separate test. 9139 if (Cmp == Cond.getOperand(1).getOperand(1) && 9140 isX86LogicalCmp(Cmp)) { 9141 CC = Cond.getOperand(0).getOperand(0); 9142 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9143 Chain, Dest, CC, Cmp); 9144 CC = Cond.getOperand(1).getOperand(0); 9145 Cond = Cmp; 9146 addTest = false; 9147 } 9148 } else { // ISD::AND 9149 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 9150 // two branches instead of an explicit AND instruction with a 9151 // separate test. However, we only do this if this block doesn't 9152 // have a fall-through edge, because this requires an explicit 9153 // jmp when the condition is false. 9154 if (Cmp == Cond.getOperand(1).getOperand(1) && 9155 isX86LogicalCmp(Cmp) && 9156 Op.getNode()->hasOneUse()) { 9157 X86::CondCode CCode = 9158 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9159 CCode = X86::GetOppositeBranchCondition(CCode); 9160 CC = DAG.getConstant(CCode, MVT::i8); 9161 SDNode *User = *Op.getNode()->use_begin(); 9162 // Look for an unconditional branch following this conditional branch. 9163 // We need this because we need to reverse the successors in order 9164 // to implement FCMP_OEQ. 9165 if (User->getOpcode() == ISD::BR) { 9166 SDValue FalseBB = User->getOperand(1); 9167 SDNode *NewBR = 9168 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9169 assert(NewBR == User); 9170 (void)NewBR; 9171 Dest = FalseBB; 9172 9173 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9174 Chain, Dest, CC, Cmp); 9175 X86::CondCode CCode = 9176 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 9177 CCode = X86::GetOppositeBranchCondition(CCode); 9178 CC = DAG.getConstant(CCode, MVT::i8); 9179 Cond = Cmp; 9180 addTest = false; 9181 } 9182 } 9183 } 9184 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 9185 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 9186 // It should be transformed during dag combiner except when the condition 9187 // is set by a arithmetics with overflow node. 9188 X86::CondCode CCode = 9189 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9190 CCode = X86::GetOppositeBranchCondition(CCode); 9191 CC = DAG.getConstant(CCode, MVT::i8); 9192 Cond = Cond.getOperand(0).getOperand(1); 9193 addTest = false; 9194 } else if (Cond.getOpcode() == ISD::SETCC && 9195 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 9196 // For FCMP_OEQ, we can emit 9197 // two branches instead of an explicit AND instruction with a 9198 // separate test. However, we only do this if this block doesn't 9199 // have a fall-through edge, because this requires an explicit 9200 // jmp when the condition is false. 9201 if (Op.getNode()->hasOneUse()) { 9202 SDNode *User = *Op.getNode()->use_begin(); 9203 // Look for an unconditional branch following this conditional branch. 9204 // We need this because we need to reverse the successors in order 9205 // to implement FCMP_OEQ. 9206 if (User->getOpcode() == ISD::BR) { 9207 SDValue FalseBB = User->getOperand(1); 9208 SDNode *NewBR = 9209 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9210 assert(NewBR == User); 9211 (void)NewBR; 9212 Dest = FalseBB; 9213 9214 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9215 Cond.getOperand(0), Cond.getOperand(1)); 9216 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9217 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9218 Chain, Dest, CC, Cmp); 9219 CC = DAG.getConstant(X86::COND_P, MVT::i8); 9220 Cond = Cmp; 9221 addTest = false; 9222 } 9223 } 9224 } else if (Cond.getOpcode() == ISD::SETCC && 9225 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 9226 // For FCMP_UNE, we can emit 9227 // two branches instead of an explicit AND instruction with a 9228 // separate test. However, we only do this if this block doesn't 9229 // have a fall-through edge, because this requires an explicit 9230 // jmp when the condition is false. 9231 if (Op.getNode()->hasOneUse()) { 9232 SDNode *User = *Op.getNode()->use_begin(); 9233 // Look for an unconditional branch following this conditional branch. 9234 // We need this because we need to reverse the successors in order 9235 // to implement FCMP_UNE. 9236 if (User->getOpcode() == ISD::BR) { 9237 SDValue FalseBB = User->getOperand(1); 9238 SDNode *NewBR = 9239 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9240 assert(NewBR == User); 9241 (void)NewBR; 9242 9243 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9244 Cond.getOperand(0), Cond.getOperand(1)); 9245 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9246 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9247 Chain, Dest, CC, Cmp); 9248 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 9249 Cond = Cmp; 9250 addTest = false; 9251 Dest = FalseBB; 9252 } 9253 } 9254 } 9255 } 9256 9257 if (addTest) { 9258 // Look pass the truncate. 9259 if (Cond.getOpcode() == ISD::TRUNCATE) 9260 Cond = Cond.getOperand(0); 9261 9262 // We know the result of AND is compared against zero. Try to match 9263 // it to BT. 9264 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9265 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 9266 if (NewSetCC.getNode()) { 9267 CC = NewSetCC.getOperand(0); 9268 Cond = NewSetCC.getOperand(1); 9269 addTest = false; 9270 } 9271 } 9272 } 9273 9274 if (addTest) { 9275 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9276 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9277 } 9278 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9279 Chain, Dest, CC, Cond); 9280} 9281 9282 9283// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 9284// Calls to _alloca is needed to probe the stack when allocating more than 4k 9285// bytes in one go. Touching the stack at 4K increments is necessary to ensure 9286// that the guard pages used by the OS virtual memory manager are allocated in 9287// correct sequence. 9288SDValue 9289X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 9290 SelectionDAG &DAG) const { 9291 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 9292 EnableSegmentedStacks) && 9293 "This should be used only on Windows targets or when segmented stacks " 9294 "are being used"); 9295 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9296 DebugLoc dl = Op.getDebugLoc(); 9297 9298 // Get the inputs. 9299 SDValue Chain = Op.getOperand(0); 9300 SDValue Size = Op.getOperand(1); 9301 // FIXME: Ensure alignment here 9302 9303 bool Is64Bit = Subtarget->is64Bit(); 9304 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9305 9306 if (EnableSegmentedStacks) { 9307 MachineFunction &MF = DAG.getMachineFunction(); 9308 MachineRegisterInfo &MRI = MF.getRegInfo(); 9309 9310 if (Is64Bit) { 9311 // The 64 bit implementation of segmented stacks needs to clobber both r10 9312 // r11. This makes it impossible to use it along with nested parameters. 9313 const Function *F = MF.getFunction(); 9314 9315 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9316 I != E; I++) 9317 if (I->hasNestAttr()) 9318 report_fatal_error("Cannot use segmented stacks with functions that " 9319 "have nested arguments."); 9320 } 9321 9322 const TargetRegisterClass *AddrRegClass = 9323 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9324 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9325 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9326 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9327 DAG.getRegister(Vreg, SPTy)); 9328 SDValue Ops1[2] = { Value, Chain }; 9329 return DAG.getMergeValues(Ops1, 2, dl); 9330 } else { 9331 SDValue Flag; 9332 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9333 9334 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9335 Flag = Chain.getValue(1); 9336 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9337 9338 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9339 Flag = Chain.getValue(1); 9340 9341 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9342 9343 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9344 return DAG.getMergeValues(Ops1, 2, dl); 9345 } 9346} 9347 9348SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9349 MachineFunction &MF = DAG.getMachineFunction(); 9350 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9351 9352 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9353 DebugLoc DL = Op.getDebugLoc(); 9354 9355 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9356 // vastart just stores the address of the VarArgsFrameIndex slot into the 9357 // memory location argument. 9358 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9359 getPointerTy()); 9360 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9361 MachinePointerInfo(SV), false, false, 0); 9362 } 9363 9364 // __va_list_tag: 9365 // gp_offset (0 - 6 * 8) 9366 // fp_offset (48 - 48 + 8 * 16) 9367 // overflow_arg_area (point to parameters coming in memory). 9368 // reg_save_area 9369 SmallVector<SDValue, 8> MemOps; 9370 SDValue FIN = Op.getOperand(1); 9371 // Store gp_offset 9372 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9373 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9374 MVT::i32), 9375 FIN, MachinePointerInfo(SV), false, false, 0); 9376 MemOps.push_back(Store); 9377 9378 // Store fp_offset 9379 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9380 FIN, DAG.getIntPtrConstant(4)); 9381 Store = DAG.getStore(Op.getOperand(0), DL, 9382 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9383 MVT::i32), 9384 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9385 MemOps.push_back(Store); 9386 9387 // Store ptr to overflow_arg_area 9388 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9389 FIN, DAG.getIntPtrConstant(4)); 9390 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9391 getPointerTy()); 9392 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9393 MachinePointerInfo(SV, 8), 9394 false, false, 0); 9395 MemOps.push_back(Store); 9396 9397 // Store ptr to reg_save_area. 9398 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9399 FIN, DAG.getIntPtrConstant(8)); 9400 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9401 getPointerTy()); 9402 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9403 MachinePointerInfo(SV, 16), false, false, 0); 9404 MemOps.push_back(Store); 9405 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9406 &MemOps[0], MemOps.size()); 9407} 9408 9409SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9410 assert(Subtarget->is64Bit() && 9411 "LowerVAARG only handles 64-bit va_arg!"); 9412 assert((Subtarget->isTargetLinux() || 9413 Subtarget->isTargetDarwin()) && 9414 "Unhandled target in LowerVAARG"); 9415 assert(Op.getNode()->getNumOperands() == 4); 9416 SDValue Chain = Op.getOperand(0); 9417 SDValue SrcPtr = Op.getOperand(1); 9418 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9419 unsigned Align = Op.getConstantOperandVal(3); 9420 DebugLoc dl = Op.getDebugLoc(); 9421 9422 EVT ArgVT = Op.getNode()->getValueType(0); 9423 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9424 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9425 uint8_t ArgMode; 9426 9427 // Decide which area this value should be read from. 9428 // TODO: Implement the AMD64 ABI in its entirety. This simple 9429 // selection mechanism works only for the basic types. 9430 if (ArgVT == MVT::f80) { 9431 llvm_unreachable("va_arg for f80 not yet implemented"); 9432 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9433 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9434 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9435 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9436 } else { 9437 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9438 } 9439 9440 if (ArgMode == 2) { 9441 // Sanity Check: Make sure using fp_offset makes sense. 9442 assert(!UseSoftFloat && 9443 !(DAG.getMachineFunction() 9444 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9445 Subtarget->hasXMM()); 9446 } 9447 9448 // Insert VAARG_64 node into the DAG 9449 // VAARG_64 returns two values: Variable Argument Address, Chain 9450 SmallVector<SDValue, 11> InstOps; 9451 InstOps.push_back(Chain); 9452 InstOps.push_back(SrcPtr); 9453 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9454 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9455 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9456 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9457 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9458 VTs, &InstOps[0], InstOps.size(), 9459 MVT::i64, 9460 MachinePointerInfo(SV), 9461 /*Align=*/0, 9462 /*Volatile=*/false, 9463 /*ReadMem=*/true, 9464 /*WriteMem=*/true); 9465 Chain = VAARG.getValue(1); 9466 9467 // Load the next argument and return it 9468 return DAG.getLoad(ArgVT, dl, 9469 Chain, 9470 VAARG, 9471 MachinePointerInfo(), 9472 false, false, false, 0); 9473} 9474 9475SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9476 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9477 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9478 SDValue Chain = Op.getOperand(0); 9479 SDValue DstPtr = Op.getOperand(1); 9480 SDValue SrcPtr = Op.getOperand(2); 9481 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9482 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9483 DebugLoc DL = Op.getDebugLoc(); 9484 9485 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9486 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9487 false, 9488 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9489} 9490 9491SDValue 9492X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9493 DebugLoc dl = Op.getDebugLoc(); 9494 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9495 switch (IntNo) { 9496 default: return SDValue(); // Don't custom lower most intrinsics. 9497 // Comparison intrinsics. 9498 case Intrinsic::x86_sse_comieq_ss: 9499 case Intrinsic::x86_sse_comilt_ss: 9500 case Intrinsic::x86_sse_comile_ss: 9501 case Intrinsic::x86_sse_comigt_ss: 9502 case Intrinsic::x86_sse_comige_ss: 9503 case Intrinsic::x86_sse_comineq_ss: 9504 case Intrinsic::x86_sse_ucomieq_ss: 9505 case Intrinsic::x86_sse_ucomilt_ss: 9506 case Intrinsic::x86_sse_ucomile_ss: 9507 case Intrinsic::x86_sse_ucomigt_ss: 9508 case Intrinsic::x86_sse_ucomige_ss: 9509 case Intrinsic::x86_sse_ucomineq_ss: 9510 case Intrinsic::x86_sse2_comieq_sd: 9511 case Intrinsic::x86_sse2_comilt_sd: 9512 case Intrinsic::x86_sse2_comile_sd: 9513 case Intrinsic::x86_sse2_comigt_sd: 9514 case Intrinsic::x86_sse2_comige_sd: 9515 case Intrinsic::x86_sse2_comineq_sd: 9516 case Intrinsic::x86_sse2_ucomieq_sd: 9517 case Intrinsic::x86_sse2_ucomilt_sd: 9518 case Intrinsic::x86_sse2_ucomile_sd: 9519 case Intrinsic::x86_sse2_ucomigt_sd: 9520 case Intrinsic::x86_sse2_ucomige_sd: 9521 case Intrinsic::x86_sse2_ucomineq_sd: { 9522 unsigned Opc = 0; 9523 ISD::CondCode CC = ISD::SETCC_INVALID; 9524 switch (IntNo) { 9525 default: break; 9526 case Intrinsic::x86_sse_comieq_ss: 9527 case Intrinsic::x86_sse2_comieq_sd: 9528 Opc = X86ISD::COMI; 9529 CC = ISD::SETEQ; 9530 break; 9531 case Intrinsic::x86_sse_comilt_ss: 9532 case Intrinsic::x86_sse2_comilt_sd: 9533 Opc = X86ISD::COMI; 9534 CC = ISD::SETLT; 9535 break; 9536 case Intrinsic::x86_sse_comile_ss: 9537 case Intrinsic::x86_sse2_comile_sd: 9538 Opc = X86ISD::COMI; 9539 CC = ISD::SETLE; 9540 break; 9541 case Intrinsic::x86_sse_comigt_ss: 9542 case Intrinsic::x86_sse2_comigt_sd: 9543 Opc = X86ISD::COMI; 9544 CC = ISD::SETGT; 9545 break; 9546 case Intrinsic::x86_sse_comige_ss: 9547 case Intrinsic::x86_sse2_comige_sd: 9548 Opc = X86ISD::COMI; 9549 CC = ISD::SETGE; 9550 break; 9551 case Intrinsic::x86_sse_comineq_ss: 9552 case Intrinsic::x86_sse2_comineq_sd: 9553 Opc = X86ISD::COMI; 9554 CC = ISD::SETNE; 9555 break; 9556 case Intrinsic::x86_sse_ucomieq_ss: 9557 case Intrinsic::x86_sse2_ucomieq_sd: 9558 Opc = X86ISD::UCOMI; 9559 CC = ISD::SETEQ; 9560 break; 9561 case Intrinsic::x86_sse_ucomilt_ss: 9562 case Intrinsic::x86_sse2_ucomilt_sd: 9563 Opc = X86ISD::UCOMI; 9564 CC = ISD::SETLT; 9565 break; 9566 case Intrinsic::x86_sse_ucomile_ss: 9567 case Intrinsic::x86_sse2_ucomile_sd: 9568 Opc = X86ISD::UCOMI; 9569 CC = ISD::SETLE; 9570 break; 9571 case Intrinsic::x86_sse_ucomigt_ss: 9572 case Intrinsic::x86_sse2_ucomigt_sd: 9573 Opc = X86ISD::UCOMI; 9574 CC = ISD::SETGT; 9575 break; 9576 case Intrinsic::x86_sse_ucomige_ss: 9577 case Intrinsic::x86_sse2_ucomige_sd: 9578 Opc = X86ISD::UCOMI; 9579 CC = ISD::SETGE; 9580 break; 9581 case Intrinsic::x86_sse_ucomineq_ss: 9582 case Intrinsic::x86_sse2_ucomineq_sd: 9583 Opc = X86ISD::UCOMI; 9584 CC = ISD::SETNE; 9585 break; 9586 } 9587 9588 SDValue LHS = Op.getOperand(1); 9589 SDValue RHS = Op.getOperand(2); 9590 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9591 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9592 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9593 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9594 DAG.getConstant(X86CC, MVT::i8), Cond); 9595 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9596 } 9597 // Arithmetic intrinsics. 9598 case Intrinsic::x86_sse3_hadd_ps: 9599 case Intrinsic::x86_sse3_hadd_pd: 9600 case Intrinsic::x86_avx_hadd_ps_256: 9601 case Intrinsic::x86_avx_hadd_pd_256: 9602 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9603 Op.getOperand(1), Op.getOperand(2)); 9604 case Intrinsic::x86_sse3_hsub_ps: 9605 case Intrinsic::x86_sse3_hsub_pd: 9606 case Intrinsic::x86_avx_hsub_ps_256: 9607 case Intrinsic::x86_avx_hsub_pd_256: 9608 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9609 Op.getOperand(1), Op.getOperand(2)); 9610 case Intrinsic::x86_avx2_psllv_d: 9611 case Intrinsic::x86_avx2_psllv_q: 9612 case Intrinsic::x86_avx2_psllv_d_256: 9613 case Intrinsic::x86_avx2_psllv_q_256: 9614 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9615 Op.getOperand(1), Op.getOperand(2)); 9616 case Intrinsic::x86_avx2_psrlv_d: 9617 case Intrinsic::x86_avx2_psrlv_q: 9618 case Intrinsic::x86_avx2_psrlv_d_256: 9619 case Intrinsic::x86_avx2_psrlv_q_256: 9620 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9621 Op.getOperand(1), Op.getOperand(2)); 9622 case Intrinsic::x86_avx2_psrav_d: 9623 case Intrinsic::x86_avx2_psrav_d_256: 9624 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9625 Op.getOperand(1), Op.getOperand(2)); 9626 9627 // ptest and testp intrinsics. The intrinsic these come from are designed to 9628 // return an integer value, not just an instruction so lower it to the ptest 9629 // or testp pattern and a setcc for the result. 9630 case Intrinsic::x86_sse41_ptestz: 9631 case Intrinsic::x86_sse41_ptestc: 9632 case Intrinsic::x86_sse41_ptestnzc: 9633 case Intrinsic::x86_avx_ptestz_256: 9634 case Intrinsic::x86_avx_ptestc_256: 9635 case Intrinsic::x86_avx_ptestnzc_256: 9636 case Intrinsic::x86_avx_vtestz_ps: 9637 case Intrinsic::x86_avx_vtestc_ps: 9638 case Intrinsic::x86_avx_vtestnzc_ps: 9639 case Intrinsic::x86_avx_vtestz_pd: 9640 case Intrinsic::x86_avx_vtestc_pd: 9641 case Intrinsic::x86_avx_vtestnzc_pd: 9642 case Intrinsic::x86_avx_vtestz_ps_256: 9643 case Intrinsic::x86_avx_vtestc_ps_256: 9644 case Intrinsic::x86_avx_vtestnzc_ps_256: 9645 case Intrinsic::x86_avx_vtestz_pd_256: 9646 case Intrinsic::x86_avx_vtestc_pd_256: 9647 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9648 bool IsTestPacked = false; 9649 unsigned X86CC = 0; 9650 switch (IntNo) { 9651 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9652 case Intrinsic::x86_avx_vtestz_ps: 9653 case Intrinsic::x86_avx_vtestz_pd: 9654 case Intrinsic::x86_avx_vtestz_ps_256: 9655 case Intrinsic::x86_avx_vtestz_pd_256: 9656 IsTestPacked = true; // Fallthrough 9657 case Intrinsic::x86_sse41_ptestz: 9658 case Intrinsic::x86_avx_ptestz_256: 9659 // ZF = 1 9660 X86CC = X86::COND_E; 9661 break; 9662 case Intrinsic::x86_avx_vtestc_ps: 9663 case Intrinsic::x86_avx_vtestc_pd: 9664 case Intrinsic::x86_avx_vtestc_ps_256: 9665 case Intrinsic::x86_avx_vtestc_pd_256: 9666 IsTestPacked = true; // Fallthrough 9667 case Intrinsic::x86_sse41_ptestc: 9668 case Intrinsic::x86_avx_ptestc_256: 9669 // CF = 1 9670 X86CC = X86::COND_B; 9671 break; 9672 case Intrinsic::x86_avx_vtestnzc_ps: 9673 case Intrinsic::x86_avx_vtestnzc_pd: 9674 case Intrinsic::x86_avx_vtestnzc_ps_256: 9675 case Intrinsic::x86_avx_vtestnzc_pd_256: 9676 IsTestPacked = true; // Fallthrough 9677 case Intrinsic::x86_sse41_ptestnzc: 9678 case Intrinsic::x86_avx_ptestnzc_256: 9679 // ZF and CF = 0 9680 X86CC = X86::COND_A; 9681 break; 9682 } 9683 9684 SDValue LHS = Op.getOperand(1); 9685 SDValue RHS = Op.getOperand(2); 9686 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9687 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9688 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9689 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9690 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9691 } 9692 9693 // Fix vector shift instructions where the last operand is a non-immediate 9694 // i32 value. 9695 case Intrinsic::x86_avx2_pslli_w: 9696 case Intrinsic::x86_avx2_pslli_d: 9697 case Intrinsic::x86_avx2_pslli_q: 9698 case Intrinsic::x86_avx2_psrli_w: 9699 case Intrinsic::x86_avx2_psrli_d: 9700 case Intrinsic::x86_avx2_psrli_q: 9701 case Intrinsic::x86_avx2_psrai_w: 9702 case Intrinsic::x86_avx2_psrai_d: 9703 case Intrinsic::x86_sse2_pslli_w: 9704 case Intrinsic::x86_sse2_pslli_d: 9705 case Intrinsic::x86_sse2_pslli_q: 9706 case Intrinsic::x86_sse2_psrli_w: 9707 case Intrinsic::x86_sse2_psrli_d: 9708 case Intrinsic::x86_sse2_psrli_q: 9709 case Intrinsic::x86_sse2_psrai_w: 9710 case Intrinsic::x86_sse2_psrai_d: 9711 case Intrinsic::x86_mmx_pslli_w: 9712 case Intrinsic::x86_mmx_pslli_d: 9713 case Intrinsic::x86_mmx_pslli_q: 9714 case Intrinsic::x86_mmx_psrli_w: 9715 case Intrinsic::x86_mmx_psrli_d: 9716 case Intrinsic::x86_mmx_psrli_q: 9717 case Intrinsic::x86_mmx_psrai_w: 9718 case Intrinsic::x86_mmx_psrai_d: { 9719 SDValue ShAmt = Op.getOperand(2); 9720 if (isa<ConstantSDNode>(ShAmt)) 9721 return SDValue(); 9722 9723 unsigned NewIntNo = 0; 9724 EVT ShAmtVT = MVT::v4i32; 9725 switch (IntNo) { 9726 case Intrinsic::x86_sse2_pslli_w: 9727 NewIntNo = Intrinsic::x86_sse2_psll_w; 9728 break; 9729 case Intrinsic::x86_sse2_pslli_d: 9730 NewIntNo = Intrinsic::x86_sse2_psll_d; 9731 break; 9732 case Intrinsic::x86_sse2_pslli_q: 9733 NewIntNo = Intrinsic::x86_sse2_psll_q; 9734 break; 9735 case Intrinsic::x86_sse2_psrli_w: 9736 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9737 break; 9738 case Intrinsic::x86_sse2_psrli_d: 9739 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9740 break; 9741 case Intrinsic::x86_sse2_psrli_q: 9742 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9743 break; 9744 case Intrinsic::x86_sse2_psrai_w: 9745 NewIntNo = Intrinsic::x86_sse2_psra_w; 9746 break; 9747 case Intrinsic::x86_sse2_psrai_d: 9748 NewIntNo = Intrinsic::x86_sse2_psra_d; 9749 break; 9750 case Intrinsic::x86_avx2_pslli_w: 9751 NewIntNo = Intrinsic::x86_avx2_psll_w; 9752 break; 9753 case Intrinsic::x86_avx2_pslli_d: 9754 NewIntNo = Intrinsic::x86_avx2_psll_d; 9755 break; 9756 case Intrinsic::x86_avx2_pslli_q: 9757 NewIntNo = Intrinsic::x86_avx2_psll_q; 9758 break; 9759 case Intrinsic::x86_avx2_psrli_w: 9760 NewIntNo = Intrinsic::x86_avx2_psrl_w; 9761 break; 9762 case Intrinsic::x86_avx2_psrli_d: 9763 NewIntNo = Intrinsic::x86_avx2_psrl_d; 9764 break; 9765 case Intrinsic::x86_avx2_psrli_q: 9766 NewIntNo = Intrinsic::x86_avx2_psrl_q; 9767 break; 9768 case Intrinsic::x86_avx2_psrai_w: 9769 NewIntNo = Intrinsic::x86_avx2_psra_w; 9770 break; 9771 case Intrinsic::x86_avx2_psrai_d: 9772 NewIntNo = Intrinsic::x86_avx2_psra_d; 9773 break; 9774 default: { 9775 ShAmtVT = MVT::v2i32; 9776 switch (IntNo) { 9777 case Intrinsic::x86_mmx_pslli_w: 9778 NewIntNo = Intrinsic::x86_mmx_psll_w; 9779 break; 9780 case Intrinsic::x86_mmx_pslli_d: 9781 NewIntNo = Intrinsic::x86_mmx_psll_d; 9782 break; 9783 case Intrinsic::x86_mmx_pslli_q: 9784 NewIntNo = Intrinsic::x86_mmx_psll_q; 9785 break; 9786 case Intrinsic::x86_mmx_psrli_w: 9787 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9788 break; 9789 case Intrinsic::x86_mmx_psrli_d: 9790 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9791 break; 9792 case Intrinsic::x86_mmx_psrli_q: 9793 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9794 break; 9795 case Intrinsic::x86_mmx_psrai_w: 9796 NewIntNo = Intrinsic::x86_mmx_psra_w; 9797 break; 9798 case Intrinsic::x86_mmx_psrai_d: 9799 NewIntNo = Intrinsic::x86_mmx_psra_d; 9800 break; 9801 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9802 } 9803 break; 9804 } 9805 } 9806 9807 // The vector shift intrinsics with scalars uses 32b shift amounts but 9808 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9809 // to be zero. 9810 SDValue ShOps[4]; 9811 ShOps[0] = ShAmt; 9812 ShOps[1] = DAG.getConstant(0, MVT::i32); 9813 if (ShAmtVT == MVT::v4i32) { 9814 ShOps[2] = DAG.getUNDEF(MVT::i32); 9815 ShOps[3] = DAG.getUNDEF(MVT::i32); 9816 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9817 } else { 9818 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9819// FIXME this must be lowered to get rid of the invalid type. 9820 } 9821 9822 EVT VT = Op.getValueType(); 9823 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9824 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9825 DAG.getConstant(NewIntNo, MVT::i32), 9826 Op.getOperand(1), ShAmt); 9827 } 9828 } 9829} 9830 9831SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9832 SelectionDAG &DAG) const { 9833 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9834 MFI->setReturnAddressIsTaken(true); 9835 9836 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9837 DebugLoc dl = Op.getDebugLoc(); 9838 9839 if (Depth > 0) { 9840 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9841 SDValue Offset = 9842 DAG.getConstant(TD->getPointerSize(), 9843 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9844 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9845 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9846 FrameAddr, Offset), 9847 MachinePointerInfo(), false, false, false, 0); 9848 } 9849 9850 // Just load the return address. 9851 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9852 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9853 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9854} 9855 9856SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9858 MFI->setFrameAddressIsTaken(true); 9859 9860 EVT VT = Op.getValueType(); 9861 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9862 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9863 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9864 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9865 while (Depth--) 9866 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9867 MachinePointerInfo(), 9868 false, false, false, 0); 9869 return FrameAddr; 9870} 9871 9872SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9873 SelectionDAG &DAG) const { 9874 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9875} 9876 9877SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9878 MachineFunction &MF = DAG.getMachineFunction(); 9879 SDValue Chain = Op.getOperand(0); 9880 SDValue Offset = Op.getOperand(1); 9881 SDValue Handler = Op.getOperand(2); 9882 DebugLoc dl = Op.getDebugLoc(); 9883 9884 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9885 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9886 getPointerTy()); 9887 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9888 9889 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9890 DAG.getIntPtrConstant(TD->getPointerSize())); 9891 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9892 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9893 false, false, 0); 9894 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9895 MF.getRegInfo().addLiveOut(StoreAddrReg); 9896 9897 return DAG.getNode(X86ISD::EH_RETURN, dl, 9898 MVT::Other, 9899 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9900} 9901 9902SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9903 SelectionDAG &DAG) const { 9904 return Op.getOperand(0); 9905} 9906 9907SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9908 SelectionDAG &DAG) const { 9909 SDValue Root = Op.getOperand(0); 9910 SDValue Trmp = Op.getOperand(1); // trampoline 9911 SDValue FPtr = Op.getOperand(2); // nested function 9912 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9913 DebugLoc dl = Op.getDebugLoc(); 9914 9915 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9916 9917 if (Subtarget->is64Bit()) { 9918 SDValue OutChains[6]; 9919 9920 // Large code-model. 9921 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9922 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9923 9924 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9925 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9926 9927 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9928 9929 // Load the pointer to the nested function into R11. 9930 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9931 SDValue Addr = Trmp; 9932 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9933 Addr, MachinePointerInfo(TrmpAddr), 9934 false, false, 0); 9935 9936 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9937 DAG.getConstant(2, MVT::i64)); 9938 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9939 MachinePointerInfo(TrmpAddr, 2), 9940 false, false, 2); 9941 9942 // Load the 'nest' parameter value into R10. 9943 // R10 is specified in X86CallingConv.td 9944 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9945 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9946 DAG.getConstant(10, MVT::i64)); 9947 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9948 Addr, MachinePointerInfo(TrmpAddr, 10), 9949 false, false, 0); 9950 9951 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9952 DAG.getConstant(12, MVT::i64)); 9953 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9954 MachinePointerInfo(TrmpAddr, 12), 9955 false, false, 2); 9956 9957 // Jump to the nested function. 9958 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9959 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9960 DAG.getConstant(20, MVT::i64)); 9961 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9962 Addr, MachinePointerInfo(TrmpAddr, 20), 9963 false, false, 0); 9964 9965 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9966 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9967 DAG.getConstant(22, MVT::i64)); 9968 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9969 MachinePointerInfo(TrmpAddr, 22), 9970 false, false, 0); 9971 9972 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9973 } else { 9974 const Function *Func = 9975 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9976 CallingConv::ID CC = Func->getCallingConv(); 9977 unsigned NestReg; 9978 9979 switch (CC) { 9980 default: 9981 llvm_unreachable("Unsupported calling convention"); 9982 case CallingConv::C: 9983 case CallingConv::X86_StdCall: { 9984 // Pass 'nest' parameter in ECX. 9985 // Must be kept in sync with X86CallingConv.td 9986 NestReg = X86::ECX; 9987 9988 // Check that ECX wasn't needed by an 'inreg' parameter. 9989 FunctionType *FTy = Func->getFunctionType(); 9990 const AttrListPtr &Attrs = Func->getAttributes(); 9991 9992 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9993 unsigned InRegCount = 0; 9994 unsigned Idx = 1; 9995 9996 for (FunctionType::param_iterator I = FTy->param_begin(), 9997 E = FTy->param_end(); I != E; ++I, ++Idx) 9998 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9999 // FIXME: should only count parameters that are lowered to integers. 10000 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 10001 10002 if (InRegCount > 2) { 10003 report_fatal_error("Nest register in use - reduce number of inreg" 10004 " parameters!"); 10005 } 10006 } 10007 break; 10008 } 10009 case CallingConv::X86_FastCall: 10010 case CallingConv::X86_ThisCall: 10011 case CallingConv::Fast: 10012 // Pass 'nest' parameter in EAX. 10013 // Must be kept in sync with X86CallingConv.td 10014 NestReg = X86::EAX; 10015 break; 10016 } 10017 10018 SDValue OutChains[4]; 10019 SDValue Addr, Disp; 10020 10021 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10022 DAG.getConstant(10, MVT::i32)); 10023 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 10024 10025 // This is storing the opcode for MOV32ri. 10026 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 10027 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 10028 OutChains[0] = DAG.getStore(Root, dl, 10029 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 10030 Trmp, MachinePointerInfo(TrmpAddr), 10031 false, false, 0); 10032 10033 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10034 DAG.getConstant(1, MVT::i32)); 10035 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 10036 MachinePointerInfo(TrmpAddr, 1), 10037 false, false, 1); 10038 10039 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 10040 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10041 DAG.getConstant(5, MVT::i32)); 10042 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 10043 MachinePointerInfo(TrmpAddr, 5), 10044 false, false, 1); 10045 10046 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10047 DAG.getConstant(6, MVT::i32)); 10048 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 10049 MachinePointerInfo(TrmpAddr, 6), 10050 false, false, 1); 10051 10052 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 10053 } 10054} 10055 10056SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 10057 SelectionDAG &DAG) const { 10058 /* 10059 The rounding mode is in bits 11:10 of FPSR, and has the following 10060 settings: 10061 00 Round to nearest 10062 01 Round to -inf 10063 10 Round to +inf 10064 11 Round to 0 10065 10066 FLT_ROUNDS, on the other hand, expects the following: 10067 -1 Undefined 10068 0 Round to 0 10069 1 Round to nearest 10070 2 Round to +inf 10071 3 Round to -inf 10072 10073 To perform the conversion, we do: 10074 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 10075 */ 10076 10077 MachineFunction &MF = DAG.getMachineFunction(); 10078 const TargetMachine &TM = MF.getTarget(); 10079 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 10080 unsigned StackAlignment = TFI.getStackAlignment(); 10081 EVT VT = Op.getValueType(); 10082 DebugLoc DL = Op.getDebugLoc(); 10083 10084 // Save FP Control Word to stack slot 10085 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 10086 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 10087 10088 10089 MachineMemOperand *MMO = 10090 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 10091 MachineMemOperand::MOStore, 2, 2); 10092 10093 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 10094 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 10095 DAG.getVTList(MVT::Other), 10096 Ops, 2, MVT::i16, MMO); 10097 10098 // Load FP Control Word from stack slot 10099 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 10100 MachinePointerInfo(), false, false, false, 0); 10101 10102 // Transform as necessary 10103 SDValue CWD1 = 10104 DAG.getNode(ISD::SRL, DL, MVT::i16, 10105 DAG.getNode(ISD::AND, DL, MVT::i16, 10106 CWD, DAG.getConstant(0x800, MVT::i16)), 10107 DAG.getConstant(11, MVT::i8)); 10108 SDValue CWD2 = 10109 DAG.getNode(ISD::SRL, DL, MVT::i16, 10110 DAG.getNode(ISD::AND, DL, MVT::i16, 10111 CWD, DAG.getConstant(0x400, MVT::i16)), 10112 DAG.getConstant(9, MVT::i8)); 10113 10114 SDValue RetVal = 10115 DAG.getNode(ISD::AND, DL, MVT::i16, 10116 DAG.getNode(ISD::ADD, DL, MVT::i16, 10117 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 10118 DAG.getConstant(1, MVT::i16)), 10119 DAG.getConstant(3, MVT::i16)); 10120 10121 10122 return DAG.getNode((VT.getSizeInBits() < 16 ? 10123 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10124} 10125 10126SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 10127 EVT VT = Op.getValueType(); 10128 EVT OpVT = VT; 10129 unsigned NumBits = VT.getSizeInBits(); 10130 DebugLoc dl = Op.getDebugLoc(); 10131 10132 Op = Op.getOperand(0); 10133 if (VT == MVT::i8) { 10134 // Zero extend to i32 since there is not an i8 bsr. 10135 OpVT = MVT::i32; 10136 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10137 } 10138 10139 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10140 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10141 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10142 10143 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10144 SDValue Ops[] = { 10145 Op, 10146 DAG.getConstant(NumBits+NumBits-1, OpVT), 10147 DAG.getConstant(X86::COND_E, MVT::i8), 10148 Op.getValue(1) 10149 }; 10150 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10151 10152 // Finally xor with NumBits-1. 10153 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10154 10155 if (VT == MVT::i8) 10156 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10157 return Op; 10158} 10159 10160SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10161 EVT VT = Op.getValueType(); 10162 EVT OpVT = VT; 10163 unsigned NumBits = VT.getSizeInBits(); 10164 DebugLoc dl = Op.getDebugLoc(); 10165 10166 Op = Op.getOperand(0); 10167 if (VT == MVT::i8) { 10168 OpVT = MVT::i32; 10169 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10170 } 10171 10172 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10173 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10174 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10175 10176 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10177 SDValue Ops[] = { 10178 Op, 10179 DAG.getConstant(NumBits, OpVT), 10180 DAG.getConstant(X86::COND_E, MVT::i8), 10181 Op.getValue(1) 10182 }; 10183 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10184 10185 if (VT == MVT::i8) 10186 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10187 return Op; 10188} 10189 10190// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10191// ones, and then concatenate the result back. 10192static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10193 EVT VT = Op.getValueType(); 10194 10195 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10196 "Unsupported value type for operation"); 10197 10198 int NumElems = VT.getVectorNumElements(); 10199 DebugLoc dl = Op.getDebugLoc(); 10200 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10201 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10202 10203 // Extract the LHS vectors 10204 SDValue LHS = Op.getOperand(0); 10205 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10206 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10207 10208 // Extract the RHS vectors 10209 SDValue RHS = Op.getOperand(1); 10210 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 10211 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 10212 10213 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10214 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10215 10216 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10217 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10218 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10219} 10220 10221SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10222 assert(Op.getValueType().getSizeInBits() == 256 && 10223 Op.getValueType().isInteger() && 10224 "Only handle AVX 256-bit vector integer operation"); 10225 return Lower256IntArith(Op, DAG); 10226} 10227 10228SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10229 assert(Op.getValueType().getSizeInBits() == 256 && 10230 Op.getValueType().isInteger() && 10231 "Only handle AVX 256-bit vector integer operation"); 10232 return Lower256IntArith(Op, DAG); 10233} 10234 10235SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10236 EVT VT = Op.getValueType(); 10237 10238 // Decompose 256-bit ops into smaller 128-bit ops. 10239 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10240 return Lower256IntArith(Op, DAG); 10241 10242 DebugLoc dl = Op.getDebugLoc(); 10243 10244 SDValue A = Op.getOperand(0); 10245 SDValue B = Op.getOperand(1); 10246 10247 if (VT == MVT::v4i64) { 10248 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2"); 10249 10250 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32); 10251 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32); 10252 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b ); 10253 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi ); 10254 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b ); 10255 // 10256 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 ); 10257 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 ); 10258 // return AloBlo + AloBhi + AhiBlo; 10259 10260 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10261 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 10262 A, DAG.getConstant(32, MVT::i32)); 10263 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10264 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 10265 B, DAG.getConstant(32, MVT::i32)); 10266 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10267 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 10268 A, B); 10269 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10270 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 10271 A, Bhi); 10272 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10273 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 10274 Ahi, B); 10275 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10276 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 10277 AloBhi, DAG.getConstant(32, MVT::i32)); 10278 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10279 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 10280 AhiBlo, DAG.getConstant(32, MVT::i32)); 10281 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10282 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10283 return Res; 10284 } 10285 10286 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 10287 10288 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 10289 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 10290 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 10291 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 10292 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 10293 // 10294 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 10295 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 10296 // return AloBlo + AloBhi + AhiBlo; 10297 10298 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10299 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10300 A, DAG.getConstant(32, MVT::i32)); 10301 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10302 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10303 B, DAG.getConstant(32, MVT::i32)); 10304 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10305 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10306 A, B); 10307 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10308 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10309 A, Bhi); 10310 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10311 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10312 Ahi, B); 10313 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10314 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10315 AloBhi, DAG.getConstant(32, MVT::i32)); 10316 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10317 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10318 AhiBlo, DAG.getConstant(32, MVT::i32)); 10319 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10320 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10321 return Res; 10322} 10323 10324SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10325 10326 EVT VT = Op.getValueType(); 10327 DebugLoc dl = Op.getDebugLoc(); 10328 SDValue R = Op.getOperand(0); 10329 SDValue Amt = Op.getOperand(1); 10330 LLVMContext *Context = DAG.getContext(); 10331 10332 if (!Subtarget->hasXMMInt()) 10333 return SDValue(); 10334 10335 // Optimize shl/srl/sra with constant shift amount. 10336 if (isSplatVector(Amt.getNode())) { 10337 SDValue SclrAmt = Amt->getOperand(0); 10338 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10339 uint64_t ShiftAmt = C->getZExtValue(); 10340 10341 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) { 10342 // Make a large shift. 10343 SDValue SHL = 10344 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10345 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10346 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10347 // Zero out the rightmost bits. 10348 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10349 MVT::i8)); 10350 return DAG.getNode(ISD::AND, dl, VT, SHL, 10351 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10352 } 10353 10354 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 10355 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10356 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10357 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10358 10359 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 10360 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10361 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10362 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10363 10364 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 10365 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10366 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10367 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10368 10369 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) { 10370 // Make a large shift. 10371 SDValue SRL = 10372 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10373 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10374 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10375 // Zero out the leftmost bits. 10376 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10377 MVT::i8)); 10378 return DAG.getNode(ISD::AND, dl, VT, SRL, 10379 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10380 } 10381 10382 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 10383 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10384 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10385 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10386 10387 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 10388 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10389 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 10390 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10391 10392 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 10393 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10394 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10395 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10396 10397 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 10398 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10399 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 10400 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10401 10402 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 10403 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10404 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 10405 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10406 10407 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) { 10408 if (ShiftAmt == 7) { 10409 // R s>> 7 === R s< 0 10410 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 10411 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10412 } 10413 10414 // R s>> a === ((R u>> a) ^ m) - m 10415 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10416 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10417 MVT::i8)); 10418 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10419 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10420 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10421 return Res; 10422 } 10423 10424 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10425 if (Op.getOpcode() == ISD::SHL) { 10426 // Make a large shift. 10427 SDValue SHL = 10428 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10429 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 10430 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10431 // Zero out the rightmost bits. 10432 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10433 MVT::i8)); 10434 return DAG.getNode(ISD::AND, dl, VT, SHL, 10435 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10436 } 10437 if (Op.getOpcode() == ISD::SRL) { 10438 // Make a large shift. 10439 SDValue SRL = 10440 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10441 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 10442 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10443 // Zero out the leftmost bits. 10444 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10445 MVT::i8)); 10446 return DAG.getNode(ISD::AND, dl, VT, SRL, 10447 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10448 } 10449 if (Op.getOpcode() == ISD::SRA) { 10450 if (ShiftAmt == 7) { 10451 // R s>> 7 === R s< 0 10452 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 10453 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10454 } 10455 10456 // R s>> a === ((R u>> a) ^ m) - m 10457 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10458 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10459 MVT::i8)); 10460 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10461 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10462 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10463 return Res; 10464 } 10465 } 10466 } 10467 } 10468 10469 // Lower SHL with variable shift amount. 10470 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10471 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10472 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10473 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 10474 10475 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 10476 10477 std::vector<Constant*> CV(4, CI); 10478 Constant *C = ConstantVector::get(CV); 10479 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10480 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10481 MachinePointerInfo::getConstantPool(), 10482 false, false, false, 16); 10483 10484 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10485 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10486 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10487 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10488 } 10489 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10490 // a = a << 5; 10491 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10492 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10493 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 10494 10495 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 10496 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 10497 10498 std::vector<Constant*> CVM1(16, CM1); 10499 std::vector<Constant*> CVM2(16, CM2); 10500 Constant *C = ConstantVector::get(CVM1); 10501 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10502 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10503 MachinePointerInfo::getConstantPool(), 10504 false, false, false, 16); 10505 10506 // r = pblendv(r, psllw(r & (char16)15, 4), a); 10507 M = DAG.getNode(ISD::AND, dl, VT, R, M); 10508 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10509 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10510 DAG.getConstant(4, MVT::i32)); 10511 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M); 10512 // a += a 10513 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10514 10515 C = ConstantVector::get(CVM2); 10516 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10517 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10518 MachinePointerInfo::getConstantPool(), 10519 false, false, false, 16); 10520 10521 // r = pblendv(r, psllw(r & (char16)63, 2), a); 10522 M = DAG.getNode(ISD::AND, dl, VT, R, M); 10523 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10524 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10525 DAG.getConstant(2, MVT::i32)); 10526 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M); 10527 // a += a 10528 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10529 10530 // return pblendv(r, r+r, a); 10531 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, 10532 R, DAG.getNode(ISD::ADD, dl, VT, R, R)); 10533 return R; 10534 } 10535 10536 // Decompose 256-bit shifts into smaller 128-bit shifts. 10537 if (VT.getSizeInBits() == 256) { 10538 int NumElems = VT.getVectorNumElements(); 10539 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10540 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10541 10542 // Extract the two vectors 10543 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10544 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10545 DAG, dl); 10546 10547 // Recreate the shift amount vectors 10548 SDValue Amt1, Amt2; 10549 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10550 // Constant shift amount 10551 SmallVector<SDValue, 4> Amt1Csts; 10552 SmallVector<SDValue, 4> Amt2Csts; 10553 for (int i = 0; i < NumElems/2; ++i) 10554 Amt1Csts.push_back(Amt->getOperand(i)); 10555 for (int i = NumElems/2; i < NumElems; ++i) 10556 Amt2Csts.push_back(Amt->getOperand(i)); 10557 10558 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10559 &Amt1Csts[0], NumElems/2); 10560 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10561 &Amt2Csts[0], NumElems/2); 10562 } else { 10563 // Variable shift amount 10564 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10565 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10566 DAG, dl); 10567 } 10568 10569 // Issue new vector shifts for the smaller types 10570 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10571 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10572 10573 // Concatenate the result back 10574 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10575 } 10576 10577 return SDValue(); 10578} 10579 10580SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10581 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10582 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10583 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10584 // has only one use. 10585 SDNode *N = Op.getNode(); 10586 SDValue LHS = N->getOperand(0); 10587 SDValue RHS = N->getOperand(1); 10588 unsigned BaseOp = 0; 10589 unsigned Cond = 0; 10590 DebugLoc DL = Op.getDebugLoc(); 10591 switch (Op.getOpcode()) { 10592 default: llvm_unreachable("Unknown ovf instruction!"); 10593 case ISD::SADDO: 10594 // A subtract of one will be selected as a INC. Note that INC doesn't 10595 // set CF, so we can't do this for UADDO. 10596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10597 if (C->isOne()) { 10598 BaseOp = X86ISD::INC; 10599 Cond = X86::COND_O; 10600 break; 10601 } 10602 BaseOp = X86ISD::ADD; 10603 Cond = X86::COND_O; 10604 break; 10605 case ISD::UADDO: 10606 BaseOp = X86ISD::ADD; 10607 Cond = X86::COND_B; 10608 break; 10609 case ISD::SSUBO: 10610 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10611 // set CF, so we can't do this for USUBO. 10612 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10613 if (C->isOne()) { 10614 BaseOp = X86ISD::DEC; 10615 Cond = X86::COND_O; 10616 break; 10617 } 10618 BaseOp = X86ISD::SUB; 10619 Cond = X86::COND_O; 10620 break; 10621 case ISD::USUBO: 10622 BaseOp = X86ISD::SUB; 10623 Cond = X86::COND_B; 10624 break; 10625 case ISD::SMULO: 10626 BaseOp = X86ISD::SMUL; 10627 Cond = X86::COND_O; 10628 break; 10629 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10630 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10631 MVT::i32); 10632 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10633 10634 SDValue SetCC = 10635 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10636 DAG.getConstant(X86::COND_O, MVT::i32), 10637 SDValue(Sum.getNode(), 2)); 10638 10639 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10640 } 10641 } 10642 10643 // Also sets EFLAGS. 10644 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10645 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10646 10647 SDValue SetCC = 10648 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10649 DAG.getConstant(Cond, MVT::i32), 10650 SDValue(Sum.getNode(), 1)); 10651 10652 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10653} 10654 10655SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{ 10656 DebugLoc dl = Op.getDebugLoc(); 10657 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10658 EVT VT = Op.getValueType(); 10659 10660 if (Subtarget->hasXMMInt() && VT.isVector()) { 10661 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10662 ExtraVT.getScalarType().getSizeInBits(); 10663 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10664 10665 unsigned SHLIntrinsicsID = 0; 10666 unsigned SRAIntrinsicsID = 0; 10667 switch (VT.getSimpleVT().SimpleTy) { 10668 default: 10669 return SDValue(); 10670 case MVT::v4i32: 10671 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 10672 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 10673 break; 10674 case MVT::v8i16: 10675 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 10676 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 10677 break; 10678 case MVT::v8i32: 10679 case MVT::v16i16: 10680 if (!Subtarget->hasAVX()) 10681 return SDValue(); 10682 if (!Subtarget->hasAVX2()) { 10683 // needs to be split 10684 int NumElems = VT.getVectorNumElements(); 10685 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10686 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10687 10688 // Extract the LHS vectors 10689 SDValue LHS = Op.getOperand(0); 10690 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10691 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10692 10693 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10694 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10695 10696 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10697 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10698 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10699 ExtraNumElems/2); 10700 SDValue Extra = DAG.getValueType(ExtraVT); 10701 10702 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10703 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10704 10705 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10706 } 10707 if (VT == MVT::v8i32) { 10708 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d; 10709 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d; 10710 } else { 10711 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w; 10712 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w; 10713 } 10714 } 10715 10716 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10717 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 10718 Op.getOperand(0), ShAmt); 10719 10720 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10721 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 10722 Tmp1, ShAmt); 10723 } 10724 10725 return SDValue(); 10726} 10727 10728 10729SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10730 DebugLoc dl = Op.getDebugLoc(); 10731 10732 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10733 // There isn't any reason to disable it if the target processor supports it. 10734 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) { 10735 SDValue Chain = Op.getOperand(0); 10736 SDValue Zero = DAG.getConstant(0, MVT::i32); 10737 SDValue Ops[] = { 10738 DAG.getRegister(X86::ESP, MVT::i32), // Base 10739 DAG.getTargetConstant(1, MVT::i8), // Scale 10740 DAG.getRegister(0, MVT::i32), // Index 10741 DAG.getTargetConstant(0, MVT::i32), // Disp 10742 DAG.getRegister(0, MVT::i32), // Segment. 10743 Zero, 10744 Chain 10745 }; 10746 SDNode *Res = 10747 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10748 array_lengthof(Ops)); 10749 return SDValue(Res, 0); 10750 } 10751 10752 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10753 if (!isDev) 10754 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10755 10756 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10757 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10758 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10759 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10760 10761 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10762 if (!Op1 && !Op2 && !Op3 && Op4) 10763 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10764 10765 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10766 if (Op1 && !Op2 && !Op3 && !Op4) 10767 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10768 10769 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10770 // (MFENCE)>; 10771 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10772} 10773 10774SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10775 SelectionDAG &DAG) const { 10776 DebugLoc dl = Op.getDebugLoc(); 10777 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10778 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10779 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10780 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10781 10782 // The only fence that needs an instruction is a sequentially-consistent 10783 // cross-thread fence. 10784 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10785 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10786 // no-sse2). There isn't any reason to disable it if the target processor 10787 // supports it. 10788 if (Subtarget->hasXMMInt() || Subtarget->is64Bit()) 10789 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10790 10791 SDValue Chain = Op.getOperand(0); 10792 SDValue Zero = DAG.getConstant(0, MVT::i32); 10793 SDValue Ops[] = { 10794 DAG.getRegister(X86::ESP, MVT::i32), // Base 10795 DAG.getTargetConstant(1, MVT::i8), // Scale 10796 DAG.getRegister(0, MVT::i32), // Index 10797 DAG.getTargetConstant(0, MVT::i32), // Disp 10798 DAG.getRegister(0, MVT::i32), // Segment. 10799 Zero, 10800 Chain 10801 }; 10802 SDNode *Res = 10803 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10804 array_lengthof(Ops)); 10805 return SDValue(Res, 0); 10806 } 10807 10808 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10809 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10810} 10811 10812 10813SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10814 EVT T = Op.getValueType(); 10815 DebugLoc DL = Op.getDebugLoc(); 10816 unsigned Reg = 0; 10817 unsigned size = 0; 10818 switch(T.getSimpleVT().SimpleTy) { 10819 default: 10820 assert(false && "Invalid value type!"); 10821 case MVT::i8: Reg = X86::AL; size = 1; break; 10822 case MVT::i16: Reg = X86::AX; size = 2; break; 10823 case MVT::i32: Reg = X86::EAX; size = 4; break; 10824 case MVT::i64: 10825 assert(Subtarget->is64Bit() && "Node not type legal!"); 10826 Reg = X86::RAX; size = 8; 10827 break; 10828 } 10829 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10830 Op.getOperand(2), SDValue()); 10831 SDValue Ops[] = { cpIn.getValue(0), 10832 Op.getOperand(1), 10833 Op.getOperand(3), 10834 DAG.getTargetConstant(size, MVT::i8), 10835 cpIn.getValue(1) }; 10836 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10837 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10838 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10839 Ops, 5, T, MMO); 10840 SDValue cpOut = 10841 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10842 return cpOut; 10843} 10844 10845SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10846 SelectionDAG &DAG) const { 10847 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10848 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10849 SDValue TheChain = Op.getOperand(0); 10850 DebugLoc dl = Op.getDebugLoc(); 10851 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10852 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10853 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10854 rax.getValue(2)); 10855 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10856 DAG.getConstant(32, MVT::i8)); 10857 SDValue Ops[] = { 10858 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10859 rdx.getValue(1) 10860 }; 10861 return DAG.getMergeValues(Ops, 2, dl); 10862} 10863 10864SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10865 SelectionDAG &DAG) const { 10866 EVT SrcVT = Op.getOperand(0).getValueType(); 10867 EVT DstVT = Op.getValueType(); 10868 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() && 10869 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10870 assert((DstVT == MVT::i64 || 10871 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10872 "Unexpected custom BITCAST"); 10873 // i64 <=> MMX conversions are Legal. 10874 if (SrcVT==MVT::i64 && DstVT.isVector()) 10875 return Op; 10876 if (DstVT==MVT::i64 && SrcVT.isVector()) 10877 return Op; 10878 // MMX <=> MMX conversions are Legal. 10879 if (SrcVT.isVector() && DstVT.isVector()) 10880 return Op; 10881 // All other conversions need to be expanded. 10882 return SDValue(); 10883} 10884 10885SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10886 SDNode *Node = Op.getNode(); 10887 DebugLoc dl = Node->getDebugLoc(); 10888 EVT T = Node->getValueType(0); 10889 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10890 DAG.getConstant(0, T), Node->getOperand(2)); 10891 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10892 cast<AtomicSDNode>(Node)->getMemoryVT(), 10893 Node->getOperand(0), 10894 Node->getOperand(1), negOp, 10895 cast<AtomicSDNode>(Node)->getSrcValue(), 10896 cast<AtomicSDNode>(Node)->getAlignment(), 10897 cast<AtomicSDNode>(Node)->getOrdering(), 10898 cast<AtomicSDNode>(Node)->getSynchScope()); 10899} 10900 10901static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10902 SDNode *Node = Op.getNode(); 10903 DebugLoc dl = Node->getDebugLoc(); 10904 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10905 10906 // Convert seq_cst store -> xchg 10907 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10908 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10909 // (The only way to get a 16-byte store is cmpxchg16b) 10910 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10911 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10912 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10913 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10914 cast<AtomicSDNode>(Node)->getMemoryVT(), 10915 Node->getOperand(0), 10916 Node->getOperand(1), Node->getOperand(2), 10917 cast<AtomicSDNode>(Node)->getMemOperand(), 10918 cast<AtomicSDNode>(Node)->getOrdering(), 10919 cast<AtomicSDNode>(Node)->getSynchScope()); 10920 return Swap.getValue(1); 10921 } 10922 // Other atomic stores have a simple pattern. 10923 return Op; 10924} 10925 10926static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10927 EVT VT = Op.getNode()->getValueType(0); 10928 10929 // Let legalize expand this if it isn't a legal type yet. 10930 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10931 return SDValue(); 10932 10933 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10934 10935 unsigned Opc; 10936 bool ExtraOp = false; 10937 switch (Op.getOpcode()) { 10938 default: assert(0 && "Invalid code"); 10939 case ISD::ADDC: Opc = X86ISD::ADD; break; 10940 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10941 case ISD::SUBC: Opc = X86ISD::SUB; break; 10942 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10943 } 10944 10945 if (!ExtraOp) 10946 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10947 Op.getOperand(1)); 10948 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10949 Op.getOperand(1), Op.getOperand(2)); 10950} 10951 10952/// LowerOperation - Provide custom lowering hooks for some operations. 10953/// 10954SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10955 switch (Op.getOpcode()) { 10956 default: llvm_unreachable("Should not custom lower this!"); 10957 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10958 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10959 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10960 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10961 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10962 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10963 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10964 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10965 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10966 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10967 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10968 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10969 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10970 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10971 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10972 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10973 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10974 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10975 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10976 case ISD::SHL_PARTS: 10977 case ISD::SRA_PARTS: 10978 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10979 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10980 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10981 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10982 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10983 case ISD::FABS: return LowerFABS(Op, DAG); 10984 case ISD::FNEG: return LowerFNEG(Op, DAG); 10985 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10986 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10987 case ISD::SETCC: return LowerSETCC(Op, DAG); 10988 case ISD::SELECT: return LowerSELECT(Op, DAG); 10989 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10990 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10991 case ISD::VASTART: return LowerVASTART(Op, DAG); 10992 case ISD::VAARG: return LowerVAARG(Op, DAG); 10993 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10994 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10995 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10996 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10997 case ISD::FRAME_TO_ARGS_OFFSET: 10998 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10999 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 11000 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 11001 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 11002 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 11003 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 11004 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 11005 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 11006 case ISD::MUL: return LowerMUL(Op, DAG); 11007 case ISD::SRA: 11008 case ISD::SRL: 11009 case ISD::SHL: return LowerShift(Op, DAG); 11010 case ISD::SADDO: 11011 case ISD::UADDO: 11012 case ISD::SSUBO: 11013 case ISD::USUBO: 11014 case ISD::SMULO: 11015 case ISD::UMULO: return LowerXALUO(Op, DAG); 11016 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 11017 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 11018 case ISD::ADDC: 11019 case ISD::ADDE: 11020 case ISD::SUBC: 11021 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 11022 case ISD::ADD: return LowerADD(Op, DAG); 11023 case ISD::SUB: return LowerSUB(Op, DAG); 11024 } 11025} 11026 11027static void ReplaceATOMIC_LOAD(SDNode *Node, 11028 SmallVectorImpl<SDValue> &Results, 11029 SelectionDAG &DAG) { 11030 DebugLoc dl = Node->getDebugLoc(); 11031 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 11032 11033 // Convert wide load -> cmpxchg8b/cmpxchg16b 11034 // FIXME: On 32-bit, load -> fild or movq would be more efficient 11035 // (The only way to get a 16-byte load is cmpxchg16b) 11036 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 11037 SDValue Zero = DAG.getConstant(0, VT); 11038 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 11039 Node->getOperand(0), 11040 Node->getOperand(1), Zero, Zero, 11041 cast<AtomicSDNode>(Node)->getMemOperand(), 11042 cast<AtomicSDNode>(Node)->getOrdering(), 11043 cast<AtomicSDNode>(Node)->getSynchScope()); 11044 Results.push_back(Swap.getValue(0)); 11045 Results.push_back(Swap.getValue(1)); 11046} 11047 11048void X86TargetLowering:: 11049ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 11050 SelectionDAG &DAG, unsigned NewOp) const { 11051 DebugLoc dl = Node->getDebugLoc(); 11052 assert (Node->getValueType(0) == MVT::i64 && 11053 "Only know how to expand i64 atomics"); 11054 11055 SDValue Chain = Node->getOperand(0); 11056 SDValue In1 = Node->getOperand(1); 11057 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11058 Node->getOperand(2), DAG.getIntPtrConstant(0)); 11059 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11060 Node->getOperand(2), DAG.getIntPtrConstant(1)); 11061 SDValue Ops[] = { Chain, In1, In2L, In2H }; 11062 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 11063 SDValue Result = 11064 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 11065 cast<MemSDNode>(Node)->getMemOperand()); 11066 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 11067 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 11068 Results.push_back(Result.getValue(2)); 11069} 11070 11071/// ReplaceNodeResults - Replace a node with an illegal result type 11072/// with a new node built out of custom code. 11073void X86TargetLowering::ReplaceNodeResults(SDNode *N, 11074 SmallVectorImpl<SDValue>&Results, 11075 SelectionDAG &DAG) const { 11076 DebugLoc dl = N->getDebugLoc(); 11077 switch (N->getOpcode()) { 11078 default: 11079 assert(false && "Do not know how to custom type legalize this operation!"); 11080 return; 11081 case ISD::SIGN_EXTEND_INREG: 11082 case ISD::ADDC: 11083 case ISD::ADDE: 11084 case ISD::SUBC: 11085 case ISD::SUBE: 11086 // We don't want to expand or promote these. 11087 return; 11088 case ISD::FP_TO_SINT: { 11089 std::pair<SDValue,SDValue> Vals = 11090 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 11091 SDValue FIST = Vals.first, StackSlot = Vals.second; 11092 if (FIST.getNode() != 0) { 11093 EVT VT = N->getValueType(0); 11094 // Return a load from the stack slot. 11095 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 11096 MachinePointerInfo(), 11097 false, false, false, 0)); 11098 } 11099 return; 11100 } 11101 case ISD::READCYCLECOUNTER: { 11102 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11103 SDValue TheChain = N->getOperand(0); 11104 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 11105 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 11106 rd.getValue(1)); 11107 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 11108 eax.getValue(2)); 11109 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 11110 SDValue Ops[] = { eax, edx }; 11111 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 11112 Results.push_back(edx.getValue(1)); 11113 return; 11114 } 11115 case ISD::ATOMIC_CMP_SWAP: { 11116 EVT T = N->getValueType(0); 11117 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 11118 bool Regs64bit = T == MVT::i128; 11119 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 11120 SDValue cpInL, cpInH; 11121 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11122 DAG.getConstant(0, HalfT)); 11123 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11124 DAG.getConstant(1, HalfT)); 11125 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 11126 Regs64bit ? X86::RAX : X86::EAX, 11127 cpInL, SDValue()); 11128 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 11129 Regs64bit ? X86::RDX : X86::EDX, 11130 cpInH, cpInL.getValue(1)); 11131 SDValue swapInL, swapInH; 11132 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11133 DAG.getConstant(0, HalfT)); 11134 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11135 DAG.getConstant(1, HalfT)); 11136 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 11137 Regs64bit ? X86::RBX : X86::EBX, 11138 swapInL, cpInH.getValue(1)); 11139 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 11140 Regs64bit ? X86::RCX : X86::ECX, 11141 swapInH, swapInL.getValue(1)); 11142 SDValue Ops[] = { swapInH.getValue(0), 11143 N->getOperand(1), 11144 swapInH.getValue(1) }; 11145 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11146 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 11147 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 11148 X86ISD::LCMPXCHG8_DAG; 11149 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 11150 Ops, 3, T, MMO); 11151 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 11152 Regs64bit ? X86::RAX : X86::EAX, 11153 HalfT, Result.getValue(1)); 11154 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 11155 Regs64bit ? X86::RDX : X86::EDX, 11156 HalfT, cpOutL.getValue(2)); 11157 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 11158 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 11159 Results.push_back(cpOutH.getValue(1)); 11160 return; 11161 } 11162 case ISD::ATOMIC_LOAD_ADD: 11163 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 11164 return; 11165 case ISD::ATOMIC_LOAD_AND: 11166 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 11167 return; 11168 case ISD::ATOMIC_LOAD_NAND: 11169 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 11170 return; 11171 case ISD::ATOMIC_LOAD_OR: 11172 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 11173 return; 11174 case ISD::ATOMIC_LOAD_SUB: 11175 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 11176 return; 11177 case ISD::ATOMIC_LOAD_XOR: 11178 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 11179 return; 11180 case ISD::ATOMIC_SWAP: 11181 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 11182 return; 11183 case ISD::ATOMIC_LOAD: 11184 ReplaceATOMIC_LOAD(N, Results, DAG); 11185 } 11186} 11187 11188const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11189 switch (Opcode) { 11190 default: return NULL; 11191 case X86ISD::BSF: return "X86ISD::BSF"; 11192 case X86ISD::BSR: return "X86ISD::BSR"; 11193 case X86ISD::SHLD: return "X86ISD::SHLD"; 11194 case X86ISD::SHRD: return "X86ISD::SHRD"; 11195 case X86ISD::FAND: return "X86ISD::FAND"; 11196 case X86ISD::FOR: return "X86ISD::FOR"; 11197 case X86ISD::FXOR: return "X86ISD::FXOR"; 11198 case X86ISD::FSRL: return "X86ISD::FSRL"; 11199 case X86ISD::FILD: return "X86ISD::FILD"; 11200 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11201 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11202 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11203 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11204 case X86ISD::FLD: return "X86ISD::FLD"; 11205 case X86ISD::FST: return "X86ISD::FST"; 11206 case X86ISD::CALL: return "X86ISD::CALL"; 11207 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11208 case X86ISD::BT: return "X86ISD::BT"; 11209 case X86ISD::CMP: return "X86ISD::CMP"; 11210 case X86ISD::COMI: return "X86ISD::COMI"; 11211 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11212 case X86ISD::SETCC: return "X86ISD::SETCC"; 11213 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11214 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11215 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11216 case X86ISD::CMOV: return "X86ISD::CMOV"; 11217 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11218 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11219 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11220 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11221 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11222 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11223 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11224 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11225 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11226 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11227 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11228 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11229 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11230 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11231 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11232 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11233 case X86ISD::FHADD: return "X86ISD::FHADD"; 11234 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11235 case X86ISD::FMAX: return "X86ISD::FMAX"; 11236 case X86ISD::FMIN: return "X86ISD::FMIN"; 11237 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11238 case X86ISD::FRCP: return "X86ISD::FRCP"; 11239 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11240 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11241 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11242 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11243 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11244 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11245 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11246 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11247 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11248 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11249 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11250 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11251 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11252 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11253 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11254 case X86ISD::VSHL: return "X86ISD::VSHL"; 11255 case X86ISD::VSRL: return "X86ISD::VSRL"; 11256 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 11257 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 11258 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 11259 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 11260 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 11261 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 11262 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 11263 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 11264 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 11265 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 11266 case X86ISD::ADD: return "X86ISD::ADD"; 11267 case X86ISD::SUB: return "X86ISD::SUB"; 11268 case X86ISD::ADC: return "X86ISD::ADC"; 11269 case X86ISD::SBB: return "X86ISD::SBB"; 11270 case X86ISD::SMUL: return "X86ISD::SMUL"; 11271 case X86ISD::UMUL: return "X86ISD::UMUL"; 11272 case X86ISD::INC: return "X86ISD::INC"; 11273 case X86ISD::DEC: return "X86ISD::DEC"; 11274 case X86ISD::OR: return "X86ISD::OR"; 11275 case X86ISD::XOR: return "X86ISD::XOR"; 11276 case X86ISD::AND: return "X86ISD::AND"; 11277 case X86ISD::ANDN: return "X86ISD::ANDN"; 11278 case X86ISD::BLSI: return "X86ISD::BLSI"; 11279 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11280 case X86ISD::BLSR: return "X86ISD::BLSR"; 11281 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11282 case X86ISD::PTEST: return "X86ISD::PTEST"; 11283 case X86ISD::TESTP: return "X86ISD::TESTP"; 11284 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11285 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11286 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11287 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 11288 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11289 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 11290 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 11291 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 11292 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11293 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11294 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11295 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 11296 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11297 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11298 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11299 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11300 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11301 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 11302 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 11303 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11304 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11305 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 11306 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 11307 case X86ISD::VUNPCKLPSY: return "X86ISD::VUNPCKLPSY"; 11308 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY"; 11309 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 11310 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 11311 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 11312 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 11313 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 11314 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 11315 case X86ISD::VPUNPCKLBWY: return "X86ISD::VPUNPCKLBWY"; 11316 case X86ISD::VPUNPCKLWDY: return "X86ISD::VPUNPCKLWDY"; 11317 case X86ISD::VPUNPCKLDQY: return "X86ISD::VPUNPCKLDQY"; 11318 case X86ISD::VPUNPCKLQDQY: return "X86ISD::VPUNPCKLQDQY"; 11319 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 11320 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 11321 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 11322 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 11323 case X86ISD::VPUNPCKHBWY: return "X86ISD::VPUNPCKHBWY"; 11324 case X86ISD::VPUNPCKHWDY: return "X86ISD::VPUNPCKHWDY"; 11325 case X86ISD::VPUNPCKHDQY: return "X86ISD::VPUNPCKHDQY"; 11326 case X86ISD::VPUNPCKHQDQY: return "X86ISD::VPUNPCKHQDQY"; 11327 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11328 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS"; 11329 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY"; 11330 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD"; 11331 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY"; 11332 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128"; 11333 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11334 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11335 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11336 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11337 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11338 } 11339} 11340 11341// isLegalAddressingMode - Return true if the addressing mode represented 11342// by AM is legal for this target, for a load/store of the specified type. 11343bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11344 Type *Ty) const { 11345 // X86 supports extremely general addressing modes. 11346 CodeModel::Model M = getTargetMachine().getCodeModel(); 11347 Reloc::Model R = getTargetMachine().getRelocationModel(); 11348 11349 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11350 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11351 return false; 11352 11353 if (AM.BaseGV) { 11354 unsigned GVFlags = 11355 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11356 11357 // If a reference to this global requires an extra load, we can't fold it. 11358 if (isGlobalStubReference(GVFlags)) 11359 return false; 11360 11361 // If BaseGV requires a register for the PIC base, we cannot also have a 11362 // BaseReg specified. 11363 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11364 return false; 11365 11366 // If lower 4G is not available, then we must use rip-relative addressing. 11367 if ((M != CodeModel::Small || R != Reloc::Static) && 11368 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11369 return false; 11370 } 11371 11372 switch (AM.Scale) { 11373 case 0: 11374 case 1: 11375 case 2: 11376 case 4: 11377 case 8: 11378 // These scales always work. 11379 break; 11380 case 3: 11381 case 5: 11382 case 9: 11383 // These scales are formed with basereg+scalereg. Only accept if there is 11384 // no basereg yet. 11385 if (AM.HasBaseReg) 11386 return false; 11387 break; 11388 default: // Other stuff never works. 11389 return false; 11390 } 11391 11392 return true; 11393} 11394 11395 11396bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11397 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11398 return false; 11399 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11400 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11401 if (NumBits1 <= NumBits2) 11402 return false; 11403 return true; 11404} 11405 11406bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11407 if (!VT1.isInteger() || !VT2.isInteger()) 11408 return false; 11409 unsigned NumBits1 = VT1.getSizeInBits(); 11410 unsigned NumBits2 = VT2.getSizeInBits(); 11411 if (NumBits1 <= NumBits2) 11412 return false; 11413 return true; 11414} 11415 11416bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11417 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11418 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11419} 11420 11421bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11422 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11423 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11424} 11425 11426bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11427 // i16 instructions are longer (0x66 prefix) and potentially slower. 11428 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11429} 11430 11431/// isShuffleMaskLegal - Targets can use this to indicate that they only 11432/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11433/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11434/// are assumed to be legal. 11435bool 11436X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11437 EVT VT) const { 11438 // Very little shuffling can be done for 64-bit vectors right now. 11439 if (VT.getSizeInBits() == 64) 11440 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()); 11441 11442 // FIXME: pshufb, blends, shifts. 11443 return (VT.getVectorNumElements() == 2 || 11444 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11445 isMOVLMask(M, VT) || 11446 isSHUFPMask(M, VT) || 11447 isPSHUFDMask(M, VT) || 11448 isPSHUFHWMask(M, VT) || 11449 isPSHUFLWMask(M, VT) || 11450 isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()) || 11451 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11452 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11453 isUNPCKL_v_undef_Mask(M, VT) || 11454 isUNPCKH_v_undef_Mask(M, VT)); 11455} 11456 11457bool 11458X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11459 EVT VT) const { 11460 unsigned NumElts = VT.getVectorNumElements(); 11461 // FIXME: This collection of masks seems suspect. 11462 if (NumElts == 2) 11463 return true; 11464 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11465 return (isMOVLMask(Mask, VT) || 11466 isCommutedMOVLMask(Mask, VT, true) || 11467 isSHUFPMask(Mask, VT) || 11468 isCommutedSHUFPMask(Mask, VT)); 11469 } 11470 return false; 11471} 11472 11473//===----------------------------------------------------------------------===// 11474// X86 Scheduler Hooks 11475//===----------------------------------------------------------------------===// 11476 11477// private utility function 11478MachineBasicBlock * 11479X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11480 MachineBasicBlock *MBB, 11481 unsigned regOpc, 11482 unsigned immOpc, 11483 unsigned LoadOpc, 11484 unsigned CXchgOpc, 11485 unsigned notOpc, 11486 unsigned EAXreg, 11487 TargetRegisterClass *RC, 11488 bool invSrc) const { 11489 // For the atomic bitwise operator, we generate 11490 // thisMBB: 11491 // newMBB: 11492 // ld t1 = [bitinstr.addr] 11493 // op t2 = t1, [bitinstr.val] 11494 // mov EAX = t1 11495 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11496 // bz newMBB 11497 // fallthrough -->nextMBB 11498 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11499 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11500 MachineFunction::iterator MBBIter = MBB; 11501 ++MBBIter; 11502 11503 /// First build the CFG 11504 MachineFunction *F = MBB->getParent(); 11505 MachineBasicBlock *thisMBB = MBB; 11506 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11507 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11508 F->insert(MBBIter, newMBB); 11509 F->insert(MBBIter, nextMBB); 11510 11511 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11512 nextMBB->splice(nextMBB->begin(), thisMBB, 11513 llvm::next(MachineBasicBlock::iterator(bInstr)), 11514 thisMBB->end()); 11515 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11516 11517 // Update thisMBB to fall through to newMBB 11518 thisMBB->addSuccessor(newMBB); 11519 11520 // newMBB jumps to itself and fall through to nextMBB 11521 newMBB->addSuccessor(nextMBB); 11522 newMBB->addSuccessor(newMBB); 11523 11524 // Insert instructions into newMBB based on incoming instruction 11525 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11526 "unexpected number of operands"); 11527 DebugLoc dl = bInstr->getDebugLoc(); 11528 MachineOperand& destOper = bInstr->getOperand(0); 11529 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11530 int numArgs = bInstr->getNumOperands() - 1; 11531 for (int i=0; i < numArgs; ++i) 11532 argOpers[i] = &bInstr->getOperand(i+1); 11533 11534 // x86 address has 4 operands: base, index, scale, and displacement 11535 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11536 int valArgIndx = lastAddrIndx + 1; 11537 11538 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11539 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11540 for (int i=0; i <= lastAddrIndx; ++i) 11541 (*MIB).addOperand(*argOpers[i]); 11542 11543 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11544 if (invSrc) { 11545 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11546 } 11547 else 11548 tt = t1; 11549 11550 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11551 assert((argOpers[valArgIndx]->isReg() || 11552 argOpers[valArgIndx]->isImm()) && 11553 "invalid operand"); 11554 if (argOpers[valArgIndx]->isReg()) 11555 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11556 else 11557 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11558 MIB.addReg(tt); 11559 (*MIB).addOperand(*argOpers[valArgIndx]); 11560 11561 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11562 MIB.addReg(t1); 11563 11564 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11565 for (int i=0; i <= lastAddrIndx; ++i) 11566 (*MIB).addOperand(*argOpers[i]); 11567 MIB.addReg(t2); 11568 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11569 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11570 bInstr->memoperands_end()); 11571 11572 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11573 MIB.addReg(EAXreg); 11574 11575 // insert branch 11576 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11577 11578 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11579 return nextMBB; 11580} 11581 11582// private utility function: 64 bit atomics on 32 bit host. 11583MachineBasicBlock * 11584X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11585 MachineBasicBlock *MBB, 11586 unsigned regOpcL, 11587 unsigned regOpcH, 11588 unsigned immOpcL, 11589 unsigned immOpcH, 11590 bool invSrc) const { 11591 // For the atomic bitwise operator, we generate 11592 // thisMBB (instructions are in pairs, except cmpxchg8b) 11593 // ld t1,t2 = [bitinstr.addr] 11594 // newMBB: 11595 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11596 // op t5, t6 <- out1, out2, [bitinstr.val] 11597 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11598 // mov ECX, EBX <- t5, t6 11599 // mov EAX, EDX <- t1, t2 11600 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11601 // mov t3, t4 <- EAX, EDX 11602 // bz newMBB 11603 // result in out1, out2 11604 // fallthrough -->nextMBB 11605 11606 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11607 const unsigned LoadOpc = X86::MOV32rm; 11608 const unsigned NotOpc = X86::NOT32r; 11609 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11610 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11611 MachineFunction::iterator MBBIter = MBB; 11612 ++MBBIter; 11613 11614 /// First build the CFG 11615 MachineFunction *F = MBB->getParent(); 11616 MachineBasicBlock *thisMBB = MBB; 11617 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11618 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11619 F->insert(MBBIter, newMBB); 11620 F->insert(MBBIter, nextMBB); 11621 11622 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11623 nextMBB->splice(nextMBB->begin(), thisMBB, 11624 llvm::next(MachineBasicBlock::iterator(bInstr)), 11625 thisMBB->end()); 11626 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11627 11628 // Update thisMBB to fall through to newMBB 11629 thisMBB->addSuccessor(newMBB); 11630 11631 // newMBB jumps to itself and fall through to nextMBB 11632 newMBB->addSuccessor(nextMBB); 11633 newMBB->addSuccessor(newMBB); 11634 11635 DebugLoc dl = bInstr->getDebugLoc(); 11636 // Insert instructions into newMBB based on incoming instruction 11637 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11638 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11639 "unexpected number of operands"); 11640 MachineOperand& dest1Oper = bInstr->getOperand(0); 11641 MachineOperand& dest2Oper = bInstr->getOperand(1); 11642 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11643 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11644 argOpers[i] = &bInstr->getOperand(i+2); 11645 11646 // We use some of the operands multiple times, so conservatively just 11647 // clear any kill flags that might be present. 11648 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11649 argOpers[i]->setIsKill(false); 11650 } 11651 11652 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11653 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11654 11655 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11656 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11657 for (int i=0; i <= lastAddrIndx; ++i) 11658 (*MIB).addOperand(*argOpers[i]); 11659 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11660 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11661 // add 4 to displacement. 11662 for (int i=0; i <= lastAddrIndx-2; ++i) 11663 (*MIB).addOperand(*argOpers[i]); 11664 MachineOperand newOp3 = *(argOpers[3]); 11665 if (newOp3.isImm()) 11666 newOp3.setImm(newOp3.getImm()+4); 11667 else 11668 newOp3.setOffset(newOp3.getOffset()+4); 11669 (*MIB).addOperand(newOp3); 11670 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11671 11672 // t3/4 are defined later, at the bottom of the loop 11673 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11674 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11675 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11676 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11677 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11678 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11679 11680 // The subsequent operations should be using the destination registers of 11681 //the PHI instructions. 11682 if (invSrc) { 11683 t1 = F->getRegInfo().createVirtualRegister(RC); 11684 t2 = F->getRegInfo().createVirtualRegister(RC); 11685 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11686 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11687 } else { 11688 t1 = dest1Oper.getReg(); 11689 t2 = dest2Oper.getReg(); 11690 } 11691 11692 int valArgIndx = lastAddrIndx + 1; 11693 assert((argOpers[valArgIndx]->isReg() || 11694 argOpers[valArgIndx]->isImm()) && 11695 "invalid operand"); 11696 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11697 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11698 if (argOpers[valArgIndx]->isReg()) 11699 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11700 else 11701 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11702 if (regOpcL != X86::MOV32rr) 11703 MIB.addReg(t1); 11704 (*MIB).addOperand(*argOpers[valArgIndx]); 11705 assert(argOpers[valArgIndx + 1]->isReg() == 11706 argOpers[valArgIndx]->isReg()); 11707 assert(argOpers[valArgIndx + 1]->isImm() == 11708 argOpers[valArgIndx]->isImm()); 11709 if (argOpers[valArgIndx + 1]->isReg()) 11710 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11711 else 11712 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11713 if (regOpcH != X86::MOV32rr) 11714 MIB.addReg(t2); 11715 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11716 11717 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11718 MIB.addReg(t1); 11719 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11720 MIB.addReg(t2); 11721 11722 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11723 MIB.addReg(t5); 11724 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11725 MIB.addReg(t6); 11726 11727 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11728 for (int i=0; i <= lastAddrIndx; ++i) 11729 (*MIB).addOperand(*argOpers[i]); 11730 11731 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11732 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11733 bInstr->memoperands_end()); 11734 11735 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11736 MIB.addReg(X86::EAX); 11737 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11738 MIB.addReg(X86::EDX); 11739 11740 // insert branch 11741 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11742 11743 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11744 return nextMBB; 11745} 11746 11747// private utility function 11748MachineBasicBlock * 11749X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11750 MachineBasicBlock *MBB, 11751 unsigned cmovOpc) const { 11752 // For the atomic min/max operator, we generate 11753 // thisMBB: 11754 // newMBB: 11755 // ld t1 = [min/max.addr] 11756 // mov t2 = [min/max.val] 11757 // cmp t1, t2 11758 // cmov[cond] t2 = t1 11759 // mov EAX = t1 11760 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11761 // bz newMBB 11762 // fallthrough -->nextMBB 11763 // 11764 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11765 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11766 MachineFunction::iterator MBBIter = MBB; 11767 ++MBBIter; 11768 11769 /// First build the CFG 11770 MachineFunction *F = MBB->getParent(); 11771 MachineBasicBlock *thisMBB = MBB; 11772 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11773 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11774 F->insert(MBBIter, newMBB); 11775 F->insert(MBBIter, nextMBB); 11776 11777 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11778 nextMBB->splice(nextMBB->begin(), thisMBB, 11779 llvm::next(MachineBasicBlock::iterator(mInstr)), 11780 thisMBB->end()); 11781 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11782 11783 // Update thisMBB to fall through to newMBB 11784 thisMBB->addSuccessor(newMBB); 11785 11786 // newMBB jumps to newMBB and fall through to nextMBB 11787 newMBB->addSuccessor(nextMBB); 11788 newMBB->addSuccessor(newMBB); 11789 11790 DebugLoc dl = mInstr->getDebugLoc(); 11791 // Insert instructions into newMBB based on incoming instruction 11792 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11793 "unexpected number of operands"); 11794 MachineOperand& destOper = mInstr->getOperand(0); 11795 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11796 int numArgs = mInstr->getNumOperands() - 1; 11797 for (int i=0; i < numArgs; ++i) 11798 argOpers[i] = &mInstr->getOperand(i+1); 11799 11800 // x86 address has 4 operands: base, index, scale, and displacement 11801 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11802 int valArgIndx = lastAddrIndx + 1; 11803 11804 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11805 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11806 for (int i=0; i <= lastAddrIndx; ++i) 11807 (*MIB).addOperand(*argOpers[i]); 11808 11809 // We only support register and immediate values 11810 assert((argOpers[valArgIndx]->isReg() || 11811 argOpers[valArgIndx]->isImm()) && 11812 "invalid operand"); 11813 11814 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11815 if (argOpers[valArgIndx]->isReg()) 11816 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11817 else 11818 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11819 (*MIB).addOperand(*argOpers[valArgIndx]); 11820 11821 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11822 MIB.addReg(t1); 11823 11824 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11825 MIB.addReg(t1); 11826 MIB.addReg(t2); 11827 11828 // Generate movc 11829 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11830 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11831 MIB.addReg(t2); 11832 MIB.addReg(t1); 11833 11834 // Cmp and exchange if none has modified the memory location 11835 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11836 for (int i=0; i <= lastAddrIndx; ++i) 11837 (*MIB).addOperand(*argOpers[i]); 11838 MIB.addReg(t3); 11839 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11840 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11841 mInstr->memoperands_end()); 11842 11843 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11844 MIB.addReg(X86::EAX); 11845 11846 // insert branch 11847 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11848 11849 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11850 return nextMBB; 11851} 11852 11853// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11854// or XMM0_V32I8 in AVX all of this code can be replaced with that 11855// in the .td file. 11856MachineBasicBlock * 11857X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11858 unsigned numArgs, bool memArg) const { 11859 assert(Subtarget->hasSSE42orAVX() && 11860 "Target must have SSE4.2 or AVX features enabled"); 11861 11862 DebugLoc dl = MI->getDebugLoc(); 11863 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11864 unsigned Opc; 11865 if (!Subtarget->hasAVX()) { 11866 if (memArg) 11867 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11868 else 11869 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11870 } else { 11871 if (memArg) 11872 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11873 else 11874 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11875 } 11876 11877 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11878 for (unsigned i = 0; i < numArgs; ++i) { 11879 MachineOperand &Op = MI->getOperand(i+1); 11880 if (!(Op.isReg() && Op.isImplicit())) 11881 MIB.addOperand(Op); 11882 } 11883 BuildMI(*BB, MI, dl, 11884 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11885 MI->getOperand(0).getReg()) 11886 .addReg(X86::XMM0); 11887 11888 MI->eraseFromParent(); 11889 return BB; 11890} 11891 11892MachineBasicBlock * 11893X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11894 DebugLoc dl = MI->getDebugLoc(); 11895 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11896 11897 // Address into RAX/EAX, other two args into ECX, EDX. 11898 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11899 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11900 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11901 for (int i = 0; i < X86::AddrNumOperands; ++i) 11902 MIB.addOperand(MI->getOperand(i)); 11903 11904 unsigned ValOps = X86::AddrNumOperands; 11905 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11906 .addReg(MI->getOperand(ValOps).getReg()); 11907 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11908 .addReg(MI->getOperand(ValOps+1).getReg()); 11909 11910 // The instruction doesn't actually take any operands though. 11911 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11912 11913 MI->eraseFromParent(); // The pseudo is gone now. 11914 return BB; 11915} 11916 11917MachineBasicBlock * 11918X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11919 DebugLoc dl = MI->getDebugLoc(); 11920 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11921 11922 // First arg in ECX, the second in EAX. 11923 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11924 .addReg(MI->getOperand(0).getReg()); 11925 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11926 .addReg(MI->getOperand(1).getReg()); 11927 11928 // The instruction doesn't actually take any operands though. 11929 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11930 11931 MI->eraseFromParent(); // The pseudo is gone now. 11932 return BB; 11933} 11934 11935MachineBasicBlock * 11936X86TargetLowering::EmitVAARG64WithCustomInserter( 11937 MachineInstr *MI, 11938 MachineBasicBlock *MBB) const { 11939 // Emit va_arg instruction on X86-64. 11940 11941 // Operands to this pseudo-instruction: 11942 // 0 ) Output : destination address (reg) 11943 // 1-5) Input : va_list address (addr, i64mem) 11944 // 6 ) ArgSize : Size (in bytes) of vararg type 11945 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11946 // 8 ) Align : Alignment of type 11947 // 9 ) EFLAGS (implicit-def) 11948 11949 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11950 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11951 11952 unsigned DestReg = MI->getOperand(0).getReg(); 11953 MachineOperand &Base = MI->getOperand(1); 11954 MachineOperand &Scale = MI->getOperand(2); 11955 MachineOperand &Index = MI->getOperand(3); 11956 MachineOperand &Disp = MI->getOperand(4); 11957 MachineOperand &Segment = MI->getOperand(5); 11958 unsigned ArgSize = MI->getOperand(6).getImm(); 11959 unsigned ArgMode = MI->getOperand(7).getImm(); 11960 unsigned Align = MI->getOperand(8).getImm(); 11961 11962 // Memory Reference 11963 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11964 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11965 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11966 11967 // Machine Information 11968 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11969 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11970 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11971 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11972 DebugLoc DL = MI->getDebugLoc(); 11973 11974 // struct va_list { 11975 // i32 gp_offset 11976 // i32 fp_offset 11977 // i64 overflow_area (address) 11978 // i64 reg_save_area (address) 11979 // } 11980 // sizeof(va_list) = 24 11981 // alignment(va_list) = 8 11982 11983 unsigned TotalNumIntRegs = 6; 11984 unsigned TotalNumXMMRegs = 8; 11985 bool UseGPOffset = (ArgMode == 1); 11986 bool UseFPOffset = (ArgMode == 2); 11987 unsigned MaxOffset = TotalNumIntRegs * 8 + 11988 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11989 11990 /* Align ArgSize to a multiple of 8 */ 11991 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11992 bool NeedsAlign = (Align > 8); 11993 11994 MachineBasicBlock *thisMBB = MBB; 11995 MachineBasicBlock *overflowMBB; 11996 MachineBasicBlock *offsetMBB; 11997 MachineBasicBlock *endMBB; 11998 11999 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 12000 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 12001 unsigned OffsetReg = 0; 12002 12003 if (!UseGPOffset && !UseFPOffset) { 12004 // If we only pull from the overflow region, we don't create a branch. 12005 // We don't need to alter control flow. 12006 OffsetDestReg = 0; // unused 12007 OverflowDestReg = DestReg; 12008 12009 offsetMBB = NULL; 12010 overflowMBB = thisMBB; 12011 endMBB = thisMBB; 12012 } else { 12013 // First emit code to check if gp_offset (or fp_offset) is below the bound. 12014 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 12015 // If not, pull from overflow_area. (branch to overflowMBB) 12016 // 12017 // thisMBB 12018 // | . 12019 // | . 12020 // offsetMBB overflowMBB 12021 // | . 12022 // | . 12023 // endMBB 12024 12025 // Registers for the PHI in endMBB 12026 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 12027 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 12028 12029 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12030 MachineFunction *MF = MBB->getParent(); 12031 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12032 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12033 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12034 12035 MachineFunction::iterator MBBIter = MBB; 12036 ++MBBIter; 12037 12038 // Insert the new basic blocks 12039 MF->insert(MBBIter, offsetMBB); 12040 MF->insert(MBBIter, overflowMBB); 12041 MF->insert(MBBIter, endMBB); 12042 12043 // Transfer the remainder of MBB and its successor edges to endMBB. 12044 endMBB->splice(endMBB->begin(), thisMBB, 12045 llvm::next(MachineBasicBlock::iterator(MI)), 12046 thisMBB->end()); 12047 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 12048 12049 // Make offsetMBB and overflowMBB successors of thisMBB 12050 thisMBB->addSuccessor(offsetMBB); 12051 thisMBB->addSuccessor(overflowMBB); 12052 12053 // endMBB is a successor of both offsetMBB and overflowMBB 12054 offsetMBB->addSuccessor(endMBB); 12055 overflowMBB->addSuccessor(endMBB); 12056 12057 // Load the offset value into a register 12058 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12059 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 12060 .addOperand(Base) 12061 .addOperand(Scale) 12062 .addOperand(Index) 12063 .addDisp(Disp, UseFPOffset ? 4 : 0) 12064 .addOperand(Segment) 12065 .setMemRefs(MMOBegin, MMOEnd); 12066 12067 // Check if there is enough room left to pull this argument. 12068 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 12069 .addReg(OffsetReg) 12070 .addImm(MaxOffset + 8 - ArgSizeA8); 12071 12072 // Branch to "overflowMBB" if offset >= max 12073 // Fall through to "offsetMBB" otherwise 12074 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 12075 .addMBB(overflowMBB); 12076 } 12077 12078 // In offsetMBB, emit code to use the reg_save_area. 12079 if (offsetMBB) { 12080 assert(OffsetReg != 0); 12081 12082 // Read the reg_save_area address. 12083 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 12084 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 12085 .addOperand(Base) 12086 .addOperand(Scale) 12087 .addOperand(Index) 12088 .addDisp(Disp, 16) 12089 .addOperand(Segment) 12090 .setMemRefs(MMOBegin, MMOEnd); 12091 12092 // Zero-extend the offset 12093 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 12094 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 12095 .addImm(0) 12096 .addReg(OffsetReg) 12097 .addImm(X86::sub_32bit); 12098 12099 // Add the offset to the reg_save_area to get the final address. 12100 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 12101 .addReg(OffsetReg64) 12102 .addReg(RegSaveReg); 12103 12104 // Compute the offset for the next argument 12105 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12106 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 12107 .addReg(OffsetReg) 12108 .addImm(UseFPOffset ? 16 : 8); 12109 12110 // Store it back into the va_list. 12111 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 12112 .addOperand(Base) 12113 .addOperand(Scale) 12114 .addOperand(Index) 12115 .addDisp(Disp, UseFPOffset ? 4 : 0) 12116 .addOperand(Segment) 12117 .addReg(NextOffsetReg) 12118 .setMemRefs(MMOBegin, MMOEnd); 12119 12120 // Jump to endMBB 12121 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 12122 .addMBB(endMBB); 12123 } 12124 12125 // 12126 // Emit code to use overflow area 12127 // 12128 12129 // Load the overflow_area address into a register. 12130 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 12131 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 12132 .addOperand(Base) 12133 .addOperand(Scale) 12134 .addOperand(Index) 12135 .addDisp(Disp, 8) 12136 .addOperand(Segment) 12137 .setMemRefs(MMOBegin, MMOEnd); 12138 12139 // If we need to align it, do so. Otherwise, just copy the address 12140 // to OverflowDestReg. 12141 if (NeedsAlign) { 12142 // Align the overflow address 12143 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 12144 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 12145 12146 // aligned_addr = (addr + (align-1)) & ~(align-1) 12147 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 12148 .addReg(OverflowAddrReg) 12149 .addImm(Align-1); 12150 12151 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 12152 .addReg(TmpReg) 12153 .addImm(~(uint64_t)(Align-1)); 12154 } else { 12155 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 12156 .addReg(OverflowAddrReg); 12157 } 12158 12159 // Compute the next overflow address after this argument. 12160 // (the overflow address should be kept 8-byte aligned) 12161 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 12162 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 12163 .addReg(OverflowDestReg) 12164 .addImm(ArgSizeA8); 12165 12166 // Store the new overflow address. 12167 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 12168 .addOperand(Base) 12169 .addOperand(Scale) 12170 .addOperand(Index) 12171 .addDisp(Disp, 8) 12172 .addOperand(Segment) 12173 .addReg(NextAddrReg) 12174 .setMemRefs(MMOBegin, MMOEnd); 12175 12176 // If we branched, emit the PHI to the front of endMBB. 12177 if (offsetMBB) { 12178 BuildMI(*endMBB, endMBB->begin(), DL, 12179 TII->get(X86::PHI), DestReg) 12180 .addReg(OffsetDestReg).addMBB(offsetMBB) 12181 .addReg(OverflowDestReg).addMBB(overflowMBB); 12182 } 12183 12184 // Erase the pseudo instruction 12185 MI->eraseFromParent(); 12186 12187 return endMBB; 12188} 12189 12190MachineBasicBlock * 12191X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 12192 MachineInstr *MI, 12193 MachineBasicBlock *MBB) const { 12194 // Emit code to save XMM registers to the stack. The ABI says that the 12195 // number of registers to save is given in %al, so it's theoretically 12196 // possible to do an indirect jump trick to avoid saving all of them, 12197 // however this code takes a simpler approach and just executes all 12198 // of the stores if %al is non-zero. It's less code, and it's probably 12199 // easier on the hardware branch predictor, and stores aren't all that 12200 // expensive anyway. 12201 12202 // Create the new basic blocks. One block contains all the XMM stores, 12203 // and one block is the final destination regardless of whether any 12204 // stores were performed. 12205 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12206 MachineFunction *F = MBB->getParent(); 12207 MachineFunction::iterator MBBIter = MBB; 12208 ++MBBIter; 12209 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12210 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12211 F->insert(MBBIter, XMMSaveMBB); 12212 F->insert(MBBIter, EndMBB); 12213 12214 // Transfer the remainder of MBB and its successor edges to EndMBB. 12215 EndMBB->splice(EndMBB->begin(), MBB, 12216 llvm::next(MachineBasicBlock::iterator(MI)), 12217 MBB->end()); 12218 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12219 12220 // The original block will now fall through to the XMM save block. 12221 MBB->addSuccessor(XMMSaveMBB); 12222 // The XMMSaveMBB will fall through to the end block. 12223 XMMSaveMBB->addSuccessor(EndMBB); 12224 12225 // Now add the instructions. 12226 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12227 DebugLoc DL = MI->getDebugLoc(); 12228 12229 unsigned CountReg = MI->getOperand(0).getReg(); 12230 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12231 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12232 12233 if (!Subtarget->isTargetWin64()) { 12234 // If %al is 0, branch around the XMM save block. 12235 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12236 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12237 MBB->addSuccessor(EndMBB); 12238 } 12239 12240 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12241 // In the XMM save block, save all the XMM argument registers. 12242 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12243 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12244 MachineMemOperand *MMO = 12245 F->getMachineMemOperand( 12246 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12247 MachineMemOperand::MOStore, 12248 /*Size=*/16, /*Align=*/16); 12249 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12250 .addFrameIndex(RegSaveFrameIndex) 12251 .addImm(/*Scale=*/1) 12252 .addReg(/*IndexReg=*/0) 12253 .addImm(/*Disp=*/Offset) 12254 .addReg(/*Segment=*/0) 12255 .addReg(MI->getOperand(i).getReg()) 12256 .addMemOperand(MMO); 12257 } 12258 12259 MI->eraseFromParent(); // The pseudo instruction is gone now. 12260 12261 return EndMBB; 12262} 12263 12264MachineBasicBlock * 12265X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12266 MachineBasicBlock *BB) const { 12267 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12268 DebugLoc DL = MI->getDebugLoc(); 12269 12270 // To "insert" a SELECT_CC instruction, we actually have to insert the 12271 // diamond control-flow pattern. The incoming instruction knows the 12272 // destination vreg to set, the condition code register to branch on, the 12273 // true/false values to select between, and a branch opcode to use. 12274 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12275 MachineFunction::iterator It = BB; 12276 ++It; 12277 12278 // thisMBB: 12279 // ... 12280 // TrueVal = ... 12281 // cmpTY ccX, r1, r2 12282 // bCC copy1MBB 12283 // fallthrough --> copy0MBB 12284 MachineBasicBlock *thisMBB = BB; 12285 MachineFunction *F = BB->getParent(); 12286 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12287 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12288 F->insert(It, copy0MBB); 12289 F->insert(It, sinkMBB); 12290 12291 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12292 // live into the sink and copy blocks. 12293 if (!MI->killsRegister(X86::EFLAGS)) { 12294 copy0MBB->addLiveIn(X86::EFLAGS); 12295 sinkMBB->addLiveIn(X86::EFLAGS); 12296 } 12297 12298 // Transfer the remainder of BB and its successor edges to sinkMBB. 12299 sinkMBB->splice(sinkMBB->begin(), BB, 12300 llvm::next(MachineBasicBlock::iterator(MI)), 12301 BB->end()); 12302 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12303 12304 // Add the true and fallthrough blocks as its successors. 12305 BB->addSuccessor(copy0MBB); 12306 BB->addSuccessor(sinkMBB); 12307 12308 // Create the conditional branch instruction. 12309 unsigned Opc = 12310 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12311 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12312 12313 // copy0MBB: 12314 // %FalseValue = ... 12315 // # fallthrough to sinkMBB 12316 copy0MBB->addSuccessor(sinkMBB); 12317 12318 // sinkMBB: 12319 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12320 // ... 12321 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12322 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12323 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12324 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12325 12326 MI->eraseFromParent(); // The pseudo instruction is gone now. 12327 return sinkMBB; 12328} 12329 12330MachineBasicBlock * 12331X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12332 bool Is64Bit) const { 12333 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12334 DebugLoc DL = MI->getDebugLoc(); 12335 MachineFunction *MF = BB->getParent(); 12336 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12337 12338 assert(EnableSegmentedStacks); 12339 12340 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12341 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12342 12343 // BB: 12344 // ... [Till the alloca] 12345 // If stacklet is not large enough, jump to mallocMBB 12346 // 12347 // bumpMBB: 12348 // Allocate by subtracting from RSP 12349 // Jump to continueMBB 12350 // 12351 // mallocMBB: 12352 // Allocate by call to runtime 12353 // 12354 // continueMBB: 12355 // ... 12356 // [rest of original BB] 12357 // 12358 12359 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12360 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12361 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12362 12363 MachineRegisterInfo &MRI = MF->getRegInfo(); 12364 const TargetRegisterClass *AddrRegClass = 12365 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12366 12367 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12368 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12369 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12370 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12371 sizeVReg = MI->getOperand(1).getReg(), 12372 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12373 12374 MachineFunction::iterator MBBIter = BB; 12375 ++MBBIter; 12376 12377 MF->insert(MBBIter, bumpMBB); 12378 MF->insert(MBBIter, mallocMBB); 12379 MF->insert(MBBIter, continueMBB); 12380 12381 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12382 (MachineBasicBlock::iterator(MI)), BB->end()); 12383 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12384 12385 // Add code to the main basic block to check if the stack limit has been hit, 12386 // and if so, jump to mallocMBB otherwise to bumpMBB. 12387 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12388 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12389 .addReg(tmpSPVReg).addReg(sizeVReg); 12390 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12391 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12392 .addReg(SPLimitVReg); 12393 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12394 12395 // bumpMBB simply decreases the stack pointer, since we know the current 12396 // stacklet has enough space. 12397 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12398 .addReg(SPLimitVReg); 12399 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12400 .addReg(SPLimitVReg); 12401 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12402 12403 // Calls into a routine in libgcc to allocate more space from the heap. 12404 if (Is64Bit) { 12405 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12406 .addReg(sizeVReg); 12407 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12408 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 12409 } else { 12410 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12411 .addImm(12); 12412 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12413 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12414 .addExternalSymbol("__morestack_allocate_stack_space"); 12415 } 12416 12417 if (!Is64Bit) 12418 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12419 .addImm(16); 12420 12421 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12422 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12423 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12424 12425 // Set up the CFG correctly. 12426 BB->addSuccessor(bumpMBB); 12427 BB->addSuccessor(mallocMBB); 12428 mallocMBB->addSuccessor(continueMBB); 12429 bumpMBB->addSuccessor(continueMBB); 12430 12431 // Take care of the PHI nodes. 12432 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12433 MI->getOperand(0).getReg()) 12434 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12435 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12436 12437 // Delete the original pseudo instruction. 12438 MI->eraseFromParent(); 12439 12440 // And we're done. 12441 return continueMBB; 12442} 12443 12444MachineBasicBlock * 12445X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12446 MachineBasicBlock *BB) const { 12447 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12448 DebugLoc DL = MI->getDebugLoc(); 12449 12450 assert(!Subtarget->isTargetEnvMacho()); 12451 12452 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12453 // non-trivial part is impdef of ESP. 12454 12455 if (Subtarget->isTargetWin64()) { 12456 if (Subtarget->isTargetCygMing()) { 12457 // ___chkstk(Mingw64): 12458 // Clobbers R10, R11, RAX and EFLAGS. 12459 // Updates RSP. 12460 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12461 .addExternalSymbol("___chkstk") 12462 .addReg(X86::RAX, RegState::Implicit) 12463 .addReg(X86::RSP, RegState::Implicit) 12464 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12465 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12466 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12467 } else { 12468 // __chkstk(MSVCRT): does not update stack pointer. 12469 // Clobbers R10, R11 and EFLAGS. 12470 // FIXME: RAX(allocated size) might be reused and not killed. 12471 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12472 .addExternalSymbol("__chkstk") 12473 .addReg(X86::RAX, RegState::Implicit) 12474 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12475 // RAX has the offset to subtracted from RSP. 12476 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12477 .addReg(X86::RSP) 12478 .addReg(X86::RAX); 12479 } 12480 } else { 12481 const char *StackProbeSymbol = 12482 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12483 12484 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12485 .addExternalSymbol(StackProbeSymbol) 12486 .addReg(X86::EAX, RegState::Implicit) 12487 .addReg(X86::ESP, RegState::Implicit) 12488 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12489 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12490 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12491 } 12492 12493 MI->eraseFromParent(); // The pseudo instruction is gone now. 12494 return BB; 12495} 12496 12497MachineBasicBlock * 12498X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12499 MachineBasicBlock *BB) const { 12500 // This is pretty easy. We're taking the value that we received from 12501 // our load from the relocation, sticking it in either RDI (x86-64) 12502 // or EAX and doing an indirect call. The return value will then 12503 // be in the normal return register. 12504 const X86InstrInfo *TII 12505 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12506 DebugLoc DL = MI->getDebugLoc(); 12507 MachineFunction *F = BB->getParent(); 12508 12509 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12510 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12511 12512 if (Subtarget->is64Bit()) { 12513 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12514 TII->get(X86::MOV64rm), X86::RDI) 12515 .addReg(X86::RIP) 12516 .addImm(0).addReg(0) 12517 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12518 MI->getOperand(3).getTargetFlags()) 12519 .addReg(0); 12520 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12521 addDirectMem(MIB, X86::RDI); 12522 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12523 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12524 TII->get(X86::MOV32rm), X86::EAX) 12525 .addReg(0) 12526 .addImm(0).addReg(0) 12527 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12528 MI->getOperand(3).getTargetFlags()) 12529 .addReg(0); 12530 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12531 addDirectMem(MIB, X86::EAX); 12532 } else { 12533 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12534 TII->get(X86::MOV32rm), X86::EAX) 12535 .addReg(TII->getGlobalBaseReg(F)) 12536 .addImm(0).addReg(0) 12537 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12538 MI->getOperand(3).getTargetFlags()) 12539 .addReg(0); 12540 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12541 addDirectMem(MIB, X86::EAX); 12542 } 12543 12544 MI->eraseFromParent(); // The pseudo instruction is gone now. 12545 return BB; 12546} 12547 12548MachineBasicBlock * 12549X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12550 MachineBasicBlock *BB) const { 12551 switch (MI->getOpcode()) { 12552 default: assert(0 && "Unexpected instr type to insert"); 12553 case X86::TAILJMPd64: 12554 case X86::TAILJMPr64: 12555 case X86::TAILJMPm64: 12556 assert(0 && "TAILJMP64 would not be touched here."); 12557 case X86::TCRETURNdi64: 12558 case X86::TCRETURNri64: 12559 case X86::TCRETURNmi64: 12560 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 12561 // On AMD64, additional defs should be added before register allocation. 12562 if (!Subtarget->isTargetWin64()) { 12563 MI->addRegisterDefined(X86::RSI); 12564 MI->addRegisterDefined(X86::RDI); 12565 MI->addRegisterDefined(X86::XMM6); 12566 MI->addRegisterDefined(X86::XMM7); 12567 MI->addRegisterDefined(X86::XMM8); 12568 MI->addRegisterDefined(X86::XMM9); 12569 MI->addRegisterDefined(X86::XMM10); 12570 MI->addRegisterDefined(X86::XMM11); 12571 MI->addRegisterDefined(X86::XMM12); 12572 MI->addRegisterDefined(X86::XMM13); 12573 MI->addRegisterDefined(X86::XMM14); 12574 MI->addRegisterDefined(X86::XMM15); 12575 } 12576 return BB; 12577 case X86::WIN_ALLOCA: 12578 return EmitLoweredWinAlloca(MI, BB); 12579 case X86::SEG_ALLOCA_32: 12580 return EmitLoweredSegAlloca(MI, BB, false); 12581 case X86::SEG_ALLOCA_64: 12582 return EmitLoweredSegAlloca(MI, BB, true); 12583 case X86::TLSCall_32: 12584 case X86::TLSCall_64: 12585 return EmitLoweredTLSCall(MI, BB); 12586 case X86::CMOV_GR8: 12587 case X86::CMOV_FR32: 12588 case X86::CMOV_FR64: 12589 case X86::CMOV_V4F32: 12590 case X86::CMOV_V2F64: 12591 case X86::CMOV_V2I64: 12592 case X86::CMOV_V8F32: 12593 case X86::CMOV_V4F64: 12594 case X86::CMOV_V4I64: 12595 case X86::CMOV_GR16: 12596 case X86::CMOV_GR32: 12597 case X86::CMOV_RFP32: 12598 case X86::CMOV_RFP64: 12599 case X86::CMOV_RFP80: 12600 return EmitLoweredSelect(MI, BB); 12601 12602 case X86::FP32_TO_INT16_IN_MEM: 12603 case X86::FP32_TO_INT32_IN_MEM: 12604 case X86::FP32_TO_INT64_IN_MEM: 12605 case X86::FP64_TO_INT16_IN_MEM: 12606 case X86::FP64_TO_INT32_IN_MEM: 12607 case X86::FP64_TO_INT64_IN_MEM: 12608 case X86::FP80_TO_INT16_IN_MEM: 12609 case X86::FP80_TO_INT32_IN_MEM: 12610 case X86::FP80_TO_INT64_IN_MEM: { 12611 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12612 DebugLoc DL = MI->getDebugLoc(); 12613 12614 // Change the floating point control register to use "round towards zero" 12615 // mode when truncating to an integer value. 12616 MachineFunction *F = BB->getParent(); 12617 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12618 addFrameReference(BuildMI(*BB, MI, DL, 12619 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12620 12621 // Load the old value of the high byte of the control word... 12622 unsigned OldCW = 12623 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12624 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12625 CWFrameIdx); 12626 12627 // Set the high part to be round to zero... 12628 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12629 .addImm(0xC7F); 12630 12631 // Reload the modified control word now... 12632 addFrameReference(BuildMI(*BB, MI, DL, 12633 TII->get(X86::FLDCW16m)), CWFrameIdx); 12634 12635 // Restore the memory image of control word to original value 12636 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12637 .addReg(OldCW); 12638 12639 // Get the X86 opcode to use. 12640 unsigned Opc; 12641 switch (MI->getOpcode()) { 12642 default: llvm_unreachable("illegal opcode!"); 12643 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12644 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12645 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12646 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12647 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12648 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12649 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12650 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12651 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12652 } 12653 12654 X86AddressMode AM; 12655 MachineOperand &Op = MI->getOperand(0); 12656 if (Op.isReg()) { 12657 AM.BaseType = X86AddressMode::RegBase; 12658 AM.Base.Reg = Op.getReg(); 12659 } else { 12660 AM.BaseType = X86AddressMode::FrameIndexBase; 12661 AM.Base.FrameIndex = Op.getIndex(); 12662 } 12663 Op = MI->getOperand(1); 12664 if (Op.isImm()) 12665 AM.Scale = Op.getImm(); 12666 Op = MI->getOperand(2); 12667 if (Op.isImm()) 12668 AM.IndexReg = Op.getImm(); 12669 Op = MI->getOperand(3); 12670 if (Op.isGlobal()) { 12671 AM.GV = Op.getGlobal(); 12672 } else { 12673 AM.Disp = Op.getImm(); 12674 } 12675 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12676 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12677 12678 // Reload the original control word now. 12679 addFrameReference(BuildMI(*BB, MI, DL, 12680 TII->get(X86::FLDCW16m)), CWFrameIdx); 12681 12682 MI->eraseFromParent(); // The pseudo instruction is gone now. 12683 return BB; 12684 } 12685 // String/text processing lowering. 12686 case X86::PCMPISTRM128REG: 12687 case X86::VPCMPISTRM128REG: 12688 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12689 case X86::PCMPISTRM128MEM: 12690 case X86::VPCMPISTRM128MEM: 12691 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12692 case X86::PCMPESTRM128REG: 12693 case X86::VPCMPESTRM128REG: 12694 return EmitPCMP(MI, BB, 5, false /* in mem */); 12695 case X86::PCMPESTRM128MEM: 12696 case X86::VPCMPESTRM128MEM: 12697 return EmitPCMP(MI, BB, 5, true /* in mem */); 12698 12699 // Thread synchronization. 12700 case X86::MONITOR: 12701 return EmitMonitor(MI, BB); 12702 case X86::MWAIT: 12703 return EmitMwait(MI, BB); 12704 12705 // Atomic Lowering. 12706 case X86::ATOMAND32: 12707 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12708 X86::AND32ri, X86::MOV32rm, 12709 X86::LCMPXCHG32, 12710 X86::NOT32r, X86::EAX, 12711 X86::GR32RegisterClass); 12712 case X86::ATOMOR32: 12713 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12714 X86::OR32ri, X86::MOV32rm, 12715 X86::LCMPXCHG32, 12716 X86::NOT32r, X86::EAX, 12717 X86::GR32RegisterClass); 12718 case X86::ATOMXOR32: 12719 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12720 X86::XOR32ri, X86::MOV32rm, 12721 X86::LCMPXCHG32, 12722 X86::NOT32r, X86::EAX, 12723 X86::GR32RegisterClass); 12724 case X86::ATOMNAND32: 12725 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12726 X86::AND32ri, X86::MOV32rm, 12727 X86::LCMPXCHG32, 12728 X86::NOT32r, X86::EAX, 12729 X86::GR32RegisterClass, true); 12730 case X86::ATOMMIN32: 12731 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12732 case X86::ATOMMAX32: 12733 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12734 case X86::ATOMUMIN32: 12735 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12736 case X86::ATOMUMAX32: 12737 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12738 12739 case X86::ATOMAND16: 12740 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12741 X86::AND16ri, X86::MOV16rm, 12742 X86::LCMPXCHG16, 12743 X86::NOT16r, X86::AX, 12744 X86::GR16RegisterClass); 12745 case X86::ATOMOR16: 12746 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12747 X86::OR16ri, X86::MOV16rm, 12748 X86::LCMPXCHG16, 12749 X86::NOT16r, X86::AX, 12750 X86::GR16RegisterClass); 12751 case X86::ATOMXOR16: 12752 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12753 X86::XOR16ri, X86::MOV16rm, 12754 X86::LCMPXCHG16, 12755 X86::NOT16r, X86::AX, 12756 X86::GR16RegisterClass); 12757 case X86::ATOMNAND16: 12758 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12759 X86::AND16ri, X86::MOV16rm, 12760 X86::LCMPXCHG16, 12761 X86::NOT16r, X86::AX, 12762 X86::GR16RegisterClass, true); 12763 case X86::ATOMMIN16: 12764 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12765 case X86::ATOMMAX16: 12766 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12767 case X86::ATOMUMIN16: 12768 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12769 case X86::ATOMUMAX16: 12770 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12771 12772 case X86::ATOMAND8: 12773 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12774 X86::AND8ri, X86::MOV8rm, 12775 X86::LCMPXCHG8, 12776 X86::NOT8r, X86::AL, 12777 X86::GR8RegisterClass); 12778 case X86::ATOMOR8: 12779 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12780 X86::OR8ri, X86::MOV8rm, 12781 X86::LCMPXCHG8, 12782 X86::NOT8r, X86::AL, 12783 X86::GR8RegisterClass); 12784 case X86::ATOMXOR8: 12785 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12786 X86::XOR8ri, X86::MOV8rm, 12787 X86::LCMPXCHG8, 12788 X86::NOT8r, X86::AL, 12789 X86::GR8RegisterClass); 12790 case X86::ATOMNAND8: 12791 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12792 X86::AND8ri, X86::MOV8rm, 12793 X86::LCMPXCHG8, 12794 X86::NOT8r, X86::AL, 12795 X86::GR8RegisterClass, true); 12796 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12797 // This group is for 64-bit host. 12798 case X86::ATOMAND64: 12799 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12800 X86::AND64ri32, X86::MOV64rm, 12801 X86::LCMPXCHG64, 12802 X86::NOT64r, X86::RAX, 12803 X86::GR64RegisterClass); 12804 case X86::ATOMOR64: 12805 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12806 X86::OR64ri32, X86::MOV64rm, 12807 X86::LCMPXCHG64, 12808 X86::NOT64r, X86::RAX, 12809 X86::GR64RegisterClass); 12810 case X86::ATOMXOR64: 12811 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12812 X86::XOR64ri32, X86::MOV64rm, 12813 X86::LCMPXCHG64, 12814 X86::NOT64r, X86::RAX, 12815 X86::GR64RegisterClass); 12816 case X86::ATOMNAND64: 12817 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12818 X86::AND64ri32, X86::MOV64rm, 12819 X86::LCMPXCHG64, 12820 X86::NOT64r, X86::RAX, 12821 X86::GR64RegisterClass, true); 12822 case X86::ATOMMIN64: 12823 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12824 case X86::ATOMMAX64: 12825 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12826 case X86::ATOMUMIN64: 12827 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12828 case X86::ATOMUMAX64: 12829 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12830 12831 // This group does 64-bit operations on a 32-bit host. 12832 case X86::ATOMAND6432: 12833 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12834 X86::AND32rr, X86::AND32rr, 12835 X86::AND32ri, X86::AND32ri, 12836 false); 12837 case X86::ATOMOR6432: 12838 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12839 X86::OR32rr, X86::OR32rr, 12840 X86::OR32ri, X86::OR32ri, 12841 false); 12842 case X86::ATOMXOR6432: 12843 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12844 X86::XOR32rr, X86::XOR32rr, 12845 X86::XOR32ri, X86::XOR32ri, 12846 false); 12847 case X86::ATOMNAND6432: 12848 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12849 X86::AND32rr, X86::AND32rr, 12850 X86::AND32ri, X86::AND32ri, 12851 true); 12852 case X86::ATOMADD6432: 12853 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12854 X86::ADD32rr, X86::ADC32rr, 12855 X86::ADD32ri, X86::ADC32ri, 12856 false); 12857 case X86::ATOMSUB6432: 12858 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12859 X86::SUB32rr, X86::SBB32rr, 12860 X86::SUB32ri, X86::SBB32ri, 12861 false); 12862 case X86::ATOMSWAP6432: 12863 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12864 X86::MOV32rr, X86::MOV32rr, 12865 X86::MOV32ri, X86::MOV32ri, 12866 false); 12867 case X86::VASTART_SAVE_XMM_REGS: 12868 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12869 12870 case X86::VAARG_64: 12871 return EmitVAARG64WithCustomInserter(MI, BB); 12872 } 12873} 12874 12875//===----------------------------------------------------------------------===// 12876// X86 Optimization Hooks 12877//===----------------------------------------------------------------------===// 12878 12879void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12880 const APInt &Mask, 12881 APInt &KnownZero, 12882 APInt &KnownOne, 12883 const SelectionDAG &DAG, 12884 unsigned Depth) const { 12885 unsigned Opc = Op.getOpcode(); 12886 assert((Opc >= ISD::BUILTIN_OP_END || 12887 Opc == ISD::INTRINSIC_WO_CHAIN || 12888 Opc == ISD::INTRINSIC_W_CHAIN || 12889 Opc == ISD::INTRINSIC_VOID) && 12890 "Should use MaskedValueIsZero if you don't know whether Op" 12891 " is a target node!"); 12892 12893 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12894 switch (Opc) { 12895 default: break; 12896 case X86ISD::ADD: 12897 case X86ISD::SUB: 12898 case X86ISD::ADC: 12899 case X86ISD::SBB: 12900 case X86ISD::SMUL: 12901 case X86ISD::UMUL: 12902 case X86ISD::INC: 12903 case X86ISD::DEC: 12904 case X86ISD::OR: 12905 case X86ISD::XOR: 12906 case X86ISD::AND: 12907 // These nodes' second result is a boolean. 12908 if (Op.getResNo() == 0) 12909 break; 12910 // Fallthrough 12911 case X86ISD::SETCC: 12912 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12913 Mask.getBitWidth() - 1); 12914 break; 12915 case ISD::INTRINSIC_WO_CHAIN: { 12916 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12917 unsigned NumLoBits = 0; 12918 switch (IntId) { 12919 default: break; 12920 case Intrinsic::x86_sse_movmsk_ps: 12921 case Intrinsic::x86_avx_movmsk_ps_256: 12922 case Intrinsic::x86_sse2_movmsk_pd: 12923 case Intrinsic::x86_avx_movmsk_pd_256: 12924 case Intrinsic::x86_mmx_pmovmskb: 12925 case Intrinsic::x86_sse2_pmovmskb_128: { 12926 // High bits of movmskp{s|d}, pmovmskb are known zero. 12927 switch (IntId) { 12928 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12929 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12930 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12931 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12932 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12933 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12934 } 12935 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12936 Mask.getBitWidth() - NumLoBits); 12937 break; 12938 } 12939 } 12940 break; 12941 } 12942 } 12943} 12944 12945unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12946 unsigned Depth) const { 12947 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12948 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12949 return Op.getValueType().getScalarType().getSizeInBits(); 12950 12951 // Fallback case. 12952 return 1; 12953} 12954 12955/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12956/// node is a GlobalAddress + offset. 12957bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12958 const GlobalValue* &GA, 12959 int64_t &Offset) const { 12960 if (N->getOpcode() == X86ISD::Wrapper) { 12961 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12962 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12963 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12964 return true; 12965 } 12966 } 12967 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12968} 12969 12970/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12971/// same as extracting the high 128-bit part of 256-bit vector and then 12972/// inserting the result into the low part of a new 256-bit vector 12973static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12974 EVT VT = SVOp->getValueType(0); 12975 int NumElems = VT.getVectorNumElements(); 12976 12977 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12978 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12979 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12980 SVOp->getMaskElt(j) >= 0) 12981 return false; 12982 12983 return true; 12984} 12985 12986/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12987/// same as extracting the low 128-bit part of 256-bit vector and then 12988/// inserting the result into the high part of a new 256-bit vector 12989static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12990 EVT VT = SVOp->getValueType(0); 12991 int NumElems = VT.getVectorNumElements(); 12992 12993 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12994 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12995 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12996 SVOp->getMaskElt(j) >= 0) 12997 return false; 12998 12999 return true; 13000} 13001 13002/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 13003static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 13004 TargetLowering::DAGCombinerInfo &DCI) { 13005 DebugLoc dl = N->getDebugLoc(); 13006 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 13007 SDValue V1 = SVOp->getOperand(0); 13008 SDValue V2 = SVOp->getOperand(1); 13009 EVT VT = SVOp->getValueType(0); 13010 int NumElems = VT.getVectorNumElements(); 13011 13012 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 13013 V2.getOpcode() == ISD::CONCAT_VECTORS) { 13014 // 13015 // 0,0,0,... 13016 // | 13017 // V UNDEF BUILD_VECTOR UNDEF 13018 // \ / \ / 13019 // CONCAT_VECTOR CONCAT_VECTOR 13020 // \ / 13021 // \ / 13022 // RESULT: V + zero extended 13023 // 13024 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 13025 V2.getOperand(1).getOpcode() != ISD::UNDEF || 13026 V1.getOperand(1).getOpcode() != ISD::UNDEF) 13027 return SDValue(); 13028 13029 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 13030 return SDValue(); 13031 13032 // To match the shuffle mask, the first half of the mask should 13033 // be exactly the first vector, and all the rest a splat with the 13034 // first element of the second one. 13035 for (int i = 0; i < NumElems/2; ++i) 13036 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 13037 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 13038 return SDValue(); 13039 13040 // Emit a zeroed vector and insert the desired subvector on its 13041 // first half. 13042 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 13043 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 13044 DAG.getConstant(0, MVT::i32), DAG, dl); 13045 return DCI.CombineTo(N, InsV); 13046 } 13047 13048 //===--------------------------------------------------------------------===// 13049 // Combine some shuffles into subvector extracts and inserts: 13050 // 13051 13052 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 13053 if (isShuffleHigh128VectorInsertLow(SVOp)) { 13054 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 13055 DAG, dl); 13056 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 13057 V, DAG.getConstant(0, MVT::i32), DAG, dl); 13058 return DCI.CombineTo(N, InsV); 13059 } 13060 13061 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 13062 if (isShuffleLow128VectorInsertHigh(SVOp)) { 13063 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 13064 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 13065 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 13066 return DCI.CombineTo(N, InsV); 13067 } 13068 13069 return SDValue(); 13070} 13071 13072/// PerformShuffleCombine - Performs several different shuffle combines. 13073static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 13074 TargetLowering::DAGCombinerInfo &DCI, 13075 const X86Subtarget *Subtarget) { 13076 DebugLoc dl = N->getDebugLoc(); 13077 EVT VT = N->getValueType(0); 13078 13079 // Don't create instructions with illegal types after legalize types has run. 13080 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13081 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 13082 return SDValue(); 13083 13084 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 13085 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 13086 N->getOpcode() == ISD::VECTOR_SHUFFLE) 13087 return PerformShuffleCombine256(N, DAG, DCI); 13088 13089 // Only handle 128 wide vector from here on. 13090 if (VT.getSizeInBits() != 128) 13091 return SDValue(); 13092 13093 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 13094 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 13095 // consecutive, non-overlapping, and in the right order. 13096 SmallVector<SDValue, 16> Elts; 13097 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 13098 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 13099 13100 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 13101} 13102 13103/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13104/// generation and convert it from being a bunch of shuffles and extracts 13105/// to a simple store and scalar loads to extract the elements. 13106static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13107 const TargetLowering &TLI) { 13108 SDValue InputVector = N->getOperand(0); 13109 13110 // Only operate on vectors of 4 elements, where the alternative shuffling 13111 // gets to be more expensive. 13112 if (InputVector.getValueType() != MVT::v4i32) 13113 return SDValue(); 13114 13115 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13116 // single use which is a sign-extend or zero-extend, and all elements are 13117 // used. 13118 SmallVector<SDNode *, 4> Uses; 13119 unsigned ExtractedElements = 0; 13120 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13121 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13122 if (UI.getUse().getResNo() != InputVector.getResNo()) 13123 return SDValue(); 13124 13125 SDNode *Extract = *UI; 13126 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13127 return SDValue(); 13128 13129 if (Extract->getValueType(0) != MVT::i32) 13130 return SDValue(); 13131 if (!Extract->hasOneUse()) 13132 return SDValue(); 13133 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13134 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13135 return SDValue(); 13136 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13137 return SDValue(); 13138 13139 // Record which element was extracted. 13140 ExtractedElements |= 13141 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13142 13143 Uses.push_back(Extract); 13144 } 13145 13146 // If not all the elements were used, this may not be worthwhile. 13147 if (ExtractedElements != 15) 13148 return SDValue(); 13149 13150 // Ok, we've now decided to do the transformation. 13151 DebugLoc dl = InputVector.getDebugLoc(); 13152 13153 // Store the value to a temporary stack slot. 13154 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13155 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13156 MachinePointerInfo(), false, false, 0); 13157 13158 // Replace each use (extract) with a load of the appropriate element. 13159 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13160 UE = Uses.end(); UI != UE; ++UI) { 13161 SDNode *Extract = *UI; 13162 13163 // cOMpute the element's address. 13164 SDValue Idx = Extract->getOperand(1); 13165 unsigned EltSize = 13166 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13167 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13168 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13169 13170 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13171 StackPtr, OffsetVal); 13172 13173 // Load the scalar. 13174 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13175 ScalarAddr, MachinePointerInfo(), 13176 false, false, false, 0); 13177 13178 // Replace the exact with the load. 13179 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13180 } 13181 13182 // The replacement was made in place; don't return anything. 13183 return SDValue(); 13184} 13185 13186/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13187/// nodes. 13188static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13189 const X86Subtarget *Subtarget) { 13190 DebugLoc DL = N->getDebugLoc(); 13191 SDValue Cond = N->getOperand(0); 13192 // Get the LHS/RHS of the select. 13193 SDValue LHS = N->getOperand(1); 13194 SDValue RHS = N->getOperand(2); 13195 EVT VT = LHS.getValueType(); 13196 13197 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13198 // instructions match the semantics of the common C idiom x<y?x:y but not 13199 // x<=y?x:y, because of how they handle negative zero (which can be 13200 // ignored in unsafe-math mode). 13201 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13202 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13203 (Subtarget->hasXMMInt() || 13204 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13205 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13206 13207 unsigned Opcode = 0; 13208 // Check for x CC y ? x : y. 13209 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13210 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13211 switch (CC) { 13212 default: break; 13213 case ISD::SETULT: 13214 // Converting this to a min would handle NaNs incorrectly, and swapping 13215 // the operands would cause it to handle comparisons between positive 13216 // and negative zero incorrectly. 13217 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13218 if (!UnsafeFPMath && 13219 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13220 break; 13221 std::swap(LHS, RHS); 13222 } 13223 Opcode = X86ISD::FMIN; 13224 break; 13225 case ISD::SETOLE: 13226 // Converting this to a min would handle comparisons between positive 13227 // and negative zero incorrectly. 13228 if (!UnsafeFPMath && 13229 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13230 break; 13231 Opcode = X86ISD::FMIN; 13232 break; 13233 case ISD::SETULE: 13234 // Converting this to a min would handle both negative zeros and NaNs 13235 // incorrectly, but we can swap the operands to fix both. 13236 std::swap(LHS, RHS); 13237 case ISD::SETOLT: 13238 case ISD::SETLT: 13239 case ISD::SETLE: 13240 Opcode = X86ISD::FMIN; 13241 break; 13242 13243 case ISD::SETOGE: 13244 // Converting this to a max would handle comparisons between positive 13245 // and negative zero incorrectly. 13246 if (!UnsafeFPMath && 13247 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13248 break; 13249 Opcode = X86ISD::FMAX; 13250 break; 13251 case ISD::SETUGT: 13252 // Converting this to a max would handle NaNs incorrectly, and swapping 13253 // the operands would cause it to handle comparisons between positive 13254 // and negative zero incorrectly. 13255 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13256 if (!UnsafeFPMath && 13257 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13258 break; 13259 std::swap(LHS, RHS); 13260 } 13261 Opcode = X86ISD::FMAX; 13262 break; 13263 case ISD::SETUGE: 13264 // Converting this to a max would handle both negative zeros and NaNs 13265 // incorrectly, but we can swap the operands to fix both. 13266 std::swap(LHS, RHS); 13267 case ISD::SETOGT: 13268 case ISD::SETGT: 13269 case ISD::SETGE: 13270 Opcode = X86ISD::FMAX; 13271 break; 13272 } 13273 // Check for x CC y ? y : x -- a min/max with reversed arms. 13274 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13275 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13276 switch (CC) { 13277 default: break; 13278 case ISD::SETOGE: 13279 // Converting this to a min would handle comparisons between positive 13280 // and negative zero incorrectly, and swapping the operands would 13281 // cause it to handle NaNs incorrectly. 13282 if (!UnsafeFPMath && 13283 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13284 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13285 break; 13286 std::swap(LHS, RHS); 13287 } 13288 Opcode = X86ISD::FMIN; 13289 break; 13290 case ISD::SETUGT: 13291 // Converting this to a min would handle NaNs incorrectly. 13292 if (!UnsafeFPMath && 13293 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13294 break; 13295 Opcode = X86ISD::FMIN; 13296 break; 13297 case ISD::SETUGE: 13298 // Converting this to a min would handle both negative zeros and NaNs 13299 // incorrectly, but we can swap the operands to fix both. 13300 std::swap(LHS, RHS); 13301 case ISD::SETOGT: 13302 case ISD::SETGT: 13303 case ISD::SETGE: 13304 Opcode = X86ISD::FMIN; 13305 break; 13306 13307 case ISD::SETULT: 13308 // Converting this to a max would handle NaNs incorrectly. 13309 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13310 break; 13311 Opcode = X86ISD::FMAX; 13312 break; 13313 case ISD::SETOLE: 13314 // Converting this to a max would handle comparisons between positive 13315 // and negative zero incorrectly, and swapping the operands would 13316 // cause it to handle NaNs incorrectly. 13317 if (!UnsafeFPMath && 13318 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13319 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13320 break; 13321 std::swap(LHS, RHS); 13322 } 13323 Opcode = X86ISD::FMAX; 13324 break; 13325 case ISD::SETULE: 13326 // Converting this to a max would handle both negative zeros and NaNs 13327 // incorrectly, but we can swap the operands to fix both. 13328 std::swap(LHS, RHS); 13329 case ISD::SETOLT: 13330 case ISD::SETLT: 13331 case ISD::SETLE: 13332 Opcode = X86ISD::FMAX; 13333 break; 13334 } 13335 } 13336 13337 if (Opcode) 13338 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13339 } 13340 13341 // If this is a select between two integer constants, try to do some 13342 // optimizations. 13343 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13344 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13345 // Don't do this for crazy integer types. 13346 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13347 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13348 // so that TrueC (the true value) is larger than FalseC. 13349 bool NeedsCondInvert = false; 13350 13351 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13352 // Efficiently invertible. 13353 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13354 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13355 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13356 NeedsCondInvert = true; 13357 std::swap(TrueC, FalseC); 13358 } 13359 13360 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13361 if (FalseC->getAPIntValue() == 0 && 13362 TrueC->getAPIntValue().isPowerOf2()) { 13363 if (NeedsCondInvert) // Invert the condition if needed. 13364 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13365 DAG.getConstant(1, Cond.getValueType())); 13366 13367 // Zero extend the condition if needed. 13368 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13369 13370 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13371 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13372 DAG.getConstant(ShAmt, MVT::i8)); 13373 } 13374 13375 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13376 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13377 if (NeedsCondInvert) // Invert the condition if needed. 13378 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13379 DAG.getConstant(1, Cond.getValueType())); 13380 13381 // Zero extend the condition if needed. 13382 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13383 FalseC->getValueType(0), Cond); 13384 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13385 SDValue(FalseC, 0)); 13386 } 13387 13388 // Optimize cases that will turn into an LEA instruction. This requires 13389 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13390 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13391 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13392 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13393 13394 bool isFastMultiplier = false; 13395 if (Diff < 10) { 13396 switch ((unsigned char)Diff) { 13397 default: break; 13398 case 1: // result = add base, cond 13399 case 2: // result = lea base( , cond*2) 13400 case 3: // result = lea base(cond, cond*2) 13401 case 4: // result = lea base( , cond*4) 13402 case 5: // result = lea base(cond, cond*4) 13403 case 8: // result = lea base( , cond*8) 13404 case 9: // result = lea base(cond, cond*8) 13405 isFastMultiplier = true; 13406 break; 13407 } 13408 } 13409 13410 if (isFastMultiplier) { 13411 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13412 if (NeedsCondInvert) // Invert the condition if needed. 13413 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13414 DAG.getConstant(1, Cond.getValueType())); 13415 13416 // Zero extend the condition if needed. 13417 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13418 Cond); 13419 // Scale the condition by the difference. 13420 if (Diff != 1) 13421 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13422 DAG.getConstant(Diff, Cond.getValueType())); 13423 13424 // Add the base if non-zero. 13425 if (FalseC->getAPIntValue() != 0) 13426 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13427 SDValue(FalseC, 0)); 13428 return Cond; 13429 } 13430 } 13431 } 13432 } 13433 13434 return SDValue(); 13435} 13436 13437/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13438static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13439 TargetLowering::DAGCombinerInfo &DCI) { 13440 DebugLoc DL = N->getDebugLoc(); 13441 13442 // If the flag operand isn't dead, don't touch this CMOV. 13443 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13444 return SDValue(); 13445 13446 SDValue FalseOp = N->getOperand(0); 13447 SDValue TrueOp = N->getOperand(1); 13448 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13449 SDValue Cond = N->getOperand(3); 13450 if (CC == X86::COND_E || CC == X86::COND_NE) { 13451 switch (Cond.getOpcode()) { 13452 default: break; 13453 case X86ISD::BSR: 13454 case X86ISD::BSF: 13455 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13456 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13457 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13458 } 13459 } 13460 13461 // If this is a select between two integer constants, try to do some 13462 // optimizations. Note that the operands are ordered the opposite of SELECT 13463 // operands. 13464 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13465 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13466 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13467 // larger than FalseC (the false value). 13468 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13469 CC = X86::GetOppositeBranchCondition(CC); 13470 std::swap(TrueC, FalseC); 13471 } 13472 13473 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13474 // This is efficient for any integer data type (including i8/i16) and 13475 // shift amount. 13476 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13477 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13478 DAG.getConstant(CC, MVT::i8), Cond); 13479 13480 // Zero extend the condition if needed. 13481 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13482 13483 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13484 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13485 DAG.getConstant(ShAmt, MVT::i8)); 13486 if (N->getNumValues() == 2) // Dead flag value? 13487 return DCI.CombineTo(N, Cond, SDValue()); 13488 return Cond; 13489 } 13490 13491 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13492 // for any integer data type, including i8/i16. 13493 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13494 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13495 DAG.getConstant(CC, MVT::i8), Cond); 13496 13497 // Zero extend the condition if needed. 13498 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13499 FalseC->getValueType(0), Cond); 13500 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13501 SDValue(FalseC, 0)); 13502 13503 if (N->getNumValues() == 2) // Dead flag value? 13504 return DCI.CombineTo(N, Cond, SDValue()); 13505 return Cond; 13506 } 13507 13508 // Optimize cases that will turn into an LEA instruction. This requires 13509 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13510 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13511 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13512 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13513 13514 bool isFastMultiplier = false; 13515 if (Diff < 10) { 13516 switch ((unsigned char)Diff) { 13517 default: break; 13518 case 1: // result = add base, cond 13519 case 2: // result = lea base( , cond*2) 13520 case 3: // result = lea base(cond, cond*2) 13521 case 4: // result = lea base( , cond*4) 13522 case 5: // result = lea base(cond, cond*4) 13523 case 8: // result = lea base( , cond*8) 13524 case 9: // result = lea base(cond, cond*8) 13525 isFastMultiplier = true; 13526 break; 13527 } 13528 } 13529 13530 if (isFastMultiplier) { 13531 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13532 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13533 DAG.getConstant(CC, MVT::i8), Cond); 13534 // Zero extend the condition if needed. 13535 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13536 Cond); 13537 // Scale the condition by the difference. 13538 if (Diff != 1) 13539 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13540 DAG.getConstant(Diff, Cond.getValueType())); 13541 13542 // Add the base if non-zero. 13543 if (FalseC->getAPIntValue() != 0) 13544 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13545 SDValue(FalseC, 0)); 13546 if (N->getNumValues() == 2) // Dead flag value? 13547 return DCI.CombineTo(N, Cond, SDValue()); 13548 return Cond; 13549 } 13550 } 13551 } 13552 } 13553 return SDValue(); 13554} 13555 13556 13557/// PerformMulCombine - Optimize a single multiply with constant into two 13558/// in order to implement it with two cheaper instructions, e.g. 13559/// LEA + SHL, LEA + LEA. 13560static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13561 TargetLowering::DAGCombinerInfo &DCI) { 13562 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13563 return SDValue(); 13564 13565 EVT VT = N->getValueType(0); 13566 if (VT != MVT::i64) 13567 return SDValue(); 13568 13569 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13570 if (!C) 13571 return SDValue(); 13572 uint64_t MulAmt = C->getZExtValue(); 13573 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13574 return SDValue(); 13575 13576 uint64_t MulAmt1 = 0; 13577 uint64_t MulAmt2 = 0; 13578 if ((MulAmt % 9) == 0) { 13579 MulAmt1 = 9; 13580 MulAmt2 = MulAmt / 9; 13581 } else if ((MulAmt % 5) == 0) { 13582 MulAmt1 = 5; 13583 MulAmt2 = MulAmt / 5; 13584 } else if ((MulAmt % 3) == 0) { 13585 MulAmt1 = 3; 13586 MulAmt2 = MulAmt / 3; 13587 } 13588 if (MulAmt2 && 13589 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13590 DebugLoc DL = N->getDebugLoc(); 13591 13592 if (isPowerOf2_64(MulAmt2) && 13593 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13594 // If second multiplifer is pow2, issue it first. We want the multiply by 13595 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13596 // is an add. 13597 std::swap(MulAmt1, MulAmt2); 13598 13599 SDValue NewMul; 13600 if (isPowerOf2_64(MulAmt1)) 13601 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13602 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13603 else 13604 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13605 DAG.getConstant(MulAmt1, VT)); 13606 13607 if (isPowerOf2_64(MulAmt2)) 13608 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13609 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13610 else 13611 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13612 DAG.getConstant(MulAmt2, VT)); 13613 13614 // Do not add new nodes to DAG combiner worklist. 13615 DCI.CombineTo(N, NewMul, false); 13616 } 13617 return SDValue(); 13618} 13619 13620static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13621 SDValue N0 = N->getOperand(0); 13622 SDValue N1 = N->getOperand(1); 13623 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13624 EVT VT = N0.getValueType(); 13625 13626 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13627 // since the result of setcc_c is all zero's or all ones. 13628 if (VT.isInteger() && !VT.isVector() && 13629 N1C && N0.getOpcode() == ISD::AND && 13630 N0.getOperand(1).getOpcode() == ISD::Constant) { 13631 SDValue N00 = N0.getOperand(0); 13632 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13633 ((N00.getOpcode() == ISD::ANY_EXTEND || 13634 N00.getOpcode() == ISD::ZERO_EXTEND) && 13635 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13636 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13637 APInt ShAmt = N1C->getAPIntValue(); 13638 Mask = Mask.shl(ShAmt); 13639 if (Mask != 0) 13640 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13641 N00, DAG.getConstant(Mask, VT)); 13642 } 13643 } 13644 13645 13646 // Hardware support for vector shifts is sparse which makes us scalarize the 13647 // vector operations in many cases. Also, on sandybridge ADD is faster than 13648 // shl. 13649 // (shl V, 1) -> add V,V 13650 if (isSplatVector(N1.getNode())) { 13651 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13653 // We shift all of the values by one. In many cases we do not have 13654 // hardware support for this operation. This is better expressed as an ADD 13655 // of two values. 13656 if (N1C && (1 == N1C->getZExtValue())) { 13657 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13658 } 13659 } 13660 13661 return SDValue(); 13662} 13663 13664/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13665/// when possible. 13666static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13667 const X86Subtarget *Subtarget) { 13668 EVT VT = N->getValueType(0); 13669 if (N->getOpcode() == ISD::SHL) { 13670 SDValue V = PerformSHLCombine(N, DAG); 13671 if (V.getNode()) return V; 13672 } 13673 13674 // On X86 with SSE2 support, we can transform this to a vector shift if 13675 // all elements are shifted by the same amount. We can't do this in legalize 13676 // because the a constant vector is typically transformed to a constant pool 13677 // so we have no knowledge of the shift amount. 13678 if (!Subtarget->hasXMMInt()) 13679 return SDValue(); 13680 13681 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13682 (!Subtarget->hasAVX2() || 13683 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13684 return SDValue(); 13685 13686 SDValue ShAmtOp = N->getOperand(1); 13687 EVT EltVT = VT.getVectorElementType(); 13688 DebugLoc DL = N->getDebugLoc(); 13689 SDValue BaseShAmt = SDValue(); 13690 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13691 unsigned NumElts = VT.getVectorNumElements(); 13692 unsigned i = 0; 13693 for (; i != NumElts; ++i) { 13694 SDValue Arg = ShAmtOp.getOperand(i); 13695 if (Arg.getOpcode() == ISD::UNDEF) continue; 13696 BaseShAmt = Arg; 13697 break; 13698 } 13699 for (; i != NumElts; ++i) { 13700 SDValue Arg = ShAmtOp.getOperand(i); 13701 if (Arg.getOpcode() == ISD::UNDEF) continue; 13702 if (Arg != BaseShAmt) { 13703 return SDValue(); 13704 } 13705 } 13706 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13707 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13708 SDValue InVec = ShAmtOp.getOperand(0); 13709 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13710 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13711 unsigned i = 0; 13712 for (; i != NumElts; ++i) { 13713 SDValue Arg = InVec.getOperand(i); 13714 if (Arg.getOpcode() == ISD::UNDEF) continue; 13715 BaseShAmt = Arg; 13716 break; 13717 } 13718 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13719 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13720 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13721 if (C->getZExtValue() == SplatIdx) 13722 BaseShAmt = InVec.getOperand(1); 13723 } 13724 } 13725 if (BaseShAmt.getNode() == 0) 13726 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13727 DAG.getIntPtrConstant(0)); 13728 } else 13729 return SDValue(); 13730 13731 // The shift amount is an i32. 13732 if (EltVT.bitsGT(MVT::i32)) 13733 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13734 else if (EltVT.bitsLT(MVT::i32)) 13735 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13736 13737 // The shift amount is identical so we can do a vector shift. 13738 SDValue ValOp = N->getOperand(0); 13739 switch (N->getOpcode()) { 13740 default: 13741 llvm_unreachable("Unknown shift opcode!"); 13742 break; 13743 case ISD::SHL: 13744 if (VT == MVT::v2i64) 13745 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13746 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 13747 ValOp, BaseShAmt); 13748 if (VT == MVT::v4i32) 13749 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13750 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 13751 ValOp, BaseShAmt); 13752 if (VT == MVT::v8i16) 13753 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13754 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 13755 ValOp, BaseShAmt); 13756 if (VT == MVT::v4i64) 13757 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13758 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 13759 ValOp, BaseShAmt); 13760 if (VT == MVT::v8i32) 13761 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13762 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32), 13763 ValOp, BaseShAmt); 13764 if (VT == MVT::v16i16) 13765 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13766 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 13767 ValOp, BaseShAmt); 13768 break; 13769 case ISD::SRA: 13770 if (VT == MVT::v4i32) 13771 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13772 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 13773 ValOp, BaseShAmt); 13774 if (VT == MVT::v8i16) 13775 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13776 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 13777 ValOp, BaseShAmt); 13778 if (VT == MVT::v8i32) 13779 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13780 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32), 13781 ValOp, BaseShAmt); 13782 if (VT == MVT::v16i16) 13783 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13784 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32), 13785 ValOp, BaseShAmt); 13786 break; 13787 case ISD::SRL: 13788 if (VT == MVT::v2i64) 13789 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13790 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 13791 ValOp, BaseShAmt); 13792 if (VT == MVT::v4i32) 13793 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13794 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 13795 ValOp, BaseShAmt); 13796 if (VT == MVT::v8i16) 13797 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13798 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 13799 ValOp, BaseShAmt); 13800 if (VT == MVT::v4i64) 13801 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13802 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 13803 ValOp, BaseShAmt); 13804 if (VT == MVT::v8i32) 13805 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13806 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32), 13807 ValOp, BaseShAmt); 13808 if (VT == MVT::v16i16) 13809 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13810 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 13811 ValOp, BaseShAmt); 13812 break; 13813 } 13814 return SDValue(); 13815} 13816 13817 13818// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13819// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13820// and friends. Likewise for OR -> CMPNEQSS. 13821static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13822 TargetLowering::DAGCombinerInfo &DCI, 13823 const X86Subtarget *Subtarget) { 13824 unsigned opcode; 13825 13826 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13827 // we're requiring SSE2 for both. 13828 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13829 SDValue N0 = N->getOperand(0); 13830 SDValue N1 = N->getOperand(1); 13831 SDValue CMP0 = N0->getOperand(1); 13832 SDValue CMP1 = N1->getOperand(1); 13833 DebugLoc DL = N->getDebugLoc(); 13834 13835 // The SETCCs should both refer to the same CMP. 13836 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13837 return SDValue(); 13838 13839 SDValue CMP00 = CMP0->getOperand(0); 13840 SDValue CMP01 = CMP0->getOperand(1); 13841 EVT VT = CMP00.getValueType(); 13842 13843 if (VT == MVT::f32 || VT == MVT::f64) { 13844 bool ExpectingFlags = false; 13845 // Check for any users that want flags: 13846 for (SDNode::use_iterator UI = N->use_begin(), 13847 UE = N->use_end(); 13848 !ExpectingFlags && UI != UE; ++UI) 13849 switch (UI->getOpcode()) { 13850 default: 13851 case ISD::BR_CC: 13852 case ISD::BRCOND: 13853 case ISD::SELECT: 13854 ExpectingFlags = true; 13855 break; 13856 case ISD::CopyToReg: 13857 case ISD::SIGN_EXTEND: 13858 case ISD::ZERO_EXTEND: 13859 case ISD::ANY_EXTEND: 13860 break; 13861 } 13862 13863 if (!ExpectingFlags) { 13864 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13865 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13866 13867 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13868 X86::CondCode tmp = cc0; 13869 cc0 = cc1; 13870 cc1 = tmp; 13871 } 13872 13873 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13874 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13875 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13876 X86ISD::NodeType NTOperator = is64BitFP ? 13877 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13878 // FIXME: need symbolic constants for these magic numbers. 13879 // See X86ATTInstPrinter.cpp:printSSECC(). 13880 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13881 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13882 DAG.getConstant(x86cc, MVT::i8)); 13883 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13884 OnesOrZeroesF); 13885 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13886 DAG.getConstant(1, MVT::i32)); 13887 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13888 return OneBitOfTruth; 13889 } 13890 } 13891 } 13892 } 13893 return SDValue(); 13894} 13895 13896/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13897/// so it can be folded inside ANDNP. 13898static bool CanFoldXORWithAllOnes(const SDNode *N) { 13899 EVT VT = N->getValueType(0); 13900 13901 // Match direct AllOnes for 128 and 256-bit vectors 13902 if (ISD::isBuildVectorAllOnes(N)) 13903 return true; 13904 13905 // Look through a bit convert. 13906 if (N->getOpcode() == ISD::BITCAST) 13907 N = N->getOperand(0).getNode(); 13908 13909 // Sometimes the operand may come from a insert_subvector building a 256-bit 13910 // allones vector 13911 if (VT.getSizeInBits() == 256 && 13912 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13913 SDValue V1 = N->getOperand(0); 13914 SDValue V2 = N->getOperand(1); 13915 13916 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13917 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13918 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13919 ISD::isBuildVectorAllOnes(V2.getNode())) 13920 return true; 13921 } 13922 13923 return false; 13924} 13925 13926static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13927 TargetLowering::DAGCombinerInfo &DCI, 13928 const X86Subtarget *Subtarget) { 13929 if (DCI.isBeforeLegalizeOps()) 13930 return SDValue(); 13931 13932 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13933 if (R.getNode()) 13934 return R; 13935 13936 EVT VT = N->getValueType(0); 13937 13938 // Create ANDN, BLSI, and BLSR instructions 13939 // BLSI is X & (-X) 13940 // BLSR is X & (X-1) 13941 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13942 SDValue N0 = N->getOperand(0); 13943 SDValue N1 = N->getOperand(1); 13944 DebugLoc DL = N->getDebugLoc(); 13945 13946 // Check LHS for not 13947 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13948 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13949 // Check RHS for not 13950 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13951 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13952 13953 // Check LHS for neg 13954 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13955 isZero(N0.getOperand(0))) 13956 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13957 13958 // Check RHS for neg 13959 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13960 isZero(N1.getOperand(0))) 13961 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13962 13963 // Check LHS for X-1 13964 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13965 isAllOnes(N0.getOperand(1))) 13966 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13967 13968 // Check RHS for X-1 13969 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13970 isAllOnes(N1.getOperand(1))) 13971 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13972 13973 return SDValue(); 13974 } 13975 13976 // Want to form ANDNP nodes: 13977 // 1) In the hopes of then easily combining them with OR and AND nodes 13978 // to form PBLEND/PSIGN. 13979 // 2) To match ANDN packed intrinsics 13980 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13981 return SDValue(); 13982 13983 SDValue N0 = N->getOperand(0); 13984 SDValue N1 = N->getOperand(1); 13985 DebugLoc DL = N->getDebugLoc(); 13986 13987 // Check LHS for vnot 13988 if (N0.getOpcode() == ISD::XOR && 13989 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13990 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13991 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13992 13993 // Check RHS for vnot 13994 if (N1.getOpcode() == ISD::XOR && 13995 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13996 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13997 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13998 13999 return SDValue(); 14000} 14001 14002static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14003 TargetLowering::DAGCombinerInfo &DCI, 14004 const X86Subtarget *Subtarget) { 14005 if (DCI.isBeforeLegalizeOps()) 14006 return SDValue(); 14007 14008 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14009 if (R.getNode()) 14010 return R; 14011 14012 EVT VT = N->getValueType(0); 14013 14014 SDValue N0 = N->getOperand(0); 14015 SDValue N1 = N->getOperand(1); 14016 14017 // look for psign/blend 14018 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14019 if (!Subtarget->hasSSSE3orAVX() || 14020 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14021 return SDValue(); 14022 14023 // Canonicalize pandn to RHS 14024 if (N0.getOpcode() == X86ISD::ANDNP) 14025 std::swap(N0, N1); 14026 // or (and (m, x), (pandn m, y)) 14027 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14028 SDValue Mask = N1.getOperand(0); 14029 SDValue X = N1.getOperand(1); 14030 SDValue Y; 14031 if (N0.getOperand(0) == Mask) 14032 Y = N0.getOperand(1); 14033 if (N0.getOperand(1) == Mask) 14034 Y = N0.getOperand(0); 14035 14036 // Check to see if the mask appeared in both the AND and ANDNP and 14037 if (!Y.getNode()) 14038 return SDValue(); 14039 14040 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14041 if (Mask.getOpcode() != ISD::BITCAST || 14042 X.getOpcode() != ISD::BITCAST || 14043 Y.getOpcode() != ISD::BITCAST) 14044 return SDValue(); 14045 14046 // Look through mask bitcast. 14047 Mask = Mask.getOperand(0); 14048 EVT MaskVT = Mask.getValueType(); 14049 14050 // Validate that the Mask operand is a vector sra node. The sra node 14051 // will be an intrinsic. 14052 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 14053 return SDValue(); 14054 14055 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14056 // there is no psrai.b 14057 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 14058 case Intrinsic::x86_sse2_psrai_w: 14059 case Intrinsic::x86_sse2_psrai_d: 14060 case Intrinsic::x86_avx2_psrai_w: 14061 case Intrinsic::x86_avx2_psrai_d: 14062 break; 14063 default: return SDValue(); 14064 } 14065 14066 // Check that the SRA is all signbits. 14067 SDValue SraC = Mask.getOperand(2); 14068 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14069 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14070 if ((SraAmt + 1) != EltBits) 14071 return SDValue(); 14072 14073 DebugLoc DL = N->getDebugLoc(); 14074 14075 // Now we know we at least have a plendvb with the mask val. See if 14076 // we can form a psignb/w/d. 14077 // psign = x.type == y.type == mask.type && y = sub(0, x); 14078 X = X.getOperand(0); 14079 Y = Y.getOperand(0); 14080 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14081 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14082 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() && 14083 (EltBits == 8 || EltBits == 16 || EltBits == 32)) { 14084 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, 14085 Mask.getOperand(1)); 14086 return DAG.getNode(ISD::BITCAST, DL, VT, Sign); 14087 } 14088 // PBLENDVB only available on SSE 4.1 14089 if (!Subtarget->hasSSE41orAVX()) 14090 return SDValue(); 14091 14092 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14093 14094 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14095 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14096 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14097 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, X, Y); 14098 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14099 } 14100 } 14101 14102 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14103 return SDValue(); 14104 14105 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14106 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14107 std::swap(N0, N1); 14108 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14109 return SDValue(); 14110 if (!N0.hasOneUse() || !N1.hasOneUse()) 14111 return SDValue(); 14112 14113 SDValue ShAmt0 = N0.getOperand(1); 14114 if (ShAmt0.getValueType() != MVT::i8) 14115 return SDValue(); 14116 SDValue ShAmt1 = N1.getOperand(1); 14117 if (ShAmt1.getValueType() != MVT::i8) 14118 return SDValue(); 14119 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14120 ShAmt0 = ShAmt0.getOperand(0); 14121 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14122 ShAmt1 = ShAmt1.getOperand(0); 14123 14124 DebugLoc DL = N->getDebugLoc(); 14125 unsigned Opc = X86ISD::SHLD; 14126 SDValue Op0 = N0.getOperand(0); 14127 SDValue Op1 = N1.getOperand(0); 14128 if (ShAmt0.getOpcode() == ISD::SUB) { 14129 Opc = X86ISD::SHRD; 14130 std::swap(Op0, Op1); 14131 std::swap(ShAmt0, ShAmt1); 14132 } 14133 14134 unsigned Bits = VT.getSizeInBits(); 14135 if (ShAmt1.getOpcode() == ISD::SUB) { 14136 SDValue Sum = ShAmt1.getOperand(0); 14137 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14138 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14139 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14140 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14141 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14142 return DAG.getNode(Opc, DL, VT, 14143 Op0, Op1, 14144 DAG.getNode(ISD::TRUNCATE, DL, 14145 MVT::i8, ShAmt0)); 14146 } 14147 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14148 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14149 if (ShAmt0C && 14150 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14151 return DAG.getNode(Opc, DL, VT, 14152 N0.getOperand(0), N1.getOperand(0), 14153 DAG.getNode(ISD::TRUNCATE, DL, 14154 MVT::i8, ShAmt0)); 14155 } 14156 14157 return SDValue(); 14158} 14159 14160static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14161 TargetLowering::DAGCombinerInfo &DCI, 14162 const X86Subtarget *Subtarget) { 14163 if (DCI.isBeforeLegalizeOps()) 14164 return SDValue(); 14165 14166 EVT VT = N->getValueType(0); 14167 14168 if (VT != MVT::i32 && VT != MVT::i64) 14169 return SDValue(); 14170 14171 // Create BLSMSK instructions by finding X ^ (X-1) 14172 SDValue N0 = N->getOperand(0); 14173 SDValue N1 = N->getOperand(1); 14174 DebugLoc DL = N->getDebugLoc(); 14175 14176 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14177 isAllOnes(N0.getOperand(1))) 14178 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14179 14180 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14181 isAllOnes(N1.getOperand(1))) 14182 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14183 14184 return SDValue(); 14185} 14186 14187/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14188static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14189 const X86Subtarget *Subtarget) { 14190 LoadSDNode *Ld = cast<LoadSDNode>(N); 14191 EVT RegVT = Ld->getValueType(0); 14192 EVT MemVT = Ld->getMemoryVT(); 14193 DebugLoc dl = Ld->getDebugLoc(); 14194 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14195 14196 ISD::LoadExtType Ext = Ld->getExtensionType(); 14197 14198 // If this is a vector EXT Load then attempt to optimize it using a 14199 // shuffle. We need SSE4 for the shuffles. 14200 // TODO: It is possible to support ZExt by zeroing the undef values 14201 // during the shuffle phase or after the shuffle. 14202 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14203 assert(MemVT != RegVT && "Cannot extend to the same type"); 14204 assert(MemVT.isVector() && "Must load a vector from memory"); 14205 14206 unsigned NumElems = RegVT.getVectorNumElements(); 14207 unsigned RegSz = RegVT.getSizeInBits(); 14208 unsigned MemSz = MemVT.getSizeInBits(); 14209 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14210 // All sizes must be a power of two 14211 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14212 14213 // Attempt to load the original value using a single load op. 14214 // Find a scalar type which is equal to the loaded word size. 14215 MVT SclrLoadTy = MVT::i8; 14216 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14217 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14218 MVT Tp = (MVT::SimpleValueType)tp; 14219 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14220 SclrLoadTy = Tp; 14221 break; 14222 } 14223 } 14224 14225 // Proceed if a load word is found. 14226 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14227 14228 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14229 RegSz/SclrLoadTy.getSizeInBits()); 14230 14231 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14232 RegSz/MemVT.getScalarType().getSizeInBits()); 14233 // Can't shuffle using an illegal type. 14234 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14235 14236 // Perform a single load. 14237 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14238 Ld->getBasePtr(), 14239 Ld->getPointerInfo(), Ld->isVolatile(), 14240 Ld->isNonTemporal(), Ld->isInvariant(), 14241 Ld->getAlignment()); 14242 14243 // Insert the word loaded into a vector. 14244 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14245 LoadUnitVecVT, ScalarLoad); 14246 14247 // Bitcast the loaded value to a vector of the original element type, in 14248 // the size of the target vector type. 14249 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector); 14250 unsigned SizeRatio = RegSz/MemSz; 14251 14252 // Redistribute the loaded elements into the different locations. 14253 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14254 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14255 14256 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14257 DAG.getUNDEF(SlicedVec.getValueType()), 14258 ShuffleVec.data()); 14259 14260 // Bitcast to the requested type. 14261 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14262 // Replace the original load with the new sequence 14263 // and return the new chain. 14264 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14265 return SDValue(ScalarLoad.getNode(), 1); 14266 } 14267 14268 return SDValue(); 14269} 14270 14271/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14272static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14273 const X86Subtarget *Subtarget) { 14274 StoreSDNode *St = cast<StoreSDNode>(N); 14275 EVT VT = St->getValue().getValueType(); 14276 EVT StVT = St->getMemoryVT(); 14277 DebugLoc dl = St->getDebugLoc(); 14278 SDValue StoredVal = St->getOperand(1); 14279 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14280 14281 // If we are saving a concatination of two XMM registers, perform two stores. 14282 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14283 // 128-bit ones. If in the future the cost becomes only one memory access the 14284 // first version would be better. 14285 if (VT.getSizeInBits() == 256 && 14286 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14287 StoredVal.getNumOperands() == 2) { 14288 14289 SDValue Value0 = StoredVal.getOperand(0); 14290 SDValue Value1 = StoredVal.getOperand(1); 14291 14292 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14293 SDValue Ptr0 = St->getBasePtr(); 14294 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14295 14296 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14297 St->getPointerInfo(), St->isVolatile(), 14298 St->isNonTemporal(), St->getAlignment()); 14299 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14300 St->getPointerInfo(), St->isVolatile(), 14301 St->isNonTemporal(), St->getAlignment()); 14302 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14303 } 14304 14305 // Optimize trunc store (of multiple scalars) to shuffle and store. 14306 // First, pack all of the elements in one place. Next, store to memory 14307 // in fewer chunks. 14308 if (St->isTruncatingStore() && VT.isVector()) { 14309 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14310 unsigned NumElems = VT.getVectorNumElements(); 14311 assert(StVT != VT && "Cannot truncate to the same type"); 14312 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14313 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14314 14315 // From, To sizes and ElemCount must be pow of two 14316 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14317 // We are going to use the original vector elt for storing. 14318 // Accumulated smaller vector elements must be a multiple of the store size. 14319 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14320 14321 unsigned SizeRatio = FromSz / ToSz; 14322 14323 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14324 14325 // Create a type on which we perform the shuffle 14326 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14327 StVT.getScalarType(), NumElems*SizeRatio); 14328 14329 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14330 14331 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14332 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14333 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14334 14335 // Can't shuffle using an illegal type 14336 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14337 14338 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14339 DAG.getUNDEF(WideVec.getValueType()), 14340 ShuffleVec.data()); 14341 // At this point all of the data is stored at the bottom of the 14342 // register. We now need to save it to mem. 14343 14344 // Find the largest store unit 14345 MVT StoreType = MVT::i8; 14346 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14347 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14348 MVT Tp = (MVT::SimpleValueType)tp; 14349 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14350 StoreType = Tp; 14351 } 14352 14353 // Bitcast the original vector into a vector of store-size units 14354 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14355 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14356 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14357 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14358 SmallVector<SDValue, 8> Chains; 14359 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14360 TLI.getPointerTy()); 14361 SDValue Ptr = St->getBasePtr(); 14362 14363 // Perform one or more big stores into memory. 14364 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14365 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14366 StoreType, ShuffWide, 14367 DAG.getIntPtrConstant(i)); 14368 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14369 St->getPointerInfo(), St->isVolatile(), 14370 St->isNonTemporal(), St->getAlignment()); 14371 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14372 Chains.push_back(Ch); 14373 } 14374 14375 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14376 Chains.size()); 14377 } 14378 14379 14380 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14381 // the FP state in cases where an emms may be missing. 14382 // A preferable solution to the general problem is to figure out the right 14383 // places to insert EMMS. This qualifies as a quick hack. 14384 14385 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14386 if (VT.getSizeInBits() != 64) 14387 return SDValue(); 14388 14389 const Function *F = DAG.getMachineFunction().getFunction(); 14390 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14391 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 14392 && Subtarget->hasXMMInt(); 14393 if ((VT.isVector() || 14394 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14395 isa<LoadSDNode>(St->getValue()) && 14396 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14397 St->getChain().hasOneUse() && !St->isVolatile()) { 14398 SDNode* LdVal = St->getValue().getNode(); 14399 LoadSDNode *Ld = 0; 14400 int TokenFactorIndex = -1; 14401 SmallVector<SDValue, 8> Ops; 14402 SDNode* ChainVal = St->getChain().getNode(); 14403 // Must be a store of a load. We currently handle two cases: the load 14404 // is a direct child, and it's under an intervening TokenFactor. It is 14405 // possible to dig deeper under nested TokenFactors. 14406 if (ChainVal == LdVal) 14407 Ld = cast<LoadSDNode>(St->getChain()); 14408 else if (St->getValue().hasOneUse() && 14409 ChainVal->getOpcode() == ISD::TokenFactor) { 14410 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 14411 if (ChainVal->getOperand(i).getNode() == LdVal) { 14412 TokenFactorIndex = i; 14413 Ld = cast<LoadSDNode>(St->getValue()); 14414 } else 14415 Ops.push_back(ChainVal->getOperand(i)); 14416 } 14417 } 14418 14419 if (!Ld || !ISD::isNormalLoad(Ld)) 14420 return SDValue(); 14421 14422 // If this is not the MMX case, i.e. we are just turning i64 load/store 14423 // into f64 load/store, avoid the transformation if there are multiple 14424 // uses of the loaded value. 14425 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14426 return SDValue(); 14427 14428 DebugLoc LdDL = Ld->getDebugLoc(); 14429 DebugLoc StDL = N->getDebugLoc(); 14430 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14431 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14432 // pair instead. 14433 if (Subtarget->is64Bit() || F64IsLegal) { 14434 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14435 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14436 Ld->getPointerInfo(), Ld->isVolatile(), 14437 Ld->isNonTemporal(), Ld->isInvariant(), 14438 Ld->getAlignment()); 14439 SDValue NewChain = NewLd.getValue(1); 14440 if (TokenFactorIndex != -1) { 14441 Ops.push_back(NewChain); 14442 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14443 Ops.size()); 14444 } 14445 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14446 St->getPointerInfo(), 14447 St->isVolatile(), St->isNonTemporal(), 14448 St->getAlignment()); 14449 } 14450 14451 // Otherwise, lower to two pairs of 32-bit loads / stores. 14452 SDValue LoAddr = Ld->getBasePtr(); 14453 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14454 DAG.getConstant(4, MVT::i32)); 14455 14456 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14457 Ld->getPointerInfo(), 14458 Ld->isVolatile(), Ld->isNonTemporal(), 14459 Ld->isInvariant(), Ld->getAlignment()); 14460 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14461 Ld->getPointerInfo().getWithOffset(4), 14462 Ld->isVolatile(), Ld->isNonTemporal(), 14463 Ld->isInvariant(), 14464 MinAlign(Ld->getAlignment(), 4)); 14465 14466 SDValue NewChain = LoLd.getValue(1); 14467 if (TokenFactorIndex != -1) { 14468 Ops.push_back(LoLd); 14469 Ops.push_back(HiLd); 14470 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14471 Ops.size()); 14472 } 14473 14474 LoAddr = St->getBasePtr(); 14475 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14476 DAG.getConstant(4, MVT::i32)); 14477 14478 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14479 St->getPointerInfo(), 14480 St->isVolatile(), St->isNonTemporal(), 14481 St->getAlignment()); 14482 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14483 St->getPointerInfo().getWithOffset(4), 14484 St->isVolatile(), 14485 St->isNonTemporal(), 14486 MinAlign(St->getAlignment(), 4)); 14487 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14488 } 14489 return SDValue(); 14490} 14491 14492/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14493/// and return the operands for the horizontal operation in LHS and RHS. A 14494/// horizontal operation performs the binary operation on successive elements 14495/// of its first operand, then on successive elements of its second operand, 14496/// returning the resulting values in a vector. For example, if 14497/// A = < float a0, float a1, float a2, float a3 > 14498/// and 14499/// B = < float b0, float b1, float b2, float b3 > 14500/// then the result of doing a horizontal operation on A and B is 14501/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14502/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14503/// A horizontal-op B, for some already available A and B, and if so then LHS is 14504/// set to A, RHS to B, and the routine returns 'true'. 14505/// Note that the binary operation should have the property that if one of the 14506/// operands is UNDEF then the result is UNDEF. 14507static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool isCommutative) { 14508 // Look for the following pattern: if 14509 // A = < float a0, float a1, float a2, float a3 > 14510 // B = < float b0, float b1, float b2, float b3 > 14511 // and 14512 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14513 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14514 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14515 // which is A horizontal-op B. 14516 14517 // At least one of the operands should be a vector shuffle. 14518 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14519 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14520 return false; 14521 14522 EVT VT = LHS.getValueType(); 14523 unsigned N = VT.getVectorNumElements(); 14524 14525 // View LHS in the form 14526 // LHS = VECTOR_SHUFFLE A, B, LMask 14527 // If LHS is not a shuffle then pretend it is the shuffle 14528 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14529 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14530 // type VT. 14531 SDValue A, B; 14532 SmallVector<int, 8> LMask(N); 14533 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14534 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14535 A = LHS.getOperand(0); 14536 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14537 B = LHS.getOperand(1); 14538 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask); 14539 } else { 14540 if (LHS.getOpcode() != ISD::UNDEF) 14541 A = LHS; 14542 for (unsigned i = 0; i != N; ++i) 14543 LMask[i] = i; 14544 } 14545 14546 // Likewise, view RHS in the form 14547 // RHS = VECTOR_SHUFFLE C, D, RMask 14548 SDValue C, D; 14549 SmallVector<int, 8> RMask(N); 14550 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14551 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14552 C = RHS.getOperand(0); 14553 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14554 D = RHS.getOperand(1); 14555 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask); 14556 } else { 14557 if (RHS.getOpcode() != ISD::UNDEF) 14558 C = RHS; 14559 for (unsigned i = 0; i != N; ++i) 14560 RMask[i] = i; 14561 } 14562 14563 // Check that the shuffles are both shuffling the same vectors. 14564 if (!(A == C && B == D) && !(A == D && B == C)) 14565 return false; 14566 14567 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14568 if (!A.getNode() && !B.getNode()) 14569 return false; 14570 14571 // If A and B occur in reverse order in RHS, then "swap" them (which means 14572 // rewriting the mask). 14573 if (A != C) 14574 for (unsigned i = 0; i != N; ++i) { 14575 unsigned Idx = RMask[i]; 14576 if (Idx < N) 14577 RMask[i] += N; 14578 else if (Idx < 2*N) 14579 RMask[i] -= N; 14580 } 14581 14582 // At this point LHS and RHS are equivalent to 14583 // LHS = VECTOR_SHUFFLE A, B, LMask 14584 // RHS = VECTOR_SHUFFLE A, B, RMask 14585 // Check that the masks correspond to performing a horizontal operation. 14586 for (unsigned i = 0; i != N; ++i) { 14587 unsigned LIdx = LMask[i], RIdx = RMask[i]; 14588 14589 // Ignore any UNDEF components. 14590 if (LIdx >= 2*N || RIdx >= 2*N || (!A.getNode() && (LIdx < N || RIdx < N)) 14591 || (!B.getNode() && (LIdx >= N || RIdx >= N))) 14592 continue; 14593 14594 // Check that successive elements are being operated on. If not, this is 14595 // not a horizontal operation. 14596 if (!(LIdx == 2*i && RIdx == 2*i + 1) && 14597 !(isCommutative && LIdx == 2*i + 1 && RIdx == 2*i)) 14598 return false; 14599 } 14600 14601 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14602 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14603 return true; 14604} 14605 14606/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14607static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14608 const X86Subtarget *Subtarget) { 14609 EVT VT = N->getValueType(0); 14610 SDValue LHS = N->getOperand(0); 14611 SDValue RHS = N->getOperand(1); 14612 14613 // Try to synthesize horizontal adds from adds of shuffles. 14614 if (Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64) && 14615 isHorizontalBinOp(LHS, RHS, true)) 14616 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14617 return SDValue(); 14618} 14619 14620/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14621static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14622 const X86Subtarget *Subtarget) { 14623 EVT VT = N->getValueType(0); 14624 SDValue LHS = N->getOperand(0); 14625 SDValue RHS = N->getOperand(1); 14626 14627 // Try to synthesize horizontal subs from subs of shuffles. 14628 if (Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64) && 14629 isHorizontalBinOp(LHS, RHS, false)) 14630 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14631 return SDValue(); 14632} 14633 14634/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14635/// X86ISD::FXOR nodes. 14636static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14637 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14638 // F[X]OR(0.0, x) -> x 14639 // F[X]OR(x, 0.0) -> x 14640 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14641 if (C->getValueAPF().isPosZero()) 14642 return N->getOperand(1); 14643 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14644 if (C->getValueAPF().isPosZero()) 14645 return N->getOperand(0); 14646 return SDValue(); 14647} 14648 14649/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14650static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14651 // FAND(0.0, x) -> 0.0 14652 // FAND(x, 0.0) -> 0.0 14653 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14654 if (C->getValueAPF().isPosZero()) 14655 return N->getOperand(0); 14656 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14657 if (C->getValueAPF().isPosZero()) 14658 return N->getOperand(1); 14659 return SDValue(); 14660} 14661 14662static SDValue PerformBTCombine(SDNode *N, 14663 SelectionDAG &DAG, 14664 TargetLowering::DAGCombinerInfo &DCI) { 14665 // BT ignores high bits in the bit index operand. 14666 SDValue Op1 = N->getOperand(1); 14667 if (Op1.hasOneUse()) { 14668 unsigned BitWidth = Op1.getValueSizeInBits(); 14669 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14670 APInt KnownZero, KnownOne; 14671 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14672 !DCI.isBeforeLegalizeOps()); 14673 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14674 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14675 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14676 DCI.CommitTargetLoweringOpt(TLO); 14677 } 14678 return SDValue(); 14679} 14680 14681static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14682 SDValue Op = N->getOperand(0); 14683 if (Op.getOpcode() == ISD::BITCAST) 14684 Op = Op.getOperand(0); 14685 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14686 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14687 VT.getVectorElementType().getSizeInBits() == 14688 OpVT.getVectorElementType().getSizeInBits()) { 14689 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14690 } 14691 return SDValue(); 14692} 14693 14694static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 14695 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14696 // (and (i32 x86isd::setcc_carry), 1) 14697 // This eliminates the zext. This transformation is necessary because 14698 // ISD::SETCC is always legalized to i8. 14699 DebugLoc dl = N->getDebugLoc(); 14700 SDValue N0 = N->getOperand(0); 14701 EVT VT = N->getValueType(0); 14702 if (N0.getOpcode() == ISD::AND && 14703 N0.hasOneUse() && 14704 N0.getOperand(0).hasOneUse()) { 14705 SDValue N00 = N0.getOperand(0); 14706 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14707 return SDValue(); 14708 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14709 if (!C || C->getZExtValue() != 1) 14710 return SDValue(); 14711 return DAG.getNode(ISD::AND, dl, VT, 14712 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14713 N00.getOperand(0), N00.getOperand(1)), 14714 DAG.getConstant(1, VT)); 14715 } 14716 14717 return SDValue(); 14718} 14719 14720// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14721static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14722 unsigned X86CC = N->getConstantOperandVal(0); 14723 SDValue EFLAG = N->getOperand(1); 14724 DebugLoc DL = N->getDebugLoc(); 14725 14726 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14727 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14728 // cases. 14729 if (X86CC == X86::COND_B) 14730 return DAG.getNode(ISD::AND, DL, MVT::i8, 14731 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14732 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14733 DAG.getConstant(1, MVT::i8)); 14734 14735 return SDValue(); 14736} 14737 14738static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14739 const X86TargetLowering *XTLI) { 14740 SDValue Op0 = N->getOperand(0); 14741 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14742 // a 32-bit target where SSE doesn't support i64->FP operations. 14743 if (Op0.getOpcode() == ISD::LOAD) { 14744 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14745 EVT VT = Ld->getValueType(0); 14746 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14747 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14748 !XTLI->getSubtarget()->is64Bit() && 14749 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14750 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14751 Ld->getChain(), Op0, DAG); 14752 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14753 return FILDChain; 14754 } 14755 } 14756 return SDValue(); 14757} 14758 14759// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14760static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14761 X86TargetLowering::DAGCombinerInfo &DCI) { 14762 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14763 // the result is either zero or one (depending on the input carry bit). 14764 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14765 if (X86::isZeroNode(N->getOperand(0)) && 14766 X86::isZeroNode(N->getOperand(1)) && 14767 // We don't have a good way to replace an EFLAGS use, so only do this when 14768 // dead right now. 14769 SDValue(N, 1).use_empty()) { 14770 DebugLoc DL = N->getDebugLoc(); 14771 EVT VT = N->getValueType(0); 14772 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14773 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14774 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14775 DAG.getConstant(X86::COND_B,MVT::i8), 14776 N->getOperand(2)), 14777 DAG.getConstant(1, VT)); 14778 return DCI.CombineTo(N, Res1, CarryOut); 14779 } 14780 14781 return SDValue(); 14782} 14783 14784// fold (add Y, (sete X, 0)) -> adc 0, Y 14785// (add Y, (setne X, 0)) -> sbb -1, Y 14786// (sub (sete X, 0), Y) -> sbb 0, Y 14787// (sub (setne X, 0), Y) -> adc -1, Y 14788static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14789 DebugLoc DL = N->getDebugLoc(); 14790 14791 // Look through ZExts. 14792 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14793 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14794 return SDValue(); 14795 14796 SDValue SetCC = Ext.getOperand(0); 14797 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14798 return SDValue(); 14799 14800 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14801 if (CC != X86::COND_E && CC != X86::COND_NE) 14802 return SDValue(); 14803 14804 SDValue Cmp = SetCC.getOperand(1); 14805 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14806 !X86::isZeroNode(Cmp.getOperand(1)) || 14807 !Cmp.getOperand(0).getValueType().isInteger()) 14808 return SDValue(); 14809 14810 SDValue CmpOp0 = Cmp.getOperand(0); 14811 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14812 DAG.getConstant(1, CmpOp0.getValueType())); 14813 14814 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14815 if (CC == X86::COND_NE) 14816 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14817 DL, OtherVal.getValueType(), OtherVal, 14818 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14819 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14820 DL, OtherVal.getValueType(), OtherVal, 14821 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14822} 14823 14824/// PerformADDCombine - Do target-specific dag combines on integer adds. 14825static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14826 const X86Subtarget *Subtarget) { 14827 EVT VT = N->getValueType(0); 14828 SDValue Op0 = N->getOperand(0); 14829 SDValue Op1 = N->getOperand(1); 14830 14831 // Try to synthesize horizontal adds from adds of shuffles. 14832 if ((Subtarget->hasSSSE3orAVX()) && (VT == MVT::v8i16 || VT == MVT::v4i32) && 14833 isHorizontalBinOp(Op0, Op1, true)) 14834 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14835 14836 return OptimizeConditionalInDecrement(N, DAG); 14837} 14838 14839static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14840 const X86Subtarget *Subtarget) { 14841 SDValue Op0 = N->getOperand(0); 14842 SDValue Op1 = N->getOperand(1); 14843 14844 // X86 can't encode an immediate LHS of a sub. See if we can push the 14845 // negation into a preceding instruction. 14846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14847 // If the RHS of the sub is a XOR with one use and a constant, invert the 14848 // immediate. Then add one to the LHS of the sub so we can turn 14849 // X-Y -> X+~Y+1, saving one register. 14850 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14851 isa<ConstantSDNode>(Op1.getOperand(1))) { 14852 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14853 EVT VT = Op0.getValueType(); 14854 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14855 Op1.getOperand(0), 14856 DAG.getConstant(~XorC, VT)); 14857 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14858 DAG.getConstant(C->getAPIntValue()+1, VT)); 14859 } 14860 } 14861 14862 // Try to synthesize horizontal adds from adds of shuffles. 14863 EVT VT = N->getValueType(0); 14864 if ((Subtarget->hasSSSE3orAVX()) && (VT == MVT::v8i16 || VT == MVT::v4i32) && 14865 isHorizontalBinOp(Op0, Op1, false)) 14866 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 14867 14868 return OptimizeConditionalInDecrement(N, DAG); 14869} 14870 14871SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14872 DAGCombinerInfo &DCI) const { 14873 SelectionDAG &DAG = DCI.DAG; 14874 switch (N->getOpcode()) { 14875 default: break; 14876 case ISD::EXTRACT_VECTOR_ELT: 14877 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14878 case ISD::VSELECT: 14879 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 14880 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14881 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 14882 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 14883 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14884 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14885 case ISD::SHL: 14886 case ISD::SRA: 14887 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 14888 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14889 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14890 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14891 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14892 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14893 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14894 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14895 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14896 case X86ISD::FXOR: 14897 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14898 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14899 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14900 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14901 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 14902 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14903 case X86ISD::SHUFPS: // Handle all target specific shuffles 14904 case X86ISD::SHUFPD: 14905 case X86ISD::PALIGN: 14906 case X86ISD::PUNPCKHBW: 14907 case X86ISD::PUNPCKHWD: 14908 case X86ISD::PUNPCKHDQ: 14909 case X86ISD::PUNPCKHQDQ: 14910 case X86ISD::VPUNPCKHBWY: 14911 case X86ISD::VPUNPCKHWDY: 14912 case X86ISD::VPUNPCKHDQY: 14913 case X86ISD::VPUNPCKHQDQY: 14914 case X86ISD::UNPCKHPS: 14915 case X86ISD::UNPCKHPD: 14916 case X86ISD::VUNPCKHPSY: 14917 case X86ISD::VUNPCKHPDY: 14918 case X86ISD::PUNPCKLBW: 14919 case X86ISD::PUNPCKLWD: 14920 case X86ISD::PUNPCKLDQ: 14921 case X86ISD::PUNPCKLQDQ: 14922 case X86ISD::VPUNPCKLBWY: 14923 case X86ISD::VPUNPCKLWDY: 14924 case X86ISD::VPUNPCKLDQY: 14925 case X86ISD::VPUNPCKLQDQY: 14926 case X86ISD::UNPCKLPS: 14927 case X86ISD::UNPCKLPD: 14928 case X86ISD::VUNPCKLPSY: 14929 case X86ISD::VUNPCKLPDY: 14930 case X86ISD::MOVHLPS: 14931 case X86ISD::MOVLHPS: 14932 case X86ISD::PSHUFD: 14933 case X86ISD::PSHUFHW: 14934 case X86ISD::PSHUFLW: 14935 case X86ISD::MOVSS: 14936 case X86ISD::MOVSD: 14937 case X86ISD::VPERMILPS: 14938 case X86ISD::VPERMILPSY: 14939 case X86ISD::VPERMILPD: 14940 case X86ISD::VPERMILPDY: 14941 case X86ISD::VPERM2F128: 14942 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14943 } 14944 14945 return SDValue(); 14946} 14947 14948/// isTypeDesirableForOp - Return true if the target has native support for 14949/// the specified value type and it is 'desirable' to use the type for the 14950/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14951/// instruction encodings are longer and some i16 instructions are slow. 14952bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14953 if (!isTypeLegal(VT)) 14954 return false; 14955 if (VT != MVT::i16) 14956 return true; 14957 14958 switch (Opc) { 14959 default: 14960 return true; 14961 case ISD::LOAD: 14962 case ISD::SIGN_EXTEND: 14963 case ISD::ZERO_EXTEND: 14964 case ISD::ANY_EXTEND: 14965 case ISD::SHL: 14966 case ISD::SRL: 14967 case ISD::SUB: 14968 case ISD::ADD: 14969 case ISD::MUL: 14970 case ISD::AND: 14971 case ISD::OR: 14972 case ISD::XOR: 14973 return false; 14974 } 14975} 14976 14977/// IsDesirableToPromoteOp - This method query the target whether it is 14978/// beneficial for dag combiner to promote the specified node. If true, it 14979/// should return the desired promotion type by reference. 14980bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14981 EVT VT = Op.getValueType(); 14982 if (VT != MVT::i16) 14983 return false; 14984 14985 bool Promote = false; 14986 bool Commute = false; 14987 switch (Op.getOpcode()) { 14988 default: break; 14989 case ISD::LOAD: { 14990 LoadSDNode *LD = cast<LoadSDNode>(Op); 14991 // If the non-extending load has a single use and it's not live out, then it 14992 // might be folded. 14993 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14994 Op.hasOneUse()*/) { 14995 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14996 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14997 // The only case where we'd want to promote LOAD (rather then it being 14998 // promoted as an operand is when it's only use is liveout. 14999 if (UI->getOpcode() != ISD::CopyToReg) 15000 return false; 15001 } 15002 } 15003 Promote = true; 15004 break; 15005 } 15006 case ISD::SIGN_EXTEND: 15007 case ISD::ZERO_EXTEND: 15008 case ISD::ANY_EXTEND: 15009 Promote = true; 15010 break; 15011 case ISD::SHL: 15012 case ISD::SRL: { 15013 SDValue N0 = Op.getOperand(0); 15014 // Look out for (store (shl (load), x)). 15015 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15016 return false; 15017 Promote = true; 15018 break; 15019 } 15020 case ISD::ADD: 15021 case ISD::MUL: 15022 case ISD::AND: 15023 case ISD::OR: 15024 case ISD::XOR: 15025 Commute = true; 15026 // fallthrough 15027 case ISD::SUB: { 15028 SDValue N0 = Op.getOperand(0); 15029 SDValue N1 = Op.getOperand(1); 15030 if (!Commute && MayFoldLoad(N1)) 15031 return false; 15032 // Avoid disabling potential load folding opportunities. 15033 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15034 return false; 15035 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15036 return false; 15037 Promote = true; 15038 } 15039 } 15040 15041 PVT = MVT::i32; 15042 return Promote; 15043} 15044 15045//===----------------------------------------------------------------------===// 15046// X86 Inline Assembly Support 15047//===----------------------------------------------------------------------===// 15048 15049bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15050 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15051 15052 std::string AsmStr = IA->getAsmString(); 15053 15054 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15055 SmallVector<StringRef, 4> AsmPieces; 15056 SplitString(AsmStr, AsmPieces, ";\n"); 15057 15058 switch (AsmPieces.size()) { 15059 default: return false; 15060 case 1: 15061 AsmStr = AsmPieces[0]; 15062 AsmPieces.clear(); 15063 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 15064 15065 // FIXME: this should verify that we are targeting a 486 or better. If not, 15066 // we will turn this bswap into something that will be lowered to logical ops 15067 // instead of emitting the bswap asm. For now, we don't support 486 or lower 15068 // so don't worry about this. 15069 // bswap $0 15070 if (AsmPieces.size() == 2 && 15071 (AsmPieces[0] == "bswap" || 15072 AsmPieces[0] == "bswapq" || 15073 AsmPieces[0] == "bswapl") && 15074 (AsmPieces[1] == "$0" || 15075 AsmPieces[1] == "${0:q}")) { 15076 // No need to check constraints, nothing other than the equivalent of 15077 // "=r,0" would be valid here. 15078 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15079 if (!Ty || Ty->getBitWidth() % 16 != 0) 15080 return false; 15081 return IntrinsicLowering::LowerToByteSwap(CI); 15082 } 15083 // rorw $$8, ${0:w} --> llvm.bswap.i16 15084 if (CI->getType()->isIntegerTy(16) && 15085 AsmPieces.size() == 3 && 15086 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 15087 AsmPieces[1] == "$$8," && 15088 AsmPieces[2] == "${0:w}" && 15089 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 15090 AsmPieces.clear(); 15091 const std::string &ConstraintsStr = IA->getConstraintString(); 15092 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15093 std::sort(AsmPieces.begin(), AsmPieces.end()); 15094 if (AsmPieces.size() == 4 && 15095 AsmPieces[0] == "~{cc}" && 15096 AsmPieces[1] == "~{dirflag}" && 15097 AsmPieces[2] == "~{flags}" && 15098 AsmPieces[3] == "~{fpsr}") { 15099 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15100 if (!Ty || Ty->getBitWidth() % 16 != 0) 15101 return false; 15102 return IntrinsicLowering::LowerToByteSwap(CI); 15103 } 15104 } 15105 break; 15106 case 3: 15107 if (CI->getType()->isIntegerTy(32) && 15108 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 15109 SmallVector<StringRef, 4> Words; 15110 SplitString(AsmPieces[0], Words, " \t,"); 15111 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 15112 Words[2] == "${0:w}") { 15113 Words.clear(); 15114 SplitString(AsmPieces[1], Words, " \t,"); 15115 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 15116 Words[2] == "$0") { 15117 Words.clear(); 15118 SplitString(AsmPieces[2], Words, " \t,"); 15119 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 15120 Words[2] == "${0:w}") { 15121 AsmPieces.clear(); 15122 const std::string &ConstraintsStr = IA->getConstraintString(); 15123 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15124 std::sort(AsmPieces.begin(), AsmPieces.end()); 15125 if (AsmPieces.size() == 4 && 15126 AsmPieces[0] == "~{cc}" && 15127 AsmPieces[1] == "~{dirflag}" && 15128 AsmPieces[2] == "~{flags}" && 15129 AsmPieces[3] == "~{fpsr}") { 15130 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15131 if (!Ty || Ty->getBitWidth() % 16 != 0) 15132 return false; 15133 return IntrinsicLowering::LowerToByteSwap(CI); 15134 } 15135 } 15136 } 15137 } 15138 } 15139 15140 if (CI->getType()->isIntegerTy(64)) { 15141 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15142 if (Constraints.size() >= 2 && 15143 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15144 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15145 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15146 SmallVector<StringRef, 4> Words; 15147 SplitString(AsmPieces[0], Words, " \t"); 15148 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 15149 Words.clear(); 15150 SplitString(AsmPieces[1], Words, " \t"); 15151 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 15152 Words.clear(); 15153 SplitString(AsmPieces[2], Words, " \t,"); 15154 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 15155 Words[2] == "%edx") { 15156 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15157 if (!Ty || Ty->getBitWidth() % 16 != 0) 15158 return false; 15159 return IntrinsicLowering::LowerToByteSwap(CI); 15160 } 15161 } 15162 } 15163 } 15164 } 15165 break; 15166 } 15167 return false; 15168} 15169 15170 15171 15172/// getConstraintType - Given a constraint letter, return the type of 15173/// constraint it is for this target. 15174X86TargetLowering::ConstraintType 15175X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15176 if (Constraint.size() == 1) { 15177 switch (Constraint[0]) { 15178 case 'R': 15179 case 'q': 15180 case 'Q': 15181 case 'f': 15182 case 't': 15183 case 'u': 15184 case 'y': 15185 case 'x': 15186 case 'Y': 15187 case 'l': 15188 return C_RegisterClass; 15189 case 'a': 15190 case 'b': 15191 case 'c': 15192 case 'd': 15193 case 'S': 15194 case 'D': 15195 case 'A': 15196 return C_Register; 15197 case 'I': 15198 case 'J': 15199 case 'K': 15200 case 'L': 15201 case 'M': 15202 case 'N': 15203 case 'G': 15204 case 'C': 15205 case 'e': 15206 case 'Z': 15207 return C_Other; 15208 default: 15209 break; 15210 } 15211 } 15212 return TargetLowering::getConstraintType(Constraint); 15213} 15214 15215/// Examine constraint type and operand type and determine a weight value. 15216/// This object must already have been set up with the operand type 15217/// and the current alternative constraint selected. 15218TargetLowering::ConstraintWeight 15219 X86TargetLowering::getSingleConstraintMatchWeight( 15220 AsmOperandInfo &info, const char *constraint) const { 15221 ConstraintWeight weight = CW_Invalid; 15222 Value *CallOperandVal = info.CallOperandVal; 15223 // If we don't have a value, we can't do a match, 15224 // but allow it at the lowest weight. 15225 if (CallOperandVal == NULL) 15226 return CW_Default; 15227 Type *type = CallOperandVal->getType(); 15228 // Look at the constraint type. 15229 switch (*constraint) { 15230 default: 15231 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15232 case 'R': 15233 case 'q': 15234 case 'Q': 15235 case 'a': 15236 case 'b': 15237 case 'c': 15238 case 'd': 15239 case 'S': 15240 case 'D': 15241 case 'A': 15242 if (CallOperandVal->getType()->isIntegerTy()) 15243 weight = CW_SpecificReg; 15244 break; 15245 case 'f': 15246 case 't': 15247 case 'u': 15248 if (type->isFloatingPointTy()) 15249 weight = CW_SpecificReg; 15250 break; 15251 case 'y': 15252 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15253 weight = CW_SpecificReg; 15254 break; 15255 case 'x': 15256 case 'Y': 15257 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) 15258 weight = CW_Register; 15259 break; 15260 case 'I': 15261 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15262 if (C->getZExtValue() <= 31) 15263 weight = CW_Constant; 15264 } 15265 break; 15266 case 'J': 15267 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15268 if (C->getZExtValue() <= 63) 15269 weight = CW_Constant; 15270 } 15271 break; 15272 case 'K': 15273 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15274 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15275 weight = CW_Constant; 15276 } 15277 break; 15278 case 'L': 15279 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15280 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15281 weight = CW_Constant; 15282 } 15283 break; 15284 case 'M': 15285 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15286 if (C->getZExtValue() <= 3) 15287 weight = CW_Constant; 15288 } 15289 break; 15290 case 'N': 15291 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15292 if (C->getZExtValue() <= 0xff) 15293 weight = CW_Constant; 15294 } 15295 break; 15296 case 'G': 15297 case 'C': 15298 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15299 weight = CW_Constant; 15300 } 15301 break; 15302 case 'e': 15303 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15304 if ((C->getSExtValue() >= -0x80000000LL) && 15305 (C->getSExtValue() <= 0x7fffffffLL)) 15306 weight = CW_Constant; 15307 } 15308 break; 15309 case 'Z': 15310 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15311 if (C->getZExtValue() <= 0xffffffff) 15312 weight = CW_Constant; 15313 } 15314 break; 15315 } 15316 return weight; 15317} 15318 15319/// LowerXConstraint - try to replace an X constraint, which matches anything, 15320/// with another that has more specific requirements based on the type of the 15321/// corresponding operand. 15322const char *X86TargetLowering:: 15323LowerXConstraint(EVT ConstraintVT) const { 15324 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15325 // 'f' like normal targets. 15326 if (ConstraintVT.isFloatingPoint()) { 15327 if (Subtarget->hasXMMInt()) 15328 return "Y"; 15329 if (Subtarget->hasXMM()) 15330 return "x"; 15331 } 15332 15333 return TargetLowering::LowerXConstraint(ConstraintVT); 15334} 15335 15336/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15337/// vector. If it is invalid, don't add anything to Ops. 15338void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15339 std::string &Constraint, 15340 std::vector<SDValue>&Ops, 15341 SelectionDAG &DAG) const { 15342 SDValue Result(0, 0); 15343 15344 // Only support length 1 constraints for now. 15345 if (Constraint.length() > 1) return; 15346 15347 char ConstraintLetter = Constraint[0]; 15348 switch (ConstraintLetter) { 15349 default: break; 15350 case 'I': 15351 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15352 if (C->getZExtValue() <= 31) { 15353 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15354 break; 15355 } 15356 } 15357 return; 15358 case 'J': 15359 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15360 if (C->getZExtValue() <= 63) { 15361 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15362 break; 15363 } 15364 } 15365 return; 15366 case 'K': 15367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15368 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15369 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15370 break; 15371 } 15372 } 15373 return; 15374 case 'N': 15375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15376 if (C->getZExtValue() <= 255) { 15377 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15378 break; 15379 } 15380 } 15381 return; 15382 case 'e': { 15383 // 32-bit signed value 15384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15385 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15386 C->getSExtValue())) { 15387 // Widen to 64 bits here to get it sign extended. 15388 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15389 break; 15390 } 15391 // FIXME gcc accepts some relocatable values here too, but only in certain 15392 // memory models; it's complicated. 15393 } 15394 return; 15395 } 15396 case 'Z': { 15397 // 32-bit unsigned value 15398 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15399 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15400 C->getZExtValue())) { 15401 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15402 break; 15403 } 15404 } 15405 // FIXME gcc accepts some relocatable values here too, but only in certain 15406 // memory models; it's complicated. 15407 return; 15408 } 15409 case 'i': { 15410 // Literal immediates are always ok. 15411 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15412 // Widen to 64 bits here to get it sign extended. 15413 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15414 break; 15415 } 15416 15417 // In any sort of PIC mode addresses need to be computed at runtime by 15418 // adding in a register or some sort of table lookup. These can't 15419 // be used as immediates. 15420 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15421 return; 15422 15423 // If we are in non-pic codegen mode, we allow the address of a global (with 15424 // an optional displacement) to be used with 'i'. 15425 GlobalAddressSDNode *GA = 0; 15426 int64_t Offset = 0; 15427 15428 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15429 while (1) { 15430 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15431 Offset += GA->getOffset(); 15432 break; 15433 } else if (Op.getOpcode() == ISD::ADD) { 15434 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15435 Offset += C->getZExtValue(); 15436 Op = Op.getOperand(0); 15437 continue; 15438 } 15439 } else if (Op.getOpcode() == ISD::SUB) { 15440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15441 Offset += -C->getZExtValue(); 15442 Op = Op.getOperand(0); 15443 continue; 15444 } 15445 } 15446 15447 // Otherwise, this isn't something we can handle, reject it. 15448 return; 15449 } 15450 15451 const GlobalValue *GV = GA->getGlobal(); 15452 // If we require an extra load to get this address, as in PIC mode, we 15453 // can't accept it. 15454 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15455 getTargetMachine()))) 15456 return; 15457 15458 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15459 GA->getValueType(0), Offset); 15460 break; 15461 } 15462 } 15463 15464 if (Result.getNode()) { 15465 Ops.push_back(Result); 15466 return; 15467 } 15468 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15469} 15470 15471std::pair<unsigned, const TargetRegisterClass*> 15472X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15473 EVT VT) const { 15474 // First, see if this is a constraint that directly corresponds to an LLVM 15475 // register class. 15476 if (Constraint.size() == 1) { 15477 // GCC Constraint Letters 15478 switch (Constraint[0]) { 15479 default: break; 15480 // TODO: Slight differences here in allocation order and leaving 15481 // RIP in the class. Do they matter any more here than they do 15482 // in the normal allocation? 15483 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15484 if (Subtarget->is64Bit()) { 15485 if (VT == MVT::i32 || VT == MVT::f32) 15486 return std::make_pair(0U, X86::GR32RegisterClass); 15487 else if (VT == MVT::i16) 15488 return std::make_pair(0U, X86::GR16RegisterClass); 15489 else if (VT == MVT::i8 || VT == MVT::i1) 15490 return std::make_pair(0U, X86::GR8RegisterClass); 15491 else if (VT == MVT::i64 || VT == MVT::f64) 15492 return std::make_pair(0U, X86::GR64RegisterClass); 15493 break; 15494 } 15495 // 32-bit fallthrough 15496 case 'Q': // Q_REGS 15497 if (VT == MVT::i32 || VT == MVT::f32) 15498 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15499 else if (VT == MVT::i16) 15500 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15501 else if (VT == MVT::i8 || VT == MVT::i1) 15502 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15503 else if (VT == MVT::i64) 15504 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15505 break; 15506 case 'r': // GENERAL_REGS 15507 case 'l': // INDEX_REGS 15508 if (VT == MVT::i8 || VT == MVT::i1) 15509 return std::make_pair(0U, X86::GR8RegisterClass); 15510 if (VT == MVT::i16) 15511 return std::make_pair(0U, X86::GR16RegisterClass); 15512 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15513 return std::make_pair(0U, X86::GR32RegisterClass); 15514 return std::make_pair(0U, X86::GR64RegisterClass); 15515 case 'R': // LEGACY_REGS 15516 if (VT == MVT::i8 || VT == MVT::i1) 15517 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15518 if (VT == MVT::i16) 15519 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15520 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15521 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15522 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15523 case 'f': // FP Stack registers. 15524 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15525 // value to the correct fpstack register class. 15526 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15527 return std::make_pair(0U, X86::RFP32RegisterClass); 15528 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15529 return std::make_pair(0U, X86::RFP64RegisterClass); 15530 return std::make_pair(0U, X86::RFP80RegisterClass); 15531 case 'y': // MMX_REGS if MMX allowed. 15532 if (!Subtarget->hasMMX()) break; 15533 return std::make_pair(0U, X86::VR64RegisterClass); 15534 case 'Y': // SSE_REGS if SSE2 allowed 15535 if (!Subtarget->hasXMMInt()) break; 15536 // FALL THROUGH. 15537 case 'x': // SSE_REGS if SSE1 allowed 15538 if (!Subtarget->hasXMM()) break; 15539 15540 switch (VT.getSimpleVT().SimpleTy) { 15541 default: break; 15542 // Scalar SSE types. 15543 case MVT::f32: 15544 case MVT::i32: 15545 return std::make_pair(0U, X86::FR32RegisterClass); 15546 case MVT::f64: 15547 case MVT::i64: 15548 return std::make_pair(0U, X86::FR64RegisterClass); 15549 // Vector types. 15550 case MVT::v16i8: 15551 case MVT::v8i16: 15552 case MVT::v4i32: 15553 case MVT::v2i64: 15554 case MVT::v4f32: 15555 case MVT::v2f64: 15556 return std::make_pair(0U, X86::VR128RegisterClass); 15557 } 15558 break; 15559 } 15560 } 15561 15562 // Use the default implementation in TargetLowering to convert the register 15563 // constraint into a member of a register class. 15564 std::pair<unsigned, const TargetRegisterClass*> Res; 15565 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15566 15567 // Not found as a standard register? 15568 if (Res.second == 0) { 15569 // Map st(0) -> st(7) -> ST0 15570 if (Constraint.size() == 7 && Constraint[0] == '{' && 15571 tolower(Constraint[1]) == 's' && 15572 tolower(Constraint[2]) == 't' && 15573 Constraint[3] == '(' && 15574 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15575 Constraint[5] == ')' && 15576 Constraint[6] == '}') { 15577 15578 Res.first = X86::ST0+Constraint[4]-'0'; 15579 Res.second = X86::RFP80RegisterClass; 15580 return Res; 15581 } 15582 15583 // GCC allows "st(0)" to be called just plain "st". 15584 if (StringRef("{st}").equals_lower(Constraint)) { 15585 Res.first = X86::ST0; 15586 Res.second = X86::RFP80RegisterClass; 15587 return Res; 15588 } 15589 15590 // flags -> EFLAGS 15591 if (StringRef("{flags}").equals_lower(Constraint)) { 15592 Res.first = X86::EFLAGS; 15593 Res.second = X86::CCRRegisterClass; 15594 return Res; 15595 } 15596 15597 // 'A' means EAX + EDX. 15598 if (Constraint == "A") { 15599 Res.first = X86::EAX; 15600 Res.second = X86::GR32_ADRegisterClass; 15601 return Res; 15602 } 15603 return Res; 15604 } 15605 15606 // Otherwise, check to see if this is a register class of the wrong value 15607 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15608 // turn into {ax},{dx}. 15609 if (Res.second->hasType(VT)) 15610 return Res; // Correct type already, nothing to do. 15611 15612 // All of the single-register GCC register classes map their values onto 15613 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15614 // really want an 8-bit or 32-bit register, map to the appropriate register 15615 // class and return the appropriate register. 15616 if (Res.second == X86::GR16RegisterClass) { 15617 if (VT == MVT::i8) { 15618 unsigned DestReg = 0; 15619 switch (Res.first) { 15620 default: break; 15621 case X86::AX: DestReg = X86::AL; break; 15622 case X86::DX: DestReg = X86::DL; break; 15623 case X86::CX: DestReg = X86::CL; break; 15624 case X86::BX: DestReg = X86::BL; break; 15625 } 15626 if (DestReg) { 15627 Res.first = DestReg; 15628 Res.second = X86::GR8RegisterClass; 15629 } 15630 } else if (VT == MVT::i32) { 15631 unsigned DestReg = 0; 15632 switch (Res.first) { 15633 default: break; 15634 case X86::AX: DestReg = X86::EAX; break; 15635 case X86::DX: DestReg = X86::EDX; break; 15636 case X86::CX: DestReg = X86::ECX; break; 15637 case X86::BX: DestReg = X86::EBX; break; 15638 case X86::SI: DestReg = X86::ESI; break; 15639 case X86::DI: DestReg = X86::EDI; break; 15640 case X86::BP: DestReg = X86::EBP; break; 15641 case X86::SP: DestReg = X86::ESP; break; 15642 } 15643 if (DestReg) { 15644 Res.first = DestReg; 15645 Res.second = X86::GR32RegisterClass; 15646 } 15647 } else if (VT == MVT::i64) { 15648 unsigned DestReg = 0; 15649 switch (Res.first) { 15650 default: break; 15651 case X86::AX: DestReg = X86::RAX; break; 15652 case X86::DX: DestReg = X86::RDX; break; 15653 case X86::CX: DestReg = X86::RCX; break; 15654 case X86::BX: DestReg = X86::RBX; break; 15655 case X86::SI: DestReg = X86::RSI; break; 15656 case X86::DI: DestReg = X86::RDI; break; 15657 case X86::BP: DestReg = X86::RBP; break; 15658 case X86::SP: DestReg = X86::RSP; break; 15659 } 15660 if (DestReg) { 15661 Res.first = DestReg; 15662 Res.second = X86::GR64RegisterClass; 15663 } 15664 } 15665 } else if (Res.second == X86::FR32RegisterClass || 15666 Res.second == X86::FR64RegisterClass || 15667 Res.second == X86::VR128RegisterClass) { 15668 // Handle references to XMM physical registers that got mapped into the 15669 // wrong class. This can happen with constraints like {xmm0} where the 15670 // target independent register mapper will just pick the first match it can 15671 // find, ignoring the required type. 15672 if (VT == MVT::f32) 15673 Res.second = X86::FR32RegisterClass; 15674 else if (VT == MVT::f64) 15675 Res.second = X86::FR64RegisterClass; 15676 else if (X86::VR128RegisterClass->hasType(VT)) 15677 Res.second = X86::VR128RegisterClass; 15678 } 15679 15680 return Res; 15681} 15682