X86ISelLowering.cpp revision f2db5b48d0a4f0800e83d8c3cd6dc5ad6a551bd6
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalAlias.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Function.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/LLVMContext.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/PseudoSourceValue.h" 37#include "llvm/MC/MCAsmInfo.h" 38#include "llvm/MC/MCContext.h" 39#include "llvm/MC/MCExpr.h" 40#include "llvm/MC/MCSymbol.h" 41#include "llvm/ADT/BitVector.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/Support/CommandLine.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/Dwarf.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/raw_ostream.h" 52using namespace llvm; 53using namespace dwarf; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57static cl::opt<bool> 58DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 59 60// Forward declarations. 61static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 62 SDValue V2); 63 64static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 65 66 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 67 68 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) { 69 if (is64Bit) return new X8664_MachoTargetObjectFile(); 70 return new TargetLoweringObjectFileMachO(); 71 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){ 72 if (is64Bit) return new X8664_ELFTargetObjectFile(TM); 73 return new X8632_ELFTargetObjectFile(TM); 74 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) { 75 return new TargetLoweringObjectFileCOFF(); 76 } 77 llvm_unreachable("unknown subtarget type"); 78} 79 80X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 81 : TargetLowering(TM, createTLOF(TM)) { 82 Subtarget = &TM.getSubtarget<X86Subtarget>(); 83 X86ScalarSSEf64 = Subtarget->hasSSE2(); 84 X86ScalarSSEf32 = Subtarget->hasSSE1(); 85 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 86 87 RegInfo = TM.getRegisterInfo(); 88 TD = getTargetData(); 89 90 // Set up the TargetLowering object. 91 92 // X86 is weird, it always uses i8 for shift amounts and setcc results. 93 setShiftAmountType(MVT::i8); 94 setBooleanContents(ZeroOrOneBooleanContent); 95 setSchedulingPreference(Sched::RegPressure); 96 setStackPointerRegisterToSaveRestore(X86StackPtr); 97 98 if (Subtarget->isTargetDarwin()) { 99 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 100 setUseUnderscoreSetJmp(false); 101 setUseUnderscoreLongJmp(false); 102 } else if (Subtarget->isTargetMingw()) { 103 // MS runtime is weird: it exports _setjmp, but longjmp! 104 setUseUnderscoreSetJmp(true); 105 setUseUnderscoreLongJmp(false); 106 } else { 107 setUseUnderscoreSetJmp(true); 108 setUseUnderscoreLongJmp(true); 109 } 110 111 // Set up the register classes. 112 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 113 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 114 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 115 if (Subtarget->is64Bit()) 116 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 117 118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 119 120 // We don't accept any truncstore of integer registers. 121 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 122 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 123 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 124 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 126 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 127 128 // SETOEQ and SETUNE require checking two conditions. 129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 135 136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 137 // operation. 138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 141 142 if (Subtarget->is64Bit()) { 143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 145 } else if (!UseSoftFloat) { 146 // We have an algorithm for SSE2->double, and we turn this into a 147 // 64-bit FILD followed by conditional FADD for other targets. 148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 149 // We have an algorithm for SSE2, and we turn this into a 64-bit 150 // FILD for other targets. 151 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 152 } 153 154 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 155 // this operation. 156 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 157 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 158 159 if (!UseSoftFloat) { 160 // SSE has no i16 to fp conversion, only i32 161 if (X86ScalarSSEf32) { 162 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 163 // f32 and f64 cases are Legal, f80 case is not 164 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 165 } else { 166 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 168 } 169 } else { 170 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 171 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 172 } 173 174 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 175 // are Legal, f80 is custom lowered. 176 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 177 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 178 179 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 180 // this operation. 181 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 182 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 183 184 if (X86ScalarSSEf32) { 185 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 186 // f32 and f64 cases are Legal, f80 case is not 187 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 188 } else { 189 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 191 } 192 193 // Handle FP_TO_UINT by promoting the destination to a larger signed 194 // conversion. 195 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 196 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 197 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 198 199 if (Subtarget->is64Bit()) { 200 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 202 } else if (!UseSoftFloat) { 203 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 204 // Expand FP_TO_UINT into a select. 205 // FIXME: We would like to use a Custom expander here eventually to do 206 // the optimal thing for SSE vs. the default expansion in the legalizer. 207 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 208 else 209 // With SSE3 we can use fisttpll to convert to a signed i64; without 210 // SSE, we're stuck with a fistpll. 211 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 212 } 213 214 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 215 if (!X86ScalarSSEf64) { 216 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 217 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 218 if (Subtarget->is64Bit()) { 219 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand); 220 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal. 221 if (Subtarget->hasMMX() && !DisableMMX) 222 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom); 223 else 224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand); 225 } 226 } 227 228 // Scalar integer divide and remainder are lowered to use operations that 229 // produce two results, to match the available instructions. This exposes 230 // the two-result form to trivial CSE, which is able to combine x/y and x%y 231 // into a single instruction. 232 // 233 // Scalar integer multiply-high is also lowered to use two-result 234 // operations, to match the available instructions. However, plain multiply 235 // (low) operations are left as Legal, as there are single-result 236 // instructions for this in x86. Using the two-result multiply instructions 237 // when both high and low results are needed must be arranged by dagcombine. 238 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 239 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 240 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 241 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 242 setOperationAction(ISD::SREM , MVT::i8 , Expand); 243 setOperationAction(ISD::UREM , MVT::i8 , Expand); 244 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 245 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 246 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 247 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 248 setOperationAction(ISD::SREM , MVT::i16 , Expand); 249 setOperationAction(ISD::UREM , MVT::i16 , Expand); 250 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 251 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 252 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 253 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 254 setOperationAction(ISD::SREM , MVT::i32 , Expand); 255 setOperationAction(ISD::UREM , MVT::i32 , Expand); 256 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 257 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 258 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 259 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 260 setOperationAction(ISD::SREM , MVT::i64 , Expand); 261 setOperationAction(ISD::UREM , MVT::i64 , Expand); 262 263 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 264 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 265 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 266 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 267 if (Subtarget->is64Bit()) 268 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 272 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 273 setOperationAction(ISD::FREM , MVT::f32 , Expand); 274 setOperationAction(ISD::FREM , MVT::f64 , Expand); 275 setOperationAction(ISD::FREM , MVT::f80 , Expand); 276 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 277 278 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 279 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 280 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 281 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 282 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 283 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 287 if (Subtarget->is64Bit()) { 288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 291 } 292 293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 295 296 // These should be promoted to a larger select which is supported. 297 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 298 // X86 wants to expand cmov itself. 299 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 300 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 301 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 302 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 303 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 304 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 305 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 306 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 307 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 308 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 309 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 310 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 311 if (Subtarget->is64Bit()) { 312 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 313 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 314 } 315 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 316 317 // Darwin ABI issue. 318 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 319 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 320 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 321 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 322 if (Subtarget->is64Bit()) 323 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 324 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 325 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 326 if (Subtarget->is64Bit()) { 327 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 328 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 329 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 330 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 331 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 332 } 333 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 334 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 335 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 336 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 337 if (Subtarget->is64Bit()) { 338 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 339 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 340 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 341 } 342 343 if (Subtarget->hasSSE1()) 344 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 345 346 // We may not have a libcall for MEMBARRIER so we should lower this. 347 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 348 349 // On X86 and X86-64, atomic operations are lowered to locked instructions. 350 // Locked instructions, in turn, have implicit fence semantics (all memory 351 // operations are flushed before issuing the locked instruction, and they 352 // are not buffered), so we can fold away the common pattern of 353 // fence-atomic-fence. 354 setShouldFoldAtomicFences(true); 355 356 // Expand certain atomics 357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 361 362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 366 367 if (!Subtarget->is64Bit()) { 368 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 370 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 371 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 372 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 373 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 374 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 375 } 376 377 // FIXME - use subtarget debug flags 378 if (!Subtarget->isTargetDarwin() && 379 !Subtarget->isTargetELF() && 380 !Subtarget->isTargetCygMing()) { 381 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 382 } 383 384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 385 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 387 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 388 if (Subtarget->is64Bit()) { 389 setExceptionPointerRegister(X86::RAX); 390 setExceptionSelectorRegister(X86::RDX); 391 } else { 392 setExceptionPointerRegister(X86::EAX); 393 setExceptionSelectorRegister(X86::EDX); 394 } 395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 397 398 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 399 400 setOperationAction(ISD::TRAP, MVT::Other, Legal); 401 402 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 403 setOperationAction(ISD::VASTART , MVT::Other, Custom); 404 setOperationAction(ISD::VAEND , MVT::Other, Expand); 405 if (Subtarget->is64Bit()) { 406 setOperationAction(ISD::VAARG , MVT::Other, Custom); 407 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 408 } else { 409 setOperationAction(ISD::VAARG , MVT::Other, Expand); 410 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 411 } 412 413 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 414 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 415 if (Subtarget->is64Bit()) 416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 417 if (Subtarget->isTargetCygMing()) 418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 419 else 420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 421 422 if (!UseSoftFloat && X86ScalarSSEf64) { 423 // f32 and f64 use SSE. 424 // Set up the FP register classes. 425 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 426 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 427 428 // Use ANDPD to simulate FABS. 429 setOperationAction(ISD::FABS , MVT::f64, Custom); 430 setOperationAction(ISD::FABS , MVT::f32, Custom); 431 432 // Use XORP to simulate FNEG. 433 setOperationAction(ISD::FNEG , MVT::f64, Custom); 434 setOperationAction(ISD::FNEG , MVT::f32, Custom); 435 436 // Use ANDPD and ORPD to simulate FCOPYSIGN. 437 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 438 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 439 440 // We don't support sin/cos/fmod 441 setOperationAction(ISD::FSIN , MVT::f64, Expand); 442 setOperationAction(ISD::FCOS , MVT::f64, Expand); 443 setOperationAction(ISD::FSIN , MVT::f32, Expand); 444 setOperationAction(ISD::FCOS , MVT::f32, Expand); 445 446 // Expand FP immediates into loads from the stack, except for the special 447 // cases we handle. 448 addLegalFPImmediate(APFloat(+0.0)); // xorpd 449 addLegalFPImmediate(APFloat(+0.0f)); // xorps 450 } else if (!UseSoftFloat && X86ScalarSSEf32) { 451 // Use SSE for f32, x87 for f64. 452 // Set up the FP register classes. 453 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 454 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 455 456 // Use ANDPS to simulate FABS. 457 setOperationAction(ISD::FABS , MVT::f32, Custom); 458 459 // Use XORP to simulate FNEG. 460 setOperationAction(ISD::FNEG , MVT::f32, Custom); 461 462 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 463 464 // Use ANDPS and ORPS to simulate FCOPYSIGN. 465 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 466 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 467 468 // We don't support sin/cos/fmod 469 setOperationAction(ISD::FSIN , MVT::f32, Expand); 470 setOperationAction(ISD::FCOS , MVT::f32, Expand); 471 472 // Special cases we handle for FP constants. 473 addLegalFPImmediate(APFloat(+0.0f)); // xorps 474 addLegalFPImmediate(APFloat(+0.0)); // FLD0 475 addLegalFPImmediate(APFloat(+1.0)); // FLD1 476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 478 479 if (!UnsafeFPMath) { 480 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 481 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 482 } 483 } else if (!UseSoftFloat) { 484 // f32 and f64 in x87. 485 // Set up the FP register classes. 486 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 487 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 488 489 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 490 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 491 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 492 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 493 494 if (!UnsafeFPMath) { 495 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 496 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 497 } 498 addLegalFPImmediate(APFloat(+0.0)); // FLD0 499 addLegalFPImmediate(APFloat(+1.0)); // FLD1 500 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 501 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 502 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 503 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 504 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 505 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 506 } 507 508 // Long double always uses X87. 509 if (!UseSoftFloat) { 510 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 511 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 512 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 513 { 514 bool ignored; 515 APFloat TmpFlt(+0.0); 516 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 517 &ignored); 518 addLegalFPImmediate(TmpFlt); // FLD0 519 TmpFlt.changeSign(); 520 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 521 APFloat TmpFlt2(+1.0); 522 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 523 &ignored); 524 addLegalFPImmediate(TmpFlt2); // FLD1 525 TmpFlt2.changeSign(); 526 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 527 } 528 529 if (!UnsafeFPMath) { 530 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 531 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 532 } 533 } 534 535 // Always use a library call for pow. 536 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 537 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 538 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 539 540 setOperationAction(ISD::FLOG, MVT::f80, Expand); 541 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 542 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 543 setOperationAction(ISD::FEXP, MVT::f80, Expand); 544 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 545 546 // First set operation action for all vector types to either promote 547 // (for widening) or expand (for scalarization). Then we will selectively 548 // turn on ones that can be effectively codegen'd. 549 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 550 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 551 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 553 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 566 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 567 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 600 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 604 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 605 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 606 setTruncStoreAction((MVT::SimpleValueType)VT, 607 (MVT::SimpleValueType)InnerVT, Expand); 608 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 609 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 610 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 611 } 612 613 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 614 // with -msoft-float, disable use of MMX as well. 615 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 616 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false); 617 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false); 618 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false); 619 620 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false); 621 622 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 623 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 624 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 625 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 626 627 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 628 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 629 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 630 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 631 632 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 633 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 634 635 setOperationAction(ISD::AND, MVT::v8i8, Promote); 636 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 637 setOperationAction(ISD::AND, MVT::v4i16, Promote); 638 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 639 setOperationAction(ISD::AND, MVT::v2i32, Promote); 640 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 641 setOperationAction(ISD::AND, MVT::v1i64, Legal); 642 643 setOperationAction(ISD::OR, MVT::v8i8, Promote); 644 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 645 setOperationAction(ISD::OR, MVT::v4i16, Promote); 646 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 647 setOperationAction(ISD::OR, MVT::v2i32, Promote); 648 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 649 setOperationAction(ISD::OR, MVT::v1i64, Legal); 650 651 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 652 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 653 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 654 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 655 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 656 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 657 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 658 659 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 660 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 661 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 662 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 663 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 664 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 665 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 666 667 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 668 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 669 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 670 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 671 672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 676 677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 680 681 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 682 683 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 684 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 685 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 686 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 687 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 688 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 689 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 690 691 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) { 692 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom); 693 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom); 694 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom); 695 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom); 696 } 697 } 698 699 if (!UseSoftFloat && Subtarget->hasSSE1()) { 700 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 701 702 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 703 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 704 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 705 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 706 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 707 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 708 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 709 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 712 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 713 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 714 } 715 716 if (!UseSoftFloat && Subtarget->hasSSE2()) { 717 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 718 719 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 720 // registers cannot be used even for integer operations. 721 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 722 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 723 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 724 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 725 726 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 727 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 728 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 729 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 730 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 731 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 732 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 733 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 734 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 735 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 736 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 737 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 738 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 739 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 740 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 741 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 742 743 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 744 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 745 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 746 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 747 748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 752 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 753 754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 759 760 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 761 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 762 EVT VT = (MVT::SimpleValueType)i; 763 // Do not attempt to custom lower non-power-of-2 vectors 764 if (!isPowerOf2_32(VT.getVectorNumElements())) 765 continue; 766 // Do not attempt to custom lower non-128-bit vectors 767 if (!VT.is128BitVector()) 768 continue; 769 setOperationAction(ISD::BUILD_VECTOR, 770 VT.getSimpleVT().SimpleTy, Custom); 771 setOperationAction(ISD::VECTOR_SHUFFLE, 772 VT.getSimpleVT().SimpleTy, Custom); 773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 774 VT.getSimpleVT().SimpleTy, Custom); 775 } 776 777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 778 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 781 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 782 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 783 784 if (Subtarget->is64Bit()) { 785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 787 } 788 789 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 790 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 791 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 792 EVT VT = SVT; 793 794 // Do not attempt to promote non-128-bit vectors 795 if (!VT.is128BitVector()) 796 continue; 797 798 setOperationAction(ISD::AND, SVT, Promote); 799 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 800 setOperationAction(ISD::OR, SVT, Promote); 801 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 802 setOperationAction(ISD::XOR, SVT, Promote); 803 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 804 setOperationAction(ISD::LOAD, SVT, Promote); 805 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 806 setOperationAction(ISD::SELECT, SVT, Promote); 807 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 808 } 809 810 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 811 812 // Custom lower v2i64 and v2f64 selects. 813 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 814 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 815 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 816 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 817 818 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 819 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 820 if (!DisableMMX && Subtarget->hasMMX()) { 821 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 822 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 823 } 824 } 825 826 if (Subtarget->hasSSE41()) { 827 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 828 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 829 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 830 setOperationAction(ISD::FRINT, MVT::f32, Legal); 831 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 832 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 833 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 834 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 835 setOperationAction(ISD::FRINT, MVT::f64, Legal); 836 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 837 838 // FIXME: Do we need to handle scalar-to-vector here? 839 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 840 841 // Can turn SHL into an integer multiply. 842 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 843 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 844 845 // i8 and i16 vectors are custom , because the source register and source 846 // source memory operand types are not the same width. f32 vectors are 847 // custom since the immediate controlling the insert encodes additional 848 // information. 849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 850 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 851 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 852 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 853 854 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 858 859 if (Subtarget->is64Bit()) { 860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 862 } 863 } 864 865 if (Subtarget->hasSSE42()) { 866 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 867 } 868 869 if (!UseSoftFloat && Subtarget->hasAVX()) { 870 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 871 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 872 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 873 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 874 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 875 876 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 877 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 878 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 879 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 880 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 881 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 882 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 883 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 884 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 885 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 886 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 887 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 888 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 889 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 890 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 891 892 // Operations to consider commented out -v16i16 v32i8 893 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 894 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 895 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 896 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 897 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 898 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 899 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 900 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 901 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 902 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 903 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 904 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 905 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 906 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 907 908 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 909 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 910 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 911 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 912 913 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 914 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 915 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 916 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 918 919 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 920 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 921 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 925 926#if 0 927 // Not sure we want to do this since there are no 256-bit integer 928 // operations in AVX 929 930 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 931 // This includes 256-bit vectors 932 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 933 EVT VT = (MVT::SimpleValueType)i; 934 935 // Do not attempt to custom lower non-power-of-2 vectors 936 if (!isPowerOf2_32(VT.getVectorNumElements())) 937 continue; 938 939 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 940 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 942 } 943 944 if (Subtarget->is64Bit()) { 945 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 947 } 948#endif 949 950#if 0 951 // Not sure we want to do this since there are no 256-bit integer 952 // operations in AVX 953 954 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 955 // Including 256-bit vectors 956 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 957 EVT VT = (MVT::SimpleValueType)i; 958 959 if (!VT.is256BitVector()) { 960 continue; 961 } 962 setOperationAction(ISD::AND, VT, Promote); 963 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 964 setOperationAction(ISD::OR, VT, Promote); 965 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 966 setOperationAction(ISD::XOR, VT, Promote); 967 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 968 setOperationAction(ISD::LOAD, VT, Promote); 969 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 970 setOperationAction(ISD::SELECT, VT, Promote); 971 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 972 } 973 974 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 975#endif 976 } 977 978 // We want to custom lower some of our intrinsics. 979 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 980 981 // Add/Sub/Mul with overflow operations are custom lowered. 982 setOperationAction(ISD::SADDO, MVT::i32, Custom); 983 setOperationAction(ISD::UADDO, MVT::i32, Custom); 984 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 985 setOperationAction(ISD::USUBO, MVT::i32, Custom); 986 setOperationAction(ISD::SMULO, MVT::i32, Custom); 987 988 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 989 // handle type legalization for these operations here. 990 // 991 // FIXME: We really should do custom legalization for addition and 992 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 993 // than generic legalization for 64-bit multiplication-with-overflow, though. 994 if (Subtarget->is64Bit()) { 995 setOperationAction(ISD::SADDO, MVT::i64, Custom); 996 setOperationAction(ISD::UADDO, MVT::i64, Custom); 997 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 998 setOperationAction(ISD::USUBO, MVT::i64, Custom); 999 setOperationAction(ISD::SMULO, MVT::i64, Custom); 1000 } 1001 1002 if (!Subtarget->is64Bit()) { 1003 // These libcalls are not available in 32-bit. 1004 setLibcallName(RTLIB::SHL_I128, 0); 1005 setLibcallName(RTLIB::SRL_I128, 0); 1006 setLibcallName(RTLIB::SRA_I128, 0); 1007 } 1008 1009 // We have target-specific dag combine patterns for the following nodes: 1010 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1011 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1012 setTargetDAGCombine(ISD::BUILD_VECTOR); 1013 setTargetDAGCombine(ISD::SELECT); 1014 setTargetDAGCombine(ISD::SHL); 1015 setTargetDAGCombine(ISD::SRA); 1016 setTargetDAGCombine(ISD::SRL); 1017 setTargetDAGCombine(ISD::OR); 1018 setTargetDAGCombine(ISD::STORE); 1019 setTargetDAGCombine(ISD::ZERO_EXTEND); 1020 if (Subtarget->is64Bit()) 1021 setTargetDAGCombine(ISD::MUL); 1022 1023 computeRegisterProperties(); 1024 1025 // FIXME: These should be based on subtarget info. Plus, the values should 1026 // be smaller when we are in optimizing for size mode. 1027 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1028 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1029 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 1030 setPrefLoopAlignment(16); 1031 benefitFromCodePlacementOpt = true; 1032} 1033 1034 1035MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1036 return MVT::i8; 1037} 1038 1039 1040/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1041/// the desired ByVal argument alignment. 1042static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1043 if (MaxAlign == 16) 1044 return; 1045 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1046 if (VTy->getBitWidth() == 128) 1047 MaxAlign = 16; 1048 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1049 unsigned EltAlign = 0; 1050 getMaxByValAlign(ATy->getElementType(), EltAlign); 1051 if (EltAlign > MaxAlign) 1052 MaxAlign = EltAlign; 1053 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1054 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1055 unsigned EltAlign = 0; 1056 getMaxByValAlign(STy->getElementType(i), EltAlign); 1057 if (EltAlign > MaxAlign) 1058 MaxAlign = EltAlign; 1059 if (MaxAlign == 16) 1060 break; 1061 } 1062 } 1063 return; 1064} 1065 1066/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1067/// function arguments in the caller parameter area. For X86, aggregates 1068/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1069/// are at 4-byte boundaries. 1070unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1071 if (Subtarget->is64Bit()) { 1072 // Max of 8 and alignment of type. 1073 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1074 if (TyAlign > 8) 1075 return TyAlign; 1076 return 8; 1077 } 1078 1079 unsigned Align = 4; 1080 if (Subtarget->hasSSE1()) 1081 getMaxByValAlign(Ty, Align); 1082 return Align; 1083} 1084 1085/// getOptimalMemOpType - Returns the target specific optimal type for load 1086/// and store operations as a result of memset, memcpy, and memmove 1087/// lowering. If DstAlign is zero that means it's safe to destination 1088/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1089/// means there isn't a need to check it against alignment requirement, 1090/// probably because the source does not need to be loaded. If 1091/// 'NonScalarIntSafe' is true, that means it's safe to return a 1092/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1093/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1094/// constant so it does not need to be loaded. 1095/// It returns EVT::Other if the type should be determined using generic 1096/// target-independent logic. 1097EVT 1098X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1099 unsigned DstAlign, unsigned SrcAlign, 1100 bool NonScalarIntSafe, 1101 bool MemcpyStrSrc, 1102 MachineFunction &MF) const { 1103 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1104 // linux. This is because the stack realignment code can't handle certain 1105 // cases like PR2962. This should be removed when PR2962 is fixed. 1106 const Function *F = MF.getFunction(); 1107 if (NonScalarIntSafe && 1108 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1109 if (Size >= 16 && 1110 (Subtarget->isUnalignedMemAccessFast() || 1111 ((DstAlign == 0 || DstAlign >= 16) && 1112 (SrcAlign == 0 || SrcAlign >= 16))) && 1113 Subtarget->getStackAlignment() >= 16) { 1114 if (Subtarget->hasSSE2()) 1115 return MVT::v4i32; 1116 if (Subtarget->hasSSE1()) 1117 return MVT::v4f32; 1118 } else if (!MemcpyStrSrc && Size >= 8 && 1119 !Subtarget->is64Bit() && 1120 Subtarget->getStackAlignment() >= 8 && 1121 Subtarget->hasSSE2()) { 1122 // Do not use f64 to lower memcpy if source is string constant. It's 1123 // better to use i32 to avoid the loads. 1124 return MVT::f64; 1125 } 1126 } 1127 if (Subtarget->is64Bit() && Size >= 8) 1128 return MVT::i64; 1129 return MVT::i32; 1130} 1131 1132/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1133/// current function. The returned value is a member of the 1134/// MachineJumpTableInfo::JTEntryKind enum. 1135unsigned X86TargetLowering::getJumpTableEncoding() const { 1136 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1137 // symbol. 1138 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1139 Subtarget->isPICStyleGOT()) 1140 return MachineJumpTableInfo::EK_Custom32; 1141 1142 // Otherwise, use the normal jump table encoding heuristics. 1143 return TargetLowering::getJumpTableEncoding(); 1144} 1145 1146/// getPICBaseSymbol - Return the X86-32 PIC base. 1147MCSymbol * 1148X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF, 1149 MCContext &Ctx) const { 1150 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo(); 1151 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+ 1152 Twine(MF->getFunctionNumber())+"$pb"); 1153} 1154 1155 1156const MCExpr * 1157X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1158 const MachineBasicBlock *MBB, 1159 unsigned uid,MCContext &Ctx) const{ 1160 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1161 Subtarget->isPICStyleGOT()); 1162 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1163 // entries. 1164 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1165 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1166} 1167 1168/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1169/// jumptable. 1170SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1171 SelectionDAG &DAG) const { 1172 if (!Subtarget->is64Bit()) 1173 // This doesn't have DebugLoc associated with it, but is not really the 1174 // same as a Register. 1175 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1176 return Table; 1177} 1178 1179/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1180/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1181/// MCExpr. 1182const MCExpr *X86TargetLowering:: 1183getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1184 MCContext &Ctx) const { 1185 // X86-64 uses RIP relative addressing based on the jump table label. 1186 if (Subtarget->isPICStyleRIPRel()) 1187 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1188 1189 // Otherwise, the reference is relative to the PIC base. 1190 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx); 1191} 1192 1193/// getFunctionAlignment - Return the Log2 alignment of this function. 1194unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1195 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1196} 1197 1198std::pair<const TargetRegisterClass*, uint8_t> 1199X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1200 const TargetRegisterClass *RRC = 0; 1201 uint8_t Cost = 1; 1202 switch (VT.getSimpleVT().SimpleTy) { 1203 default: 1204 return TargetLowering::findRepresentativeClass(VT); 1205 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1206 RRC = (Subtarget->is64Bit() 1207 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1208 break; 1209 case MVT::v8i8: case MVT::v4i16: 1210 case MVT::v2i32: case MVT::v1i64: 1211 RRC = X86::VR64RegisterClass; 1212 break; 1213 case MVT::f32: case MVT::f64: 1214 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1215 case MVT::v4f32: case MVT::v2f64: 1216 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1217 case MVT::v4f64: 1218 RRC = X86::VR128RegisterClass; 1219 break; 1220 } 1221 return std::make_pair(RRC, Cost); 1222} 1223 1224unsigned 1225X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC, 1226 MachineFunction &MF) const { 1227 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0; 1228 switch (RC->getID()) { 1229 default: 1230 return 0; 1231 case X86::GR32RegClassID: 1232 return 4 - FPDiff; 1233 case X86::GR64RegClassID: 1234 return 8 - FPDiff; 1235 case X86::VR128RegClassID: 1236 return Subtarget->is64Bit() ? 10 : 4; 1237 case X86::VR64RegClassID: 1238 return 4; 1239 } 1240} 1241 1242bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1243 unsigned &Offset) const { 1244 if (!Subtarget->isTargetLinux()) 1245 return false; 1246 1247 if (Subtarget->is64Bit()) { 1248 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1249 Offset = 0x28; 1250 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1251 AddressSpace = 256; 1252 else 1253 AddressSpace = 257; 1254 } else { 1255 // %gs:0x14 on i386 1256 Offset = 0x14; 1257 AddressSpace = 256; 1258 } 1259 return true; 1260} 1261 1262 1263//===----------------------------------------------------------------------===// 1264// Return Value Calling Convention Implementation 1265//===----------------------------------------------------------------------===// 1266 1267#include "X86GenCallingConv.inc" 1268 1269bool 1270X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1271 const SmallVectorImpl<ISD::OutputArg> &Outs, 1272 LLVMContext &Context) const { 1273 SmallVector<CCValAssign, 16> RVLocs; 1274 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1275 RVLocs, Context); 1276 return CCInfo.CheckReturn(Outs, RetCC_X86); 1277} 1278 1279SDValue 1280X86TargetLowering::LowerReturn(SDValue Chain, 1281 CallingConv::ID CallConv, bool isVarArg, 1282 const SmallVectorImpl<ISD::OutputArg> &Outs, 1283 const SmallVectorImpl<SDValue> &OutVals, 1284 DebugLoc dl, SelectionDAG &DAG) const { 1285 MachineFunction &MF = DAG.getMachineFunction(); 1286 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1287 1288 SmallVector<CCValAssign, 16> RVLocs; 1289 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1290 RVLocs, *DAG.getContext()); 1291 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1292 1293 // Add the regs to the liveout set for the function. 1294 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1295 for (unsigned i = 0; i != RVLocs.size(); ++i) 1296 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1297 MRI.addLiveOut(RVLocs[i].getLocReg()); 1298 1299 SDValue Flag; 1300 1301 SmallVector<SDValue, 6> RetOps; 1302 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1303 // Operand #1 = Bytes To Pop 1304 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1305 MVT::i16)); 1306 1307 // Copy the result values into the output registers. 1308 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1309 CCValAssign &VA = RVLocs[i]; 1310 assert(VA.isRegLoc() && "Can only return in registers!"); 1311 SDValue ValToCopy = OutVals[i]; 1312 EVT ValVT = ValToCopy.getValueType(); 1313 1314 // If this is x86-64, and we disabled SSE, we can't return FP values 1315 if ((ValVT == MVT::f32 || ValVT == MVT::f64) && 1316 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1317 report_fatal_error("SSE register return with SSE disabled"); 1318 } 1319 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1320 // llvm-gcc has never done it right and no one has noticed, so this 1321 // should be OK for now. 1322 if (ValVT == MVT::f64 && 1323 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1324 report_fatal_error("SSE2 register return with SSE2 disabled"); 1325 1326 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1327 // the RET instruction and handled by the FP Stackifier. 1328 if (VA.getLocReg() == X86::ST0 || 1329 VA.getLocReg() == X86::ST1) { 1330 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1331 // change the value to the FP stack register class. 1332 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1333 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1334 RetOps.push_back(ValToCopy); 1335 // Don't emit a copytoreg. 1336 continue; 1337 } 1338 1339 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1340 // which is returned in RAX / RDX. 1341 if (Subtarget->is64Bit()) { 1342 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1343 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1344 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1345 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1346 ValToCopy); 1347 1348 // If we don't have SSE2 available, convert to v4f32 so the generated 1349 // register is legal. 1350 if (!Subtarget->hasSSE2()) 1351 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy); 1352 } 1353 } 1354 } 1355 1356 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1357 Flag = Chain.getValue(1); 1358 } 1359 1360 // The x86-64 ABI for returning structs by value requires that we copy 1361 // the sret argument into %rax for the return. We saved the argument into 1362 // a virtual register in the entry block, so now we copy the value out 1363 // and into %rax. 1364 if (Subtarget->is64Bit() && 1365 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1366 MachineFunction &MF = DAG.getMachineFunction(); 1367 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1368 unsigned Reg = FuncInfo->getSRetReturnReg(); 1369 assert(Reg && 1370 "SRetReturnReg should have been set in LowerFormalArguments()."); 1371 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1372 1373 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1374 Flag = Chain.getValue(1); 1375 1376 // RAX now acts like a return value. 1377 MRI.addLiveOut(X86::RAX); 1378 } 1379 1380 RetOps[0] = Chain; // Update chain. 1381 1382 // Add the flag if we have it. 1383 if (Flag.getNode()) 1384 RetOps.push_back(Flag); 1385 1386 return DAG.getNode(X86ISD::RET_FLAG, dl, 1387 MVT::Other, &RetOps[0], RetOps.size()); 1388} 1389 1390/// LowerCallResult - Lower the result values of a call into the 1391/// appropriate copies out of appropriate physical registers. 1392/// 1393SDValue 1394X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1395 CallingConv::ID CallConv, bool isVarArg, 1396 const SmallVectorImpl<ISD::InputArg> &Ins, 1397 DebugLoc dl, SelectionDAG &DAG, 1398 SmallVectorImpl<SDValue> &InVals) const { 1399 1400 // Assign locations to each value returned by this call. 1401 SmallVector<CCValAssign, 16> RVLocs; 1402 bool Is64Bit = Subtarget->is64Bit(); 1403 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1404 RVLocs, *DAG.getContext()); 1405 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1406 1407 // Copy all of the result registers out of their specified physreg. 1408 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1409 CCValAssign &VA = RVLocs[i]; 1410 EVT CopyVT = VA.getValVT(); 1411 1412 // If this is x86-64, and we disabled SSE, we can't return FP values 1413 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1414 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1415 report_fatal_error("SSE register return with SSE disabled"); 1416 } 1417 1418 SDValue Val; 1419 1420 // If this is a call to a function that returns an fp value on the floating 1421 // point stack, we must guarantee the the value is popped from the stack, so 1422 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1423 // if the return value is not used. We use the FpGET_ST0 instructions 1424 // instead. 1425 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1426 // If we prefer to use the value in xmm registers, copy it out as f80 and 1427 // use a truncate to move it from fp stack reg to xmm reg. 1428 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1429 bool isST0 = VA.getLocReg() == X86::ST0; 1430 unsigned Opc = 0; 1431 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32; 1432 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64; 1433 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80; 1434 SDValue Ops[] = { Chain, InFlag }; 1435 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag, 1436 Ops, 2), 1); 1437 Val = Chain.getValue(0); 1438 1439 // Round the f80 to the right size, which also moves it to the appropriate 1440 // xmm register. 1441 if (CopyVT != VA.getValVT()) 1442 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1443 // This truncation won't change the value. 1444 DAG.getIntPtrConstant(1)); 1445 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1446 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1447 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1448 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1449 MVT::v2i64, InFlag).getValue(1); 1450 Val = Chain.getValue(0); 1451 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1452 Val, DAG.getConstant(0, MVT::i64)); 1453 } else { 1454 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1455 MVT::i64, InFlag).getValue(1); 1456 Val = Chain.getValue(0); 1457 } 1458 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1459 } else { 1460 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1461 CopyVT, InFlag).getValue(1); 1462 Val = Chain.getValue(0); 1463 } 1464 InFlag = Chain.getValue(2); 1465 InVals.push_back(Val); 1466 } 1467 1468 return Chain; 1469} 1470 1471 1472//===----------------------------------------------------------------------===// 1473// C & StdCall & Fast Calling Convention implementation 1474//===----------------------------------------------------------------------===// 1475// StdCall calling convention seems to be standard for many Windows' API 1476// routines and around. It differs from C calling convention just a little: 1477// callee should clean up the stack, not caller. Symbols should be also 1478// decorated in some fancy way :) It doesn't support any vector arguments. 1479// For info on fast calling convention see Fast Calling Convention (tail call) 1480// implementation LowerX86_32FastCCCallTo. 1481 1482/// CallIsStructReturn - Determines whether a call uses struct return 1483/// semantics. 1484static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1485 if (Outs.empty()) 1486 return false; 1487 1488 return Outs[0].Flags.isSRet(); 1489} 1490 1491/// ArgsAreStructReturn - Determines whether a function uses struct 1492/// return semantics. 1493static bool 1494ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1495 if (Ins.empty()) 1496 return false; 1497 1498 return Ins[0].Flags.isSRet(); 1499} 1500 1501/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1502/// given CallingConvention value. 1503CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1504 if (Subtarget->is64Bit()) { 1505 if (CC == CallingConv::GHC) 1506 return CC_X86_64_GHC; 1507 else if (Subtarget->isTargetWin64()) 1508 return CC_X86_Win64_C; 1509 else 1510 return CC_X86_64_C; 1511 } 1512 1513 if (CC == CallingConv::X86_FastCall) 1514 return CC_X86_32_FastCall; 1515 else if (CC == CallingConv::X86_ThisCall) 1516 return CC_X86_32_ThisCall; 1517 else if (CC == CallingConv::Fast) 1518 return CC_X86_32_FastCC; 1519 else if (CC == CallingConv::GHC) 1520 return CC_X86_32_GHC; 1521 else 1522 return CC_X86_32_C; 1523} 1524 1525/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1526/// by "Src" to address "Dst" with size and alignment information specified by 1527/// the specific parameter attribute. The copy will be passed as a byval 1528/// function parameter. 1529static SDValue 1530CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1531 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1532 DebugLoc dl) { 1533 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1534 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1535 /*isVolatile*/false, /*AlwaysInline=*/true, 1536 NULL, 0, NULL, 0); 1537} 1538 1539/// IsTailCallConvention - Return true if the calling convention is one that 1540/// supports tail call optimization. 1541static bool IsTailCallConvention(CallingConv::ID CC) { 1542 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1543} 1544 1545/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1546/// a tailcall target by changing its ABI. 1547static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1548 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1549} 1550 1551SDValue 1552X86TargetLowering::LowerMemArgument(SDValue Chain, 1553 CallingConv::ID CallConv, 1554 const SmallVectorImpl<ISD::InputArg> &Ins, 1555 DebugLoc dl, SelectionDAG &DAG, 1556 const CCValAssign &VA, 1557 MachineFrameInfo *MFI, 1558 unsigned i) const { 1559 // Create the nodes corresponding to a load from this parameter slot. 1560 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1561 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1562 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1563 EVT ValVT; 1564 1565 // If value is passed by pointer we have address passed instead of the value 1566 // itself. 1567 if (VA.getLocInfo() == CCValAssign::Indirect) 1568 ValVT = VA.getLocVT(); 1569 else 1570 ValVT = VA.getValVT(); 1571 1572 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1573 // changed with more analysis. 1574 // In case of tail call optimization mark all arguments mutable. Since they 1575 // could be overwritten by lowering of arguments in case of a tail call. 1576 if (Flags.isByVal()) { 1577 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1578 VA.getLocMemOffset(), isImmutable); 1579 return DAG.getFrameIndex(FI, getPointerTy()); 1580 } else { 1581 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1582 VA.getLocMemOffset(), isImmutable); 1583 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1584 return DAG.getLoad(ValVT, dl, Chain, FIN, 1585 PseudoSourceValue::getFixedStack(FI), 0, 1586 false, false, 0); 1587 } 1588} 1589 1590SDValue 1591X86TargetLowering::LowerFormalArguments(SDValue Chain, 1592 CallingConv::ID CallConv, 1593 bool isVarArg, 1594 const SmallVectorImpl<ISD::InputArg> &Ins, 1595 DebugLoc dl, 1596 SelectionDAG &DAG, 1597 SmallVectorImpl<SDValue> &InVals) 1598 const { 1599 MachineFunction &MF = DAG.getMachineFunction(); 1600 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1601 1602 const Function* Fn = MF.getFunction(); 1603 if (Fn->hasExternalLinkage() && 1604 Subtarget->isTargetCygMing() && 1605 Fn->getName() == "main") 1606 FuncInfo->setForceFramePointer(true); 1607 1608 MachineFrameInfo *MFI = MF.getFrameInfo(); 1609 bool Is64Bit = Subtarget->is64Bit(); 1610 bool IsWin64 = Subtarget->isTargetWin64(); 1611 1612 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1613 "Var args not supported with calling convention fastcc or ghc"); 1614 1615 // Assign locations to all of the incoming arguments. 1616 SmallVector<CCValAssign, 16> ArgLocs; 1617 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1618 ArgLocs, *DAG.getContext()); 1619 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1620 1621 unsigned LastVal = ~0U; 1622 SDValue ArgValue; 1623 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1624 CCValAssign &VA = ArgLocs[i]; 1625 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1626 // places. 1627 assert(VA.getValNo() != LastVal && 1628 "Don't support value assigned to multiple locs yet"); 1629 LastVal = VA.getValNo(); 1630 1631 if (VA.isRegLoc()) { 1632 EVT RegVT = VA.getLocVT(); 1633 TargetRegisterClass *RC = NULL; 1634 if (RegVT == MVT::i32) 1635 RC = X86::GR32RegisterClass; 1636 else if (Is64Bit && RegVT == MVT::i64) 1637 RC = X86::GR64RegisterClass; 1638 else if (RegVT == MVT::f32) 1639 RC = X86::FR32RegisterClass; 1640 else if (RegVT == MVT::f64) 1641 RC = X86::FR64RegisterClass; 1642 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1643 RC = X86::VR256RegisterClass; 1644 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1645 RC = X86::VR128RegisterClass; 1646 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1647 RC = X86::VR64RegisterClass; 1648 else 1649 llvm_unreachable("Unknown argument type!"); 1650 1651 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1652 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1653 1654 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1655 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1656 // right size. 1657 if (VA.getLocInfo() == CCValAssign::SExt) 1658 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1659 DAG.getValueType(VA.getValVT())); 1660 else if (VA.getLocInfo() == CCValAssign::ZExt) 1661 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1662 DAG.getValueType(VA.getValVT())); 1663 else if (VA.getLocInfo() == CCValAssign::BCvt) 1664 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1665 1666 if (VA.isExtInLoc()) { 1667 // Handle MMX values passed in XMM regs. 1668 if (RegVT.isVector()) { 1669 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1670 ArgValue, DAG.getConstant(0, MVT::i64)); 1671 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1672 } else 1673 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1674 } 1675 } else { 1676 assert(VA.isMemLoc()); 1677 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1678 } 1679 1680 // If value is passed via pointer - do a load. 1681 if (VA.getLocInfo() == CCValAssign::Indirect) 1682 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0, 1683 false, false, 0); 1684 1685 InVals.push_back(ArgValue); 1686 } 1687 1688 // The x86-64 ABI for returning structs by value requires that we copy 1689 // the sret argument into %rax for the return. Save the argument into 1690 // a virtual register so that we can access it from the return points. 1691 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1692 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1693 unsigned Reg = FuncInfo->getSRetReturnReg(); 1694 if (!Reg) { 1695 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1696 FuncInfo->setSRetReturnReg(Reg); 1697 } 1698 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1699 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1700 } 1701 1702 unsigned StackSize = CCInfo.getNextStackOffset(); 1703 // Align stack specially for tail calls. 1704 if (FuncIsMadeTailCallSafe(CallConv)) 1705 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1706 1707 // If the function takes variable number of arguments, make a frame index for 1708 // the start of the first vararg value... for expansion of llvm.va_start. 1709 if (isVarArg) { 1710 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1711 CallConv != CallingConv::X86_ThisCall)) { 1712 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1713 } 1714 if (Is64Bit) { 1715 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1716 1717 // FIXME: We should really autogenerate these arrays 1718 static const unsigned GPR64ArgRegsWin64[] = { 1719 X86::RCX, X86::RDX, X86::R8, X86::R9 1720 }; 1721 static const unsigned XMMArgRegsWin64[] = { 1722 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1723 }; 1724 static const unsigned GPR64ArgRegs64Bit[] = { 1725 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1726 }; 1727 static const unsigned XMMArgRegs64Bit[] = { 1728 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1729 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1730 }; 1731 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1732 1733 if (IsWin64) { 1734 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1735 GPR64ArgRegs = GPR64ArgRegsWin64; 1736 XMMArgRegs = XMMArgRegsWin64; 1737 } else { 1738 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1739 GPR64ArgRegs = GPR64ArgRegs64Bit; 1740 XMMArgRegs = XMMArgRegs64Bit; 1741 } 1742 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1743 TotalNumIntRegs); 1744 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1745 TotalNumXMMRegs); 1746 1747 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1748 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1749 "SSE register cannot be used when SSE is disabled!"); 1750 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1751 "SSE register cannot be used when SSE is disabled!"); 1752 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1753 // Kernel mode asks for SSE to be disabled, so don't push them 1754 // on the stack. 1755 TotalNumXMMRegs = 0; 1756 1757 // For X86-64, if there are vararg parameters that are passed via 1758 // registers, then we must store them to their spots on the stack so they 1759 // may be loaded by deferencing the result of va_next. 1760 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1761 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1762 FuncInfo->setRegSaveFrameIndex( 1763 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1764 false)); 1765 1766 // Store the integer parameter registers. 1767 SmallVector<SDValue, 8> MemOps; 1768 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1769 getPointerTy()); 1770 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1771 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1772 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1773 DAG.getIntPtrConstant(Offset)); 1774 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1775 X86::GR64RegisterClass); 1776 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1777 SDValue Store = 1778 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1779 PseudoSourceValue::getFixedStack( 1780 FuncInfo->getRegSaveFrameIndex()), 1781 Offset, false, false, 0); 1782 MemOps.push_back(Store); 1783 Offset += 8; 1784 } 1785 1786 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1787 // Now store the XMM (fp + vector) parameter registers. 1788 SmallVector<SDValue, 11> SaveXMMOps; 1789 SaveXMMOps.push_back(Chain); 1790 1791 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1792 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1793 SaveXMMOps.push_back(ALVal); 1794 1795 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1796 FuncInfo->getRegSaveFrameIndex())); 1797 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1798 FuncInfo->getVarArgsFPOffset())); 1799 1800 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1801 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1802 X86::VR128RegisterClass); 1803 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1804 SaveXMMOps.push_back(Val); 1805 } 1806 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1807 MVT::Other, 1808 &SaveXMMOps[0], SaveXMMOps.size())); 1809 } 1810 1811 if (!MemOps.empty()) 1812 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1813 &MemOps[0], MemOps.size()); 1814 } 1815 } 1816 1817 // Some CCs need callee pop. 1818 if (Subtarget->IsCalleePop(isVarArg, CallConv)) { 1819 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1820 } else { 1821 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1822 // If this is an sret function, the return should pop the hidden pointer. 1823 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1824 FuncInfo->setBytesToPopOnReturn(4); 1825 } 1826 1827 if (!Is64Bit) { 1828 // RegSaveFrameIndex is X86-64 only. 1829 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1830 if (CallConv == CallingConv::X86_FastCall || 1831 CallConv == CallingConv::X86_ThisCall) 1832 // fastcc functions can't have varargs. 1833 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1834 } 1835 1836 return Chain; 1837} 1838 1839SDValue 1840X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1841 SDValue StackPtr, SDValue Arg, 1842 DebugLoc dl, SelectionDAG &DAG, 1843 const CCValAssign &VA, 1844 ISD::ArgFlagsTy Flags) const { 1845 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1846 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1847 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1848 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1849 if (Flags.isByVal()) { 1850 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1851 } 1852 return DAG.getStore(Chain, dl, Arg, PtrOff, 1853 PseudoSourceValue::getStack(), LocMemOffset, 1854 false, false, 0); 1855} 1856 1857/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1858/// optimization is performed and it is required. 1859SDValue 1860X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1861 SDValue &OutRetAddr, SDValue Chain, 1862 bool IsTailCall, bool Is64Bit, 1863 int FPDiff, DebugLoc dl) const { 1864 // Adjust the Return address stack slot. 1865 EVT VT = getPointerTy(); 1866 OutRetAddr = getReturnAddressFrameIndex(DAG); 1867 1868 // Load the "old" Return address. 1869 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0); 1870 return SDValue(OutRetAddr.getNode(), 1); 1871} 1872 1873/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1874/// optimization is performed and it is required (FPDiff!=0). 1875static SDValue 1876EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1877 SDValue Chain, SDValue RetAddrFrIdx, 1878 bool Is64Bit, int FPDiff, DebugLoc dl) { 1879 // Store the return address to the appropriate stack slot. 1880 if (!FPDiff) return Chain; 1881 // Calculate the new stack slot for the return address. 1882 int SlotSize = Is64Bit ? 8 : 4; 1883 int NewReturnAddrFI = 1884 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 1885 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1886 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1887 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1888 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0, 1889 false, false, 0); 1890 return Chain; 1891} 1892 1893SDValue 1894X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1895 CallingConv::ID CallConv, bool isVarArg, 1896 bool &isTailCall, 1897 const SmallVectorImpl<ISD::OutputArg> &Outs, 1898 const SmallVectorImpl<SDValue> &OutVals, 1899 const SmallVectorImpl<ISD::InputArg> &Ins, 1900 DebugLoc dl, SelectionDAG &DAG, 1901 SmallVectorImpl<SDValue> &InVals) const { 1902 MachineFunction &MF = DAG.getMachineFunction(); 1903 bool Is64Bit = Subtarget->is64Bit(); 1904 bool IsStructRet = CallIsStructReturn(Outs); 1905 bool IsSibcall = false; 1906 1907 if (isTailCall) { 1908 // Check if it's really possible to do a tail call. 1909 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1910 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1911 Outs, OutVals, Ins, DAG); 1912 1913 // Sibcalls are automatically detected tailcalls which do not require 1914 // ABI changes. 1915 if (!GuaranteedTailCallOpt && isTailCall) 1916 IsSibcall = true; 1917 1918 if (isTailCall) 1919 ++NumTailCalls; 1920 } 1921 1922 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1923 "Var args not supported with calling convention fastcc or ghc"); 1924 1925 // Analyze operands of the call, assigning locations to each operand. 1926 SmallVector<CCValAssign, 16> ArgLocs; 1927 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1928 ArgLocs, *DAG.getContext()); 1929 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1930 1931 // Get a count of how many bytes are to be pushed on the stack. 1932 unsigned NumBytes = CCInfo.getNextStackOffset(); 1933 if (IsSibcall) 1934 // This is a sibcall. The memory operands are available in caller's 1935 // own caller's stack. 1936 NumBytes = 0; 1937 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 1938 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1939 1940 int FPDiff = 0; 1941 if (isTailCall && !IsSibcall) { 1942 // Lower arguments at fp - stackoffset + fpdiff. 1943 unsigned NumBytesCallerPushed = 1944 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1945 FPDiff = NumBytesCallerPushed - NumBytes; 1946 1947 // Set the delta of movement of the returnaddr stackslot. 1948 // But only set if delta is greater than previous delta. 1949 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1950 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1951 } 1952 1953 if (!IsSibcall) 1954 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1955 1956 SDValue RetAddrFrIdx; 1957 // Load return adress for tail calls. 1958 if (isTailCall && FPDiff) 1959 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1960 Is64Bit, FPDiff, dl); 1961 1962 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1963 SmallVector<SDValue, 8> MemOpChains; 1964 SDValue StackPtr; 1965 1966 // Walk the register/memloc assignments, inserting copies/loads. In the case 1967 // of tail call optimization arguments are handle later. 1968 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1969 CCValAssign &VA = ArgLocs[i]; 1970 EVT RegVT = VA.getLocVT(); 1971 SDValue Arg = OutVals[i]; 1972 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1973 bool isByVal = Flags.isByVal(); 1974 1975 // Promote the value if needed. 1976 switch (VA.getLocInfo()) { 1977 default: llvm_unreachable("Unknown loc info!"); 1978 case CCValAssign::Full: break; 1979 case CCValAssign::SExt: 1980 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1981 break; 1982 case CCValAssign::ZExt: 1983 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1984 break; 1985 case CCValAssign::AExt: 1986 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1987 // Special case: passing MMX values in XMM registers. 1988 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1989 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1990 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1991 } else 1992 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1993 break; 1994 case CCValAssign::BCvt: 1995 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1996 break; 1997 case CCValAssign::Indirect: { 1998 // Store the argument. 1999 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2000 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2001 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2002 PseudoSourceValue::getFixedStack(FI), 0, 2003 false, false, 0); 2004 Arg = SpillSlot; 2005 break; 2006 } 2007 } 2008 2009 if (VA.isRegLoc()) { 2010 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2011 if (isVarArg && Subtarget->isTargetWin64()) { 2012 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2013 // shadow reg if callee is a varargs function. 2014 unsigned ShadowReg = 0; 2015 switch (VA.getLocReg()) { 2016 case X86::XMM0: ShadowReg = X86::RCX; break; 2017 case X86::XMM1: ShadowReg = X86::RDX; break; 2018 case X86::XMM2: ShadowReg = X86::R8; break; 2019 case X86::XMM3: ShadowReg = X86::R9; break; 2020 } 2021 if (ShadowReg) 2022 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2023 } 2024 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2025 assert(VA.isMemLoc()); 2026 if (StackPtr.getNode() == 0) 2027 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2028 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2029 dl, DAG, VA, Flags)); 2030 } 2031 } 2032 2033 if (!MemOpChains.empty()) 2034 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2035 &MemOpChains[0], MemOpChains.size()); 2036 2037 // Build a sequence of copy-to-reg nodes chained together with token chain 2038 // and flag operands which copy the outgoing args into registers. 2039 SDValue InFlag; 2040 // Tail call byval lowering might overwrite argument registers so in case of 2041 // tail call optimization the copies to registers are lowered later. 2042 if (!isTailCall) 2043 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2044 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2045 RegsToPass[i].second, InFlag); 2046 InFlag = Chain.getValue(1); 2047 } 2048 2049 if (Subtarget->isPICStyleGOT()) { 2050 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2051 // GOT pointer. 2052 if (!isTailCall) { 2053 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2054 DAG.getNode(X86ISD::GlobalBaseReg, 2055 DebugLoc(), getPointerTy()), 2056 InFlag); 2057 InFlag = Chain.getValue(1); 2058 } else { 2059 // If we are tail calling and generating PIC/GOT style code load the 2060 // address of the callee into ECX. The value in ecx is used as target of 2061 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2062 // for tail calls on PIC/GOT architectures. Normally we would just put the 2063 // address of GOT into ebx and then call target@PLT. But for tail calls 2064 // ebx would be restored (since ebx is callee saved) before jumping to the 2065 // target@PLT. 2066 2067 // Note: The actual moving to ECX is done further down. 2068 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2069 if (G && !G->getGlobal()->hasHiddenVisibility() && 2070 !G->getGlobal()->hasProtectedVisibility()) 2071 Callee = LowerGlobalAddress(Callee, DAG); 2072 else if (isa<ExternalSymbolSDNode>(Callee)) 2073 Callee = LowerExternalSymbol(Callee, DAG); 2074 } 2075 } 2076 2077 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) { 2078 // From AMD64 ABI document: 2079 // For calls that may call functions that use varargs or stdargs 2080 // (prototype-less calls or calls to functions containing ellipsis (...) in 2081 // the declaration) %al is used as hidden argument to specify the number 2082 // of SSE registers used. The contents of %al do not need to match exactly 2083 // the number of registers, but must be an ubound on the number of SSE 2084 // registers used and is in the range 0 - 8 inclusive. 2085 2086 // Count the number of XMM registers allocated. 2087 static const unsigned XMMArgRegs[] = { 2088 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2089 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2090 }; 2091 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2092 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2093 && "SSE registers cannot be used when SSE is disabled"); 2094 2095 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2096 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2097 InFlag = Chain.getValue(1); 2098 } 2099 2100 2101 // For tail calls lower the arguments to the 'real' stack slot. 2102 if (isTailCall) { 2103 // Force all the incoming stack arguments to be loaded from the stack 2104 // before any new outgoing arguments are stored to the stack, because the 2105 // outgoing stack slots may alias the incoming argument stack slots, and 2106 // the alias isn't otherwise explicit. This is slightly more conservative 2107 // than necessary, because it means that each store effectively depends 2108 // on every argument instead of just those arguments it would clobber. 2109 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2110 2111 SmallVector<SDValue, 8> MemOpChains2; 2112 SDValue FIN; 2113 int FI = 0; 2114 // Do not flag preceeding copytoreg stuff together with the following stuff. 2115 InFlag = SDValue(); 2116 if (GuaranteedTailCallOpt) { 2117 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2118 CCValAssign &VA = ArgLocs[i]; 2119 if (VA.isRegLoc()) 2120 continue; 2121 assert(VA.isMemLoc()); 2122 SDValue Arg = OutVals[i]; 2123 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2124 // Create frame index. 2125 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2126 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2127 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2128 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2129 2130 if (Flags.isByVal()) { 2131 // Copy relative to framepointer. 2132 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2133 if (StackPtr.getNode() == 0) 2134 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2135 getPointerTy()); 2136 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2137 2138 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2139 ArgChain, 2140 Flags, DAG, dl)); 2141 } else { 2142 // Store relative to framepointer. 2143 MemOpChains2.push_back( 2144 DAG.getStore(ArgChain, dl, Arg, FIN, 2145 PseudoSourceValue::getFixedStack(FI), 0, 2146 false, false, 0)); 2147 } 2148 } 2149 } 2150 2151 if (!MemOpChains2.empty()) 2152 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2153 &MemOpChains2[0], MemOpChains2.size()); 2154 2155 // Copy arguments to their registers. 2156 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2157 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2158 RegsToPass[i].second, InFlag); 2159 InFlag = Chain.getValue(1); 2160 } 2161 InFlag =SDValue(); 2162 2163 // Store the return address to the appropriate stack slot. 2164 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2165 FPDiff, dl); 2166 } 2167 2168 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2169 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2170 // In the 64-bit large code model, we have to make all calls 2171 // through a register, since the call instruction's 32-bit 2172 // pc-relative offset may not be large enough to hold the whole 2173 // address. 2174 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2175 // If the callee is a GlobalAddress node (quite common, every direct call 2176 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2177 // it. 2178 2179 // We should use extra load for direct calls to dllimported functions in 2180 // non-JIT mode. 2181 const GlobalValue *GV = G->getGlobal(); 2182 if (!GV->hasDLLImportLinkage()) { 2183 unsigned char OpFlags = 0; 2184 2185 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2186 // external symbols most go through the PLT in PIC mode. If the symbol 2187 // has hidden or protected visibility, or if it is static or local, then 2188 // we don't need to use the PLT - we can directly call it. 2189 if (Subtarget->isTargetELF() && 2190 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2191 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2192 OpFlags = X86II::MO_PLT; 2193 } else if (Subtarget->isPICStyleStubAny() && 2194 (GV->isDeclaration() || GV->isWeakForLinker()) && 2195 Subtarget->getDarwinVers() < 9) { 2196 // PC-relative references to external symbols should go through $stub, 2197 // unless we're building with the leopard linker or later, which 2198 // automatically synthesizes these stubs. 2199 OpFlags = X86II::MO_DARWIN_STUB; 2200 } 2201 2202 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2203 G->getOffset(), OpFlags); 2204 } 2205 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2206 unsigned char OpFlags = 0; 2207 2208 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 2209 // symbols should go through the PLT. 2210 if (Subtarget->isTargetELF() && 2211 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2212 OpFlags = X86II::MO_PLT; 2213 } else if (Subtarget->isPICStyleStubAny() && 2214 Subtarget->getDarwinVers() < 9) { 2215 // PC-relative references to external symbols should go through $stub, 2216 // unless we're building with the leopard linker or later, which 2217 // automatically synthesizes these stubs. 2218 OpFlags = X86II::MO_DARWIN_STUB; 2219 } 2220 2221 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2222 OpFlags); 2223 } 2224 2225 // Returns a chain & a flag for retval copy to use. 2226 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2227 SmallVector<SDValue, 8> Ops; 2228 2229 if (!IsSibcall && isTailCall) { 2230 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2231 DAG.getIntPtrConstant(0, true), InFlag); 2232 InFlag = Chain.getValue(1); 2233 } 2234 2235 Ops.push_back(Chain); 2236 Ops.push_back(Callee); 2237 2238 if (isTailCall) 2239 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2240 2241 // Add argument registers to the end of the list so that they are known live 2242 // into the call. 2243 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2244 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2245 RegsToPass[i].second.getValueType())); 2246 2247 // Add an implicit use GOT pointer in EBX. 2248 if (!isTailCall && Subtarget->isPICStyleGOT()) 2249 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2250 2251 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2252 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) 2253 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2254 2255 if (InFlag.getNode()) 2256 Ops.push_back(InFlag); 2257 2258 if (isTailCall) { 2259 // We used to do: 2260 //// If this is the first return lowered for this function, add the regs 2261 //// to the liveout set for the function. 2262 // This isn't right, although it's probably harmless on x86; liveouts 2263 // should be computed from returns not tail calls. Consider a void 2264 // function making a tail call to a function returning int. 2265 return DAG.getNode(X86ISD::TC_RETURN, dl, 2266 NodeTys, &Ops[0], Ops.size()); 2267 } 2268 2269 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2270 InFlag = Chain.getValue(1); 2271 2272 // Create the CALLSEQ_END node. 2273 unsigned NumBytesForCalleeToPush; 2274 if (Subtarget->IsCalleePop(isVarArg, CallConv)) 2275 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2276 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2277 // If this is a call to a struct-return function, the callee 2278 // pops the hidden struct pointer, so we have to push it back. 2279 // This is common for Darwin/X86, Linux & Mingw32 targets. 2280 NumBytesForCalleeToPush = 4; 2281 else 2282 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2283 2284 // Returns a flag for retval copy to use. 2285 if (!IsSibcall) { 2286 Chain = DAG.getCALLSEQ_END(Chain, 2287 DAG.getIntPtrConstant(NumBytes, true), 2288 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2289 true), 2290 InFlag); 2291 InFlag = Chain.getValue(1); 2292 } 2293 2294 // Handle result values, copying them out of physregs into vregs that we 2295 // return. 2296 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2297 Ins, dl, DAG, InVals); 2298} 2299 2300 2301//===----------------------------------------------------------------------===// 2302// Fast Calling Convention (tail call) implementation 2303//===----------------------------------------------------------------------===// 2304 2305// Like std call, callee cleans arguments, convention except that ECX is 2306// reserved for storing the tail called function address. Only 2 registers are 2307// free for argument passing (inreg). Tail call optimization is performed 2308// provided: 2309// * tailcallopt is enabled 2310// * caller/callee are fastcc 2311// On X86_64 architecture with GOT-style position independent code only local 2312// (within module) calls are supported at the moment. 2313// To keep the stack aligned according to platform abi the function 2314// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2315// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2316// If a tail called function callee has more arguments than the caller the 2317// caller needs to make sure that there is room to move the RETADDR to. This is 2318// achieved by reserving an area the size of the argument delta right after the 2319// original REtADDR, but before the saved framepointer or the spilled registers 2320// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2321// stack layout: 2322// arg1 2323// arg2 2324// RETADDR 2325// [ new RETADDR 2326// move area ] 2327// (possible EBP) 2328// ESI 2329// EDI 2330// local1 .. 2331 2332/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2333/// for a 16 byte align requirement. 2334unsigned 2335X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2336 SelectionDAG& DAG) const { 2337 MachineFunction &MF = DAG.getMachineFunction(); 2338 const TargetMachine &TM = MF.getTarget(); 2339 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2340 unsigned StackAlignment = TFI.getStackAlignment(); 2341 uint64_t AlignMask = StackAlignment - 1; 2342 int64_t Offset = StackSize; 2343 uint64_t SlotSize = TD->getPointerSize(); 2344 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2345 // Number smaller than 12 so just add the difference. 2346 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2347 } else { 2348 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2349 Offset = ((~AlignMask) & Offset) + StackAlignment + 2350 (StackAlignment-SlotSize); 2351 } 2352 return Offset; 2353} 2354 2355/// MatchingStackOffset - Return true if the given stack call argument is 2356/// already available in the same position (relatively) of the caller's 2357/// incoming argument stack. 2358static 2359bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2360 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2361 const X86InstrInfo *TII) { 2362 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2363 int FI = INT_MAX; 2364 if (Arg.getOpcode() == ISD::CopyFromReg) { 2365 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2366 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2367 return false; 2368 MachineInstr *Def = MRI->getVRegDef(VR); 2369 if (!Def) 2370 return false; 2371 if (!Flags.isByVal()) { 2372 if (!TII->isLoadFromStackSlot(Def, FI)) 2373 return false; 2374 } else { 2375 unsigned Opcode = Def->getOpcode(); 2376 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2377 Def->getOperand(1).isFI()) { 2378 FI = Def->getOperand(1).getIndex(); 2379 Bytes = Flags.getByValSize(); 2380 } else 2381 return false; 2382 } 2383 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2384 if (Flags.isByVal()) 2385 // ByVal argument is passed in as a pointer but it's now being 2386 // dereferenced. e.g. 2387 // define @foo(%struct.X* %A) { 2388 // tail call @bar(%struct.X* byval %A) 2389 // } 2390 return false; 2391 SDValue Ptr = Ld->getBasePtr(); 2392 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2393 if (!FINode) 2394 return false; 2395 FI = FINode->getIndex(); 2396 } else 2397 return false; 2398 2399 assert(FI != INT_MAX); 2400 if (!MFI->isFixedObjectIndex(FI)) 2401 return false; 2402 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2403} 2404 2405/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2406/// for tail call optimization. Targets which want to do tail call 2407/// optimization should implement this function. 2408bool 2409X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2410 CallingConv::ID CalleeCC, 2411 bool isVarArg, 2412 bool isCalleeStructRet, 2413 bool isCallerStructRet, 2414 const SmallVectorImpl<ISD::OutputArg> &Outs, 2415 const SmallVectorImpl<SDValue> &OutVals, 2416 const SmallVectorImpl<ISD::InputArg> &Ins, 2417 SelectionDAG& DAG) const { 2418 if (!IsTailCallConvention(CalleeCC) && 2419 CalleeCC != CallingConv::C) 2420 return false; 2421 2422 // If -tailcallopt is specified, make fastcc functions tail-callable. 2423 const MachineFunction &MF = DAG.getMachineFunction(); 2424 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2425 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2426 bool CCMatch = CallerCC == CalleeCC; 2427 2428 if (GuaranteedTailCallOpt) { 2429 if (IsTailCallConvention(CalleeCC) && CCMatch) 2430 return true; 2431 return false; 2432 } 2433 2434 // Look for obvious safe cases to perform tail call optimization that do not 2435 // require ABI changes. This is what gcc calls sibcall. 2436 2437 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2438 // emit a special epilogue. 2439 if (RegInfo->needsStackRealignment(MF)) 2440 return false; 2441 2442 // Do not sibcall optimize vararg calls unless the call site is not passing 2443 // any arguments. 2444 if (isVarArg && !Outs.empty()) 2445 return false; 2446 2447 // Also avoid sibcall optimization if either caller or callee uses struct 2448 // return semantics. 2449 if (isCalleeStructRet || isCallerStructRet) 2450 return false; 2451 2452 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2453 // Therefore if it's not used by the call it is not safe to optimize this into 2454 // a sibcall. 2455 bool Unused = false; 2456 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2457 if (!Ins[i].Used) { 2458 Unused = true; 2459 break; 2460 } 2461 } 2462 if (Unused) { 2463 SmallVector<CCValAssign, 16> RVLocs; 2464 CCState CCInfo(CalleeCC, false, getTargetMachine(), 2465 RVLocs, *DAG.getContext()); 2466 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2467 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2468 CCValAssign &VA = RVLocs[i]; 2469 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2470 return false; 2471 } 2472 } 2473 2474 // If the calling conventions do not match, then we'd better make sure the 2475 // results are returned in the same way as what the caller expects. 2476 if (!CCMatch) { 2477 SmallVector<CCValAssign, 16> RVLocs1; 2478 CCState CCInfo1(CalleeCC, false, getTargetMachine(), 2479 RVLocs1, *DAG.getContext()); 2480 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2481 2482 SmallVector<CCValAssign, 16> RVLocs2; 2483 CCState CCInfo2(CallerCC, false, getTargetMachine(), 2484 RVLocs2, *DAG.getContext()); 2485 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2486 2487 if (RVLocs1.size() != RVLocs2.size()) 2488 return false; 2489 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2490 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2491 return false; 2492 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2493 return false; 2494 if (RVLocs1[i].isRegLoc()) { 2495 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2496 return false; 2497 } else { 2498 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2499 return false; 2500 } 2501 } 2502 } 2503 2504 // If the callee takes no arguments then go on to check the results of the 2505 // call. 2506 if (!Outs.empty()) { 2507 // Check if stack adjustment is needed. For now, do not do this if any 2508 // argument is passed on the stack. 2509 SmallVector<CCValAssign, 16> ArgLocs; 2510 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2511 ArgLocs, *DAG.getContext()); 2512 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 2513 if (CCInfo.getNextStackOffset()) { 2514 MachineFunction &MF = DAG.getMachineFunction(); 2515 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2516 return false; 2517 if (Subtarget->isTargetWin64()) 2518 // Win64 ABI has additional complications. 2519 return false; 2520 2521 // Check if the arguments are already laid out in the right way as 2522 // the caller's fixed stack objects. 2523 MachineFrameInfo *MFI = MF.getFrameInfo(); 2524 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2525 const X86InstrInfo *TII = 2526 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2527 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2528 CCValAssign &VA = ArgLocs[i]; 2529 SDValue Arg = OutVals[i]; 2530 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2531 if (VA.getLocInfo() == CCValAssign::Indirect) 2532 return false; 2533 if (!VA.isRegLoc()) { 2534 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2535 MFI, MRI, TII)) 2536 return false; 2537 } 2538 } 2539 } 2540 2541 // If the tailcall address may be in a register, then make sure it's 2542 // possible to register allocate for it. In 32-bit, the call address can 2543 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2544 // callee-saved registers are restored. These happen to be the same 2545 // registers used to pass 'inreg' arguments so watch out for those. 2546 if (!Subtarget->is64Bit() && 2547 !isa<GlobalAddressSDNode>(Callee) && 2548 !isa<ExternalSymbolSDNode>(Callee)) { 2549 unsigned NumInRegs = 0; 2550 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2551 CCValAssign &VA = ArgLocs[i]; 2552 if (!VA.isRegLoc()) 2553 continue; 2554 unsigned Reg = VA.getLocReg(); 2555 switch (Reg) { 2556 default: break; 2557 case X86::EAX: case X86::EDX: case X86::ECX: 2558 if (++NumInRegs == 3) 2559 return false; 2560 break; 2561 } 2562 } 2563 } 2564 } 2565 2566 return true; 2567} 2568 2569FastISel * 2570X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2571 return X86::createFastISel(funcInfo); 2572} 2573 2574 2575//===----------------------------------------------------------------------===// 2576// Other Lowering Hooks 2577//===----------------------------------------------------------------------===// 2578 2579static bool isTargetShuffle(unsigned Opcode) { 2580 switch(Opcode) { 2581 default: return false; 2582 case X86ISD::PSHUFD: 2583 case X86ISD::PSHUFHW: 2584 case X86ISD::PSHUFLW: 2585 case X86ISD::SHUFPD: 2586 case X86ISD::SHUFPS: 2587 case X86ISD::MOVLHPS: 2588 case X86ISD::MOVSS: 2589 case X86ISD::MOVSD: 2590 case X86ISD::PUNPCKLDQ: 2591 return true; 2592 } 2593 return false; 2594} 2595 2596static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2597 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2598 switch(Opc) { 2599 default: llvm_unreachable("Unknown x86 shuffle node"); 2600 case X86ISD::PSHUFD: 2601 case X86ISD::PSHUFHW: 2602 case X86ISD::PSHUFLW: 2603 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2604 } 2605 2606 return SDValue(); 2607} 2608 2609static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2610 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2611 switch(Opc) { 2612 default: llvm_unreachable("Unknown x86 shuffle node"); 2613 case X86ISD::SHUFPD: 2614 case X86ISD::SHUFPS: 2615 return DAG.getNode(Opc, dl, VT, V1, V2, 2616 DAG.getConstant(TargetMask, MVT::i8)); 2617 } 2618 return SDValue(); 2619} 2620 2621static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2622 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2623 switch(Opc) { 2624 default: llvm_unreachable("Unknown x86 shuffle node"); 2625 case X86ISD::MOVLHPS: 2626 case X86ISD::MOVLHPD: 2627 case X86ISD::MOVSS: 2628 case X86ISD::MOVSD: 2629 case X86ISD::PUNPCKLDQ: 2630 return DAG.getNode(Opc, dl, VT, V1, V2); 2631 } 2632 return SDValue(); 2633} 2634 2635SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2636 MachineFunction &MF = DAG.getMachineFunction(); 2637 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2638 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2639 2640 if (ReturnAddrIndex == 0) { 2641 // Set up a frame object for the return address. 2642 uint64_t SlotSize = TD->getPointerSize(); 2643 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2644 false); 2645 FuncInfo->setRAIndex(ReturnAddrIndex); 2646 } 2647 2648 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2649} 2650 2651 2652bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2653 bool hasSymbolicDisplacement) { 2654 // Offset should fit into 32 bit immediate field. 2655 if (!isInt<32>(Offset)) 2656 return false; 2657 2658 // If we don't have a symbolic displacement - we don't have any extra 2659 // restrictions. 2660 if (!hasSymbolicDisplacement) 2661 return true; 2662 2663 // FIXME: Some tweaks might be needed for medium code model. 2664 if (M != CodeModel::Small && M != CodeModel::Kernel) 2665 return false; 2666 2667 // For small code model we assume that latest object is 16MB before end of 31 2668 // bits boundary. We may also accept pretty large negative constants knowing 2669 // that all objects are in the positive half of address space. 2670 if (M == CodeModel::Small && Offset < 16*1024*1024) 2671 return true; 2672 2673 // For kernel code model we know that all object resist in the negative half 2674 // of 32bits address space. We may not accept negative offsets, since they may 2675 // be just off and we may accept pretty large positive ones. 2676 if (M == CodeModel::Kernel && Offset > 0) 2677 return true; 2678 2679 return false; 2680} 2681 2682/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2683/// specific condition code, returning the condition code and the LHS/RHS of the 2684/// comparison to make. 2685static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2686 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2687 if (!isFP) { 2688 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2689 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2690 // X > -1 -> X == 0, jump !sign. 2691 RHS = DAG.getConstant(0, RHS.getValueType()); 2692 return X86::COND_NS; 2693 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2694 // X < 0 -> X == 0, jump on sign. 2695 return X86::COND_S; 2696 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2697 // X < 1 -> X <= 0 2698 RHS = DAG.getConstant(0, RHS.getValueType()); 2699 return X86::COND_LE; 2700 } 2701 } 2702 2703 switch (SetCCOpcode) { 2704 default: llvm_unreachable("Invalid integer condition!"); 2705 case ISD::SETEQ: return X86::COND_E; 2706 case ISD::SETGT: return X86::COND_G; 2707 case ISD::SETGE: return X86::COND_GE; 2708 case ISD::SETLT: return X86::COND_L; 2709 case ISD::SETLE: return X86::COND_LE; 2710 case ISD::SETNE: return X86::COND_NE; 2711 case ISD::SETULT: return X86::COND_B; 2712 case ISD::SETUGT: return X86::COND_A; 2713 case ISD::SETULE: return X86::COND_BE; 2714 case ISD::SETUGE: return X86::COND_AE; 2715 } 2716 } 2717 2718 // First determine if it is required or is profitable to flip the operands. 2719 2720 // If LHS is a foldable load, but RHS is not, flip the condition. 2721 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2722 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2723 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2724 std::swap(LHS, RHS); 2725 } 2726 2727 switch (SetCCOpcode) { 2728 default: break; 2729 case ISD::SETOLT: 2730 case ISD::SETOLE: 2731 case ISD::SETUGT: 2732 case ISD::SETUGE: 2733 std::swap(LHS, RHS); 2734 break; 2735 } 2736 2737 // On a floating point condition, the flags are set as follows: 2738 // ZF PF CF op 2739 // 0 | 0 | 0 | X > Y 2740 // 0 | 0 | 1 | X < Y 2741 // 1 | 0 | 0 | X == Y 2742 // 1 | 1 | 1 | unordered 2743 switch (SetCCOpcode) { 2744 default: llvm_unreachable("Condcode should be pre-legalized away"); 2745 case ISD::SETUEQ: 2746 case ISD::SETEQ: return X86::COND_E; 2747 case ISD::SETOLT: // flipped 2748 case ISD::SETOGT: 2749 case ISD::SETGT: return X86::COND_A; 2750 case ISD::SETOLE: // flipped 2751 case ISD::SETOGE: 2752 case ISD::SETGE: return X86::COND_AE; 2753 case ISD::SETUGT: // flipped 2754 case ISD::SETULT: 2755 case ISD::SETLT: return X86::COND_B; 2756 case ISD::SETUGE: // flipped 2757 case ISD::SETULE: 2758 case ISD::SETLE: return X86::COND_BE; 2759 case ISD::SETONE: 2760 case ISD::SETNE: return X86::COND_NE; 2761 case ISD::SETUO: return X86::COND_P; 2762 case ISD::SETO: return X86::COND_NP; 2763 case ISD::SETOEQ: 2764 case ISD::SETUNE: return X86::COND_INVALID; 2765 } 2766} 2767 2768/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2769/// code. Current x86 isa includes the following FP cmov instructions: 2770/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2771static bool hasFPCMov(unsigned X86CC) { 2772 switch (X86CC) { 2773 default: 2774 return false; 2775 case X86::COND_B: 2776 case X86::COND_BE: 2777 case X86::COND_E: 2778 case X86::COND_P: 2779 case X86::COND_A: 2780 case X86::COND_AE: 2781 case X86::COND_NE: 2782 case X86::COND_NP: 2783 return true; 2784 } 2785} 2786 2787/// isFPImmLegal - Returns true if the target can instruction select the 2788/// specified FP immediate natively. If false, the legalizer will 2789/// materialize the FP immediate as a load from a constant pool. 2790bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2791 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2792 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2793 return true; 2794 } 2795 return false; 2796} 2797 2798/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2799/// the specified range (L, H]. 2800static bool isUndefOrInRange(int Val, int Low, int Hi) { 2801 return (Val < 0) || (Val >= Low && Val < Hi); 2802} 2803 2804/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2805/// specified value. 2806static bool isUndefOrEqual(int Val, int CmpVal) { 2807 if (Val < 0 || Val == CmpVal) 2808 return true; 2809 return false; 2810} 2811 2812/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2813/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2814/// the second operand. 2815static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2816 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2817 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2818 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2819 return (Mask[0] < 2 && Mask[1] < 2); 2820 return false; 2821} 2822 2823bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2824 SmallVector<int, 8> M; 2825 N->getMask(M); 2826 return ::isPSHUFDMask(M, N->getValueType(0)); 2827} 2828 2829/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2830/// is suitable for input to PSHUFHW. 2831static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2832 if (VT != MVT::v8i16) 2833 return false; 2834 2835 // Lower quadword copied in order or undef. 2836 for (int i = 0; i != 4; ++i) 2837 if (Mask[i] >= 0 && Mask[i] != i) 2838 return false; 2839 2840 // Upper quadword shuffled. 2841 for (int i = 4; i != 8; ++i) 2842 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2843 return false; 2844 2845 return true; 2846} 2847 2848bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2849 SmallVector<int, 8> M; 2850 N->getMask(M); 2851 return ::isPSHUFHWMask(M, N->getValueType(0)); 2852} 2853 2854/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2855/// is suitable for input to PSHUFLW. 2856static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2857 if (VT != MVT::v8i16) 2858 return false; 2859 2860 // Upper quadword copied in order. 2861 for (int i = 4; i != 8; ++i) 2862 if (Mask[i] >= 0 && Mask[i] != i) 2863 return false; 2864 2865 // Lower quadword shuffled. 2866 for (int i = 0; i != 4; ++i) 2867 if (Mask[i] >= 4) 2868 return false; 2869 2870 return true; 2871} 2872 2873bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2874 SmallVector<int, 8> M; 2875 N->getMask(M); 2876 return ::isPSHUFLWMask(M, N->getValueType(0)); 2877} 2878 2879/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2880/// is suitable for input to PALIGNR. 2881static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2882 bool hasSSSE3) { 2883 int i, e = VT.getVectorNumElements(); 2884 2885 // Do not handle v2i64 / v2f64 shuffles with palignr. 2886 if (e < 4 || !hasSSSE3) 2887 return false; 2888 2889 for (i = 0; i != e; ++i) 2890 if (Mask[i] >= 0) 2891 break; 2892 2893 // All undef, not a palignr. 2894 if (i == e) 2895 return false; 2896 2897 // Determine if it's ok to perform a palignr with only the LHS, since we 2898 // don't have access to the actual shuffle elements to see if RHS is undef. 2899 bool Unary = Mask[i] < (int)e; 2900 bool NeedsUnary = false; 2901 2902 int s = Mask[i] - i; 2903 2904 // Check the rest of the elements to see if they are consecutive. 2905 for (++i; i != e; ++i) { 2906 int m = Mask[i]; 2907 if (m < 0) 2908 continue; 2909 2910 Unary = Unary && (m < (int)e); 2911 NeedsUnary = NeedsUnary || (m < s); 2912 2913 if (NeedsUnary && !Unary) 2914 return false; 2915 if (Unary && m != ((s+i) & (e-1))) 2916 return false; 2917 if (!Unary && m != (s+i)) 2918 return false; 2919 } 2920 return true; 2921} 2922 2923bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2924 SmallVector<int, 8> M; 2925 N->getMask(M); 2926 return ::isPALIGNRMask(M, N->getValueType(0), true); 2927} 2928 2929/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2930/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2931static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2932 int NumElems = VT.getVectorNumElements(); 2933 if (NumElems != 2 && NumElems != 4) 2934 return false; 2935 2936 int Half = NumElems / 2; 2937 for (int i = 0; i < Half; ++i) 2938 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2939 return false; 2940 for (int i = Half; i < NumElems; ++i) 2941 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2942 return false; 2943 2944 return true; 2945} 2946 2947bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2948 SmallVector<int, 8> M; 2949 N->getMask(M); 2950 return ::isSHUFPMask(M, N->getValueType(0)); 2951} 2952 2953/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2954/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2955/// half elements to come from vector 1 (which would equal the dest.) and 2956/// the upper half to come from vector 2. 2957static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2958 int NumElems = VT.getVectorNumElements(); 2959 2960 if (NumElems != 2 && NumElems != 4) 2961 return false; 2962 2963 int Half = NumElems / 2; 2964 for (int i = 0; i < Half; ++i) 2965 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2966 return false; 2967 for (int i = Half; i < NumElems; ++i) 2968 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2969 return false; 2970 return true; 2971} 2972 2973static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2974 SmallVector<int, 8> M; 2975 N->getMask(M); 2976 return isCommutedSHUFPMask(M, N->getValueType(0)); 2977} 2978 2979/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2980/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2981bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2982 if (N->getValueType(0).getVectorNumElements() != 4) 2983 return false; 2984 2985 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2986 return isUndefOrEqual(N->getMaskElt(0), 6) && 2987 isUndefOrEqual(N->getMaskElt(1), 7) && 2988 isUndefOrEqual(N->getMaskElt(2), 2) && 2989 isUndefOrEqual(N->getMaskElt(3), 3); 2990} 2991 2992/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2993/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2994/// <2, 3, 2, 3> 2995bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2996 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2997 2998 if (NumElems != 4) 2999 return false; 3000 3001 return isUndefOrEqual(N->getMaskElt(0), 2) && 3002 isUndefOrEqual(N->getMaskElt(1), 3) && 3003 isUndefOrEqual(N->getMaskElt(2), 2) && 3004 isUndefOrEqual(N->getMaskElt(3), 3); 3005} 3006 3007/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3008/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3009bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3010 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3011 3012 if (NumElems != 2 && NumElems != 4) 3013 return false; 3014 3015 for (unsigned i = 0; i < NumElems/2; ++i) 3016 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3017 return false; 3018 3019 for (unsigned i = NumElems/2; i < NumElems; ++i) 3020 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3021 return false; 3022 3023 return true; 3024} 3025 3026/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3027/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3028bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3029 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3030 3031 if (NumElems != 2 && NumElems != 4) 3032 return false; 3033 3034 for (unsigned i = 0; i < NumElems/2; ++i) 3035 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3036 return false; 3037 3038 for (unsigned i = 0; i < NumElems/2; ++i) 3039 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3040 return false; 3041 3042 return true; 3043} 3044 3045/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3046/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3047static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3048 bool V2IsSplat = false) { 3049 int NumElts = VT.getVectorNumElements(); 3050 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 3051 return false; 3052 3053 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 3054 int BitI = Mask[i]; 3055 int BitI1 = Mask[i+1]; 3056 if (!isUndefOrEqual(BitI, j)) 3057 return false; 3058 if (V2IsSplat) { 3059 if (!isUndefOrEqual(BitI1, NumElts)) 3060 return false; 3061 } else { 3062 if (!isUndefOrEqual(BitI1, j + NumElts)) 3063 return false; 3064 } 3065 } 3066 return true; 3067} 3068 3069bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3070 SmallVector<int, 8> M; 3071 N->getMask(M); 3072 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3073} 3074 3075/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3076/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3077static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3078 bool V2IsSplat = false) { 3079 int NumElts = VT.getVectorNumElements(); 3080 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 3081 return false; 3082 3083 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 3084 int BitI = Mask[i]; 3085 int BitI1 = Mask[i+1]; 3086 if (!isUndefOrEqual(BitI, j + NumElts/2)) 3087 return false; 3088 if (V2IsSplat) { 3089 if (isUndefOrEqual(BitI1, NumElts)) 3090 return false; 3091 } else { 3092 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 3093 return false; 3094 } 3095 } 3096 return true; 3097} 3098 3099bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3100 SmallVector<int, 8> M; 3101 N->getMask(M); 3102 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3103} 3104 3105/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3106/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3107/// <0, 0, 1, 1> 3108static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3109 int NumElems = VT.getVectorNumElements(); 3110 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3111 return false; 3112 3113 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 3114 int BitI = Mask[i]; 3115 int BitI1 = Mask[i+1]; 3116 if (!isUndefOrEqual(BitI, j)) 3117 return false; 3118 if (!isUndefOrEqual(BitI1, j)) 3119 return false; 3120 } 3121 return true; 3122} 3123 3124bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3125 SmallVector<int, 8> M; 3126 N->getMask(M); 3127 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3128} 3129 3130/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3131/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3132/// <2, 2, 3, 3> 3133static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3134 int NumElems = VT.getVectorNumElements(); 3135 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3136 return false; 3137 3138 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3139 int BitI = Mask[i]; 3140 int BitI1 = Mask[i+1]; 3141 if (!isUndefOrEqual(BitI, j)) 3142 return false; 3143 if (!isUndefOrEqual(BitI1, j)) 3144 return false; 3145 } 3146 return true; 3147} 3148 3149bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3150 SmallVector<int, 8> M; 3151 N->getMask(M); 3152 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3153} 3154 3155/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3156/// specifies a shuffle of elements that is suitable for input to MOVSS, 3157/// MOVSD, and MOVD, i.e. setting the lowest element. 3158static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3159 if (VT.getVectorElementType().getSizeInBits() < 32) 3160 return false; 3161 3162 int NumElts = VT.getVectorNumElements(); 3163 3164 if (!isUndefOrEqual(Mask[0], NumElts)) 3165 return false; 3166 3167 for (int i = 1; i < NumElts; ++i) 3168 if (!isUndefOrEqual(Mask[i], i)) 3169 return false; 3170 3171 return true; 3172} 3173 3174bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3175 SmallVector<int, 8> M; 3176 N->getMask(M); 3177 return ::isMOVLMask(M, N->getValueType(0)); 3178} 3179 3180/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3181/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3182/// element of vector 2 and the other elements to come from vector 1 in order. 3183static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3184 bool V2IsSplat = false, bool V2IsUndef = false) { 3185 int NumOps = VT.getVectorNumElements(); 3186 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3187 return false; 3188 3189 if (!isUndefOrEqual(Mask[0], 0)) 3190 return false; 3191 3192 for (int i = 1; i < NumOps; ++i) 3193 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3194 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3195 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3196 return false; 3197 3198 return true; 3199} 3200 3201static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3202 bool V2IsUndef = false) { 3203 SmallVector<int, 8> M; 3204 N->getMask(M); 3205 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3206} 3207 3208/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3209/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3210bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 3211 if (N->getValueType(0).getVectorNumElements() != 4) 3212 return false; 3213 3214 // Expect 1, 1, 3, 3 3215 for (unsigned i = 0; i < 2; ++i) { 3216 int Elt = N->getMaskElt(i); 3217 if (Elt >= 0 && Elt != 1) 3218 return false; 3219 } 3220 3221 bool HasHi = false; 3222 for (unsigned i = 2; i < 4; ++i) { 3223 int Elt = N->getMaskElt(i); 3224 if (Elt >= 0 && Elt != 3) 3225 return false; 3226 if (Elt == 3) 3227 HasHi = true; 3228 } 3229 // Don't use movshdup if it can be done with a shufps. 3230 // FIXME: verify that matching u, u, 3, 3 is what we want. 3231 return HasHi; 3232} 3233 3234/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3235/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3236bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 3237 if (N->getValueType(0).getVectorNumElements() != 4) 3238 return false; 3239 3240 // Expect 0, 0, 2, 2 3241 for (unsigned i = 0; i < 2; ++i) 3242 if (N->getMaskElt(i) > 0) 3243 return false; 3244 3245 bool HasHi = false; 3246 for (unsigned i = 2; i < 4; ++i) { 3247 int Elt = N->getMaskElt(i); 3248 if (Elt >= 0 && Elt != 2) 3249 return false; 3250 if (Elt == 2) 3251 HasHi = true; 3252 } 3253 // Don't use movsldup if it can be done with a shufps. 3254 return HasHi; 3255} 3256 3257/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3258/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3259bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3260 int e = N->getValueType(0).getVectorNumElements() / 2; 3261 3262 for (int i = 0; i < e; ++i) 3263 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3264 return false; 3265 for (int i = 0; i < e; ++i) 3266 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3267 return false; 3268 return true; 3269} 3270 3271/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3272/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3273unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3274 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3275 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3276 3277 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3278 unsigned Mask = 0; 3279 for (int i = 0; i < NumOperands; ++i) { 3280 int Val = SVOp->getMaskElt(NumOperands-i-1); 3281 if (Val < 0) Val = 0; 3282 if (Val >= NumOperands) Val -= NumOperands; 3283 Mask |= Val; 3284 if (i != NumOperands - 1) 3285 Mask <<= Shift; 3286 } 3287 return Mask; 3288} 3289 3290/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3291/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3292unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3293 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3294 unsigned Mask = 0; 3295 // 8 nodes, but we only care about the last 4. 3296 for (unsigned i = 7; i >= 4; --i) { 3297 int Val = SVOp->getMaskElt(i); 3298 if (Val >= 0) 3299 Mask |= (Val - 4); 3300 if (i != 4) 3301 Mask <<= 2; 3302 } 3303 return Mask; 3304} 3305 3306/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3307/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3308unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3309 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3310 unsigned Mask = 0; 3311 // 8 nodes, but we only care about the first 4. 3312 for (int i = 3; i >= 0; --i) { 3313 int Val = SVOp->getMaskElt(i); 3314 if (Val >= 0) 3315 Mask |= Val; 3316 if (i != 0) 3317 Mask <<= 2; 3318 } 3319 return Mask; 3320} 3321 3322/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3323/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3324unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3325 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3326 EVT VVT = N->getValueType(0); 3327 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3328 int Val = 0; 3329 3330 unsigned i, e; 3331 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3332 Val = SVOp->getMaskElt(i); 3333 if (Val >= 0) 3334 break; 3335 } 3336 return (Val - i) * EltSize; 3337} 3338 3339/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3340/// constant +0.0. 3341bool X86::isZeroNode(SDValue Elt) { 3342 return ((isa<ConstantSDNode>(Elt) && 3343 cast<ConstantSDNode>(Elt)->isNullValue()) || 3344 (isa<ConstantFPSDNode>(Elt) && 3345 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3346} 3347 3348/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3349/// their permute mask. 3350static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3351 SelectionDAG &DAG) { 3352 EVT VT = SVOp->getValueType(0); 3353 unsigned NumElems = VT.getVectorNumElements(); 3354 SmallVector<int, 8> MaskVec; 3355 3356 for (unsigned i = 0; i != NumElems; ++i) { 3357 int idx = SVOp->getMaskElt(i); 3358 if (idx < 0) 3359 MaskVec.push_back(idx); 3360 else if (idx < (int)NumElems) 3361 MaskVec.push_back(idx + NumElems); 3362 else 3363 MaskVec.push_back(idx - NumElems); 3364 } 3365 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3366 SVOp->getOperand(0), &MaskVec[0]); 3367} 3368 3369/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3370/// the two vector operands have swapped position. 3371static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3372 unsigned NumElems = VT.getVectorNumElements(); 3373 for (unsigned i = 0; i != NumElems; ++i) { 3374 int idx = Mask[i]; 3375 if (idx < 0) 3376 continue; 3377 else if (idx < (int)NumElems) 3378 Mask[i] = idx + NumElems; 3379 else 3380 Mask[i] = idx - NumElems; 3381 } 3382} 3383 3384/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3385/// match movhlps. The lower half elements should come from upper half of 3386/// V1 (and in order), and the upper half elements should come from the upper 3387/// half of V2 (and in order). 3388static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3389 if (Op->getValueType(0).getVectorNumElements() != 4) 3390 return false; 3391 for (unsigned i = 0, e = 2; i != e; ++i) 3392 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3393 return false; 3394 for (unsigned i = 2; i != 4; ++i) 3395 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3396 return false; 3397 return true; 3398} 3399 3400/// isScalarLoadToVector - Returns true if the node is a scalar load that 3401/// is promoted to a vector. It also returns the LoadSDNode by reference if 3402/// required. 3403static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3404 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3405 return false; 3406 N = N->getOperand(0).getNode(); 3407 if (!ISD::isNON_EXTLoad(N)) 3408 return false; 3409 if (LD) 3410 *LD = cast<LoadSDNode>(N); 3411 return true; 3412} 3413 3414/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3415/// match movlp{s|d}. The lower half elements should come from lower half of 3416/// V1 (and in order), and the upper half elements should come from the upper 3417/// half of V2 (and in order). And since V1 will become the source of the 3418/// MOVLP, it must be either a vector load or a scalar load to vector. 3419static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3420 ShuffleVectorSDNode *Op) { 3421 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3422 return false; 3423 // Is V2 is a vector load, don't do this transformation. We will try to use 3424 // load folding shufps op. 3425 if (ISD::isNON_EXTLoad(V2)) 3426 return false; 3427 3428 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3429 3430 if (NumElems != 2 && NumElems != 4) 3431 return false; 3432 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3433 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3434 return false; 3435 for (unsigned i = NumElems/2; i != NumElems; ++i) 3436 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3437 return false; 3438 return true; 3439} 3440 3441/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3442/// all the same. 3443static bool isSplatVector(SDNode *N) { 3444 if (N->getOpcode() != ISD::BUILD_VECTOR) 3445 return false; 3446 3447 SDValue SplatValue = N->getOperand(0); 3448 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3449 if (N->getOperand(i) != SplatValue) 3450 return false; 3451 return true; 3452} 3453 3454/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3455/// to an zero vector. 3456/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3457static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3458 SDValue V1 = N->getOperand(0); 3459 SDValue V2 = N->getOperand(1); 3460 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3461 for (unsigned i = 0; i != NumElems; ++i) { 3462 int Idx = N->getMaskElt(i); 3463 if (Idx >= (int)NumElems) { 3464 unsigned Opc = V2.getOpcode(); 3465 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3466 continue; 3467 if (Opc != ISD::BUILD_VECTOR || 3468 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3469 return false; 3470 } else if (Idx >= 0) { 3471 unsigned Opc = V1.getOpcode(); 3472 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3473 continue; 3474 if (Opc != ISD::BUILD_VECTOR || 3475 !X86::isZeroNode(V1.getOperand(Idx))) 3476 return false; 3477 } 3478 } 3479 return true; 3480} 3481 3482/// getZeroVector - Returns a vector of specified type with all zero elements. 3483/// 3484static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3485 DebugLoc dl) { 3486 assert(VT.isVector() && "Expected a vector type"); 3487 3488 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted 3489 // to their dest type. This ensures they get CSE'd. 3490 SDValue Vec; 3491 if (VT.getSizeInBits() == 64) { // MMX 3492 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3493 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3494 } else if (VT.getSizeInBits() == 128) { 3495 if (HasSSE2) { // SSE2 3496 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3497 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3498 } else { // SSE1 3499 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3500 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3501 } 3502 } else if (VT.getSizeInBits() == 256) { // AVX 3503 // 256-bit logic and arithmetic instructions in AVX are 3504 // all floating-point, no support for integer ops. Default 3505 // to emitting fp zeroed vectors then. 3506 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3507 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 3508 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 3509 } 3510 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3511} 3512 3513/// getOnesVector - Returns a vector of specified type with all bits set. 3514/// 3515static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3516 assert(VT.isVector() && "Expected a vector type"); 3517 3518 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3519 // type. This ensures they get CSE'd. 3520 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3521 SDValue Vec; 3522 if (VT.getSizeInBits() == 64) // MMX 3523 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3524 else // SSE 3525 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3526 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3527} 3528 3529 3530/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3531/// that point to V2 points to its first element. 3532static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3533 EVT VT = SVOp->getValueType(0); 3534 unsigned NumElems = VT.getVectorNumElements(); 3535 3536 bool Changed = false; 3537 SmallVector<int, 8> MaskVec; 3538 SVOp->getMask(MaskVec); 3539 3540 for (unsigned i = 0; i != NumElems; ++i) { 3541 if (MaskVec[i] > (int)NumElems) { 3542 MaskVec[i] = NumElems; 3543 Changed = true; 3544 } 3545 } 3546 if (Changed) 3547 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3548 SVOp->getOperand(1), &MaskVec[0]); 3549 return SDValue(SVOp, 0); 3550} 3551 3552/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3553/// operation of specified width. 3554static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3555 SDValue V2) { 3556 unsigned NumElems = VT.getVectorNumElements(); 3557 SmallVector<int, 8> Mask; 3558 Mask.push_back(NumElems); 3559 for (unsigned i = 1; i != NumElems; ++i) 3560 Mask.push_back(i); 3561 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3562} 3563 3564/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3565static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3566 SDValue V2) { 3567 unsigned NumElems = VT.getVectorNumElements(); 3568 SmallVector<int, 8> Mask; 3569 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3570 Mask.push_back(i); 3571 Mask.push_back(i + NumElems); 3572 } 3573 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3574} 3575 3576/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3577static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3578 SDValue V2) { 3579 unsigned NumElems = VT.getVectorNumElements(); 3580 unsigned Half = NumElems/2; 3581 SmallVector<int, 8> Mask; 3582 for (unsigned i = 0; i != Half; ++i) { 3583 Mask.push_back(i + Half); 3584 Mask.push_back(i + NumElems + Half); 3585 } 3586 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3587} 3588 3589/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32. 3590static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 3591 if (SV->getValueType(0).getVectorNumElements() <= 4) 3592 return SDValue(SV, 0); 3593 3594 EVT PVT = MVT::v4f32; 3595 EVT VT = SV->getValueType(0); 3596 DebugLoc dl = SV->getDebugLoc(); 3597 SDValue V1 = SV->getOperand(0); 3598 int NumElems = VT.getVectorNumElements(); 3599 int EltNo = SV->getSplatIndex(); 3600 3601 // unpack elements to the correct location 3602 while (NumElems > 4) { 3603 if (EltNo < NumElems/2) { 3604 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3605 } else { 3606 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3607 EltNo -= NumElems/2; 3608 } 3609 NumElems >>= 1; 3610 } 3611 3612 // Perform the splat. 3613 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3614 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3615 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3616 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3617} 3618 3619/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3620/// vector of zero or undef vector. This produces a shuffle where the low 3621/// element of V2 is swizzled into the zero/undef vector, landing at element 3622/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3623static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3624 bool isZero, bool HasSSE2, 3625 SelectionDAG &DAG) { 3626 EVT VT = V2.getValueType(); 3627 SDValue V1 = isZero 3628 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3629 unsigned NumElems = VT.getVectorNumElements(); 3630 SmallVector<int, 16> MaskVec; 3631 for (unsigned i = 0; i != NumElems; ++i) 3632 // If this is the insertion idx, put the low elt of V2 here. 3633 MaskVec.push_back(i == Idx ? NumElems : i); 3634 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3635} 3636 3637/// getShuffleScalarElt - Returns the scalar element that will make up the ith 3638/// element of the result of the vector shuffle. 3639SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG) { 3640 SDValue V = SDValue(N, 0); 3641 EVT VT = V.getValueType(); 3642 unsigned Opcode = V.getOpcode(); 3643 int NumElems = VT.getVectorNumElements(); 3644 3645 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 3646 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 3647 Index = SV->getMaskElt(Index); 3648 3649 if (Index < 0) 3650 return DAG.getUNDEF(VT.getVectorElementType()); 3651 3652 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 3653 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG); 3654 } 3655 3656 // Recurse into target specific vector shuffles to find scalars. 3657 if (isTargetShuffle(Opcode)) { 3658 switch(Opcode) { 3659 case X86ISD::MOVSS: 3660 case X86ISD::MOVSD: { 3661 // The index 0 always comes from the first element of the second source, 3662 // this is why MOVSS and MOVSD are used in the first place. The other 3663 // elements come from the other positions of the first source vector. 3664 unsigned OpNum = (Index == 0) ? 1 : 0; 3665 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG); 3666 } 3667 default: 3668 assert("not implemented for target shuffle node"); 3669 return SDValue(); 3670 } 3671 } 3672 3673 // Actual nodes that may contain scalar elements 3674 if (Opcode == ISD::BIT_CONVERT) { 3675 V = V.getOperand(0); 3676 EVT SrcVT = V.getValueType(); 3677 3678 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != (unsigned)NumElems) 3679 return SDValue(); 3680 } 3681 3682 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 3683 return (Index == 0) ? V.getOperand(0) 3684 : DAG.getUNDEF(VT.getVectorElementType()); 3685 3686 if (V.getOpcode() == ISD::BUILD_VECTOR) 3687 return V.getOperand(Index); 3688 3689 return SDValue(); 3690} 3691 3692/// getNumOfConsecutiveZeros - Return the number of elements of a vector 3693/// shuffle operation which come from a consecutively from a zero. The 3694/// search can start in two diferent directions, from left or right. 3695static 3696unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 3697 bool ZerosFromLeft, SelectionDAG &DAG) { 3698 int i = 0; 3699 3700 while (i < NumElems) { 3701 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 3702 SDValue Elt = getShuffleScalarElt(N, Index, DAG); 3703 if (!(Elt.getNode() && 3704 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 3705 break; 3706 ++i; 3707 } 3708 3709 return i; 3710} 3711 3712/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 3713/// MaskE correspond consecutively to elements from one of the vector operands, 3714/// starting from its index OpIdx. Also tell OpNum which source vector operand. 3715static 3716bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 3717 int OpIdx, int NumElems, unsigned &OpNum) { 3718 bool SeenV1 = false; 3719 bool SeenV2 = false; 3720 3721 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 3722 int Idx = SVOp->getMaskElt(i); 3723 // Ignore undef indicies 3724 if (Idx < 0) 3725 continue; 3726 3727 if (Idx < NumElems) 3728 SeenV1 = true; 3729 else 3730 SeenV2 = true; 3731 3732 // Only accept consecutive elements from the same vector 3733 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 3734 return false; 3735 } 3736 3737 OpNum = SeenV1 ? 0 : 1; 3738 return true; 3739} 3740 3741/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 3742/// logical left shift of a vector. 3743static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3744 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3745 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 3746 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 3747 false /* check zeros from right */, DAG); 3748 unsigned OpSrc; 3749 3750 if (!NumZeros) 3751 return false; 3752 3753 // Considering the elements in the mask that are not consecutive zeros, 3754 // check if they consecutively come from only one of the source vectors. 3755 // 3756 // V1 = {X, A, B, C} 0 3757 // \ \ \ / 3758 // vector_shuffle V1, V2 <1, 2, 3, X> 3759 // 3760 if (!isShuffleMaskConsecutive(SVOp, 3761 0, // Mask Start Index 3762 NumElems-NumZeros-1, // Mask End Index 3763 NumZeros, // Where to start looking in the src vector 3764 NumElems, // Number of elements in vector 3765 OpSrc)) // Which source operand ? 3766 return false; 3767 3768 isLeft = false; 3769 ShAmt = NumZeros; 3770 ShVal = SVOp->getOperand(OpSrc); 3771 return true; 3772} 3773 3774/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 3775/// logical left shift of a vector. 3776static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3777 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3778 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 3779 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 3780 true /* check zeros from left */, DAG); 3781 unsigned OpSrc; 3782 3783 if (!NumZeros) 3784 return false; 3785 3786 // Considering the elements in the mask that are not consecutive zeros, 3787 // check if they consecutively come from only one of the source vectors. 3788 // 3789 // 0 { A, B, X, X } = V2 3790 // / \ / / 3791 // vector_shuffle V1, V2 <X, X, 4, 5> 3792 // 3793 if (!isShuffleMaskConsecutive(SVOp, 3794 NumZeros, // Mask Start Index 3795 NumElems-1, // Mask End Index 3796 0, // Where to start looking in the src vector 3797 NumElems, // Number of elements in vector 3798 OpSrc)) // Which source operand ? 3799 return false; 3800 3801 isLeft = true; 3802 ShAmt = NumZeros; 3803 ShVal = SVOp->getOperand(OpSrc); 3804 return true; 3805} 3806 3807/// isVectorShift - Returns true if the shuffle can be implemented as a 3808/// logical left or right shift of a vector. 3809static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3810 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3811 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 3812 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 3813 return true; 3814 3815 return false; 3816} 3817 3818/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3819/// 3820static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3821 unsigned NumNonZero, unsigned NumZero, 3822 SelectionDAG &DAG, 3823 const TargetLowering &TLI) { 3824 if (NumNonZero > 8) 3825 return SDValue(); 3826 3827 DebugLoc dl = Op.getDebugLoc(); 3828 SDValue V(0, 0); 3829 bool First = true; 3830 for (unsigned i = 0; i < 16; ++i) { 3831 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3832 if (ThisIsNonZero && First) { 3833 if (NumZero) 3834 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3835 else 3836 V = DAG.getUNDEF(MVT::v8i16); 3837 First = false; 3838 } 3839 3840 if ((i & 1) != 0) { 3841 SDValue ThisElt(0, 0), LastElt(0, 0); 3842 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3843 if (LastIsNonZero) { 3844 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3845 MVT::i16, Op.getOperand(i-1)); 3846 } 3847 if (ThisIsNonZero) { 3848 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3849 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3850 ThisElt, DAG.getConstant(8, MVT::i8)); 3851 if (LastIsNonZero) 3852 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3853 } else 3854 ThisElt = LastElt; 3855 3856 if (ThisElt.getNode()) 3857 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3858 DAG.getIntPtrConstant(i/2)); 3859 } 3860 } 3861 3862 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3863} 3864 3865/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3866/// 3867static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3868 unsigned NumNonZero, unsigned NumZero, 3869 SelectionDAG &DAG, 3870 const TargetLowering &TLI) { 3871 if (NumNonZero > 4) 3872 return SDValue(); 3873 3874 DebugLoc dl = Op.getDebugLoc(); 3875 SDValue V(0, 0); 3876 bool First = true; 3877 for (unsigned i = 0; i < 8; ++i) { 3878 bool isNonZero = (NonZeros & (1 << i)) != 0; 3879 if (isNonZero) { 3880 if (First) { 3881 if (NumZero) 3882 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3883 else 3884 V = DAG.getUNDEF(MVT::v8i16); 3885 First = false; 3886 } 3887 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3888 MVT::v8i16, V, Op.getOperand(i), 3889 DAG.getIntPtrConstant(i)); 3890 } 3891 } 3892 3893 return V; 3894} 3895 3896/// getVShift - Return a vector logical shift node. 3897/// 3898static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3899 unsigned NumBits, SelectionDAG &DAG, 3900 const TargetLowering &TLI, DebugLoc dl) { 3901 bool isMMX = VT.getSizeInBits() == 64; 3902 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3903 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3904 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3905 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3906 DAG.getNode(Opc, dl, ShVT, SrcOp, 3907 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3908} 3909 3910SDValue 3911X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3912 SelectionDAG &DAG) const { 3913 3914 // Check if the scalar load can be widened into a vector load. And if 3915 // the address is "base + cst" see if the cst can be "absorbed" into 3916 // the shuffle mask. 3917 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3918 SDValue Ptr = LD->getBasePtr(); 3919 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 3920 return SDValue(); 3921 EVT PVT = LD->getValueType(0); 3922 if (PVT != MVT::i32 && PVT != MVT::f32) 3923 return SDValue(); 3924 3925 int FI = -1; 3926 int64_t Offset = 0; 3927 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 3928 FI = FINode->getIndex(); 3929 Offset = 0; 3930 } else if (Ptr.getOpcode() == ISD::ADD && 3931 isa<ConstantSDNode>(Ptr.getOperand(1)) && 3932 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 3933 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 3934 Offset = Ptr.getConstantOperandVal(1); 3935 Ptr = Ptr.getOperand(0); 3936 } else { 3937 return SDValue(); 3938 } 3939 3940 SDValue Chain = LD->getChain(); 3941 // Make sure the stack object alignment is at least 16. 3942 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3943 if (DAG.InferPtrAlignment(Ptr) < 16) { 3944 if (MFI->isFixedObjectIndex(FI)) { 3945 // Can't change the alignment. FIXME: It's possible to compute 3946 // the exact stack offset and reference FI + adjust offset instead. 3947 // If someone *really* cares about this. That's the way to implement it. 3948 return SDValue(); 3949 } else { 3950 MFI->setObjectAlignment(FI, 16); 3951 } 3952 } 3953 3954 // (Offset % 16) must be multiple of 4. Then address is then 3955 // Ptr + (Offset & ~15). 3956 if (Offset < 0) 3957 return SDValue(); 3958 if ((Offset % 16) & 3) 3959 return SDValue(); 3960 int64_t StartOffset = Offset & ~15; 3961 if (StartOffset) 3962 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 3963 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 3964 3965 int EltNo = (Offset - StartOffset) >> 2; 3966 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 3967 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 3968 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0, 3969 false, false, 0); 3970 // Canonicalize it to a v4i32 shuffle. 3971 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); 3972 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3973 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 3974 DAG.getUNDEF(MVT::v4i32), &Mask[0])); 3975 } 3976 3977 return SDValue(); 3978} 3979 3980/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 3981/// vector of type 'VT', see if the elements can be replaced by a single large 3982/// load which has the same value as a build_vector whose operands are 'elts'. 3983/// 3984/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 3985/// 3986/// FIXME: we'd also like to handle the case where the last elements are zero 3987/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 3988/// There's even a handy isZeroNode for that purpose. 3989static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 3990 DebugLoc &dl, SelectionDAG &DAG) { 3991 EVT EltVT = VT.getVectorElementType(); 3992 unsigned NumElems = Elts.size(); 3993 3994 LoadSDNode *LDBase = NULL; 3995 unsigned LastLoadedElt = -1U; 3996 3997 // For each element in the initializer, see if we've found a load or an undef. 3998 // If we don't find an initial load element, or later load elements are 3999 // non-consecutive, bail out. 4000 for (unsigned i = 0; i < NumElems; ++i) { 4001 SDValue Elt = Elts[i]; 4002 4003 if (!Elt.getNode() || 4004 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4005 return SDValue(); 4006 if (!LDBase) { 4007 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4008 return SDValue(); 4009 LDBase = cast<LoadSDNode>(Elt.getNode()); 4010 LastLoadedElt = i; 4011 continue; 4012 } 4013 if (Elt.getOpcode() == ISD::UNDEF) 4014 continue; 4015 4016 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4017 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4018 return SDValue(); 4019 LastLoadedElt = i; 4020 } 4021 4022 // If we have found an entire vector of loads and undefs, then return a large 4023 // load of the entire vector width starting at the base pointer. If we found 4024 // consecutive loads for the low half, generate a vzext_load node. 4025 if (LastLoadedElt == NumElems - 1) { 4026 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4027 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 4028 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 4029 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 4030 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 4031 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 4032 LDBase->isVolatile(), LDBase->isNonTemporal(), 4033 LDBase->getAlignment()); 4034 } else if (NumElems == 4 && LastLoadedElt == 1) { 4035 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4036 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4037 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 4038 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 4039 } 4040 return SDValue(); 4041} 4042 4043SDValue 4044X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4045 DebugLoc dl = Op.getDebugLoc(); 4046 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1. 4047 // All one's are handled with pcmpeqd. In AVX, zero's are handled with 4048 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd 4049 // is present, so AllOnes is ignored. 4050 if (ISD::isBuildVectorAllZeros(Op.getNode()) || 4051 (Op.getValueType().getSizeInBits() != 256 && 4052 ISD::isBuildVectorAllOnes(Op.getNode()))) { 4053 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 4054 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 4055 // eliminated on x86-32 hosts. 4056 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 4057 return Op; 4058 4059 if (ISD::isBuildVectorAllOnes(Op.getNode())) 4060 return getOnesVector(Op.getValueType(), DAG, dl); 4061 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 4062 } 4063 4064 EVT VT = Op.getValueType(); 4065 EVT ExtVT = VT.getVectorElementType(); 4066 unsigned EVTBits = ExtVT.getSizeInBits(); 4067 4068 unsigned NumElems = Op.getNumOperands(); 4069 unsigned NumZero = 0; 4070 unsigned NumNonZero = 0; 4071 unsigned NonZeros = 0; 4072 bool IsAllConstants = true; 4073 SmallSet<SDValue, 8> Values; 4074 for (unsigned i = 0; i < NumElems; ++i) { 4075 SDValue Elt = Op.getOperand(i); 4076 if (Elt.getOpcode() == ISD::UNDEF) 4077 continue; 4078 Values.insert(Elt); 4079 if (Elt.getOpcode() != ISD::Constant && 4080 Elt.getOpcode() != ISD::ConstantFP) 4081 IsAllConstants = false; 4082 if (X86::isZeroNode(Elt)) 4083 NumZero++; 4084 else { 4085 NonZeros |= (1 << i); 4086 NumNonZero++; 4087 } 4088 } 4089 4090 // All undef vector. Return an UNDEF. All zero vectors were handled above. 4091 if (NumNonZero == 0) 4092 return DAG.getUNDEF(VT); 4093 4094 // Special case for single non-zero, non-undef, element. 4095 if (NumNonZero == 1) { 4096 unsigned Idx = CountTrailingZeros_32(NonZeros); 4097 SDValue Item = Op.getOperand(Idx); 4098 4099 // If this is an insertion of an i64 value on x86-32, and if the top bits of 4100 // the value are obviously zero, truncate the value to i32 and do the 4101 // insertion that way. Only do this if the value is non-constant or if the 4102 // value is a constant being inserted into element 0. It is cheaper to do 4103 // a constant pool load than it is to do a movd + shuffle. 4104 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 4105 (!IsAllConstants || Idx == 0)) { 4106 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 4107 // Handle MMX and SSE both. 4108 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 4109 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 4110 4111 // Truncate the value (which may itself be a constant) to i32, and 4112 // convert it to a vector with movd (S2V+shuffle to zero extend). 4113 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 4114 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 4115 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4116 Subtarget->hasSSE2(), DAG); 4117 4118 // Now we have our 32-bit value zero extended in the low element of 4119 // a vector. If Idx != 0, swizzle it into place. 4120 if (Idx != 0) { 4121 SmallVector<int, 4> Mask; 4122 Mask.push_back(Idx); 4123 for (unsigned i = 1; i != VecElts; ++i) 4124 Mask.push_back(i); 4125 Item = DAG.getVectorShuffle(VecVT, dl, Item, 4126 DAG.getUNDEF(Item.getValueType()), 4127 &Mask[0]); 4128 } 4129 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 4130 } 4131 } 4132 4133 // If we have a constant or non-constant insertion into the low element of 4134 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 4135 // the rest of the elements. This will be matched as movd/movq/movss/movsd 4136 // depending on what the source datatype is. 4137 if (Idx == 0) { 4138 if (NumZero == 0) { 4139 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4140 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 4141 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 4142 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4143 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 4144 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 4145 DAG); 4146 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 4147 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 4148 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 4149 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 4150 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4151 Subtarget->hasSSE2(), DAG); 4152 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 4153 } 4154 } 4155 4156 // Is it a vector logical left shift? 4157 if (NumElems == 2 && Idx == 1 && 4158 X86::isZeroNode(Op.getOperand(0)) && 4159 !X86::isZeroNode(Op.getOperand(1))) { 4160 unsigned NumBits = VT.getSizeInBits(); 4161 return getVShift(true, VT, 4162 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4163 VT, Op.getOperand(1)), 4164 NumBits/2, DAG, *this, dl); 4165 } 4166 4167 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 4168 return SDValue(); 4169 4170 // Otherwise, if this is a vector with i32 or f32 elements, and the element 4171 // is a non-constant being inserted into an element other than the low one, 4172 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 4173 // movd/movss) to move this into the low element, then shuffle it into 4174 // place. 4175 if (EVTBits == 32) { 4176 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4177 4178 // Turn it into a shuffle of zero and zero-extended scalar to vector. 4179 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 4180 Subtarget->hasSSE2(), DAG); 4181 SmallVector<int, 8> MaskVec; 4182 for (unsigned i = 0; i < NumElems; i++) 4183 MaskVec.push_back(i == Idx ? 0 : 1); 4184 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 4185 } 4186 } 4187 4188 // Splat is obviously ok. Let legalizer expand it to a shuffle. 4189 if (Values.size() == 1) { 4190 if (EVTBits == 32) { 4191 // Instead of a shuffle like this: 4192 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 4193 // Check if it's possible to issue this instead. 4194 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 4195 unsigned Idx = CountTrailingZeros_32(NonZeros); 4196 SDValue Item = Op.getOperand(Idx); 4197 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 4198 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 4199 } 4200 return SDValue(); 4201 } 4202 4203 // A vector full of immediates; various special cases are already 4204 // handled, so this is best done with a single constant-pool load. 4205 if (IsAllConstants) 4206 return SDValue(); 4207 4208 // Let legalizer expand 2-wide build_vectors. 4209 if (EVTBits == 64) { 4210 if (NumNonZero == 1) { 4211 // One half is zero or undef. 4212 unsigned Idx = CountTrailingZeros_32(NonZeros); 4213 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 4214 Op.getOperand(Idx)); 4215 return getShuffleVectorZeroOrUndef(V2, Idx, true, 4216 Subtarget->hasSSE2(), DAG); 4217 } 4218 return SDValue(); 4219 } 4220 4221 // If element VT is < 32 bits, convert it to inserts into a zero vector. 4222 if (EVTBits == 8 && NumElems == 16) { 4223 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 4224 *this); 4225 if (V.getNode()) return V; 4226 } 4227 4228 if (EVTBits == 16 && NumElems == 8) { 4229 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 4230 *this); 4231 if (V.getNode()) return V; 4232 } 4233 4234 // If element VT is == 32 bits, turn it into a number of shuffles. 4235 SmallVector<SDValue, 8> V; 4236 V.resize(NumElems); 4237 if (NumElems == 4 && NumZero > 0) { 4238 for (unsigned i = 0; i < 4; ++i) { 4239 bool isZero = !(NonZeros & (1 << i)); 4240 if (isZero) 4241 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4242 else 4243 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4244 } 4245 4246 for (unsigned i = 0; i < 2; ++i) { 4247 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 4248 default: break; 4249 case 0: 4250 V[i] = V[i*2]; // Must be a zero vector. 4251 break; 4252 case 1: 4253 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 4254 break; 4255 case 2: 4256 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 4257 break; 4258 case 3: 4259 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 4260 break; 4261 } 4262 } 4263 4264 SmallVector<int, 8> MaskVec; 4265 bool Reverse = (NonZeros & 0x3) == 2; 4266 for (unsigned i = 0; i < 2; ++i) 4267 MaskVec.push_back(Reverse ? 1-i : i); 4268 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 4269 for (unsigned i = 0; i < 2; ++i) 4270 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 4271 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 4272 } 4273 4274 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 4275 // Check for a build vector of consecutive loads. 4276 for (unsigned i = 0; i < NumElems; ++i) 4277 V[i] = Op.getOperand(i); 4278 4279 // Check for elements which are consecutive loads. 4280 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 4281 if (LD.getNode()) 4282 return LD; 4283 4284 // For SSE 4.1, use insertps to put the high elements into the low element. 4285 if (getSubtarget()->hasSSE41()) { 4286 SDValue Result; 4287 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 4288 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 4289 else 4290 Result = DAG.getUNDEF(VT); 4291 4292 for (unsigned i = 1; i < NumElems; ++i) { 4293 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 4294 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 4295 Op.getOperand(i), DAG.getIntPtrConstant(i)); 4296 } 4297 return Result; 4298 } 4299 4300 // Otherwise, expand into a number of unpckl*, start by extending each of 4301 // our (non-undef) elements to the full vector width with the element in the 4302 // bottom slot of the vector (which generates no code for SSE). 4303 for (unsigned i = 0; i < NumElems; ++i) { 4304 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 4305 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4306 else 4307 V[i] = DAG.getUNDEF(VT); 4308 } 4309 4310 // Next, we iteratively mix elements, e.g. for v4f32: 4311 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 4312 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 4313 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 4314 unsigned EltStride = NumElems >> 1; 4315 while (EltStride != 0) { 4316 for (unsigned i = 0; i < EltStride; ++i) { 4317 // If V[i+EltStride] is undef and this is the first round of mixing, 4318 // then it is safe to just drop this shuffle: V[i] is already in the 4319 // right place, the one element (since it's the first round) being 4320 // inserted as undef can be dropped. This isn't safe for successive 4321 // rounds because they will permute elements within both vectors. 4322 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 4323 EltStride == NumElems/2) 4324 continue; 4325 4326 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 4327 } 4328 EltStride >>= 1; 4329 } 4330 return V[0]; 4331 } 4332 return SDValue(); 4333} 4334 4335SDValue 4336X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 4337 // We support concatenate two MMX registers and place them in a MMX 4338 // register. This is better than doing a stack convert. 4339 DebugLoc dl = Op.getDebugLoc(); 4340 EVT ResVT = Op.getValueType(); 4341 assert(Op.getNumOperands() == 2); 4342 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 4343 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 4344 int Mask[2]; 4345 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); 4346 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4347 InVec = Op.getOperand(1); 4348 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4349 unsigned NumElts = ResVT.getVectorNumElements(); 4350 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 4351 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 4352 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 4353 } else { 4354 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); 4355 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 4356 Mask[0] = 0; Mask[1] = 2; 4357 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 4358 } 4359 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 4360} 4361 4362// v8i16 shuffles - Prefer shuffles in the following order: 4363// 1. [all] pshuflw, pshufhw, optional move 4364// 2. [ssse3] 1 x pshufb 4365// 3. [ssse3] 2 x pshufb + 1 x por 4366// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 4367SDValue 4368X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 4369 SelectionDAG &DAG) const { 4370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4371 SDValue V1 = SVOp->getOperand(0); 4372 SDValue V2 = SVOp->getOperand(1); 4373 DebugLoc dl = SVOp->getDebugLoc(); 4374 SmallVector<int, 8> MaskVals; 4375 4376 // Determine if more than 1 of the words in each of the low and high quadwords 4377 // of the result come from the same quadword of one of the two inputs. Undef 4378 // mask values count as coming from any quadword, for better codegen. 4379 SmallVector<unsigned, 4> LoQuad(4); 4380 SmallVector<unsigned, 4> HiQuad(4); 4381 BitVector InputQuads(4); 4382 for (unsigned i = 0; i < 8; ++i) { 4383 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 4384 int EltIdx = SVOp->getMaskElt(i); 4385 MaskVals.push_back(EltIdx); 4386 if (EltIdx < 0) { 4387 ++Quad[0]; 4388 ++Quad[1]; 4389 ++Quad[2]; 4390 ++Quad[3]; 4391 continue; 4392 } 4393 ++Quad[EltIdx / 4]; 4394 InputQuads.set(EltIdx / 4); 4395 } 4396 4397 int BestLoQuad = -1; 4398 unsigned MaxQuad = 1; 4399 for (unsigned i = 0; i < 4; ++i) { 4400 if (LoQuad[i] > MaxQuad) { 4401 BestLoQuad = i; 4402 MaxQuad = LoQuad[i]; 4403 } 4404 } 4405 4406 int BestHiQuad = -1; 4407 MaxQuad = 1; 4408 for (unsigned i = 0; i < 4; ++i) { 4409 if (HiQuad[i] > MaxQuad) { 4410 BestHiQuad = i; 4411 MaxQuad = HiQuad[i]; 4412 } 4413 } 4414 4415 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 4416 // of the two input vectors, shuffle them into one input vector so only a 4417 // single pshufb instruction is necessary. If There are more than 2 input 4418 // quads, disable the next transformation since it does not help SSSE3. 4419 bool V1Used = InputQuads[0] || InputQuads[1]; 4420 bool V2Used = InputQuads[2] || InputQuads[3]; 4421 if (Subtarget->hasSSSE3()) { 4422 if (InputQuads.count() == 2 && V1Used && V2Used) { 4423 BestLoQuad = InputQuads.find_first(); 4424 BestHiQuad = InputQuads.find_next(BestLoQuad); 4425 } 4426 if (InputQuads.count() > 2) { 4427 BestLoQuad = -1; 4428 BestHiQuad = -1; 4429 } 4430 } 4431 4432 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 4433 // the shuffle mask. If a quad is scored as -1, that means that it contains 4434 // words from all 4 input quadwords. 4435 SDValue NewV; 4436 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 4437 SmallVector<int, 8> MaskV; 4438 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 4439 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 4440 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 4441 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 4442 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 4443 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 4444 4445 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 4446 // source words for the shuffle, to aid later transformations. 4447 bool AllWordsInNewV = true; 4448 bool InOrder[2] = { true, true }; 4449 for (unsigned i = 0; i != 8; ++i) { 4450 int idx = MaskVals[i]; 4451 if (idx != (int)i) 4452 InOrder[i/4] = false; 4453 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 4454 continue; 4455 AllWordsInNewV = false; 4456 break; 4457 } 4458 4459 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 4460 if (AllWordsInNewV) { 4461 for (int i = 0; i != 8; ++i) { 4462 int idx = MaskVals[i]; 4463 if (idx < 0) 4464 continue; 4465 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 4466 if ((idx != i) && idx < 4) 4467 pshufhw = false; 4468 if ((idx != i) && idx > 3) 4469 pshuflw = false; 4470 } 4471 V1 = NewV; 4472 V2Used = false; 4473 BestLoQuad = 0; 4474 BestHiQuad = 1; 4475 } 4476 4477 // If we've eliminated the use of V2, and the new mask is a pshuflw or 4478 // pshufhw, that's as cheap as it gets. Return the new shuffle. 4479 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 4480 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 4481 unsigned TargetMask = 0; 4482 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 4483 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 4484 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 4485 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 4486 V1 = NewV.getOperand(0); 4487 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 4488 } 4489 } 4490 4491 // If we have SSSE3, and all words of the result are from 1 input vector, 4492 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4493 // is present, fall back to case 4. 4494 if (Subtarget->hasSSSE3()) { 4495 SmallVector<SDValue,16> pshufbMask; 4496 4497 // If we have elements from both input vectors, set the high bit of the 4498 // shuffle mask element to zero out elements that come from V2 in the V1 4499 // mask, and elements that come from V1 in the V2 mask, so that the two 4500 // results can be OR'd together. 4501 bool TwoInputs = V1Used && V2Used; 4502 for (unsigned i = 0; i != 8; ++i) { 4503 int EltIdx = MaskVals[i] * 2; 4504 if (TwoInputs && (EltIdx >= 16)) { 4505 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4506 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4507 continue; 4508 } 4509 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4510 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4511 } 4512 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 4513 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4514 DAG.getNode(ISD::BUILD_VECTOR, dl, 4515 MVT::v16i8, &pshufbMask[0], 16)); 4516 if (!TwoInputs) 4517 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4518 4519 // Calculate the shuffle mask for the second input, shuffle it, and 4520 // OR it with the first shuffled input. 4521 pshufbMask.clear(); 4522 for (unsigned i = 0; i != 8; ++i) { 4523 int EltIdx = MaskVals[i] * 2; 4524 if (EltIdx < 16) { 4525 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4526 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4527 continue; 4528 } 4529 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4530 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4531 } 4532 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 4533 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4534 DAG.getNode(ISD::BUILD_VECTOR, dl, 4535 MVT::v16i8, &pshufbMask[0], 16)); 4536 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4537 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4538 } 4539 4540 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4541 // and update MaskVals with new element order. 4542 BitVector InOrder(8); 4543 if (BestLoQuad >= 0) { 4544 SmallVector<int, 8> MaskV; 4545 for (int i = 0; i != 4; ++i) { 4546 int idx = MaskVals[i]; 4547 if (idx < 0) { 4548 MaskV.push_back(-1); 4549 InOrder.set(i); 4550 } else if ((idx / 4) == BestLoQuad) { 4551 MaskV.push_back(idx & 3); 4552 InOrder.set(i); 4553 } else { 4554 MaskV.push_back(-1); 4555 } 4556 } 4557 for (unsigned i = 4; i != 8; ++i) 4558 MaskV.push_back(i); 4559 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4560 &MaskV[0]); 4561 4562 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 4563 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 4564 NewV.getOperand(0), 4565 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 4566 DAG); 4567 } 4568 4569 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4570 // and update MaskVals with the new element order. 4571 if (BestHiQuad >= 0) { 4572 SmallVector<int, 8> MaskV; 4573 for (unsigned i = 0; i != 4; ++i) 4574 MaskV.push_back(i); 4575 for (unsigned i = 4; i != 8; ++i) { 4576 int idx = MaskVals[i]; 4577 if (idx < 0) { 4578 MaskV.push_back(-1); 4579 InOrder.set(i); 4580 } else if ((idx / 4) == BestHiQuad) { 4581 MaskV.push_back((idx & 3) + 4); 4582 InOrder.set(i); 4583 } else { 4584 MaskV.push_back(-1); 4585 } 4586 } 4587 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4588 &MaskV[0]); 4589 4590 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 4591 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 4592 NewV.getOperand(0), 4593 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 4594 DAG); 4595 } 4596 4597 // In case BestHi & BestLo were both -1, which means each quadword has a word 4598 // from each of the four input quadwords, calculate the InOrder bitvector now 4599 // before falling through to the insert/extract cleanup. 4600 if (BestLoQuad == -1 && BestHiQuad == -1) { 4601 NewV = V1; 4602 for (int i = 0; i != 8; ++i) 4603 if (MaskVals[i] < 0 || MaskVals[i] == i) 4604 InOrder.set(i); 4605 } 4606 4607 // The other elements are put in the right place using pextrw and pinsrw. 4608 for (unsigned i = 0; i != 8; ++i) { 4609 if (InOrder[i]) 4610 continue; 4611 int EltIdx = MaskVals[i]; 4612 if (EltIdx < 0) 4613 continue; 4614 SDValue ExtOp = (EltIdx < 8) 4615 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4616 DAG.getIntPtrConstant(EltIdx)) 4617 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4618 DAG.getIntPtrConstant(EltIdx - 8)); 4619 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4620 DAG.getIntPtrConstant(i)); 4621 } 4622 return NewV; 4623} 4624 4625// v16i8 shuffles - Prefer shuffles in the following order: 4626// 1. [ssse3] 1 x pshufb 4627// 2. [ssse3] 2 x pshufb + 1 x por 4628// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4629static 4630SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4631 SelectionDAG &DAG, 4632 const X86TargetLowering &TLI) { 4633 SDValue V1 = SVOp->getOperand(0); 4634 SDValue V2 = SVOp->getOperand(1); 4635 DebugLoc dl = SVOp->getDebugLoc(); 4636 SmallVector<int, 16> MaskVals; 4637 SVOp->getMask(MaskVals); 4638 4639 // If we have SSSE3, case 1 is generated when all result bytes come from 4640 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4641 // present, fall back to case 3. 4642 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4643 bool V1Only = true; 4644 bool V2Only = true; 4645 for (unsigned i = 0; i < 16; ++i) { 4646 int EltIdx = MaskVals[i]; 4647 if (EltIdx < 0) 4648 continue; 4649 if (EltIdx < 16) 4650 V2Only = false; 4651 else 4652 V1Only = false; 4653 } 4654 4655 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4656 if (TLI.getSubtarget()->hasSSSE3()) { 4657 SmallVector<SDValue,16> pshufbMask; 4658 4659 // If all result elements are from one input vector, then only translate 4660 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4661 // 4662 // Otherwise, we have elements from both input vectors, and must zero out 4663 // elements that come from V2 in the first mask, and V1 in the second mask 4664 // so that we can OR them together. 4665 bool TwoInputs = !(V1Only || V2Only); 4666 for (unsigned i = 0; i != 16; ++i) { 4667 int EltIdx = MaskVals[i]; 4668 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4669 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4670 continue; 4671 } 4672 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4673 } 4674 // If all the elements are from V2, assign it to V1 and return after 4675 // building the first pshufb. 4676 if (V2Only) 4677 V1 = V2; 4678 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4679 DAG.getNode(ISD::BUILD_VECTOR, dl, 4680 MVT::v16i8, &pshufbMask[0], 16)); 4681 if (!TwoInputs) 4682 return V1; 4683 4684 // Calculate the shuffle mask for the second input, shuffle it, and 4685 // OR it with the first shuffled input. 4686 pshufbMask.clear(); 4687 for (unsigned i = 0; i != 16; ++i) { 4688 int EltIdx = MaskVals[i]; 4689 if (EltIdx < 16) { 4690 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4691 continue; 4692 } 4693 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4694 } 4695 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4696 DAG.getNode(ISD::BUILD_VECTOR, dl, 4697 MVT::v16i8, &pshufbMask[0], 16)); 4698 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4699 } 4700 4701 // No SSSE3 - Calculate in place words and then fix all out of place words 4702 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4703 // the 16 different words that comprise the two doublequadword input vectors. 4704 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4705 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 4706 SDValue NewV = V2Only ? V2 : V1; 4707 for (int i = 0; i != 8; ++i) { 4708 int Elt0 = MaskVals[i*2]; 4709 int Elt1 = MaskVals[i*2+1]; 4710 4711 // This word of the result is all undef, skip it. 4712 if (Elt0 < 0 && Elt1 < 0) 4713 continue; 4714 4715 // This word of the result is already in the correct place, skip it. 4716 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4717 continue; 4718 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4719 continue; 4720 4721 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4722 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4723 SDValue InsElt; 4724 4725 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4726 // using a single extract together, load it and store it. 4727 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4728 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4729 DAG.getIntPtrConstant(Elt1 / 2)); 4730 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4731 DAG.getIntPtrConstant(i)); 4732 continue; 4733 } 4734 4735 // If Elt1 is defined, extract it from the appropriate source. If the 4736 // source byte is not also odd, shift the extracted word left 8 bits 4737 // otherwise clear the bottom 8 bits if we need to do an or. 4738 if (Elt1 >= 0) { 4739 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4740 DAG.getIntPtrConstant(Elt1 / 2)); 4741 if ((Elt1 & 1) == 0) 4742 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4743 DAG.getConstant(8, TLI.getShiftAmountTy())); 4744 else if (Elt0 >= 0) 4745 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4746 DAG.getConstant(0xFF00, MVT::i16)); 4747 } 4748 // If Elt0 is defined, extract it from the appropriate source. If the 4749 // source byte is not also even, shift the extracted word right 8 bits. If 4750 // Elt1 was also defined, OR the extracted values together before 4751 // inserting them in the result. 4752 if (Elt0 >= 0) { 4753 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4754 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4755 if ((Elt0 & 1) != 0) 4756 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4757 DAG.getConstant(8, TLI.getShiftAmountTy())); 4758 else if (Elt1 >= 0) 4759 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4760 DAG.getConstant(0x00FF, MVT::i16)); 4761 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4762 : InsElt0; 4763 } 4764 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4765 DAG.getIntPtrConstant(i)); 4766 } 4767 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 4768} 4769 4770/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4771/// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be 4772/// done when every pair / quad of shuffle mask elements point to elements in 4773/// the right sequence. e.g. 4774/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 4775static 4776SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4777 SelectionDAG &DAG, 4778 const TargetLowering &TLI, DebugLoc dl) { 4779 EVT VT = SVOp->getValueType(0); 4780 SDValue V1 = SVOp->getOperand(0); 4781 SDValue V2 = SVOp->getOperand(1); 4782 unsigned NumElems = VT.getVectorNumElements(); 4783 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4784 EVT MaskVT = (NewWidth == 4) ? MVT::v4i16 : MVT::v2i32; 4785 EVT NewVT = MaskVT; 4786 switch (VT.getSimpleVT().SimpleTy) { 4787 default: assert(false && "Unexpected!"); 4788 case MVT::v4f32: NewVT = MVT::v2f64; break; 4789 case MVT::v4i32: NewVT = MVT::v2i64; break; 4790 case MVT::v8i16: NewVT = MVT::v4i32; break; 4791 case MVT::v16i8: NewVT = MVT::v4i32; break; 4792 } 4793 4794 if (NewWidth == 2) { 4795 if (VT.isInteger()) 4796 NewVT = MVT::v2i64; 4797 else 4798 NewVT = MVT::v2f64; 4799 } 4800 int Scale = NumElems / NewWidth; 4801 SmallVector<int, 8> MaskVec; 4802 for (unsigned i = 0; i < NumElems; i += Scale) { 4803 int StartIdx = -1; 4804 for (int j = 0; j < Scale; ++j) { 4805 int EltIdx = SVOp->getMaskElt(i+j); 4806 if (EltIdx < 0) 4807 continue; 4808 if (StartIdx == -1) 4809 StartIdx = EltIdx - (EltIdx % Scale); 4810 if (EltIdx != StartIdx + j) 4811 return SDValue(); 4812 } 4813 if (StartIdx == -1) 4814 MaskVec.push_back(-1); 4815 else 4816 MaskVec.push_back(StartIdx / Scale); 4817 } 4818 4819 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 4820 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 4821 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4822} 4823 4824/// getVZextMovL - Return a zero-extending vector move low node. 4825/// 4826static SDValue getVZextMovL(EVT VT, EVT OpVT, 4827 SDValue SrcOp, SelectionDAG &DAG, 4828 const X86Subtarget *Subtarget, DebugLoc dl) { 4829 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4830 LoadSDNode *LD = NULL; 4831 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4832 LD = dyn_cast<LoadSDNode>(SrcOp); 4833 if (!LD) { 4834 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4835 // instead. 4836 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4837 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 4838 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4839 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4840 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4841 // PR2108 4842 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4843 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4844 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4845 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4846 OpVT, 4847 SrcOp.getOperand(0) 4848 .getOperand(0)))); 4849 } 4850 } 4851 } 4852 4853 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4854 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4855 DAG.getNode(ISD::BIT_CONVERT, dl, 4856 OpVT, SrcOp))); 4857} 4858 4859/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4860/// shuffles. 4861static SDValue 4862LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4863 SDValue V1 = SVOp->getOperand(0); 4864 SDValue V2 = SVOp->getOperand(1); 4865 DebugLoc dl = SVOp->getDebugLoc(); 4866 EVT VT = SVOp->getValueType(0); 4867 4868 SmallVector<std::pair<int, int>, 8> Locs; 4869 Locs.resize(4); 4870 SmallVector<int, 8> Mask1(4U, -1); 4871 SmallVector<int, 8> PermMask; 4872 SVOp->getMask(PermMask); 4873 4874 unsigned NumHi = 0; 4875 unsigned NumLo = 0; 4876 for (unsigned i = 0; i != 4; ++i) { 4877 int Idx = PermMask[i]; 4878 if (Idx < 0) { 4879 Locs[i] = std::make_pair(-1, -1); 4880 } else { 4881 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4882 if (Idx < 4) { 4883 Locs[i] = std::make_pair(0, NumLo); 4884 Mask1[NumLo] = Idx; 4885 NumLo++; 4886 } else { 4887 Locs[i] = std::make_pair(1, NumHi); 4888 if (2+NumHi < 4) 4889 Mask1[2+NumHi] = Idx; 4890 NumHi++; 4891 } 4892 } 4893 } 4894 4895 if (NumLo <= 2 && NumHi <= 2) { 4896 // If no more than two elements come from either vector. This can be 4897 // implemented with two shuffles. First shuffle gather the elements. 4898 // The second shuffle, which takes the first shuffle as both of its 4899 // vector operands, put the elements into the right order. 4900 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4901 4902 SmallVector<int, 8> Mask2(4U, -1); 4903 4904 for (unsigned i = 0; i != 4; ++i) { 4905 if (Locs[i].first == -1) 4906 continue; 4907 else { 4908 unsigned Idx = (i < 2) ? 0 : 4; 4909 Idx += Locs[i].first * 2 + Locs[i].second; 4910 Mask2[i] = Idx; 4911 } 4912 } 4913 4914 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4915 } else if (NumLo == 3 || NumHi == 3) { 4916 // Otherwise, we must have three elements from one vector, call it X, and 4917 // one element from the other, call it Y. First, use a shufps to build an 4918 // intermediate vector with the one element from Y and the element from X 4919 // that will be in the same half in the final destination (the indexes don't 4920 // matter). Then, use a shufps to build the final vector, taking the half 4921 // containing the element from Y from the intermediate, and the other half 4922 // from X. 4923 if (NumHi == 3) { 4924 // Normalize it so the 3 elements come from V1. 4925 CommuteVectorShuffleMask(PermMask, VT); 4926 std::swap(V1, V2); 4927 } 4928 4929 // Find the element from V2. 4930 unsigned HiIndex; 4931 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4932 int Val = PermMask[HiIndex]; 4933 if (Val < 0) 4934 continue; 4935 if (Val >= 4) 4936 break; 4937 } 4938 4939 Mask1[0] = PermMask[HiIndex]; 4940 Mask1[1] = -1; 4941 Mask1[2] = PermMask[HiIndex^1]; 4942 Mask1[3] = -1; 4943 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4944 4945 if (HiIndex >= 2) { 4946 Mask1[0] = PermMask[0]; 4947 Mask1[1] = PermMask[1]; 4948 Mask1[2] = HiIndex & 1 ? 6 : 4; 4949 Mask1[3] = HiIndex & 1 ? 4 : 6; 4950 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4951 } else { 4952 Mask1[0] = HiIndex & 1 ? 2 : 0; 4953 Mask1[1] = HiIndex & 1 ? 0 : 2; 4954 Mask1[2] = PermMask[2]; 4955 Mask1[3] = PermMask[3]; 4956 if (Mask1[2] >= 0) 4957 Mask1[2] += 4; 4958 if (Mask1[3] >= 0) 4959 Mask1[3] += 4; 4960 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4961 } 4962 } 4963 4964 // Break it into (shuffle shuffle_hi, shuffle_lo). 4965 Locs.clear(); 4966 SmallVector<int,8> LoMask(4U, -1); 4967 SmallVector<int,8> HiMask(4U, -1); 4968 4969 SmallVector<int,8> *MaskPtr = &LoMask; 4970 unsigned MaskIdx = 0; 4971 unsigned LoIdx = 0; 4972 unsigned HiIdx = 2; 4973 for (unsigned i = 0; i != 4; ++i) { 4974 if (i == 2) { 4975 MaskPtr = &HiMask; 4976 MaskIdx = 1; 4977 LoIdx = 0; 4978 HiIdx = 2; 4979 } 4980 int Idx = PermMask[i]; 4981 if (Idx < 0) { 4982 Locs[i] = std::make_pair(-1, -1); 4983 } else if (Idx < 4) { 4984 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4985 (*MaskPtr)[LoIdx] = Idx; 4986 LoIdx++; 4987 } else { 4988 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4989 (*MaskPtr)[HiIdx] = Idx; 4990 HiIdx++; 4991 } 4992 } 4993 4994 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4995 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4996 SmallVector<int, 8> MaskOps; 4997 for (unsigned i = 0; i != 4; ++i) { 4998 if (Locs[i].first == -1) { 4999 MaskOps.push_back(-1); 5000 } else { 5001 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 5002 MaskOps.push_back(Idx); 5003 } 5004 } 5005 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 5006} 5007 5008static 5009SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 5010 bool HasSSE2) { 5011 SDValue V1 = Op.getOperand(0); 5012 SDValue V2 = Op.getOperand(1); 5013 EVT VT = Op.getValueType(); 5014 5015 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 5016 5017 if (HasSSE2 && VT == MVT::v2f64) 5018 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 5019 5020 // v4f32 or v4i32 5021 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); 5022} 5023 5024SDValue 5025X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 5026 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5027 SDValue V1 = Op.getOperand(0); 5028 SDValue V2 = Op.getOperand(1); 5029 EVT VT = Op.getValueType(); 5030 DebugLoc dl = Op.getDebugLoc(); 5031 unsigned NumElems = VT.getVectorNumElements(); 5032 bool isMMX = VT.getSizeInBits() == 64; 5033 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 5034 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 5035 bool V1IsSplat = false; 5036 bool V2IsSplat = false; 5037 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); 5038 MachineFunction &MF = DAG.getMachineFunction(); 5039 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 5040 5041 if (isZeroShuffle(SVOp)) 5042 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 5043 5044 // Promote splats to v4f32. 5045 if (SVOp->isSplat()) { 5046 if (isMMX || NumElems < 4) 5047 return Op; 5048 return PromoteSplat(SVOp, DAG); 5049 } 5050 5051 // If the shuffle can be profitably rewritten as a narrower shuffle, then 5052 // do it! 5053 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 5054 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 5055 if (NewOp.getNode()) 5056 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5057 LowerVECTOR_SHUFFLE(NewOp, DAG)); 5058 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 5059 // FIXME: Figure out a cleaner way to do this. 5060 // Try to make use of movq to zero out the top part. 5061 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 5062 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 5063 if (NewOp.getNode()) { 5064 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 5065 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 5066 DAG, Subtarget, dl); 5067 } 5068 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 5069 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 5070 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 5071 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 5072 DAG, Subtarget, dl); 5073 } 5074 } 5075 5076 if (X86::isPSHUFDMask(SVOp)) { 5077 // The actual implementation will match the mask in the if above and then 5078 // during isel it can match several different instructions, not only pshufd 5079 // as its name says, sad but true, emulate the behavior for now... 5080 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 5081 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 5082 5083 if (OptForSize && HasSSE2 && X86::isUNPCKL_v_undef_Mask(SVOp) && 5084 VT == MVT::v4i32) 5085 return getTargetShuffleNode(X86ISD::PUNPCKLDQ, dl, VT, V1, V1, DAG); 5086 5087 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 5088 5089 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 5090 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 5091 5092 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 5093 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, 5094 TargetMask, DAG); 5095 5096 if (VT == MVT::v4f32) 5097 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1, 5098 TargetMask, DAG); 5099 } 5100 5101 // Check if this can be converted into a logical shift. 5102 bool isLeft = false; 5103 unsigned ShAmt = 0; 5104 SDValue ShVal; 5105 bool isShift = getSubtarget()->hasSSE2() && 5106 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 5107 if (isShift && ShVal.hasOneUse()) { 5108 // If the shifted value has multiple uses, it may be cheaper to use 5109 // v_set0 + movlhps or movhlps, etc. 5110 EVT EltVT = VT.getVectorElementType(); 5111 ShAmt *= EltVT.getSizeInBits(); 5112 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 5113 } 5114 5115 if (X86::isMOVLMask(SVOp)) { 5116 if (V1IsUndef) 5117 return V2; 5118 if (ISD::isBuildVectorAllZeros(V1.getNode())) 5119 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 5120 if (!isMMX && !X86::isMOVLPMask(SVOp)) { 5121 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 5122 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5123 5124 if (VT == MVT::v4i32 || VT == MVT::v4f32) 5125 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5126 } 5127 } 5128 5129 // FIXME: fold these into legal mask. 5130 if (!isMMX) { 5131 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 5132 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 5133 5134 if (X86::isMOVSHDUPMask(SVOp) || 5135 X86::isMOVSLDUPMask(SVOp) || 5136 X86::isMOVHLPSMask(SVOp) || 5137 X86::isMOVLPMask(SVOp)) 5138 return Op; 5139 } 5140 5141 if (ShouldXformToMOVHLPS(SVOp) || 5142 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 5143 return CommuteVectorShuffle(SVOp, DAG); 5144 5145 if (isShift) { 5146 // No better options. Use a vshl / vsrl. 5147 EVT EltVT = VT.getVectorElementType(); 5148 ShAmt *= EltVT.getSizeInBits(); 5149 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 5150 } 5151 5152 bool Commuted = false; 5153 // FIXME: This should also accept a bitcast of a splat? Be careful, not 5154 // 1,1,1,1 -> v8i16 though. 5155 V1IsSplat = isSplatVector(V1.getNode()); 5156 V2IsSplat = isSplatVector(V2.getNode()); 5157 5158 // Canonicalize the splat or undef, if present, to be on the RHS. 5159 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 5160 Op = CommuteVectorShuffle(SVOp, DAG); 5161 SVOp = cast<ShuffleVectorSDNode>(Op); 5162 V1 = SVOp->getOperand(0); 5163 V2 = SVOp->getOperand(1); 5164 std::swap(V1IsSplat, V2IsSplat); 5165 std::swap(V1IsUndef, V2IsUndef); 5166 Commuted = true; 5167 } 5168 5169 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 5170 // Shuffling low element of v1 into undef, just return v1. 5171 if (V2IsUndef) 5172 return V1; 5173 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 5174 // the instruction selector will not match, so get a canonical MOVL with 5175 // swapped operands to undo the commute. 5176 return getMOVL(DAG, dl, VT, V2, V1); 5177 } 5178 5179 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 5180 X86::isUNPCKH_v_undef_Mask(SVOp) || 5181 X86::isUNPCKLMask(SVOp) || 5182 X86::isUNPCKHMask(SVOp)) 5183 return Op; 5184 5185 if (V2IsSplat) { 5186 // Normalize mask so all entries that point to V2 points to its first 5187 // element then try to match unpck{h|l} again. If match, return a 5188 // new vector_shuffle with the corrected mask. 5189 SDValue NewMask = NormalizeMask(SVOp, DAG); 5190 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 5191 if (NSVOp != SVOp) { 5192 if (X86::isUNPCKLMask(NSVOp, true)) { 5193 return NewMask; 5194 } else if (X86::isUNPCKHMask(NSVOp, true)) { 5195 return NewMask; 5196 } 5197 } 5198 } 5199 5200 if (Commuted) { 5201 // Commute is back and try unpck* again. 5202 // FIXME: this seems wrong. 5203 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 5204 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 5205 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 5206 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 5207 X86::isUNPCKLMask(NewSVOp) || 5208 X86::isUNPCKHMask(NewSVOp)) 5209 return NewOp; 5210 } 5211 5212 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 5213 5214 // Normalize the node to match x86 shuffle ops if needed 5215 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 5216 return CommuteVectorShuffle(SVOp, DAG); 5217 5218 // Check for legal shuffle and return? 5219 SmallVector<int, 16> PermMask; 5220 SVOp->getMask(PermMask); 5221 if (isShuffleMaskLegal(PermMask, VT)) 5222 return Op; 5223 5224 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 5225 if (VT == MVT::v8i16) { 5226 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 5227 if (NewOp.getNode()) 5228 return NewOp; 5229 } 5230 5231 if (VT == MVT::v16i8) { 5232 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 5233 if (NewOp.getNode()) 5234 return NewOp; 5235 } 5236 5237 // Handle all 4 wide cases with a number of shuffles except for MMX. 5238 if (NumElems == 4 && !isMMX) 5239 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 5240 5241 return SDValue(); 5242} 5243 5244SDValue 5245X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 5246 SelectionDAG &DAG) const { 5247 EVT VT = Op.getValueType(); 5248 DebugLoc dl = Op.getDebugLoc(); 5249 if (VT.getSizeInBits() == 8) { 5250 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 5251 Op.getOperand(0), Op.getOperand(1)); 5252 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 5253 DAG.getValueType(VT)); 5254 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5255 } else if (VT.getSizeInBits() == 16) { 5256 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5257 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 5258 if (Idx == 0) 5259 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 5260 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5261 DAG.getNode(ISD::BIT_CONVERT, dl, 5262 MVT::v4i32, 5263 Op.getOperand(0)), 5264 Op.getOperand(1))); 5265 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 5266 Op.getOperand(0), Op.getOperand(1)); 5267 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 5268 DAG.getValueType(VT)); 5269 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5270 } else if (VT == MVT::f32) { 5271 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 5272 // the result back to FR32 register. It's only worth matching if the 5273 // result has a single use which is a store or a bitcast to i32. And in 5274 // the case of a store, it's not worth it if the index is a constant 0, 5275 // because a MOVSSmr can be used instead, which is smaller and faster. 5276 if (!Op.hasOneUse()) 5277 return SDValue(); 5278 SDNode *User = *Op.getNode()->use_begin(); 5279 if ((User->getOpcode() != ISD::STORE || 5280 (isa<ConstantSDNode>(Op.getOperand(1)) && 5281 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 5282 (User->getOpcode() != ISD::BIT_CONVERT || 5283 User->getValueType(0) != MVT::i32)) 5284 return SDValue(); 5285 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5286 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 5287 Op.getOperand(0)), 5288 Op.getOperand(1)); 5289 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 5290 } else if (VT == MVT::i32) { 5291 // ExtractPS works with constant index. 5292 if (isa<ConstantSDNode>(Op.getOperand(1))) 5293 return Op; 5294 } 5295 return SDValue(); 5296} 5297 5298 5299SDValue 5300X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 5301 SelectionDAG &DAG) const { 5302 if (!isa<ConstantSDNode>(Op.getOperand(1))) 5303 return SDValue(); 5304 5305 if (Subtarget->hasSSE41()) { 5306 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 5307 if (Res.getNode()) 5308 return Res; 5309 } 5310 5311 EVT VT = Op.getValueType(); 5312 DebugLoc dl = Op.getDebugLoc(); 5313 // TODO: handle v16i8. 5314 if (VT.getSizeInBits() == 16) { 5315 SDValue Vec = Op.getOperand(0); 5316 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5317 if (Idx == 0) 5318 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 5319 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 5320 DAG.getNode(ISD::BIT_CONVERT, dl, 5321 MVT::v4i32, Vec), 5322 Op.getOperand(1))); 5323 // Transform it so it match pextrw which produces a 32-bit result. 5324 EVT EltVT = MVT::i32; 5325 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 5326 Op.getOperand(0), Op.getOperand(1)); 5327 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 5328 DAG.getValueType(VT)); 5329 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 5330 } else if (VT.getSizeInBits() == 32) { 5331 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5332 if (Idx == 0) 5333 return Op; 5334 5335 // SHUFPS the element to the lowest double word, then movss. 5336 int Mask[4] = { Idx, -1, -1, -1 }; 5337 EVT VVT = Op.getOperand(0).getValueType(); 5338 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 5339 DAG.getUNDEF(VVT), Mask); 5340 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 5341 DAG.getIntPtrConstant(0)); 5342 } else if (VT.getSizeInBits() == 64) { 5343 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 5344 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 5345 // to match extract_elt for f64. 5346 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 5347 if (Idx == 0) 5348 return Op; 5349 5350 // UNPCKHPD the element to the lowest double word, then movsd. 5351 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 5352 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 5353 int Mask[2] = { 1, -1 }; 5354 EVT VVT = Op.getOperand(0).getValueType(); 5355 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 5356 DAG.getUNDEF(VVT), Mask); 5357 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 5358 DAG.getIntPtrConstant(0)); 5359 } 5360 5361 return SDValue(); 5362} 5363 5364SDValue 5365X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 5366 SelectionDAG &DAG) const { 5367 EVT VT = Op.getValueType(); 5368 EVT EltVT = VT.getVectorElementType(); 5369 DebugLoc dl = Op.getDebugLoc(); 5370 5371 SDValue N0 = Op.getOperand(0); 5372 SDValue N1 = Op.getOperand(1); 5373 SDValue N2 = Op.getOperand(2); 5374 5375 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 5376 isa<ConstantSDNode>(N2)) { 5377 unsigned Opc; 5378 if (VT == MVT::v8i16) 5379 Opc = X86ISD::PINSRW; 5380 else if (VT == MVT::v4i16) 5381 Opc = X86ISD::MMX_PINSRW; 5382 else if (VT == MVT::v16i8) 5383 Opc = X86ISD::PINSRB; 5384 else 5385 Opc = X86ISD::PINSRB; 5386 5387 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 5388 // argument. 5389 if (N1.getValueType() != MVT::i32) 5390 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 5391 if (N2.getValueType() != MVT::i32) 5392 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5393 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 5394 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 5395 // Bits [7:6] of the constant are the source select. This will always be 5396 // zero here. The DAG Combiner may combine an extract_elt index into these 5397 // bits. For example (insert (extract, 3), 2) could be matched by putting 5398 // the '3' into bits [7:6] of X86ISD::INSERTPS. 5399 // Bits [5:4] of the constant are the destination select. This is the 5400 // value of the incoming immediate. 5401 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 5402 // combine either bitwise AND or insert of float 0.0 to set these bits. 5403 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 5404 // Create this as a scalar to vector.. 5405 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 5406 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 5407 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 5408 // PINSR* works with constant index. 5409 return Op; 5410 } 5411 return SDValue(); 5412} 5413 5414SDValue 5415X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 5416 EVT VT = Op.getValueType(); 5417 EVT EltVT = VT.getVectorElementType(); 5418 5419 if (Subtarget->hasSSE41()) 5420 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 5421 5422 if (EltVT == MVT::i8) 5423 return SDValue(); 5424 5425 DebugLoc dl = Op.getDebugLoc(); 5426 SDValue N0 = Op.getOperand(0); 5427 SDValue N1 = Op.getOperand(1); 5428 SDValue N2 = Op.getOperand(2); 5429 5430 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 5431 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 5432 // as its second argument. 5433 if (N1.getValueType() != MVT::i32) 5434 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 5435 if (N2.getValueType() != MVT::i32) 5436 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5437 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW, 5438 dl, VT, N0, N1, N2); 5439 } 5440 return SDValue(); 5441} 5442 5443SDValue 5444X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5445 DebugLoc dl = Op.getDebugLoc(); 5446 5447 if (Op.getValueType() == MVT::v1i64 && 5448 Op.getOperand(0).getValueType() == MVT::i64) 5449 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 5450 5451 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 5452 EVT VT = MVT::v2i32; 5453 switch (Op.getValueType().getSimpleVT().SimpleTy) { 5454 default: break; 5455 case MVT::v16i8: 5456 case MVT::v8i16: 5457 VT = MVT::v4i32; 5458 break; 5459 } 5460 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 5461 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 5462} 5463 5464// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 5465// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 5466// one of the above mentioned nodes. It has to be wrapped because otherwise 5467// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 5468// be used to form addressing mode. These wrapped nodes will be selected 5469// into MOV32ri. 5470SDValue 5471X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 5472 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 5473 5474 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5475 // global base reg. 5476 unsigned char OpFlag = 0; 5477 unsigned WrapperKind = X86ISD::Wrapper; 5478 CodeModel::Model M = getTargetMachine().getCodeModel(); 5479 5480 if (Subtarget->isPICStyleRIPRel() && 5481 (M == CodeModel::Small || M == CodeModel::Kernel)) 5482 WrapperKind = X86ISD::WrapperRIP; 5483 else if (Subtarget->isPICStyleGOT()) 5484 OpFlag = X86II::MO_GOTOFF; 5485 else if (Subtarget->isPICStyleStubPIC()) 5486 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5487 5488 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 5489 CP->getAlignment(), 5490 CP->getOffset(), OpFlag); 5491 DebugLoc DL = CP->getDebugLoc(); 5492 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5493 // With PIC, the address is actually $g + Offset. 5494 if (OpFlag) { 5495 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5496 DAG.getNode(X86ISD::GlobalBaseReg, 5497 DebugLoc(), getPointerTy()), 5498 Result); 5499 } 5500 5501 return Result; 5502} 5503 5504SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 5505 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 5506 5507 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5508 // global base reg. 5509 unsigned char OpFlag = 0; 5510 unsigned WrapperKind = X86ISD::Wrapper; 5511 CodeModel::Model M = getTargetMachine().getCodeModel(); 5512 5513 if (Subtarget->isPICStyleRIPRel() && 5514 (M == CodeModel::Small || M == CodeModel::Kernel)) 5515 WrapperKind = X86ISD::WrapperRIP; 5516 else if (Subtarget->isPICStyleGOT()) 5517 OpFlag = X86II::MO_GOTOFF; 5518 else if (Subtarget->isPICStyleStubPIC()) 5519 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5520 5521 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 5522 OpFlag); 5523 DebugLoc DL = JT->getDebugLoc(); 5524 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5525 5526 // With PIC, the address is actually $g + Offset. 5527 if (OpFlag) { 5528 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5529 DAG.getNode(X86ISD::GlobalBaseReg, 5530 DebugLoc(), getPointerTy()), 5531 Result); 5532 } 5533 5534 return Result; 5535} 5536 5537SDValue 5538X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 5539 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 5540 5541 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5542 // global base reg. 5543 unsigned char OpFlag = 0; 5544 unsigned WrapperKind = X86ISD::Wrapper; 5545 CodeModel::Model M = getTargetMachine().getCodeModel(); 5546 5547 if (Subtarget->isPICStyleRIPRel() && 5548 (M == CodeModel::Small || M == CodeModel::Kernel)) 5549 WrapperKind = X86ISD::WrapperRIP; 5550 else if (Subtarget->isPICStyleGOT()) 5551 OpFlag = X86II::MO_GOTOFF; 5552 else if (Subtarget->isPICStyleStubPIC()) 5553 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5554 5555 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 5556 5557 DebugLoc DL = Op.getDebugLoc(); 5558 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5559 5560 5561 // With PIC, the address is actually $g + Offset. 5562 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 5563 !Subtarget->is64Bit()) { 5564 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5565 DAG.getNode(X86ISD::GlobalBaseReg, 5566 DebugLoc(), getPointerTy()), 5567 Result); 5568 } 5569 5570 return Result; 5571} 5572 5573SDValue 5574X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 5575 // Create the TargetBlockAddressAddress node. 5576 unsigned char OpFlags = 5577 Subtarget->ClassifyBlockAddressReference(); 5578 CodeModel::Model M = getTargetMachine().getCodeModel(); 5579 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5580 DebugLoc dl = Op.getDebugLoc(); 5581 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5582 /*isTarget=*/true, OpFlags); 5583 5584 if (Subtarget->isPICStyleRIPRel() && 5585 (M == CodeModel::Small || M == CodeModel::Kernel)) 5586 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5587 else 5588 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5589 5590 // With PIC, the address is actually $g + Offset. 5591 if (isGlobalRelativeToPICBase(OpFlags)) { 5592 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5593 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5594 Result); 5595 } 5596 5597 return Result; 5598} 5599 5600SDValue 5601X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5602 int64_t Offset, 5603 SelectionDAG &DAG) const { 5604 // Create the TargetGlobalAddress node, folding in the constant 5605 // offset if it is legal. 5606 unsigned char OpFlags = 5607 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5608 CodeModel::Model M = getTargetMachine().getCodeModel(); 5609 SDValue Result; 5610 if (OpFlags == X86II::MO_NO_FLAG && 5611 X86::isOffsetSuitableForCodeModel(Offset, M)) { 5612 // A direct static reference to a global. 5613 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 5614 Offset = 0; 5615 } else { 5616 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 5617 } 5618 5619 if (Subtarget->isPICStyleRIPRel() && 5620 (M == CodeModel::Small || M == CodeModel::Kernel)) 5621 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5622 else 5623 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5624 5625 // With PIC, the address is actually $g + Offset. 5626 if (isGlobalRelativeToPICBase(OpFlags)) { 5627 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5628 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5629 Result); 5630 } 5631 5632 // For globals that require a load from a stub to get the address, emit the 5633 // load. 5634 if (isGlobalStubReference(OpFlags)) 5635 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 5636 PseudoSourceValue::getGOT(), 0, false, false, 0); 5637 5638 // If there was a non-zero offset that we didn't fold, create an explicit 5639 // addition for it. 5640 if (Offset != 0) 5641 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 5642 DAG.getConstant(Offset, getPointerTy())); 5643 5644 return Result; 5645} 5646 5647SDValue 5648X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 5649 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 5650 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 5651 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 5652} 5653 5654static SDValue 5655GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 5656 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 5657 unsigned char OperandFlags) { 5658 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5659 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5660 DebugLoc dl = GA->getDebugLoc(); 5661 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 5662 GA->getValueType(0), 5663 GA->getOffset(), 5664 OperandFlags); 5665 if (InFlag) { 5666 SDValue Ops[] = { Chain, TGA, *InFlag }; 5667 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 5668 } else { 5669 SDValue Ops[] = { Chain, TGA }; 5670 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 5671 } 5672 5673 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 5674 MFI->setAdjustsStack(true); 5675 5676 SDValue Flag = Chain.getValue(1); 5677 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 5678} 5679 5680// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 5681static SDValue 5682LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5683 const EVT PtrVT) { 5684 SDValue InFlag; 5685 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 5686 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 5687 DAG.getNode(X86ISD::GlobalBaseReg, 5688 DebugLoc(), PtrVT), InFlag); 5689 InFlag = Chain.getValue(1); 5690 5691 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 5692} 5693 5694// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 5695static SDValue 5696LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5697 const EVT PtrVT) { 5698 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 5699 X86::RAX, X86II::MO_TLSGD); 5700} 5701 5702// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 5703// "local exec" model. 5704static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5705 const EVT PtrVT, TLSModel::Model model, 5706 bool is64Bit) { 5707 DebugLoc dl = GA->getDebugLoc(); 5708 // Get the Thread Pointer 5709 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 5710 DebugLoc(), PtrVT, 5711 DAG.getRegister(is64Bit? X86::FS : X86::GS, 5712 MVT::i32)); 5713 5714 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 5715 NULL, 0, false, false, 0); 5716 5717 unsigned char OperandFlags = 0; 5718 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 5719 // initialexec. 5720 unsigned WrapperKind = X86ISD::Wrapper; 5721 if (model == TLSModel::LocalExec) { 5722 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 5723 } else if (is64Bit) { 5724 assert(model == TLSModel::InitialExec); 5725 OperandFlags = X86II::MO_GOTTPOFF; 5726 WrapperKind = X86ISD::WrapperRIP; 5727 } else { 5728 assert(model == TLSModel::InitialExec); 5729 OperandFlags = X86II::MO_INDNTPOFF; 5730 } 5731 5732 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 5733 // exec) 5734 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 5735 GA->getValueType(0), 5736 GA->getOffset(), OperandFlags); 5737 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 5738 5739 if (model == TLSModel::InitialExec) 5740 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 5741 PseudoSourceValue::getGOT(), 0, false, false, 0); 5742 5743 // The address of the thread local variable is the add of the thread 5744 // pointer with the offset of the variable. 5745 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 5746} 5747 5748SDValue 5749X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 5750 5751 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 5752 const GlobalValue *GV = GA->getGlobal(); 5753 5754 if (Subtarget->isTargetELF()) { 5755 // TODO: implement the "local dynamic" model 5756 // TODO: implement the "initial exec"model for pic executables 5757 5758 // If GV is an alias then use the aliasee for determining 5759 // thread-localness. 5760 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 5761 GV = GA->resolveAliasedGlobal(false); 5762 5763 TLSModel::Model model 5764 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 5765 5766 switch (model) { 5767 case TLSModel::GeneralDynamic: 5768 case TLSModel::LocalDynamic: // not implemented 5769 if (Subtarget->is64Bit()) 5770 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 5771 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 5772 5773 case TLSModel::InitialExec: 5774 case TLSModel::LocalExec: 5775 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 5776 Subtarget->is64Bit()); 5777 } 5778 } else if (Subtarget->isTargetDarwin()) { 5779 // Darwin only has one model of TLS. Lower to that. 5780 unsigned char OpFlag = 0; 5781 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 5782 X86ISD::WrapperRIP : X86ISD::Wrapper; 5783 5784 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5785 // global base reg. 5786 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 5787 !Subtarget->is64Bit(); 5788 if (PIC32) 5789 OpFlag = X86II::MO_TLVP_PIC_BASE; 5790 else 5791 OpFlag = X86II::MO_TLVP; 5792 DebugLoc DL = Op.getDebugLoc(); 5793 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 5794 getPointerTy(), 5795 GA->getOffset(), OpFlag); 5796 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5797 5798 // With PIC32, the address is actually $g + Offset. 5799 if (PIC32) 5800 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5801 DAG.getNode(X86ISD::GlobalBaseReg, 5802 DebugLoc(), getPointerTy()), 5803 Offset); 5804 5805 // Lowering the machine isd will make sure everything is in the right 5806 // location. 5807 SDValue Args[] = { Offset }; 5808 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1); 5809 5810 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 5811 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5812 MFI->setAdjustsStack(true); 5813 5814 // And our return value (tls address) is in the standard call return value 5815 // location. 5816 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 5817 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 5818 } 5819 5820 assert(false && 5821 "TLS not implemented for this target."); 5822 5823 llvm_unreachable("Unreachable"); 5824 return SDValue(); 5825} 5826 5827 5828/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 5829/// take a 2 x i32 value to shift plus a shift amount. 5830SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 5831 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 5832 EVT VT = Op.getValueType(); 5833 unsigned VTBits = VT.getSizeInBits(); 5834 DebugLoc dl = Op.getDebugLoc(); 5835 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 5836 SDValue ShOpLo = Op.getOperand(0); 5837 SDValue ShOpHi = Op.getOperand(1); 5838 SDValue ShAmt = Op.getOperand(2); 5839 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 5840 DAG.getConstant(VTBits - 1, MVT::i8)) 5841 : DAG.getConstant(0, VT); 5842 5843 SDValue Tmp2, Tmp3; 5844 if (Op.getOpcode() == ISD::SHL_PARTS) { 5845 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 5846 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 5847 } else { 5848 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 5849 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 5850 } 5851 5852 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 5853 DAG.getConstant(VTBits, MVT::i8)); 5854 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 5855 AndNode, DAG.getConstant(0, MVT::i8)); 5856 5857 SDValue Hi, Lo; 5858 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5859 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 5860 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 5861 5862 if (Op.getOpcode() == ISD::SHL_PARTS) { 5863 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5864 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5865 } else { 5866 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5867 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5868 } 5869 5870 SDValue Ops[2] = { Lo, Hi }; 5871 return DAG.getMergeValues(Ops, 2, dl); 5872} 5873 5874SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 5875 SelectionDAG &DAG) const { 5876 EVT SrcVT = Op.getOperand(0).getValueType(); 5877 5878 if (SrcVT.isVector()) { 5879 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 5880 return Op; 5881 } 5882 return SDValue(); 5883 } 5884 5885 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 5886 "Unknown SINT_TO_FP to lower!"); 5887 5888 // These are really Legal; return the operand so the caller accepts it as 5889 // Legal. 5890 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 5891 return Op; 5892 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 5893 Subtarget->is64Bit()) { 5894 return Op; 5895 } 5896 5897 DebugLoc dl = Op.getDebugLoc(); 5898 unsigned Size = SrcVT.getSizeInBits()/8; 5899 MachineFunction &MF = DAG.getMachineFunction(); 5900 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 5901 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5902 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5903 StackSlot, 5904 PseudoSourceValue::getFixedStack(SSFI), 0, 5905 false, false, 0); 5906 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 5907} 5908 5909SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 5910 SDValue StackSlot, 5911 SelectionDAG &DAG) const { 5912 // Build the FILD 5913 DebugLoc dl = Op.getDebugLoc(); 5914 SDVTList Tys; 5915 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 5916 if (useSSE) 5917 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 5918 else 5919 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 5920 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 5921 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 5922 Tys, Ops, array_lengthof(Ops)); 5923 5924 if (useSSE) { 5925 Chain = Result.getValue(1); 5926 SDValue InFlag = Result.getValue(2); 5927 5928 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 5929 // shouldn't be necessary except that RFP cannot be live across 5930 // multiple blocks. When stackifier is fixed, they can be uncoupled. 5931 MachineFunction &MF = DAG.getMachineFunction(); 5932 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 5933 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5934 Tys = DAG.getVTList(MVT::Other); 5935 SDValue Ops[] = { 5936 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 5937 }; 5938 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops)); 5939 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 5940 PseudoSourceValue::getFixedStack(SSFI), 0, 5941 false, false, 0); 5942 } 5943 5944 return Result; 5945} 5946 5947// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 5948SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 5949 SelectionDAG &DAG) const { 5950 // This algorithm is not obvious. Here it is in C code, more or less: 5951 /* 5952 double uint64_to_double( uint32_t hi, uint32_t lo ) { 5953 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 5954 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 5955 5956 // Copy ints to xmm registers. 5957 __m128i xh = _mm_cvtsi32_si128( hi ); 5958 __m128i xl = _mm_cvtsi32_si128( lo ); 5959 5960 // Combine into low half of a single xmm register. 5961 __m128i x = _mm_unpacklo_epi32( xh, xl ); 5962 __m128d d; 5963 double sd; 5964 5965 // Merge in appropriate exponents to give the integer bits the right 5966 // magnitude. 5967 x = _mm_unpacklo_epi32( x, exp ); 5968 5969 // Subtract away the biases to deal with the IEEE-754 double precision 5970 // implicit 1. 5971 d = _mm_sub_pd( (__m128d) x, bias ); 5972 5973 // All conversions up to here are exact. The correctly rounded result is 5974 // calculated using the current rounding mode using the following 5975 // horizontal add. 5976 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 5977 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 5978 // store doesn't really need to be here (except 5979 // maybe to zero the other double) 5980 return sd; 5981 } 5982 */ 5983 5984 DebugLoc dl = Op.getDebugLoc(); 5985 LLVMContext *Context = DAG.getContext(); 5986 5987 // Build some magic constants. 5988 std::vector<Constant*> CV0; 5989 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 5990 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 5991 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5992 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5993 Constant *C0 = ConstantVector::get(CV0); 5994 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 5995 5996 std::vector<Constant*> CV1; 5997 CV1.push_back( 5998 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 5999 CV1.push_back( 6000 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 6001 Constant *C1 = ConstantVector::get(CV1); 6002 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 6003 6004 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6005 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6006 Op.getOperand(0), 6007 DAG.getIntPtrConstant(1))); 6008 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6009 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6010 Op.getOperand(0), 6011 DAG.getIntPtrConstant(0))); 6012 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 6013 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 6014 PseudoSourceValue::getConstantPool(), 0, 6015 false, false, 16); 6016 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 6017 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 6018 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 6019 PseudoSourceValue::getConstantPool(), 0, 6020 false, false, 16); 6021 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 6022 6023 // Add the halves; easiest way is to swap them into another reg first. 6024 int ShufMask[2] = { 1, -1 }; 6025 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 6026 DAG.getUNDEF(MVT::v2f64), ShufMask); 6027 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 6028 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 6029 DAG.getIntPtrConstant(0)); 6030} 6031 6032// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 6033SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 6034 SelectionDAG &DAG) const { 6035 DebugLoc dl = Op.getDebugLoc(); 6036 // FP constant to bias correct the final result. 6037 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 6038 MVT::f64); 6039 6040 // Load the 32-bit value into an XMM register. 6041 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 6042 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6043 Op.getOperand(0), 6044 DAG.getIntPtrConstant(0))); 6045 6046 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6047 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 6048 DAG.getIntPtrConstant(0)); 6049 6050 // Or the load with the bias. 6051 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 6052 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 6053 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6054 MVT::v2f64, Load)), 6055 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 6056 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6057 MVT::v2f64, Bias))); 6058 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6059 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 6060 DAG.getIntPtrConstant(0)); 6061 6062 // Subtract the bias. 6063 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 6064 6065 // Handle final rounding. 6066 EVT DestVT = Op.getValueType(); 6067 6068 if (DestVT.bitsLT(MVT::f64)) { 6069 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 6070 DAG.getIntPtrConstant(0)); 6071 } else if (DestVT.bitsGT(MVT::f64)) { 6072 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 6073 } 6074 6075 // Handle final rounding. 6076 return Sub; 6077} 6078 6079SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 6080 SelectionDAG &DAG) const { 6081 SDValue N0 = Op.getOperand(0); 6082 DebugLoc dl = Op.getDebugLoc(); 6083 6084 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 6085 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 6086 // the optimization here. 6087 if (DAG.SignBitIsZero(N0)) 6088 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 6089 6090 EVT SrcVT = N0.getValueType(); 6091 EVT DstVT = Op.getValueType(); 6092 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 6093 return LowerUINT_TO_FP_i64(Op, DAG); 6094 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 6095 return LowerUINT_TO_FP_i32(Op, DAG); 6096 6097 // Make a 64-bit buffer, and use it to build an FILD. 6098 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 6099 if (SrcVT == MVT::i32) { 6100 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 6101 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 6102 getPointerTy(), StackSlot, WordOff); 6103 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6104 StackSlot, NULL, 0, false, false, 0); 6105 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 6106 OffsetSlot, NULL, 0, false, false, 0); 6107 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 6108 return Fild; 6109 } 6110 6111 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 6112 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 6113 StackSlot, NULL, 0, false, false, 0); 6114 // For i64 source, we need to add the appropriate power of 2 if the input 6115 // was negative. This is the same as the optimization in 6116 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 6117 // we must be careful to do the computation in x87 extended precision, not 6118 // in SSE. (The generic code can't know it's OK to do this, or how to.) 6119 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 6120 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 6121 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3); 6122 6123 APInt FF(32, 0x5F800000ULL); 6124 6125 // Check whether the sign bit is set. 6126 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 6127 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 6128 ISD::SETLT); 6129 6130 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 6131 SDValue FudgePtr = DAG.getConstantPool( 6132 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 6133 getPointerTy()); 6134 6135 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 6136 SDValue Zero = DAG.getIntPtrConstant(0); 6137 SDValue Four = DAG.getIntPtrConstant(4); 6138 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 6139 Zero, Four); 6140 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 6141 6142 // Load the value out, extending it from f32 to f80. 6143 // FIXME: Avoid the extend by constructing the right constant pool? 6144 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(), 6145 FudgePtr, PseudoSourceValue::getConstantPool(), 6146 0, MVT::f32, false, false, 4); 6147 // Extend everything to 80 bits to force it to be done on x87. 6148 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 6149 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 6150} 6151 6152std::pair<SDValue,SDValue> X86TargetLowering:: 6153FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 6154 DebugLoc dl = Op.getDebugLoc(); 6155 6156 EVT DstTy = Op.getValueType(); 6157 6158 if (!IsSigned) { 6159 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 6160 DstTy = MVT::i64; 6161 } 6162 6163 assert(DstTy.getSimpleVT() <= MVT::i64 && 6164 DstTy.getSimpleVT() >= MVT::i16 && 6165 "Unknown FP_TO_SINT to lower!"); 6166 6167 // These are really Legal. 6168 if (DstTy == MVT::i32 && 6169 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 6170 return std::make_pair(SDValue(), SDValue()); 6171 if (Subtarget->is64Bit() && 6172 DstTy == MVT::i64 && 6173 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 6174 return std::make_pair(SDValue(), SDValue()); 6175 6176 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 6177 // stack slot. 6178 MachineFunction &MF = DAG.getMachineFunction(); 6179 unsigned MemSize = DstTy.getSizeInBits()/8; 6180 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 6181 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6182 6183 unsigned Opc; 6184 switch (DstTy.getSimpleVT().SimpleTy) { 6185 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 6186 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 6187 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 6188 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 6189 } 6190 6191 SDValue Chain = DAG.getEntryNode(); 6192 SDValue Value = Op.getOperand(0); 6193 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 6194 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 6195 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 6196 PseudoSourceValue::getFixedStack(SSFI), 0, 6197 false, false, 0); 6198 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 6199 SDValue Ops[] = { 6200 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 6201 }; 6202 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 6203 Chain = Value.getValue(1); 6204 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 6205 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6206 } 6207 6208 // Build the FP_TO_INT*_IN_MEM 6209 SDValue Ops[] = { Chain, Value, StackSlot }; 6210 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 6211 6212 return std::make_pair(FIST, StackSlot); 6213} 6214 6215SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 6216 SelectionDAG &DAG) const { 6217 if (Op.getValueType().isVector()) { 6218 if (Op.getValueType() == MVT::v2i32 && 6219 Op.getOperand(0).getValueType() == MVT::v2f64) { 6220 return Op; 6221 } 6222 return SDValue(); 6223 } 6224 6225 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 6226 SDValue FIST = Vals.first, StackSlot = Vals.second; 6227 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 6228 if (FIST.getNode() == 0) return Op; 6229 6230 // Load the result. 6231 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 6232 FIST, StackSlot, NULL, 0, false, false, 0); 6233} 6234 6235SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 6236 SelectionDAG &DAG) const { 6237 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 6238 SDValue FIST = Vals.first, StackSlot = Vals.second; 6239 assert(FIST.getNode() && "Unexpected failure"); 6240 6241 // Load the result. 6242 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 6243 FIST, StackSlot, NULL, 0, false, false, 0); 6244} 6245 6246SDValue X86TargetLowering::LowerFABS(SDValue Op, 6247 SelectionDAG &DAG) const { 6248 LLVMContext *Context = DAG.getContext(); 6249 DebugLoc dl = Op.getDebugLoc(); 6250 EVT VT = Op.getValueType(); 6251 EVT EltVT = VT; 6252 if (VT.isVector()) 6253 EltVT = VT.getVectorElementType(); 6254 std::vector<Constant*> CV; 6255 if (EltVT == MVT::f64) { 6256 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 6257 CV.push_back(C); 6258 CV.push_back(C); 6259 } else { 6260 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 6261 CV.push_back(C); 6262 CV.push_back(C); 6263 CV.push_back(C); 6264 CV.push_back(C); 6265 } 6266 Constant *C = ConstantVector::get(CV); 6267 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6268 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6269 PseudoSourceValue::getConstantPool(), 0, 6270 false, false, 16); 6271 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 6272} 6273 6274SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 6275 LLVMContext *Context = DAG.getContext(); 6276 DebugLoc dl = Op.getDebugLoc(); 6277 EVT VT = Op.getValueType(); 6278 EVT EltVT = VT; 6279 if (VT.isVector()) 6280 EltVT = VT.getVectorElementType(); 6281 std::vector<Constant*> CV; 6282 if (EltVT == MVT::f64) { 6283 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 6284 CV.push_back(C); 6285 CV.push_back(C); 6286 } else { 6287 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 6288 CV.push_back(C); 6289 CV.push_back(C); 6290 CV.push_back(C); 6291 CV.push_back(C); 6292 } 6293 Constant *C = ConstantVector::get(CV); 6294 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6295 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6296 PseudoSourceValue::getConstantPool(), 0, 6297 false, false, 16); 6298 if (VT.isVector()) { 6299 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 6300 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 6301 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 6302 Op.getOperand(0)), 6303 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 6304 } else { 6305 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 6306 } 6307} 6308 6309SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 6310 LLVMContext *Context = DAG.getContext(); 6311 SDValue Op0 = Op.getOperand(0); 6312 SDValue Op1 = Op.getOperand(1); 6313 DebugLoc dl = Op.getDebugLoc(); 6314 EVT VT = Op.getValueType(); 6315 EVT SrcVT = Op1.getValueType(); 6316 6317 // If second operand is smaller, extend it first. 6318 if (SrcVT.bitsLT(VT)) { 6319 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 6320 SrcVT = VT; 6321 } 6322 // And if it is bigger, shrink it first. 6323 if (SrcVT.bitsGT(VT)) { 6324 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 6325 SrcVT = VT; 6326 } 6327 6328 // At this point the operands and the result should have the same 6329 // type, and that won't be f80 since that is not custom lowered. 6330 6331 // First get the sign bit of second operand. 6332 std::vector<Constant*> CV; 6333 if (SrcVT == MVT::f64) { 6334 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 6335 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 6336 } else { 6337 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 6338 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6339 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6340 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6341 } 6342 Constant *C = ConstantVector::get(CV); 6343 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6344 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 6345 PseudoSourceValue::getConstantPool(), 0, 6346 false, false, 16); 6347 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 6348 6349 // Shift sign bit right or left if the two operands have different types. 6350 if (SrcVT.bitsGT(VT)) { 6351 // Op0 is MVT::f32, Op1 is MVT::f64. 6352 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 6353 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 6354 DAG.getConstant(32, MVT::i32)); 6355 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 6356 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 6357 DAG.getIntPtrConstant(0)); 6358 } 6359 6360 // Clear first operand sign bit. 6361 CV.clear(); 6362 if (VT == MVT::f64) { 6363 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 6364 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 6365 } else { 6366 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 6367 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6368 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6369 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 6370 } 6371 C = ConstantVector::get(CV); 6372 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 6373 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 6374 PseudoSourceValue::getConstantPool(), 0, 6375 false, false, 16); 6376 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 6377 6378 // Or the value with the sign bit. 6379 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 6380} 6381 6382/// Emit nodes that will be selected as "test Op0,Op0", or something 6383/// equivalent. 6384SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 6385 SelectionDAG &DAG) const { 6386 DebugLoc dl = Op.getDebugLoc(); 6387 6388 // CF and OF aren't always set the way we want. Determine which 6389 // of these we need. 6390 bool NeedCF = false; 6391 bool NeedOF = false; 6392 switch (X86CC) { 6393 default: break; 6394 case X86::COND_A: case X86::COND_AE: 6395 case X86::COND_B: case X86::COND_BE: 6396 NeedCF = true; 6397 break; 6398 case X86::COND_G: case X86::COND_GE: 6399 case X86::COND_L: case X86::COND_LE: 6400 case X86::COND_O: case X86::COND_NO: 6401 NeedOF = true; 6402 break; 6403 } 6404 6405 // See if we can use the EFLAGS value from the operand instead of 6406 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 6407 // we prove that the arithmetic won't overflow, we can't use OF or CF. 6408 if (Op.getResNo() != 0 || NeedOF || NeedCF) 6409 // Emit a CMP with 0, which is the TEST pattern. 6410 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 6411 DAG.getConstant(0, Op.getValueType())); 6412 6413 unsigned Opcode = 0; 6414 unsigned NumOperands = 0; 6415 switch (Op.getNode()->getOpcode()) { 6416 case ISD::ADD: 6417 // Due to an isel shortcoming, be conservative if this add is likely to be 6418 // selected as part of a load-modify-store instruction. When the root node 6419 // in a match is a store, isel doesn't know how to remap non-chain non-flag 6420 // uses of other nodes in the match, such as the ADD in this case. This 6421 // leads to the ADD being left around and reselected, with the result being 6422 // two adds in the output. Alas, even if none our users are stores, that 6423 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 6424 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 6425 // climbing the DAG back to the root, and it doesn't seem to be worth the 6426 // effort. 6427 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6428 UE = Op.getNode()->use_end(); UI != UE; ++UI) 6429 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 6430 goto default_case; 6431 6432 if (ConstantSDNode *C = 6433 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 6434 // An add of one will be selected as an INC. 6435 if (C->getAPIntValue() == 1) { 6436 Opcode = X86ISD::INC; 6437 NumOperands = 1; 6438 break; 6439 } 6440 6441 // An add of negative one (subtract of one) will be selected as a DEC. 6442 if (C->getAPIntValue().isAllOnesValue()) { 6443 Opcode = X86ISD::DEC; 6444 NumOperands = 1; 6445 break; 6446 } 6447 } 6448 6449 // Otherwise use a regular EFLAGS-setting add. 6450 Opcode = X86ISD::ADD; 6451 NumOperands = 2; 6452 break; 6453 case ISD::AND: { 6454 // If the primary and result isn't used, don't bother using X86ISD::AND, 6455 // because a TEST instruction will be better. 6456 bool NonFlagUse = false; 6457 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6458 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 6459 SDNode *User = *UI; 6460 unsigned UOpNo = UI.getOperandNo(); 6461 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 6462 // Look pass truncate. 6463 UOpNo = User->use_begin().getOperandNo(); 6464 User = *User->use_begin(); 6465 } 6466 6467 if (User->getOpcode() != ISD::BRCOND && 6468 User->getOpcode() != ISD::SETCC && 6469 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 6470 NonFlagUse = true; 6471 break; 6472 } 6473 } 6474 6475 if (!NonFlagUse) 6476 break; 6477 } 6478 // FALL THROUGH 6479 case ISD::SUB: 6480 case ISD::OR: 6481 case ISD::XOR: 6482 // Due to the ISEL shortcoming noted above, be conservative if this op is 6483 // likely to be selected as part of a load-modify-store instruction. 6484 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 6485 UE = Op.getNode()->use_end(); UI != UE; ++UI) 6486 if (UI->getOpcode() == ISD::STORE) 6487 goto default_case; 6488 6489 // Otherwise use a regular EFLAGS-setting instruction. 6490 switch (Op.getNode()->getOpcode()) { 6491 default: llvm_unreachable("unexpected operator!"); 6492 case ISD::SUB: Opcode = X86ISD::SUB; break; 6493 case ISD::OR: Opcode = X86ISD::OR; break; 6494 case ISD::XOR: Opcode = X86ISD::XOR; break; 6495 case ISD::AND: Opcode = X86ISD::AND; break; 6496 } 6497 6498 NumOperands = 2; 6499 break; 6500 case X86ISD::ADD: 6501 case X86ISD::SUB: 6502 case X86ISD::INC: 6503 case X86ISD::DEC: 6504 case X86ISD::OR: 6505 case X86ISD::XOR: 6506 case X86ISD::AND: 6507 return SDValue(Op.getNode(), 1); 6508 default: 6509 default_case: 6510 break; 6511 } 6512 6513 if (Opcode == 0) 6514 // Emit a CMP with 0, which is the TEST pattern. 6515 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 6516 DAG.getConstant(0, Op.getValueType())); 6517 6518 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 6519 SmallVector<SDValue, 4> Ops; 6520 for (unsigned i = 0; i != NumOperands; ++i) 6521 Ops.push_back(Op.getOperand(i)); 6522 6523 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 6524 DAG.ReplaceAllUsesWith(Op, New); 6525 return SDValue(New.getNode(), 1); 6526} 6527 6528/// Emit nodes that will be selected as "cmp Op0,Op1", or something 6529/// equivalent. 6530SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 6531 SelectionDAG &DAG) const { 6532 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 6533 if (C->getAPIntValue() == 0) 6534 return EmitTest(Op0, X86CC, DAG); 6535 6536 DebugLoc dl = Op0.getDebugLoc(); 6537 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 6538} 6539 6540/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 6541/// if it's possible. 6542SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 6543 DebugLoc dl, SelectionDAG &DAG) const { 6544 SDValue Op0 = And.getOperand(0); 6545 SDValue Op1 = And.getOperand(1); 6546 if (Op0.getOpcode() == ISD::TRUNCATE) 6547 Op0 = Op0.getOperand(0); 6548 if (Op1.getOpcode() == ISD::TRUNCATE) 6549 Op1 = Op1.getOperand(0); 6550 6551 SDValue LHS, RHS; 6552 if (Op1.getOpcode() == ISD::SHL) 6553 std::swap(Op0, Op1); 6554 if (Op0.getOpcode() == ISD::SHL) { 6555 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 6556 if (And00C->getZExtValue() == 1) { 6557 // If we looked past a truncate, check that it's only truncating away 6558 // known zeros. 6559 unsigned BitWidth = Op0.getValueSizeInBits(); 6560 unsigned AndBitWidth = And.getValueSizeInBits(); 6561 if (BitWidth > AndBitWidth) { 6562 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 6563 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 6564 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 6565 return SDValue(); 6566 } 6567 LHS = Op1; 6568 RHS = Op0.getOperand(1); 6569 } 6570 } else if (Op1.getOpcode() == ISD::Constant) { 6571 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 6572 SDValue AndLHS = Op0; 6573 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 6574 LHS = AndLHS.getOperand(0); 6575 RHS = AndLHS.getOperand(1); 6576 } 6577 } 6578 6579 if (LHS.getNode()) { 6580 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 6581 // instruction. Since the shift amount is in-range-or-undefined, we know 6582 // that doing a bittest on the i32 value is ok. We extend to i32 because 6583 // the encoding for the i16 version is larger than the i32 version. 6584 // Also promote i16 to i32 for performance / code size reason. 6585 if (LHS.getValueType() == MVT::i8 || 6586 LHS.getValueType() == MVT::i16) 6587 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 6588 6589 // If the operand types disagree, extend the shift amount to match. Since 6590 // BT ignores high bits (like shifts) we can use anyextend. 6591 if (LHS.getValueType() != RHS.getValueType()) 6592 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 6593 6594 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 6595 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 6596 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6597 DAG.getConstant(Cond, MVT::i8), BT); 6598 } 6599 6600 return SDValue(); 6601} 6602 6603SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 6604 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 6605 SDValue Op0 = Op.getOperand(0); 6606 SDValue Op1 = Op.getOperand(1); 6607 DebugLoc dl = Op.getDebugLoc(); 6608 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 6609 6610 // Optimize to BT if possible. 6611 // Lower (X & (1 << N)) == 0 to BT(X, N). 6612 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 6613 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 6614 if (Op0.getOpcode() == ISD::AND && 6615 Op0.hasOneUse() && 6616 Op1.getOpcode() == ISD::Constant && 6617 cast<ConstantSDNode>(Op1)->isNullValue() && 6618 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6619 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 6620 if (NewSetCC.getNode()) 6621 return NewSetCC; 6622 } 6623 6624 // Look for "(setcc) == / != 1" to avoid unncessary setcc. 6625 if (Op0.getOpcode() == X86ISD::SETCC && 6626 Op1.getOpcode() == ISD::Constant && 6627 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 6628 cast<ConstantSDNode>(Op1)->isNullValue()) && 6629 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6630 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 6631 bool Invert = (CC == ISD::SETNE) ^ 6632 cast<ConstantSDNode>(Op1)->isNullValue(); 6633 if (Invert) 6634 CCode = X86::GetOppositeBranchCondition(CCode); 6635 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6636 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 6637 } 6638 6639 bool isFP = Op1.getValueType().isFloatingPoint(); 6640 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 6641 if (X86CC == X86::COND_INVALID) 6642 return SDValue(); 6643 6644 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 6645 6646 // Use sbb x, x to materialize carry bit into a GPR. 6647 if (X86CC == X86::COND_B) 6648 return DAG.getNode(ISD::AND, dl, MVT::i8, 6649 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 6650 DAG.getConstant(X86CC, MVT::i8), Cond), 6651 DAG.getConstant(1, MVT::i8)); 6652 6653 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6654 DAG.getConstant(X86CC, MVT::i8), Cond); 6655} 6656 6657SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 6658 SDValue Cond; 6659 SDValue Op0 = Op.getOperand(0); 6660 SDValue Op1 = Op.getOperand(1); 6661 SDValue CC = Op.getOperand(2); 6662 EVT VT = Op.getValueType(); 6663 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 6664 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6665 DebugLoc dl = Op.getDebugLoc(); 6666 6667 if (isFP) { 6668 unsigned SSECC = 8; 6669 EVT VT0 = Op0.getValueType(); 6670 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 6671 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 6672 bool Swap = false; 6673 6674 switch (SetCCOpcode) { 6675 default: break; 6676 case ISD::SETOEQ: 6677 case ISD::SETEQ: SSECC = 0; break; 6678 case ISD::SETOGT: 6679 case ISD::SETGT: Swap = true; // Fallthrough 6680 case ISD::SETLT: 6681 case ISD::SETOLT: SSECC = 1; break; 6682 case ISD::SETOGE: 6683 case ISD::SETGE: Swap = true; // Fallthrough 6684 case ISD::SETLE: 6685 case ISD::SETOLE: SSECC = 2; break; 6686 case ISD::SETUO: SSECC = 3; break; 6687 case ISD::SETUNE: 6688 case ISD::SETNE: SSECC = 4; break; 6689 case ISD::SETULE: Swap = true; 6690 case ISD::SETUGE: SSECC = 5; break; 6691 case ISD::SETULT: Swap = true; 6692 case ISD::SETUGT: SSECC = 6; break; 6693 case ISD::SETO: SSECC = 7; break; 6694 } 6695 if (Swap) 6696 std::swap(Op0, Op1); 6697 6698 // In the two special cases we can't handle, emit two comparisons. 6699 if (SSECC == 8) { 6700 if (SetCCOpcode == ISD::SETUEQ) { 6701 SDValue UNORD, EQ; 6702 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 6703 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 6704 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 6705 } 6706 else if (SetCCOpcode == ISD::SETONE) { 6707 SDValue ORD, NEQ; 6708 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 6709 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 6710 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 6711 } 6712 llvm_unreachable("Illegal FP comparison"); 6713 } 6714 // Handle all other FP comparisons here. 6715 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 6716 } 6717 6718 // We are handling one of the integer comparisons here. Since SSE only has 6719 // GT and EQ comparisons for integer, swapping operands and multiple 6720 // operations may be required for some comparisons. 6721 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 6722 bool Swap = false, Invert = false, FlipSigns = false; 6723 6724 switch (VT.getSimpleVT().SimpleTy) { 6725 default: break; 6726 case MVT::v8i8: 6727 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 6728 case MVT::v4i16: 6729 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 6730 case MVT::v2i32: 6731 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 6732 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 6733 } 6734 6735 switch (SetCCOpcode) { 6736 default: break; 6737 case ISD::SETNE: Invert = true; 6738 case ISD::SETEQ: Opc = EQOpc; break; 6739 case ISD::SETLT: Swap = true; 6740 case ISD::SETGT: Opc = GTOpc; break; 6741 case ISD::SETGE: Swap = true; 6742 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 6743 case ISD::SETULT: Swap = true; 6744 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 6745 case ISD::SETUGE: Swap = true; 6746 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 6747 } 6748 if (Swap) 6749 std::swap(Op0, Op1); 6750 6751 // Since SSE has no unsigned integer comparisons, we need to flip the sign 6752 // bits of the inputs before performing those operations. 6753 if (FlipSigns) { 6754 EVT EltVT = VT.getVectorElementType(); 6755 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 6756 EltVT); 6757 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 6758 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 6759 SignBits.size()); 6760 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 6761 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 6762 } 6763 6764 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 6765 6766 // If the logical-not of the result is required, perform that now. 6767 if (Invert) 6768 Result = DAG.getNOT(dl, Result, VT); 6769 6770 return Result; 6771} 6772 6773// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 6774static bool isX86LogicalCmp(SDValue Op) { 6775 unsigned Opc = Op.getNode()->getOpcode(); 6776 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 6777 return true; 6778 if (Op.getResNo() == 1 && 6779 (Opc == X86ISD::ADD || 6780 Opc == X86ISD::SUB || 6781 Opc == X86ISD::SMUL || 6782 Opc == X86ISD::UMUL || 6783 Opc == X86ISD::INC || 6784 Opc == X86ISD::DEC || 6785 Opc == X86ISD::OR || 6786 Opc == X86ISD::XOR || 6787 Opc == X86ISD::AND)) 6788 return true; 6789 6790 return false; 6791} 6792 6793SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 6794 bool addTest = true; 6795 SDValue Cond = Op.getOperand(0); 6796 DebugLoc dl = Op.getDebugLoc(); 6797 SDValue CC; 6798 6799 if (Cond.getOpcode() == ISD::SETCC) { 6800 SDValue NewCond = LowerSETCC(Cond, DAG); 6801 if (NewCond.getNode()) 6802 Cond = NewCond; 6803 } 6804 6805 // (select (x == 0), -1, 0) -> (sign_bit (x - 1)) 6806 SDValue Op1 = Op.getOperand(1); 6807 SDValue Op2 = Op.getOperand(2); 6808 if (Cond.getOpcode() == X86ISD::SETCC && 6809 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) { 6810 SDValue Cmp = Cond.getOperand(1); 6811 if (Cmp.getOpcode() == X86ISD::CMP) { 6812 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1); 6813 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 6814 ConstantSDNode *RHSC = 6815 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode()); 6816 if (N1C && N1C->isAllOnesValue() && 6817 N2C && N2C->isNullValue() && 6818 RHSC && RHSC->isNullValue()) { 6819 SDValue CmpOp0 = Cmp.getOperand(0); 6820 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 6821 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 6822 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(), 6823 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 6824 } 6825 } 6826 } 6827 6828 // Look pass (and (setcc_carry (cmp ...)), 1). 6829 if (Cond.getOpcode() == ISD::AND && 6830 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6831 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6832 if (C && C->getAPIntValue() == 1) 6833 Cond = Cond.getOperand(0); 6834 } 6835 6836 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6837 // setting operand in place of the X86ISD::SETCC. 6838 if (Cond.getOpcode() == X86ISD::SETCC || 6839 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6840 CC = Cond.getOperand(0); 6841 6842 SDValue Cmp = Cond.getOperand(1); 6843 unsigned Opc = Cmp.getOpcode(); 6844 EVT VT = Op.getValueType(); 6845 6846 bool IllegalFPCMov = false; 6847 if (VT.isFloatingPoint() && !VT.isVector() && 6848 !isScalarFPTypeInSSEReg(VT)) // FPStack? 6849 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 6850 6851 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 6852 Opc == X86ISD::BT) { // FIXME 6853 Cond = Cmp; 6854 addTest = false; 6855 } 6856 } 6857 6858 if (addTest) { 6859 // Look pass the truncate. 6860 if (Cond.getOpcode() == ISD::TRUNCATE) 6861 Cond = Cond.getOperand(0); 6862 6863 // We know the result of AND is compared against zero. Try to match 6864 // it to BT. 6865 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6866 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6867 if (NewSetCC.getNode()) { 6868 CC = NewSetCC.getOperand(0); 6869 Cond = NewSetCC.getOperand(1); 6870 addTest = false; 6871 } 6872 } 6873 } 6874 6875 if (addTest) { 6876 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6877 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6878 } 6879 6880 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 6881 // condition is true. 6882 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 6883 SDValue Ops[] = { Op2, Op1, CC, Cond }; 6884 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops)); 6885} 6886 6887// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 6888// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 6889// from the AND / OR. 6890static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 6891 Opc = Op.getOpcode(); 6892 if (Opc != ISD::OR && Opc != ISD::AND) 6893 return false; 6894 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6895 Op.getOperand(0).hasOneUse() && 6896 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 6897 Op.getOperand(1).hasOneUse()); 6898} 6899 6900// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 6901// 1 and that the SETCC node has a single use. 6902static bool isXor1OfSetCC(SDValue Op) { 6903 if (Op.getOpcode() != ISD::XOR) 6904 return false; 6905 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6906 if (N1C && N1C->getAPIntValue() == 1) { 6907 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6908 Op.getOperand(0).hasOneUse(); 6909 } 6910 return false; 6911} 6912 6913SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 6914 bool addTest = true; 6915 SDValue Chain = Op.getOperand(0); 6916 SDValue Cond = Op.getOperand(1); 6917 SDValue Dest = Op.getOperand(2); 6918 DebugLoc dl = Op.getDebugLoc(); 6919 SDValue CC; 6920 6921 if (Cond.getOpcode() == ISD::SETCC) { 6922 SDValue NewCond = LowerSETCC(Cond, DAG); 6923 if (NewCond.getNode()) 6924 Cond = NewCond; 6925 } 6926#if 0 6927 // FIXME: LowerXALUO doesn't handle these!! 6928 else if (Cond.getOpcode() == X86ISD::ADD || 6929 Cond.getOpcode() == X86ISD::SUB || 6930 Cond.getOpcode() == X86ISD::SMUL || 6931 Cond.getOpcode() == X86ISD::UMUL) 6932 Cond = LowerXALUO(Cond, DAG); 6933#endif 6934 6935 // Look pass (and (setcc_carry (cmp ...)), 1). 6936 if (Cond.getOpcode() == ISD::AND && 6937 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6939 if (C && C->getAPIntValue() == 1) 6940 Cond = Cond.getOperand(0); 6941 } 6942 6943 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6944 // setting operand in place of the X86ISD::SETCC. 6945 if (Cond.getOpcode() == X86ISD::SETCC || 6946 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6947 CC = Cond.getOperand(0); 6948 6949 SDValue Cmp = Cond.getOperand(1); 6950 unsigned Opc = Cmp.getOpcode(); 6951 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 6952 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 6953 Cond = Cmp; 6954 addTest = false; 6955 } else { 6956 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 6957 default: break; 6958 case X86::COND_O: 6959 case X86::COND_B: 6960 // These can only come from an arithmetic instruction with overflow, 6961 // e.g. SADDO, UADDO. 6962 Cond = Cond.getNode()->getOperand(1); 6963 addTest = false; 6964 break; 6965 } 6966 } 6967 } else { 6968 unsigned CondOpc; 6969 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 6970 SDValue Cmp = Cond.getOperand(0).getOperand(1); 6971 if (CondOpc == ISD::OR) { 6972 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 6973 // two branches instead of an explicit OR instruction with a 6974 // separate test. 6975 if (Cmp == Cond.getOperand(1).getOperand(1) && 6976 isX86LogicalCmp(Cmp)) { 6977 CC = Cond.getOperand(0).getOperand(0); 6978 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6979 Chain, Dest, CC, Cmp); 6980 CC = Cond.getOperand(1).getOperand(0); 6981 Cond = Cmp; 6982 addTest = false; 6983 } 6984 } else { // ISD::AND 6985 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 6986 // two branches instead of an explicit AND instruction with a 6987 // separate test. However, we only do this if this block doesn't 6988 // have a fall-through edge, because this requires an explicit 6989 // jmp when the condition is false. 6990 if (Cmp == Cond.getOperand(1).getOperand(1) && 6991 isX86LogicalCmp(Cmp) && 6992 Op.getNode()->hasOneUse()) { 6993 X86::CondCode CCode = 6994 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6995 CCode = X86::GetOppositeBranchCondition(CCode); 6996 CC = DAG.getConstant(CCode, MVT::i8); 6997 SDNode *User = *Op.getNode()->use_begin(); 6998 // Look for an unconditional branch following this conditional branch. 6999 // We need this because we need to reverse the successors in order 7000 // to implement FCMP_OEQ. 7001 if (User->getOpcode() == ISD::BR) { 7002 SDValue FalseBB = User->getOperand(1); 7003 SDNode *NewBR = 7004 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 7005 assert(NewBR == User); 7006 (void)NewBR; 7007 Dest = FalseBB; 7008 7009 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7010 Chain, Dest, CC, Cmp); 7011 X86::CondCode CCode = 7012 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 7013 CCode = X86::GetOppositeBranchCondition(CCode); 7014 CC = DAG.getConstant(CCode, MVT::i8); 7015 Cond = Cmp; 7016 addTest = false; 7017 } 7018 } 7019 } 7020 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 7021 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 7022 // It should be transformed during dag combiner except when the condition 7023 // is set by a arithmetics with overflow node. 7024 X86::CondCode CCode = 7025 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 7026 CCode = X86::GetOppositeBranchCondition(CCode); 7027 CC = DAG.getConstant(CCode, MVT::i8); 7028 Cond = Cond.getOperand(0).getOperand(1); 7029 addTest = false; 7030 } 7031 } 7032 7033 if (addTest) { 7034 // Look pass the truncate. 7035 if (Cond.getOpcode() == ISD::TRUNCATE) 7036 Cond = Cond.getOperand(0); 7037 7038 // We know the result of AND is compared against zero. Try to match 7039 // it to BT. 7040 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 7041 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 7042 if (NewSetCC.getNode()) { 7043 CC = NewSetCC.getOperand(0); 7044 Cond = NewSetCC.getOperand(1); 7045 addTest = false; 7046 } 7047 } 7048 } 7049 7050 if (addTest) { 7051 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7052 Cond = EmitTest(Cond, X86::COND_NE, DAG); 7053 } 7054 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 7055 Chain, Dest, CC, Cond); 7056} 7057 7058 7059// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 7060// Calls to _alloca is needed to probe the stack when allocating more than 4k 7061// bytes in one go. Touching the stack at 4K increments is necessary to ensure 7062// that the guard pages used by the OS virtual memory manager are allocated in 7063// correct sequence. 7064SDValue 7065X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 7066 SelectionDAG &DAG) const { 7067 assert(Subtarget->isTargetCygMing() && 7068 "This should be used only on Cygwin/Mingw targets"); 7069 DebugLoc dl = Op.getDebugLoc(); 7070 7071 // Get the inputs. 7072 SDValue Chain = Op.getOperand(0); 7073 SDValue Size = Op.getOperand(1); 7074 // FIXME: Ensure alignment here 7075 7076 SDValue Flag; 7077 7078 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 7079 7080 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 7081 Flag = Chain.getValue(1); 7082 7083 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 7084 7085 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag); 7086 Flag = Chain.getValue(1); 7087 7088 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 7089 7090 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 7091 return DAG.getMergeValues(Ops1, 2, dl); 7092} 7093 7094SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 7095 MachineFunction &MF = DAG.getMachineFunction(); 7096 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 7097 7098 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 7099 DebugLoc dl = Op.getDebugLoc(); 7100 7101 if (!Subtarget->is64Bit()) { 7102 // vastart just stores the address of the VarArgsFrameIndex slot into the 7103 // memory location argument. 7104 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 7105 getPointerTy()); 7106 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 7107 false, false, 0); 7108 } 7109 7110 // __va_list_tag: 7111 // gp_offset (0 - 6 * 8) 7112 // fp_offset (48 - 48 + 8 * 16) 7113 // overflow_arg_area (point to parameters coming in memory). 7114 // reg_save_area 7115 SmallVector<SDValue, 8> MemOps; 7116 SDValue FIN = Op.getOperand(1); 7117 // Store gp_offset 7118 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 7119 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 7120 MVT::i32), 7121 FIN, SV, 0, false, false, 0); 7122 MemOps.push_back(Store); 7123 7124 // Store fp_offset 7125 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7126 FIN, DAG.getIntPtrConstant(4)); 7127 Store = DAG.getStore(Op.getOperand(0), dl, 7128 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 7129 MVT::i32), 7130 FIN, SV, 4, false, false, 0); 7131 MemOps.push_back(Store); 7132 7133 // Store ptr to overflow_arg_area 7134 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7135 FIN, DAG.getIntPtrConstant(4)); 7136 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 7137 getPointerTy()); 7138 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8, 7139 false, false, 0); 7140 MemOps.push_back(Store); 7141 7142 // Store ptr to reg_save_area. 7143 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7144 FIN, DAG.getIntPtrConstant(8)); 7145 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 7146 getPointerTy()); 7147 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16, 7148 false, false, 0); 7149 MemOps.push_back(Store); 7150 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 7151 &MemOps[0], MemOps.size()); 7152} 7153 7154SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 7155 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 7156 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 7157 7158 report_fatal_error("VAArgInst is not yet implemented for x86-64!"); 7159 return SDValue(); 7160} 7161 7162SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 7163 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 7164 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 7165 SDValue Chain = Op.getOperand(0); 7166 SDValue DstPtr = Op.getOperand(1); 7167 SDValue SrcPtr = Op.getOperand(2); 7168 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 7169 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7170 DebugLoc dl = Op.getDebugLoc(); 7171 7172 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 7173 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 7174 false, DstSV, 0, SrcSV, 0); 7175} 7176 7177SDValue 7178X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 7179 DebugLoc dl = Op.getDebugLoc(); 7180 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7181 switch (IntNo) { 7182 default: return SDValue(); // Don't custom lower most intrinsics. 7183 // Comparison intrinsics. 7184 case Intrinsic::x86_sse_comieq_ss: 7185 case Intrinsic::x86_sse_comilt_ss: 7186 case Intrinsic::x86_sse_comile_ss: 7187 case Intrinsic::x86_sse_comigt_ss: 7188 case Intrinsic::x86_sse_comige_ss: 7189 case Intrinsic::x86_sse_comineq_ss: 7190 case Intrinsic::x86_sse_ucomieq_ss: 7191 case Intrinsic::x86_sse_ucomilt_ss: 7192 case Intrinsic::x86_sse_ucomile_ss: 7193 case Intrinsic::x86_sse_ucomigt_ss: 7194 case Intrinsic::x86_sse_ucomige_ss: 7195 case Intrinsic::x86_sse_ucomineq_ss: 7196 case Intrinsic::x86_sse2_comieq_sd: 7197 case Intrinsic::x86_sse2_comilt_sd: 7198 case Intrinsic::x86_sse2_comile_sd: 7199 case Intrinsic::x86_sse2_comigt_sd: 7200 case Intrinsic::x86_sse2_comige_sd: 7201 case Intrinsic::x86_sse2_comineq_sd: 7202 case Intrinsic::x86_sse2_ucomieq_sd: 7203 case Intrinsic::x86_sse2_ucomilt_sd: 7204 case Intrinsic::x86_sse2_ucomile_sd: 7205 case Intrinsic::x86_sse2_ucomigt_sd: 7206 case Intrinsic::x86_sse2_ucomige_sd: 7207 case Intrinsic::x86_sse2_ucomineq_sd: { 7208 unsigned Opc = 0; 7209 ISD::CondCode CC = ISD::SETCC_INVALID; 7210 switch (IntNo) { 7211 default: break; 7212 case Intrinsic::x86_sse_comieq_ss: 7213 case Intrinsic::x86_sse2_comieq_sd: 7214 Opc = X86ISD::COMI; 7215 CC = ISD::SETEQ; 7216 break; 7217 case Intrinsic::x86_sse_comilt_ss: 7218 case Intrinsic::x86_sse2_comilt_sd: 7219 Opc = X86ISD::COMI; 7220 CC = ISD::SETLT; 7221 break; 7222 case Intrinsic::x86_sse_comile_ss: 7223 case Intrinsic::x86_sse2_comile_sd: 7224 Opc = X86ISD::COMI; 7225 CC = ISD::SETLE; 7226 break; 7227 case Intrinsic::x86_sse_comigt_ss: 7228 case Intrinsic::x86_sse2_comigt_sd: 7229 Opc = X86ISD::COMI; 7230 CC = ISD::SETGT; 7231 break; 7232 case Intrinsic::x86_sse_comige_ss: 7233 case Intrinsic::x86_sse2_comige_sd: 7234 Opc = X86ISD::COMI; 7235 CC = ISD::SETGE; 7236 break; 7237 case Intrinsic::x86_sse_comineq_ss: 7238 case Intrinsic::x86_sse2_comineq_sd: 7239 Opc = X86ISD::COMI; 7240 CC = ISD::SETNE; 7241 break; 7242 case Intrinsic::x86_sse_ucomieq_ss: 7243 case Intrinsic::x86_sse2_ucomieq_sd: 7244 Opc = X86ISD::UCOMI; 7245 CC = ISD::SETEQ; 7246 break; 7247 case Intrinsic::x86_sse_ucomilt_ss: 7248 case Intrinsic::x86_sse2_ucomilt_sd: 7249 Opc = X86ISD::UCOMI; 7250 CC = ISD::SETLT; 7251 break; 7252 case Intrinsic::x86_sse_ucomile_ss: 7253 case Intrinsic::x86_sse2_ucomile_sd: 7254 Opc = X86ISD::UCOMI; 7255 CC = ISD::SETLE; 7256 break; 7257 case Intrinsic::x86_sse_ucomigt_ss: 7258 case Intrinsic::x86_sse2_ucomigt_sd: 7259 Opc = X86ISD::UCOMI; 7260 CC = ISD::SETGT; 7261 break; 7262 case Intrinsic::x86_sse_ucomige_ss: 7263 case Intrinsic::x86_sse2_ucomige_sd: 7264 Opc = X86ISD::UCOMI; 7265 CC = ISD::SETGE; 7266 break; 7267 case Intrinsic::x86_sse_ucomineq_ss: 7268 case Intrinsic::x86_sse2_ucomineq_sd: 7269 Opc = X86ISD::UCOMI; 7270 CC = ISD::SETNE; 7271 break; 7272 } 7273 7274 SDValue LHS = Op.getOperand(1); 7275 SDValue RHS = Op.getOperand(2); 7276 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 7277 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 7278 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 7279 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7280 DAG.getConstant(X86CC, MVT::i8), Cond); 7281 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 7282 } 7283 // ptest and testp intrinsics. The intrinsic these come from are designed to 7284 // return an integer value, not just an instruction so lower it to the ptest 7285 // or testp pattern and a setcc for the result. 7286 case Intrinsic::x86_sse41_ptestz: 7287 case Intrinsic::x86_sse41_ptestc: 7288 case Intrinsic::x86_sse41_ptestnzc: 7289 case Intrinsic::x86_avx_ptestz_256: 7290 case Intrinsic::x86_avx_ptestc_256: 7291 case Intrinsic::x86_avx_ptestnzc_256: 7292 case Intrinsic::x86_avx_vtestz_ps: 7293 case Intrinsic::x86_avx_vtestc_ps: 7294 case Intrinsic::x86_avx_vtestnzc_ps: 7295 case Intrinsic::x86_avx_vtestz_pd: 7296 case Intrinsic::x86_avx_vtestc_pd: 7297 case Intrinsic::x86_avx_vtestnzc_pd: 7298 case Intrinsic::x86_avx_vtestz_ps_256: 7299 case Intrinsic::x86_avx_vtestc_ps_256: 7300 case Intrinsic::x86_avx_vtestnzc_ps_256: 7301 case Intrinsic::x86_avx_vtestz_pd_256: 7302 case Intrinsic::x86_avx_vtestc_pd_256: 7303 case Intrinsic::x86_avx_vtestnzc_pd_256: { 7304 bool IsTestPacked = false; 7305 unsigned X86CC = 0; 7306 switch (IntNo) { 7307 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 7308 case Intrinsic::x86_avx_vtestz_ps: 7309 case Intrinsic::x86_avx_vtestz_pd: 7310 case Intrinsic::x86_avx_vtestz_ps_256: 7311 case Intrinsic::x86_avx_vtestz_pd_256: 7312 IsTestPacked = true; // Fallthrough 7313 case Intrinsic::x86_sse41_ptestz: 7314 case Intrinsic::x86_avx_ptestz_256: 7315 // ZF = 1 7316 X86CC = X86::COND_E; 7317 break; 7318 case Intrinsic::x86_avx_vtestc_ps: 7319 case Intrinsic::x86_avx_vtestc_pd: 7320 case Intrinsic::x86_avx_vtestc_ps_256: 7321 case Intrinsic::x86_avx_vtestc_pd_256: 7322 IsTestPacked = true; // Fallthrough 7323 case Intrinsic::x86_sse41_ptestc: 7324 case Intrinsic::x86_avx_ptestc_256: 7325 // CF = 1 7326 X86CC = X86::COND_B; 7327 break; 7328 case Intrinsic::x86_avx_vtestnzc_ps: 7329 case Intrinsic::x86_avx_vtestnzc_pd: 7330 case Intrinsic::x86_avx_vtestnzc_ps_256: 7331 case Intrinsic::x86_avx_vtestnzc_pd_256: 7332 IsTestPacked = true; // Fallthrough 7333 case Intrinsic::x86_sse41_ptestnzc: 7334 case Intrinsic::x86_avx_ptestnzc_256: 7335 // ZF and CF = 0 7336 X86CC = X86::COND_A; 7337 break; 7338 } 7339 7340 SDValue LHS = Op.getOperand(1); 7341 SDValue RHS = Op.getOperand(2); 7342 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 7343 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 7344 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 7345 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 7346 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 7347 } 7348 7349 // Fix vector shift instructions where the last operand is a non-immediate 7350 // i32 value. 7351 case Intrinsic::x86_sse2_pslli_w: 7352 case Intrinsic::x86_sse2_pslli_d: 7353 case Intrinsic::x86_sse2_pslli_q: 7354 case Intrinsic::x86_sse2_psrli_w: 7355 case Intrinsic::x86_sse2_psrli_d: 7356 case Intrinsic::x86_sse2_psrli_q: 7357 case Intrinsic::x86_sse2_psrai_w: 7358 case Intrinsic::x86_sse2_psrai_d: 7359 case Intrinsic::x86_mmx_pslli_w: 7360 case Intrinsic::x86_mmx_pslli_d: 7361 case Intrinsic::x86_mmx_pslli_q: 7362 case Intrinsic::x86_mmx_psrli_w: 7363 case Intrinsic::x86_mmx_psrli_d: 7364 case Intrinsic::x86_mmx_psrli_q: 7365 case Intrinsic::x86_mmx_psrai_w: 7366 case Intrinsic::x86_mmx_psrai_d: { 7367 SDValue ShAmt = Op.getOperand(2); 7368 if (isa<ConstantSDNode>(ShAmt)) 7369 return SDValue(); 7370 7371 unsigned NewIntNo = 0; 7372 EVT ShAmtVT = MVT::v4i32; 7373 switch (IntNo) { 7374 case Intrinsic::x86_sse2_pslli_w: 7375 NewIntNo = Intrinsic::x86_sse2_psll_w; 7376 break; 7377 case Intrinsic::x86_sse2_pslli_d: 7378 NewIntNo = Intrinsic::x86_sse2_psll_d; 7379 break; 7380 case Intrinsic::x86_sse2_pslli_q: 7381 NewIntNo = Intrinsic::x86_sse2_psll_q; 7382 break; 7383 case Intrinsic::x86_sse2_psrli_w: 7384 NewIntNo = Intrinsic::x86_sse2_psrl_w; 7385 break; 7386 case Intrinsic::x86_sse2_psrli_d: 7387 NewIntNo = Intrinsic::x86_sse2_psrl_d; 7388 break; 7389 case Intrinsic::x86_sse2_psrli_q: 7390 NewIntNo = Intrinsic::x86_sse2_psrl_q; 7391 break; 7392 case Intrinsic::x86_sse2_psrai_w: 7393 NewIntNo = Intrinsic::x86_sse2_psra_w; 7394 break; 7395 case Intrinsic::x86_sse2_psrai_d: 7396 NewIntNo = Intrinsic::x86_sse2_psra_d; 7397 break; 7398 default: { 7399 ShAmtVT = MVT::v2i32; 7400 switch (IntNo) { 7401 case Intrinsic::x86_mmx_pslli_w: 7402 NewIntNo = Intrinsic::x86_mmx_psll_w; 7403 break; 7404 case Intrinsic::x86_mmx_pslli_d: 7405 NewIntNo = Intrinsic::x86_mmx_psll_d; 7406 break; 7407 case Intrinsic::x86_mmx_pslli_q: 7408 NewIntNo = Intrinsic::x86_mmx_psll_q; 7409 break; 7410 case Intrinsic::x86_mmx_psrli_w: 7411 NewIntNo = Intrinsic::x86_mmx_psrl_w; 7412 break; 7413 case Intrinsic::x86_mmx_psrli_d: 7414 NewIntNo = Intrinsic::x86_mmx_psrl_d; 7415 break; 7416 case Intrinsic::x86_mmx_psrli_q: 7417 NewIntNo = Intrinsic::x86_mmx_psrl_q; 7418 break; 7419 case Intrinsic::x86_mmx_psrai_w: 7420 NewIntNo = Intrinsic::x86_mmx_psra_w; 7421 break; 7422 case Intrinsic::x86_mmx_psrai_d: 7423 NewIntNo = Intrinsic::x86_mmx_psra_d; 7424 break; 7425 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 7426 } 7427 break; 7428 } 7429 } 7430 7431 // The vector shift intrinsics with scalars uses 32b shift amounts but 7432 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 7433 // to be zero. 7434 SDValue ShOps[4]; 7435 ShOps[0] = ShAmt; 7436 ShOps[1] = DAG.getConstant(0, MVT::i32); 7437 if (ShAmtVT == MVT::v4i32) { 7438 ShOps[2] = DAG.getUNDEF(MVT::i32); 7439 ShOps[3] = DAG.getUNDEF(MVT::i32); 7440 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 7441 } else { 7442 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 7443 } 7444 7445 EVT VT = Op.getValueType(); 7446 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 7447 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7448 DAG.getConstant(NewIntNo, MVT::i32), 7449 Op.getOperand(1), ShAmt); 7450 } 7451 } 7452} 7453 7454SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 7455 SelectionDAG &DAG) const { 7456 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7457 MFI->setReturnAddressIsTaken(true); 7458 7459 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7460 DebugLoc dl = Op.getDebugLoc(); 7461 7462 if (Depth > 0) { 7463 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 7464 SDValue Offset = 7465 DAG.getConstant(TD->getPointerSize(), 7466 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 7467 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7468 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7469 FrameAddr, Offset), 7470 NULL, 0, false, false, 0); 7471 } 7472 7473 // Just load the return address. 7474 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 7475 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7476 RetAddrFI, NULL, 0, false, false, 0); 7477} 7478 7479SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 7480 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7481 MFI->setFrameAddressIsTaken(true); 7482 7483 EVT VT = Op.getValueType(); 7484 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 7485 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7486 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 7487 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 7488 while (Depth--) 7489 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 7490 false, false, 0); 7491 return FrameAddr; 7492} 7493 7494SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 7495 SelectionDAG &DAG) const { 7496 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 7497} 7498 7499SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 7500 MachineFunction &MF = DAG.getMachineFunction(); 7501 SDValue Chain = Op.getOperand(0); 7502 SDValue Offset = Op.getOperand(1); 7503 SDValue Handler = Op.getOperand(2); 7504 DebugLoc dl = Op.getDebugLoc(); 7505 7506 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 7507 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 7508 getPointerTy()); 7509 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 7510 7511 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 7512 DAG.getIntPtrConstant(TD->getPointerSize())); 7513 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 7514 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0); 7515 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 7516 MF.getRegInfo().addLiveOut(StoreAddrReg); 7517 7518 return DAG.getNode(X86ISD::EH_RETURN, dl, 7519 MVT::Other, 7520 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 7521} 7522 7523SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 7524 SelectionDAG &DAG) const { 7525 SDValue Root = Op.getOperand(0); 7526 SDValue Trmp = Op.getOperand(1); // trampoline 7527 SDValue FPtr = Op.getOperand(2); // nested function 7528 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 7529 DebugLoc dl = Op.getDebugLoc(); 7530 7531 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7532 7533 if (Subtarget->is64Bit()) { 7534 SDValue OutChains[6]; 7535 7536 // Large code-model. 7537 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 7538 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 7539 7540 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 7541 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 7542 7543 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 7544 7545 // Load the pointer to the nested function into R11. 7546 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 7547 SDValue Addr = Trmp; 7548 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7549 Addr, TrmpAddr, 0, false, false, 0); 7550 7551 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7552 DAG.getConstant(2, MVT::i64)); 7553 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, 7554 false, false, 2); 7555 7556 // Load the 'nest' parameter value into R10. 7557 // R10 is specified in X86CallingConv.td 7558 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 7559 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7560 DAG.getConstant(10, MVT::i64)); 7561 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7562 Addr, TrmpAddr, 10, false, false, 0); 7563 7564 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7565 DAG.getConstant(12, MVT::i64)); 7566 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, 7567 false, false, 2); 7568 7569 // Jump to the nested function. 7570 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 7571 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7572 DAG.getConstant(20, MVT::i64)); 7573 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7574 Addr, TrmpAddr, 20, false, false, 0); 7575 7576 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 7577 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7578 DAG.getConstant(22, MVT::i64)); 7579 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 7580 TrmpAddr, 22, false, false, 0); 7581 7582 SDValue Ops[] = 7583 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 7584 return DAG.getMergeValues(Ops, 2, dl); 7585 } else { 7586 const Function *Func = 7587 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 7588 CallingConv::ID CC = Func->getCallingConv(); 7589 unsigned NestReg; 7590 7591 switch (CC) { 7592 default: 7593 llvm_unreachable("Unsupported calling convention"); 7594 case CallingConv::C: 7595 case CallingConv::X86_StdCall: { 7596 // Pass 'nest' parameter in ECX. 7597 // Must be kept in sync with X86CallingConv.td 7598 NestReg = X86::ECX; 7599 7600 // Check that ECX wasn't needed by an 'inreg' parameter. 7601 const FunctionType *FTy = Func->getFunctionType(); 7602 const AttrListPtr &Attrs = Func->getAttributes(); 7603 7604 if (!Attrs.isEmpty() && !Func->isVarArg()) { 7605 unsigned InRegCount = 0; 7606 unsigned Idx = 1; 7607 7608 for (FunctionType::param_iterator I = FTy->param_begin(), 7609 E = FTy->param_end(); I != E; ++I, ++Idx) 7610 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 7611 // FIXME: should only count parameters that are lowered to integers. 7612 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 7613 7614 if (InRegCount > 2) { 7615 report_fatal_error("Nest register in use - reduce number of inreg" 7616 " parameters!"); 7617 } 7618 } 7619 break; 7620 } 7621 case CallingConv::X86_FastCall: 7622 case CallingConv::X86_ThisCall: 7623 case CallingConv::Fast: 7624 // Pass 'nest' parameter in EAX. 7625 // Must be kept in sync with X86CallingConv.td 7626 NestReg = X86::EAX; 7627 break; 7628 } 7629 7630 SDValue OutChains[4]; 7631 SDValue Addr, Disp; 7632 7633 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7634 DAG.getConstant(10, MVT::i32)); 7635 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 7636 7637 // This is storing the opcode for MOV32ri. 7638 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 7639 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 7640 OutChains[0] = DAG.getStore(Root, dl, 7641 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 7642 Trmp, TrmpAddr, 0, false, false, 0); 7643 7644 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7645 DAG.getConstant(1, MVT::i32)); 7646 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, 7647 false, false, 1); 7648 7649 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 7650 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7651 DAG.getConstant(5, MVT::i32)); 7652 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 7653 TrmpAddr, 5, false, false, 1); 7654 7655 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7656 DAG.getConstant(6, MVT::i32)); 7657 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, 7658 false, false, 1); 7659 7660 SDValue Ops[] = 7661 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 7662 return DAG.getMergeValues(Ops, 2, dl); 7663 } 7664} 7665 7666SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 7667 SelectionDAG &DAG) const { 7668 /* 7669 The rounding mode is in bits 11:10 of FPSR, and has the following 7670 settings: 7671 00 Round to nearest 7672 01 Round to -inf 7673 10 Round to +inf 7674 11 Round to 0 7675 7676 FLT_ROUNDS, on the other hand, expects the following: 7677 -1 Undefined 7678 0 Round to 0 7679 1 Round to nearest 7680 2 Round to +inf 7681 3 Round to -inf 7682 7683 To perform the conversion, we do: 7684 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 7685 */ 7686 7687 MachineFunction &MF = DAG.getMachineFunction(); 7688 const TargetMachine &TM = MF.getTarget(); 7689 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 7690 unsigned StackAlignment = TFI.getStackAlignment(); 7691 EVT VT = Op.getValueType(); 7692 DebugLoc dl = Op.getDebugLoc(); 7693 7694 // Save FP Control Word to stack slot 7695 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 7696 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7697 7698 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 7699 DAG.getEntryNode(), StackSlot); 7700 7701 // Load FP Control Word from stack slot 7702 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0, 7703 false, false, 0); 7704 7705 // Transform as necessary 7706 SDValue CWD1 = 7707 DAG.getNode(ISD::SRL, dl, MVT::i16, 7708 DAG.getNode(ISD::AND, dl, MVT::i16, 7709 CWD, DAG.getConstant(0x800, MVT::i16)), 7710 DAG.getConstant(11, MVT::i8)); 7711 SDValue CWD2 = 7712 DAG.getNode(ISD::SRL, dl, MVT::i16, 7713 DAG.getNode(ISD::AND, dl, MVT::i16, 7714 CWD, DAG.getConstant(0x400, MVT::i16)), 7715 DAG.getConstant(9, MVT::i8)); 7716 7717 SDValue RetVal = 7718 DAG.getNode(ISD::AND, dl, MVT::i16, 7719 DAG.getNode(ISD::ADD, dl, MVT::i16, 7720 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 7721 DAG.getConstant(1, MVT::i16)), 7722 DAG.getConstant(3, MVT::i16)); 7723 7724 7725 return DAG.getNode((VT.getSizeInBits() < 16 ? 7726 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 7727} 7728 7729SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 7730 EVT VT = Op.getValueType(); 7731 EVT OpVT = VT; 7732 unsigned NumBits = VT.getSizeInBits(); 7733 DebugLoc dl = Op.getDebugLoc(); 7734 7735 Op = Op.getOperand(0); 7736 if (VT == MVT::i8) { 7737 // Zero extend to i32 since there is not an i8 bsr. 7738 OpVT = MVT::i32; 7739 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7740 } 7741 7742 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 7743 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7744 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 7745 7746 // If src is zero (i.e. bsr sets ZF), returns NumBits. 7747 SDValue Ops[] = { 7748 Op, 7749 DAG.getConstant(NumBits+NumBits-1, OpVT), 7750 DAG.getConstant(X86::COND_E, MVT::i8), 7751 Op.getValue(1) 7752 }; 7753 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7754 7755 // Finally xor with NumBits-1. 7756 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 7757 7758 if (VT == MVT::i8) 7759 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7760 return Op; 7761} 7762 7763SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 7764 EVT VT = Op.getValueType(); 7765 EVT OpVT = VT; 7766 unsigned NumBits = VT.getSizeInBits(); 7767 DebugLoc dl = Op.getDebugLoc(); 7768 7769 Op = Op.getOperand(0); 7770 if (VT == MVT::i8) { 7771 OpVT = MVT::i32; 7772 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7773 } 7774 7775 // Issue a bsf (scan bits forward) which also sets EFLAGS. 7776 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7777 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 7778 7779 // If src is zero (i.e. bsf sets ZF), returns NumBits. 7780 SDValue Ops[] = { 7781 Op, 7782 DAG.getConstant(NumBits, OpVT), 7783 DAG.getConstant(X86::COND_E, MVT::i8), 7784 Op.getValue(1) 7785 }; 7786 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7787 7788 if (VT == MVT::i8) 7789 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7790 return Op; 7791} 7792 7793SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const { 7794 EVT VT = Op.getValueType(); 7795 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 7796 DebugLoc dl = Op.getDebugLoc(); 7797 7798 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 7799 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 7800 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 7801 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 7802 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 7803 // 7804 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 7805 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 7806 // return AloBlo + AloBhi + AhiBlo; 7807 7808 SDValue A = Op.getOperand(0); 7809 SDValue B = Op.getOperand(1); 7810 7811 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7812 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7813 A, DAG.getConstant(32, MVT::i32)); 7814 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7815 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7816 B, DAG.getConstant(32, MVT::i32)); 7817 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7818 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7819 A, B); 7820 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7821 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7822 A, Bhi); 7823 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7824 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7825 Ahi, B); 7826 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7827 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7828 AloBhi, DAG.getConstant(32, MVT::i32)); 7829 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7830 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7831 AhiBlo, DAG.getConstant(32, MVT::i32)); 7832 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 7833 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 7834 return Res; 7835} 7836 7837SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const { 7838 EVT VT = Op.getValueType(); 7839 DebugLoc dl = Op.getDebugLoc(); 7840 SDValue R = Op.getOperand(0); 7841 7842 LLVMContext *Context = DAG.getContext(); 7843 7844 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later"); 7845 7846 if (VT == MVT::v4i32) { 7847 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7848 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 7849 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 7850 7851 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 7852 7853 std::vector<Constant*> CV(4, CI); 7854 Constant *C = ConstantVector::get(CV); 7855 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7856 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7857 PseudoSourceValue::getConstantPool(), 0, 7858 false, false, 16); 7859 7860 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 7861 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op); 7862 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 7863 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 7864 } 7865 if (VT == MVT::v16i8) { 7866 // a = a << 5; 7867 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7868 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 7869 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 7870 7871 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 7872 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 7873 7874 std::vector<Constant*> CVM1(16, CM1); 7875 std::vector<Constant*> CVM2(16, CM2); 7876 Constant *C = ConstantVector::get(CVM1); 7877 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7878 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7879 PseudoSourceValue::getConstantPool(), 0, 7880 false, false, 16); 7881 7882 // r = pblendv(r, psllw(r & (char16)15, 4), a); 7883 M = DAG.getNode(ISD::AND, dl, VT, R, M); 7884 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7885 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 7886 DAG.getConstant(4, MVT::i32)); 7887 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7888 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 7889 R, M, Op); 7890 // a += a 7891 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 7892 7893 C = ConstantVector::get(CVM2); 7894 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7895 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7896 PseudoSourceValue::getConstantPool(), 0, false, false, 16); 7897 7898 // r = pblendv(r, psllw(r & (char16)63, 2), a); 7899 M = DAG.getNode(ISD::AND, dl, VT, R, M); 7900 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7901 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 7902 DAG.getConstant(2, MVT::i32)); 7903 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7904 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 7905 R, M, Op); 7906 // a += a 7907 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 7908 7909 // return pblendv(r, r+r, a); 7910 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7911 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32), 7912 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); 7913 return R; 7914 } 7915 return SDValue(); 7916} 7917 7918SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 7919 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 7920 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 7921 // looks for this combo and may remove the "setcc" instruction if the "setcc" 7922 // has only one use. 7923 SDNode *N = Op.getNode(); 7924 SDValue LHS = N->getOperand(0); 7925 SDValue RHS = N->getOperand(1); 7926 unsigned BaseOp = 0; 7927 unsigned Cond = 0; 7928 DebugLoc dl = Op.getDebugLoc(); 7929 7930 switch (Op.getOpcode()) { 7931 default: llvm_unreachable("Unknown ovf instruction!"); 7932 case ISD::SADDO: 7933 // A subtract of one will be selected as a INC. Note that INC doesn't 7934 // set CF, so we can't do this for UADDO. 7935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7936 if (C->getAPIntValue() == 1) { 7937 BaseOp = X86ISD::INC; 7938 Cond = X86::COND_O; 7939 break; 7940 } 7941 BaseOp = X86ISD::ADD; 7942 Cond = X86::COND_O; 7943 break; 7944 case ISD::UADDO: 7945 BaseOp = X86ISD::ADD; 7946 Cond = X86::COND_B; 7947 break; 7948 case ISD::SSUBO: 7949 // A subtract of one will be selected as a DEC. Note that DEC doesn't 7950 // set CF, so we can't do this for USUBO. 7951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7952 if (C->getAPIntValue() == 1) { 7953 BaseOp = X86ISD::DEC; 7954 Cond = X86::COND_O; 7955 break; 7956 } 7957 BaseOp = X86ISD::SUB; 7958 Cond = X86::COND_O; 7959 break; 7960 case ISD::USUBO: 7961 BaseOp = X86ISD::SUB; 7962 Cond = X86::COND_B; 7963 break; 7964 case ISD::SMULO: 7965 BaseOp = X86ISD::SMUL; 7966 Cond = X86::COND_O; 7967 break; 7968 case ISD::UMULO: 7969 BaseOp = X86ISD::UMUL; 7970 Cond = X86::COND_B; 7971 break; 7972 } 7973 7974 // Also sets EFLAGS. 7975 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 7976 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 7977 7978 SDValue SetCC = 7979 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 7980 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 7981 7982 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 7983 return Sum; 7984} 7985 7986SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 7987 DebugLoc dl = Op.getDebugLoc(); 7988 7989 if (!Subtarget->hasSSE2()) { 7990 SDValue Chain = Op.getOperand(0); 7991 SDValue Zero = DAG.getConstant(0, 7992 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 7993 SDValue Ops[] = { 7994 DAG.getRegister(X86::ESP, MVT::i32), // Base 7995 DAG.getTargetConstant(1, MVT::i8), // Scale 7996 DAG.getRegister(0, MVT::i32), // Index 7997 DAG.getTargetConstant(0, MVT::i32), // Disp 7998 DAG.getRegister(0, MVT::i32), // Segment. 7999 Zero, 8000 Chain 8001 }; 8002 SDNode *Res = 8003 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 8004 array_lengthof(Ops)); 8005 return SDValue(Res, 0); 8006 } 8007 8008 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 8009 if (!isDev) 8010 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 8011 8012 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 8013 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 8014 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 8015 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 8016 8017 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 8018 if (!Op1 && !Op2 && !Op3 && Op4) 8019 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 8020 8021 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 8022 if (Op1 && !Op2 && !Op3 && !Op4) 8023 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 8024 8025 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 8026 // (MFENCE)>; 8027 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 8028} 8029 8030SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 8031 EVT T = Op.getValueType(); 8032 DebugLoc dl = Op.getDebugLoc(); 8033 unsigned Reg = 0; 8034 unsigned size = 0; 8035 switch(T.getSimpleVT().SimpleTy) { 8036 default: 8037 assert(false && "Invalid value type!"); 8038 case MVT::i8: Reg = X86::AL; size = 1; break; 8039 case MVT::i16: Reg = X86::AX; size = 2; break; 8040 case MVT::i32: Reg = X86::EAX; size = 4; break; 8041 case MVT::i64: 8042 assert(Subtarget->is64Bit() && "Node not type legal!"); 8043 Reg = X86::RAX; size = 8; 8044 break; 8045 } 8046 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 8047 Op.getOperand(2), SDValue()); 8048 SDValue Ops[] = { cpIn.getValue(0), 8049 Op.getOperand(1), 8050 Op.getOperand(3), 8051 DAG.getTargetConstant(size, MVT::i8), 8052 cpIn.getValue(1) }; 8053 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8054 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 8055 SDValue cpOut = 8056 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 8057 return cpOut; 8058} 8059 8060SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 8061 SelectionDAG &DAG) const { 8062 assert(Subtarget->is64Bit() && "Result not type legalized?"); 8063 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8064 SDValue TheChain = Op.getOperand(0); 8065 DebugLoc dl = Op.getDebugLoc(); 8066 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 8067 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 8068 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 8069 rax.getValue(2)); 8070 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 8071 DAG.getConstant(32, MVT::i8)); 8072 SDValue Ops[] = { 8073 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 8074 rdx.getValue(1) 8075 }; 8076 return DAG.getMergeValues(Ops, 2, dl); 8077} 8078 8079SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op, 8080 SelectionDAG &DAG) const { 8081 EVT SrcVT = Op.getOperand(0).getValueType(); 8082 EVT DstVT = Op.getValueType(); 8083 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() && 8084 Subtarget->hasMMX() && !DisableMMX) && 8085 "Unexpected custom BIT_CONVERT"); 8086 assert((DstVT == MVT::i64 || 8087 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 8088 "Unexpected custom BIT_CONVERT"); 8089 // i64 <=> MMX conversions are Legal. 8090 if (SrcVT==MVT::i64 && DstVT.isVector()) 8091 return Op; 8092 if (DstVT==MVT::i64 && SrcVT.isVector()) 8093 return Op; 8094 // MMX <=> MMX conversions are Legal. 8095 if (SrcVT.isVector() && DstVT.isVector()) 8096 return Op; 8097 // All other conversions need to be expanded. 8098 return SDValue(); 8099} 8100SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 8101 SDNode *Node = Op.getNode(); 8102 DebugLoc dl = Node->getDebugLoc(); 8103 EVT T = Node->getValueType(0); 8104 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 8105 DAG.getConstant(0, T), Node->getOperand(2)); 8106 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 8107 cast<AtomicSDNode>(Node)->getMemoryVT(), 8108 Node->getOperand(0), 8109 Node->getOperand(1), negOp, 8110 cast<AtomicSDNode>(Node)->getSrcValue(), 8111 cast<AtomicSDNode>(Node)->getAlignment()); 8112} 8113 8114/// LowerOperation - Provide custom lowering hooks for some operations. 8115/// 8116SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 8117 switch (Op.getOpcode()) { 8118 default: llvm_unreachable("Should not custom lower this!"); 8119 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 8120 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 8121 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 8122 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 8123 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 8124 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 8125 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 8126 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 8127 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 8128 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 8129 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 8130 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 8131 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 8132 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 8133 case ISD::SHL_PARTS: 8134 case ISD::SRA_PARTS: 8135 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 8136 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 8137 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 8138 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 8139 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 8140 case ISD::FABS: return LowerFABS(Op, DAG); 8141 case ISD::FNEG: return LowerFNEG(Op, DAG); 8142 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 8143 case ISD::SETCC: return LowerSETCC(Op, DAG); 8144 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 8145 case ISD::SELECT: return LowerSELECT(Op, DAG); 8146 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 8147 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 8148 case ISD::VASTART: return LowerVASTART(Op, DAG); 8149 case ISD::VAARG: return LowerVAARG(Op, DAG); 8150 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 8151 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 8152 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 8153 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 8154 case ISD::FRAME_TO_ARGS_OFFSET: 8155 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 8156 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 8157 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 8158 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 8159 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 8160 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 8161 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 8162 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 8163 case ISD::SHL: return LowerSHL(Op, DAG); 8164 case ISD::SADDO: 8165 case ISD::UADDO: 8166 case ISD::SSUBO: 8167 case ISD::USUBO: 8168 case ISD::SMULO: 8169 case ISD::UMULO: return LowerXALUO(Op, DAG); 8170 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 8171 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); 8172 } 8173} 8174 8175void X86TargetLowering:: 8176ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 8177 SelectionDAG &DAG, unsigned NewOp) const { 8178 EVT T = Node->getValueType(0); 8179 DebugLoc dl = Node->getDebugLoc(); 8180 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 8181 8182 SDValue Chain = Node->getOperand(0); 8183 SDValue In1 = Node->getOperand(1); 8184 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 8185 Node->getOperand(2), DAG.getIntPtrConstant(0)); 8186 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 8187 Node->getOperand(2), DAG.getIntPtrConstant(1)); 8188 SDValue Ops[] = { Chain, In1, In2L, In2H }; 8189 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 8190 SDValue Result = 8191 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 8192 cast<MemSDNode>(Node)->getMemOperand()); 8193 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 8194 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 8195 Results.push_back(Result.getValue(2)); 8196} 8197 8198/// ReplaceNodeResults - Replace a node with an illegal result type 8199/// with a new node built out of custom code. 8200void X86TargetLowering::ReplaceNodeResults(SDNode *N, 8201 SmallVectorImpl<SDValue>&Results, 8202 SelectionDAG &DAG) const { 8203 DebugLoc dl = N->getDebugLoc(); 8204 switch (N->getOpcode()) { 8205 default: 8206 assert(false && "Do not know how to custom type legalize this operation!"); 8207 return; 8208 case ISD::FP_TO_SINT: { 8209 std::pair<SDValue,SDValue> Vals = 8210 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 8211 SDValue FIST = Vals.first, StackSlot = Vals.second; 8212 if (FIST.getNode() != 0) { 8213 EVT VT = N->getValueType(0); 8214 // Return a load from the stack slot. 8215 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0, 8216 false, false, 0)); 8217 } 8218 return; 8219 } 8220 case ISD::READCYCLECOUNTER: { 8221 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8222 SDValue TheChain = N->getOperand(0); 8223 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 8224 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 8225 rd.getValue(1)); 8226 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 8227 eax.getValue(2)); 8228 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 8229 SDValue Ops[] = { eax, edx }; 8230 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 8231 Results.push_back(edx.getValue(1)); 8232 return; 8233 } 8234 case ISD::ATOMIC_CMP_SWAP: { 8235 EVT T = N->getValueType(0); 8236 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 8237 SDValue cpInL, cpInH; 8238 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 8239 DAG.getConstant(0, MVT::i32)); 8240 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 8241 DAG.getConstant(1, MVT::i32)); 8242 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 8243 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 8244 cpInL.getValue(1)); 8245 SDValue swapInL, swapInH; 8246 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 8247 DAG.getConstant(0, MVT::i32)); 8248 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 8249 DAG.getConstant(1, MVT::i32)); 8250 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 8251 cpInH.getValue(1)); 8252 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 8253 swapInL.getValue(1)); 8254 SDValue Ops[] = { swapInH.getValue(0), 8255 N->getOperand(1), 8256 swapInH.getValue(1) }; 8257 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 8258 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 8259 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 8260 MVT::i32, Result.getValue(1)); 8261 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 8262 MVT::i32, cpOutL.getValue(2)); 8263 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 8264 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 8265 Results.push_back(cpOutH.getValue(1)); 8266 return; 8267 } 8268 case ISD::ATOMIC_LOAD_ADD: 8269 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 8270 return; 8271 case ISD::ATOMIC_LOAD_AND: 8272 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 8273 return; 8274 case ISD::ATOMIC_LOAD_NAND: 8275 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 8276 return; 8277 case ISD::ATOMIC_LOAD_OR: 8278 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 8279 return; 8280 case ISD::ATOMIC_LOAD_SUB: 8281 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 8282 return; 8283 case ISD::ATOMIC_LOAD_XOR: 8284 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 8285 return; 8286 case ISD::ATOMIC_SWAP: 8287 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 8288 return; 8289 } 8290} 8291 8292const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 8293 switch (Opcode) { 8294 default: return NULL; 8295 case X86ISD::BSF: return "X86ISD::BSF"; 8296 case X86ISD::BSR: return "X86ISD::BSR"; 8297 case X86ISD::SHLD: return "X86ISD::SHLD"; 8298 case X86ISD::SHRD: return "X86ISD::SHRD"; 8299 case X86ISD::FAND: return "X86ISD::FAND"; 8300 case X86ISD::FOR: return "X86ISD::FOR"; 8301 case X86ISD::FXOR: return "X86ISD::FXOR"; 8302 case X86ISD::FSRL: return "X86ISD::FSRL"; 8303 case X86ISD::FILD: return "X86ISD::FILD"; 8304 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 8305 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 8306 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 8307 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 8308 case X86ISD::FLD: return "X86ISD::FLD"; 8309 case X86ISD::FST: return "X86ISD::FST"; 8310 case X86ISD::CALL: return "X86ISD::CALL"; 8311 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 8312 case X86ISD::BT: return "X86ISD::BT"; 8313 case X86ISD::CMP: return "X86ISD::CMP"; 8314 case X86ISD::COMI: return "X86ISD::COMI"; 8315 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 8316 case X86ISD::SETCC: return "X86ISD::SETCC"; 8317 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 8318 case X86ISD::CMOV: return "X86ISD::CMOV"; 8319 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 8320 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 8321 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 8322 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 8323 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 8324 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 8325 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 8326 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 8327 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 8328 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 8329 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 8330 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 8331 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW"; 8332 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 8333 case X86ISD::FMAX: return "X86ISD::FMAX"; 8334 case X86ISD::FMIN: return "X86ISD::FMIN"; 8335 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 8336 case X86ISD::FRCP: return "X86ISD::FRCP"; 8337 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 8338 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 8339 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 8340 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 8341 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 8342 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 8343 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 8344 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 8345 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 8346 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 8347 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 8348 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 8349 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 8350 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 8351 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 8352 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 8353 case X86ISD::VSHL: return "X86ISD::VSHL"; 8354 case X86ISD::VSRL: return "X86ISD::VSRL"; 8355 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 8356 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 8357 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 8358 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 8359 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 8360 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 8361 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 8362 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 8363 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 8364 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 8365 case X86ISD::ADD: return "X86ISD::ADD"; 8366 case X86ISD::SUB: return "X86ISD::SUB"; 8367 case X86ISD::SMUL: return "X86ISD::SMUL"; 8368 case X86ISD::UMUL: return "X86ISD::UMUL"; 8369 case X86ISD::INC: return "X86ISD::INC"; 8370 case X86ISD::DEC: return "X86ISD::DEC"; 8371 case X86ISD::OR: return "X86ISD::OR"; 8372 case X86ISD::XOR: return "X86ISD::XOR"; 8373 case X86ISD::AND: return "X86ISD::AND"; 8374 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 8375 case X86ISD::PTEST: return "X86ISD::PTEST"; 8376 case X86ISD::TESTP: return "X86ISD::TESTP"; 8377 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 8378 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 8379 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 8380 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 8381 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 8382 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 8383 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 8384 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 8385 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 8386 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 8387 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 8388 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 8389 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 8390 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 8391 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 8392 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 8393 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 8394 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 8395 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 8396 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 8397 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 8398 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 8399 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 8400 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 8401 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 8402 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 8403 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 8404 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 8405 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 8406 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 8407 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 8408 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 8409 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA"; 8410 } 8411} 8412 8413// isLegalAddressingMode - Return true if the addressing mode represented 8414// by AM is legal for this target, for a load/store of the specified type. 8415bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 8416 const Type *Ty) const { 8417 // X86 supports extremely general addressing modes. 8418 CodeModel::Model M = getTargetMachine().getCodeModel(); 8419 Reloc::Model R = getTargetMachine().getRelocationModel(); 8420 8421 // X86 allows a sign-extended 32-bit immediate field as a displacement. 8422 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 8423 return false; 8424 8425 if (AM.BaseGV) { 8426 unsigned GVFlags = 8427 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 8428 8429 // If a reference to this global requires an extra load, we can't fold it. 8430 if (isGlobalStubReference(GVFlags)) 8431 return false; 8432 8433 // If BaseGV requires a register for the PIC base, we cannot also have a 8434 // BaseReg specified. 8435 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 8436 return false; 8437 8438 // If lower 4G is not available, then we must use rip-relative addressing. 8439 if ((M != CodeModel::Small || R != Reloc::Static) && 8440 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 8441 return false; 8442 } 8443 8444 switch (AM.Scale) { 8445 case 0: 8446 case 1: 8447 case 2: 8448 case 4: 8449 case 8: 8450 // These scales always work. 8451 break; 8452 case 3: 8453 case 5: 8454 case 9: 8455 // These scales are formed with basereg+scalereg. Only accept if there is 8456 // no basereg yet. 8457 if (AM.HasBaseReg) 8458 return false; 8459 break; 8460 default: // Other stuff never works. 8461 return false; 8462 } 8463 8464 return true; 8465} 8466 8467 8468bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 8469 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 8470 return false; 8471 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 8472 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 8473 if (NumBits1 <= NumBits2) 8474 return false; 8475 return true; 8476} 8477 8478bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 8479 if (!VT1.isInteger() || !VT2.isInteger()) 8480 return false; 8481 unsigned NumBits1 = VT1.getSizeInBits(); 8482 unsigned NumBits2 = VT2.getSizeInBits(); 8483 if (NumBits1 <= NumBits2) 8484 return false; 8485 return true; 8486} 8487 8488bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 8489 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 8490 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 8491} 8492 8493bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 8494 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 8495 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 8496} 8497 8498bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 8499 // i16 instructions are longer (0x66 prefix) and potentially slower. 8500 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 8501} 8502 8503/// isShuffleMaskLegal - Targets can use this to indicate that they only 8504/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 8505/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 8506/// are assumed to be legal. 8507bool 8508X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 8509 EVT VT) const { 8510 // Very little shuffling can be done for 64-bit vectors right now. 8511 if (VT.getSizeInBits() == 64) 8512 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()); 8513 8514 // FIXME: pshufb, blends, shifts. 8515 return (VT.getVectorNumElements() == 2 || 8516 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 8517 isMOVLMask(M, VT) || 8518 isSHUFPMask(M, VT) || 8519 isPSHUFDMask(M, VT) || 8520 isPSHUFHWMask(M, VT) || 8521 isPSHUFLWMask(M, VT) || 8522 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 8523 isUNPCKLMask(M, VT) || 8524 isUNPCKHMask(M, VT) || 8525 isUNPCKL_v_undef_Mask(M, VT) || 8526 isUNPCKH_v_undef_Mask(M, VT)); 8527} 8528 8529bool 8530X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 8531 EVT VT) const { 8532 unsigned NumElts = VT.getVectorNumElements(); 8533 // FIXME: This collection of masks seems suspect. 8534 if (NumElts == 2) 8535 return true; 8536 if (NumElts == 4 && VT.getSizeInBits() == 128) { 8537 return (isMOVLMask(Mask, VT) || 8538 isCommutedMOVLMask(Mask, VT, true) || 8539 isSHUFPMask(Mask, VT) || 8540 isCommutedSHUFPMask(Mask, VT)); 8541 } 8542 return false; 8543} 8544 8545//===----------------------------------------------------------------------===// 8546// X86 Scheduler Hooks 8547//===----------------------------------------------------------------------===// 8548 8549// private utility function 8550MachineBasicBlock * 8551X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 8552 MachineBasicBlock *MBB, 8553 unsigned regOpc, 8554 unsigned immOpc, 8555 unsigned LoadOpc, 8556 unsigned CXchgOpc, 8557 unsigned notOpc, 8558 unsigned EAXreg, 8559 TargetRegisterClass *RC, 8560 bool invSrc) const { 8561 // For the atomic bitwise operator, we generate 8562 // thisMBB: 8563 // newMBB: 8564 // ld t1 = [bitinstr.addr] 8565 // op t2 = t1, [bitinstr.val] 8566 // mov EAX = t1 8567 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8568 // bz newMBB 8569 // fallthrough -->nextMBB 8570 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8571 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8572 MachineFunction::iterator MBBIter = MBB; 8573 ++MBBIter; 8574 8575 /// First build the CFG 8576 MachineFunction *F = MBB->getParent(); 8577 MachineBasicBlock *thisMBB = MBB; 8578 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8579 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8580 F->insert(MBBIter, newMBB); 8581 F->insert(MBBIter, nextMBB); 8582 8583 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8584 nextMBB->splice(nextMBB->begin(), thisMBB, 8585 llvm::next(MachineBasicBlock::iterator(bInstr)), 8586 thisMBB->end()); 8587 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8588 8589 // Update thisMBB to fall through to newMBB 8590 thisMBB->addSuccessor(newMBB); 8591 8592 // newMBB jumps to itself and fall through to nextMBB 8593 newMBB->addSuccessor(nextMBB); 8594 newMBB->addSuccessor(newMBB); 8595 8596 // Insert instructions into newMBB based on incoming instruction 8597 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 8598 "unexpected number of operands"); 8599 DebugLoc dl = bInstr->getDebugLoc(); 8600 MachineOperand& destOper = bInstr->getOperand(0); 8601 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8602 int numArgs = bInstr->getNumOperands() - 1; 8603 for (int i=0; i < numArgs; ++i) 8604 argOpers[i] = &bInstr->getOperand(i+1); 8605 8606 // x86 address has 4 operands: base, index, scale, and displacement 8607 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8608 int valArgIndx = lastAddrIndx + 1; 8609 8610 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8611 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 8612 for (int i=0; i <= lastAddrIndx; ++i) 8613 (*MIB).addOperand(*argOpers[i]); 8614 8615 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 8616 if (invSrc) { 8617 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 8618 } 8619 else 8620 tt = t1; 8621 8622 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8623 assert((argOpers[valArgIndx]->isReg() || 8624 argOpers[valArgIndx]->isImm()) && 8625 "invalid operand"); 8626 if (argOpers[valArgIndx]->isReg()) 8627 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 8628 else 8629 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 8630 MIB.addReg(tt); 8631 (*MIB).addOperand(*argOpers[valArgIndx]); 8632 8633 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 8634 MIB.addReg(t1); 8635 8636 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 8637 for (int i=0; i <= lastAddrIndx; ++i) 8638 (*MIB).addOperand(*argOpers[i]); 8639 MIB.addReg(t2); 8640 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8641 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8642 bInstr->memoperands_end()); 8643 8644 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 8645 MIB.addReg(EAXreg); 8646 8647 // insert branch 8648 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8649 8650 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 8651 return nextMBB; 8652} 8653 8654// private utility function: 64 bit atomics on 32 bit host. 8655MachineBasicBlock * 8656X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 8657 MachineBasicBlock *MBB, 8658 unsigned regOpcL, 8659 unsigned regOpcH, 8660 unsigned immOpcL, 8661 unsigned immOpcH, 8662 bool invSrc) const { 8663 // For the atomic bitwise operator, we generate 8664 // thisMBB (instructions are in pairs, except cmpxchg8b) 8665 // ld t1,t2 = [bitinstr.addr] 8666 // newMBB: 8667 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 8668 // op t5, t6 <- out1, out2, [bitinstr.val] 8669 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 8670 // mov ECX, EBX <- t5, t6 8671 // mov EAX, EDX <- t1, t2 8672 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 8673 // mov t3, t4 <- EAX, EDX 8674 // bz newMBB 8675 // result in out1, out2 8676 // fallthrough -->nextMBB 8677 8678 const TargetRegisterClass *RC = X86::GR32RegisterClass; 8679 const unsigned LoadOpc = X86::MOV32rm; 8680 const unsigned NotOpc = X86::NOT32r; 8681 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8682 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8683 MachineFunction::iterator MBBIter = MBB; 8684 ++MBBIter; 8685 8686 /// First build the CFG 8687 MachineFunction *F = MBB->getParent(); 8688 MachineBasicBlock *thisMBB = MBB; 8689 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8690 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8691 F->insert(MBBIter, newMBB); 8692 F->insert(MBBIter, nextMBB); 8693 8694 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8695 nextMBB->splice(nextMBB->begin(), thisMBB, 8696 llvm::next(MachineBasicBlock::iterator(bInstr)), 8697 thisMBB->end()); 8698 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8699 8700 // Update thisMBB to fall through to newMBB 8701 thisMBB->addSuccessor(newMBB); 8702 8703 // newMBB jumps to itself and fall through to nextMBB 8704 newMBB->addSuccessor(nextMBB); 8705 newMBB->addSuccessor(newMBB); 8706 8707 DebugLoc dl = bInstr->getDebugLoc(); 8708 // Insert instructions into newMBB based on incoming instruction 8709 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 8710 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 8711 "unexpected number of operands"); 8712 MachineOperand& dest1Oper = bInstr->getOperand(0); 8713 MachineOperand& dest2Oper = bInstr->getOperand(1); 8714 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8715 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 8716 argOpers[i] = &bInstr->getOperand(i+2); 8717 8718 // We use some of the operands multiple times, so conservatively just 8719 // clear any kill flags that might be present. 8720 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 8721 argOpers[i]->setIsKill(false); 8722 } 8723 8724 // x86 address has 5 operands: base, index, scale, displacement, and segment. 8725 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8726 8727 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8728 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 8729 for (int i=0; i <= lastAddrIndx; ++i) 8730 (*MIB).addOperand(*argOpers[i]); 8731 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8732 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 8733 // add 4 to displacement. 8734 for (int i=0; i <= lastAddrIndx-2; ++i) 8735 (*MIB).addOperand(*argOpers[i]); 8736 MachineOperand newOp3 = *(argOpers[3]); 8737 if (newOp3.isImm()) 8738 newOp3.setImm(newOp3.getImm()+4); 8739 else 8740 newOp3.setOffset(newOp3.getOffset()+4); 8741 (*MIB).addOperand(newOp3); 8742 (*MIB).addOperand(*argOpers[lastAddrIndx]); 8743 8744 // t3/4 are defined later, at the bottom of the loop 8745 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 8746 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 8747 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 8748 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 8749 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 8750 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 8751 8752 // The subsequent operations should be using the destination registers of 8753 //the PHI instructions. 8754 if (invSrc) { 8755 t1 = F->getRegInfo().createVirtualRegister(RC); 8756 t2 = F->getRegInfo().createVirtualRegister(RC); 8757 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 8758 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 8759 } else { 8760 t1 = dest1Oper.getReg(); 8761 t2 = dest2Oper.getReg(); 8762 } 8763 8764 int valArgIndx = lastAddrIndx + 1; 8765 assert((argOpers[valArgIndx]->isReg() || 8766 argOpers[valArgIndx]->isImm()) && 8767 "invalid operand"); 8768 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 8769 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 8770 if (argOpers[valArgIndx]->isReg()) 8771 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 8772 else 8773 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 8774 if (regOpcL != X86::MOV32rr) 8775 MIB.addReg(t1); 8776 (*MIB).addOperand(*argOpers[valArgIndx]); 8777 assert(argOpers[valArgIndx + 1]->isReg() == 8778 argOpers[valArgIndx]->isReg()); 8779 assert(argOpers[valArgIndx + 1]->isImm() == 8780 argOpers[valArgIndx]->isImm()); 8781 if (argOpers[valArgIndx + 1]->isReg()) 8782 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 8783 else 8784 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 8785 if (regOpcH != X86::MOV32rr) 8786 MIB.addReg(t2); 8787 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 8788 8789 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 8790 MIB.addReg(t1); 8791 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 8792 MIB.addReg(t2); 8793 8794 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 8795 MIB.addReg(t5); 8796 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 8797 MIB.addReg(t6); 8798 8799 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 8800 for (int i=0; i <= lastAddrIndx; ++i) 8801 (*MIB).addOperand(*argOpers[i]); 8802 8803 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8804 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8805 bInstr->memoperands_end()); 8806 8807 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 8808 MIB.addReg(X86::EAX); 8809 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 8810 MIB.addReg(X86::EDX); 8811 8812 // insert branch 8813 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8814 8815 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 8816 return nextMBB; 8817} 8818 8819// private utility function 8820MachineBasicBlock * 8821X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 8822 MachineBasicBlock *MBB, 8823 unsigned cmovOpc) const { 8824 // For the atomic min/max operator, we generate 8825 // thisMBB: 8826 // newMBB: 8827 // ld t1 = [min/max.addr] 8828 // mov t2 = [min/max.val] 8829 // cmp t1, t2 8830 // cmov[cond] t2 = t1 8831 // mov EAX = t1 8832 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8833 // bz newMBB 8834 // fallthrough -->nextMBB 8835 // 8836 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8837 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8838 MachineFunction::iterator MBBIter = MBB; 8839 ++MBBIter; 8840 8841 /// First build the CFG 8842 MachineFunction *F = MBB->getParent(); 8843 MachineBasicBlock *thisMBB = MBB; 8844 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8845 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8846 F->insert(MBBIter, newMBB); 8847 F->insert(MBBIter, nextMBB); 8848 8849 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 8850 nextMBB->splice(nextMBB->begin(), thisMBB, 8851 llvm::next(MachineBasicBlock::iterator(mInstr)), 8852 thisMBB->end()); 8853 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 8854 8855 // Update thisMBB to fall through to newMBB 8856 thisMBB->addSuccessor(newMBB); 8857 8858 // newMBB jumps to newMBB and fall through to nextMBB 8859 newMBB->addSuccessor(nextMBB); 8860 newMBB->addSuccessor(newMBB); 8861 8862 DebugLoc dl = mInstr->getDebugLoc(); 8863 // Insert instructions into newMBB based on incoming instruction 8864 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 8865 "unexpected number of operands"); 8866 MachineOperand& destOper = mInstr->getOperand(0); 8867 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 8868 int numArgs = mInstr->getNumOperands() - 1; 8869 for (int i=0; i < numArgs; ++i) 8870 argOpers[i] = &mInstr->getOperand(i+1); 8871 8872 // x86 address has 4 operands: base, index, scale, and displacement 8873 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 8874 int valArgIndx = lastAddrIndx + 1; 8875 8876 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8877 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 8878 for (int i=0; i <= lastAddrIndx; ++i) 8879 (*MIB).addOperand(*argOpers[i]); 8880 8881 // We only support register and immediate values 8882 assert((argOpers[valArgIndx]->isReg() || 8883 argOpers[valArgIndx]->isImm()) && 8884 "invalid operand"); 8885 8886 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8887 if (argOpers[valArgIndx]->isReg()) 8888 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 8889 else 8890 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8891 (*MIB).addOperand(*argOpers[valArgIndx]); 8892 8893 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 8894 MIB.addReg(t1); 8895 8896 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 8897 MIB.addReg(t1); 8898 MIB.addReg(t2); 8899 8900 // Generate movc 8901 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8902 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 8903 MIB.addReg(t2); 8904 MIB.addReg(t1); 8905 8906 // Cmp and exchange if none has modified the memory location 8907 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 8908 for (int i=0; i <= lastAddrIndx; ++i) 8909 (*MIB).addOperand(*argOpers[i]); 8910 MIB.addReg(t3); 8911 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8912 (*MIB).setMemRefs(mInstr->memoperands_begin(), 8913 mInstr->memoperands_end()); 8914 8915 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 8916 MIB.addReg(X86::EAX); 8917 8918 // insert branch 8919 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8920 8921 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 8922 return nextMBB; 8923} 8924 8925// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 8926// or XMM0_V32I8 in AVX all of this code can be replaced with that 8927// in the .td file. 8928MachineBasicBlock * 8929X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 8930 unsigned numArgs, bool memArg) const { 8931 8932 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 8933 "Target must have SSE4.2 or AVX features enabled"); 8934 8935 DebugLoc dl = MI->getDebugLoc(); 8936 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8937 8938 unsigned Opc; 8939 8940 if (!Subtarget->hasAVX()) { 8941 if (memArg) 8942 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 8943 else 8944 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 8945 } else { 8946 if (memArg) 8947 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 8948 else 8949 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 8950 } 8951 8952 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 8953 8954 for (unsigned i = 0; i < numArgs; ++i) { 8955 MachineOperand &Op = MI->getOperand(i+1); 8956 8957 if (!(Op.isReg() && Op.isImplicit())) 8958 MIB.addOperand(Op); 8959 } 8960 8961 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 8962 .addReg(X86::XMM0); 8963 8964 MI->eraseFromParent(); 8965 8966 return BB; 8967} 8968 8969MachineBasicBlock * 8970X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 8971 MachineInstr *MI, 8972 MachineBasicBlock *MBB) const { 8973 // Emit code to save XMM registers to the stack. The ABI says that the 8974 // number of registers to save is given in %al, so it's theoretically 8975 // possible to do an indirect jump trick to avoid saving all of them, 8976 // however this code takes a simpler approach and just executes all 8977 // of the stores if %al is non-zero. It's less code, and it's probably 8978 // easier on the hardware branch predictor, and stores aren't all that 8979 // expensive anyway. 8980 8981 // Create the new basic blocks. One block contains all the XMM stores, 8982 // and one block is the final destination regardless of whether any 8983 // stores were performed. 8984 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8985 MachineFunction *F = MBB->getParent(); 8986 MachineFunction::iterator MBBIter = MBB; 8987 ++MBBIter; 8988 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 8989 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 8990 F->insert(MBBIter, XMMSaveMBB); 8991 F->insert(MBBIter, EndMBB); 8992 8993 // Transfer the remainder of MBB and its successor edges to EndMBB. 8994 EndMBB->splice(EndMBB->begin(), MBB, 8995 llvm::next(MachineBasicBlock::iterator(MI)), 8996 MBB->end()); 8997 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 8998 8999 // The original block will now fall through to the XMM save block. 9000 MBB->addSuccessor(XMMSaveMBB); 9001 // The XMMSaveMBB will fall through to the end block. 9002 XMMSaveMBB->addSuccessor(EndMBB); 9003 9004 // Now add the instructions. 9005 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9006 DebugLoc DL = MI->getDebugLoc(); 9007 9008 unsigned CountReg = MI->getOperand(0).getReg(); 9009 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 9010 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 9011 9012 if (!Subtarget->isTargetWin64()) { 9013 // If %al is 0, branch around the XMM save block. 9014 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 9015 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 9016 MBB->addSuccessor(EndMBB); 9017 } 9018 9019 // In the XMM save block, save all the XMM argument registers. 9020 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 9021 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 9022 MachineMemOperand *MMO = 9023 F->getMachineMemOperand( 9024 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 9025 MachineMemOperand::MOStore, Offset, 9026 /*Size=*/16, /*Align=*/16); 9027 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 9028 .addFrameIndex(RegSaveFrameIndex) 9029 .addImm(/*Scale=*/1) 9030 .addReg(/*IndexReg=*/0) 9031 .addImm(/*Disp=*/Offset) 9032 .addReg(/*Segment=*/0) 9033 .addReg(MI->getOperand(i).getReg()) 9034 .addMemOperand(MMO); 9035 } 9036 9037 MI->eraseFromParent(); // The pseudo instruction is gone now. 9038 9039 return EndMBB; 9040} 9041 9042MachineBasicBlock * 9043X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 9044 MachineBasicBlock *BB) const { 9045 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9046 DebugLoc DL = MI->getDebugLoc(); 9047 9048 // To "insert" a SELECT_CC instruction, we actually have to insert the 9049 // diamond control-flow pattern. The incoming instruction knows the 9050 // destination vreg to set, the condition code register to branch on, the 9051 // true/false values to select between, and a branch opcode to use. 9052 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 9053 MachineFunction::iterator It = BB; 9054 ++It; 9055 9056 // thisMBB: 9057 // ... 9058 // TrueVal = ... 9059 // cmpTY ccX, r1, r2 9060 // bCC copy1MBB 9061 // fallthrough --> copy0MBB 9062 MachineBasicBlock *thisMBB = BB; 9063 MachineFunction *F = BB->getParent(); 9064 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 9065 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 9066 F->insert(It, copy0MBB); 9067 F->insert(It, sinkMBB); 9068 9069 // If the EFLAGS register isn't dead in the terminator, then claim that it's 9070 // live into the sink and copy blocks. 9071 const MachineFunction *MF = BB->getParent(); 9072 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 9073 BitVector ReservedRegs = TRI->getReservedRegs(*MF); 9074 9075 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 9076 const MachineOperand &MO = MI->getOperand(I); 9077 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue; 9078 unsigned Reg = MO.getReg(); 9079 if (Reg != X86::EFLAGS) continue; 9080 copy0MBB->addLiveIn(Reg); 9081 sinkMBB->addLiveIn(Reg); 9082 } 9083 9084 // Transfer the remainder of BB and its successor edges to sinkMBB. 9085 sinkMBB->splice(sinkMBB->begin(), BB, 9086 llvm::next(MachineBasicBlock::iterator(MI)), 9087 BB->end()); 9088 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 9089 9090 // Add the true and fallthrough blocks as its successors. 9091 BB->addSuccessor(copy0MBB); 9092 BB->addSuccessor(sinkMBB); 9093 9094 // Create the conditional branch instruction. 9095 unsigned Opc = 9096 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 9097 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 9098 9099 // copy0MBB: 9100 // %FalseValue = ... 9101 // # fallthrough to sinkMBB 9102 copy0MBB->addSuccessor(sinkMBB); 9103 9104 // sinkMBB: 9105 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 9106 // ... 9107 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 9108 TII->get(X86::PHI), MI->getOperand(0).getReg()) 9109 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 9110 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 9111 9112 MI->eraseFromParent(); // The pseudo instruction is gone now. 9113 return sinkMBB; 9114} 9115 9116MachineBasicBlock * 9117X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI, 9118 MachineBasicBlock *BB) const { 9119 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9120 DebugLoc DL = MI->getDebugLoc(); 9121 9122 // The lowering is pretty easy: we're just emitting the call to _alloca. The 9123 // non-trivial part is impdef of ESP. 9124 // FIXME: The code should be tweaked as soon as we'll try to do codegen for 9125 // mingw-w64. 9126 9127 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 9128 .addExternalSymbol("_alloca") 9129 .addReg(X86::EAX, RegState::Implicit) 9130 .addReg(X86::ESP, RegState::Implicit) 9131 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 9132 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 9133 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 9134 9135 MI->eraseFromParent(); // The pseudo instruction is gone now. 9136 return BB; 9137} 9138 9139MachineBasicBlock * 9140X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 9141 MachineBasicBlock *BB) const { 9142 // This is pretty easy. We're taking the value that we received from 9143 // our load from the relocation, sticking it in either RDI (x86-64) 9144 // or EAX and doing an indirect call. The return value will then 9145 // be in the normal return register. 9146 const X86InstrInfo *TII 9147 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 9148 DebugLoc DL = MI->getDebugLoc(); 9149 MachineFunction *F = BB->getParent(); 9150 bool IsWin64 = Subtarget->isTargetWin64(); 9151 9152 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 9153 9154 if (Subtarget->is64Bit()) { 9155 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9156 TII->get(X86::MOV64rm), X86::RDI) 9157 .addReg(X86::RIP) 9158 .addImm(0).addReg(0) 9159 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 9160 MI->getOperand(3).getTargetFlags()) 9161 .addReg(0); 9162 MIB = BuildMI(*BB, MI, DL, TII->get(IsWin64 ? X86::WINCALL64m : X86::CALL64m)); 9163 addDirectMem(MIB, X86::RDI); 9164 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 9165 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9166 TII->get(X86::MOV32rm), X86::EAX) 9167 .addReg(0) 9168 .addImm(0).addReg(0) 9169 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 9170 MI->getOperand(3).getTargetFlags()) 9171 .addReg(0); 9172 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 9173 addDirectMem(MIB, X86::EAX); 9174 } else { 9175 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 9176 TII->get(X86::MOV32rm), X86::EAX) 9177 .addReg(TII->getGlobalBaseReg(F)) 9178 .addImm(0).addReg(0) 9179 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 9180 MI->getOperand(3).getTargetFlags()) 9181 .addReg(0); 9182 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 9183 addDirectMem(MIB, X86::EAX); 9184 } 9185 9186 MI->eraseFromParent(); // The pseudo instruction is gone now. 9187 return BB; 9188} 9189 9190MachineBasicBlock * 9191X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 9192 MachineBasicBlock *BB) const { 9193 switch (MI->getOpcode()) { 9194 default: assert(false && "Unexpected instr type to insert"); 9195 case X86::MINGW_ALLOCA: 9196 return EmitLoweredMingwAlloca(MI, BB); 9197 case X86::TLSCall_32: 9198 case X86::TLSCall_64: 9199 return EmitLoweredTLSCall(MI, BB); 9200 case X86::CMOV_GR8: 9201 case X86::CMOV_V1I64: 9202 case X86::CMOV_FR32: 9203 case X86::CMOV_FR64: 9204 case X86::CMOV_V4F32: 9205 case X86::CMOV_V2F64: 9206 case X86::CMOV_V2I64: 9207 case X86::CMOV_GR16: 9208 case X86::CMOV_GR32: 9209 case X86::CMOV_RFP32: 9210 case X86::CMOV_RFP64: 9211 case X86::CMOV_RFP80: 9212 return EmitLoweredSelect(MI, BB); 9213 9214 case X86::FP32_TO_INT16_IN_MEM: 9215 case X86::FP32_TO_INT32_IN_MEM: 9216 case X86::FP32_TO_INT64_IN_MEM: 9217 case X86::FP64_TO_INT16_IN_MEM: 9218 case X86::FP64_TO_INT32_IN_MEM: 9219 case X86::FP64_TO_INT64_IN_MEM: 9220 case X86::FP80_TO_INT16_IN_MEM: 9221 case X86::FP80_TO_INT32_IN_MEM: 9222 case X86::FP80_TO_INT64_IN_MEM: { 9223 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 9224 DebugLoc DL = MI->getDebugLoc(); 9225 9226 // Change the floating point control register to use "round towards zero" 9227 // mode when truncating to an integer value. 9228 MachineFunction *F = BB->getParent(); 9229 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 9230 addFrameReference(BuildMI(*BB, MI, DL, 9231 TII->get(X86::FNSTCW16m)), CWFrameIdx); 9232 9233 // Load the old value of the high byte of the control word... 9234 unsigned OldCW = 9235 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 9236 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 9237 CWFrameIdx); 9238 9239 // Set the high part to be round to zero... 9240 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 9241 .addImm(0xC7F); 9242 9243 // Reload the modified control word now... 9244 addFrameReference(BuildMI(*BB, MI, DL, 9245 TII->get(X86::FLDCW16m)), CWFrameIdx); 9246 9247 // Restore the memory image of control word to original value 9248 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 9249 .addReg(OldCW); 9250 9251 // Get the X86 opcode to use. 9252 unsigned Opc; 9253 switch (MI->getOpcode()) { 9254 default: llvm_unreachable("illegal opcode!"); 9255 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 9256 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 9257 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 9258 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 9259 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 9260 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 9261 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 9262 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 9263 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 9264 } 9265 9266 X86AddressMode AM; 9267 MachineOperand &Op = MI->getOperand(0); 9268 if (Op.isReg()) { 9269 AM.BaseType = X86AddressMode::RegBase; 9270 AM.Base.Reg = Op.getReg(); 9271 } else { 9272 AM.BaseType = X86AddressMode::FrameIndexBase; 9273 AM.Base.FrameIndex = Op.getIndex(); 9274 } 9275 Op = MI->getOperand(1); 9276 if (Op.isImm()) 9277 AM.Scale = Op.getImm(); 9278 Op = MI->getOperand(2); 9279 if (Op.isImm()) 9280 AM.IndexReg = Op.getImm(); 9281 Op = MI->getOperand(3); 9282 if (Op.isGlobal()) { 9283 AM.GV = Op.getGlobal(); 9284 } else { 9285 AM.Disp = Op.getImm(); 9286 } 9287 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 9288 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 9289 9290 // Reload the original control word now. 9291 addFrameReference(BuildMI(*BB, MI, DL, 9292 TII->get(X86::FLDCW16m)), CWFrameIdx); 9293 9294 MI->eraseFromParent(); // The pseudo instruction is gone now. 9295 return BB; 9296 } 9297 // String/text processing lowering. 9298 case X86::PCMPISTRM128REG: 9299 case X86::VPCMPISTRM128REG: 9300 return EmitPCMP(MI, BB, 3, false /* in-mem */); 9301 case X86::PCMPISTRM128MEM: 9302 case X86::VPCMPISTRM128MEM: 9303 return EmitPCMP(MI, BB, 3, true /* in-mem */); 9304 case X86::PCMPESTRM128REG: 9305 case X86::VPCMPESTRM128REG: 9306 return EmitPCMP(MI, BB, 5, false /* in mem */); 9307 case X86::PCMPESTRM128MEM: 9308 case X86::VPCMPESTRM128MEM: 9309 return EmitPCMP(MI, BB, 5, true /* in mem */); 9310 9311 // Atomic Lowering. 9312 case X86::ATOMAND32: 9313 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 9314 X86::AND32ri, X86::MOV32rm, 9315 X86::LCMPXCHG32, 9316 X86::NOT32r, X86::EAX, 9317 X86::GR32RegisterClass); 9318 case X86::ATOMOR32: 9319 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 9320 X86::OR32ri, X86::MOV32rm, 9321 X86::LCMPXCHG32, 9322 X86::NOT32r, X86::EAX, 9323 X86::GR32RegisterClass); 9324 case X86::ATOMXOR32: 9325 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 9326 X86::XOR32ri, X86::MOV32rm, 9327 X86::LCMPXCHG32, 9328 X86::NOT32r, X86::EAX, 9329 X86::GR32RegisterClass); 9330 case X86::ATOMNAND32: 9331 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 9332 X86::AND32ri, X86::MOV32rm, 9333 X86::LCMPXCHG32, 9334 X86::NOT32r, X86::EAX, 9335 X86::GR32RegisterClass, true); 9336 case X86::ATOMMIN32: 9337 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 9338 case X86::ATOMMAX32: 9339 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 9340 case X86::ATOMUMIN32: 9341 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 9342 case X86::ATOMUMAX32: 9343 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 9344 9345 case X86::ATOMAND16: 9346 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 9347 X86::AND16ri, X86::MOV16rm, 9348 X86::LCMPXCHG16, 9349 X86::NOT16r, X86::AX, 9350 X86::GR16RegisterClass); 9351 case X86::ATOMOR16: 9352 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 9353 X86::OR16ri, X86::MOV16rm, 9354 X86::LCMPXCHG16, 9355 X86::NOT16r, X86::AX, 9356 X86::GR16RegisterClass); 9357 case X86::ATOMXOR16: 9358 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 9359 X86::XOR16ri, X86::MOV16rm, 9360 X86::LCMPXCHG16, 9361 X86::NOT16r, X86::AX, 9362 X86::GR16RegisterClass); 9363 case X86::ATOMNAND16: 9364 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 9365 X86::AND16ri, X86::MOV16rm, 9366 X86::LCMPXCHG16, 9367 X86::NOT16r, X86::AX, 9368 X86::GR16RegisterClass, true); 9369 case X86::ATOMMIN16: 9370 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 9371 case X86::ATOMMAX16: 9372 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 9373 case X86::ATOMUMIN16: 9374 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 9375 case X86::ATOMUMAX16: 9376 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 9377 9378 case X86::ATOMAND8: 9379 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 9380 X86::AND8ri, X86::MOV8rm, 9381 X86::LCMPXCHG8, 9382 X86::NOT8r, X86::AL, 9383 X86::GR8RegisterClass); 9384 case X86::ATOMOR8: 9385 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 9386 X86::OR8ri, X86::MOV8rm, 9387 X86::LCMPXCHG8, 9388 X86::NOT8r, X86::AL, 9389 X86::GR8RegisterClass); 9390 case X86::ATOMXOR8: 9391 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 9392 X86::XOR8ri, X86::MOV8rm, 9393 X86::LCMPXCHG8, 9394 X86::NOT8r, X86::AL, 9395 X86::GR8RegisterClass); 9396 case X86::ATOMNAND8: 9397 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 9398 X86::AND8ri, X86::MOV8rm, 9399 X86::LCMPXCHG8, 9400 X86::NOT8r, X86::AL, 9401 X86::GR8RegisterClass, true); 9402 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 9403 // This group is for 64-bit host. 9404 case X86::ATOMAND64: 9405 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 9406 X86::AND64ri32, X86::MOV64rm, 9407 X86::LCMPXCHG64, 9408 X86::NOT64r, X86::RAX, 9409 X86::GR64RegisterClass); 9410 case X86::ATOMOR64: 9411 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 9412 X86::OR64ri32, X86::MOV64rm, 9413 X86::LCMPXCHG64, 9414 X86::NOT64r, X86::RAX, 9415 X86::GR64RegisterClass); 9416 case X86::ATOMXOR64: 9417 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 9418 X86::XOR64ri32, X86::MOV64rm, 9419 X86::LCMPXCHG64, 9420 X86::NOT64r, X86::RAX, 9421 X86::GR64RegisterClass); 9422 case X86::ATOMNAND64: 9423 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 9424 X86::AND64ri32, X86::MOV64rm, 9425 X86::LCMPXCHG64, 9426 X86::NOT64r, X86::RAX, 9427 X86::GR64RegisterClass, true); 9428 case X86::ATOMMIN64: 9429 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 9430 case X86::ATOMMAX64: 9431 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 9432 case X86::ATOMUMIN64: 9433 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 9434 case X86::ATOMUMAX64: 9435 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 9436 9437 // This group does 64-bit operations on a 32-bit host. 9438 case X86::ATOMAND6432: 9439 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9440 X86::AND32rr, X86::AND32rr, 9441 X86::AND32ri, X86::AND32ri, 9442 false); 9443 case X86::ATOMOR6432: 9444 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9445 X86::OR32rr, X86::OR32rr, 9446 X86::OR32ri, X86::OR32ri, 9447 false); 9448 case X86::ATOMXOR6432: 9449 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9450 X86::XOR32rr, X86::XOR32rr, 9451 X86::XOR32ri, X86::XOR32ri, 9452 false); 9453 case X86::ATOMNAND6432: 9454 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9455 X86::AND32rr, X86::AND32rr, 9456 X86::AND32ri, X86::AND32ri, 9457 true); 9458 case X86::ATOMADD6432: 9459 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9460 X86::ADD32rr, X86::ADC32rr, 9461 X86::ADD32ri, X86::ADC32ri, 9462 false); 9463 case X86::ATOMSUB6432: 9464 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9465 X86::SUB32rr, X86::SBB32rr, 9466 X86::SUB32ri, X86::SBB32ri, 9467 false); 9468 case X86::ATOMSWAP6432: 9469 return EmitAtomicBit6432WithCustomInserter(MI, BB, 9470 X86::MOV32rr, X86::MOV32rr, 9471 X86::MOV32ri, X86::MOV32ri, 9472 false); 9473 case X86::VASTART_SAVE_XMM_REGS: 9474 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 9475 } 9476} 9477 9478//===----------------------------------------------------------------------===// 9479// X86 Optimization Hooks 9480//===----------------------------------------------------------------------===// 9481 9482void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 9483 const APInt &Mask, 9484 APInt &KnownZero, 9485 APInt &KnownOne, 9486 const SelectionDAG &DAG, 9487 unsigned Depth) const { 9488 unsigned Opc = Op.getOpcode(); 9489 assert((Opc >= ISD::BUILTIN_OP_END || 9490 Opc == ISD::INTRINSIC_WO_CHAIN || 9491 Opc == ISD::INTRINSIC_W_CHAIN || 9492 Opc == ISD::INTRINSIC_VOID) && 9493 "Should use MaskedValueIsZero if you don't know whether Op" 9494 " is a target node!"); 9495 9496 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 9497 switch (Opc) { 9498 default: break; 9499 case X86ISD::ADD: 9500 case X86ISD::SUB: 9501 case X86ISD::SMUL: 9502 case X86ISD::UMUL: 9503 case X86ISD::INC: 9504 case X86ISD::DEC: 9505 case X86ISD::OR: 9506 case X86ISD::XOR: 9507 case X86ISD::AND: 9508 // These nodes' second result is a boolean. 9509 if (Op.getResNo() == 0) 9510 break; 9511 // Fallthrough 9512 case X86ISD::SETCC: 9513 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 9514 Mask.getBitWidth() - 1); 9515 break; 9516 } 9517} 9518 9519/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 9520/// node is a GlobalAddress + offset. 9521bool X86TargetLowering::isGAPlusOffset(SDNode *N, 9522 const GlobalValue* &GA, 9523 int64_t &Offset) const { 9524 if (N->getOpcode() == X86ISD::Wrapper) { 9525 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 9526 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 9527 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 9528 return true; 9529 } 9530 } 9531 return TargetLowering::isGAPlusOffset(N, GA, Offset); 9532} 9533 9534/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 9535/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 9536/// if the load addresses are consecutive, non-overlapping, and in the right 9537/// order. 9538static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 9539 const TargetLowering &TLI) { 9540 DebugLoc dl = N->getDebugLoc(); 9541 EVT VT = N->getValueType(0); 9542 9543 if (VT.getSizeInBits() != 128) 9544 return SDValue(); 9545 9546 SmallVector<SDValue, 16> Elts; 9547 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 9548 Elts.push_back(getShuffleScalarElt(N, i, DAG)); 9549 9550 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 9551} 9552 9553/// PerformShuffleCombine - Detect vector gather/scatter index generation 9554/// and convert it from being a bunch of shuffles and extracts to a simple 9555/// store and scalar loads to extract the elements. 9556static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 9557 const TargetLowering &TLI) { 9558 SDValue InputVector = N->getOperand(0); 9559 9560 // Only operate on vectors of 4 elements, where the alternative shuffling 9561 // gets to be more expensive. 9562 if (InputVector.getValueType() != MVT::v4i32) 9563 return SDValue(); 9564 9565 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 9566 // single use which is a sign-extend or zero-extend, and all elements are 9567 // used. 9568 SmallVector<SDNode *, 4> Uses; 9569 unsigned ExtractedElements = 0; 9570 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 9571 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 9572 if (UI.getUse().getResNo() != InputVector.getResNo()) 9573 return SDValue(); 9574 9575 SDNode *Extract = *UI; 9576 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 9577 return SDValue(); 9578 9579 if (Extract->getValueType(0) != MVT::i32) 9580 return SDValue(); 9581 if (!Extract->hasOneUse()) 9582 return SDValue(); 9583 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 9584 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 9585 return SDValue(); 9586 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 9587 return SDValue(); 9588 9589 // Record which element was extracted. 9590 ExtractedElements |= 9591 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 9592 9593 Uses.push_back(Extract); 9594 } 9595 9596 // If not all the elements were used, this may not be worthwhile. 9597 if (ExtractedElements != 15) 9598 return SDValue(); 9599 9600 // Ok, we've now decided to do the transformation. 9601 DebugLoc dl = InputVector.getDebugLoc(); 9602 9603 // Store the value to a temporary stack slot. 9604 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 9605 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 9606 0, false, false, 0); 9607 9608 // Replace each use (extract) with a load of the appropriate element. 9609 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 9610 UE = Uses.end(); UI != UE; ++UI) { 9611 SDNode *Extract = *UI; 9612 9613 // Compute the element's address. 9614 SDValue Idx = Extract->getOperand(1); 9615 unsigned EltSize = 9616 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 9617 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 9618 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 9619 9620 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), 9621 OffsetVal, StackPtr); 9622 9623 // Load the scalar. 9624 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 9625 ScalarAddr, NULL, 0, false, false, 0); 9626 9627 // Replace the exact with the load. 9628 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 9629 } 9630 9631 // The replacement was made in place; don't return anything. 9632 return SDValue(); 9633} 9634 9635/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 9636static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 9637 const X86Subtarget *Subtarget) { 9638 DebugLoc DL = N->getDebugLoc(); 9639 SDValue Cond = N->getOperand(0); 9640 // Get the LHS/RHS of the select. 9641 SDValue LHS = N->getOperand(1); 9642 SDValue RHS = N->getOperand(2); 9643 9644 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 9645 // instructions match the semantics of the common C idiom x<y?x:y but not 9646 // x<=y?x:y, because of how they handle negative zero (which can be 9647 // ignored in unsafe-math mode). 9648 if (Subtarget->hasSSE2() && 9649 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 9650 Cond.getOpcode() == ISD::SETCC) { 9651 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 9652 9653 unsigned Opcode = 0; 9654 // Check for x CC y ? x : y. 9655 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 9656 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 9657 switch (CC) { 9658 default: break; 9659 case ISD::SETULT: 9660 // Converting this to a min would handle NaNs incorrectly, and swapping 9661 // the operands would cause it to handle comparisons between positive 9662 // and negative zero incorrectly. 9663 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 9664 if (!UnsafeFPMath && 9665 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9666 break; 9667 std::swap(LHS, RHS); 9668 } 9669 Opcode = X86ISD::FMIN; 9670 break; 9671 case ISD::SETOLE: 9672 // Converting this to a min would handle comparisons between positive 9673 // and negative zero incorrectly. 9674 if (!UnsafeFPMath && 9675 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 9676 break; 9677 Opcode = X86ISD::FMIN; 9678 break; 9679 case ISD::SETULE: 9680 // Converting this to a min would handle both negative zeros and NaNs 9681 // incorrectly, but we can swap the operands to fix both. 9682 std::swap(LHS, RHS); 9683 case ISD::SETOLT: 9684 case ISD::SETLT: 9685 case ISD::SETLE: 9686 Opcode = X86ISD::FMIN; 9687 break; 9688 9689 case ISD::SETOGE: 9690 // Converting this to a max would handle comparisons between positive 9691 // and negative zero incorrectly. 9692 if (!UnsafeFPMath && 9693 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS)) 9694 break; 9695 Opcode = X86ISD::FMAX; 9696 break; 9697 case ISD::SETUGT: 9698 // Converting this to a max would handle NaNs incorrectly, and swapping 9699 // the operands would cause it to handle comparisons between positive 9700 // and negative zero incorrectly. 9701 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 9702 if (!UnsafeFPMath && 9703 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9704 break; 9705 std::swap(LHS, RHS); 9706 } 9707 Opcode = X86ISD::FMAX; 9708 break; 9709 case ISD::SETUGE: 9710 // Converting this to a max would handle both negative zeros and NaNs 9711 // incorrectly, but we can swap the operands to fix both. 9712 std::swap(LHS, RHS); 9713 case ISD::SETOGT: 9714 case ISD::SETGT: 9715 case ISD::SETGE: 9716 Opcode = X86ISD::FMAX; 9717 break; 9718 } 9719 // Check for x CC y ? y : x -- a min/max with reversed arms. 9720 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 9721 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 9722 switch (CC) { 9723 default: break; 9724 case ISD::SETOGE: 9725 // Converting this to a min would handle comparisons between positive 9726 // and negative zero incorrectly, and swapping the operands would 9727 // cause it to handle NaNs incorrectly. 9728 if (!UnsafeFPMath && 9729 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 9730 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9731 break; 9732 std::swap(LHS, RHS); 9733 } 9734 Opcode = X86ISD::FMIN; 9735 break; 9736 case ISD::SETUGT: 9737 // Converting this to a min would handle NaNs incorrectly. 9738 if (!UnsafeFPMath && 9739 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9740 break; 9741 Opcode = X86ISD::FMIN; 9742 break; 9743 case ISD::SETUGE: 9744 // Converting this to a min would handle both negative zeros and NaNs 9745 // incorrectly, but we can swap the operands to fix both. 9746 std::swap(LHS, RHS); 9747 case ISD::SETOGT: 9748 case ISD::SETGT: 9749 case ISD::SETGE: 9750 Opcode = X86ISD::FMIN; 9751 break; 9752 9753 case ISD::SETULT: 9754 // Converting this to a max would handle NaNs incorrectly. 9755 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9756 break; 9757 Opcode = X86ISD::FMAX; 9758 break; 9759 case ISD::SETOLE: 9760 // Converting this to a max would handle comparisons between positive 9761 // and negative zero incorrectly, and swapping the operands would 9762 // cause it to handle NaNs incorrectly. 9763 if (!UnsafeFPMath && 9764 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 9765 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 9766 break; 9767 std::swap(LHS, RHS); 9768 } 9769 Opcode = X86ISD::FMAX; 9770 break; 9771 case ISD::SETULE: 9772 // Converting this to a max would handle both negative zeros and NaNs 9773 // incorrectly, but we can swap the operands to fix both. 9774 std::swap(LHS, RHS); 9775 case ISD::SETOLT: 9776 case ISD::SETLT: 9777 case ISD::SETLE: 9778 Opcode = X86ISD::FMAX; 9779 break; 9780 } 9781 } 9782 9783 if (Opcode) 9784 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 9785 } 9786 9787 // If this is a select between two integer constants, try to do some 9788 // optimizations. 9789 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 9790 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 9791 // Don't do this for crazy integer types. 9792 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 9793 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 9794 // so that TrueC (the true value) is larger than FalseC. 9795 bool NeedsCondInvert = false; 9796 9797 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 9798 // Efficiently invertible. 9799 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 9800 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 9801 isa<ConstantSDNode>(Cond.getOperand(1))))) { 9802 NeedsCondInvert = true; 9803 std::swap(TrueC, FalseC); 9804 } 9805 9806 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 9807 if (FalseC->getAPIntValue() == 0 && 9808 TrueC->getAPIntValue().isPowerOf2()) { 9809 if (NeedsCondInvert) // Invert the condition if needed. 9810 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9811 DAG.getConstant(1, Cond.getValueType())); 9812 9813 // Zero extend the condition if needed. 9814 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 9815 9816 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9817 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 9818 DAG.getConstant(ShAmt, MVT::i8)); 9819 } 9820 9821 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 9822 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9823 if (NeedsCondInvert) // Invert the condition if needed. 9824 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9825 DAG.getConstant(1, Cond.getValueType())); 9826 9827 // Zero extend the condition if needed. 9828 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9829 FalseC->getValueType(0), Cond); 9830 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9831 SDValue(FalseC, 0)); 9832 } 9833 9834 // Optimize cases that will turn into an LEA instruction. This requires 9835 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9836 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9837 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9838 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9839 9840 bool isFastMultiplier = false; 9841 if (Diff < 10) { 9842 switch ((unsigned char)Diff) { 9843 default: break; 9844 case 1: // result = add base, cond 9845 case 2: // result = lea base( , cond*2) 9846 case 3: // result = lea base(cond, cond*2) 9847 case 4: // result = lea base( , cond*4) 9848 case 5: // result = lea base(cond, cond*4) 9849 case 8: // result = lea base( , cond*8) 9850 case 9: // result = lea base(cond, cond*8) 9851 isFastMultiplier = true; 9852 break; 9853 } 9854 } 9855 9856 if (isFastMultiplier) { 9857 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9858 if (NeedsCondInvert) // Invert the condition if needed. 9859 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9860 DAG.getConstant(1, Cond.getValueType())); 9861 9862 // Zero extend the condition if needed. 9863 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9864 Cond); 9865 // Scale the condition by the difference. 9866 if (Diff != 1) 9867 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9868 DAG.getConstant(Diff, Cond.getValueType())); 9869 9870 // Add the base if non-zero. 9871 if (FalseC->getAPIntValue() != 0) 9872 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9873 SDValue(FalseC, 0)); 9874 return Cond; 9875 } 9876 } 9877 } 9878 } 9879 9880 return SDValue(); 9881} 9882 9883/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 9884static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 9885 TargetLowering::DAGCombinerInfo &DCI) { 9886 DebugLoc DL = N->getDebugLoc(); 9887 9888 // If the flag operand isn't dead, don't touch this CMOV. 9889 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 9890 return SDValue(); 9891 9892 // If this is a select between two integer constants, try to do some 9893 // optimizations. Note that the operands are ordered the opposite of SELECT 9894 // operands. 9895 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 9896 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 9897 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 9898 // larger than FalseC (the false value). 9899 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 9900 9901 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 9902 CC = X86::GetOppositeBranchCondition(CC); 9903 std::swap(TrueC, FalseC); 9904 } 9905 9906 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 9907 // This is efficient for any integer data type (including i8/i16) and 9908 // shift amount. 9909 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 9910 SDValue Cond = N->getOperand(3); 9911 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9912 DAG.getConstant(CC, MVT::i8), Cond); 9913 9914 // Zero extend the condition if needed. 9915 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 9916 9917 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9918 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 9919 DAG.getConstant(ShAmt, MVT::i8)); 9920 if (N->getNumValues() == 2) // Dead flag value? 9921 return DCI.CombineTo(N, Cond, SDValue()); 9922 return Cond; 9923 } 9924 9925 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 9926 // for any integer data type, including i8/i16. 9927 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9928 SDValue Cond = N->getOperand(3); 9929 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9930 DAG.getConstant(CC, MVT::i8), Cond); 9931 9932 // Zero extend the condition if needed. 9933 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9934 FalseC->getValueType(0), Cond); 9935 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9936 SDValue(FalseC, 0)); 9937 9938 if (N->getNumValues() == 2) // Dead flag value? 9939 return DCI.CombineTo(N, Cond, SDValue()); 9940 return Cond; 9941 } 9942 9943 // Optimize cases that will turn into an LEA instruction. This requires 9944 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9945 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9946 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9947 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9948 9949 bool isFastMultiplier = false; 9950 if (Diff < 10) { 9951 switch ((unsigned char)Diff) { 9952 default: break; 9953 case 1: // result = add base, cond 9954 case 2: // result = lea base( , cond*2) 9955 case 3: // result = lea base(cond, cond*2) 9956 case 4: // result = lea base( , cond*4) 9957 case 5: // result = lea base(cond, cond*4) 9958 case 8: // result = lea base( , cond*8) 9959 case 9: // result = lea base(cond, cond*8) 9960 isFastMultiplier = true; 9961 break; 9962 } 9963 } 9964 9965 if (isFastMultiplier) { 9966 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9967 SDValue Cond = N->getOperand(3); 9968 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9969 DAG.getConstant(CC, MVT::i8), Cond); 9970 // Zero extend the condition if needed. 9971 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9972 Cond); 9973 // Scale the condition by the difference. 9974 if (Diff != 1) 9975 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9976 DAG.getConstant(Diff, Cond.getValueType())); 9977 9978 // Add the base if non-zero. 9979 if (FalseC->getAPIntValue() != 0) 9980 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9981 SDValue(FalseC, 0)); 9982 if (N->getNumValues() == 2) // Dead flag value? 9983 return DCI.CombineTo(N, Cond, SDValue()); 9984 return Cond; 9985 } 9986 } 9987 } 9988 } 9989 return SDValue(); 9990} 9991 9992 9993/// PerformMulCombine - Optimize a single multiply with constant into two 9994/// in order to implement it with two cheaper instructions, e.g. 9995/// LEA + SHL, LEA + LEA. 9996static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 9997 TargetLowering::DAGCombinerInfo &DCI) { 9998 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 9999 return SDValue(); 10000 10001 EVT VT = N->getValueType(0); 10002 if (VT != MVT::i64) 10003 return SDValue(); 10004 10005 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 10006 if (!C) 10007 return SDValue(); 10008 uint64_t MulAmt = C->getZExtValue(); 10009 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 10010 return SDValue(); 10011 10012 uint64_t MulAmt1 = 0; 10013 uint64_t MulAmt2 = 0; 10014 if ((MulAmt % 9) == 0) { 10015 MulAmt1 = 9; 10016 MulAmt2 = MulAmt / 9; 10017 } else if ((MulAmt % 5) == 0) { 10018 MulAmt1 = 5; 10019 MulAmt2 = MulAmt / 5; 10020 } else if ((MulAmt % 3) == 0) { 10021 MulAmt1 = 3; 10022 MulAmt2 = MulAmt / 3; 10023 } 10024 if (MulAmt2 && 10025 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 10026 DebugLoc DL = N->getDebugLoc(); 10027 10028 if (isPowerOf2_64(MulAmt2) && 10029 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 10030 // If second multiplifer is pow2, issue it first. We want the multiply by 10031 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 10032 // is an add. 10033 std::swap(MulAmt1, MulAmt2); 10034 10035 SDValue NewMul; 10036 if (isPowerOf2_64(MulAmt1)) 10037 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 10038 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 10039 else 10040 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 10041 DAG.getConstant(MulAmt1, VT)); 10042 10043 if (isPowerOf2_64(MulAmt2)) 10044 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 10045 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 10046 else 10047 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 10048 DAG.getConstant(MulAmt2, VT)); 10049 10050 // Do not add new nodes to DAG combiner worklist. 10051 DCI.CombineTo(N, NewMul, false); 10052 } 10053 return SDValue(); 10054} 10055 10056static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 10057 SDValue N0 = N->getOperand(0); 10058 SDValue N1 = N->getOperand(1); 10059 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 10060 EVT VT = N0.getValueType(); 10061 10062 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 10063 // since the result of setcc_c is all zero's or all ones. 10064 if (N1C && N0.getOpcode() == ISD::AND && 10065 N0.getOperand(1).getOpcode() == ISD::Constant) { 10066 SDValue N00 = N0.getOperand(0); 10067 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 10068 ((N00.getOpcode() == ISD::ANY_EXTEND || 10069 N00.getOpcode() == ISD::ZERO_EXTEND) && 10070 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 10071 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 10072 APInt ShAmt = N1C->getAPIntValue(); 10073 Mask = Mask.shl(ShAmt); 10074 if (Mask != 0) 10075 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 10076 N00, DAG.getConstant(Mask, VT)); 10077 } 10078 } 10079 10080 return SDValue(); 10081} 10082 10083/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 10084/// when possible. 10085static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 10086 const X86Subtarget *Subtarget) { 10087 EVT VT = N->getValueType(0); 10088 if (!VT.isVector() && VT.isInteger() && 10089 N->getOpcode() == ISD::SHL) 10090 return PerformSHLCombine(N, DAG); 10091 10092 // On X86 with SSE2 support, we can transform this to a vector shift if 10093 // all elements are shifted by the same amount. We can't do this in legalize 10094 // because the a constant vector is typically transformed to a constant pool 10095 // so we have no knowledge of the shift amount. 10096 if (!Subtarget->hasSSE2()) 10097 return SDValue(); 10098 10099 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 10100 return SDValue(); 10101 10102 SDValue ShAmtOp = N->getOperand(1); 10103 EVT EltVT = VT.getVectorElementType(); 10104 DebugLoc DL = N->getDebugLoc(); 10105 SDValue BaseShAmt = SDValue(); 10106 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 10107 unsigned NumElts = VT.getVectorNumElements(); 10108 unsigned i = 0; 10109 for (; i != NumElts; ++i) { 10110 SDValue Arg = ShAmtOp.getOperand(i); 10111 if (Arg.getOpcode() == ISD::UNDEF) continue; 10112 BaseShAmt = Arg; 10113 break; 10114 } 10115 for (; i != NumElts; ++i) { 10116 SDValue Arg = ShAmtOp.getOperand(i); 10117 if (Arg.getOpcode() == ISD::UNDEF) continue; 10118 if (Arg != BaseShAmt) { 10119 return SDValue(); 10120 } 10121 } 10122 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 10123 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 10124 SDValue InVec = ShAmtOp.getOperand(0); 10125 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 10126 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 10127 unsigned i = 0; 10128 for (; i != NumElts; ++i) { 10129 SDValue Arg = InVec.getOperand(i); 10130 if (Arg.getOpcode() == ISD::UNDEF) continue; 10131 BaseShAmt = Arg; 10132 break; 10133 } 10134 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 10135 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 10136 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 10137 if (C->getZExtValue() == SplatIdx) 10138 BaseShAmt = InVec.getOperand(1); 10139 } 10140 } 10141 if (BaseShAmt.getNode() == 0) 10142 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 10143 DAG.getIntPtrConstant(0)); 10144 } else 10145 return SDValue(); 10146 10147 // The shift amount is an i32. 10148 if (EltVT.bitsGT(MVT::i32)) 10149 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 10150 else if (EltVT.bitsLT(MVT::i32)) 10151 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 10152 10153 // The shift amount is identical so we can do a vector shift. 10154 SDValue ValOp = N->getOperand(0); 10155 switch (N->getOpcode()) { 10156 default: 10157 llvm_unreachable("Unknown shift opcode!"); 10158 break; 10159 case ISD::SHL: 10160 if (VT == MVT::v2i64) 10161 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10162 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10163 ValOp, BaseShAmt); 10164 if (VT == MVT::v4i32) 10165 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10166 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10167 ValOp, BaseShAmt); 10168 if (VT == MVT::v8i16) 10169 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10170 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10171 ValOp, BaseShAmt); 10172 break; 10173 case ISD::SRA: 10174 if (VT == MVT::v4i32) 10175 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10176 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 10177 ValOp, BaseShAmt); 10178 if (VT == MVT::v8i16) 10179 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10180 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 10181 ValOp, BaseShAmt); 10182 break; 10183 case ISD::SRL: 10184 if (VT == MVT::v2i64) 10185 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10186 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10187 ValOp, BaseShAmt); 10188 if (VT == MVT::v4i32) 10189 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10190 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 10191 ValOp, BaseShAmt); 10192 if (VT == MVT::v8i16) 10193 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 10194 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10195 ValOp, BaseShAmt); 10196 break; 10197 } 10198 return SDValue(); 10199} 10200 10201static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 10202 TargetLowering::DAGCombinerInfo &DCI, 10203 const X86Subtarget *Subtarget) { 10204 if (DCI.isBeforeLegalizeOps()) 10205 return SDValue(); 10206 10207 EVT VT = N->getValueType(0); 10208 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 10209 return SDValue(); 10210 10211 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 10212 SDValue N0 = N->getOperand(0); 10213 SDValue N1 = N->getOperand(1); 10214 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 10215 std::swap(N0, N1); 10216 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 10217 return SDValue(); 10218 if (!N0.hasOneUse() || !N1.hasOneUse()) 10219 return SDValue(); 10220 10221 SDValue ShAmt0 = N0.getOperand(1); 10222 if (ShAmt0.getValueType() != MVT::i8) 10223 return SDValue(); 10224 SDValue ShAmt1 = N1.getOperand(1); 10225 if (ShAmt1.getValueType() != MVT::i8) 10226 return SDValue(); 10227 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 10228 ShAmt0 = ShAmt0.getOperand(0); 10229 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 10230 ShAmt1 = ShAmt1.getOperand(0); 10231 10232 DebugLoc DL = N->getDebugLoc(); 10233 unsigned Opc = X86ISD::SHLD; 10234 SDValue Op0 = N0.getOperand(0); 10235 SDValue Op1 = N1.getOperand(0); 10236 if (ShAmt0.getOpcode() == ISD::SUB) { 10237 Opc = X86ISD::SHRD; 10238 std::swap(Op0, Op1); 10239 std::swap(ShAmt0, ShAmt1); 10240 } 10241 10242 unsigned Bits = VT.getSizeInBits(); 10243 if (ShAmt1.getOpcode() == ISD::SUB) { 10244 SDValue Sum = ShAmt1.getOperand(0); 10245 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 10246 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 10247 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 10248 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 10249 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 10250 return DAG.getNode(Opc, DL, VT, 10251 Op0, Op1, 10252 DAG.getNode(ISD::TRUNCATE, DL, 10253 MVT::i8, ShAmt0)); 10254 } 10255 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 10256 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 10257 if (ShAmt0C && 10258 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 10259 return DAG.getNode(Opc, DL, VT, 10260 N0.getOperand(0), N1.getOperand(0), 10261 DAG.getNode(ISD::TRUNCATE, DL, 10262 MVT::i8, ShAmt0)); 10263 } 10264 10265 return SDValue(); 10266} 10267 10268/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 10269static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 10270 const X86Subtarget *Subtarget) { 10271 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 10272 // the FP state in cases where an emms may be missing. 10273 // A preferable solution to the general problem is to figure out the right 10274 // places to insert EMMS. This qualifies as a quick hack. 10275 10276 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 10277 StoreSDNode *St = cast<StoreSDNode>(N); 10278 EVT VT = St->getValue().getValueType(); 10279 if (VT.getSizeInBits() != 64) 10280 return SDValue(); 10281 10282 const Function *F = DAG.getMachineFunction().getFunction(); 10283 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 10284 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 10285 && Subtarget->hasSSE2(); 10286 if ((VT.isVector() || 10287 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 10288 isa<LoadSDNode>(St->getValue()) && 10289 !cast<LoadSDNode>(St->getValue())->isVolatile() && 10290 St->getChain().hasOneUse() && !St->isVolatile()) { 10291 SDNode* LdVal = St->getValue().getNode(); 10292 LoadSDNode *Ld = 0; 10293 int TokenFactorIndex = -1; 10294 SmallVector<SDValue, 8> Ops; 10295 SDNode* ChainVal = St->getChain().getNode(); 10296 // Must be a store of a load. We currently handle two cases: the load 10297 // is a direct child, and it's under an intervening TokenFactor. It is 10298 // possible to dig deeper under nested TokenFactors. 10299 if (ChainVal == LdVal) 10300 Ld = cast<LoadSDNode>(St->getChain()); 10301 else if (St->getValue().hasOneUse() && 10302 ChainVal->getOpcode() == ISD::TokenFactor) { 10303 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 10304 if (ChainVal->getOperand(i).getNode() == LdVal) { 10305 TokenFactorIndex = i; 10306 Ld = cast<LoadSDNode>(St->getValue()); 10307 } else 10308 Ops.push_back(ChainVal->getOperand(i)); 10309 } 10310 } 10311 10312 if (!Ld || !ISD::isNormalLoad(Ld)) 10313 return SDValue(); 10314 10315 // If this is not the MMX case, i.e. we are just turning i64 load/store 10316 // into f64 load/store, avoid the transformation if there are multiple 10317 // uses of the loaded value. 10318 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 10319 return SDValue(); 10320 10321 DebugLoc LdDL = Ld->getDebugLoc(); 10322 DebugLoc StDL = N->getDebugLoc(); 10323 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 10324 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 10325 // pair instead. 10326 if (Subtarget->is64Bit() || F64IsLegal) { 10327 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 10328 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 10329 Ld->getBasePtr(), Ld->getSrcValue(), 10330 Ld->getSrcValueOffset(), Ld->isVolatile(), 10331 Ld->isNonTemporal(), Ld->getAlignment()); 10332 SDValue NewChain = NewLd.getValue(1); 10333 if (TokenFactorIndex != -1) { 10334 Ops.push_back(NewChain); 10335 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 10336 Ops.size()); 10337 } 10338 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 10339 St->getSrcValue(), St->getSrcValueOffset(), 10340 St->isVolatile(), St->isNonTemporal(), 10341 St->getAlignment()); 10342 } 10343 10344 // Otherwise, lower to two pairs of 32-bit loads / stores. 10345 SDValue LoAddr = Ld->getBasePtr(); 10346 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 10347 DAG.getConstant(4, MVT::i32)); 10348 10349 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 10350 Ld->getSrcValue(), Ld->getSrcValueOffset(), 10351 Ld->isVolatile(), Ld->isNonTemporal(), 10352 Ld->getAlignment()); 10353 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 10354 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 10355 Ld->isVolatile(), Ld->isNonTemporal(), 10356 MinAlign(Ld->getAlignment(), 4)); 10357 10358 SDValue NewChain = LoLd.getValue(1); 10359 if (TokenFactorIndex != -1) { 10360 Ops.push_back(LoLd); 10361 Ops.push_back(HiLd); 10362 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 10363 Ops.size()); 10364 } 10365 10366 LoAddr = St->getBasePtr(); 10367 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 10368 DAG.getConstant(4, MVT::i32)); 10369 10370 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 10371 St->getSrcValue(), St->getSrcValueOffset(), 10372 St->isVolatile(), St->isNonTemporal(), 10373 St->getAlignment()); 10374 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 10375 St->getSrcValue(), 10376 St->getSrcValueOffset() + 4, 10377 St->isVolatile(), 10378 St->isNonTemporal(), 10379 MinAlign(St->getAlignment(), 4)); 10380 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 10381 } 10382 return SDValue(); 10383} 10384 10385/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 10386/// X86ISD::FXOR nodes. 10387static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 10388 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 10389 // F[X]OR(0.0, x) -> x 10390 // F[X]OR(x, 0.0) -> x 10391 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 10392 if (C->getValueAPF().isPosZero()) 10393 return N->getOperand(1); 10394 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 10395 if (C->getValueAPF().isPosZero()) 10396 return N->getOperand(0); 10397 return SDValue(); 10398} 10399 10400/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 10401static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 10402 // FAND(0.0, x) -> 0.0 10403 // FAND(x, 0.0) -> 0.0 10404 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 10405 if (C->getValueAPF().isPosZero()) 10406 return N->getOperand(0); 10407 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 10408 if (C->getValueAPF().isPosZero()) 10409 return N->getOperand(1); 10410 return SDValue(); 10411} 10412 10413static SDValue PerformBTCombine(SDNode *N, 10414 SelectionDAG &DAG, 10415 TargetLowering::DAGCombinerInfo &DCI) { 10416 // BT ignores high bits in the bit index operand. 10417 SDValue Op1 = N->getOperand(1); 10418 if (Op1.hasOneUse()) { 10419 unsigned BitWidth = Op1.getValueSizeInBits(); 10420 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 10421 APInt KnownZero, KnownOne; 10422 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 10423 !DCI.isBeforeLegalizeOps()); 10424 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 10425 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 10426 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 10427 DCI.CommitTargetLoweringOpt(TLO); 10428 } 10429 return SDValue(); 10430} 10431 10432static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 10433 SDValue Op = N->getOperand(0); 10434 if (Op.getOpcode() == ISD::BIT_CONVERT) 10435 Op = Op.getOperand(0); 10436 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 10437 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 10438 VT.getVectorElementType().getSizeInBits() == 10439 OpVT.getVectorElementType().getSizeInBits()) { 10440 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 10441 } 10442 return SDValue(); 10443} 10444 10445static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 10446 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 10447 // (and (i32 x86isd::setcc_carry), 1) 10448 // This eliminates the zext. This transformation is necessary because 10449 // ISD::SETCC is always legalized to i8. 10450 DebugLoc dl = N->getDebugLoc(); 10451 SDValue N0 = N->getOperand(0); 10452 EVT VT = N->getValueType(0); 10453 if (N0.getOpcode() == ISD::AND && 10454 N0.hasOneUse() && 10455 N0.getOperand(0).hasOneUse()) { 10456 SDValue N00 = N0.getOperand(0); 10457 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 10458 return SDValue(); 10459 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 10460 if (!C || C->getZExtValue() != 1) 10461 return SDValue(); 10462 return DAG.getNode(ISD::AND, dl, VT, 10463 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 10464 N00.getOperand(0), N00.getOperand(1)), 10465 DAG.getConstant(1, VT)); 10466 } 10467 10468 return SDValue(); 10469} 10470 10471SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 10472 DAGCombinerInfo &DCI) const { 10473 SelectionDAG &DAG = DCI.DAG; 10474 switch (N->getOpcode()) { 10475 default: break; 10476 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 10477 case ISD::EXTRACT_VECTOR_ELT: 10478 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 10479 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 10480 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 10481 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 10482 case ISD::SHL: 10483 case ISD::SRA: 10484 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 10485 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 10486 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 10487 case X86ISD::FXOR: 10488 case X86ISD::FOR: return PerformFORCombine(N, DAG); 10489 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 10490 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 10491 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 10492 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 10493 } 10494 10495 return SDValue(); 10496} 10497 10498/// isTypeDesirableForOp - Return true if the target has native support for 10499/// the specified value type and it is 'desirable' to use the type for the 10500/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 10501/// instruction encodings are longer and some i16 instructions are slow. 10502bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 10503 if (!isTypeLegal(VT)) 10504 return false; 10505 if (VT != MVT::i16) 10506 return true; 10507 10508 switch (Opc) { 10509 default: 10510 return true; 10511 case ISD::LOAD: 10512 case ISD::SIGN_EXTEND: 10513 case ISD::ZERO_EXTEND: 10514 case ISD::ANY_EXTEND: 10515 case ISD::SHL: 10516 case ISD::SRL: 10517 case ISD::SUB: 10518 case ISD::ADD: 10519 case ISD::MUL: 10520 case ISD::AND: 10521 case ISD::OR: 10522 case ISD::XOR: 10523 return false; 10524 } 10525} 10526 10527static bool MayFoldLoad(SDValue Op) { 10528 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 10529} 10530 10531static bool MayFoldIntoStore(SDValue Op) { 10532 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 10533} 10534 10535/// IsDesirableToPromoteOp - This method query the target whether it is 10536/// beneficial for dag combiner to promote the specified node. If true, it 10537/// should return the desired promotion type by reference. 10538bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 10539 EVT VT = Op.getValueType(); 10540 if (VT != MVT::i16) 10541 return false; 10542 10543 bool Promote = false; 10544 bool Commute = false; 10545 switch (Op.getOpcode()) { 10546 default: break; 10547 case ISD::LOAD: { 10548 LoadSDNode *LD = cast<LoadSDNode>(Op); 10549 // If the non-extending load has a single use and it's not live out, then it 10550 // might be folded. 10551 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 10552 Op.hasOneUse()*/) { 10553 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 10554 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 10555 // The only case where we'd want to promote LOAD (rather then it being 10556 // promoted as an operand is when it's only use is liveout. 10557 if (UI->getOpcode() != ISD::CopyToReg) 10558 return false; 10559 } 10560 } 10561 Promote = true; 10562 break; 10563 } 10564 case ISD::SIGN_EXTEND: 10565 case ISD::ZERO_EXTEND: 10566 case ISD::ANY_EXTEND: 10567 Promote = true; 10568 break; 10569 case ISD::SHL: 10570 case ISD::SRL: { 10571 SDValue N0 = Op.getOperand(0); 10572 // Look out for (store (shl (load), x)). 10573 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 10574 return false; 10575 Promote = true; 10576 break; 10577 } 10578 case ISD::ADD: 10579 case ISD::MUL: 10580 case ISD::AND: 10581 case ISD::OR: 10582 case ISD::XOR: 10583 Commute = true; 10584 // fallthrough 10585 case ISD::SUB: { 10586 SDValue N0 = Op.getOperand(0); 10587 SDValue N1 = Op.getOperand(1); 10588 if (!Commute && MayFoldLoad(N1)) 10589 return false; 10590 // Avoid disabling potential load folding opportunities. 10591 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 10592 return false; 10593 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 10594 return false; 10595 Promote = true; 10596 } 10597 } 10598 10599 PVT = MVT::i32; 10600 return Promote; 10601} 10602 10603//===----------------------------------------------------------------------===// 10604// X86 Inline Assembly Support 10605//===----------------------------------------------------------------------===// 10606 10607static bool LowerToBSwap(CallInst *CI) { 10608 // FIXME: this should verify that we are targetting a 486 or better. If not, 10609 // we will turn this bswap into something that will be lowered to logical ops 10610 // instead of emitting the bswap asm. For now, we don't support 486 or lower 10611 // so don't worry about this. 10612 10613 // Verify this is a simple bswap. 10614 if (CI->getNumArgOperands() != 1 || 10615 CI->getType() != CI->getArgOperand(0)->getType() || 10616 !CI->getType()->isIntegerTy()) 10617 return false; 10618 10619 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 10620 if (!Ty || Ty->getBitWidth() % 16 != 0) 10621 return false; 10622 10623 // Okay, we can do this xform, do so now. 10624 const Type *Tys[] = { Ty }; 10625 Module *M = CI->getParent()->getParent()->getParent(); 10626 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 10627 10628 Value *Op = CI->getArgOperand(0); 10629 Op = CallInst::Create(Int, Op, CI->getName(), CI); 10630 10631 CI->replaceAllUsesWith(Op); 10632 CI->eraseFromParent(); 10633 return true; 10634} 10635 10636bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 10637 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 10638 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 10639 10640 std::string AsmStr = IA->getAsmString(); 10641 10642 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 10643 SmallVector<StringRef, 4> AsmPieces; 10644 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 10645 10646 switch (AsmPieces.size()) { 10647 default: return false; 10648 case 1: 10649 AsmStr = AsmPieces[0]; 10650 AsmPieces.clear(); 10651 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 10652 10653 // bswap $0 10654 if (AsmPieces.size() == 2 && 10655 (AsmPieces[0] == "bswap" || 10656 AsmPieces[0] == "bswapq" || 10657 AsmPieces[0] == "bswapl") && 10658 (AsmPieces[1] == "$0" || 10659 AsmPieces[1] == "${0:q}")) { 10660 // No need to check constraints, nothing other than the equivalent of 10661 // "=r,0" would be valid here. 10662 return LowerToBSwap(CI); 10663 } 10664 // rorw $$8, ${0:w} --> llvm.bswap.i16 10665 if (CI->getType()->isIntegerTy(16) && 10666 AsmPieces.size() == 3 && 10667 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 10668 AsmPieces[1] == "$$8," && 10669 AsmPieces[2] == "${0:w}" && 10670 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 10671 AsmPieces.clear(); 10672 const std::string &Constraints = IA->getConstraintString(); 10673 SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); 10674 std::sort(AsmPieces.begin(), AsmPieces.end()); 10675 if (AsmPieces.size() == 4 && 10676 AsmPieces[0] == "~{cc}" && 10677 AsmPieces[1] == "~{dirflag}" && 10678 AsmPieces[2] == "~{flags}" && 10679 AsmPieces[3] == "~{fpsr}") { 10680 return LowerToBSwap(CI); 10681 } 10682 } 10683 break; 10684 case 3: 10685 if (CI->getType()->isIntegerTy(64) && 10686 Constraints.size() >= 2 && 10687 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 10688 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 10689 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 10690 SmallVector<StringRef, 4> Words; 10691 SplitString(AsmPieces[0], Words, " \t"); 10692 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 10693 Words.clear(); 10694 SplitString(AsmPieces[1], Words, " \t"); 10695 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 10696 Words.clear(); 10697 SplitString(AsmPieces[2], Words, " \t,"); 10698 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 10699 Words[2] == "%edx") { 10700 return LowerToBSwap(CI); 10701 } 10702 } 10703 } 10704 } 10705 break; 10706 } 10707 return false; 10708} 10709 10710 10711 10712/// getConstraintType - Given a constraint letter, return the type of 10713/// constraint it is for this target. 10714X86TargetLowering::ConstraintType 10715X86TargetLowering::getConstraintType(const std::string &Constraint) const { 10716 if (Constraint.size() == 1) { 10717 switch (Constraint[0]) { 10718 case 'A': 10719 return C_Register; 10720 case 'f': 10721 case 'r': 10722 case 'R': 10723 case 'l': 10724 case 'q': 10725 case 'Q': 10726 case 'x': 10727 case 'y': 10728 case 'Y': 10729 return C_RegisterClass; 10730 case 'e': 10731 case 'Z': 10732 return C_Other; 10733 default: 10734 break; 10735 } 10736 } 10737 return TargetLowering::getConstraintType(Constraint); 10738} 10739 10740/// LowerXConstraint - try to replace an X constraint, which matches anything, 10741/// with another that has more specific requirements based on the type of the 10742/// corresponding operand. 10743const char *X86TargetLowering:: 10744LowerXConstraint(EVT ConstraintVT) const { 10745 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 10746 // 'f' like normal targets. 10747 if (ConstraintVT.isFloatingPoint()) { 10748 if (Subtarget->hasSSE2()) 10749 return "Y"; 10750 if (Subtarget->hasSSE1()) 10751 return "x"; 10752 } 10753 10754 return TargetLowering::LowerXConstraint(ConstraintVT); 10755} 10756 10757/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 10758/// vector. If it is invalid, don't add anything to Ops. 10759void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 10760 char Constraint, 10761 std::vector<SDValue>&Ops, 10762 SelectionDAG &DAG) const { 10763 SDValue Result(0, 0); 10764 10765 switch (Constraint) { 10766 default: break; 10767 case 'I': 10768 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10769 if (C->getZExtValue() <= 31) { 10770 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10771 break; 10772 } 10773 } 10774 return; 10775 case 'J': 10776 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10777 if (C->getZExtValue() <= 63) { 10778 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10779 break; 10780 } 10781 } 10782 return; 10783 case 'K': 10784 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10785 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 10786 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10787 break; 10788 } 10789 } 10790 return; 10791 case 'N': 10792 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10793 if (C->getZExtValue() <= 255) { 10794 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10795 break; 10796 } 10797 } 10798 return; 10799 case 'e': { 10800 // 32-bit signed value 10801 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10802 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10803 C->getSExtValue())) { 10804 // Widen to 64 bits here to get it sign extended. 10805 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 10806 break; 10807 } 10808 // FIXME gcc accepts some relocatable values here too, but only in certain 10809 // memory models; it's complicated. 10810 } 10811 return; 10812 } 10813 case 'Z': { 10814 // 32-bit unsigned value 10815 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10816 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10817 C->getZExtValue())) { 10818 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10819 break; 10820 } 10821 } 10822 // FIXME gcc accepts some relocatable values here too, but only in certain 10823 // memory models; it's complicated. 10824 return; 10825 } 10826 case 'i': { 10827 // Literal immediates are always ok. 10828 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 10829 // Widen to 64 bits here to get it sign extended. 10830 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 10831 break; 10832 } 10833 10834 // In any sort of PIC mode addresses need to be computed at runtime by 10835 // adding in a register or some sort of table lookup. These can't 10836 // be used as immediates. 10837 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 10838 return; 10839 10840 // If we are in non-pic codegen mode, we allow the address of a global (with 10841 // an optional displacement) to be used with 'i'. 10842 GlobalAddressSDNode *GA = 0; 10843 int64_t Offset = 0; 10844 10845 // Match either (GA), (GA+C), (GA+C1+C2), etc. 10846 while (1) { 10847 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 10848 Offset += GA->getOffset(); 10849 break; 10850 } else if (Op.getOpcode() == ISD::ADD) { 10851 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10852 Offset += C->getZExtValue(); 10853 Op = Op.getOperand(0); 10854 continue; 10855 } 10856 } else if (Op.getOpcode() == ISD::SUB) { 10857 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10858 Offset += -C->getZExtValue(); 10859 Op = Op.getOperand(0); 10860 continue; 10861 } 10862 } 10863 10864 // Otherwise, this isn't something we can handle, reject it. 10865 return; 10866 } 10867 10868 const GlobalValue *GV = GA->getGlobal(); 10869 // If we require an extra load to get this address, as in PIC mode, we 10870 // can't accept it. 10871 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 10872 getTargetMachine()))) 10873 return; 10874 10875 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 10876 GA->getValueType(0), Offset); 10877 break; 10878 } 10879 } 10880 10881 if (Result.getNode()) { 10882 Ops.push_back(Result); 10883 return; 10884 } 10885 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 10886} 10887 10888std::vector<unsigned> X86TargetLowering:: 10889getRegClassForInlineAsmConstraint(const std::string &Constraint, 10890 EVT VT) const { 10891 if (Constraint.size() == 1) { 10892 // FIXME: not handling fp-stack yet! 10893 switch (Constraint[0]) { // GCC X86 Constraint Letters 10894 default: break; // Unknown constraint letter 10895 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 10896 if (Subtarget->is64Bit()) { 10897 if (VT == MVT::i32) 10898 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 10899 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 10900 X86::R10D,X86::R11D,X86::R12D, 10901 X86::R13D,X86::R14D,X86::R15D, 10902 X86::EBP, X86::ESP, 0); 10903 else if (VT == MVT::i16) 10904 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 10905 X86::SI, X86::DI, X86::R8W,X86::R9W, 10906 X86::R10W,X86::R11W,X86::R12W, 10907 X86::R13W,X86::R14W,X86::R15W, 10908 X86::BP, X86::SP, 0); 10909 else if (VT == MVT::i8) 10910 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 10911 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 10912 X86::R10B,X86::R11B,X86::R12B, 10913 X86::R13B,X86::R14B,X86::R15B, 10914 X86::BPL, X86::SPL, 0); 10915 10916 else if (VT == MVT::i64) 10917 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 10918 X86::RSI, X86::RDI, X86::R8, X86::R9, 10919 X86::R10, X86::R11, X86::R12, 10920 X86::R13, X86::R14, X86::R15, 10921 X86::RBP, X86::RSP, 0); 10922 10923 break; 10924 } 10925 // 32-bit fallthrough 10926 case 'Q': // Q_REGS 10927 if (VT == MVT::i32) 10928 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 10929 else if (VT == MVT::i16) 10930 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 10931 else if (VT == MVT::i8) 10932 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 10933 else if (VT == MVT::i64) 10934 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 10935 break; 10936 } 10937 } 10938 10939 return std::vector<unsigned>(); 10940} 10941 10942std::pair<unsigned, const TargetRegisterClass*> 10943X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 10944 EVT VT) const { 10945 // First, see if this is a constraint that directly corresponds to an LLVM 10946 // register class. 10947 if (Constraint.size() == 1) { 10948 // GCC Constraint Letters 10949 switch (Constraint[0]) { 10950 default: break; 10951 case 'r': // GENERAL_REGS 10952 case 'l': // INDEX_REGS 10953 if (VT == MVT::i8) 10954 return std::make_pair(0U, X86::GR8RegisterClass); 10955 if (VT == MVT::i16) 10956 return std::make_pair(0U, X86::GR16RegisterClass); 10957 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10958 return std::make_pair(0U, X86::GR32RegisterClass); 10959 return std::make_pair(0U, X86::GR64RegisterClass); 10960 case 'R': // LEGACY_REGS 10961 if (VT == MVT::i8) 10962 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 10963 if (VT == MVT::i16) 10964 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 10965 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10966 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 10967 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 10968 case 'f': // FP Stack registers. 10969 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 10970 // value to the correct fpstack register class. 10971 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 10972 return std::make_pair(0U, X86::RFP32RegisterClass); 10973 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 10974 return std::make_pair(0U, X86::RFP64RegisterClass); 10975 return std::make_pair(0U, X86::RFP80RegisterClass); 10976 case 'y': // MMX_REGS if MMX allowed. 10977 if (!Subtarget->hasMMX()) break; 10978 return std::make_pair(0U, X86::VR64RegisterClass); 10979 case 'Y': // SSE_REGS if SSE2 allowed 10980 if (!Subtarget->hasSSE2()) break; 10981 // FALL THROUGH. 10982 case 'x': // SSE_REGS if SSE1 allowed 10983 if (!Subtarget->hasSSE1()) break; 10984 10985 switch (VT.getSimpleVT().SimpleTy) { 10986 default: break; 10987 // Scalar SSE types. 10988 case MVT::f32: 10989 case MVT::i32: 10990 return std::make_pair(0U, X86::FR32RegisterClass); 10991 case MVT::f64: 10992 case MVT::i64: 10993 return std::make_pair(0U, X86::FR64RegisterClass); 10994 // Vector types. 10995 case MVT::v16i8: 10996 case MVT::v8i16: 10997 case MVT::v4i32: 10998 case MVT::v2i64: 10999 case MVT::v4f32: 11000 case MVT::v2f64: 11001 return std::make_pair(0U, X86::VR128RegisterClass); 11002 } 11003 break; 11004 } 11005 } 11006 11007 // Use the default implementation in TargetLowering to convert the register 11008 // constraint into a member of a register class. 11009 std::pair<unsigned, const TargetRegisterClass*> Res; 11010 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 11011 11012 // Not found as a standard register? 11013 if (Res.second == 0) { 11014 // Map st(0) -> st(7) -> ST0 11015 if (Constraint.size() == 7 && Constraint[0] == '{' && 11016 tolower(Constraint[1]) == 's' && 11017 tolower(Constraint[2]) == 't' && 11018 Constraint[3] == '(' && 11019 (Constraint[4] >= '0' && Constraint[4] <= '7') && 11020 Constraint[5] == ')' && 11021 Constraint[6] == '}') { 11022 11023 Res.first = X86::ST0+Constraint[4]-'0'; 11024 Res.second = X86::RFP80RegisterClass; 11025 return Res; 11026 } 11027 11028 // GCC allows "st(0)" to be called just plain "st". 11029 if (StringRef("{st}").equals_lower(Constraint)) { 11030 Res.first = X86::ST0; 11031 Res.second = X86::RFP80RegisterClass; 11032 return Res; 11033 } 11034 11035 // flags -> EFLAGS 11036 if (StringRef("{flags}").equals_lower(Constraint)) { 11037 Res.first = X86::EFLAGS; 11038 Res.second = X86::CCRRegisterClass; 11039 return Res; 11040 } 11041 11042 // 'A' means EAX + EDX. 11043 if (Constraint == "A") { 11044 Res.first = X86::EAX; 11045 Res.second = X86::GR32_ADRegisterClass; 11046 return Res; 11047 } 11048 return Res; 11049 } 11050 11051 // Otherwise, check to see if this is a register class of the wrong value 11052 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 11053 // turn into {ax},{dx}. 11054 if (Res.second->hasType(VT)) 11055 return Res; // Correct type already, nothing to do. 11056 11057 // All of the single-register GCC register classes map their values onto 11058 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 11059 // really want an 8-bit or 32-bit register, map to the appropriate register 11060 // class and return the appropriate register. 11061 if (Res.second == X86::GR16RegisterClass) { 11062 if (VT == MVT::i8) { 11063 unsigned DestReg = 0; 11064 switch (Res.first) { 11065 default: break; 11066 case X86::AX: DestReg = X86::AL; break; 11067 case X86::DX: DestReg = X86::DL; break; 11068 case X86::CX: DestReg = X86::CL; break; 11069 case X86::BX: DestReg = X86::BL; break; 11070 } 11071 if (DestReg) { 11072 Res.first = DestReg; 11073 Res.second = X86::GR8RegisterClass; 11074 } 11075 } else if (VT == MVT::i32) { 11076 unsigned DestReg = 0; 11077 switch (Res.first) { 11078 default: break; 11079 case X86::AX: DestReg = X86::EAX; break; 11080 case X86::DX: DestReg = X86::EDX; break; 11081 case X86::CX: DestReg = X86::ECX; break; 11082 case X86::BX: DestReg = X86::EBX; break; 11083 case X86::SI: DestReg = X86::ESI; break; 11084 case X86::DI: DestReg = X86::EDI; break; 11085 case X86::BP: DestReg = X86::EBP; break; 11086 case X86::SP: DestReg = X86::ESP; break; 11087 } 11088 if (DestReg) { 11089 Res.first = DestReg; 11090 Res.second = X86::GR32RegisterClass; 11091 } 11092 } else if (VT == MVT::i64) { 11093 unsigned DestReg = 0; 11094 switch (Res.first) { 11095 default: break; 11096 case X86::AX: DestReg = X86::RAX; break; 11097 case X86::DX: DestReg = X86::RDX; break; 11098 case X86::CX: DestReg = X86::RCX; break; 11099 case X86::BX: DestReg = X86::RBX; break; 11100 case X86::SI: DestReg = X86::RSI; break; 11101 case X86::DI: DestReg = X86::RDI; break; 11102 case X86::BP: DestReg = X86::RBP; break; 11103 case X86::SP: DestReg = X86::RSP; break; 11104 } 11105 if (DestReg) { 11106 Res.first = DestReg; 11107 Res.second = X86::GR64RegisterClass; 11108 } 11109 } 11110 } else if (Res.second == X86::FR32RegisterClass || 11111 Res.second == X86::FR64RegisterClass || 11112 Res.second == X86::VR128RegisterClass) { 11113 // Handle references to XMM physical registers that got mapped into the 11114 // wrong class. This can happen with constraints like {xmm0} where the 11115 // target independent register mapper will just pick the first match it can 11116 // find, ignoring the required type. 11117 if (VT == MVT::f32) 11118 Res.second = X86::FR32RegisterClass; 11119 else if (VT == MVT::f64) 11120 Res.second = X86::FR64RegisterClass; 11121 else if (X86::VR128RegisterClass->hasType(VT)) 11122 Res.second = X86::VR128RegisterClass; 11123 } 11124 11125 return Res; 11126} 11127