X86ISelLowering.cpp revision f321e1075eabae96f62b1f2570d9dee5d10b8200
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/SmallSet.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/VariadicFunction.h" 47#include "llvm/Support/CallSite.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/Dwarf.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/MathExtras.h" 52#include "llvm/Support/raw_ostream.h" 53#include "llvm/Target/TargetOptions.h" 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63static SDValue Insert128BitVector(SDValue Result, 64 SDValue Vec, 65 SDValue Idx, 66 SelectionDAG &DAG, 67 DebugLoc dl); 68 69static SDValue Extract128BitVector(SDValue Vec, 70 SDValue Idx, 71 SelectionDAG &DAG, 72 DebugLoc dl); 73 74/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 75/// sets things up to match to an AVX VEXTRACTF128 instruction or a 76/// simple subregister reference. Idx is an index in the 128 bits we 77/// want. It need not be aligned to a 128-bit bounday. That makes 78/// lowering EXTRACT_VECTOR_ELT operations easier. 79static SDValue Extract128BitVector(SDValue Vec, 80 SDValue Idx, 81 SelectionDAG &DAG, 82 DebugLoc dl) { 83 EVT VT = Vec.getValueType(); 84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 85 EVT ElVT = VT.getVectorElementType(); 86 int Factor = VT.getSizeInBits()/128; 87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 88 VT.getVectorNumElements()/Factor); 89 90 // Extract from UNDEF is UNDEF. 91 if (Vec.getOpcode() == ISD::UNDEF) 92 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 93 94 if (isa<ConstantSDNode>(Idx)) { 95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 96 97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 98 // we can match to VEXTRACTF128. 99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 100 101 // This is the index of the first element of the 128-bit chunk 102 // we want. 103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 104 * ElemsPerChunk); 105 106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 108 VecIdx); 109 110 return Result; 111 } 112 113 return SDValue(); 114} 115 116/// Generate a DAG to put 128-bits into a vector > 128 bits. This 117/// sets things up to match to an AVX VINSERTF128 instruction or a 118/// simple superregister reference. Idx is an index in the 128 bits 119/// we want. It need not be aligned to a 128-bit bounday. That makes 120/// lowering INSERT_VECTOR_ELT operations easier. 121static SDValue Insert128BitVector(SDValue Result, 122 SDValue Vec, 123 SDValue Idx, 124 SelectionDAG &DAG, 125 DebugLoc dl) { 126 if (isa<ConstantSDNode>(Idx)) { 127 EVT VT = Vec.getValueType(); 128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 129 130 EVT ElVT = VT.getVectorElementType(); 131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 132 EVT ResultVT = Result.getValueType(); 133 134 // Insert the relevant 128 bits. 135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 136 137 // This is the index of the first element of the 128-bit chunk 138 // we want. 139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 140 * ElemsPerChunk); 141 142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 144 VecIdx); 145 return Result; 146 } 147 148 return SDValue(); 149} 150 151static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 bool is64Bit = Subtarget->is64Bit(); 154 155 if (Subtarget->isTargetEnvMacho()) { 156 if (is64Bit) 157 return new X8664_MachoTargetObjectFile(); 158 return new TargetLoweringObjectFileMachO(); 159 } 160 161 if (Subtarget->isTargetELF()) 162 return new TargetLoweringObjectFileELF(); 163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 164 return new TargetLoweringObjectFileCOFF(); 165 llvm_unreachable("unknown subtarget type"); 166} 167 168X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 169 : TargetLowering(TM, createTLOF(TM)) { 170 Subtarget = &TM.getSubtarget<X86Subtarget>(); 171 X86ScalarSSEf64 = Subtarget->hasXMMInt(); 172 X86ScalarSSEf32 = Subtarget->hasXMM(); 173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 174 175 RegInfo = TM.getRegisterInfo(); 176 TD = getTargetData(); 177 178 // Set up the TargetLowering object. 179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 180 181 // X86 is weird, it always uses i8 for shift amounts and setcc results. 182 setBooleanContents(ZeroOrOneBooleanContent); 183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 185 186 // For 64-bit since we have so many registers use the ILP scheduler, for 187 // 32-bit code use the register pressure specific scheduling. 188 if (Subtarget->is64Bit()) 189 setSchedulingPreference(Sched::ILP); 190 else 191 setSchedulingPreference(Sched::RegPressure); 192 setStackPointerRegisterToSaveRestore(X86StackPtr); 193 194 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 195 // Setup Windows compiler runtime calls. 196 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 197 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 198 setLibcallName(RTLIB::SREM_I64, "_allrem"); 199 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 200 setLibcallName(RTLIB::MUL_I64, "_allmul"); 201 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 208 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 209 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 210 } 211 212 if (Subtarget->isTargetDarwin()) { 213 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 214 setUseUnderscoreSetJmp(false); 215 setUseUnderscoreLongJmp(false); 216 } else if (Subtarget->isTargetMingw()) { 217 // MS runtime is weird: it exports _setjmp, but longjmp! 218 setUseUnderscoreSetJmp(true); 219 setUseUnderscoreLongJmp(false); 220 } else { 221 setUseUnderscoreSetJmp(true); 222 setUseUnderscoreLongJmp(true); 223 } 224 225 // Set up the register classes. 226 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 227 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 228 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 229 if (Subtarget->is64Bit()) 230 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 231 232 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 233 234 // We don't accept any truncstore of integer registers. 235 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 236 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 237 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 238 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 239 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 240 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 241 242 // SETOEQ and SETUNE require checking two conditions. 243 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 244 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 245 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 248 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 249 250 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 251 // operation. 252 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 253 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 254 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 255 256 if (Subtarget->is64Bit()) { 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 258 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 259 } else if (!TM.Options.UseSoftFloat) { 260 // We have an algorithm for SSE2->double, and we turn this into a 261 // 64-bit FILD followed by conditional FADD for other targets. 262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 263 // We have an algorithm for SSE2, and we turn this into a 64-bit 264 // FILD for other targets. 265 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 266 } 267 268 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 269 // this operation. 270 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 271 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 272 273 if (!TM.Options.UseSoftFloat) { 274 // SSE has no i16 to fp conversion, only i32 275 if (X86ScalarSSEf32) { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 // f32 and f64 cases are Legal, f80 case is not 278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 279 } else { 280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 281 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 282 } 283 } else { 284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 286 } 287 288 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 289 // are Legal, f80 is custom lowered. 290 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 291 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 292 293 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 294 // this operation. 295 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 297 298 if (X86ScalarSSEf32) { 299 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 300 // f32 and f64 cases are Legal, f80 case is not 301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 302 } else { 303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 304 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 305 } 306 307 // Handle FP_TO_UINT by promoting the destination to a larger signed 308 // conversion. 309 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 310 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 311 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 312 313 if (Subtarget->is64Bit()) { 314 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 316 } else if (!TM.Options.UseSoftFloat) { 317 // Since AVX is a superset of SSE3, only check for SSE here. 318 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 319 // Expand FP_TO_UINT into a select. 320 // FIXME: We would like to use a Custom expander here eventually to do 321 // the optimal thing for SSE vs. the default expansion in the legalizer. 322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 323 else 324 // With SSE3 we can use fisttpll to convert to a signed i64; without 325 // SSE, we're stuck with a fistpll. 326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 327 } 328 329 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 330 if (!X86ScalarSSEf64) { 331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 333 if (Subtarget->is64Bit()) { 334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 335 // Without SSE, i64->f64 goes through memory. 336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 337 } 338 } 339 340 // Scalar integer divide and remainder are lowered to use operations that 341 // produce two results, to match the available instructions. This exposes 342 // the two-result form to trivial CSE, which is able to combine x/y and x%y 343 // into a single instruction. 344 // 345 // Scalar integer multiply-high is also lowered to use two-result 346 // operations, to match the available instructions. However, plain multiply 347 // (low) operations are left as Legal, as there are single-result 348 // instructions for this in x86. Using the two-result multiply instructions 349 // when both high and low results are needed must be arranged by dagcombine. 350 for (unsigned i = 0, e = 4; i != e; ++i) { 351 MVT VT = IntVTs[i]; 352 setOperationAction(ISD::MULHS, VT, Expand); 353 setOperationAction(ISD::MULHU, VT, Expand); 354 setOperationAction(ISD::SDIV, VT, Expand); 355 setOperationAction(ISD::UDIV, VT, Expand); 356 setOperationAction(ISD::SREM, VT, Expand); 357 setOperationAction(ISD::UREM, VT, Expand); 358 359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 360 setOperationAction(ISD::ADDC, VT, Custom); 361 setOperationAction(ISD::ADDE, VT, Custom); 362 setOperationAction(ISD::SUBC, VT, Custom); 363 setOperationAction(ISD::SUBE, VT, Custom); 364 } 365 366 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 367 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 368 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 370 if (Subtarget->is64Bit()) 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 376 setOperationAction(ISD::FREM , MVT::f32 , Expand); 377 setOperationAction(ISD::FREM , MVT::f64 , Expand); 378 setOperationAction(ISD::FREM , MVT::f80 , Expand); 379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 380 381 // Promote the i8 variants and force them on up to i32 which has a shorter 382 // encoding. 383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 384 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 385 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 386 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 387 if (Subtarget->hasBMI()) { 388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 390 if (Subtarget->is64Bit()) 391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 392 } else { 393 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 394 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 395 if (Subtarget->is64Bit()) 396 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 397 } 398 399 if (Subtarget->hasLZCNT()) { 400 // When promoting the i8 variants, force them to i32 for a shorter 401 // encoding. 402 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 403 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 405 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 408 if (Subtarget->is64Bit()) 409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 410 } else { 411 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 412 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 413 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 417 if (Subtarget->is64Bit()) { 418 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 420 } 421 } 422 423 if (Subtarget->hasPOPCNT()) { 424 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 425 } else { 426 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 427 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 428 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 429 if (Subtarget->is64Bit()) 430 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 431 } 432 433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 434 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 435 436 // These should be promoted to a larger select which is supported. 437 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 438 // X86 wants to expand cmov itself. 439 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 440 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 441 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 442 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 443 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 444 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 446 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 447 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 448 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 449 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 450 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 451 if (Subtarget->is64Bit()) { 452 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 453 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 454 } 455 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 456 457 // Darwin ABI issue. 458 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 459 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 460 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 461 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 462 if (Subtarget->is64Bit()) 463 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 464 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 465 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 466 if (Subtarget->is64Bit()) { 467 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 468 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 469 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 470 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 471 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 472 } 473 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 474 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 475 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 476 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 477 if (Subtarget->is64Bit()) { 478 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 479 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 480 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 481 } 482 483 if (Subtarget->hasXMM()) 484 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 485 486 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 487 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 488 489 // On X86 and X86-64, atomic operations are lowered to locked instructions. 490 // Locked instructions, in turn, have implicit fence semantics (all memory 491 // operations are flushed before issuing the locked instruction, and they 492 // are not buffered), so we can fold away the common pattern of 493 // fence-atomic-fence. 494 setShouldFoldAtomicFences(true); 495 496 // Expand certain atomics 497 for (unsigned i = 0, e = 4; i != e; ++i) { 498 MVT VT = IntVTs[i]; 499 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 500 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 501 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 502 } 503 504 if (!Subtarget->is64Bit()) { 505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 513 } 514 515 if (Subtarget->hasCmpxchg16b()) { 516 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 517 } 518 519 // FIXME - use subtarget debug flags 520 if (!Subtarget->isTargetDarwin() && 521 !Subtarget->isTargetELF() && 522 !Subtarget->isTargetCygMing()) { 523 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 524 } 525 526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 527 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 528 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 529 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 530 if (Subtarget->is64Bit()) { 531 setExceptionPointerRegister(X86::RAX); 532 setExceptionSelectorRegister(X86::RDX); 533 } else { 534 setExceptionPointerRegister(X86::EAX); 535 setExceptionSelectorRegister(X86::EDX); 536 } 537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 539 540 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 541 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 542 543 setOperationAction(ISD::TRAP, MVT::Other, Legal); 544 545 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 546 setOperationAction(ISD::VASTART , MVT::Other, Custom); 547 setOperationAction(ISD::VAEND , MVT::Other, Expand); 548 if (Subtarget->is64Bit()) { 549 setOperationAction(ISD::VAARG , MVT::Other, Custom); 550 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 551 } else { 552 setOperationAction(ISD::VAARG , MVT::Other, Expand); 553 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 554 } 555 556 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 557 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 558 559 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 561 MVT::i64 : MVT::i32, Custom); 562 else if (TM.Options.EnableSegmentedStacks) 563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 564 MVT::i64 : MVT::i32, Custom); 565 else 566 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 567 MVT::i64 : MVT::i32, Expand); 568 569 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 570 // f32 and f64 use SSE. 571 // Set up the FP register classes. 572 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 573 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 574 575 // Use ANDPD to simulate FABS. 576 setOperationAction(ISD::FABS , MVT::f64, Custom); 577 setOperationAction(ISD::FABS , MVT::f32, Custom); 578 579 // Use XORP to simulate FNEG. 580 setOperationAction(ISD::FNEG , MVT::f64, Custom); 581 setOperationAction(ISD::FNEG , MVT::f32, Custom); 582 583 // Use ANDPD and ORPD to simulate FCOPYSIGN. 584 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 585 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 586 587 // Lower this to FGETSIGNx86 plus an AND. 588 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 589 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 590 591 // We don't support sin/cos/fmod 592 setOperationAction(ISD::FSIN , MVT::f64, Expand); 593 setOperationAction(ISD::FCOS , MVT::f64, Expand); 594 setOperationAction(ISD::FSIN , MVT::f32, Expand); 595 setOperationAction(ISD::FCOS , MVT::f32, Expand); 596 597 // Expand FP immediates into loads from the stack, except for the special 598 // cases we handle. 599 addLegalFPImmediate(APFloat(+0.0)); // xorpd 600 addLegalFPImmediate(APFloat(+0.0f)); // xorps 601 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 602 // Use SSE for f32, x87 for f64. 603 // Set up the FP register classes. 604 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 605 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 606 607 // Use ANDPS to simulate FABS. 608 setOperationAction(ISD::FABS , MVT::f32, Custom); 609 610 // Use XORP to simulate FNEG. 611 setOperationAction(ISD::FNEG , MVT::f32, Custom); 612 613 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 614 615 // Use ANDPS and ORPS to simulate FCOPYSIGN. 616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 618 619 // We don't support sin/cos/fmod 620 setOperationAction(ISD::FSIN , MVT::f32, Expand); 621 setOperationAction(ISD::FCOS , MVT::f32, Expand); 622 623 // Special cases we handle for FP constants. 624 addLegalFPImmediate(APFloat(+0.0f)); // xorps 625 addLegalFPImmediate(APFloat(+0.0)); // FLD0 626 addLegalFPImmediate(APFloat(+1.0)); // FLD1 627 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 628 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 629 630 if (!TM.Options.UnsafeFPMath) { 631 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 632 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 633 } 634 } else if (!TM.Options.UseSoftFloat) { 635 // f32 and f64 in x87. 636 // Set up the FP register classes. 637 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 638 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 639 640 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 641 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 642 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 643 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 644 645 if (!TM.Options.UnsafeFPMath) { 646 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 647 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 648 } 649 addLegalFPImmediate(APFloat(+0.0)); // FLD0 650 addLegalFPImmediate(APFloat(+1.0)); // FLD1 651 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 652 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 653 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 654 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 655 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 656 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 657 } 658 659 // We don't support FMA. 660 setOperationAction(ISD::FMA, MVT::f64, Expand); 661 setOperationAction(ISD::FMA, MVT::f32, Expand); 662 663 // Long double always uses X87. 664 if (!TM.Options.UseSoftFloat) { 665 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 666 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 667 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 668 { 669 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 670 addLegalFPImmediate(TmpFlt); // FLD0 671 TmpFlt.changeSign(); 672 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 673 674 bool ignored; 675 APFloat TmpFlt2(+1.0); 676 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 677 &ignored); 678 addLegalFPImmediate(TmpFlt2); // FLD1 679 TmpFlt2.changeSign(); 680 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 681 } 682 683 if (!TM.Options.UnsafeFPMath) { 684 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 685 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 686 } 687 688 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 689 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 690 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 691 setOperationAction(ISD::FRINT, MVT::f80, Expand); 692 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 693 setOperationAction(ISD::FMA, MVT::f80, Expand); 694 } 695 696 // Always use a library call for pow. 697 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 698 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 699 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 700 701 setOperationAction(ISD::FLOG, MVT::f80, Expand); 702 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 703 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 704 setOperationAction(ISD::FEXP, MVT::f80, Expand); 705 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 706 707 // First set operation action for all vector types to either promote 708 // (for widening) or expand (for scalarization). Then we will selectively 709 // turn on ones that can be effectively codegen'd. 710 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 711 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 712 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 729 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 730 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 764 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 767 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 768 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 769 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 770 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 771 setTruncStoreAction((MVT::SimpleValueType)VT, 772 (MVT::SimpleValueType)InnerVT, Expand); 773 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 774 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 775 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 776 } 777 778 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 779 // with -msoft-float, disable use of MMX as well. 780 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 781 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 782 // No operations on x86mmx supported, everything uses intrinsics. 783 } 784 785 // MMX-sized vectors (other than x86mmx) are expected to be expanded 786 // into smaller operations. 787 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 788 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 789 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 790 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 791 setOperationAction(ISD::AND, MVT::v8i8, Expand); 792 setOperationAction(ISD::AND, MVT::v4i16, Expand); 793 setOperationAction(ISD::AND, MVT::v2i32, Expand); 794 setOperationAction(ISD::AND, MVT::v1i64, Expand); 795 setOperationAction(ISD::OR, MVT::v8i8, Expand); 796 setOperationAction(ISD::OR, MVT::v4i16, Expand); 797 setOperationAction(ISD::OR, MVT::v2i32, Expand); 798 setOperationAction(ISD::OR, MVT::v1i64, Expand); 799 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 800 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 801 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 802 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 807 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 808 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 809 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 810 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 811 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 813 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 814 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 815 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 816 817 if (!TM.Options.UseSoftFloat && Subtarget->hasXMM()) { 818 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 819 820 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 821 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 822 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 823 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 824 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 825 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 826 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 827 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 828 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 830 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 831 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 832 } 833 834 if (!TM.Options.UseSoftFloat && Subtarget->hasXMMInt()) { 835 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 836 837 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 838 // registers cannot be used even for integer operations. 839 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 840 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 841 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 842 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 843 844 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 845 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 846 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 847 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 848 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 849 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 850 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 851 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 852 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 853 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 854 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 855 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 856 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 857 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 858 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 859 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 860 861 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 862 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 863 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 864 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 865 866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 871 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 877 878 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 879 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 880 EVT VT = (MVT::SimpleValueType)i; 881 // Do not attempt to custom lower non-power-of-2 vectors 882 if (!isPowerOf2_32(VT.getVectorNumElements())) 883 continue; 884 // Do not attempt to custom lower non-128-bit vectors 885 if (!VT.is128BitVector()) 886 continue; 887 setOperationAction(ISD::BUILD_VECTOR, 888 VT.getSimpleVT().SimpleTy, Custom); 889 setOperationAction(ISD::VECTOR_SHUFFLE, 890 VT.getSimpleVT().SimpleTy, Custom); 891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 892 VT.getSimpleVT().SimpleTy, Custom); 893 } 894 895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 896 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 898 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 899 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 900 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 901 902 if (Subtarget->is64Bit()) { 903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 905 } 906 907 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 908 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 909 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 910 EVT VT = SVT; 911 912 // Do not attempt to promote non-128-bit vectors 913 if (!VT.is128BitVector()) 914 continue; 915 916 setOperationAction(ISD::AND, SVT, Promote); 917 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 918 setOperationAction(ISD::OR, SVT, Promote); 919 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 920 setOperationAction(ISD::XOR, SVT, Promote); 921 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 922 setOperationAction(ISD::LOAD, SVT, Promote); 923 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 924 setOperationAction(ISD::SELECT, SVT, Promote); 925 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 926 } 927 928 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 929 930 // Custom lower v2i64 and v2f64 selects. 931 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 932 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 933 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 934 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 935 936 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 937 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 938 } 939 940 if (Subtarget->hasSSE41orAVX()) { 941 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 942 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 943 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 944 setOperationAction(ISD::FRINT, MVT::f32, Legal); 945 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 946 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 947 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 948 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 949 setOperationAction(ISD::FRINT, MVT::f64, Legal); 950 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 951 952 // FIXME: Do we need to handle scalar-to-vector here? 953 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 954 955 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 957 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 958 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 959 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 960 961 // i8 and i16 vectors are custom , because the source register and source 962 // source memory operand types are not the same width. f32 vectors are 963 // custom since the immediate controlling the insert encodes additional 964 // information. 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 969 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 974 975 // FIXME: these should be Legal but thats only for the case where 976 // the index is constant. For now custom expand to deal with that. 977 if (Subtarget->is64Bit()) { 978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 980 } 981 } 982 983 if (Subtarget->hasXMMInt()) { 984 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 985 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 986 987 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 988 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 989 990 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 991 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 992 993 if (Subtarget->hasAVX2()) { 994 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 995 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 996 997 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 998 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 999 1000 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 1001 } else { 1002 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1003 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1004 1005 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1006 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1007 1008 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1009 } 1010 } 1011 1012 if (Subtarget->hasSSE42orAVX()) 1013 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1014 1015 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1016 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1017 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1018 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1019 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1020 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1021 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1022 1023 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1024 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1025 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1026 1027 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1031 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1032 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1033 1034 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1037 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1038 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1039 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1040 1041 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1042 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1043 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1044 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1051 1052 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1056 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1057 1058 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1059 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1060 1061 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1063 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1064 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1065 1066 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1067 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1068 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1069 1070 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1072 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1073 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1074 1075 if (Subtarget->hasAVX2()) { 1076 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1077 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1078 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1079 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1080 1081 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1082 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1083 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1084 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1085 1086 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1087 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1088 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1089 // Don't lower v32i8 because there is no 128-bit byte mul 1090 1091 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1092 1093 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1094 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1095 1096 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1097 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1098 1099 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1100 } else { 1101 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1102 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1103 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1104 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1105 1106 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1107 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1108 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1109 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1110 1111 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1112 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1113 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1114 // Don't lower v32i8 because there is no 128-bit byte mul 1115 1116 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1117 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1118 1119 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1120 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1121 1122 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1123 } 1124 1125 // Custom lower several nodes for 256-bit types. 1126 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1127 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1128 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1129 EVT VT = SVT; 1130 1131 // Extract subvector is special because the value type 1132 // (result) is 128-bit but the source is 256-bit wide. 1133 if (VT.is128BitVector()) 1134 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1135 1136 // Do not attempt to custom lower other non-256-bit vectors 1137 if (!VT.is256BitVector()) 1138 continue; 1139 1140 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1141 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1142 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1144 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1145 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1146 } 1147 1148 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1149 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1150 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1151 EVT VT = SVT; 1152 1153 // Do not attempt to promote non-256-bit vectors 1154 if (!VT.is256BitVector()) 1155 continue; 1156 1157 setOperationAction(ISD::AND, SVT, Promote); 1158 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1159 setOperationAction(ISD::OR, SVT, Promote); 1160 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1161 setOperationAction(ISD::XOR, SVT, Promote); 1162 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1163 setOperationAction(ISD::LOAD, SVT, Promote); 1164 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1165 setOperationAction(ISD::SELECT, SVT, Promote); 1166 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1167 } 1168 } 1169 1170 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1171 // of this type with custom code. 1172 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1173 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1174 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1175 Custom); 1176 } 1177 1178 // We want to custom lower some of our intrinsics. 1179 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1180 1181 1182 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1183 // handle type legalization for these operations here. 1184 // 1185 // FIXME: We really should do custom legalization for addition and 1186 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1187 // than generic legalization for 64-bit multiplication-with-overflow, though. 1188 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1189 // Add/Sub/Mul with overflow operations are custom lowered. 1190 MVT VT = IntVTs[i]; 1191 setOperationAction(ISD::SADDO, VT, Custom); 1192 setOperationAction(ISD::UADDO, VT, Custom); 1193 setOperationAction(ISD::SSUBO, VT, Custom); 1194 setOperationAction(ISD::USUBO, VT, Custom); 1195 setOperationAction(ISD::SMULO, VT, Custom); 1196 setOperationAction(ISD::UMULO, VT, Custom); 1197 } 1198 1199 // There are no 8-bit 3-address imul/mul instructions 1200 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1201 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1202 1203 if (!Subtarget->is64Bit()) { 1204 // These libcalls are not available in 32-bit. 1205 setLibcallName(RTLIB::SHL_I128, 0); 1206 setLibcallName(RTLIB::SRL_I128, 0); 1207 setLibcallName(RTLIB::SRA_I128, 0); 1208 } 1209 1210 // We have target-specific dag combine patterns for the following nodes: 1211 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1212 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1213 setTargetDAGCombine(ISD::VSELECT); 1214 setTargetDAGCombine(ISD::SELECT); 1215 setTargetDAGCombine(ISD::SHL); 1216 setTargetDAGCombine(ISD::SRA); 1217 setTargetDAGCombine(ISD::SRL); 1218 setTargetDAGCombine(ISD::OR); 1219 setTargetDAGCombine(ISD::AND); 1220 setTargetDAGCombine(ISD::ADD); 1221 setTargetDAGCombine(ISD::FADD); 1222 setTargetDAGCombine(ISD::FSUB); 1223 setTargetDAGCombine(ISD::SUB); 1224 setTargetDAGCombine(ISD::LOAD); 1225 setTargetDAGCombine(ISD::STORE); 1226 setTargetDAGCombine(ISD::ZERO_EXTEND); 1227 setTargetDAGCombine(ISD::SINT_TO_FP); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279 return; 1280} 1281 1282/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1283/// function arguments in the caller parameter area. For X86, aggregates 1284/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1285/// are at 4-byte boundaries. 1286unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1287 if (Subtarget->is64Bit()) { 1288 // Max of 8 and alignment of type. 1289 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1290 if (TyAlign > 8) 1291 return TyAlign; 1292 return 8; 1293 } 1294 1295 unsigned Align = 4; 1296 if (Subtarget->hasXMM()) 1297 getMaxByValAlign(Ty, Align); 1298 return Align; 1299} 1300 1301/// getOptimalMemOpType - Returns the target specific optimal type for load 1302/// and store operations as a result of memset, memcpy, and memmove 1303/// lowering. If DstAlign is zero that means it's safe to destination 1304/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1305/// means there isn't a need to check it against alignment requirement, 1306/// probably because the source does not need to be loaded. If 1307/// 'IsZeroVal' is true, that means it's safe to return a 1308/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1309/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1310/// constant so it does not need to be loaded. 1311/// It returns EVT::Other if the type should be determined using generic 1312/// target-independent logic. 1313EVT 1314X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1315 unsigned DstAlign, unsigned SrcAlign, 1316 bool IsZeroVal, 1317 bool MemcpyStrSrc, 1318 MachineFunction &MF) const { 1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1320 // linux. This is because the stack realignment code can't handle certain 1321 // cases like PR2962. This should be removed when PR2962 is fixed. 1322 const Function *F = MF.getFunction(); 1323 if (IsZeroVal && 1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1325 if (Size >= 16 && 1326 (Subtarget->isUnalignedMemAccessFast() || 1327 ((DstAlign == 0 || DstAlign >= 16) && 1328 (SrcAlign == 0 || SrcAlign >= 16))) && 1329 Subtarget->getStackAlignment() >= 16) { 1330 if (Subtarget->hasAVX() && 1331 Subtarget->getStackAlignment() >= 32) 1332 return MVT::v8f32; 1333 if (Subtarget->hasXMMInt()) 1334 return MVT::v4i32; 1335 if (Subtarget->hasXMM()) 1336 return MVT::v4f32; 1337 } else if (!MemcpyStrSrc && Size >= 8 && 1338 !Subtarget->is64Bit() && 1339 Subtarget->getStackAlignment() >= 8 && 1340 Subtarget->hasXMMInt()) { 1341 // Do not use f64 to lower memcpy if source is string constant. It's 1342 // better to use i32 to avoid the loads. 1343 return MVT::f64; 1344 } 1345 } 1346 if (Subtarget->is64Bit() && Size >= 8) 1347 return MVT::i64; 1348 return MVT::i32; 1349} 1350 1351/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1352/// current function. The returned value is a member of the 1353/// MachineJumpTableInfo::JTEntryKind enum. 1354unsigned X86TargetLowering::getJumpTableEncoding() const { 1355 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1356 // symbol. 1357 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1358 Subtarget->isPICStyleGOT()) 1359 return MachineJumpTableInfo::EK_Custom32; 1360 1361 // Otherwise, use the normal jump table encoding heuristics. 1362 return TargetLowering::getJumpTableEncoding(); 1363} 1364 1365const MCExpr * 1366X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1367 const MachineBasicBlock *MBB, 1368 unsigned uid,MCContext &Ctx) const{ 1369 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1370 Subtarget->isPICStyleGOT()); 1371 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1372 // entries. 1373 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1374 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1375} 1376 1377/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1378/// jumptable. 1379SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1380 SelectionDAG &DAG) const { 1381 if (!Subtarget->is64Bit()) 1382 // This doesn't have DebugLoc associated with it, but is not really the 1383 // same as a Register. 1384 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1385 return Table; 1386} 1387 1388/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1389/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1390/// MCExpr. 1391const MCExpr *X86TargetLowering:: 1392getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1393 MCContext &Ctx) const { 1394 // X86-64 uses RIP relative addressing based on the jump table label. 1395 if (Subtarget->isPICStyleRIPRel()) 1396 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1397 1398 // Otherwise, the reference is relative to the PIC base. 1399 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1400} 1401 1402// FIXME: Why this routine is here? Move to RegInfo! 1403std::pair<const TargetRegisterClass*, uint8_t> 1404X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1405 const TargetRegisterClass *RRC = 0; 1406 uint8_t Cost = 1; 1407 switch (VT.getSimpleVT().SimpleTy) { 1408 default: 1409 return TargetLowering::findRepresentativeClass(VT); 1410 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1411 RRC = (Subtarget->is64Bit() 1412 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1413 break; 1414 case MVT::x86mmx: 1415 RRC = X86::VR64RegisterClass; 1416 break; 1417 case MVT::f32: case MVT::f64: 1418 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1419 case MVT::v4f32: case MVT::v2f64: 1420 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1421 case MVT::v4f64: 1422 RRC = X86::VR128RegisterClass; 1423 break; 1424 } 1425 return std::make_pair(RRC, Cost); 1426} 1427 1428bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1429 unsigned &Offset) const { 1430 if (!Subtarget->isTargetLinux()) 1431 return false; 1432 1433 if (Subtarget->is64Bit()) { 1434 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1435 Offset = 0x28; 1436 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1437 AddressSpace = 256; 1438 else 1439 AddressSpace = 257; 1440 } else { 1441 // %gs:0x14 on i386 1442 Offset = 0x14; 1443 AddressSpace = 256; 1444 } 1445 return true; 1446} 1447 1448 1449//===----------------------------------------------------------------------===// 1450// Return Value Calling Convention Implementation 1451//===----------------------------------------------------------------------===// 1452 1453#include "X86GenCallingConv.inc" 1454 1455bool 1456X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1457 MachineFunction &MF, bool isVarArg, 1458 const SmallVectorImpl<ISD::OutputArg> &Outs, 1459 LLVMContext &Context) const { 1460 SmallVector<CCValAssign, 16> RVLocs; 1461 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1462 RVLocs, Context); 1463 return CCInfo.CheckReturn(Outs, RetCC_X86); 1464} 1465 1466SDValue 1467X86TargetLowering::LowerReturn(SDValue Chain, 1468 CallingConv::ID CallConv, bool isVarArg, 1469 const SmallVectorImpl<ISD::OutputArg> &Outs, 1470 const SmallVectorImpl<SDValue> &OutVals, 1471 DebugLoc dl, SelectionDAG &DAG) const { 1472 MachineFunction &MF = DAG.getMachineFunction(); 1473 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1474 1475 SmallVector<CCValAssign, 16> RVLocs; 1476 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1477 RVLocs, *DAG.getContext()); 1478 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1479 1480 // Add the regs to the liveout set for the function. 1481 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1482 for (unsigned i = 0; i != RVLocs.size(); ++i) 1483 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1484 MRI.addLiveOut(RVLocs[i].getLocReg()); 1485 1486 SDValue Flag; 1487 1488 SmallVector<SDValue, 6> RetOps; 1489 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1490 // Operand #1 = Bytes To Pop 1491 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1492 MVT::i16)); 1493 1494 // Copy the result values into the output registers. 1495 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1496 CCValAssign &VA = RVLocs[i]; 1497 assert(VA.isRegLoc() && "Can only return in registers!"); 1498 SDValue ValToCopy = OutVals[i]; 1499 EVT ValVT = ValToCopy.getValueType(); 1500 1501 // If this is x86-64, and we disabled SSE, we can't return FP values, 1502 // or SSE or MMX vectors. 1503 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1504 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1505 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1506 report_fatal_error("SSE register return with SSE disabled"); 1507 } 1508 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1509 // llvm-gcc has never done it right and no one has noticed, so this 1510 // should be OK for now. 1511 if (ValVT == MVT::f64 && 1512 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1513 report_fatal_error("SSE2 register return with SSE2 disabled"); 1514 1515 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1516 // the RET instruction and handled by the FP Stackifier. 1517 if (VA.getLocReg() == X86::ST0 || 1518 VA.getLocReg() == X86::ST1) { 1519 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1520 // change the value to the FP stack register class. 1521 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1522 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1523 RetOps.push_back(ValToCopy); 1524 // Don't emit a copytoreg. 1525 continue; 1526 } 1527 1528 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1529 // which is returned in RAX / RDX. 1530 if (Subtarget->is64Bit()) { 1531 if (ValVT == MVT::x86mmx) { 1532 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1533 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1534 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1535 ValToCopy); 1536 // If we don't have SSE2 available, convert to v4f32 so the generated 1537 // register is legal. 1538 if (!Subtarget->hasXMMInt()) 1539 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1540 } 1541 } 1542 } 1543 1544 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1545 Flag = Chain.getValue(1); 1546 } 1547 1548 // The x86-64 ABI for returning structs by value requires that we copy 1549 // the sret argument into %rax for the return. We saved the argument into 1550 // a virtual register in the entry block, so now we copy the value out 1551 // and into %rax. 1552 if (Subtarget->is64Bit() && 1553 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1554 MachineFunction &MF = DAG.getMachineFunction(); 1555 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1556 unsigned Reg = FuncInfo->getSRetReturnReg(); 1557 assert(Reg && 1558 "SRetReturnReg should have been set in LowerFormalArguments()."); 1559 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1560 1561 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1562 Flag = Chain.getValue(1); 1563 1564 // RAX now acts like a return value. 1565 MRI.addLiveOut(X86::RAX); 1566 } 1567 1568 RetOps[0] = Chain; // Update chain. 1569 1570 // Add the flag if we have it. 1571 if (Flag.getNode()) 1572 RetOps.push_back(Flag); 1573 1574 return DAG.getNode(X86ISD::RET_FLAG, dl, 1575 MVT::Other, &RetOps[0], RetOps.size()); 1576} 1577 1578bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1579 if (N->getNumValues() != 1) 1580 return false; 1581 if (!N->hasNUsesOfValue(1, 0)) 1582 return false; 1583 1584 SDNode *Copy = *N->use_begin(); 1585 if (Copy->getOpcode() != ISD::CopyToReg && 1586 Copy->getOpcode() != ISD::FP_EXTEND) 1587 return false; 1588 1589 bool HasRet = false; 1590 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1591 UI != UE; ++UI) { 1592 if (UI->getOpcode() != X86ISD::RET_FLAG) 1593 return false; 1594 HasRet = true; 1595 } 1596 1597 return HasRet; 1598} 1599 1600EVT 1601X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1602 ISD::NodeType ExtendKind) const { 1603 MVT ReturnMVT; 1604 // TODO: Is this also valid on 32-bit? 1605 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1606 ReturnMVT = MVT::i8; 1607 else 1608 ReturnMVT = MVT::i32; 1609 1610 EVT MinVT = getRegisterType(Context, ReturnMVT); 1611 return VT.bitsLT(MinVT) ? MinVT : VT; 1612} 1613 1614/// LowerCallResult - Lower the result values of a call into the 1615/// appropriate copies out of appropriate physical registers. 1616/// 1617SDValue 1618X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1619 CallingConv::ID CallConv, bool isVarArg, 1620 const SmallVectorImpl<ISD::InputArg> &Ins, 1621 DebugLoc dl, SelectionDAG &DAG, 1622 SmallVectorImpl<SDValue> &InVals) const { 1623 1624 // Assign locations to each value returned by this call. 1625 SmallVector<CCValAssign, 16> RVLocs; 1626 bool Is64Bit = Subtarget->is64Bit(); 1627 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1628 getTargetMachine(), RVLocs, *DAG.getContext()); 1629 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1630 1631 // Copy all of the result registers out of their specified physreg. 1632 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1633 CCValAssign &VA = RVLocs[i]; 1634 EVT CopyVT = VA.getValVT(); 1635 1636 // If this is x86-64, and we disabled SSE, we can't return FP values 1637 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1638 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1639 report_fatal_error("SSE register return with SSE disabled"); 1640 } 1641 1642 SDValue Val; 1643 1644 // If this is a call to a function that returns an fp value on the floating 1645 // point stack, we must guarantee the the value is popped from the stack, so 1646 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1647 // if the return value is not used. We use the FpPOP_RETVAL instruction 1648 // instead. 1649 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1650 // If we prefer to use the value in xmm registers, copy it out as f80 and 1651 // use a truncate to move it from fp stack reg to xmm reg. 1652 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1653 SDValue Ops[] = { Chain, InFlag }; 1654 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1655 MVT::Other, MVT::Glue, Ops, 2), 1); 1656 Val = Chain.getValue(0); 1657 1658 // Round the f80 to the right size, which also moves it to the appropriate 1659 // xmm register. 1660 if (CopyVT != VA.getValVT()) 1661 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1662 // This truncation won't change the value. 1663 DAG.getIntPtrConstant(1)); 1664 } else { 1665 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1666 CopyVT, InFlag).getValue(1); 1667 Val = Chain.getValue(0); 1668 } 1669 InFlag = Chain.getValue(2); 1670 InVals.push_back(Val); 1671 } 1672 1673 return Chain; 1674} 1675 1676 1677//===----------------------------------------------------------------------===// 1678// C & StdCall & Fast Calling Convention implementation 1679//===----------------------------------------------------------------------===// 1680// StdCall calling convention seems to be standard for many Windows' API 1681// routines and around. It differs from C calling convention just a little: 1682// callee should clean up the stack, not caller. Symbols should be also 1683// decorated in some fancy way :) It doesn't support any vector arguments. 1684// For info on fast calling convention see Fast Calling Convention (tail call) 1685// implementation LowerX86_32FastCCCallTo. 1686 1687/// CallIsStructReturn - Determines whether a call uses struct return 1688/// semantics. 1689static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1690 if (Outs.empty()) 1691 return false; 1692 1693 return Outs[0].Flags.isSRet(); 1694} 1695 1696/// ArgsAreStructReturn - Determines whether a function uses struct 1697/// return semantics. 1698static bool 1699ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1700 if (Ins.empty()) 1701 return false; 1702 1703 return Ins[0].Flags.isSRet(); 1704} 1705 1706/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1707/// by "Src" to address "Dst" with size and alignment information specified by 1708/// the specific parameter attribute. The copy will be passed as a byval 1709/// function parameter. 1710static SDValue 1711CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1712 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1713 DebugLoc dl) { 1714 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1715 1716 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1717 /*isVolatile*/false, /*AlwaysInline=*/true, 1718 MachinePointerInfo(), MachinePointerInfo()); 1719} 1720 1721/// IsTailCallConvention - Return true if the calling convention is one that 1722/// supports tail call optimization. 1723static bool IsTailCallConvention(CallingConv::ID CC) { 1724 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1725} 1726 1727bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1728 if (!CI->isTailCall()) 1729 return false; 1730 1731 CallSite CS(CI); 1732 CallingConv::ID CalleeCC = CS.getCallingConv(); 1733 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1734 return false; 1735 1736 return true; 1737} 1738 1739/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1740/// a tailcall target by changing its ABI. 1741static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1742 bool GuaranteedTailCallOpt) { 1743 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1744} 1745 1746SDValue 1747X86TargetLowering::LowerMemArgument(SDValue Chain, 1748 CallingConv::ID CallConv, 1749 const SmallVectorImpl<ISD::InputArg> &Ins, 1750 DebugLoc dl, SelectionDAG &DAG, 1751 const CCValAssign &VA, 1752 MachineFrameInfo *MFI, 1753 unsigned i) const { 1754 // Create the nodes corresponding to a load from this parameter slot. 1755 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1756 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1757 getTargetMachine().Options.GuaranteedTailCallOpt); 1758 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1759 EVT ValVT; 1760 1761 // If value is passed by pointer we have address passed instead of the value 1762 // itself. 1763 if (VA.getLocInfo() == CCValAssign::Indirect) 1764 ValVT = VA.getLocVT(); 1765 else 1766 ValVT = VA.getValVT(); 1767 1768 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1769 // changed with more analysis. 1770 // In case of tail call optimization mark all arguments mutable. Since they 1771 // could be overwritten by lowering of arguments in case of a tail call. 1772 if (Flags.isByVal()) { 1773 unsigned Bytes = Flags.getByValSize(); 1774 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1775 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1776 return DAG.getFrameIndex(FI, getPointerTy()); 1777 } else { 1778 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1779 VA.getLocMemOffset(), isImmutable); 1780 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1781 return DAG.getLoad(ValVT, dl, Chain, FIN, 1782 MachinePointerInfo::getFixedStack(FI), 1783 false, false, false, 0); 1784 } 1785} 1786 1787SDValue 1788X86TargetLowering::LowerFormalArguments(SDValue Chain, 1789 CallingConv::ID CallConv, 1790 bool isVarArg, 1791 const SmallVectorImpl<ISD::InputArg> &Ins, 1792 DebugLoc dl, 1793 SelectionDAG &DAG, 1794 SmallVectorImpl<SDValue> &InVals) 1795 const { 1796 MachineFunction &MF = DAG.getMachineFunction(); 1797 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1798 1799 const Function* Fn = MF.getFunction(); 1800 if (Fn->hasExternalLinkage() && 1801 Subtarget->isTargetCygMing() && 1802 Fn->getName() == "main") 1803 FuncInfo->setForceFramePointer(true); 1804 1805 MachineFrameInfo *MFI = MF.getFrameInfo(); 1806 bool Is64Bit = Subtarget->is64Bit(); 1807 bool IsWin64 = Subtarget->isTargetWin64(); 1808 1809 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1810 "Var args not supported with calling convention fastcc or ghc"); 1811 1812 // Assign locations to all of the incoming arguments. 1813 SmallVector<CCValAssign, 16> ArgLocs; 1814 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1815 ArgLocs, *DAG.getContext()); 1816 1817 // Allocate shadow area for Win64 1818 if (IsWin64) { 1819 CCInfo.AllocateStack(32, 8); 1820 } 1821 1822 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1823 1824 unsigned LastVal = ~0U; 1825 SDValue ArgValue; 1826 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1827 CCValAssign &VA = ArgLocs[i]; 1828 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1829 // places. 1830 assert(VA.getValNo() != LastVal && 1831 "Don't support value assigned to multiple locs yet"); 1832 (void)LastVal; 1833 LastVal = VA.getValNo(); 1834 1835 if (VA.isRegLoc()) { 1836 EVT RegVT = VA.getLocVT(); 1837 TargetRegisterClass *RC = NULL; 1838 if (RegVT == MVT::i32) 1839 RC = X86::GR32RegisterClass; 1840 else if (Is64Bit && RegVT == MVT::i64) 1841 RC = X86::GR64RegisterClass; 1842 else if (RegVT == MVT::f32) 1843 RC = X86::FR32RegisterClass; 1844 else if (RegVT == MVT::f64) 1845 RC = X86::FR64RegisterClass; 1846 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1847 RC = X86::VR256RegisterClass; 1848 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1849 RC = X86::VR128RegisterClass; 1850 else if (RegVT == MVT::x86mmx) 1851 RC = X86::VR64RegisterClass; 1852 else 1853 llvm_unreachable("Unknown argument type!"); 1854 1855 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1856 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1857 1858 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1859 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1860 // right size. 1861 if (VA.getLocInfo() == CCValAssign::SExt) 1862 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1863 DAG.getValueType(VA.getValVT())); 1864 else if (VA.getLocInfo() == CCValAssign::ZExt) 1865 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1866 DAG.getValueType(VA.getValVT())); 1867 else if (VA.getLocInfo() == CCValAssign::BCvt) 1868 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1869 1870 if (VA.isExtInLoc()) { 1871 // Handle MMX values passed in XMM regs. 1872 if (RegVT.isVector()) { 1873 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1874 ArgValue); 1875 } else 1876 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1877 } 1878 } else { 1879 assert(VA.isMemLoc()); 1880 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1881 } 1882 1883 // If value is passed via pointer - do a load. 1884 if (VA.getLocInfo() == CCValAssign::Indirect) 1885 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1886 MachinePointerInfo(), false, false, false, 0); 1887 1888 InVals.push_back(ArgValue); 1889 } 1890 1891 // The x86-64 ABI for returning structs by value requires that we copy 1892 // the sret argument into %rax for the return. Save the argument into 1893 // a virtual register so that we can access it from the return points. 1894 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1895 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1896 unsigned Reg = FuncInfo->getSRetReturnReg(); 1897 if (!Reg) { 1898 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1899 FuncInfo->setSRetReturnReg(Reg); 1900 } 1901 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1902 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1903 } 1904 1905 unsigned StackSize = CCInfo.getNextStackOffset(); 1906 // Align stack specially for tail calls. 1907 if (FuncIsMadeTailCallSafe(CallConv, 1908 MF.getTarget().Options.GuaranteedTailCallOpt)) 1909 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1910 1911 // If the function takes variable number of arguments, make a frame index for 1912 // the start of the first vararg value... for expansion of llvm.va_start. 1913 if (isVarArg) { 1914 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1915 CallConv != CallingConv::X86_ThisCall)) { 1916 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1917 } 1918 if (Is64Bit) { 1919 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1920 1921 // FIXME: We should really autogenerate these arrays 1922 static const unsigned GPR64ArgRegsWin64[] = { 1923 X86::RCX, X86::RDX, X86::R8, X86::R9 1924 }; 1925 static const unsigned GPR64ArgRegs64Bit[] = { 1926 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1927 }; 1928 static const unsigned XMMArgRegs64Bit[] = { 1929 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1930 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1931 }; 1932 const unsigned *GPR64ArgRegs; 1933 unsigned NumXMMRegs = 0; 1934 1935 if (IsWin64) { 1936 // The XMM registers which might contain var arg parameters are shadowed 1937 // in their paired GPR. So we only need to save the GPR to their home 1938 // slots. 1939 TotalNumIntRegs = 4; 1940 GPR64ArgRegs = GPR64ArgRegsWin64; 1941 } else { 1942 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1943 GPR64ArgRegs = GPR64ArgRegs64Bit; 1944 1945 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1946 TotalNumXMMRegs); 1947 } 1948 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1949 TotalNumIntRegs); 1950 1951 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1952 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1953 "SSE register cannot be used when SSE is disabled!"); 1954 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1955 NoImplicitFloatOps) && 1956 "SSE register cannot be used when SSE is disabled!"); 1957 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1958 !Subtarget->hasXMM()) 1959 // Kernel mode asks for SSE to be disabled, so don't push them 1960 // on the stack. 1961 TotalNumXMMRegs = 0; 1962 1963 if (IsWin64) { 1964 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1965 // Get to the caller-allocated home save location. Add 8 to account 1966 // for the return address. 1967 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1968 FuncInfo->setRegSaveFrameIndex( 1969 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1970 // Fixup to set vararg frame on shadow area (4 x i64). 1971 if (NumIntRegs < 4) 1972 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1973 } else { 1974 // For X86-64, if there are vararg parameters that are passed via 1975 // registers, then we must store them to their spots on the stack so 1976 // they may be loaded by deferencing the result of va_next. 1977 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1978 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1979 FuncInfo->setRegSaveFrameIndex( 1980 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1981 false)); 1982 } 1983 1984 // Store the integer parameter registers. 1985 SmallVector<SDValue, 8> MemOps; 1986 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1987 getPointerTy()); 1988 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1989 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1990 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1991 DAG.getIntPtrConstant(Offset)); 1992 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1993 X86::GR64RegisterClass); 1994 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1995 SDValue Store = 1996 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1997 MachinePointerInfo::getFixedStack( 1998 FuncInfo->getRegSaveFrameIndex(), Offset), 1999 false, false, 0); 2000 MemOps.push_back(Store); 2001 Offset += 8; 2002 } 2003 2004 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2005 // Now store the XMM (fp + vector) parameter registers. 2006 SmallVector<SDValue, 11> SaveXMMOps; 2007 SaveXMMOps.push_back(Chain); 2008 2009 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2010 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2011 SaveXMMOps.push_back(ALVal); 2012 2013 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2014 FuncInfo->getRegSaveFrameIndex())); 2015 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2016 FuncInfo->getVarArgsFPOffset())); 2017 2018 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2019 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2020 X86::VR128RegisterClass); 2021 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2022 SaveXMMOps.push_back(Val); 2023 } 2024 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2025 MVT::Other, 2026 &SaveXMMOps[0], SaveXMMOps.size())); 2027 } 2028 2029 if (!MemOps.empty()) 2030 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2031 &MemOps[0], MemOps.size()); 2032 } 2033 } 2034 2035 // Some CCs need callee pop. 2036 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2037 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2038 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2039 } else { 2040 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2041 // If this is an sret function, the return should pop the hidden pointer. 2042 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 2043 FuncInfo->setBytesToPopOnReturn(4); 2044 } 2045 2046 if (!Is64Bit) { 2047 // RegSaveFrameIndex is X86-64 only. 2048 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2049 if (CallConv == CallingConv::X86_FastCall || 2050 CallConv == CallingConv::X86_ThisCall) 2051 // fastcc functions can't have varargs. 2052 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2053 } 2054 2055 FuncInfo->setArgumentStackSize(StackSize); 2056 2057 return Chain; 2058} 2059 2060SDValue 2061X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2062 SDValue StackPtr, SDValue Arg, 2063 DebugLoc dl, SelectionDAG &DAG, 2064 const CCValAssign &VA, 2065 ISD::ArgFlagsTy Flags) const { 2066 unsigned LocMemOffset = VA.getLocMemOffset(); 2067 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2068 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2069 if (Flags.isByVal()) 2070 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2071 2072 return DAG.getStore(Chain, dl, Arg, PtrOff, 2073 MachinePointerInfo::getStack(LocMemOffset), 2074 false, false, 0); 2075} 2076 2077/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2078/// optimization is performed and it is required. 2079SDValue 2080X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2081 SDValue &OutRetAddr, SDValue Chain, 2082 bool IsTailCall, bool Is64Bit, 2083 int FPDiff, DebugLoc dl) const { 2084 // Adjust the Return address stack slot. 2085 EVT VT = getPointerTy(); 2086 OutRetAddr = getReturnAddressFrameIndex(DAG); 2087 2088 // Load the "old" Return address. 2089 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2090 false, false, false, 0); 2091 return SDValue(OutRetAddr.getNode(), 1); 2092} 2093 2094/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2095/// optimization is performed and it is required (FPDiff!=0). 2096static SDValue 2097EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2098 SDValue Chain, SDValue RetAddrFrIdx, 2099 bool Is64Bit, int FPDiff, DebugLoc dl) { 2100 // Store the return address to the appropriate stack slot. 2101 if (!FPDiff) return Chain; 2102 // Calculate the new stack slot for the return address. 2103 int SlotSize = Is64Bit ? 8 : 4; 2104 int NewReturnAddrFI = 2105 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2106 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2107 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2108 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2109 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2110 false, false, 0); 2111 return Chain; 2112} 2113 2114SDValue 2115X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2116 CallingConv::ID CallConv, bool isVarArg, 2117 bool &isTailCall, 2118 const SmallVectorImpl<ISD::OutputArg> &Outs, 2119 const SmallVectorImpl<SDValue> &OutVals, 2120 const SmallVectorImpl<ISD::InputArg> &Ins, 2121 DebugLoc dl, SelectionDAG &DAG, 2122 SmallVectorImpl<SDValue> &InVals) const { 2123 MachineFunction &MF = DAG.getMachineFunction(); 2124 bool Is64Bit = Subtarget->is64Bit(); 2125 bool IsWin64 = Subtarget->isTargetWin64(); 2126 bool IsStructRet = CallIsStructReturn(Outs); 2127 bool IsSibcall = false; 2128 2129 if (isTailCall) { 2130 // Check if it's really possible to do a tail call. 2131 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2132 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2133 Outs, OutVals, Ins, DAG); 2134 2135 // Sibcalls are automatically detected tailcalls which do not require 2136 // ABI changes. 2137 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2138 IsSibcall = true; 2139 2140 if (isTailCall) 2141 ++NumTailCalls; 2142 } 2143 2144 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2145 "Var args not supported with calling convention fastcc or ghc"); 2146 2147 // Analyze operands of the call, assigning locations to each operand. 2148 SmallVector<CCValAssign, 16> ArgLocs; 2149 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2150 ArgLocs, *DAG.getContext()); 2151 2152 // Allocate shadow area for Win64 2153 if (IsWin64) { 2154 CCInfo.AllocateStack(32, 8); 2155 } 2156 2157 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2158 2159 // Get a count of how many bytes are to be pushed on the stack. 2160 unsigned NumBytes = CCInfo.getNextStackOffset(); 2161 if (IsSibcall) 2162 // This is a sibcall. The memory operands are available in caller's 2163 // own caller's stack. 2164 NumBytes = 0; 2165 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2166 IsTailCallConvention(CallConv)) 2167 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2168 2169 int FPDiff = 0; 2170 if (isTailCall && !IsSibcall) { 2171 // Lower arguments at fp - stackoffset + fpdiff. 2172 unsigned NumBytesCallerPushed = 2173 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2174 FPDiff = NumBytesCallerPushed - NumBytes; 2175 2176 // Set the delta of movement of the returnaddr stackslot. 2177 // But only set if delta is greater than previous delta. 2178 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2179 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2180 } 2181 2182 if (!IsSibcall) 2183 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2184 2185 SDValue RetAddrFrIdx; 2186 // Load return address for tail calls. 2187 if (isTailCall && FPDiff) 2188 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2189 Is64Bit, FPDiff, dl); 2190 2191 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2192 SmallVector<SDValue, 8> MemOpChains; 2193 SDValue StackPtr; 2194 2195 // Walk the register/memloc assignments, inserting copies/loads. In the case 2196 // of tail call optimization arguments are handle later. 2197 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2198 CCValAssign &VA = ArgLocs[i]; 2199 EVT RegVT = VA.getLocVT(); 2200 SDValue Arg = OutVals[i]; 2201 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2202 bool isByVal = Flags.isByVal(); 2203 2204 // Promote the value if needed. 2205 switch (VA.getLocInfo()) { 2206 default: llvm_unreachable("Unknown loc info!"); 2207 case CCValAssign::Full: break; 2208 case CCValAssign::SExt: 2209 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2210 break; 2211 case CCValAssign::ZExt: 2212 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2213 break; 2214 case CCValAssign::AExt: 2215 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2216 // Special case: passing MMX values in XMM registers. 2217 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2218 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2219 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2220 } else 2221 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2222 break; 2223 case CCValAssign::BCvt: 2224 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2225 break; 2226 case CCValAssign::Indirect: { 2227 // Store the argument. 2228 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2229 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2230 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2231 MachinePointerInfo::getFixedStack(FI), 2232 false, false, 0); 2233 Arg = SpillSlot; 2234 break; 2235 } 2236 } 2237 2238 if (VA.isRegLoc()) { 2239 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2240 if (isVarArg && IsWin64) { 2241 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2242 // shadow reg if callee is a varargs function. 2243 unsigned ShadowReg = 0; 2244 switch (VA.getLocReg()) { 2245 case X86::XMM0: ShadowReg = X86::RCX; break; 2246 case X86::XMM1: ShadowReg = X86::RDX; break; 2247 case X86::XMM2: ShadowReg = X86::R8; break; 2248 case X86::XMM3: ShadowReg = X86::R9; break; 2249 } 2250 if (ShadowReg) 2251 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2252 } 2253 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2254 assert(VA.isMemLoc()); 2255 if (StackPtr.getNode() == 0) 2256 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2257 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2258 dl, DAG, VA, Flags)); 2259 } 2260 } 2261 2262 if (!MemOpChains.empty()) 2263 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2264 &MemOpChains[0], MemOpChains.size()); 2265 2266 // Build a sequence of copy-to-reg nodes chained together with token chain 2267 // and flag operands which copy the outgoing args into registers. 2268 SDValue InFlag; 2269 // Tail call byval lowering might overwrite argument registers so in case of 2270 // tail call optimization the copies to registers are lowered later. 2271 if (!isTailCall) 2272 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2273 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2274 RegsToPass[i].second, InFlag); 2275 InFlag = Chain.getValue(1); 2276 } 2277 2278 if (Subtarget->isPICStyleGOT()) { 2279 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2280 // GOT pointer. 2281 if (!isTailCall) { 2282 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2283 DAG.getNode(X86ISD::GlobalBaseReg, 2284 DebugLoc(), getPointerTy()), 2285 InFlag); 2286 InFlag = Chain.getValue(1); 2287 } else { 2288 // If we are tail calling and generating PIC/GOT style code load the 2289 // address of the callee into ECX. The value in ecx is used as target of 2290 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2291 // for tail calls on PIC/GOT architectures. Normally we would just put the 2292 // address of GOT into ebx and then call target@PLT. But for tail calls 2293 // ebx would be restored (since ebx is callee saved) before jumping to the 2294 // target@PLT. 2295 2296 // Note: The actual moving to ECX is done further down. 2297 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2298 if (G && !G->getGlobal()->hasHiddenVisibility() && 2299 !G->getGlobal()->hasProtectedVisibility()) 2300 Callee = LowerGlobalAddress(Callee, DAG); 2301 else if (isa<ExternalSymbolSDNode>(Callee)) 2302 Callee = LowerExternalSymbol(Callee, DAG); 2303 } 2304 } 2305 2306 if (Is64Bit && isVarArg && !IsWin64) { 2307 // From AMD64 ABI document: 2308 // For calls that may call functions that use varargs or stdargs 2309 // (prototype-less calls or calls to functions containing ellipsis (...) in 2310 // the declaration) %al is used as hidden argument to specify the number 2311 // of SSE registers used. The contents of %al do not need to match exactly 2312 // the number of registers, but must be an ubound on the number of SSE 2313 // registers used and is in the range 0 - 8 inclusive. 2314 2315 // Count the number of XMM registers allocated. 2316 static const unsigned XMMArgRegs[] = { 2317 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2318 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2319 }; 2320 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2321 assert((Subtarget->hasXMM() || !NumXMMRegs) 2322 && "SSE registers cannot be used when SSE is disabled"); 2323 2324 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2325 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2326 InFlag = Chain.getValue(1); 2327 } 2328 2329 2330 // For tail calls lower the arguments to the 'real' stack slot. 2331 if (isTailCall) { 2332 // Force all the incoming stack arguments to be loaded from the stack 2333 // before any new outgoing arguments are stored to the stack, because the 2334 // outgoing stack slots may alias the incoming argument stack slots, and 2335 // the alias isn't otherwise explicit. This is slightly more conservative 2336 // than necessary, because it means that each store effectively depends 2337 // on every argument instead of just those arguments it would clobber. 2338 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2339 2340 SmallVector<SDValue, 8> MemOpChains2; 2341 SDValue FIN; 2342 int FI = 0; 2343 // Do not flag preceding copytoreg stuff together with the following stuff. 2344 InFlag = SDValue(); 2345 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2346 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2347 CCValAssign &VA = ArgLocs[i]; 2348 if (VA.isRegLoc()) 2349 continue; 2350 assert(VA.isMemLoc()); 2351 SDValue Arg = OutVals[i]; 2352 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2353 // Create frame index. 2354 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2355 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2356 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2357 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2358 2359 if (Flags.isByVal()) { 2360 // Copy relative to framepointer. 2361 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2362 if (StackPtr.getNode() == 0) 2363 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2364 getPointerTy()); 2365 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2366 2367 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2368 ArgChain, 2369 Flags, DAG, dl)); 2370 } else { 2371 // Store relative to framepointer. 2372 MemOpChains2.push_back( 2373 DAG.getStore(ArgChain, dl, Arg, FIN, 2374 MachinePointerInfo::getFixedStack(FI), 2375 false, false, 0)); 2376 } 2377 } 2378 } 2379 2380 if (!MemOpChains2.empty()) 2381 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2382 &MemOpChains2[0], MemOpChains2.size()); 2383 2384 // Copy arguments to their registers. 2385 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2386 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2387 RegsToPass[i].second, InFlag); 2388 InFlag = Chain.getValue(1); 2389 } 2390 InFlag =SDValue(); 2391 2392 // Store the return address to the appropriate stack slot. 2393 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2394 FPDiff, dl); 2395 } 2396 2397 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2398 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2399 // In the 64-bit large code model, we have to make all calls 2400 // through a register, since the call instruction's 32-bit 2401 // pc-relative offset may not be large enough to hold the whole 2402 // address. 2403 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2404 // If the callee is a GlobalAddress node (quite common, every direct call 2405 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2406 // it. 2407 2408 // We should use extra load for direct calls to dllimported functions in 2409 // non-JIT mode. 2410 const GlobalValue *GV = G->getGlobal(); 2411 if (!GV->hasDLLImportLinkage()) { 2412 unsigned char OpFlags = 0; 2413 bool ExtraLoad = false; 2414 unsigned WrapperKind = ISD::DELETED_NODE; 2415 2416 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2417 // external symbols most go through the PLT in PIC mode. If the symbol 2418 // has hidden or protected visibility, or if it is static or local, then 2419 // we don't need to use the PLT - we can directly call it. 2420 if (Subtarget->isTargetELF() && 2421 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2422 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2423 OpFlags = X86II::MO_PLT; 2424 } else if (Subtarget->isPICStyleStubAny() && 2425 (GV->isDeclaration() || GV->isWeakForLinker()) && 2426 (!Subtarget->getTargetTriple().isMacOSX() || 2427 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2428 // PC-relative references to external symbols should go through $stub, 2429 // unless we're building with the leopard linker or later, which 2430 // automatically synthesizes these stubs. 2431 OpFlags = X86II::MO_DARWIN_STUB; 2432 } else if (Subtarget->isPICStyleRIPRel() && 2433 isa<Function>(GV) && 2434 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2435 // If the function is marked as non-lazy, generate an indirect call 2436 // which loads from the GOT directly. This avoids runtime overhead 2437 // at the cost of eager binding (and one extra byte of encoding). 2438 OpFlags = X86II::MO_GOTPCREL; 2439 WrapperKind = X86ISD::WrapperRIP; 2440 ExtraLoad = true; 2441 } 2442 2443 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2444 G->getOffset(), OpFlags); 2445 2446 // Add a wrapper if needed. 2447 if (WrapperKind != ISD::DELETED_NODE) 2448 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2449 // Add extra indirection if needed. 2450 if (ExtraLoad) 2451 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2452 MachinePointerInfo::getGOT(), 2453 false, false, false, 0); 2454 } 2455 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2456 unsigned char OpFlags = 0; 2457 2458 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2459 // external symbols should go through the PLT. 2460 if (Subtarget->isTargetELF() && 2461 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2462 OpFlags = X86II::MO_PLT; 2463 } else if (Subtarget->isPICStyleStubAny() && 2464 (!Subtarget->getTargetTriple().isMacOSX() || 2465 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2466 // PC-relative references to external symbols should go through $stub, 2467 // unless we're building with the leopard linker or later, which 2468 // automatically synthesizes these stubs. 2469 OpFlags = X86II::MO_DARWIN_STUB; 2470 } 2471 2472 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2473 OpFlags); 2474 } 2475 2476 // Returns a chain & a flag for retval copy to use. 2477 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2478 SmallVector<SDValue, 8> Ops; 2479 2480 if (!IsSibcall && isTailCall) { 2481 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2482 DAG.getIntPtrConstant(0, true), InFlag); 2483 InFlag = Chain.getValue(1); 2484 } 2485 2486 Ops.push_back(Chain); 2487 Ops.push_back(Callee); 2488 2489 if (isTailCall) 2490 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2491 2492 // Add argument registers to the end of the list so that they are known live 2493 // into the call. 2494 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2495 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2496 RegsToPass[i].second.getValueType())); 2497 2498 // Add an implicit use GOT pointer in EBX. 2499 if (!isTailCall && Subtarget->isPICStyleGOT()) 2500 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2501 2502 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2503 if (Is64Bit && isVarArg && !IsWin64) 2504 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2505 2506 if (InFlag.getNode()) 2507 Ops.push_back(InFlag); 2508 2509 if (isTailCall) { 2510 // We used to do: 2511 //// If this is the first return lowered for this function, add the regs 2512 //// to the liveout set for the function. 2513 // This isn't right, although it's probably harmless on x86; liveouts 2514 // should be computed from returns not tail calls. Consider a void 2515 // function making a tail call to a function returning int. 2516 return DAG.getNode(X86ISD::TC_RETURN, dl, 2517 NodeTys, &Ops[0], Ops.size()); 2518 } 2519 2520 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2521 InFlag = Chain.getValue(1); 2522 2523 // Create the CALLSEQ_END node. 2524 unsigned NumBytesForCalleeToPush; 2525 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2526 getTargetMachine().Options.GuaranteedTailCallOpt)) 2527 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2528 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2529 // If this is a call to a struct-return function, the callee 2530 // pops the hidden struct pointer, so we have to push it back. 2531 // This is common for Darwin/X86, Linux & Mingw32 targets. 2532 NumBytesForCalleeToPush = 4; 2533 else 2534 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2535 2536 // Returns a flag for retval copy to use. 2537 if (!IsSibcall) { 2538 Chain = DAG.getCALLSEQ_END(Chain, 2539 DAG.getIntPtrConstant(NumBytes, true), 2540 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2541 true), 2542 InFlag); 2543 InFlag = Chain.getValue(1); 2544 } 2545 2546 // Handle result values, copying them out of physregs into vregs that we 2547 // return. 2548 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2549 Ins, dl, DAG, InVals); 2550} 2551 2552 2553//===----------------------------------------------------------------------===// 2554// Fast Calling Convention (tail call) implementation 2555//===----------------------------------------------------------------------===// 2556 2557// Like std call, callee cleans arguments, convention except that ECX is 2558// reserved for storing the tail called function address. Only 2 registers are 2559// free for argument passing (inreg). Tail call optimization is performed 2560// provided: 2561// * tailcallopt is enabled 2562// * caller/callee are fastcc 2563// On X86_64 architecture with GOT-style position independent code only local 2564// (within module) calls are supported at the moment. 2565// To keep the stack aligned according to platform abi the function 2566// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2567// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2568// If a tail called function callee has more arguments than the caller the 2569// caller needs to make sure that there is room to move the RETADDR to. This is 2570// achieved by reserving an area the size of the argument delta right after the 2571// original REtADDR, but before the saved framepointer or the spilled registers 2572// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2573// stack layout: 2574// arg1 2575// arg2 2576// RETADDR 2577// [ new RETADDR 2578// move area ] 2579// (possible EBP) 2580// ESI 2581// EDI 2582// local1 .. 2583 2584/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2585/// for a 16 byte align requirement. 2586unsigned 2587X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2588 SelectionDAG& DAG) const { 2589 MachineFunction &MF = DAG.getMachineFunction(); 2590 const TargetMachine &TM = MF.getTarget(); 2591 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2592 unsigned StackAlignment = TFI.getStackAlignment(); 2593 uint64_t AlignMask = StackAlignment - 1; 2594 int64_t Offset = StackSize; 2595 uint64_t SlotSize = TD->getPointerSize(); 2596 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2597 // Number smaller than 12 so just add the difference. 2598 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2599 } else { 2600 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2601 Offset = ((~AlignMask) & Offset) + StackAlignment + 2602 (StackAlignment-SlotSize); 2603 } 2604 return Offset; 2605} 2606 2607/// MatchingStackOffset - Return true if the given stack call argument is 2608/// already available in the same position (relatively) of the caller's 2609/// incoming argument stack. 2610static 2611bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2612 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2613 const X86InstrInfo *TII) { 2614 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2615 int FI = INT_MAX; 2616 if (Arg.getOpcode() == ISD::CopyFromReg) { 2617 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2618 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2619 return false; 2620 MachineInstr *Def = MRI->getVRegDef(VR); 2621 if (!Def) 2622 return false; 2623 if (!Flags.isByVal()) { 2624 if (!TII->isLoadFromStackSlot(Def, FI)) 2625 return false; 2626 } else { 2627 unsigned Opcode = Def->getOpcode(); 2628 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2629 Def->getOperand(1).isFI()) { 2630 FI = Def->getOperand(1).getIndex(); 2631 Bytes = Flags.getByValSize(); 2632 } else 2633 return false; 2634 } 2635 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2636 if (Flags.isByVal()) 2637 // ByVal argument is passed in as a pointer but it's now being 2638 // dereferenced. e.g. 2639 // define @foo(%struct.X* %A) { 2640 // tail call @bar(%struct.X* byval %A) 2641 // } 2642 return false; 2643 SDValue Ptr = Ld->getBasePtr(); 2644 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2645 if (!FINode) 2646 return false; 2647 FI = FINode->getIndex(); 2648 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2649 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2650 FI = FINode->getIndex(); 2651 Bytes = Flags.getByValSize(); 2652 } else 2653 return false; 2654 2655 assert(FI != INT_MAX); 2656 if (!MFI->isFixedObjectIndex(FI)) 2657 return false; 2658 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2659} 2660 2661/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2662/// for tail call optimization. Targets which want to do tail call 2663/// optimization should implement this function. 2664bool 2665X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2666 CallingConv::ID CalleeCC, 2667 bool isVarArg, 2668 bool isCalleeStructRet, 2669 bool isCallerStructRet, 2670 const SmallVectorImpl<ISD::OutputArg> &Outs, 2671 const SmallVectorImpl<SDValue> &OutVals, 2672 const SmallVectorImpl<ISD::InputArg> &Ins, 2673 SelectionDAG& DAG) const { 2674 if (!IsTailCallConvention(CalleeCC) && 2675 CalleeCC != CallingConv::C) 2676 return false; 2677 2678 // If -tailcallopt is specified, make fastcc functions tail-callable. 2679 const MachineFunction &MF = DAG.getMachineFunction(); 2680 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2681 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2682 bool CCMatch = CallerCC == CalleeCC; 2683 2684 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2685 if (IsTailCallConvention(CalleeCC) && CCMatch) 2686 return true; 2687 return false; 2688 } 2689 2690 // Look for obvious safe cases to perform tail call optimization that do not 2691 // require ABI changes. This is what gcc calls sibcall. 2692 2693 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2694 // emit a special epilogue. 2695 if (RegInfo->needsStackRealignment(MF)) 2696 return false; 2697 2698 // Also avoid sibcall optimization if either caller or callee uses struct 2699 // return semantics. 2700 if (isCalleeStructRet || isCallerStructRet) 2701 return false; 2702 2703 // An stdcall caller is expected to clean up its arguments; the callee 2704 // isn't going to do that. 2705 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2706 return false; 2707 2708 // Do not sibcall optimize vararg calls unless all arguments are passed via 2709 // registers. 2710 if (isVarArg && !Outs.empty()) { 2711 2712 // Optimizing for varargs on Win64 is unlikely to be safe without 2713 // additional testing. 2714 if (Subtarget->isTargetWin64()) 2715 return false; 2716 2717 SmallVector<CCValAssign, 16> ArgLocs; 2718 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2719 getTargetMachine(), ArgLocs, *DAG.getContext()); 2720 2721 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2723 if (!ArgLocs[i].isRegLoc()) 2724 return false; 2725 } 2726 2727 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2728 // stack. Therefore, if it's not used by the call it is not safe to optimize 2729 // this into a sibcall. 2730 bool Unused = false; 2731 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2732 if (!Ins[i].Used) { 2733 Unused = true; 2734 break; 2735 } 2736 } 2737 if (Unused) { 2738 SmallVector<CCValAssign, 16> RVLocs; 2739 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2740 getTargetMachine(), RVLocs, *DAG.getContext()); 2741 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2742 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2743 CCValAssign &VA = RVLocs[i]; 2744 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2745 return false; 2746 } 2747 } 2748 2749 // If the calling conventions do not match, then we'd better make sure the 2750 // results are returned in the same way as what the caller expects. 2751 if (!CCMatch) { 2752 SmallVector<CCValAssign, 16> RVLocs1; 2753 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2754 getTargetMachine(), RVLocs1, *DAG.getContext()); 2755 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2756 2757 SmallVector<CCValAssign, 16> RVLocs2; 2758 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2759 getTargetMachine(), RVLocs2, *DAG.getContext()); 2760 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2761 2762 if (RVLocs1.size() != RVLocs2.size()) 2763 return false; 2764 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2765 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2766 return false; 2767 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2768 return false; 2769 if (RVLocs1[i].isRegLoc()) { 2770 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2771 return false; 2772 } else { 2773 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2774 return false; 2775 } 2776 } 2777 } 2778 2779 // If the callee takes no arguments then go on to check the results of the 2780 // call. 2781 if (!Outs.empty()) { 2782 // Check if stack adjustment is needed. For now, do not do this if any 2783 // argument is passed on the stack. 2784 SmallVector<CCValAssign, 16> ArgLocs; 2785 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2786 getTargetMachine(), ArgLocs, *DAG.getContext()); 2787 2788 // Allocate shadow area for Win64 2789 if (Subtarget->isTargetWin64()) { 2790 CCInfo.AllocateStack(32, 8); 2791 } 2792 2793 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2794 if (CCInfo.getNextStackOffset()) { 2795 MachineFunction &MF = DAG.getMachineFunction(); 2796 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2797 return false; 2798 2799 // Check if the arguments are already laid out in the right way as 2800 // the caller's fixed stack objects. 2801 MachineFrameInfo *MFI = MF.getFrameInfo(); 2802 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2803 const X86InstrInfo *TII = 2804 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2805 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2806 CCValAssign &VA = ArgLocs[i]; 2807 SDValue Arg = OutVals[i]; 2808 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2809 if (VA.getLocInfo() == CCValAssign::Indirect) 2810 return false; 2811 if (!VA.isRegLoc()) { 2812 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2813 MFI, MRI, TII)) 2814 return false; 2815 } 2816 } 2817 } 2818 2819 // If the tailcall address may be in a register, then make sure it's 2820 // possible to register allocate for it. In 32-bit, the call address can 2821 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2822 // callee-saved registers are restored. These happen to be the same 2823 // registers used to pass 'inreg' arguments so watch out for those. 2824 if (!Subtarget->is64Bit() && 2825 !isa<GlobalAddressSDNode>(Callee) && 2826 !isa<ExternalSymbolSDNode>(Callee)) { 2827 unsigned NumInRegs = 0; 2828 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2829 CCValAssign &VA = ArgLocs[i]; 2830 if (!VA.isRegLoc()) 2831 continue; 2832 unsigned Reg = VA.getLocReg(); 2833 switch (Reg) { 2834 default: break; 2835 case X86::EAX: case X86::EDX: case X86::ECX: 2836 if (++NumInRegs == 3) 2837 return false; 2838 break; 2839 } 2840 } 2841 } 2842 } 2843 2844 return true; 2845} 2846 2847FastISel * 2848X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2849 return X86::createFastISel(funcInfo); 2850} 2851 2852 2853//===----------------------------------------------------------------------===// 2854// Other Lowering Hooks 2855//===----------------------------------------------------------------------===// 2856 2857static bool MayFoldLoad(SDValue Op) { 2858 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2859} 2860 2861static bool MayFoldIntoStore(SDValue Op) { 2862 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2863} 2864 2865static bool isTargetShuffle(unsigned Opcode) { 2866 switch(Opcode) { 2867 default: return false; 2868 case X86ISD::PSHUFD: 2869 case X86ISD::PSHUFHW: 2870 case X86ISD::PSHUFLW: 2871 case X86ISD::SHUFP: 2872 case X86ISD::PALIGN: 2873 case X86ISD::MOVLHPS: 2874 case X86ISD::MOVLHPD: 2875 case X86ISD::MOVHLPS: 2876 case X86ISD::MOVLPS: 2877 case X86ISD::MOVLPD: 2878 case X86ISD::MOVSHDUP: 2879 case X86ISD::MOVSLDUP: 2880 case X86ISD::MOVDDUP: 2881 case X86ISD::MOVSS: 2882 case X86ISD::MOVSD: 2883 case X86ISD::UNPCKL: 2884 case X86ISD::UNPCKH: 2885 case X86ISD::VPERMILP: 2886 case X86ISD::VPERM2X128: 2887 return true; 2888 } 2889 return false; 2890} 2891 2892static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2893 SDValue V1, SelectionDAG &DAG) { 2894 switch(Opc) { 2895 default: llvm_unreachable("Unknown x86 shuffle node"); 2896 case X86ISD::MOVSHDUP: 2897 case X86ISD::MOVSLDUP: 2898 case X86ISD::MOVDDUP: 2899 return DAG.getNode(Opc, dl, VT, V1); 2900 } 2901 2902 return SDValue(); 2903} 2904 2905static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2906 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2907 switch(Opc) { 2908 default: llvm_unreachable("Unknown x86 shuffle node"); 2909 case X86ISD::PSHUFD: 2910 case X86ISD::PSHUFHW: 2911 case X86ISD::PSHUFLW: 2912 case X86ISD::VPERMILP: 2913 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2914 } 2915 2916 return SDValue(); 2917} 2918 2919static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2920 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2921 switch(Opc) { 2922 default: llvm_unreachable("Unknown x86 shuffle node"); 2923 case X86ISD::PALIGN: 2924 case X86ISD::SHUFP: 2925 case X86ISD::VPERM2X128: 2926 return DAG.getNode(Opc, dl, VT, V1, V2, 2927 DAG.getConstant(TargetMask, MVT::i8)); 2928 } 2929 return SDValue(); 2930} 2931 2932static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2933 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2934 switch(Opc) { 2935 default: llvm_unreachable("Unknown x86 shuffle node"); 2936 case X86ISD::MOVLHPS: 2937 case X86ISD::MOVLHPD: 2938 case X86ISD::MOVHLPS: 2939 case X86ISD::MOVLPS: 2940 case X86ISD::MOVLPD: 2941 case X86ISD::MOVSS: 2942 case X86ISD::MOVSD: 2943 case X86ISD::UNPCKL: 2944 case X86ISD::UNPCKH: 2945 return DAG.getNode(Opc, dl, VT, V1, V2); 2946 } 2947 return SDValue(); 2948} 2949 2950SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2951 MachineFunction &MF = DAG.getMachineFunction(); 2952 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2953 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2954 2955 if (ReturnAddrIndex == 0) { 2956 // Set up a frame object for the return address. 2957 uint64_t SlotSize = TD->getPointerSize(); 2958 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2959 false); 2960 FuncInfo->setRAIndex(ReturnAddrIndex); 2961 } 2962 2963 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2964} 2965 2966 2967bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2968 bool hasSymbolicDisplacement) { 2969 // Offset should fit into 32 bit immediate field. 2970 if (!isInt<32>(Offset)) 2971 return false; 2972 2973 // If we don't have a symbolic displacement - we don't have any extra 2974 // restrictions. 2975 if (!hasSymbolicDisplacement) 2976 return true; 2977 2978 // FIXME: Some tweaks might be needed for medium code model. 2979 if (M != CodeModel::Small && M != CodeModel::Kernel) 2980 return false; 2981 2982 // For small code model we assume that latest object is 16MB before end of 31 2983 // bits boundary. We may also accept pretty large negative constants knowing 2984 // that all objects are in the positive half of address space. 2985 if (M == CodeModel::Small && Offset < 16*1024*1024) 2986 return true; 2987 2988 // For kernel code model we know that all object resist in the negative half 2989 // of 32bits address space. We may not accept negative offsets, since they may 2990 // be just off and we may accept pretty large positive ones. 2991 if (M == CodeModel::Kernel && Offset > 0) 2992 return true; 2993 2994 return false; 2995} 2996 2997/// isCalleePop - Determines whether the callee is required to pop its 2998/// own arguments. Callee pop is necessary to support tail calls. 2999bool X86::isCalleePop(CallingConv::ID CallingConv, 3000 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3001 if (IsVarArg) 3002 return false; 3003 3004 switch (CallingConv) { 3005 default: 3006 return false; 3007 case CallingConv::X86_StdCall: 3008 return !is64Bit; 3009 case CallingConv::X86_FastCall: 3010 return !is64Bit; 3011 case CallingConv::X86_ThisCall: 3012 return !is64Bit; 3013 case CallingConv::Fast: 3014 return TailCallOpt; 3015 case CallingConv::GHC: 3016 return TailCallOpt; 3017 } 3018} 3019 3020/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3021/// specific condition code, returning the condition code and the LHS/RHS of the 3022/// comparison to make. 3023static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3024 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3025 if (!isFP) { 3026 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3027 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3028 // X > -1 -> X == 0, jump !sign. 3029 RHS = DAG.getConstant(0, RHS.getValueType()); 3030 return X86::COND_NS; 3031 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3032 // X < 0 -> X == 0, jump on sign. 3033 return X86::COND_S; 3034 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3035 // X < 1 -> X <= 0 3036 RHS = DAG.getConstant(0, RHS.getValueType()); 3037 return X86::COND_LE; 3038 } 3039 } 3040 3041 switch (SetCCOpcode) { 3042 default: llvm_unreachable("Invalid integer condition!"); 3043 case ISD::SETEQ: return X86::COND_E; 3044 case ISD::SETGT: return X86::COND_G; 3045 case ISD::SETGE: return X86::COND_GE; 3046 case ISD::SETLT: return X86::COND_L; 3047 case ISD::SETLE: return X86::COND_LE; 3048 case ISD::SETNE: return X86::COND_NE; 3049 case ISD::SETULT: return X86::COND_B; 3050 case ISD::SETUGT: return X86::COND_A; 3051 case ISD::SETULE: return X86::COND_BE; 3052 case ISD::SETUGE: return X86::COND_AE; 3053 } 3054 } 3055 3056 // First determine if it is required or is profitable to flip the operands. 3057 3058 // If LHS is a foldable load, but RHS is not, flip the condition. 3059 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3060 !ISD::isNON_EXTLoad(RHS.getNode())) { 3061 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3062 std::swap(LHS, RHS); 3063 } 3064 3065 switch (SetCCOpcode) { 3066 default: break; 3067 case ISD::SETOLT: 3068 case ISD::SETOLE: 3069 case ISD::SETUGT: 3070 case ISD::SETUGE: 3071 std::swap(LHS, RHS); 3072 break; 3073 } 3074 3075 // On a floating point condition, the flags are set as follows: 3076 // ZF PF CF op 3077 // 0 | 0 | 0 | X > Y 3078 // 0 | 0 | 1 | X < Y 3079 // 1 | 0 | 0 | X == Y 3080 // 1 | 1 | 1 | unordered 3081 switch (SetCCOpcode) { 3082 default: llvm_unreachable("Condcode should be pre-legalized away"); 3083 case ISD::SETUEQ: 3084 case ISD::SETEQ: return X86::COND_E; 3085 case ISD::SETOLT: // flipped 3086 case ISD::SETOGT: 3087 case ISD::SETGT: return X86::COND_A; 3088 case ISD::SETOLE: // flipped 3089 case ISD::SETOGE: 3090 case ISD::SETGE: return X86::COND_AE; 3091 case ISD::SETUGT: // flipped 3092 case ISD::SETULT: 3093 case ISD::SETLT: return X86::COND_B; 3094 case ISD::SETUGE: // flipped 3095 case ISD::SETULE: 3096 case ISD::SETLE: return X86::COND_BE; 3097 case ISD::SETONE: 3098 case ISD::SETNE: return X86::COND_NE; 3099 case ISD::SETUO: return X86::COND_P; 3100 case ISD::SETO: return X86::COND_NP; 3101 case ISD::SETOEQ: 3102 case ISD::SETUNE: return X86::COND_INVALID; 3103 } 3104} 3105 3106/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3107/// code. Current x86 isa includes the following FP cmov instructions: 3108/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3109static bool hasFPCMov(unsigned X86CC) { 3110 switch (X86CC) { 3111 default: 3112 return false; 3113 case X86::COND_B: 3114 case X86::COND_BE: 3115 case X86::COND_E: 3116 case X86::COND_P: 3117 case X86::COND_A: 3118 case X86::COND_AE: 3119 case X86::COND_NE: 3120 case X86::COND_NP: 3121 return true; 3122 } 3123} 3124 3125/// isFPImmLegal - Returns true if the target can instruction select the 3126/// specified FP immediate natively. If false, the legalizer will 3127/// materialize the FP immediate as a load from a constant pool. 3128bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3129 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3130 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3131 return true; 3132 } 3133 return false; 3134} 3135 3136/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3137/// the specified range (L, H]. 3138static bool isUndefOrInRange(int Val, int Low, int Hi) { 3139 return (Val < 0) || (Val >= Low && Val < Hi); 3140} 3141 3142/// isUndefOrInRange - Return true if every element in Mask, begining 3143/// from position Pos and ending in Pos+Size, falls within the specified 3144/// range (L, L+Pos]. or is undef. 3145static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask, 3146 int Pos, int Size, int Low, int Hi) { 3147 for (int i = Pos, e = Pos+Size; i != e; ++i) 3148 if (!isUndefOrInRange(Mask[i], Low, Hi)) 3149 return false; 3150 return true; 3151} 3152 3153/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3154/// specified value. 3155static bool isUndefOrEqual(int Val, int CmpVal) { 3156 if (Val < 0 || Val == CmpVal) 3157 return true; 3158 return false; 3159} 3160 3161/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3162/// from position Pos and ending in Pos+Size, falls within the specified 3163/// sequential range (L, L+Pos]. or is undef. 3164static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask, 3165 int Pos, int Size, int Low) { 3166 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3167 if (!isUndefOrEqual(Mask[i], Low)) 3168 return false; 3169 return true; 3170} 3171 3172/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3173/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3174/// the second operand. 3175static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3176 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3177 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3178 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3179 return (Mask[0] < 2 && Mask[1] < 2); 3180 return false; 3181} 3182 3183bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3184 SmallVector<int, 8> M; 3185 N->getMask(M); 3186 return ::isPSHUFDMask(M, N->getValueType(0)); 3187} 3188 3189/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3190/// is suitable for input to PSHUFHW. 3191static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3192 if (VT != MVT::v8i16) 3193 return false; 3194 3195 // Lower quadword copied in order or undef. 3196 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3197 return false; 3198 3199 // Upper quadword shuffled. 3200 for (unsigned i = 4; i != 8; ++i) 3201 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3202 return false; 3203 3204 return true; 3205} 3206 3207bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3208 SmallVector<int, 8> M; 3209 N->getMask(M); 3210 return ::isPSHUFHWMask(M, N->getValueType(0)); 3211} 3212 3213/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3214/// is suitable for input to PSHUFLW. 3215static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3216 if (VT != MVT::v8i16) 3217 return false; 3218 3219 // Upper quadword copied in order. 3220 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3221 return false; 3222 3223 // Lower quadword shuffled. 3224 for (unsigned i = 0; i != 4; ++i) 3225 if (Mask[i] >= 4) 3226 return false; 3227 3228 return true; 3229} 3230 3231bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3232 SmallVector<int, 8> M; 3233 N->getMask(M); 3234 return ::isPSHUFLWMask(M, N->getValueType(0)); 3235} 3236 3237/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3238/// is suitable for input to PALIGNR. 3239static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3240 bool hasSSSE3OrAVX) { 3241 int i, e = VT.getVectorNumElements(); 3242 if (VT.getSizeInBits() != 128) 3243 return false; 3244 3245 // Do not handle v2i64 / v2f64 shuffles with palignr. 3246 if (e < 4 || !hasSSSE3OrAVX) 3247 return false; 3248 3249 for (i = 0; i != e; ++i) 3250 if (Mask[i] >= 0) 3251 break; 3252 3253 // All undef, not a palignr. 3254 if (i == e) 3255 return false; 3256 3257 // Make sure we're shifting in the right direction. 3258 if (Mask[i] <= i) 3259 return false; 3260 3261 int s = Mask[i] - i; 3262 3263 // Check the rest of the elements to see if they are consecutive. 3264 for (++i; i != e; ++i) { 3265 int m = Mask[i]; 3266 if (m >= 0 && m != s+i) 3267 return false; 3268 } 3269 return true; 3270} 3271 3272/// isVSHUFPYMask - Return true if the specified VECTOR_SHUFFLE operand 3273/// specifies a shuffle of elements that is suitable for input to 256-bit 3274/// VSHUFPSY. 3275static bool isVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3276 bool HasAVX, bool Commuted = false) { 3277 int NumElems = VT.getVectorNumElements(); 3278 3279 if (!HasAVX || VT.getSizeInBits() != 256) 3280 return false; 3281 3282 if (NumElems != 4 && NumElems != 8) 3283 return false; 3284 3285 // VSHUFPSY divides the resulting vector into 4 chunks. 3286 // The sources are also splitted into 4 chunks, and each destination 3287 // chunk must come from a different source chunk. 3288 // 3289 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3290 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3291 // 3292 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3293 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3294 // 3295 // VSHUFPDY divides the resulting vector into 4 chunks. 3296 // The sources are also splitted into 4 chunks, and each destination 3297 // chunk must come from a different source chunk. 3298 // 3299 // SRC1 => X3 X2 X1 X0 3300 // SRC2 => Y3 Y2 Y1 Y0 3301 // 3302 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3303 // 3304 unsigned QuarterSize = NumElems/4; 3305 unsigned HalfSize = QuarterSize*2; 3306 for (unsigned l = 0; l != 2; ++l) { 3307 unsigned LaneStart = l*HalfSize; 3308 for (unsigned s = 0; s != 2; ++s) { 3309 unsigned QuarterStart = s*QuarterSize; 3310 unsigned Src = (Commuted) ? (1-s) : s; 3311 unsigned SrcStart = Src*NumElems + LaneStart; 3312 for (unsigned i = 0; i != QuarterSize; ++i) { 3313 int Idx = Mask[i+QuarterStart+LaneStart]; 3314 if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize)) 3315 return false; 3316 // For VSHUFPSY, the mask of the second half must be the same as the 3317 // first but with the appropriate offsets. This works in the same way as 3318 // VPERMILPS works with masks. 3319 if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0) 3320 continue; 3321 if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+LaneStart)) 3322 return false; 3323 } 3324 } 3325 } 3326 3327 return true; 3328} 3329 3330/// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle 3331/// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions. 3332static unsigned getShuffleVSHUFPYImmediate(ShuffleVectorSDNode *SVOp) { 3333 EVT VT = SVOp->getValueType(0); 3334 unsigned NumElems = VT.getVectorNumElements(); 3335 3336 assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types"); 3337 assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types"); 3338 3339 unsigned HalfSize = NumElems/2; 3340 unsigned Mul = (NumElems == 8) ? 2 : 1; 3341 unsigned Mask = 0; 3342 for (unsigned i = 0; i != NumElems; ++i) { 3343 int Elt = SVOp->getMaskElt(i); 3344 if (Elt < 0) 3345 continue; 3346 Elt %= HalfSize; 3347 unsigned Shamt = i; 3348 // For VSHUFPSY, the mask of the first half must be equal to the second one. 3349 if (NumElems == 8) Shamt %= HalfSize; 3350 Mask |= Elt << (Shamt*Mul); 3351 } 3352 3353 return Mask; 3354} 3355 3356/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3357/// the two vector operands have swapped position. 3358static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3359 unsigned NumElems) { 3360 for (unsigned i = 0; i != NumElems; ++i) { 3361 int idx = Mask[i]; 3362 if (idx < 0) 3363 continue; 3364 else if (idx < (int)NumElems) 3365 Mask[i] = idx + NumElems; 3366 else 3367 Mask[i] = idx - NumElems; 3368 } 3369} 3370 3371/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3372/// specifies a shuffle of elements that is suitable for input to 128-bit 3373/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3374/// reverse of what x86 shuffles want. 3375static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT, 3376 bool Commuted = false) { 3377 unsigned NumElems = VT.getVectorNumElements(); 3378 3379 if (VT.getSizeInBits() != 128) 3380 return false; 3381 3382 if (NumElems != 2 && NumElems != 4) 3383 return false; 3384 3385 unsigned Half = NumElems / 2; 3386 unsigned SrcStart = Commuted ? NumElems : 0; 3387 for (unsigned i = 0; i != Half; ++i) 3388 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems)) 3389 return false; 3390 SrcStart = Commuted ? 0 : NumElems; 3391 for (unsigned i = Half; i != NumElems; ++i) 3392 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems)) 3393 return false; 3394 3395 return true; 3396} 3397 3398bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3399 SmallVector<int, 8> M; 3400 N->getMask(M); 3401 return ::isSHUFPMask(M, N->getValueType(0)); 3402} 3403 3404/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3405/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3406bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3407 EVT VT = N->getValueType(0); 3408 unsigned NumElems = VT.getVectorNumElements(); 3409 3410 if (VT.getSizeInBits() != 128) 3411 return false; 3412 3413 if (NumElems != 4) 3414 return false; 3415 3416 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3417 return isUndefOrEqual(N->getMaskElt(0), 6) && 3418 isUndefOrEqual(N->getMaskElt(1), 7) && 3419 isUndefOrEqual(N->getMaskElt(2), 2) && 3420 isUndefOrEqual(N->getMaskElt(3), 3); 3421} 3422 3423/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3424/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3425/// <2, 3, 2, 3> 3426bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3427 EVT VT = N->getValueType(0); 3428 unsigned NumElems = VT.getVectorNumElements(); 3429 3430 if (VT.getSizeInBits() != 128) 3431 return false; 3432 3433 if (NumElems != 4) 3434 return false; 3435 3436 return isUndefOrEqual(N->getMaskElt(0), 2) && 3437 isUndefOrEqual(N->getMaskElt(1), 3) && 3438 isUndefOrEqual(N->getMaskElt(2), 2) && 3439 isUndefOrEqual(N->getMaskElt(3), 3); 3440} 3441 3442/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3443/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3444bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3445 EVT VT = N->getValueType(0); 3446 3447 if (VT.getSizeInBits() != 128) 3448 return false; 3449 3450 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3451 3452 if (NumElems != 2 && NumElems != 4) 3453 return false; 3454 3455 for (unsigned i = 0; i < NumElems/2; ++i) 3456 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3457 return false; 3458 3459 for (unsigned i = NumElems/2; i < NumElems; ++i) 3460 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3461 return false; 3462 3463 return true; 3464} 3465 3466/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3467/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3468bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3469 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3470 3471 if ((NumElems != 2 && NumElems != 4) 3472 || N->getValueType(0).getSizeInBits() > 128) 3473 return false; 3474 3475 for (unsigned i = 0; i < NumElems/2; ++i) 3476 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3477 return false; 3478 3479 for (unsigned i = 0; i < NumElems/2; ++i) 3480 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3481 return false; 3482 3483 return true; 3484} 3485 3486/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3487/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3488static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3489 bool HasAVX2, bool V2IsSplat = false) { 3490 unsigned NumElts = VT.getVectorNumElements(); 3491 3492 assert((VT.is128BitVector() || VT.is256BitVector()) && 3493 "Unsupported vector type for unpckh"); 3494 3495 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3496 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3497 return false; 3498 3499 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3500 // independently on 128-bit lanes. 3501 unsigned NumLanes = VT.getSizeInBits()/128; 3502 unsigned NumLaneElts = NumElts/NumLanes; 3503 3504 for (unsigned l = 0; l != NumLanes; ++l) { 3505 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3506 i != (l+1)*NumLaneElts; 3507 i += 2, ++j) { 3508 int BitI = Mask[i]; 3509 int BitI1 = Mask[i+1]; 3510 if (!isUndefOrEqual(BitI, j)) 3511 return false; 3512 if (V2IsSplat) { 3513 if (!isUndefOrEqual(BitI1, NumElts)) 3514 return false; 3515 } else { 3516 if (!isUndefOrEqual(BitI1, j + NumElts)) 3517 return false; 3518 } 3519 } 3520 } 3521 3522 return true; 3523} 3524 3525bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3526 SmallVector<int, 8> M; 3527 N->getMask(M); 3528 return ::isUNPCKLMask(M, N->getValueType(0), HasAVX2, V2IsSplat); 3529} 3530 3531/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3532/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3533static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3534 bool HasAVX2, bool V2IsSplat = false) { 3535 unsigned NumElts = VT.getVectorNumElements(); 3536 3537 assert((VT.is128BitVector() || VT.is256BitVector()) && 3538 "Unsupported vector type for unpckh"); 3539 3540 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3541 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3542 return false; 3543 3544 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3545 // independently on 128-bit lanes. 3546 unsigned NumLanes = VT.getSizeInBits()/128; 3547 unsigned NumLaneElts = NumElts/NumLanes; 3548 3549 for (unsigned l = 0; l != NumLanes; ++l) { 3550 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3551 i != (l+1)*NumLaneElts; i += 2, ++j) { 3552 int BitI = Mask[i]; 3553 int BitI1 = Mask[i+1]; 3554 if (!isUndefOrEqual(BitI, j)) 3555 return false; 3556 if (V2IsSplat) { 3557 if (isUndefOrEqual(BitI1, NumElts)) 3558 return false; 3559 } else { 3560 if (!isUndefOrEqual(BitI1, j+NumElts)) 3561 return false; 3562 } 3563 } 3564 } 3565 return true; 3566} 3567 3568bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3569 SmallVector<int, 8> M; 3570 N->getMask(M); 3571 return ::isUNPCKHMask(M, N->getValueType(0), HasAVX2, V2IsSplat); 3572} 3573 3574/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3575/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3576/// <0, 0, 1, 1> 3577static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3578 bool HasAVX2) { 3579 unsigned NumElts = VT.getVectorNumElements(); 3580 3581 assert((VT.is128BitVector() || VT.is256BitVector()) && 3582 "Unsupported vector type for unpckh"); 3583 3584 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3585 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3586 return false; 3587 3588 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3589 // FIXME: Need a better way to get rid of this, there's no latency difference 3590 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3591 // the former later. We should also remove the "_undef" special mask. 3592 if (NumElts == 4 && VT.getSizeInBits() == 256) 3593 return false; 3594 3595 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3596 // independently on 128-bit lanes. 3597 unsigned NumLanes = VT.getSizeInBits()/128; 3598 unsigned NumLaneElts = NumElts/NumLanes; 3599 3600 for (unsigned l = 0; l != NumLanes; ++l) { 3601 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3602 i != (l+1)*NumLaneElts; 3603 i += 2, ++j) { 3604 int BitI = Mask[i]; 3605 int BitI1 = Mask[i+1]; 3606 3607 if (!isUndefOrEqual(BitI, j)) 3608 return false; 3609 if (!isUndefOrEqual(BitI1, j)) 3610 return false; 3611 } 3612 } 3613 3614 return true; 3615} 3616 3617bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3618 SmallVector<int, 8> M; 3619 N->getMask(M); 3620 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0), HasAVX2); 3621} 3622 3623/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3624/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3625/// <2, 2, 3, 3> 3626static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3627 bool HasAVX2) { 3628 unsigned NumElts = VT.getVectorNumElements(); 3629 3630 assert((VT.is128BitVector() || VT.is256BitVector()) && 3631 "Unsupported vector type for unpckh"); 3632 3633 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3634 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3635 return false; 3636 3637 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3638 // independently on 128-bit lanes. 3639 unsigned NumLanes = VT.getSizeInBits()/128; 3640 unsigned NumLaneElts = NumElts/NumLanes; 3641 3642 for (unsigned l = 0; l != NumLanes; ++l) { 3643 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3644 i != (l+1)*NumLaneElts; i += 2, ++j) { 3645 int BitI = Mask[i]; 3646 int BitI1 = Mask[i+1]; 3647 if (!isUndefOrEqual(BitI, j)) 3648 return false; 3649 if (!isUndefOrEqual(BitI1, j)) 3650 return false; 3651 } 3652 } 3653 return true; 3654} 3655 3656bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3657 SmallVector<int, 8> M; 3658 N->getMask(M); 3659 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0), HasAVX2); 3660} 3661 3662/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3663/// specifies a shuffle of elements that is suitable for input to MOVSS, 3664/// MOVSD, and MOVD, i.e. setting the lowest element. 3665static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3666 if (VT.getVectorElementType().getSizeInBits() < 32) 3667 return false; 3668 if (VT.getSizeInBits() == 256) 3669 return false; 3670 3671 unsigned NumElts = VT.getVectorNumElements(); 3672 3673 if (!isUndefOrEqual(Mask[0], NumElts)) 3674 return false; 3675 3676 for (unsigned i = 1; i != NumElts; ++i) 3677 if (!isUndefOrEqual(Mask[i], i)) 3678 return false; 3679 3680 return true; 3681} 3682 3683bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3684 SmallVector<int, 8> M; 3685 N->getMask(M); 3686 return ::isMOVLMask(M, N->getValueType(0)); 3687} 3688 3689/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3690/// as permutations between 128-bit chunks or halves. As an example: this 3691/// shuffle bellow: 3692/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3693/// The first half comes from the second half of V1 and the second half from the 3694/// the second half of V2. 3695static bool isVPERM2X128Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3696 bool HasAVX) { 3697 if (!HasAVX || VT.getSizeInBits() != 256) 3698 return false; 3699 3700 // The shuffle result is divided into half A and half B. In total the two 3701 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3702 // B must come from C, D, E or F. 3703 unsigned HalfSize = VT.getVectorNumElements()/2; 3704 bool MatchA = false, MatchB = false; 3705 3706 // Check if A comes from one of C, D, E, F. 3707 for (unsigned Half = 0; Half != 4; ++Half) { 3708 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3709 MatchA = true; 3710 break; 3711 } 3712 } 3713 3714 // Check if B comes from one of C, D, E, F. 3715 for (unsigned Half = 0; Half != 4; ++Half) { 3716 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3717 MatchB = true; 3718 break; 3719 } 3720 } 3721 3722 return MatchA && MatchB; 3723} 3724 3725/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3726/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3727static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3728 EVT VT = SVOp->getValueType(0); 3729 3730 unsigned HalfSize = VT.getVectorNumElements()/2; 3731 3732 unsigned FstHalf = 0, SndHalf = 0; 3733 for (unsigned i = 0; i < HalfSize; ++i) { 3734 if (SVOp->getMaskElt(i) > 0) { 3735 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3736 break; 3737 } 3738 } 3739 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3740 if (SVOp->getMaskElt(i) > 0) { 3741 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3742 break; 3743 } 3744 } 3745 3746 return (FstHalf | (SndHalf << 4)); 3747} 3748 3749/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3750/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3751/// Note that VPERMIL mask matching is different depending whether theunderlying 3752/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3753/// to the same elements of the low, but to the higher half of the source. 3754/// In VPERMILPD the two lanes could be shuffled independently of each other 3755/// with the same restriction that lanes can't be crossed. 3756static bool isVPERMILPMask(const SmallVectorImpl<int> &Mask, EVT VT, 3757 bool HasAVX) { 3758 if (!HasAVX) 3759 return false; 3760 3761 unsigned NumElts = VT.getVectorNumElements(); 3762 // Only match 256-bit with 32/64-bit types 3763 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3764 return false; 3765 3766 unsigned NumLanes = VT.getSizeInBits()/128; 3767 unsigned LaneSize = NumElts/NumLanes; 3768 for (unsigned l = 0; l != NumLanes; ++l) { 3769 unsigned LaneStart = l*LaneSize; 3770 for (unsigned i = 0; i != LaneSize; ++i) { 3771 if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize)) 3772 return false; 3773 if (NumElts == 4 || l == 0) 3774 continue; 3775 // VPERMILPS handling 3776 if (Mask[i] < 0) 3777 continue; 3778 if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneStart)) 3779 return false; 3780 } 3781 } 3782 3783 return true; 3784} 3785 3786/// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle 3787/// the specified VECTOR_MASK mask with VPERMILPS/D* instructions. 3788static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) { 3789 EVT VT = SVOp->getValueType(0); 3790 3791 unsigned NumElts = VT.getVectorNumElements(); 3792 unsigned NumLanes = VT.getSizeInBits()/128; 3793 unsigned LaneSize = NumElts/NumLanes; 3794 3795 // Although the mask is equal for both lanes do it twice to get the cases 3796 // where a mask will match because the same mask element is undef on the 3797 // first half but valid on the second. This would get pathological cases 3798 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3799 unsigned Shift = (LaneSize == 4) ? 2 : 1; 3800 unsigned Mask = 0; 3801 for (unsigned i = 0; i != NumElts; ++i) { 3802 int MaskElt = SVOp->getMaskElt(i); 3803 if (MaskElt < 0) 3804 continue; 3805 MaskElt %= LaneSize; 3806 unsigned Shamt = i; 3807 // VPERMILPSY, the mask of the first half must be equal to the second one 3808 if (NumElts == 8) Shamt %= LaneSize; 3809 Mask |= MaskElt << (Shamt*Shift); 3810 } 3811 3812 return Mask; 3813} 3814 3815/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3816/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3817/// element of vector 2 and the other elements to come from vector 1 in order. 3818static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3819 bool V2IsSplat = false, bool V2IsUndef = false) { 3820 unsigned NumOps = VT.getVectorNumElements(); 3821 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3822 return false; 3823 3824 if (!isUndefOrEqual(Mask[0], 0)) 3825 return false; 3826 3827 for (unsigned i = 1; i != NumOps; ++i) 3828 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3829 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3830 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3831 return false; 3832 3833 return true; 3834} 3835 3836static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3837 bool V2IsUndef = false) { 3838 SmallVector<int, 8> M; 3839 N->getMask(M); 3840 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3841} 3842 3843/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3844/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3845/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3846bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3847 const X86Subtarget *Subtarget) { 3848 if (!Subtarget->hasSSE3orAVX()) 3849 return false; 3850 3851 // The second vector must be undef 3852 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3853 return false; 3854 3855 EVT VT = N->getValueType(0); 3856 unsigned NumElems = VT.getVectorNumElements(); 3857 3858 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3859 (VT.getSizeInBits() == 256 && NumElems != 8)) 3860 return false; 3861 3862 // "i+1" is the value the indexed mask element must have 3863 for (unsigned i = 0; i < NumElems; i += 2) 3864 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3865 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3866 return false; 3867 3868 return true; 3869} 3870 3871/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3872/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3873/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3874bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3875 const X86Subtarget *Subtarget) { 3876 if (!Subtarget->hasSSE3orAVX()) 3877 return false; 3878 3879 // The second vector must be undef 3880 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3881 return false; 3882 3883 EVT VT = N->getValueType(0); 3884 unsigned NumElems = VT.getVectorNumElements(); 3885 3886 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3887 (VT.getSizeInBits() == 256 && NumElems != 8)) 3888 return false; 3889 3890 // "i" is the value the indexed mask element must have 3891 for (unsigned i = 0; i != NumElems; i += 2) 3892 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3893 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3894 return false; 3895 3896 return true; 3897} 3898 3899/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3900/// specifies a shuffle of elements that is suitable for input to 256-bit 3901/// version of MOVDDUP. 3902static bool isMOVDDUPYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3903 bool HasAVX) { 3904 unsigned NumElts = VT.getVectorNumElements(); 3905 3906 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3907 return false; 3908 3909 for (unsigned i = 0; i != NumElts/2; ++i) 3910 if (!isUndefOrEqual(Mask[i], 0)) 3911 return false; 3912 for (unsigned i = NumElts/2; i != NumElts; ++i) 3913 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3914 return false; 3915 return true; 3916} 3917 3918/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3919/// specifies a shuffle of elements that is suitable for input to 128-bit 3920/// version of MOVDDUP. 3921bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3922 EVT VT = N->getValueType(0); 3923 3924 if (VT.getSizeInBits() != 128) 3925 return false; 3926 3927 unsigned e = VT.getVectorNumElements() / 2; 3928 for (unsigned i = 0; i != e; ++i) 3929 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3930 return false; 3931 for (unsigned i = 0; i != e; ++i) 3932 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3933 return false; 3934 return true; 3935} 3936 3937/// isVEXTRACTF128Index - Return true if the specified 3938/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3939/// suitable for input to VEXTRACTF128. 3940bool X86::isVEXTRACTF128Index(SDNode *N) { 3941 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3942 return false; 3943 3944 // The index should be aligned on a 128-bit boundary. 3945 uint64_t Index = 3946 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3947 3948 unsigned VL = N->getValueType(0).getVectorNumElements(); 3949 unsigned VBits = N->getValueType(0).getSizeInBits(); 3950 unsigned ElSize = VBits / VL; 3951 bool Result = (Index * ElSize) % 128 == 0; 3952 3953 return Result; 3954} 3955 3956/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3957/// operand specifies a subvector insert that is suitable for input to 3958/// VINSERTF128. 3959bool X86::isVINSERTF128Index(SDNode *N) { 3960 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3961 return false; 3962 3963 // The index should be aligned on a 128-bit boundary. 3964 uint64_t Index = 3965 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3966 3967 unsigned VL = N->getValueType(0).getVectorNumElements(); 3968 unsigned VBits = N->getValueType(0).getSizeInBits(); 3969 unsigned ElSize = VBits / VL; 3970 bool Result = (Index * ElSize) % 128 == 0; 3971 3972 return Result; 3973} 3974 3975/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3976/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3977unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3978 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3979 unsigned NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3980 3981 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3982 unsigned Mask = 0; 3983 for (unsigned i = 0; i != NumOperands; ++i) { 3984 int Val = SVOp->getMaskElt(NumOperands-i-1); 3985 if (Val < 0) Val = 0; 3986 if (Val >= (int)NumOperands) Val -= NumOperands; 3987 Mask |= Val; 3988 if (i != NumOperands - 1) 3989 Mask <<= Shift; 3990 } 3991 return Mask; 3992} 3993 3994/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3995/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3996unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3998 unsigned Mask = 0; 3999 // 8 nodes, but we only care about the last 4. 4000 for (unsigned i = 7; i >= 4; --i) { 4001 int Val = SVOp->getMaskElt(i); 4002 if (Val >= 0) 4003 Mask |= (Val - 4); 4004 if (i != 4) 4005 Mask <<= 2; 4006 } 4007 return Mask; 4008} 4009 4010/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4011/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4012unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 4013 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4014 unsigned Mask = 0; 4015 // 8 nodes, but we only care about the first 4. 4016 for (int i = 3; i >= 0; --i) { 4017 int Val = SVOp->getMaskElt(i); 4018 if (Val >= 0) 4019 Mask |= Val; 4020 if (i != 0) 4021 Mask <<= 2; 4022 } 4023 return Mask; 4024} 4025 4026/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4027/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4028static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4029 EVT VT = SVOp->getValueType(0); 4030 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 4031 int Val = 0; 4032 4033 unsigned i, e; 4034 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4035 Val = SVOp->getMaskElt(i); 4036 if (Val >= 0) 4037 break; 4038 } 4039 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4040 return (Val - i) * EltSize; 4041} 4042 4043/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4044/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4045/// instructions. 4046unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4047 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4048 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4049 4050 uint64_t Index = 4051 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4052 4053 EVT VecVT = N->getOperand(0).getValueType(); 4054 EVT ElVT = VecVT.getVectorElementType(); 4055 4056 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4057 return Index / NumElemsPerChunk; 4058} 4059 4060/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4061/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4062/// instructions. 4063unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4064 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4065 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4066 4067 uint64_t Index = 4068 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4069 4070 EVT VecVT = N->getValueType(0); 4071 EVT ElVT = VecVT.getVectorElementType(); 4072 4073 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4074 return Index / NumElemsPerChunk; 4075} 4076 4077/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4078/// constant +0.0. 4079bool X86::isZeroNode(SDValue Elt) { 4080 return ((isa<ConstantSDNode>(Elt) && 4081 cast<ConstantSDNode>(Elt)->isNullValue()) || 4082 (isa<ConstantFPSDNode>(Elt) && 4083 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4084} 4085 4086/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4087/// their permute mask. 4088static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4089 SelectionDAG &DAG) { 4090 EVT VT = SVOp->getValueType(0); 4091 unsigned NumElems = VT.getVectorNumElements(); 4092 SmallVector<int, 8> MaskVec; 4093 4094 for (unsigned i = 0; i != NumElems; ++i) { 4095 int idx = SVOp->getMaskElt(i); 4096 if (idx < 0) 4097 MaskVec.push_back(idx); 4098 else if (idx < (int)NumElems) 4099 MaskVec.push_back(idx + NumElems); 4100 else 4101 MaskVec.push_back(idx - NumElems); 4102 } 4103 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4104 SVOp->getOperand(0), &MaskVec[0]); 4105} 4106 4107/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4108/// match movhlps. The lower half elements should come from upper half of 4109/// V1 (and in order), and the upper half elements should come from the upper 4110/// half of V2 (and in order). 4111static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4112 EVT VT = Op->getValueType(0); 4113 if (VT.getSizeInBits() != 128) 4114 return false; 4115 if (VT.getVectorNumElements() != 4) 4116 return false; 4117 for (unsigned i = 0, e = 2; i != e; ++i) 4118 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4119 return false; 4120 for (unsigned i = 2; i != 4; ++i) 4121 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4122 return false; 4123 return true; 4124} 4125 4126/// isScalarLoadToVector - Returns true if the node is a scalar load that 4127/// is promoted to a vector. It also returns the LoadSDNode by reference if 4128/// required. 4129static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4130 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4131 return false; 4132 N = N->getOperand(0).getNode(); 4133 if (!ISD::isNON_EXTLoad(N)) 4134 return false; 4135 if (LD) 4136 *LD = cast<LoadSDNode>(N); 4137 return true; 4138} 4139 4140// Test whether the given value is a vector value which will be legalized 4141// into a load. 4142static bool WillBeConstantPoolLoad(SDNode *N) { 4143 if (N->getOpcode() != ISD::BUILD_VECTOR) 4144 return false; 4145 4146 // Check for any non-constant elements. 4147 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4148 switch (N->getOperand(i).getNode()->getOpcode()) { 4149 case ISD::UNDEF: 4150 case ISD::ConstantFP: 4151 case ISD::Constant: 4152 break; 4153 default: 4154 return false; 4155 } 4156 4157 // Vectors of all-zeros and all-ones are materialized with special 4158 // instructions rather than being loaded. 4159 return !ISD::isBuildVectorAllZeros(N) && 4160 !ISD::isBuildVectorAllOnes(N); 4161} 4162 4163/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4164/// match movlp{s|d}. The lower half elements should come from lower half of 4165/// V1 (and in order), and the upper half elements should come from the upper 4166/// half of V2 (and in order). And since V1 will become the source of the 4167/// MOVLP, it must be either a vector load or a scalar load to vector. 4168static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4169 ShuffleVectorSDNode *Op) { 4170 EVT VT = Op->getValueType(0); 4171 if (VT.getSizeInBits() != 128) 4172 return false; 4173 4174 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4175 return false; 4176 // Is V2 is a vector load, don't do this transformation. We will try to use 4177 // load folding shufps op. 4178 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4179 return false; 4180 4181 unsigned NumElems = VT.getVectorNumElements(); 4182 4183 if (NumElems != 2 && NumElems != 4) 4184 return false; 4185 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4186 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4187 return false; 4188 for (unsigned i = NumElems/2; i != NumElems; ++i) 4189 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4190 return false; 4191 return true; 4192} 4193 4194/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4195/// all the same. 4196static bool isSplatVector(SDNode *N) { 4197 if (N->getOpcode() != ISD::BUILD_VECTOR) 4198 return false; 4199 4200 SDValue SplatValue = N->getOperand(0); 4201 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4202 if (N->getOperand(i) != SplatValue) 4203 return false; 4204 return true; 4205} 4206 4207/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4208/// to an zero vector. 4209/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4210static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4211 SDValue V1 = N->getOperand(0); 4212 SDValue V2 = N->getOperand(1); 4213 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4214 for (unsigned i = 0; i != NumElems; ++i) { 4215 int Idx = N->getMaskElt(i); 4216 if (Idx >= (int)NumElems) { 4217 unsigned Opc = V2.getOpcode(); 4218 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4219 continue; 4220 if (Opc != ISD::BUILD_VECTOR || 4221 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4222 return false; 4223 } else if (Idx >= 0) { 4224 unsigned Opc = V1.getOpcode(); 4225 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4226 continue; 4227 if (Opc != ISD::BUILD_VECTOR || 4228 !X86::isZeroNode(V1.getOperand(Idx))) 4229 return false; 4230 } 4231 } 4232 return true; 4233} 4234 4235/// getZeroVector - Returns a vector of specified type with all zero elements. 4236/// 4237static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG, 4238 DebugLoc dl) { 4239 assert(VT.isVector() && "Expected a vector type"); 4240 4241 // Always build SSE zero vectors as <4 x i32> bitcasted 4242 // to their dest type. This ensures they get CSE'd. 4243 SDValue Vec; 4244 if (VT.getSizeInBits() == 128) { // SSE 4245 if (HasXMMInt) { // SSE2 4246 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4247 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4248 } else { // SSE1 4249 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4250 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4251 } 4252 } else if (VT.getSizeInBits() == 256) { // AVX 4253 // 256-bit logic and arithmetic instructions in AVX are 4254 // all floating-point, no support for integer ops. Default 4255 // to emitting fp zeroed vectors then. 4256 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4257 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4259 } 4260 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4261} 4262 4263/// getOnesVector - Returns a vector of specified type with all bits set. 4264/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4265/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4266/// Then bitcast to their original type, ensuring they get CSE'd. 4267static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4268 DebugLoc dl) { 4269 assert(VT.isVector() && "Expected a vector type"); 4270 assert((VT.is128BitVector() || VT.is256BitVector()) 4271 && "Expected a 128-bit or 256-bit vector type"); 4272 4273 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4274 SDValue Vec; 4275 if (VT.getSizeInBits() == 256) { 4276 if (HasAVX2) { // AVX2 4277 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4278 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4279 } else { // AVX 4280 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4281 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4282 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4283 Vec = Insert128BitVector(InsV, Vec, 4284 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4285 } 4286 } else { 4287 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4288 } 4289 4290 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4291} 4292 4293/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4294/// that point to V2 points to its first element. 4295static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4296 EVT VT = SVOp->getValueType(0); 4297 unsigned NumElems = VT.getVectorNumElements(); 4298 4299 bool Changed = false; 4300 SmallVector<int, 8> MaskVec; 4301 SVOp->getMask(MaskVec); 4302 4303 for (unsigned i = 0; i != NumElems; ++i) { 4304 if (MaskVec[i] > (int)NumElems) { 4305 MaskVec[i] = NumElems; 4306 Changed = true; 4307 } 4308 } 4309 if (Changed) 4310 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4311 SVOp->getOperand(1), &MaskVec[0]); 4312 return SDValue(SVOp, 0); 4313} 4314 4315/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4316/// operation of specified width. 4317static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4318 SDValue V2) { 4319 unsigned NumElems = VT.getVectorNumElements(); 4320 SmallVector<int, 8> Mask; 4321 Mask.push_back(NumElems); 4322 for (unsigned i = 1; i != NumElems; ++i) 4323 Mask.push_back(i); 4324 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4325} 4326 4327/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4328static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4329 SDValue V2) { 4330 unsigned NumElems = VT.getVectorNumElements(); 4331 SmallVector<int, 8> Mask; 4332 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4333 Mask.push_back(i); 4334 Mask.push_back(i + NumElems); 4335 } 4336 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4337} 4338 4339/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4340static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4341 SDValue V2) { 4342 unsigned NumElems = VT.getVectorNumElements(); 4343 unsigned Half = NumElems/2; 4344 SmallVector<int, 8> Mask; 4345 for (unsigned i = 0; i != Half; ++i) { 4346 Mask.push_back(i + Half); 4347 Mask.push_back(i + NumElems + Half); 4348 } 4349 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4350} 4351 4352// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4353// a generic shuffle instruction because the target has no such instructions. 4354// Generate shuffles which repeat i16 and i8 several times until they can be 4355// represented by v4f32 and then be manipulated by target suported shuffles. 4356static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4357 EVT VT = V.getValueType(); 4358 int NumElems = VT.getVectorNumElements(); 4359 DebugLoc dl = V.getDebugLoc(); 4360 4361 while (NumElems > 4) { 4362 if (EltNo < NumElems/2) { 4363 V = getUnpackl(DAG, dl, VT, V, V); 4364 } else { 4365 V = getUnpackh(DAG, dl, VT, V, V); 4366 EltNo -= NumElems/2; 4367 } 4368 NumElems >>= 1; 4369 } 4370 return V; 4371} 4372 4373/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4374static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4375 EVT VT = V.getValueType(); 4376 DebugLoc dl = V.getDebugLoc(); 4377 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4378 && "Vector size not supported"); 4379 4380 if (VT.getSizeInBits() == 128) { 4381 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4382 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4383 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4384 &SplatMask[0]); 4385 } else { 4386 // To use VPERMILPS to splat scalars, the second half of indicies must 4387 // refer to the higher part, which is a duplication of the lower one, 4388 // because VPERMILPS can only handle in-lane permutations. 4389 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4390 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4391 4392 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4393 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4394 &SplatMask[0]); 4395 } 4396 4397 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4398} 4399 4400/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4401static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4402 EVT SrcVT = SV->getValueType(0); 4403 SDValue V1 = SV->getOperand(0); 4404 DebugLoc dl = SV->getDebugLoc(); 4405 4406 int EltNo = SV->getSplatIndex(); 4407 int NumElems = SrcVT.getVectorNumElements(); 4408 unsigned Size = SrcVT.getSizeInBits(); 4409 4410 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4411 "Unknown how to promote splat for type"); 4412 4413 // Extract the 128-bit part containing the splat element and update 4414 // the splat element index when it refers to the higher register. 4415 if (Size == 256) { 4416 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0; 4417 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4418 if (Idx > 0) 4419 EltNo -= NumElems/2; 4420 } 4421 4422 // All i16 and i8 vector types can't be used directly by a generic shuffle 4423 // instruction because the target has no such instruction. Generate shuffles 4424 // which repeat i16 and i8 several times until they fit in i32, and then can 4425 // be manipulated by target suported shuffles. 4426 EVT EltVT = SrcVT.getVectorElementType(); 4427 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4428 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4429 4430 // Recreate the 256-bit vector and place the same 128-bit vector 4431 // into the low and high part. This is necessary because we want 4432 // to use VPERM* to shuffle the vectors 4433 if (Size == 256) { 4434 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4435 DAG.getConstant(0, MVT::i32), DAG, dl); 4436 V1 = Insert128BitVector(InsV, V1, 4437 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4438 } 4439 4440 return getLegalSplat(DAG, V1, EltNo); 4441} 4442 4443/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4444/// vector of zero or undef vector. This produces a shuffle where the low 4445/// element of V2 is swizzled into the zero/undef vector, landing at element 4446/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4447static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4448 bool isZero, bool HasXMMInt, 4449 SelectionDAG &DAG) { 4450 EVT VT = V2.getValueType(); 4451 SDValue V1 = isZero 4452 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4453 unsigned NumElems = VT.getVectorNumElements(); 4454 SmallVector<int, 16> MaskVec; 4455 for (unsigned i = 0; i != NumElems; ++i) 4456 // If this is the insertion idx, put the low elt of V2 here. 4457 MaskVec.push_back(i == Idx ? NumElems : i); 4458 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4459} 4460 4461/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4462/// element of the result of the vector shuffle. 4463static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4464 unsigned Depth) { 4465 if (Depth == 6) 4466 return SDValue(); // Limit search depth. 4467 4468 SDValue V = SDValue(N, 0); 4469 EVT VT = V.getValueType(); 4470 unsigned Opcode = V.getOpcode(); 4471 4472 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4473 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4474 Index = SV->getMaskElt(Index); 4475 4476 if (Index < 0) 4477 return DAG.getUNDEF(VT.getVectorElementType()); 4478 4479 int NumElems = VT.getVectorNumElements(); 4480 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4481 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4482 } 4483 4484 // Recurse into target specific vector shuffles to find scalars. 4485 if (isTargetShuffle(Opcode)) { 4486 int NumElems = VT.getVectorNumElements(); 4487 SmallVector<unsigned, 16> ShuffleMask; 4488 SDValue ImmN; 4489 4490 switch(Opcode) { 4491 case X86ISD::SHUFP: 4492 ImmN = N->getOperand(N->getNumOperands()-1); 4493 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4494 ShuffleMask); 4495 break; 4496 case X86ISD::UNPCKH: 4497 DecodeUNPCKHMask(VT, ShuffleMask); 4498 break; 4499 case X86ISD::UNPCKL: 4500 DecodeUNPCKLMask(VT, ShuffleMask); 4501 break; 4502 case X86ISD::MOVHLPS: 4503 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4504 break; 4505 case X86ISD::MOVLHPS: 4506 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4507 break; 4508 case X86ISD::PSHUFD: 4509 ImmN = N->getOperand(N->getNumOperands()-1); 4510 DecodePSHUFMask(NumElems, 4511 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4512 ShuffleMask); 4513 break; 4514 case X86ISD::PSHUFHW: 4515 ImmN = N->getOperand(N->getNumOperands()-1); 4516 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4517 ShuffleMask); 4518 break; 4519 case X86ISD::PSHUFLW: 4520 ImmN = N->getOperand(N->getNumOperands()-1); 4521 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4522 ShuffleMask); 4523 break; 4524 case X86ISD::MOVSS: 4525 case X86ISD::MOVSD: { 4526 // The index 0 always comes from the first element of the second source, 4527 // this is why MOVSS and MOVSD are used in the first place. The other 4528 // elements come from the other positions of the first source vector. 4529 unsigned OpNum = (Index == 0) ? 1 : 0; 4530 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4531 Depth+1); 4532 } 4533 case X86ISD::VPERMILP: 4534 ImmN = N->getOperand(N->getNumOperands()-1); 4535 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4536 ShuffleMask); 4537 break; 4538 case X86ISD::VPERM2X128: 4539 ImmN = N->getOperand(N->getNumOperands()-1); 4540 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4541 ShuffleMask); 4542 break; 4543 case X86ISD::MOVDDUP: 4544 case X86ISD::MOVLHPD: 4545 case X86ISD::MOVLPD: 4546 case X86ISD::MOVLPS: 4547 case X86ISD::MOVSHDUP: 4548 case X86ISD::MOVSLDUP: 4549 case X86ISD::PALIGN: 4550 return SDValue(); // Not yet implemented. 4551 default: 4552 assert(0 && "unknown target shuffle node"); 4553 return SDValue(); 4554 } 4555 4556 Index = ShuffleMask[Index]; 4557 if (Index < 0) 4558 return DAG.getUNDEF(VT.getVectorElementType()); 4559 4560 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4561 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4562 Depth+1); 4563 } 4564 4565 // Actual nodes that may contain scalar elements 4566 if (Opcode == ISD::BITCAST) { 4567 V = V.getOperand(0); 4568 EVT SrcVT = V.getValueType(); 4569 unsigned NumElems = VT.getVectorNumElements(); 4570 4571 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4572 return SDValue(); 4573 } 4574 4575 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4576 return (Index == 0) ? V.getOperand(0) 4577 : DAG.getUNDEF(VT.getVectorElementType()); 4578 4579 if (V.getOpcode() == ISD::BUILD_VECTOR) 4580 return V.getOperand(Index); 4581 4582 return SDValue(); 4583} 4584 4585/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4586/// shuffle operation which come from a consecutively from a zero. The 4587/// search can start in two different directions, from left or right. 4588static 4589unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4590 bool ZerosFromLeft, SelectionDAG &DAG) { 4591 int i = 0; 4592 4593 while (i < NumElems) { 4594 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4595 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4596 if (!(Elt.getNode() && 4597 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4598 break; 4599 ++i; 4600 } 4601 4602 return i; 4603} 4604 4605/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4606/// MaskE correspond consecutively to elements from one of the vector operands, 4607/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4608static 4609bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4610 int OpIdx, int NumElems, unsigned &OpNum) { 4611 bool SeenV1 = false; 4612 bool SeenV2 = false; 4613 4614 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4615 int Idx = SVOp->getMaskElt(i); 4616 // Ignore undef indicies 4617 if (Idx < 0) 4618 continue; 4619 4620 if (Idx < NumElems) 4621 SeenV1 = true; 4622 else 4623 SeenV2 = true; 4624 4625 // Only accept consecutive elements from the same vector 4626 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4627 return false; 4628 } 4629 4630 OpNum = SeenV1 ? 0 : 1; 4631 return true; 4632} 4633 4634/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4635/// logical left shift of a vector. 4636static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4637 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4638 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4639 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4640 false /* check zeros from right */, DAG); 4641 unsigned OpSrc; 4642 4643 if (!NumZeros) 4644 return false; 4645 4646 // Considering the elements in the mask that are not consecutive zeros, 4647 // check if they consecutively come from only one of the source vectors. 4648 // 4649 // V1 = {X, A, B, C} 0 4650 // \ \ \ / 4651 // vector_shuffle V1, V2 <1, 2, 3, X> 4652 // 4653 if (!isShuffleMaskConsecutive(SVOp, 4654 0, // Mask Start Index 4655 NumElems-NumZeros-1, // Mask End Index 4656 NumZeros, // Where to start looking in the src vector 4657 NumElems, // Number of elements in vector 4658 OpSrc)) // Which source operand ? 4659 return false; 4660 4661 isLeft = false; 4662 ShAmt = NumZeros; 4663 ShVal = SVOp->getOperand(OpSrc); 4664 return true; 4665} 4666 4667/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4668/// logical left shift of a vector. 4669static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4670 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4671 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4672 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4673 true /* check zeros from left */, DAG); 4674 unsigned OpSrc; 4675 4676 if (!NumZeros) 4677 return false; 4678 4679 // Considering the elements in the mask that are not consecutive zeros, 4680 // check if they consecutively come from only one of the source vectors. 4681 // 4682 // 0 { A, B, X, X } = V2 4683 // / \ / / 4684 // vector_shuffle V1, V2 <X, X, 4, 5> 4685 // 4686 if (!isShuffleMaskConsecutive(SVOp, 4687 NumZeros, // Mask Start Index 4688 NumElems-1, // Mask End Index 4689 0, // Where to start looking in the src vector 4690 NumElems, // Number of elements in vector 4691 OpSrc)) // Which source operand ? 4692 return false; 4693 4694 isLeft = true; 4695 ShAmt = NumZeros; 4696 ShVal = SVOp->getOperand(OpSrc); 4697 return true; 4698} 4699 4700/// isVectorShift - Returns true if the shuffle can be implemented as a 4701/// logical left or right shift of a vector. 4702static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4703 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4704 // Although the logic below support any bitwidth size, there are no 4705 // shift instructions which handle more than 128-bit vectors. 4706 if (SVOp->getValueType(0).getSizeInBits() > 128) 4707 return false; 4708 4709 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4710 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4711 return true; 4712 4713 return false; 4714} 4715 4716/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4717/// 4718static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4719 unsigned NumNonZero, unsigned NumZero, 4720 SelectionDAG &DAG, 4721 const TargetLowering &TLI) { 4722 if (NumNonZero > 8) 4723 return SDValue(); 4724 4725 DebugLoc dl = Op.getDebugLoc(); 4726 SDValue V(0, 0); 4727 bool First = true; 4728 for (unsigned i = 0; i < 16; ++i) { 4729 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4730 if (ThisIsNonZero && First) { 4731 if (NumZero) 4732 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4733 else 4734 V = DAG.getUNDEF(MVT::v8i16); 4735 First = false; 4736 } 4737 4738 if ((i & 1) != 0) { 4739 SDValue ThisElt(0, 0), LastElt(0, 0); 4740 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4741 if (LastIsNonZero) { 4742 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4743 MVT::i16, Op.getOperand(i-1)); 4744 } 4745 if (ThisIsNonZero) { 4746 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4747 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4748 ThisElt, DAG.getConstant(8, MVT::i8)); 4749 if (LastIsNonZero) 4750 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4751 } else 4752 ThisElt = LastElt; 4753 4754 if (ThisElt.getNode()) 4755 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4756 DAG.getIntPtrConstant(i/2)); 4757 } 4758 } 4759 4760 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4761} 4762 4763/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4764/// 4765static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4766 unsigned NumNonZero, unsigned NumZero, 4767 SelectionDAG &DAG, 4768 const TargetLowering &TLI) { 4769 if (NumNonZero > 4) 4770 return SDValue(); 4771 4772 DebugLoc dl = Op.getDebugLoc(); 4773 SDValue V(0, 0); 4774 bool First = true; 4775 for (unsigned i = 0; i < 8; ++i) { 4776 bool isNonZero = (NonZeros & (1 << i)) != 0; 4777 if (isNonZero) { 4778 if (First) { 4779 if (NumZero) 4780 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4781 else 4782 V = DAG.getUNDEF(MVT::v8i16); 4783 First = false; 4784 } 4785 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4786 MVT::v8i16, V, Op.getOperand(i), 4787 DAG.getIntPtrConstant(i)); 4788 } 4789 } 4790 4791 return V; 4792} 4793 4794/// getVShift - Return a vector logical shift node. 4795/// 4796static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4797 unsigned NumBits, SelectionDAG &DAG, 4798 const TargetLowering &TLI, DebugLoc dl) { 4799 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4800 EVT ShVT = MVT::v2i64; 4801 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4802 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4803 return DAG.getNode(ISD::BITCAST, dl, VT, 4804 DAG.getNode(Opc, dl, ShVT, SrcOp, 4805 DAG.getConstant(NumBits, 4806 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4807} 4808 4809SDValue 4810X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4811 SelectionDAG &DAG) const { 4812 4813 // Check if the scalar load can be widened into a vector load. And if 4814 // the address is "base + cst" see if the cst can be "absorbed" into 4815 // the shuffle mask. 4816 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4817 SDValue Ptr = LD->getBasePtr(); 4818 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4819 return SDValue(); 4820 EVT PVT = LD->getValueType(0); 4821 if (PVT != MVT::i32 && PVT != MVT::f32) 4822 return SDValue(); 4823 4824 int FI = -1; 4825 int64_t Offset = 0; 4826 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4827 FI = FINode->getIndex(); 4828 Offset = 0; 4829 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4830 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4831 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4832 Offset = Ptr.getConstantOperandVal(1); 4833 Ptr = Ptr.getOperand(0); 4834 } else { 4835 return SDValue(); 4836 } 4837 4838 // FIXME: 256-bit vector instructions don't require a strict alignment, 4839 // improve this code to support it better. 4840 unsigned RequiredAlign = VT.getSizeInBits()/8; 4841 SDValue Chain = LD->getChain(); 4842 // Make sure the stack object alignment is at least 16 or 32. 4843 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4844 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4845 if (MFI->isFixedObjectIndex(FI)) { 4846 // Can't change the alignment. FIXME: It's possible to compute 4847 // the exact stack offset and reference FI + adjust offset instead. 4848 // If someone *really* cares about this. That's the way to implement it. 4849 return SDValue(); 4850 } else { 4851 MFI->setObjectAlignment(FI, RequiredAlign); 4852 } 4853 } 4854 4855 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4856 // Ptr + (Offset & ~15). 4857 if (Offset < 0) 4858 return SDValue(); 4859 if ((Offset % RequiredAlign) & 3) 4860 return SDValue(); 4861 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4862 if (StartOffset) 4863 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4864 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4865 4866 int EltNo = (Offset - StartOffset) >> 2; 4867 int NumElems = VT.getVectorNumElements(); 4868 4869 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4870 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4871 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4872 LD->getPointerInfo().getWithOffset(StartOffset), 4873 false, false, false, 0); 4874 4875 // Canonicalize it to a v4i32 or v8i32 shuffle. 4876 SmallVector<int, 8> Mask; 4877 for (int i = 0; i < NumElems; ++i) 4878 Mask.push_back(EltNo); 4879 4880 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4881 return DAG.getNode(ISD::BITCAST, dl, NVT, 4882 DAG.getVectorShuffle(CanonVT, dl, V1, 4883 DAG.getUNDEF(CanonVT),&Mask[0])); 4884 } 4885 4886 return SDValue(); 4887} 4888 4889/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4890/// vector of type 'VT', see if the elements can be replaced by a single large 4891/// load which has the same value as a build_vector whose operands are 'elts'. 4892/// 4893/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4894/// 4895/// FIXME: we'd also like to handle the case where the last elements are zero 4896/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4897/// There's even a handy isZeroNode for that purpose. 4898static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4899 DebugLoc &DL, SelectionDAG &DAG) { 4900 EVT EltVT = VT.getVectorElementType(); 4901 unsigned NumElems = Elts.size(); 4902 4903 LoadSDNode *LDBase = NULL; 4904 unsigned LastLoadedElt = -1U; 4905 4906 // For each element in the initializer, see if we've found a load or an undef. 4907 // If we don't find an initial load element, or later load elements are 4908 // non-consecutive, bail out. 4909 for (unsigned i = 0; i < NumElems; ++i) { 4910 SDValue Elt = Elts[i]; 4911 4912 if (!Elt.getNode() || 4913 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4914 return SDValue(); 4915 if (!LDBase) { 4916 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4917 return SDValue(); 4918 LDBase = cast<LoadSDNode>(Elt.getNode()); 4919 LastLoadedElt = i; 4920 continue; 4921 } 4922 if (Elt.getOpcode() == ISD::UNDEF) 4923 continue; 4924 4925 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4926 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4927 return SDValue(); 4928 LastLoadedElt = i; 4929 } 4930 4931 // If we have found an entire vector of loads and undefs, then return a large 4932 // load of the entire vector width starting at the base pointer. If we found 4933 // consecutive loads for the low half, generate a vzext_load node. 4934 if (LastLoadedElt == NumElems - 1) { 4935 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4936 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4937 LDBase->getPointerInfo(), 4938 LDBase->isVolatile(), LDBase->isNonTemporal(), 4939 LDBase->isInvariant(), 0); 4940 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4941 LDBase->getPointerInfo(), 4942 LDBase->isVolatile(), LDBase->isNonTemporal(), 4943 LDBase->isInvariant(), LDBase->getAlignment()); 4944 } else if (NumElems == 4 && LastLoadedElt == 1 && 4945 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4946 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4947 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4948 SDValue ResNode = 4949 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4950 LDBase->getPointerInfo(), 4951 LDBase->getAlignment(), 4952 false/*isVolatile*/, true/*ReadMem*/, 4953 false/*WriteMem*/); 4954 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4955 } 4956 return SDValue(); 4957} 4958 4959/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 4960/// a vbroadcast node. We support two patterns: 4961/// 1. A splat BUILD_VECTOR which uses a single scalar load. 4962/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4963/// a scalar load. 4964/// The scalar load node is returned when a pattern is found, 4965/// or SDValue() otherwise. 4966static SDValue isVectorBroadcast(SDValue &Op, bool hasAVX2) { 4967 EVT VT = Op.getValueType(); 4968 SDValue V = Op; 4969 4970 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 4971 V = V.getOperand(0); 4972 4973 //A suspected load to be broadcasted. 4974 SDValue Ld; 4975 4976 switch (V.getOpcode()) { 4977 default: 4978 // Unknown pattern found. 4979 return SDValue(); 4980 4981 case ISD::BUILD_VECTOR: { 4982 // The BUILD_VECTOR node must be a splat. 4983 if (!isSplatVector(V.getNode())) 4984 return SDValue(); 4985 4986 Ld = V.getOperand(0); 4987 4988 // The suspected load node has several users. Make sure that all 4989 // of its users are from the BUILD_VECTOR node. 4990 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4991 return SDValue(); 4992 break; 4993 } 4994 4995 case ISD::VECTOR_SHUFFLE: { 4996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4997 4998 // Shuffles must have a splat mask where the first element is 4999 // broadcasted. 5000 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 5001 return SDValue(); 5002 5003 SDValue Sc = Op.getOperand(0); 5004 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 5005 return SDValue(); 5006 5007 Ld = Sc.getOperand(0); 5008 5009 // The scalar_to_vector node and the suspected 5010 // load node must have exactly one user. 5011 if (!Sc.hasOneUse() || !Ld.hasOneUse()) 5012 return SDValue(); 5013 break; 5014 } 5015 } 5016 5017 // The scalar source must be a normal load. 5018 if (!ISD::isNormalLoad(Ld.getNode())) 5019 return SDValue(); 5020 5021 bool Is256 = VT.getSizeInBits() == 256; 5022 bool Is128 = VT.getSizeInBits() == 128; 5023 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5024 5025 if (hasAVX2) { 5026 // VBroadcast to YMM 5027 if (Is256 && (ScalarSize == 8 || ScalarSize == 16 || 5028 ScalarSize == 32 || ScalarSize == 64 )) 5029 return Ld; 5030 5031 // VBroadcast to XMM 5032 if (Is128 && (ScalarSize == 8 || ScalarSize == 32 || 5033 ScalarSize == 16 || ScalarSize == 64 )) 5034 return Ld; 5035 } 5036 5037 // VBroadcast to YMM 5038 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 5039 return Ld; 5040 5041 // VBroadcast to XMM 5042 if (Is128 && (ScalarSize == 32)) 5043 return Ld; 5044 5045 5046 // Unsupported broadcast. 5047 return SDValue(); 5048} 5049 5050SDValue 5051X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5052 DebugLoc dl = Op.getDebugLoc(); 5053 5054 EVT VT = Op.getValueType(); 5055 EVT ExtVT = VT.getVectorElementType(); 5056 unsigned NumElems = Op.getNumOperands(); 5057 5058 // Vectors containing all zeros can be matched by pxor and xorps later 5059 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5060 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5061 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5062 if (Op.getValueType() == MVT::v4i32 || 5063 Op.getValueType() == MVT::v8i32) 5064 return Op; 5065 5066 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl); 5067 } 5068 5069 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5070 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5071 // vpcmpeqd on 256-bit vectors. 5072 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5073 if (Op.getValueType() == MVT::v4i32 || 5074 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2())) 5075 return Op; 5076 5077 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl); 5078 } 5079 5080 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2()); 5081 if (Subtarget->hasAVX() && LD.getNode()) 5082 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 5083 5084 unsigned EVTBits = ExtVT.getSizeInBits(); 5085 5086 unsigned NumZero = 0; 5087 unsigned NumNonZero = 0; 5088 unsigned NonZeros = 0; 5089 bool IsAllConstants = true; 5090 SmallSet<SDValue, 8> Values; 5091 for (unsigned i = 0; i < NumElems; ++i) { 5092 SDValue Elt = Op.getOperand(i); 5093 if (Elt.getOpcode() == ISD::UNDEF) 5094 continue; 5095 Values.insert(Elt); 5096 if (Elt.getOpcode() != ISD::Constant && 5097 Elt.getOpcode() != ISD::ConstantFP) 5098 IsAllConstants = false; 5099 if (X86::isZeroNode(Elt)) 5100 NumZero++; 5101 else { 5102 NonZeros |= (1 << i); 5103 NumNonZero++; 5104 } 5105 } 5106 5107 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5108 if (NumNonZero == 0) 5109 return DAG.getUNDEF(VT); 5110 5111 // Special case for single non-zero, non-undef, element. 5112 if (NumNonZero == 1) { 5113 unsigned Idx = CountTrailingZeros_32(NonZeros); 5114 SDValue Item = Op.getOperand(Idx); 5115 5116 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5117 // the value are obviously zero, truncate the value to i32 and do the 5118 // insertion that way. Only do this if the value is non-constant or if the 5119 // value is a constant being inserted into element 0. It is cheaper to do 5120 // a constant pool load than it is to do a movd + shuffle. 5121 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5122 (!IsAllConstants || Idx == 0)) { 5123 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5124 // Handle SSE only. 5125 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5126 EVT VecVT = MVT::v4i32; 5127 unsigned VecElts = 4; 5128 5129 // Truncate the value (which may itself be a constant) to i32, and 5130 // convert it to a vector with movd (S2V+shuffle to zero extend). 5131 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5132 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5133 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5134 Subtarget->hasXMMInt(), DAG); 5135 5136 // Now we have our 32-bit value zero extended in the low element of 5137 // a vector. If Idx != 0, swizzle it into place. 5138 if (Idx != 0) { 5139 SmallVector<int, 4> Mask; 5140 Mask.push_back(Idx); 5141 for (unsigned i = 1; i != VecElts; ++i) 5142 Mask.push_back(i); 5143 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5144 DAG.getUNDEF(Item.getValueType()), 5145 &Mask[0]); 5146 } 5147 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 5148 } 5149 } 5150 5151 // If we have a constant or non-constant insertion into the low element of 5152 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5153 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5154 // depending on what the source datatype is. 5155 if (Idx == 0) { 5156 if (NumZero == 0) 5157 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5158 5159 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5160 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5161 if (VT.getSizeInBits() == 256) { 5162 EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2); 5163 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item); 5164 SDValue ZeroVec = getZeroVector(VT, true, DAG, dl); 5165 return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5166 DAG, dl); 5167 } 5168 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5169 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5170 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5171 return getShuffleVectorZeroOrUndef(Item, 0, true, 5172 Subtarget->hasXMMInt(), DAG); 5173 } 5174 5175 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5176 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5177 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5178 if (VT.getSizeInBits() == 256) { 5179 SDValue ZeroVec = getZeroVector(MVT::v8i32, true, DAG, dl); 5180 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5181 DAG, dl); 5182 } else { 5183 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5184 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5185 Subtarget->hasXMMInt(), DAG); 5186 } 5187 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5188 } 5189 } 5190 5191 // Is it a vector logical left shift? 5192 if (NumElems == 2 && Idx == 1 && 5193 X86::isZeroNode(Op.getOperand(0)) && 5194 !X86::isZeroNode(Op.getOperand(1))) { 5195 unsigned NumBits = VT.getSizeInBits(); 5196 return getVShift(true, VT, 5197 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5198 VT, Op.getOperand(1)), 5199 NumBits/2, DAG, *this, dl); 5200 } 5201 5202 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5203 return SDValue(); 5204 5205 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5206 // is a non-constant being inserted into an element other than the low one, 5207 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5208 // movd/movss) to move this into the low element, then shuffle it into 5209 // place. 5210 if (EVTBits == 32) { 5211 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5212 5213 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5214 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 5215 Subtarget->hasXMMInt(), DAG); 5216 SmallVector<int, 8> MaskVec; 5217 for (unsigned i = 0; i < NumElems; i++) 5218 MaskVec.push_back(i == Idx ? 0 : 1); 5219 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5220 } 5221 } 5222 5223 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5224 if (Values.size() == 1) { 5225 if (EVTBits == 32) { 5226 // Instead of a shuffle like this: 5227 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5228 // Check if it's possible to issue this instead. 5229 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5230 unsigned Idx = CountTrailingZeros_32(NonZeros); 5231 SDValue Item = Op.getOperand(Idx); 5232 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5233 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5234 } 5235 return SDValue(); 5236 } 5237 5238 // A vector full of immediates; various special cases are already 5239 // handled, so this is best done with a single constant-pool load. 5240 if (IsAllConstants) 5241 return SDValue(); 5242 5243 // For AVX-length vectors, build the individual 128-bit pieces and use 5244 // shuffles to put them in place. 5245 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5246 SmallVector<SDValue, 32> V; 5247 for (unsigned i = 0; i < NumElems; ++i) 5248 V.push_back(Op.getOperand(i)); 5249 5250 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5251 5252 // Build both the lower and upper subvector. 5253 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5254 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5255 NumElems/2); 5256 5257 // Recreate the wider vector with the lower and upper part. 5258 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5259 DAG.getConstant(0, MVT::i32), DAG, dl); 5260 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5261 DAG, dl); 5262 } 5263 5264 // Let legalizer expand 2-wide build_vectors. 5265 if (EVTBits == 64) { 5266 if (NumNonZero == 1) { 5267 // One half is zero or undef. 5268 unsigned Idx = CountTrailingZeros_32(NonZeros); 5269 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5270 Op.getOperand(Idx)); 5271 return getShuffleVectorZeroOrUndef(V2, Idx, true, 5272 Subtarget->hasXMMInt(), DAG); 5273 } 5274 return SDValue(); 5275 } 5276 5277 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5278 if (EVTBits == 8 && NumElems == 16) { 5279 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5280 *this); 5281 if (V.getNode()) return V; 5282 } 5283 5284 if (EVTBits == 16 && NumElems == 8) { 5285 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5286 *this); 5287 if (V.getNode()) return V; 5288 } 5289 5290 // If element VT is == 32 bits, turn it into a number of shuffles. 5291 SmallVector<SDValue, 8> V; 5292 V.resize(NumElems); 5293 if (NumElems == 4 && NumZero > 0) { 5294 for (unsigned i = 0; i < 4; ++i) { 5295 bool isZero = !(NonZeros & (1 << i)); 5296 if (isZero) 5297 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 5298 else 5299 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5300 } 5301 5302 for (unsigned i = 0; i < 2; ++i) { 5303 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5304 default: break; 5305 case 0: 5306 V[i] = V[i*2]; // Must be a zero vector. 5307 break; 5308 case 1: 5309 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5310 break; 5311 case 2: 5312 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5313 break; 5314 case 3: 5315 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5316 break; 5317 } 5318 } 5319 5320 SmallVector<int, 8> MaskVec; 5321 bool Reverse = (NonZeros & 0x3) == 2; 5322 for (unsigned i = 0; i < 2; ++i) 5323 MaskVec.push_back(Reverse ? 1-i : i); 5324 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5325 for (unsigned i = 0; i < 2; ++i) 5326 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5327 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5328 } 5329 5330 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5331 // Check for a build vector of consecutive loads. 5332 for (unsigned i = 0; i < NumElems; ++i) 5333 V[i] = Op.getOperand(i); 5334 5335 // Check for elements which are consecutive loads. 5336 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5337 if (LD.getNode()) 5338 return LD; 5339 5340 // For SSE 4.1, use insertps to put the high elements into the low element. 5341 if (getSubtarget()->hasSSE41orAVX()) { 5342 SDValue Result; 5343 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5344 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5345 else 5346 Result = DAG.getUNDEF(VT); 5347 5348 for (unsigned i = 1; i < NumElems; ++i) { 5349 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5350 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5351 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5352 } 5353 return Result; 5354 } 5355 5356 // Otherwise, expand into a number of unpckl*, start by extending each of 5357 // our (non-undef) elements to the full vector width with the element in the 5358 // bottom slot of the vector (which generates no code for SSE). 5359 for (unsigned i = 0; i < NumElems; ++i) { 5360 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5361 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5362 else 5363 V[i] = DAG.getUNDEF(VT); 5364 } 5365 5366 // Next, we iteratively mix elements, e.g. for v4f32: 5367 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5368 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5369 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5370 unsigned EltStride = NumElems >> 1; 5371 while (EltStride != 0) { 5372 for (unsigned i = 0; i < EltStride; ++i) { 5373 // If V[i+EltStride] is undef and this is the first round of mixing, 5374 // then it is safe to just drop this shuffle: V[i] is already in the 5375 // right place, the one element (since it's the first round) being 5376 // inserted as undef can be dropped. This isn't safe for successive 5377 // rounds because they will permute elements within both vectors. 5378 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5379 EltStride == NumElems/2) 5380 continue; 5381 5382 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5383 } 5384 EltStride >>= 1; 5385 } 5386 return V[0]; 5387 } 5388 return SDValue(); 5389} 5390 5391// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5392// them in a MMX register. This is better than doing a stack convert. 5393static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5394 DebugLoc dl = Op.getDebugLoc(); 5395 EVT ResVT = Op.getValueType(); 5396 5397 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5398 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5399 int Mask[2]; 5400 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5401 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5402 InVec = Op.getOperand(1); 5403 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5404 unsigned NumElts = ResVT.getVectorNumElements(); 5405 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5406 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5407 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5408 } else { 5409 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5410 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5411 Mask[0] = 0; Mask[1] = 2; 5412 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5413 } 5414 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5415} 5416 5417// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5418// to create 256-bit vectors from two other 128-bit ones. 5419static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5420 DebugLoc dl = Op.getDebugLoc(); 5421 EVT ResVT = Op.getValueType(); 5422 5423 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5424 5425 SDValue V1 = Op.getOperand(0); 5426 SDValue V2 = Op.getOperand(1); 5427 unsigned NumElems = ResVT.getVectorNumElements(); 5428 5429 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5430 DAG.getConstant(0, MVT::i32), DAG, dl); 5431 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5432 DAG, dl); 5433} 5434 5435SDValue 5436X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5437 EVT ResVT = Op.getValueType(); 5438 5439 assert(Op.getNumOperands() == 2); 5440 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5441 "Unsupported CONCAT_VECTORS for value type"); 5442 5443 // We support concatenate two MMX registers and place them in a MMX register. 5444 // This is better than doing a stack convert. 5445 if (ResVT.is128BitVector()) 5446 return LowerMMXCONCAT_VECTORS(Op, DAG); 5447 5448 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5449 // from two other 128-bit ones. 5450 return LowerAVXCONCAT_VECTORS(Op, DAG); 5451} 5452 5453// v8i16 shuffles - Prefer shuffles in the following order: 5454// 1. [all] pshuflw, pshufhw, optional move 5455// 2. [ssse3] 1 x pshufb 5456// 3. [ssse3] 2 x pshufb + 1 x por 5457// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5458SDValue 5459X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5460 SelectionDAG &DAG) const { 5461 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5462 SDValue V1 = SVOp->getOperand(0); 5463 SDValue V2 = SVOp->getOperand(1); 5464 DebugLoc dl = SVOp->getDebugLoc(); 5465 SmallVector<int, 8> MaskVals; 5466 5467 // Determine if more than 1 of the words in each of the low and high quadwords 5468 // of the result come from the same quadword of one of the two inputs. Undef 5469 // mask values count as coming from any quadword, for better codegen. 5470 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5471 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5472 BitVector InputQuads(4); 5473 for (unsigned i = 0; i < 8; ++i) { 5474 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5475 int EltIdx = SVOp->getMaskElt(i); 5476 MaskVals.push_back(EltIdx); 5477 if (EltIdx < 0) { 5478 ++Quad[0]; 5479 ++Quad[1]; 5480 ++Quad[2]; 5481 ++Quad[3]; 5482 continue; 5483 } 5484 ++Quad[EltIdx / 4]; 5485 InputQuads.set(EltIdx / 4); 5486 } 5487 5488 int BestLoQuad = -1; 5489 unsigned MaxQuad = 1; 5490 for (unsigned i = 0; i < 4; ++i) { 5491 if (LoQuad[i] > MaxQuad) { 5492 BestLoQuad = i; 5493 MaxQuad = LoQuad[i]; 5494 } 5495 } 5496 5497 int BestHiQuad = -1; 5498 MaxQuad = 1; 5499 for (unsigned i = 0; i < 4; ++i) { 5500 if (HiQuad[i] > MaxQuad) { 5501 BestHiQuad = i; 5502 MaxQuad = HiQuad[i]; 5503 } 5504 } 5505 5506 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5507 // of the two input vectors, shuffle them into one input vector so only a 5508 // single pshufb instruction is necessary. If There are more than 2 input 5509 // quads, disable the next transformation since it does not help SSSE3. 5510 bool V1Used = InputQuads[0] || InputQuads[1]; 5511 bool V2Used = InputQuads[2] || InputQuads[3]; 5512 if (Subtarget->hasSSSE3orAVX()) { 5513 if (InputQuads.count() == 2 && V1Used && V2Used) { 5514 BestLoQuad = InputQuads.find_first(); 5515 BestHiQuad = InputQuads.find_next(BestLoQuad); 5516 } 5517 if (InputQuads.count() > 2) { 5518 BestLoQuad = -1; 5519 BestHiQuad = -1; 5520 } 5521 } 5522 5523 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5524 // the shuffle mask. If a quad is scored as -1, that means that it contains 5525 // words from all 4 input quadwords. 5526 SDValue NewV; 5527 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5528 SmallVector<int, 8> MaskV; 5529 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5530 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5531 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5532 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5533 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5534 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5535 5536 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5537 // source words for the shuffle, to aid later transformations. 5538 bool AllWordsInNewV = true; 5539 bool InOrder[2] = { true, true }; 5540 for (unsigned i = 0; i != 8; ++i) { 5541 int idx = MaskVals[i]; 5542 if (idx != (int)i) 5543 InOrder[i/4] = false; 5544 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5545 continue; 5546 AllWordsInNewV = false; 5547 break; 5548 } 5549 5550 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5551 if (AllWordsInNewV) { 5552 for (int i = 0; i != 8; ++i) { 5553 int idx = MaskVals[i]; 5554 if (idx < 0) 5555 continue; 5556 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5557 if ((idx != i) && idx < 4) 5558 pshufhw = false; 5559 if ((idx != i) && idx > 3) 5560 pshuflw = false; 5561 } 5562 V1 = NewV; 5563 V2Used = false; 5564 BestLoQuad = 0; 5565 BestHiQuad = 1; 5566 } 5567 5568 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5569 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5570 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5571 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5572 unsigned TargetMask = 0; 5573 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5574 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5575 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5576 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5577 V1 = NewV.getOperand(0); 5578 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5579 } 5580 } 5581 5582 // If we have SSSE3, and all words of the result are from 1 input vector, 5583 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5584 // is present, fall back to case 4. 5585 if (Subtarget->hasSSSE3orAVX()) { 5586 SmallVector<SDValue,16> pshufbMask; 5587 5588 // If we have elements from both input vectors, set the high bit of the 5589 // shuffle mask element to zero out elements that come from V2 in the V1 5590 // mask, and elements that come from V1 in the V2 mask, so that the two 5591 // results can be OR'd together. 5592 bool TwoInputs = V1Used && V2Used; 5593 for (unsigned i = 0; i != 8; ++i) { 5594 int EltIdx = MaskVals[i] * 2; 5595 if (TwoInputs && (EltIdx >= 16)) { 5596 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5597 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5598 continue; 5599 } 5600 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5601 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5602 } 5603 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5604 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5605 DAG.getNode(ISD::BUILD_VECTOR, dl, 5606 MVT::v16i8, &pshufbMask[0], 16)); 5607 if (!TwoInputs) 5608 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5609 5610 // Calculate the shuffle mask for the second input, shuffle it, and 5611 // OR it with the first shuffled input. 5612 pshufbMask.clear(); 5613 for (unsigned i = 0; i != 8; ++i) { 5614 int EltIdx = MaskVals[i] * 2; 5615 if (EltIdx < 16) { 5616 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5617 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5618 continue; 5619 } 5620 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5621 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5622 } 5623 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5624 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5625 DAG.getNode(ISD::BUILD_VECTOR, dl, 5626 MVT::v16i8, &pshufbMask[0], 16)); 5627 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5628 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5629 } 5630 5631 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5632 // and update MaskVals with new element order. 5633 BitVector InOrder(8); 5634 if (BestLoQuad >= 0) { 5635 SmallVector<int, 8> MaskV; 5636 for (int i = 0; i != 4; ++i) { 5637 int idx = MaskVals[i]; 5638 if (idx < 0) { 5639 MaskV.push_back(-1); 5640 InOrder.set(i); 5641 } else if ((idx / 4) == BestLoQuad) { 5642 MaskV.push_back(idx & 3); 5643 InOrder.set(i); 5644 } else { 5645 MaskV.push_back(-1); 5646 } 5647 } 5648 for (unsigned i = 4; i != 8; ++i) 5649 MaskV.push_back(i); 5650 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5651 &MaskV[0]); 5652 5653 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX()) 5654 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5655 NewV.getOperand(0), 5656 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5657 DAG); 5658 } 5659 5660 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5661 // and update MaskVals with the new element order. 5662 if (BestHiQuad >= 0) { 5663 SmallVector<int, 8> MaskV; 5664 for (unsigned i = 0; i != 4; ++i) 5665 MaskV.push_back(i); 5666 for (unsigned i = 4; i != 8; ++i) { 5667 int idx = MaskVals[i]; 5668 if (idx < 0) { 5669 MaskV.push_back(-1); 5670 InOrder.set(i); 5671 } else if ((idx / 4) == BestHiQuad) { 5672 MaskV.push_back((idx & 3) + 4); 5673 InOrder.set(i); 5674 } else { 5675 MaskV.push_back(-1); 5676 } 5677 } 5678 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5679 &MaskV[0]); 5680 5681 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX()) 5682 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5683 NewV.getOperand(0), 5684 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5685 DAG); 5686 } 5687 5688 // In case BestHi & BestLo were both -1, which means each quadword has a word 5689 // from each of the four input quadwords, calculate the InOrder bitvector now 5690 // before falling through to the insert/extract cleanup. 5691 if (BestLoQuad == -1 && BestHiQuad == -1) { 5692 NewV = V1; 5693 for (int i = 0; i != 8; ++i) 5694 if (MaskVals[i] < 0 || MaskVals[i] == i) 5695 InOrder.set(i); 5696 } 5697 5698 // The other elements are put in the right place using pextrw and pinsrw. 5699 for (unsigned i = 0; i != 8; ++i) { 5700 if (InOrder[i]) 5701 continue; 5702 int EltIdx = MaskVals[i]; 5703 if (EltIdx < 0) 5704 continue; 5705 SDValue ExtOp = (EltIdx < 8) 5706 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5707 DAG.getIntPtrConstant(EltIdx)) 5708 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5709 DAG.getIntPtrConstant(EltIdx - 8)); 5710 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5711 DAG.getIntPtrConstant(i)); 5712 } 5713 return NewV; 5714} 5715 5716// v16i8 shuffles - Prefer shuffles in the following order: 5717// 1. [ssse3] 1 x pshufb 5718// 2. [ssse3] 2 x pshufb + 1 x por 5719// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5720static 5721SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5722 SelectionDAG &DAG, 5723 const X86TargetLowering &TLI) { 5724 SDValue V1 = SVOp->getOperand(0); 5725 SDValue V2 = SVOp->getOperand(1); 5726 DebugLoc dl = SVOp->getDebugLoc(); 5727 SmallVector<int, 16> MaskVals; 5728 SVOp->getMask(MaskVals); 5729 5730 // If we have SSSE3, case 1 is generated when all result bytes come from 5731 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5732 // present, fall back to case 3. 5733 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5734 bool V1Only = true; 5735 bool V2Only = true; 5736 for (unsigned i = 0; i < 16; ++i) { 5737 int EltIdx = MaskVals[i]; 5738 if (EltIdx < 0) 5739 continue; 5740 if (EltIdx < 16) 5741 V2Only = false; 5742 else 5743 V1Only = false; 5744 } 5745 5746 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5747 if (TLI.getSubtarget()->hasSSSE3orAVX()) { 5748 SmallVector<SDValue,16> pshufbMask; 5749 5750 // If all result elements are from one input vector, then only translate 5751 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5752 // 5753 // Otherwise, we have elements from both input vectors, and must zero out 5754 // elements that come from V2 in the first mask, and V1 in the second mask 5755 // so that we can OR them together. 5756 bool TwoInputs = !(V1Only || V2Only); 5757 for (unsigned i = 0; i != 16; ++i) { 5758 int EltIdx = MaskVals[i]; 5759 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5760 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5761 continue; 5762 } 5763 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5764 } 5765 // If all the elements are from V2, assign it to V1 and return after 5766 // building the first pshufb. 5767 if (V2Only) 5768 V1 = V2; 5769 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5770 DAG.getNode(ISD::BUILD_VECTOR, dl, 5771 MVT::v16i8, &pshufbMask[0], 16)); 5772 if (!TwoInputs) 5773 return V1; 5774 5775 // Calculate the shuffle mask for the second input, shuffle it, and 5776 // OR it with the first shuffled input. 5777 pshufbMask.clear(); 5778 for (unsigned i = 0; i != 16; ++i) { 5779 int EltIdx = MaskVals[i]; 5780 if (EltIdx < 16) { 5781 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5782 continue; 5783 } 5784 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5785 } 5786 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5787 DAG.getNode(ISD::BUILD_VECTOR, dl, 5788 MVT::v16i8, &pshufbMask[0], 16)); 5789 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5790 } 5791 5792 // No SSSE3 - Calculate in place words and then fix all out of place words 5793 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5794 // the 16 different words that comprise the two doublequadword input vectors. 5795 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5796 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5797 SDValue NewV = V2Only ? V2 : V1; 5798 for (int i = 0; i != 8; ++i) { 5799 int Elt0 = MaskVals[i*2]; 5800 int Elt1 = MaskVals[i*2+1]; 5801 5802 // This word of the result is all undef, skip it. 5803 if (Elt0 < 0 && Elt1 < 0) 5804 continue; 5805 5806 // This word of the result is already in the correct place, skip it. 5807 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5808 continue; 5809 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5810 continue; 5811 5812 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5813 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5814 SDValue InsElt; 5815 5816 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5817 // using a single extract together, load it and store it. 5818 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5819 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5820 DAG.getIntPtrConstant(Elt1 / 2)); 5821 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5822 DAG.getIntPtrConstant(i)); 5823 continue; 5824 } 5825 5826 // If Elt1 is defined, extract it from the appropriate source. If the 5827 // source byte is not also odd, shift the extracted word left 8 bits 5828 // otherwise clear the bottom 8 bits if we need to do an or. 5829 if (Elt1 >= 0) { 5830 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5831 DAG.getIntPtrConstant(Elt1 / 2)); 5832 if ((Elt1 & 1) == 0) 5833 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5834 DAG.getConstant(8, 5835 TLI.getShiftAmountTy(InsElt.getValueType()))); 5836 else if (Elt0 >= 0) 5837 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5838 DAG.getConstant(0xFF00, MVT::i16)); 5839 } 5840 // If Elt0 is defined, extract it from the appropriate source. If the 5841 // source byte is not also even, shift the extracted word right 8 bits. If 5842 // Elt1 was also defined, OR the extracted values together before 5843 // inserting them in the result. 5844 if (Elt0 >= 0) { 5845 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5846 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5847 if ((Elt0 & 1) != 0) 5848 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5849 DAG.getConstant(8, 5850 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5851 else if (Elt1 >= 0) 5852 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5853 DAG.getConstant(0x00FF, MVT::i16)); 5854 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5855 : InsElt0; 5856 } 5857 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5858 DAG.getIntPtrConstant(i)); 5859 } 5860 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5861} 5862 5863/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5864/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5865/// done when every pair / quad of shuffle mask elements point to elements in 5866/// the right sequence. e.g. 5867/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5868static 5869SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5870 SelectionDAG &DAG, DebugLoc dl) { 5871 EVT VT = SVOp->getValueType(0); 5872 SDValue V1 = SVOp->getOperand(0); 5873 SDValue V2 = SVOp->getOperand(1); 5874 unsigned NumElems = VT.getVectorNumElements(); 5875 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5876 EVT NewVT; 5877 switch (VT.getSimpleVT().SimpleTy) { 5878 default: assert(false && "Unexpected!"); 5879 case MVT::v4f32: NewVT = MVT::v2f64; break; 5880 case MVT::v4i32: NewVT = MVT::v2i64; break; 5881 case MVT::v8i16: NewVT = MVT::v4i32; break; 5882 case MVT::v16i8: NewVT = MVT::v4i32; break; 5883 } 5884 5885 int Scale = NumElems / NewWidth; 5886 SmallVector<int, 8> MaskVec; 5887 for (unsigned i = 0; i < NumElems; i += Scale) { 5888 int StartIdx = -1; 5889 for (int j = 0; j < Scale; ++j) { 5890 int EltIdx = SVOp->getMaskElt(i+j); 5891 if (EltIdx < 0) 5892 continue; 5893 if (StartIdx == -1) 5894 StartIdx = EltIdx - (EltIdx % Scale); 5895 if (EltIdx != StartIdx + j) 5896 return SDValue(); 5897 } 5898 if (StartIdx == -1) 5899 MaskVec.push_back(-1); 5900 else 5901 MaskVec.push_back(StartIdx / Scale); 5902 } 5903 5904 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5905 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5906 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5907} 5908 5909/// getVZextMovL - Return a zero-extending vector move low node. 5910/// 5911static SDValue getVZextMovL(EVT VT, EVT OpVT, 5912 SDValue SrcOp, SelectionDAG &DAG, 5913 const X86Subtarget *Subtarget, DebugLoc dl) { 5914 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5915 LoadSDNode *LD = NULL; 5916 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5917 LD = dyn_cast<LoadSDNode>(SrcOp); 5918 if (!LD) { 5919 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5920 // instead. 5921 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5922 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5923 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5924 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5925 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5926 // PR2108 5927 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5928 return DAG.getNode(ISD::BITCAST, dl, VT, 5929 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5930 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5931 OpVT, 5932 SrcOp.getOperand(0) 5933 .getOperand(0)))); 5934 } 5935 } 5936 } 5937 5938 return DAG.getNode(ISD::BITCAST, dl, VT, 5939 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5940 DAG.getNode(ISD::BITCAST, dl, 5941 OpVT, SrcOp))); 5942} 5943 5944/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector 5945/// shuffle node referes to only one lane in the sources. 5946static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) { 5947 EVT VT = SVOp->getValueType(0); 5948 int NumElems = VT.getVectorNumElements(); 5949 int HalfSize = NumElems/2; 5950 SmallVector<int, 16> M; 5951 SVOp->getMask(M); 5952 bool MatchA = false, MatchB = false; 5953 5954 for (int l = 0; l < NumElems*2; l += HalfSize) { 5955 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) { 5956 MatchA = true; 5957 break; 5958 } 5959 } 5960 5961 for (int l = 0; l < NumElems*2; l += HalfSize) { 5962 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) { 5963 MatchB = true; 5964 break; 5965 } 5966 } 5967 5968 return MatchA && MatchB; 5969} 5970 5971/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5972/// which could not be matched by any known target speficic shuffle 5973static SDValue 5974LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5975 if (areShuffleHalvesWithinDisjointLanes(SVOp)) { 5976 // If each half of a vector shuffle node referes to only one lane in the 5977 // source vectors, extract each used 128-bit lane and shuffle them using 5978 // 128-bit shuffles. Then, concatenate the results. Otherwise leave 5979 // the work to the legalizer. 5980 DebugLoc dl = SVOp->getDebugLoc(); 5981 EVT VT = SVOp->getValueType(0); 5982 int NumElems = VT.getVectorNumElements(); 5983 int HalfSize = NumElems/2; 5984 5985 // Extract the reference for each half 5986 int FstVecExtractIdx = 0, SndVecExtractIdx = 0; 5987 int FstVecOpNum = 0, SndVecOpNum = 0; 5988 for (int i = 0; i < HalfSize; ++i) { 5989 int Elt = SVOp->getMaskElt(i); 5990 if (SVOp->getMaskElt(i) < 0) 5991 continue; 5992 FstVecOpNum = Elt/NumElems; 5993 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5994 break; 5995 } 5996 for (int i = HalfSize; i < NumElems; ++i) { 5997 int Elt = SVOp->getMaskElt(i); 5998 if (SVOp->getMaskElt(i) < 0) 5999 continue; 6000 SndVecOpNum = Elt/NumElems; 6001 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 6002 break; 6003 } 6004 6005 // Extract the subvectors 6006 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum), 6007 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl); 6008 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum), 6009 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl); 6010 6011 // Generate 128-bit shuffles 6012 SmallVector<int, 16> MaskV1, MaskV2; 6013 for (int i = 0; i < HalfSize; ++i) { 6014 int Elt = SVOp->getMaskElt(i); 6015 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6016 } 6017 for (int i = HalfSize; i < NumElems; ++i) { 6018 int Elt = SVOp->getMaskElt(i); 6019 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6020 } 6021 6022 EVT NVT = V1.getValueType(); 6023 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]); 6024 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]); 6025 6026 // Concatenate the result back 6027 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1, 6028 DAG.getConstant(0, MVT::i32), DAG, dl); 6029 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 6030 DAG, dl); 6031 } 6032 6033 return SDValue(); 6034} 6035 6036/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6037/// 4 elements, and match them with several different shuffle types. 6038static SDValue 6039LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6040 SDValue V1 = SVOp->getOperand(0); 6041 SDValue V2 = SVOp->getOperand(1); 6042 DebugLoc dl = SVOp->getDebugLoc(); 6043 EVT VT = SVOp->getValueType(0); 6044 6045 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6046 6047 SmallVector<std::pair<int, int>, 8> Locs; 6048 Locs.resize(4); 6049 SmallVector<int, 8> Mask1(4U, -1); 6050 SmallVector<int, 8> PermMask; 6051 SVOp->getMask(PermMask); 6052 6053 unsigned NumHi = 0; 6054 unsigned NumLo = 0; 6055 for (unsigned i = 0; i != 4; ++i) { 6056 int Idx = PermMask[i]; 6057 if (Idx < 0) { 6058 Locs[i] = std::make_pair(-1, -1); 6059 } else { 6060 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6061 if (Idx < 4) { 6062 Locs[i] = std::make_pair(0, NumLo); 6063 Mask1[NumLo] = Idx; 6064 NumLo++; 6065 } else { 6066 Locs[i] = std::make_pair(1, NumHi); 6067 if (2+NumHi < 4) 6068 Mask1[2+NumHi] = Idx; 6069 NumHi++; 6070 } 6071 } 6072 } 6073 6074 if (NumLo <= 2 && NumHi <= 2) { 6075 // If no more than two elements come from either vector. This can be 6076 // implemented with two shuffles. First shuffle gather the elements. 6077 // The second shuffle, which takes the first shuffle as both of its 6078 // vector operands, put the elements into the right order. 6079 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6080 6081 SmallVector<int, 8> Mask2(4U, -1); 6082 6083 for (unsigned i = 0; i != 4; ++i) { 6084 if (Locs[i].first == -1) 6085 continue; 6086 else { 6087 unsigned Idx = (i < 2) ? 0 : 4; 6088 Idx += Locs[i].first * 2 + Locs[i].second; 6089 Mask2[i] = Idx; 6090 } 6091 } 6092 6093 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6094 } else if (NumLo == 3 || NumHi == 3) { 6095 // Otherwise, we must have three elements from one vector, call it X, and 6096 // one element from the other, call it Y. First, use a shufps to build an 6097 // intermediate vector with the one element from Y and the element from X 6098 // that will be in the same half in the final destination (the indexes don't 6099 // matter). Then, use a shufps to build the final vector, taking the half 6100 // containing the element from Y from the intermediate, and the other half 6101 // from X. 6102 if (NumHi == 3) { 6103 // Normalize it so the 3 elements come from V1. 6104 CommuteVectorShuffleMask(PermMask, 4); 6105 std::swap(V1, V2); 6106 } 6107 6108 // Find the element from V2. 6109 unsigned HiIndex; 6110 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6111 int Val = PermMask[HiIndex]; 6112 if (Val < 0) 6113 continue; 6114 if (Val >= 4) 6115 break; 6116 } 6117 6118 Mask1[0] = PermMask[HiIndex]; 6119 Mask1[1] = -1; 6120 Mask1[2] = PermMask[HiIndex^1]; 6121 Mask1[3] = -1; 6122 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6123 6124 if (HiIndex >= 2) { 6125 Mask1[0] = PermMask[0]; 6126 Mask1[1] = PermMask[1]; 6127 Mask1[2] = HiIndex & 1 ? 6 : 4; 6128 Mask1[3] = HiIndex & 1 ? 4 : 6; 6129 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6130 } else { 6131 Mask1[0] = HiIndex & 1 ? 2 : 0; 6132 Mask1[1] = HiIndex & 1 ? 0 : 2; 6133 Mask1[2] = PermMask[2]; 6134 Mask1[3] = PermMask[3]; 6135 if (Mask1[2] >= 0) 6136 Mask1[2] += 4; 6137 if (Mask1[3] >= 0) 6138 Mask1[3] += 4; 6139 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6140 } 6141 } 6142 6143 // Break it into (shuffle shuffle_hi, shuffle_lo). 6144 Locs.clear(); 6145 Locs.resize(4); 6146 SmallVector<int,8> LoMask(4U, -1); 6147 SmallVector<int,8> HiMask(4U, -1); 6148 6149 SmallVector<int,8> *MaskPtr = &LoMask; 6150 unsigned MaskIdx = 0; 6151 unsigned LoIdx = 0; 6152 unsigned HiIdx = 2; 6153 for (unsigned i = 0; i != 4; ++i) { 6154 if (i == 2) { 6155 MaskPtr = &HiMask; 6156 MaskIdx = 1; 6157 LoIdx = 0; 6158 HiIdx = 2; 6159 } 6160 int Idx = PermMask[i]; 6161 if (Idx < 0) { 6162 Locs[i] = std::make_pair(-1, -1); 6163 } else if (Idx < 4) { 6164 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6165 (*MaskPtr)[LoIdx] = Idx; 6166 LoIdx++; 6167 } else { 6168 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6169 (*MaskPtr)[HiIdx] = Idx; 6170 HiIdx++; 6171 } 6172 } 6173 6174 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6175 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6176 SmallVector<int, 8> MaskOps; 6177 for (unsigned i = 0; i != 4; ++i) { 6178 if (Locs[i].first == -1) { 6179 MaskOps.push_back(-1); 6180 } else { 6181 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6182 MaskOps.push_back(Idx); 6183 } 6184 } 6185 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6186} 6187 6188static bool MayFoldVectorLoad(SDValue V) { 6189 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6190 V = V.getOperand(0); 6191 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6192 V = V.getOperand(0); 6193 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6194 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6195 // BUILD_VECTOR (load), undef 6196 V = V.getOperand(0); 6197 if (MayFoldLoad(V)) 6198 return true; 6199 return false; 6200} 6201 6202// FIXME: the version above should always be used. Since there's 6203// a bug where several vector shuffles can't be folded because the 6204// DAG is not updated during lowering and a node claims to have two 6205// uses while it only has one, use this version, and let isel match 6206// another instruction if the load really happens to have more than 6207// one use. Remove this version after this bug get fixed. 6208// rdar://8434668, PR8156 6209static bool RelaxedMayFoldVectorLoad(SDValue V) { 6210 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6211 V = V.getOperand(0); 6212 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6213 V = V.getOperand(0); 6214 if (ISD::isNormalLoad(V.getNode())) 6215 return true; 6216 return false; 6217} 6218 6219/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6220/// a vector extract, and if both can be later optimized into a single load. 6221/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6222/// here because otherwise a target specific shuffle node is going to be 6223/// emitted for this shuffle, and the optimization not done. 6224/// FIXME: This is probably not the best approach, but fix the problem 6225/// until the right path is decided. 6226static 6227bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6228 const TargetLowering &TLI) { 6229 EVT VT = V.getValueType(); 6230 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6231 6232 // Be sure that the vector shuffle is present in a pattern like this: 6233 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6234 if (!V.hasOneUse()) 6235 return false; 6236 6237 SDNode *N = *V.getNode()->use_begin(); 6238 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6239 return false; 6240 6241 SDValue EltNo = N->getOperand(1); 6242 if (!isa<ConstantSDNode>(EltNo)) 6243 return false; 6244 6245 // If the bit convert changed the number of elements, it is unsafe 6246 // to examine the mask. 6247 bool HasShuffleIntoBitcast = false; 6248 if (V.getOpcode() == ISD::BITCAST) { 6249 EVT SrcVT = V.getOperand(0).getValueType(); 6250 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6251 return false; 6252 V = V.getOperand(0); 6253 HasShuffleIntoBitcast = true; 6254 } 6255 6256 // Select the input vector, guarding against out of range extract vector. 6257 unsigned NumElems = VT.getVectorNumElements(); 6258 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6259 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6260 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6261 6262 // Skip one more bit_convert if necessary 6263 if (V.getOpcode() == ISD::BITCAST) 6264 V = V.getOperand(0); 6265 6266 if (!ISD::isNormalLoad(V.getNode())) 6267 return false; 6268 6269 // Is the original load suitable? 6270 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6271 6272 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6273 return false; 6274 6275 if (!HasShuffleIntoBitcast) 6276 return true; 6277 6278 // If there's a bitcast before the shuffle, check if the load type and 6279 // alignment is valid. 6280 unsigned Align = LN0->getAlignment(); 6281 unsigned NewAlign = 6282 TLI.getTargetData()->getABITypeAlignment( 6283 VT.getTypeForEVT(*DAG.getContext())); 6284 6285 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6286 return false; 6287 6288 return true; 6289} 6290 6291static 6292SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6293 EVT VT = Op.getValueType(); 6294 6295 // Canonizalize to v2f64. 6296 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6297 return DAG.getNode(ISD::BITCAST, dl, VT, 6298 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6299 V1, DAG)); 6300} 6301 6302static 6303SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6304 bool HasXMMInt) { 6305 SDValue V1 = Op.getOperand(0); 6306 SDValue V2 = Op.getOperand(1); 6307 EVT VT = Op.getValueType(); 6308 6309 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6310 6311 if (HasXMMInt && VT == MVT::v2f64) 6312 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6313 6314 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6315 return DAG.getNode(ISD::BITCAST, dl, VT, 6316 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6317 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6318 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6319} 6320 6321static 6322SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6323 SDValue V1 = Op.getOperand(0); 6324 SDValue V2 = Op.getOperand(1); 6325 EVT VT = Op.getValueType(); 6326 6327 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6328 "unsupported shuffle type"); 6329 6330 if (V2.getOpcode() == ISD::UNDEF) 6331 V2 = V1; 6332 6333 // v4i32 or v4f32 6334 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6335} 6336 6337static 6338SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) { 6339 SDValue V1 = Op.getOperand(0); 6340 SDValue V2 = Op.getOperand(1); 6341 EVT VT = Op.getValueType(); 6342 unsigned NumElems = VT.getVectorNumElements(); 6343 6344 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6345 // operand of these instructions is only memory, so check if there's a 6346 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6347 // same masks. 6348 bool CanFoldLoad = false; 6349 6350 // Trivial case, when V2 comes from a load. 6351 if (MayFoldVectorLoad(V2)) 6352 CanFoldLoad = true; 6353 6354 // When V1 is a load, it can be folded later into a store in isel, example: 6355 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6356 // turns into: 6357 // (MOVLPSmr addr:$src1, VR128:$src2) 6358 // So, recognize this potential and also use MOVLPS or MOVLPD 6359 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6360 CanFoldLoad = true; 6361 6362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6363 if (CanFoldLoad) { 6364 if (HasXMMInt && NumElems == 2) 6365 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6366 6367 if (NumElems == 4) 6368 // If we don't care about the second element, procede to use movss. 6369 if (SVOp->getMaskElt(1) != -1) 6370 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6371 } 6372 6373 // movl and movlp will both match v2i64, but v2i64 is never matched by 6374 // movl earlier because we make it strict to avoid messing with the movlp load 6375 // folding logic (see the code above getMOVLP call). Match it here then, 6376 // this is horrible, but will stay like this until we move all shuffle 6377 // matching to x86 specific nodes. Note that for the 1st condition all 6378 // types are matched with movsd. 6379 if (HasXMMInt) { 6380 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6381 // as to remove this logic from here, as much as possible 6382 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6383 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6384 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6385 } 6386 6387 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6388 6389 // Invert the operand order and use SHUFPS to match it. 6390 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6391 X86::getShuffleSHUFImmediate(SVOp), DAG); 6392} 6393 6394static 6395SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6396 const TargetLowering &TLI, 6397 const X86Subtarget *Subtarget) { 6398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6399 EVT VT = Op.getValueType(); 6400 DebugLoc dl = Op.getDebugLoc(); 6401 SDValue V1 = Op.getOperand(0); 6402 SDValue V2 = Op.getOperand(1); 6403 6404 if (isZeroShuffle(SVOp)) 6405 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 6406 6407 // Handle splat operations 6408 if (SVOp->isSplat()) { 6409 unsigned NumElem = VT.getVectorNumElements(); 6410 int Size = VT.getSizeInBits(); 6411 // Special case, this is the only place now where it's allowed to return 6412 // a vector_shuffle operation without using a target specific node, because 6413 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6414 // this be moved to DAGCombine instead? 6415 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6416 return Op; 6417 6418 // Use vbroadcast whenever the splat comes from a foldable load 6419 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2()); 6420 if (Subtarget->hasAVX() && LD.getNode()) 6421 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 6422 6423 // Handle splats by matching through known shuffle masks 6424 if ((Size == 128 && NumElem <= 4) || 6425 (Size == 256 && NumElem < 8)) 6426 return SDValue(); 6427 6428 // All remaning splats are promoted to target supported vector shuffles. 6429 return PromoteSplat(SVOp, DAG); 6430 } 6431 6432 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6433 // do it! 6434 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6435 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6436 if (NewOp.getNode()) 6437 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6438 } else if ((VT == MVT::v4i32 || 6439 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) { 6440 // FIXME: Figure out a cleaner way to do this. 6441 // Try to make use of movq to zero out the top part. 6442 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6443 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6444 if (NewOp.getNode()) { 6445 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6446 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6447 DAG, Subtarget, dl); 6448 } 6449 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6450 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6451 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6452 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6453 DAG, Subtarget, dl); 6454 } 6455 } 6456 return SDValue(); 6457} 6458 6459SDValue 6460X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6461 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6462 SDValue V1 = Op.getOperand(0); 6463 SDValue V2 = Op.getOperand(1); 6464 EVT VT = Op.getValueType(); 6465 DebugLoc dl = Op.getDebugLoc(); 6466 unsigned NumElems = VT.getVectorNumElements(); 6467 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6468 bool V1IsSplat = false; 6469 bool V2IsSplat = false; 6470 bool HasXMMInt = Subtarget->hasXMMInt(); 6471 bool HasAVX = Subtarget->hasAVX(); 6472 bool HasAVX2 = Subtarget->hasAVX2(); 6473 MachineFunction &MF = DAG.getMachineFunction(); 6474 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6475 6476 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6477 6478 assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef"); 6479 6480 // Vector shuffle lowering takes 3 steps: 6481 // 6482 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6483 // narrowing and commutation of operands should be handled. 6484 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6485 // shuffle nodes. 6486 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6487 // so the shuffle can be broken into other shuffles and the legalizer can 6488 // try the lowering again. 6489 // 6490 // The general idea is that no vector_shuffle operation should be left to 6491 // be matched during isel, all of them must be converted to a target specific 6492 // node here. 6493 6494 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6495 // narrowing and commutation of operands should be handled. The actual code 6496 // doesn't include all of those, work in progress... 6497 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6498 if (NewOp.getNode()) 6499 return NewOp; 6500 6501 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6502 // unpckh_undef). Only use pshufd if speed is more important than size. 6503 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2)) 6504 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6505 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2)) 6506 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6507 6508 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() && 6509 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6510 return getMOVDDup(Op, dl, V1, DAG); 6511 6512 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6513 return getMOVHighToLow(Op, dl, DAG); 6514 6515 // Use to match splats 6516 if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef && 6517 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6518 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6519 6520 if (X86::isPSHUFDMask(SVOp)) { 6521 // The actual implementation will match the mask in the if above and then 6522 // during isel it can match several different instructions, not only pshufd 6523 // as its name says, sad but true, emulate the behavior for now... 6524 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6525 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6526 6527 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6528 6529 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6530 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6531 6532 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6533 TargetMask, DAG); 6534 } 6535 6536 // Check if this can be converted into a logical shift. 6537 bool isLeft = false; 6538 unsigned ShAmt = 0; 6539 SDValue ShVal; 6540 bool isShift = HasXMMInt && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6541 if (isShift && ShVal.hasOneUse()) { 6542 // If the shifted value has multiple uses, it may be cheaper to use 6543 // v_set0 + movlhps or movhlps, etc. 6544 EVT EltVT = VT.getVectorElementType(); 6545 ShAmt *= EltVT.getSizeInBits(); 6546 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6547 } 6548 6549 if (X86::isMOVLMask(SVOp)) { 6550 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6551 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6552 if (!X86::isMOVLPMask(SVOp)) { 6553 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6554 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6555 6556 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6557 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6558 } 6559 } 6560 6561 // FIXME: fold these into legal mask. 6562 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2)) 6563 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt); 6564 6565 if (X86::isMOVHLPSMask(SVOp)) 6566 return getMOVHighToLow(Op, dl, DAG); 6567 6568 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6569 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6570 6571 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6572 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6573 6574 if (X86::isMOVLPMask(SVOp)) 6575 return getMOVLP(Op, dl, DAG, HasXMMInt); 6576 6577 if (ShouldXformToMOVHLPS(SVOp) || 6578 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6579 return CommuteVectorShuffle(SVOp, DAG); 6580 6581 if (isShift) { 6582 // No better options. Use a vshl / vsrl. 6583 EVT EltVT = VT.getVectorElementType(); 6584 ShAmt *= EltVT.getSizeInBits(); 6585 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6586 } 6587 6588 bool Commuted = false; 6589 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6590 // 1,1,1,1 -> v8i16 though. 6591 V1IsSplat = isSplatVector(V1.getNode()); 6592 V2IsSplat = isSplatVector(V2.getNode()); 6593 6594 // Canonicalize the splat or undef, if present, to be on the RHS. 6595 if (V1IsSplat && !V2IsSplat) { 6596 Op = CommuteVectorShuffle(SVOp, DAG); 6597 SVOp = cast<ShuffleVectorSDNode>(Op); 6598 V1 = SVOp->getOperand(0); 6599 V2 = SVOp->getOperand(1); 6600 std::swap(V1IsSplat, V2IsSplat); 6601 Commuted = true; 6602 } 6603 6604 SmallVector<int, 32> M; 6605 SVOp->getMask(M); 6606 6607 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6608 // Shuffling low element of v1 into undef, just return v1. 6609 if (V2IsUndef) 6610 return V1; 6611 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6612 // the instruction selector will not match, so get a canonical MOVL with 6613 // swapped operands to undo the commute. 6614 return getMOVL(DAG, dl, VT, V2, V1); 6615 } 6616 6617 if (isUNPCKLMask(M, VT, HasAVX2)) 6618 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6619 6620 if (isUNPCKHMask(M, VT, HasAVX2)) 6621 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6622 6623 if (V2IsSplat) { 6624 // Normalize mask so all entries that point to V2 points to its first 6625 // element then try to match unpck{h|l} again. If match, return a 6626 // new vector_shuffle with the corrected mask. 6627 SDValue NewMask = NormalizeMask(SVOp, DAG); 6628 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6629 if (NSVOp != SVOp) { 6630 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) { 6631 return NewMask; 6632 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) { 6633 return NewMask; 6634 } 6635 } 6636 } 6637 6638 if (Commuted) { 6639 // Commute is back and try unpck* again. 6640 // FIXME: this seems wrong. 6641 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6642 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6643 6644 if (X86::isUNPCKLMask(NewSVOp, HasAVX2)) 6645 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG); 6646 6647 if (X86::isUNPCKHMask(NewSVOp, HasAVX2)) 6648 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG); 6649 } 6650 6651 // Normalize the node to match x86 shuffle ops if needed 6652 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) || 6653 isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true))) 6654 return CommuteVectorShuffle(SVOp, DAG); 6655 6656 // The checks below are all present in isShuffleMaskLegal, but they are 6657 // inlined here right now to enable us to directly emit target specific 6658 // nodes, and remove one by one until they don't return Op anymore. 6659 6660 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX())) 6661 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6662 getShufflePALIGNRImmediate(SVOp), 6663 DAG); 6664 6665 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6666 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6667 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6668 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6669 } 6670 6671 if (isPSHUFHWMask(M, VT)) 6672 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6673 X86::getShufflePSHUFHWImmediate(SVOp), 6674 DAG); 6675 6676 if (isPSHUFLWMask(M, VT)) 6677 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6678 X86::getShufflePSHUFLWImmediate(SVOp), 6679 DAG); 6680 6681 if (isSHUFPMask(M, VT)) 6682 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6683 X86::getShuffleSHUFImmediate(SVOp), DAG); 6684 6685 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6686 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6687 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6688 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6689 6690 //===--------------------------------------------------------------------===// 6691 // Generate target specific nodes for 128 or 256-bit shuffles only 6692 // supported in the AVX instruction set. 6693 // 6694 6695 // Handle VMOVDDUPY permutations 6696 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6697 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6698 6699 // Handle VPERMILPS/D* permutations 6700 if (isVPERMILPMask(M, VT, HasAVX)) 6701 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6702 getShuffleVPERMILPImmediate(SVOp), DAG); 6703 6704 // Handle VPERM2F128/VPERM2I128 permutations 6705 if (isVPERM2X128Mask(M, VT, HasAVX)) 6706 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6707 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6708 6709 // Handle VSHUFPS/DY permutations 6710 if (isVSHUFPYMask(M, VT, HasAVX)) 6711 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6712 getShuffleVSHUFPYImmediate(SVOp), DAG); 6713 6714 //===--------------------------------------------------------------------===// 6715 // Since no target specific shuffle was selected for this generic one, 6716 // lower it into other known shuffles. FIXME: this isn't true yet, but 6717 // this is the plan. 6718 // 6719 6720 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6721 if (VT == MVT::v8i16) { 6722 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6723 if (NewOp.getNode()) 6724 return NewOp; 6725 } 6726 6727 if (VT == MVT::v16i8) { 6728 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6729 if (NewOp.getNode()) 6730 return NewOp; 6731 } 6732 6733 // Handle all 128-bit wide vectors with 4 elements, and match them with 6734 // several different shuffle types. 6735 if (NumElems == 4 && VT.getSizeInBits() == 128) 6736 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6737 6738 // Handle general 256-bit shuffles 6739 if (VT.is256BitVector()) 6740 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6741 6742 return SDValue(); 6743} 6744 6745SDValue 6746X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6747 SelectionDAG &DAG) const { 6748 EVT VT = Op.getValueType(); 6749 DebugLoc dl = Op.getDebugLoc(); 6750 6751 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6752 return SDValue(); 6753 6754 if (VT.getSizeInBits() == 8) { 6755 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6756 Op.getOperand(0), Op.getOperand(1)); 6757 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6758 DAG.getValueType(VT)); 6759 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6760 } else if (VT.getSizeInBits() == 16) { 6761 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6762 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6763 if (Idx == 0) 6764 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6765 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6766 DAG.getNode(ISD::BITCAST, dl, 6767 MVT::v4i32, 6768 Op.getOperand(0)), 6769 Op.getOperand(1))); 6770 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6771 Op.getOperand(0), Op.getOperand(1)); 6772 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6773 DAG.getValueType(VT)); 6774 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6775 } else if (VT == MVT::f32) { 6776 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6777 // the result back to FR32 register. It's only worth matching if the 6778 // result has a single use which is a store or a bitcast to i32. And in 6779 // the case of a store, it's not worth it if the index is a constant 0, 6780 // because a MOVSSmr can be used instead, which is smaller and faster. 6781 if (!Op.hasOneUse()) 6782 return SDValue(); 6783 SDNode *User = *Op.getNode()->use_begin(); 6784 if ((User->getOpcode() != ISD::STORE || 6785 (isa<ConstantSDNode>(Op.getOperand(1)) && 6786 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6787 (User->getOpcode() != ISD::BITCAST || 6788 User->getValueType(0) != MVT::i32)) 6789 return SDValue(); 6790 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6791 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6792 Op.getOperand(0)), 6793 Op.getOperand(1)); 6794 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6795 } else if (VT == MVT::i32 || VT == MVT::i64) { 6796 // ExtractPS/pextrq works with constant index. 6797 if (isa<ConstantSDNode>(Op.getOperand(1))) 6798 return Op; 6799 } 6800 return SDValue(); 6801} 6802 6803 6804SDValue 6805X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6806 SelectionDAG &DAG) const { 6807 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6808 return SDValue(); 6809 6810 SDValue Vec = Op.getOperand(0); 6811 EVT VecVT = Vec.getValueType(); 6812 6813 // If this is a 256-bit vector result, first extract the 128-bit vector and 6814 // then extract the element from the 128-bit vector. 6815 if (VecVT.getSizeInBits() == 256) { 6816 DebugLoc dl = Op.getNode()->getDebugLoc(); 6817 unsigned NumElems = VecVT.getVectorNumElements(); 6818 SDValue Idx = Op.getOperand(1); 6819 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6820 6821 // Get the 128-bit vector. 6822 bool Upper = IdxVal >= NumElems/2; 6823 Vec = Extract128BitVector(Vec, 6824 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6825 6826 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6827 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6828 } 6829 6830 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6831 6832 if (Subtarget->hasSSE41orAVX()) { 6833 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6834 if (Res.getNode()) 6835 return Res; 6836 } 6837 6838 EVT VT = Op.getValueType(); 6839 DebugLoc dl = Op.getDebugLoc(); 6840 // TODO: handle v16i8. 6841 if (VT.getSizeInBits() == 16) { 6842 SDValue Vec = Op.getOperand(0); 6843 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6844 if (Idx == 0) 6845 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6846 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6847 DAG.getNode(ISD::BITCAST, dl, 6848 MVT::v4i32, Vec), 6849 Op.getOperand(1))); 6850 // Transform it so it match pextrw which produces a 32-bit result. 6851 EVT EltVT = MVT::i32; 6852 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6853 Op.getOperand(0), Op.getOperand(1)); 6854 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6855 DAG.getValueType(VT)); 6856 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6857 } else if (VT.getSizeInBits() == 32) { 6858 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6859 if (Idx == 0) 6860 return Op; 6861 6862 // SHUFPS the element to the lowest double word, then movss. 6863 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6864 EVT VVT = Op.getOperand(0).getValueType(); 6865 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6866 DAG.getUNDEF(VVT), Mask); 6867 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6868 DAG.getIntPtrConstant(0)); 6869 } else if (VT.getSizeInBits() == 64) { 6870 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6871 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6872 // to match extract_elt for f64. 6873 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6874 if (Idx == 0) 6875 return Op; 6876 6877 // UNPCKHPD the element to the lowest double word, then movsd. 6878 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6879 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6880 int Mask[2] = { 1, -1 }; 6881 EVT VVT = Op.getOperand(0).getValueType(); 6882 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6883 DAG.getUNDEF(VVT), Mask); 6884 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6885 DAG.getIntPtrConstant(0)); 6886 } 6887 6888 return SDValue(); 6889} 6890 6891SDValue 6892X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6893 SelectionDAG &DAG) const { 6894 EVT VT = Op.getValueType(); 6895 EVT EltVT = VT.getVectorElementType(); 6896 DebugLoc dl = Op.getDebugLoc(); 6897 6898 SDValue N0 = Op.getOperand(0); 6899 SDValue N1 = Op.getOperand(1); 6900 SDValue N2 = Op.getOperand(2); 6901 6902 if (VT.getSizeInBits() == 256) 6903 return SDValue(); 6904 6905 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6906 isa<ConstantSDNode>(N2)) { 6907 unsigned Opc; 6908 if (VT == MVT::v8i16) 6909 Opc = X86ISD::PINSRW; 6910 else if (VT == MVT::v16i8) 6911 Opc = X86ISD::PINSRB; 6912 else 6913 Opc = X86ISD::PINSRB; 6914 6915 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6916 // argument. 6917 if (N1.getValueType() != MVT::i32) 6918 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6919 if (N2.getValueType() != MVT::i32) 6920 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6921 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6922 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6923 // Bits [7:6] of the constant are the source select. This will always be 6924 // zero here. The DAG Combiner may combine an extract_elt index into these 6925 // bits. For example (insert (extract, 3), 2) could be matched by putting 6926 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6927 // Bits [5:4] of the constant are the destination select. This is the 6928 // value of the incoming immediate. 6929 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6930 // combine either bitwise AND or insert of float 0.0 to set these bits. 6931 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6932 // Create this as a scalar to vector.. 6933 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6934 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6935 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6936 isa<ConstantSDNode>(N2)) { 6937 // PINSR* works with constant index. 6938 return Op; 6939 } 6940 return SDValue(); 6941} 6942 6943SDValue 6944X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6945 EVT VT = Op.getValueType(); 6946 EVT EltVT = VT.getVectorElementType(); 6947 6948 DebugLoc dl = Op.getDebugLoc(); 6949 SDValue N0 = Op.getOperand(0); 6950 SDValue N1 = Op.getOperand(1); 6951 SDValue N2 = Op.getOperand(2); 6952 6953 // If this is a 256-bit vector result, first extract the 128-bit vector, 6954 // insert the element into the extracted half and then place it back. 6955 if (VT.getSizeInBits() == 256) { 6956 if (!isa<ConstantSDNode>(N2)) 6957 return SDValue(); 6958 6959 // Get the desired 128-bit vector half. 6960 unsigned NumElems = VT.getVectorNumElements(); 6961 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6962 bool Upper = IdxVal >= NumElems/2; 6963 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6964 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6965 6966 // Insert the element into the desired half. 6967 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6968 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6969 6970 // Insert the changed part back to the 256-bit vector 6971 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6972 } 6973 6974 if (Subtarget->hasSSE41orAVX()) 6975 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6976 6977 if (EltVT == MVT::i8) 6978 return SDValue(); 6979 6980 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6981 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6982 // as its second argument. 6983 if (N1.getValueType() != MVT::i32) 6984 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6985 if (N2.getValueType() != MVT::i32) 6986 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6987 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6988 } 6989 return SDValue(); 6990} 6991 6992SDValue 6993X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6994 LLVMContext *Context = DAG.getContext(); 6995 DebugLoc dl = Op.getDebugLoc(); 6996 EVT OpVT = Op.getValueType(); 6997 6998 // If this is a 256-bit vector result, first insert into a 128-bit 6999 // vector and then insert into the 256-bit vector. 7000 if (OpVT.getSizeInBits() > 128) { 7001 // Insert into a 128-bit vector. 7002 EVT VT128 = EVT::getVectorVT(*Context, 7003 OpVT.getVectorElementType(), 7004 OpVT.getVectorNumElements() / 2); 7005 7006 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7007 7008 // Insert the 128-bit vector. 7009 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7010 DAG.getConstant(0, MVT::i32), 7011 DAG, dl); 7012 } 7013 7014 if (Op.getValueType() == MVT::v1i64 && 7015 Op.getOperand(0).getValueType() == MVT::i64) 7016 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7017 7018 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7019 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7020 "Expected an SSE type!"); 7021 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7022 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7023} 7024 7025// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7026// a simple subregister reference or explicit instructions to grab 7027// upper bits of a vector. 7028SDValue 7029X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7030 if (Subtarget->hasAVX()) { 7031 DebugLoc dl = Op.getNode()->getDebugLoc(); 7032 SDValue Vec = Op.getNode()->getOperand(0); 7033 SDValue Idx = Op.getNode()->getOperand(1); 7034 7035 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7036 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7037 return Extract128BitVector(Vec, Idx, DAG, dl); 7038 } 7039 } 7040 return SDValue(); 7041} 7042 7043// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7044// simple superregister reference or explicit instructions to insert 7045// the upper bits of a vector. 7046SDValue 7047X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7048 if (Subtarget->hasAVX()) { 7049 DebugLoc dl = Op.getNode()->getDebugLoc(); 7050 SDValue Vec = Op.getNode()->getOperand(0); 7051 SDValue SubVec = Op.getNode()->getOperand(1); 7052 SDValue Idx = Op.getNode()->getOperand(2); 7053 7054 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7055 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7056 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7057 } 7058 } 7059 return SDValue(); 7060} 7061 7062// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7063// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7064// one of the above mentioned nodes. It has to be wrapped because otherwise 7065// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7066// be used to form addressing mode. These wrapped nodes will be selected 7067// into MOV32ri. 7068SDValue 7069X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7070 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7071 7072 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7073 // global base reg. 7074 unsigned char OpFlag = 0; 7075 unsigned WrapperKind = X86ISD::Wrapper; 7076 CodeModel::Model M = getTargetMachine().getCodeModel(); 7077 7078 if (Subtarget->isPICStyleRIPRel() && 7079 (M == CodeModel::Small || M == CodeModel::Kernel)) 7080 WrapperKind = X86ISD::WrapperRIP; 7081 else if (Subtarget->isPICStyleGOT()) 7082 OpFlag = X86II::MO_GOTOFF; 7083 else if (Subtarget->isPICStyleStubPIC()) 7084 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7085 7086 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7087 CP->getAlignment(), 7088 CP->getOffset(), OpFlag); 7089 DebugLoc DL = CP->getDebugLoc(); 7090 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7091 // With PIC, the address is actually $g + Offset. 7092 if (OpFlag) { 7093 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7094 DAG.getNode(X86ISD::GlobalBaseReg, 7095 DebugLoc(), getPointerTy()), 7096 Result); 7097 } 7098 7099 return Result; 7100} 7101 7102SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7103 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7104 7105 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7106 // global base reg. 7107 unsigned char OpFlag = 0; 7108 unsigned WrapperKind = X86ISD::Wrapper; 7109 CodeModel::Model M = getTargetMachine().getCodeModel(); 7110 7111 if (Subtarget->isPICStyleRIPRel() && 7112 (M == CodeModel::Small || M == CodeModel::Kernel)) 7113 WrapperKind = X86ISD::WrapperRIP; 7114 else if (Subtarget->isPICStyleGOT()) 7115 OpFlag = X86II::MO_GOTOFF; 7116 else if (Subtarget->isPICStyleStubPIC()) 7117 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7118 7119 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7120 OpFlag); 7121 DebugLoc DL = JT->getDebugLoc(); 7122 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7123 7124 // With PIC, the address is actually $g + Offset. 7125 if (OpFlag) 7126 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7127 DAG.getNode(X86ISD::GlobalBaseReg, 7128 DebugLoc(), getPointerTy()), 7129 Result); 7130 7131 return Result; 7132} 7133 7134SDValue 7135X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7136 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7137 7138 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7139 // global base reg. 7140 unsigned char OpFlag = 0; 7141 unsigned WrapperKind = X86ISD::Wrapper; 7142 CodeModel::Model M = getTargetMachine().getCodeModel(); 7143 7144 if (Subtarget->isPICStyleRIPRel() && 7145 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7146 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7147 OpFlag = X86II::MO_GOTPCREL; 7148 WrapperKind = X86ISD::WrapperRIP; 7149 } else if (Subtarget->isPICStyleGOT()) { 7150 OpFlag = X86II::MO_GOT; 7151 } else if (Subtarget->isPICStyleStubPIC()) { 7152 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7153 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7154 OpFlag = X86II::MO_DARWIN_NONLAZY; 7155 } 7156 7157 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7158 7159 DebugLoc DL = Op.getDebugLoc(); 7160 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7161 7162 7163 // With PIC, the address is actually $g + Offset. 7164 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7165 !Subtarget->is64Bit()) { 7166 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7167 DAG.getNode(X86ISD::GlobalBaseReg, 7168 DebugLoc(), getPointerTy()), 7169 Result); 7170 } 7171 7172 // For symbols that require a load from a stub to get the address, emit the 7173 // load. 7174 if (isGlobalStubReference(OpFlag)) 7175 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7176 MachinePointerInfo::getGOT(), false, false, false, 0); 7177 7178 return Result; 7179} 7180 7181SDValue 7182X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7183 // Create the TargetBlockAddressAddress node. 7184 unsigned char OpFlags = 7185 Subtarget->ClassifyBlockAddressReference(); 7186 CodeModel::Model M = getTargetMachine().getCodeModel(); 7187 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7188 DebugLoc dl = Op.getDebugLoc(); 7189 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7190 /*isTarget=*/true, OpFlags); 7191 7192 if (Subtarget->isPICStyleRIPRel() && 7193 (M == CodeModel::Small || M == CodeModel::Kernel)) 7194 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7195 else 7196 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7197 7198 // With PIC, the address is actually $g + Offset. 7199 if (isGlobalRelativeToPICBase(OpFlags)) { 7200 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7201 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7202 Result); 7203 } 7204 7205 return Result; 7206} 7207 7208SDValue 7209X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7210 int64_t Offset, 7211 SelectionDAG &DAG) const { 7212 // Create the TargetGlobalAddress node, folding in the constant 7213 // offset if it is legal. 7214 unsigned char OpFlags = 7215 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7216 CodeModel::Model M = getTargetMachine().getCodeModel(); 7217 SDValue Result; 7218 if (OpFlags == X86II::MO_NO_FLAG && 7219 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7220 // A direct static reference to a global. 7221 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7222 Offset = 0; 7223 } else { 7224 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7225 } 7226 7227 if (Subtarget->isPICStyleRIPRel() && 7228 (M == CodeModel::Small || M == CodeModel::Kernel)) 7229 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7230 else 7231 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7232 7233 // With PIC, the address is actually $g + Offset. 7234 if (isGlobalRelativeToPICBase(OpFlags)) { 7235 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7236 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7237 Result); 7238 } 7239 7240 // For globals that require a load from a stub to get the address, emit the 7241 // load. 7242 if (isGlobalStubReference(OpFlags)) 7243 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7244 MachinePointerInfo::getGOT(), false, false, false, 0); 7245 7246 // If there was a non-zero offset that we didn't fold, create an explicit 7247 // addition for it. 7248 if (Offset != 0) 7249 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7250 DAG.getConstant(Offset, getPointerTy())); 7251 7252 return Result; 7253} 7254 7255SDValue 7256X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7257 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7258 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7259 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7260} 7261 7262static SDValue 7263GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7264 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7265 unsigned char OperandFlags) { 7266 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7267 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7268 DebugLoc dl = GA->getDebugLoc(); 7269 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7270 GA->getValueType(0), 7271 GA->getOffset(), 7272 OperandFlags); 7273 if (InFlag) { 7274 SDValue Ops[] = { Chain, TGA, *InFlag }; 7275 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7276 } else { 7277 SDValue Ops[] = { Chain, TGA }; 7278 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7279 } 7280 7281 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7282 MFI->setAdjustsStack(true); 7283 7284 SDValue Flag = Chain.getValue(1); 7285 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7286} 7287 7288// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7289static SDValue 7290LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7291 const EVT PtrVT) { 7292 SDValue InFlag; 7293 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7294 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7295 DAG.getNode(X86ISD::GlobalBaseReg, 7296 DebugLoc(), PtrVT), InFlag); 7297 InFlag = Chain.getValue(1); 7298 7299 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7300} 7301 7302// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7303static SDValue 7304LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7305 const EVT PtrVT) { 7306 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7307 X86::RAX, X86II::MO_TLSGD); 7308} 7309 7310// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7311// "local exec" model. 7312static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7313 const EVT PtrVT, TLSModel::Model model, 7314 bool is64Bit) { 7315 DebugLoc dl = GA->getDebugLoc(); 7316 7317 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7318 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7319 is64Bit ? 257 : 256)); 7320 7321 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7322 DAG.getIntPtrConstant(0), 7323 MachinePointerInfo(Ptr), 7324 false, false, false, 0); 7325 7326 unsigned char OperandFlags = 0; 7327 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7328 // initialexec. 7329 unsigned WrapperKind = X86ISD::Wrapper; 7330 if (model == TLSModel::LocalExec) { 7331 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7332 } else if (is64Bit) { 7333 assert(model == TLSModel::InitialExec); 7334 OperandFlags = X86II::MO_GOTTPOFF; 7335 WrapperKind = X86ISD::WrapperRIP; 7336 } else { 7337 assert(model == TLSModel::InitialExec); 7338 OperandFlags = X86II::MO_INDNTPOFF; 7339 } 7340 7341 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7342 // exec) 7343 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7344 GA->getValueType(0), 7345 GA->getOffset(), OperandFlags); 7346 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7347 7348 if (model == TLSModel::InitialExec) 7349 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7350 MachinePointerInfo::getGOT(), false, false, false, 0); 7351 7352 // The address of the thread local variable is the add of the thread 7353 // pointer with the offset of the variable. 7354 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7355} 7356 7357SDValue 7358X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7359 7360 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7361 const GlobalValue *GV = GA->getGlobal(); 7362 7363 if (Subtarget->isTargetELF()) { 7364 // TODO: implement the "local dynamic" model 7365 // TODO: implement the "initial exec"model for pic executables 7366 7367 // If GV is an alias then use the aliasee for determining 7368 // thread-localness. 7369 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7370 GV = GA->resolveAliasedGlobal(false); 7371 7372 TLSModel::Model model 7373 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7374 7375 switch (model) { 7376 case TLSModel::GeneralDynamic: 7377 case TLSModel::LocalDynamic: // not implemented 7378 if (Subtarget->is64Bit()) 7379 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7380 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7381 7382 case TLSModel::InitialExec: 7383 case TLSModel::LocalExec: 7384 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7385 Subtarget->is64Bit()); 7386 } 7387 } else if (Subtarget->isTargetDarwin()) { 7388 // Darwin only has one model of TLS. Lower to that. 7389 unsigned char OpFlag = 0; 7390 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7391 X86ISD::WrapperRIP : X86ISD::Wrapper; 7392 7393 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7394 // global base reg. 7395 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7396 !Subtarget->is64Bit(); 7397 if (PIC32) 7398 OpFlag = X86II::MO_TLVP_PIC_BASE; 7399 else 7400 OpFlag = X86II::MO_TLVP; 7401 DebugLoc DL = Op.getDebugLoc(); 7402 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7403 GA->getValueType(0), 7404 GA->getOffset(), OpFlag); 7405 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7406 7407 // With PIC32, the address is actually $g + Offset. 7408 if (PIC32) 7409 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7410 DAG.getNode(X86ISD::GlobalBaseReg, 7411 DebugLoc(), getPointerTy()), 7412 Offset); 7413 7414 // Lowering the machine isd will make sure everything is in the right 7415 // location. 7416 SDValue Chain = DAG.getEntryNode(); 7417 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7418 SDValue Args[] = { Chain, Offset }; 7419 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7420 7421 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7422 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7423 MFI->setAdjustsStack(true); 7424 7425 // And our return value (tls address) is in the standard call return value 7426 // location. 7427 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7428 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7429 Chain.getValue(1)); 7430 } 7431 7432 assert(false && 7433 "TLS not implemented for this target."); 7434 7435 llvm_unreachable("Unreachable"); 7436 return SDValue(); 7437} 7438 7439 7440/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7441/// and take a 2 x i32 value to shift plus a shift amount. 7442SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7443 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7444 EVT VT = Op.getValueType(); 7445 unsigned VTBits = VT.getSizeInBits(); 7446 DebugLoc dl = Op.getDebugLoc(); 7447 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7448 SDValue ShOpLo = Op.getOperand(0); 7449 SDValue ShOpHi = Op.getOperand(1); 7450 SDValue ShAmt = Op.getOperand(2); 7451 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7452 DAG.getConstant(VTBits - 1, MVT::i8)) 7453 : DAG.getConstant(0, VT); 7454 7455 SDValue Tmp2, Tmp3; 7456 if (Op.getOpcode() == ISD::SHL_PARTS) { 7457 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7458 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7459 } else { 7460 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7461 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7462 } 7463 7464 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7465 DAG.getConstant(VTBits, MVT::i8)); 7466 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7467 AndNode, DAG.getConstant(0, MVT::i8)); 7468 7469 SDValue Hi, Lo; 7470 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7471 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7472 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7473 7474 if (Op.getOpcode() == ISD::SHL_PARTS) { 7475 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7476 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7477 } else { 7478 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7479 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7480 } 7481 7482 SDValue Ops[2] = { Lo, Hi }; 7483 return DAG.getMergeValues(Ops, 2, dl); 7484} 7485 7486SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7487 SelectionDAG &DAG) const { 7488 EVT SrcVT = Op.getOperand(0).getValueType(); 7489 7490 if (SrcVT.isVector()) 7491 return SDValue(); 7492 7493 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7494 "Unknown SINT_TO_FP to lower!"); 7495 7496 // These are really Legal; return the operand so the caller accepts it as 7497 // Legal. 7498 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7499 return Op; 7500 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7501 Subtarget->is64Bit()) { 7502 return Op; 7503 } 7504 7505 DebugLoc dl = Op.getDebugLoc(); 7506 unsigned Size = SrcVT.getSizeInBits()/8; 7507 MachineFunction &MF = DAG.getMachineFunction(); 7508 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7509 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7510 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7511 StackSlot, 7512 MachinePointerInfo::getFixedStack(SSFI), 7513 false, false, 0); 7514 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7515} 7516 7517SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7518 SDValue StackSlot, 7519 SelectionDAG &DAG) const { 7520 // Build the FILD 7521 DebugLoc DL = Op.getDebugLoc(); 7522 SDVTList Tys; 7523 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7524 if (useSSE) 7525 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7526 else 7527 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7528 7529 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7530 7531 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7532 MachineMemOperand *MMO; 7533 if (FI) { 7534 int SSFI = FI->getIndex(); 7535 MMO = 7536 DAG.getMachineFunction() 7537 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7538 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7539 } else { 7540 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7541 StackSlot = StackSlot.getOperand(1); 7542 } 7543 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7544 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7545 X86ISD::FILD, DL, 7546 Tys, Ops, array_lengthof(Ops), 7547 SrcVT, MMO); 7548 7549 if (useSSE) { 7550 Chain = Result.getValue(1); 7551 SDValue InFlag = Result.getValue(2); 7552 7553 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7554 // shouldn't be necessary except that RFP cannot be live across 7555 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7556 MachineFunction &MF = DAG.getMachineFunction(); 7557 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7558 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7559 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7560 Tys = DAG.getVTList(MVT::Other); 7561 SDValue Ops[] = { 7562 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7563 }; 7564 MachineMemOperand *MMO = 7565 DAG.getMachineFunction() 7566 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7567 MachineMemOperand::MOStore, SSFISize, SSFISize); 7568 7569 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7570 Ops, array_lengthof(Ops), 7571 Op.getValueType(), MMO); 7572 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7573 MachinePointerInfo::getFixedStack(SSFI), 7574 false, false, false, 0); 7575 } 7576 7577 return Result; 7578} 7579 7580// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7581SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7582 SelectionDAG &DAG) const { 7583 // This algorithm is not obvious. Here it is what we're trying to output: 7584 /* 7585 movq %rax, %xmm0 7586 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7587 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7588 #ifdef __SSE3__ 7589 haddpd %xmm0, %xmm0 7590 #else 7591 pshufd $0x4e, %xmm0, %xmm1 7592 addpd %xmm1, %xmm0 7593 #endif 7594 */ 7595 7596 DebugLoc dl = Op.getDebugLoc(); 7597 LLVMContext *Context = DAG.getContext(); 7598 7599 // Build some magic constants. 7600 SmallVector<Constant*,4> CV0; 7601 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7602 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7603 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7604 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7605 Constant *C0 = ConstantVector::get(CV0); 7606 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7607 7608 SmallVector<Constant*,2> CV1; 7609 CV1.push_back( 7610 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7611 CV1.push_back( 7612 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7613 Constant *C1 = ConstantVector::get(CV1); 7614 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7615 7616 // Load the 64-bit value into an XMM register. 7617 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7618 Op.getOperand(0)); 7619 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7620 MachinePointerInfo::getConstantPool(), 7621 false, false, false, 16); 7622 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7623 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7624 CLod0); 7625 7626 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7627 MachinePointerInfo::getConstantPool(), 7628 false, false, false, 16); 7629 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7630 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7631 SDValue Result; 7632 7633 if (Subtarget->hasSSE3()) { 7634 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7635 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7636 } else { 7637 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7638 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7639 S2F, 0x4E, DAG); 7640 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7641 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7642 Sub); 7643 } 7644 7645 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7646 DAG.getIntPtrConstant(0)); 7647} 7648 7649// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7650SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7651 SelectionDAG &DAG) const { 7652 DebugLoc dl = Op.getDebugLoc(); 7653 // FP constant to bias correct the final result. 7654 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7655 MVT::f64); 7656 7657 // Load the 32-bit value into an XMM register. 7658 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7659 Op.getOperand(0)); 7660 7661 // Zero out the upper parts of the register. 7662 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(), 7663 DAG); 7664 7665 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7666 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7667 DAG.getIntPtrConstant(0)); 7668 7669 // Or the load with the bias. 7670 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7671 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7672 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7673 MVT::v2f64, Load)), 7674 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7675 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7676 MVT::v2f64, Bias))); 7677 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7678 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7679 DAG.getIntPtrConstant(0)); 7680 7681 // Subtract the bias. 7682 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7683 7684 // Handle final rounding. 7685 EVT DestVT = Op.getValueType(); 7686 7687 if (DestVT.bitsLT(MVT::f64)) { 7688 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7689 DAG.getIntPtrConstant(0)); 7690 } else if (DestVT.bitsGT(MVT::f64)) { 7691 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7692 } 7693 7694 // Handle final rounding. 7695 return Sub; 7696} 7697 7698SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7699 SelectionDAG &DAG) const { 7700 SDValue N0 = Op.getOperand(0); 7701 DebugLoc dl = Op.getDebugLoc(); 7702 7703 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7704 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7705 // the optimization here. 7706 if (DAG.SignBitIsZero(N0)) 7707 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7708 7709 EVT SrcVT = N0.getValueType(); 7710 EVT DstVT = Op.getValueType(); 7711 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7712 return LowerUINT_TO_FP_i64(Op, DAG); 7713 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7714 return LowerUINT_TO_FP_i32(Op, DAG); 7715 else if (SrcVT == MVT::i64 && DstVT == MVT::f32) 7716 return SDValue(); 7717 7718 // Make a 64-bit buffer, and use it to build an FILD. 7719 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7720 if (SrcVT == MVT::i32) { 7721 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7722 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7723 getPointerTy(), StackSlot, WordOff); 7724 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7725 StackSlot, MachinePointerInfo(), 7726 false, false, 0); 7727 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7728 OffsetSlot, MachinePointerInfo(), 7729 false, false, 0); 7730 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7731 return Fild; 7732 } 7733 7734 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7735 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7736 StackSlot, MachinePointerInfo(), 7737 false, false, 0); 7738 // For i64 source, we need to add the appropriate power of 2 if the input 7739 // was negative. This is the same as the optimization in 7740 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7741 // we must be careful to do the computation in x87 extended precision, not 7742 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7743 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7744 MachineMemOperand *MMO = 7745 DAG.getMachineFunction() 7746 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7747 MachineMemOperand::MOLoad, 8, 8); 7748 7749 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7750 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7751 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7752 MVT::i64, MMO); 7753 7754 APInt FF(32, 0x5F800000ULL); 7755 7756 // Check whether the sign bit is set. 7757 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7758 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7759 ISD::SETLT); 7760 7761 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7762 SDValue FudgePtr = DAG.getConstantPool( 7763 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7764 getPointerTy()); 7765 7766 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7767 SDValue Zero = DAG.getIntPtrConstant(0); 7768 SDValue Four = DAG.getIntPtrConstant(4); 7769 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7770 Zero, Four); 7771 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7772 7773 // Load the value out, extending it from f32 to f80. 7774 // FIXME: Avoid the extend by constructing the right constant pool? 7775 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7776 FudgePtr, MachinePointerInfo::getConstantPool(), 7777 MVT::f32, false, false, 4); 7778 // Extend everything to 80 bits to force it to be done on x87. 7779 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7780 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7781} 7782 7783std::pair<SDValue,SDValue> X86TargetLowering:: 7784FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7785 DebugLoc DL = Op.getDebugLoc(); 7786 7787 EVT DstTy = Op.getValueType(); 7788 7789 if (!IsSigned) { 7790 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7791 DstTy = MVT::i64; 7792 } 7793 7794 assert(DstTy.getSimpleVT() <= MVT::i64 && 7795 DstTy.getSimpleVT() >= MVT::i16 && 7796 "Unknown FP_TO_SINT to lower!"); 7797 7798 // These are really Legal. 7799 if (DstTy == MVT::i32 && 7800 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7801 return std::make_pair(SDValue(), SDValue()); 7802 if (Subtarget->is64Bit() && 7803 DstTy == MVT::i64 && 7804 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7805 return std::make_pair(SDValue(), SDValue()); 7806 7807 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7808 // stack slot. 7809 MachineFunction &MF = DAG.getMachineFunction(); 7810 unsigned MemSize = DstTy.getSizeInBits()/8; 7811 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7812 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7813 7814 7815 7816 unsigned Opc; 7817 switch (DstTy.getSimpleVT().SimpleTy) { 7818 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7819 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7820 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7821 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7822 } 7823 7824 SDValue Chain = DAG.getEntryNode(); 7825 SDValue Value = Op.getOperand(0); 7826 EVT TheVT = Op.getOperand(0).getValueType(); 7827 if (isScalarFPTypeInSSEReg(TheVT)) { 7828 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7829 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7830 MachinePointerInfo::getFixedStack(SSFI), 7831 false, false, 0); 7832 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7833 SDValue Ops[] = { 7834 Chain, StackSlot, DAG.getValueType(TheVT) 7835 }; 7836 7837 MachineMemOperand *MMO = 7838 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7839 MachineMemOperand::MOLoad, MemSize, MemSize); 7840 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7841 DstTy, MMO); 7842 Chain = Value.getValue(1); 7843 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7844 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7845 } 7846 7847 MachineMemOperand *MMO = 7848 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7849 MachineMemOperand::MOStore, MemSize, MemSize); 7850 7851 // Build the FP_TO_INT*_IN_MEM 7852 SDValue Ops[] = { Chain, Value, StackSlot }; 7853 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7854 Ops, 3, DstTy, MMO); 7855 7856 return std::make_pair(FIST, StackSlot); 7857} 7858 7859SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7860 SelectionDAG &DAG) const { 7861 if (Op.getValueType().isVector()) 7862 return SDValue(); 7863 7864 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7865 SDValue FIST = Vals.first, StackSlot = Vals.second; 7866 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7867 if (FIST.getNode() == 0) return Op; 7868 7869 // Load the result. 7870 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7871 FIST, StackSlot, MachinePointerInfo(), 7872 false, false, false, 0); 7873} 7874 7875SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7876 SelectionDAG &DAG) const { 7877 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7878 SDValue FIST = Vals.first, StackSlot = Vals.second; 7879 assert(FIST.getNode() && "Unexpected failure"); 7880 7881 // Load the result. 7882 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7883 FIST, StackSlot, MachinePointerInfo(), 7884 false, false, false, 0); 7885} 7886 7887SDValue X86TargetLowering::LowerFABS(SDValue Op, 7888 SelectionDAG &DAG) const { 7889 LLVMContext *Context = DAG.getContext(); 7890 DebugLoc dl = Op.getDebugLoc(); 7891 EVT VT = Op.getValueType(); 7892 EVT EltVT = VT; 7893 if (VT.isVector()) 7894 EltVT = VT.getVectorElementType(); 7895 SmallVector<Constant*,4> CV; 7896 if (EltVT == MVT::f64) { 7897 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 7898 CV.assign(2, C); 7899 } else { 7900 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 7901 CV.assign(4, C); 7902 } 7903 Constant *C = ConstantVector::get(CV); 7904 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7905 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7906 MachinePointerInfo::getConstantPool(), 7907 false, false, false, 16); 7908 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7909} 7910 7911SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7912 LLVMContext *Context = DAG.getContext(); 7913 DebugLoc dl = Op.getDebugLoc(); 7914 EVT VT = Op.getValueType(); 7915 EVT EltVT = VT; 7916 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7917 if (VT.isVector()) { 7918 EltVT = VT.getVectorElementType(); 7919 NumElts = VT.getVectorNumElements(); 7920 } 7921 SmallVector<Constant*,8> CV; 7922 if (EltVT == MVT::f64) { 7923 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7924 CV.assign(NumElts, C); 7925 } else { 7926 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7927 CV.assign(NumElts, C); 7928 } 7929 Constant *C = ConstantVector::get(CV); 7930 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7931 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7932 MachinePointerInfo::getConstantPool(), 7933 false, false, false, 16); 7934 if (VT.isVector()) { 7935 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7936 return DAG.getNode(ISD::BITCAST, dl, VT, 7937 DAG.getNode(ISD::XOR, dl, XORVT, 7938 DAG.getNode(ISD::BITCAST, dl, XORVT, 7939 Op.getOperand(0)), 7940 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7941 } else { 7942 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7943 } 7944} 7945 7946SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7947 LLVMContext *Context = DAG.getContext(); 7948 SDValue Op0 = Op.getOperand(0); 7949 SDValue Op1 = Op.getOperand(1); 7950 DebugLoc dl = Op.getDebugLoc(); 7951 EVT VT = Op.getValueType(); 7952 EVT SrcVT = Op1.getValueType(); 7953 7954 // If second operand is smaller, extend it first. 7955 if (SrcVT.bitsLT(VT)) { 7956 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7957 SrcVT = VT; 7958 } 7959 // And if it is bigger, shrink it first. 7960 if (SrcVT.bitsGT(VT)) { 7961 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7962 SrcVT = VT; 7963 } 7964 7965 // At this point the operands and the result should have the same 7966 // type, and that won't be f80 since that is not custom lowered. 7967 7968 // First get the sign bit of second operand. 7969 SmallVector<Constant*,4> CV; 7970 if (SrcVT == MVT::f64) { 7971 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7972 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7973 } else { 7974 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7975 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7976 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7977 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7978 } 7979 Constant *C = ConstantVector::get(CV); 7980 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7981 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7982 MachinePointerInfo::getConstantPool(), 7983 false, false, false, 16); 7984 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7985 7986 // Shift sign bit right or left if the two operands have different types. 7987 if (SrcVT.bitsGT(VT)) { 7988 // Op0 is MVT::f32, Op1 is MVT::f64. 7989 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7990 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7991 DAG.getConstant(32, MVT::i32)); 7992 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7993 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7994 DAG.getIntPtrConstant(0)); 7995 } 7996 7997 // Clear first operand sign bit. 7998 CV.clear(); 7999 if (VT == MVT::f64) { 8000 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8001 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8002 } else { 8003 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8005 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8007 } 8008 C = ConstantVector::get(CV); 8009 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8010 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8011 MachinePointerInfo::getConstantPool(), 8012 false, false, false, 16); 8013 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8014 8015 // Or the value with the sign bit. 8016 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8017} 8018 8019SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8020 SDValue N0 = Op.getOperand(0); 8021 DebugLoc dl = Op.getDebugLoc(); 8022 EVT VT = Op.getValueType(); 8023 8024 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8025 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8026 DAG.getConstant(1, VT)); 8027 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8028} 8029 8030/// Emit nodes that will be selected as "test Op0,Op0", or something 8031/// equivalent. 8032SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8033 SelectionDAG &DAG) const { 8034 DebugLoc dl = Op.getDebugLoc(); 8035 8036 // CF and OF aren't always set the way we want. Determine which 8037 // of these we need. 8038 bool NeedCF = false; 8039 bool NeedOF = false; 8040 switch (X86CC) { 8041 default: break; 8042 case X86::COND_A: case X86::COND_AE: 8043 case X86::COND_B: case X86::COND_BE: 8044 NeedCF = true; 8045 break; 8046 case X86::COND_G: case X86::COND_GE: 8047 case X86::COND_L: case X86::COND_LE: 8048 case X86::COND_O: case X86::COND_NO: 8049 NeedOF = true; 8050 break; 8051 } 8052 8053 // See if we can use the EFLAGS value from the operand instead of 8054 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8055 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8056 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8057 // Emit a CMP with 0, which is the TEST pattern. 8058 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8059 DAG.getConstant(0, Op.getValueType())); 8060 8061 unsigned Opcode = 0; 8062 unsigned NumOperands = 0; 8063 switch (Op.getNode()->getOpcode()) { 8064 case ISD::ADD: 8065 // Due to an isel shortcoming, be conservative if this add is likely to be 8066 // selected as part of a load-modify-store instruction. When the root node 8067 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8068 // uses of other nodes in the match, such as the ADD in this case. This 8069 // leads to the ADD being left around and reselected, with the result being 8070 // two adds in the output. Alas, even if none our users are stores, that 8071 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8072 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8073 // climbing the DAG back to the root, and it doesn't seem to be worth the 8074 // effort. 8075 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8076 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8077 if (UI->getOpcode() != ISD::CopyToReg && 8078 UI->getOpcode() != ISD::SETCC && 8079 UI->getOpcode() != ISD::STORE) 8080 goto default_case; 8081 8082 if (ConstantSDNode *C = 8083 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8084 // An add of one will be selected as an INC. 8085 if (C->getAPIntValue() == 1) { 8086 Opcode = X86ISD::INC; 8087 NumOperands = 1; 8088 break; 8089 } 8090 8091 // An add of negative one (subtract of one) will be selected as a DEC. 8092 if (C->getAPIntValue().isAllOnesValue()) { 8093 Opcode = X86ISD::DEC; 8094 NumOperands = 1; 8095 break; 8096 } 8097 } 8098 8099 // Otherwise use a regular EFLAGS-setting add. 8100 Opcode = X86ISD::ADD; 8101 NumOperands = 2; 8102 break; 8103 case ISD::AND: { 8104 // If the primary and result isn't used, don't bother using X86ISD::AND, 8105 // because a TEST instruction will be better. 8106 bool NonFlagUse = false; 8107 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8108 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8109 SDNode *User = *UI; 8110 unsigned UOpNo = UI.getOperandNo(); 8111 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8112 // Look pass truncate. 8113 UOpNo = User->use_begin().getOperandNo(); 8114 User = *User->use_begin(); 8115 } 8116 8117 if (User->getOpcode() != ISD::BRCOND && 8118 User->getOpcode() != ISD::SETCC && 8119 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8120 NonFlagUse = true; 8121 break; 8122 } 8123 } 8124 8125 if (!NonFlagUse) 8126 break; 8127 } 8128 // FALL THROUGH 8129 case ISD::SUB: 8130 case ISD::OR: 8131 case ISD::XOR: 8132 // Due to the ISEL shortcoming noted above, be conservative if this op is 8133 // likely to be selected as part of a load-modify-store instruction. 8134 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8135 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8136 if (UI->getOpcode() == ISD::STORE) 8137 goto default_case; 8138 8139 // Otherwise use a regular EFLAGS-setting instruction. 8140 switch (Op.getNode()->getOpcode()) { 8141 default: llvm_unreachable("unexpected operator!"); 8142 case ISD::SUB: Opcode = X86ISD::SUB; break; 8143 case ISD::OR: Opcode = X86ISD::OR; break; 8144 case ISD::XOR: Opcode = X86ISD::XOR; break; 8145 case ISD::AND: Opcode = X86ISD::AND; break; 8146 } 8147 8148 NumOperands = 2; 8149 break; 8150 case X86ISD::ADD: 8151 case X86ISD::SUB: 8152 case X86ISD::INC: 8153 case X86ISD::DEC: 8154 case X86ISD::OR: 8155 case X86ISD::XOR: 8156 case X86ISD::AND: 8157 return SDValue(Op.getNode(), 1); 8158 default: 8159 default_case: 8160 break; 8161 } 8162 8163 if (Opcode == 0) 8164 // Emit a CMP with 0, which is the TEST pattern. 8165 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8166 DAG.getConstant(0, Op.getValueType())); 8167 8168 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8169 SmallVector<SDValue, 4> Ops; 8170 for (unsigned i = 0; i != NumOperands; ++i) 8171 Ops.push_back(Op.getOperand(i)); 8172 8173 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8174 DAG.ReplaceAllUsesWith(Op, New); 8175 return SDValue(New.getNode(), 1); 8176} 8177 8178/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8179/// equivalent. 8180SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8181 SelectionDAG &DAG) const { 8182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8183 if (C->getAPIntValue() == 0) 8184 return EmitTest(Op0, X86CC, DAG); 8185 8186 DebugLoc dl = Op0.getDebugLoc(); 8187 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8188} 8189 8190/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8191/// if it's possible. 8192SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8193 DebugLoc dl, SelectionDAG &DAG) const { 8194 SDValue Op0 = And.getOperand(0); 8195 SDValue Op1 = And.getOperand(1); 8196 if (Op0.getOpcode() == ISD::TRUNCATE) 8197 Op0 = Op0.getOperand(0); 8198 if (Op1.getOpcode() == ISD::TRUNCATE) 8199 Op1 = Op1.getOperand(0); 8200 8201 SDValue LHS, RHS; 8202 if (Op1.getOpcode() == ISD::SHL) 8203 std::swap(Op0, Op1); 8204 if (Op0.getOpcode() == ISD::SHL) { 8205 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8206 if (And00C->getZExtValue() == 1) { 8207 // If we looked past a truncate, check that it's only truncating away 8208 // known zeros. 8209 unsigned BitWidth = Op0.getValueSizeInBits(); 8210 unsigned AndBitWidth = And.getValueSizeInBits(); 8211 if (BitWidth > AndBitWidth) { 8212 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8213 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8214 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8215 return SDValue(); 8216 } 8217 LHS = Op1; 8218 RHS = Op0.getOperand(1); 8219 } 8220 } else if (Op1.getOpcode() == ISD::Constant) { 8221 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8222 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8223 SDValue AndLHS = Op0; 8224 8225 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8226 LHS = AndLHS.getOperand(0); 8227 RHS = AndLHS.getOperand(1); 8228 } 8229 8230 // Use BT if the immediate can't be encoded in a TEST instruction. 8231 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8232 LHS = AndLHS; 8233 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8234 } 8235 } 8236 8237 if (LHS.getNode()) { 8238 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8239 // instruction. Since the shift amount is in-range-or-undefined, we know 8240 // that doing a bittest on the i32 value is ok. We extend to i32 because 8241 // the encoding for the i16 version is larger than the i32 version. 8242 // Also promote i16 to i32 for performance / code size reason. 8243 if (LHS.getValueType() == MVT::i8 || 8244 LHS.getValueType() == MVT::i16) 8245 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8246 8247 // If the operand types disagree, extend the shift amount to match. Since 8248 // BT ignores high bits (like shifts) we can use anyextend. 8249 if (LHS.getValueType() != RHS.getValueType()) 8250 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8251 8252 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8253 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8254 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8255 DAG.getConstant(Cond, MVT::i8), BT); 8256 } 8257 8258 return SDValue(); 8259} 8260 8261SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8262 8263 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8264 8265 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8266 SDValue Op0 = Op.getOperand(0); 8267 SDValue Op1 = Op.getOperand(1); 8268 DebugLoc dl = Op.getDebugLoc(); 8269 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8270 8271 // Optimize to BT if possible. 8272 // Lower (X & (1 << N)) == 0 to BT(X, N). 8273 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8274 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8275 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8276 Op1.getOpcode() == ISD::Constant && 8277 cast<ConstantSDNode>(Op1)->isNullValue() && 8278 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8279 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8280 if (NewSetCC.getNode()) 8281 return NewSetCC; 8282 } 8283 8284 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8285 // these. 8286 if (Op1.getOpcode() == ISD::Constant && 8287 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8288 cast<ConstantSDNode>(Op1)->isNullValue()) && 8289 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8290 8291 // If the input is a setcc, then reuse the input setcc or use a new one with 8292 // the inverted condition. 8293 if (Op0.getOpcode() == X86ISD::SETCC) { 8294 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8295 bool Invert = (CC == ISD::SETNE) ^ 8296 cast<ConstantSDNode>(Op1)->isNullValue(); 8297 if (!Invert) return Op0; 8298 8299 CCode = X86::GetOppositeBranchCondition(CCode); 8300 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8301 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8302 } 8303 } 8304 8305 bool isFP = Op1.getValueType().isFloatingPoint(); 8306 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8307 if (X86CC == X86::COND_INVALID) 8308 return SDValue(); 8309 8310 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8311 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8312 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8313} 8314 8315// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8316// ones, and then concatenate the result back. 8317static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8318 EVT VT = Op.getValueType(); 8319 8320 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8321 "Unsupported value type for operation"); 8322 8323 int NumElems = VT.getVectorNumElements(); 8324 DebugLoc dl = Op.getDebugLoc(); 8325 SDValue CC = Op.getOperand(2); 8326 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8327 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8328 8329 // Extract the LHS vectors 8330 SDValue LHS = Op.getOperand(0); 8331 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8332 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8333 8334 // Extract the RHS vectors 8335 SDValue RHS = Op.getOperand(1); 8336 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8337 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8338 8339 // Issue the operation on the smaller types and concatenate the result back 8340 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8341 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8342 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8343 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8344 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8345} 8346 8347 8348SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8349 SDValue Cond; 8350 SDValue Op0 = Op.getOperand(0); 8351 SDValue Op1 = Op.getOperand(1); 8352 SDValue CC = Op.getOperand(2); 8353 EVT VT = Op.getValueType(); 8354 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8355 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8356 DebugLoc dl = Op.getDebugLoc(); 8357 8358 if (isFP) { 8359 unsigned SSECC = 8; 8360 EVT EltVT = Op0.getValueType().getVectorElementType(); 8361 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8362 8363 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8364 bool Swap = false; 8365 8366 // SSE Condition code mapping: 8367 // 0 - EQ 8368 // 1 - LT 8369 // 2 - LE 8370 // 3 - UNORD 8371 // 4 - NEQ 8372 // 5 - NLT 8373 // 6 - NLE 8374 // 7 - ORD 8375 switch (SetCCOpcode) { 8376 default: break; 8377 case ISD::SETOEQ: 8378 case ISD::SETEQ: SSECC = 0; break; 8379 case ISD::SETOGT: 8380 case ISD::SETGT: Swap = true; // Fallthrough 8381 case ISD::SETLT: 8382 case ISD::SETOLT: SSECC = 1; break; 8383 case ISD::SETOGE: 8384 case ISD::SETGE: Swap = true; // Fallthrough 8385 case ISD::SETLE: 8386 case ISD::SETOLE: SSECC = 2; break; 8387 case ISD::SETUO: SSECC = 3; break; 8388 case ISD::SETUNE: 8389 case ISD::SETNE: SSECC = 4; break; 8390 case ISD::SETULE: Swap = true; 8391 case ISD::SETUGE: SSECC = 5; break; 8392 case ISD::SETULT: Swap = true; 8393 case ISD::SETUGT: SSECC = 6; break; 8394 case ISD::SETO: SSECC = 7; break; 8395 } 8396 if (Swap) 8397 std::swap(Op0, Op1); 8398 8399 // In the two special cases we can't handle, emit two comparisons. 8400 if (SSECC == 8) { 8401 if (SetCCOpcode == ISD::SETUEQ) { 8402 SDValue UNORD, EQ; 8403 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8404 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8405 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8406 } else if (SetCCOpcode == ISD::SETONE) { 8407 SDValue ORD, NEQ; 8408 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8409 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8410 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8411 } 8412 llvm_unreachable("Illegal FP comparison"); 8413 } 8414 // Handle all other FP comparisons here. 8415 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8416 } 8417 8418 // Break 256-bit integer vector compare into smaller ones. 8419 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8420 return Lower256IntVSETCC(Op, DAG); 8421 8422 // We are handling one of the integer comparisons here. Since SSE only has 8423 // GT and EQ comparisons for integer, swapping operands and multiple 8424 // operations may be required for some comparisons. 8425 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 8426 bool Swap = false, Invert = false, FlipSigns = false; 8427 8428 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 8429 default: break; 8430 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8431 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8432 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8433 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8434 } 8435 8436 switch (SetCCOpcode) { 8437 default: break; 8438 case ISD::SETNE: Invert = true; 8439 case ISD::SETEQ: Opc = EQOpc; break; 8440 case ISD::SETLT: Swap = true; 8441 case ISD::SETGT: Opc = GTOpc; break; 8442 case ISD::SETGE: Swap = true; 8443 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8444 case ISD::SETULT: Swap = true; 8445 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8446 case ISD::SETUGE: Swap = true; 8447 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8448 } 8449 if (Swap) 8450 std::swap(Op0, Op1); 8451 8452 // Check that the operation in question is available (most are plain SSE2, 8453 // but PCMPGTQ and PCMPEQQ have different requirements). 8454 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42orAVX()) 8455 return SDValue(); 8456 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41orAVX()) 8457 return SDValue(); 8458 8459 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8460 // bits of the inputs before performing those operations. 8461 if (FlipSigns) { 8462 EVT EltVT = VT.getVectorElementType(); 8463 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8464 EltVT); 8465 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8466 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8467 SignBits.size()); 8468 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8469 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8470 } 8471 8472 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8473 8474 // If the logical-not of the result is required, perform that now. 8475 if (Invert) 8476 Result = DAG.getNOT(dl, Result, VT); 8477 8478 return Result; 8479} 8480 8481// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8482static bool isX86LogicalCmp(SDValue Op) { 8483 unsigned Opc = Op.getNode()->getOpcode(); 8484 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8485 return true; 8486 if (Op.getResNo() == 1 && 8487 (Opc == X86ISD::ADD || 8488 Opc == X86ISD::SUB || 8489 Opc == X86ISD::ADC || 8490 Opc == X86ISD::SBB || 8491 Opc == X86ISD::SMUL || 8492 Opc == X86ISD::UMUL || 8493 Opc == X86ISD::INC || 8494 Opc == X86ISD::DEC || 8495 Opc == X86ISD::OR || 8496 Opc == X86ISD::XOR || 8497 Opc == X86ISD::AND)) 8498 return true; 8499 8500 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8501 return true; 8502 8503 return false; 8504} 8505 8506static bool isZero(SDValue V) { 8507 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8508 return C && C->isNullValue(); 8509} 8510 8511static bool isAllOnes(SDValue V) { 8512 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8513 return C && C->isAllOnesValue(); 8514} 8515 8516SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8517 bool addTest = true; 8518 SDValue Cond = Op.getOperand(0); 8519 SDValue Op1 = Op.getOperand(1); 8520 SDValue Op2 = Op.getOperand(2); 8521 DebugLoc DL = Op.getDebugLoc(); 8522 SDValue CC; 8523 8524 if (Cond.getOpcode() == ISD::SETCC) { 8525 SDValue NewCond = LowerSETCC(Cond, DAG); 8526 if (NewCond.getNode()) 8527 Cond = NewCond; 8528 } 8529 8530 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8531 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8532 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8533 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8534 if (Cond.getOpcode() == X86ISD::SETCC && 8535 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8536 isZero(Cond.getOperand(1).getOperand(1))) { 8537 SDValue Cmp = Cond.getOperand(1); 8538 8539 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8540 8541 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8542 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8543 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8544 8545 SDValue CmpOp0 = Cmp.getOperand(0); 8546 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8547 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8548 8549 SDValue Res = // Res = 0 or -1. 8550 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8551 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8552 8553 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8554 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8555 8556 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8557 if (N2C == 0 || !N2C->isNullValue()) 8558 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8559 return Res; 8560 } 8561 } 8562 8563 // Look past (and (setcc_carry (cmp ...)), 1). 8564 if (Cond.getOpcode() == ISD::AND && 8565 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8566 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8567 if (C && C->getAPIntValue() == 1) 8568 Cond = Cond.getOperand(0); 8569 } 8570 8571 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8572 // setting operand in place of the X86ISD::SETCC. 8573 unsigned CondOpcode = Cond.getOpcode(); 8574 if (CondOpcode == X86ISD::SETCC || 8575 CondOpcode == X86ISD::SETCC_CARRY) { 8576 CC = Cond.getOperand(0); 8577 8578 SDValue Cmp = Cond.getOperand(1); 8579 unsigned Opc = Cmp.getOpcode(); 8580 EVT VT = Op.getValueType(); 8581 8582 bool IllegalFPCMov = false; 8583 if (VT.isFloatingPoint() && !VT.isVector() && 8584 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8585 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8586 8587 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8588 Opc == X86ISD::BT) { // FIXME 8589 Cond = Cmp; 8590 addTest = false; 8591 } 8592 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8593 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8594 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8595 Cond.getOperand(0).getValueType() != MVT::i8)) { 8596 SDValue LHS = Cond.getOperand(0); 8597 SDValue RHS = Cond.getOperand(1); 8598 unsigned X86Opcode; 8599 unsigned X86Cond; 8600 SDVTList VTs; 8601 switch (CondOpcode) { 8602 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8603 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8604 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8605 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8606 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8607 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8608 default: llvm_unreachable("unexpected overflowing operator"); 8609 } 8610 if (CondOpcode == ISD::UMULO) 8611 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8612 MVT::i32); 8613 else 8614 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8615 8616 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8617 8618 if (CondOpcode == ISD::UMULO) 8619 Cond = X86Op.getValue(2); 8620 else 8621 Cond = X86Op.getValue(1); 8622 8623 CC = DAG.getConstant(X86Cond, MVT::i8); 8624 addTest = false; 8625 } 8626 8627 if (addTest) { 8628 // Look pass the truncate. 8629 if (Cond.getOpcode() == ISD::TRUNCATE) 8630 Cond = Cond.getOperand(0); 8631 8632 // We know the result of AND is compared against zero. Try to match 8633 // it to BT. 8634 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8635 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8636 if (NewSetCC.getNode()) { 8637 CC = NewSetCC.getOperand(0); 8638 Cond = NewSetCC.getOperand(1); 8639 addTest = false; 8640 } 8641 } 8642 } 8643 8644 if (addTest) { 8645 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8646 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8647 } 8648 8649 // a < b ? -1 : 0 -> RES = ~setcc_carry 8650 // a < b ? 0 : -1 -> RES = setcc_carry 8651 // a >= b ? -1 : 0 -> RES = setcc_carry 8652 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8653 if (Cond.getOpcode() == X86ISD::CMP) { 8654 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8655 8656 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8657 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8658 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8659 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8660 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8661 return DAG.getNOT(DL, Res, Res.getValueType()); 8662 return Res; 8663 } 8664 } 8665 8666 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8667 // condition is true. 8668 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8669 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8670 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8671} 8672 8673// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8674// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8675// from the AND / OR. 8676static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8677 Opc = Op.getOpcode(); 8678 if (Opc != ISD::OR && Opc != ISD::AND) 8679 return false; 8680 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8681 Op.getOperand(0).hasOneUse() && 8682 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8683 Op.getOperand(1).hasOneUse()); 8684} 8685 8686// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8687// 1 and that the SETCC node has a single use. 8688static bool isXor1OfSetCC(SDValue Op) { 8689 if (Op.getOpcode() != ISD::XOR) 8690 return false; 8691 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8692 if (N1C && N1C->getAPIntValue() == 1) { 8693 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8694 Op.getOperand(0).hasOneUse(); 8695 } 8696 return false; 8697} 8698 8699SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8700 bool addTest = true; 8701 SDValue Chain = Op.getOperand(0); 8702 SDValue Cond = Op.getOperand(1); 8703 SDValue Dest = Op.getOperand(2); 8704 DebugLoc dl = Op.getDebugLoc(); 8705 SDValue CC; 8706 bool Inverted = false; 8707 8708 if (Cond.getOpcode() == ISD::SETCC) { 8709 // Check for setcc([su]{add,sub,mul}o == 0). 8710 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8711 isa<ConstantSDNode>(Cond.getOperand(1)) && 8712 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8713 Cond.getOperand(0).getResNo() == 1 && 8714 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8715 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8716 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8717 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8718 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8719 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8720 Inverted = true; 8721 Cond = Cond.getOperand(0); 8722 } else { 8723 SDValue NewCond = LowerSETCC(Cond, DAG); 8724 if (NewCond.getNode()) 8725 Cond = NewCond; 8726 } 8727 } 8728#if 0 8729 // FIXME: LowerXALUO doesn't handle these!! 8730 else if (Cond.getOpcode() == X86ISD::ADD || 8731 Cond.getOpcode() == X86ISD::SUB || 8732 Cond.getOpcode() == X86ISD::SMUL || 8733 Cond.getOpcode() == X86ISD::UMUL) 8734 Cond = LowerXALUO(Cond, DAG); 8735#endif 8736 8737 // Look pass (and (setcc_carry (cmp ...)), 1). 8738 if (Cond.getOpcode() == ISD::AND && 8739 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8740 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8741 if (C && C->getAPIntValue() == 1) 8742 Cond = Cond.getOperand(0); 8743 } 8744 8745 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8746 // setting operand in place of the X86ISD::SETCC. 8747 unsigned CondOpcode = Cond.getOpcode(); 8748 if (CondOpcode == X86ISD::SETCC || 8749 CondOpcode == X86ISD::SETCC_CARRY) { 8750 CC = Cond.getOperand(0); 8751 8752 SDValue Cmp = Cond.getOperand(1); 8753 unsigned Opc = Cmp.getOpcode(); 8754 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8755 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8756 Cond = Cmp; 8757 addTest = false; 8758 } else { 8759 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8760 default: break; 8761 case X86::COND_O: 8762 case X86::COND_B: 8763 // These can only come from an arithmetic instruction with overflow, 8764 // e.g. SADDO, UADDO. 8765 Cond = Cond.getNode()->getOperand(1); 8766 addTest = false; 8767 break; 8768 } 8769 } 8770 } 8771 CondOpcode = Cond.getOpcode(); 8772 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8773 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8774 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8775 Cond.getOperand(0).getValueType() != MVT::i8)) { 8776 SDValue LHS = Cond.getOperand(0); 8777 SDValue RHS = Cond.getOperand(1); 8778 unsigned X86Opcode; 8779 unsigned X86Cond; 8780 SDVTList VTs; 8781 switch (CondOpcode) { 8782 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8783 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8784 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8785 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8786 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8787 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8788 default: llvm_unreachable("unexpected overflowing operator"); 8789 } 8790 if (Inverted) 8791 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8792 if (CondOpcode == ISD::UMULO) 8793 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8794 MVT::i32); 8795 else 8796 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8797 8798 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8799 8800 if (CondOpcode == ISD::UMULO) 8801 Cond = X86Op.getValue(2); 8802 else 8803 Cond = X86Op.getValue(1); 8804 8805 CC = DAG.getConstant(X86Cond, MVT::i8); 8806 addTest = false; 8807 } else { 8808 unsigned CondOpc; 8809 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8810 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8811 if (CondOpc == ISD::OR) { 8812 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8813 // two branches instead of an explicit OR instruction with a 8814 // separate test. 8815 if (Cmp == Cond.getOperand(1).getOperand(1) && 8816 isX86LogicalCmp(Cmp)) { 8817 CC = Cond.getOperand(0).getOperand(0); 8818 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8819 Chain, Dest, CC, Cmp); 8820 CC = Cond.getOperand(1).getOperand(0); 8821 Cond = Cmp; 8822 addTest = false; 8823 } 8824 } else { // ISD::AND 8825 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8826 // two branches instead of an explicit AND instruction with a 8827 // separate test. However, we only do this if this block doesn't 8828 // have a fall-through edge, because this requires an explicit 8829 // jmp when the condition is false. 8830 if (Cmp == Cond.getOperand(1).getOperand(1) && 8831 isX86LogicalCmp(Cmp) && 8832 Op.getNode()->hasOneUse()) { 8833 X86::CondCode CCode = 8834 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8835 CCode = X86::GetOppositeBranchCondition(CCode); 8836 CC = DAG.getConstant(CCode, MVT::i8); 8837 SDNode *User = *Op.getNode()->use_begin(); 8838 // Look for an unconditional branch following this conditional branch. 8839 // We need this because we need to reverse the successors in order 8840 // to implement FCMP_OEQ. 8841 if (User->getOpcode() == ISD::BR) { 8842 SDValue FalseBB = User->getOperand(1); 8843 SDNode *NewBR = 8844 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8845 assert(NewBR == User); 8846 (void)NewBR; 8847 Dest = FalseBB; 8848 8849 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8850 Chain, Dest, CC, Cmp); 8851 X86::CondCode CCode = 8852 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8853 CCode = X86::GetOppositeBranchCondition(CCode); 8854 CC = DAG.getConstant(CCode, MVT::i8); 8855 Cond = Cmp; 8856 addTest = false; 8857 } 8858 } 8859 } 8860 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8861 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8862 // It should be transformed during dag combiner except when the condition 8863 // is set by a arithmetics with overflow node. 8864 X86::CondCode CCode = 8865 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8866 CCode = X86::GetOppositeBranchCondition(CCode); 8867 CC = DAG.getConstant(CCode, MVT::i8); 8868 Cond = Cond.getOperand(0).getOperand(1); 8869 addTest = false; 8870 } else if (Cond.getOpcode() == ISD::SETCC && 8871 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8872 // For FCMP_OEQ, we can emit 8873 // two branches instead of an explicit AND instruction with a 8874 // separate test. However, we only do this if this block doesn't 8875 // have a fall-through edge, because this requires an explicit 8876 // jmp when the condition is false. 8877 if (Op.getNode()->hasOneUse()) { 8878 SDNode *User = *Op.getNode()->use_begin(); 8879 // Look for an unconditional branch following this conditional branch. 8880 // We need this because we need to reverse the successors in order 8881 // to implement FCMP_OEQ. 8882 if (User->getOpcode() == ISD::BR) { 8883 SDValue FalseBB = User->getOperand(1); 8884 SDNode *NewBR = 8885 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8886 assert(NewBR == User); 8887 (void)NewBR; 8888 Dest = FalseBB; 8889 8890 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8891 Cond.getOperand(0), Cond.getOperand(1)); 8892 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8893 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8894 Chain, Dest, CC, Cmp); 8895 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8896 Cond = Cmp; 8897 addTest = false; 8898 } 8899 } 8900 } else if (Cond.getOpcode() == ISD::SETCC && 8901 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8902 // For FCMP_UNE, we can emit 8903 // two branches instead of an explicit AND instruction with a 8904 // separate test. However, we only do this if this block doesn't 8905 // have a fall-through edge, because this requires an explicit 8906 // jmp when the condition is false. 8907 if (Op.getNode()->hasOneUse()) { 8908 SDNode *User = *Op.getNode()->use_begin(); 8909 // Look for an unconditional branch following this conditional branch. 8910 // We need this because we need to reverse the successors in order 8911 // to implement FCMP_UNE. 8912 if (User->getOpcode() == ISD::BR) { 8913 SDValue FalseBB = User->getOperand(1); 8914 SDNode *NewBR = 8915 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8916 assert(NewBR == User); 8917 (void)NewBR; 8918 8919 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8920 Cond.getOperand(0), Cond.getOperand(1)); 8921 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8922 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8923 Chain, Dest, CC, Cmp); 8924 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8925 Cond = Cmp; 8926 addTest = false; 8927 Dest = FalseBB; 8928 } 8929 } 8930 } 8931 } 8932 8933 if (addTest) { 8934 // Look pass the truncate. 8935 if (Cond.getOpcode() == ISD::TRUNCATE) 8936 Cond = Cond.getOperand(0); 8937 8938 // We know the result of AND is compared against zero. Try to match 8939 // it to BT. 8940 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8941 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8942 if (NewSetCC.getNode()) { 8943 CC = NewSetCC.getOperand(0); 8944 Cond = NewSetCC.getOperand(1); 8945 addTest = false; 8946 } 8947 } 8948 } 8949 8950 if (addTest) { 8951 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8952 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8953 } 8954 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8955 Chain, Dest, CC, Cond); 8956} 8957 8958 8959// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8960// Calls to _alloca is needed to probe the stack when allocating more than 4k 8961// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8962// that the guard pages used by the OS virtual memory manager are allocated in 8963// correct sequence. 8964SDValue 8965X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8966 SelectionDAG &DAG) const { 8967 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8968 getTargetMachine().Options.EnableSegmentedStacks) && 8969 "This should be used only on Windows targets or when segmented stacks " 8970 "are being used"); 8971 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8972 DebugLoc dl = Op.getDebugLoc(); 8973 8974 // Get the inputs. 8975 SDValue Chain = Op.getOperand(0); 8976 SDValue Size = Op.getOperand(1); 8977 // FIXME: Ensure alignment here 8978 8979 bool Is64Bit = Subtarget->is64Bit(); 8980 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8981 8982 if (getTargetMachine().Options.EnableSegmentedStacks) { 8983 MachineFunction &MF = DAG.getMachineFunction(); 8984 MachineRegisterInfo &MRI = MF.getRegInfo(); 8985 8986 if (Is64Bit) { 8987 // The 64 bit implementation of segmented stacks needs to clobber both r10 8988 // r11. This makes it impossible to use it along with nested parameters. 8989 const Function *F = MF.getFunction(); 8990 8991 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8992 I != E; I++) 8993 if (I->hasNestAttr()) 8994 report_fatal_error("Cannot use segmented stacks with functions that " 8995 "have nested arguments."); 8996 } 8997 8998 const TargetRegisterClass *AddrRegClass = 8999 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9000 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9001 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9002 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9003 DAG.getRegister(Vreg, SPTy)); 9004 SDValue Ops1[2] = { Value, Chain }; 9005 return DAG.getMergeValues(Ops1, 2, dl); 9006 } else { 9007 SDValue Flag; 9008 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9009 9010 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9011 Flag = Chain.getValue(1); 9012 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9013 9014 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9015 Flag = Chain.getValue(1); 9016 9017 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9018 9019 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9020 return DAG.getMergeValues(Ops1, 2, dl); 9021 } 9022} 9023 9024SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9025 MachineFunction &MF = DAG.getMachineFunction(); 9026 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9027 9028 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9029 DebugLoc DL = Op.getDebugLoc(); 9030 9031 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9032 // vastart just stores the address of the VarArgsFrameIndex slot into the 9033 // memory location argument. 9034 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9035 getPointerTy()); 9036 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9037 MachinePointerInfo(SV), false, false, 0); 9038 } 9039 9040 // __va_list_tag: 9041 // gp_offset (0 - 6 * 8) 9042 // fp_offset (48 - 48 + 8 * 16) 9043 // overflow_arg_area (point to parameters coming in memory). 9044 // reg_save_area 9045 SmallVector<SDValue, 8> MemOps; 9046 SDValue FIN = Op.getOperand(1); 9047 // Store gp_offset 9048 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9049 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9050 MVT::i32), 9051 FIN, MachinePointerInfo(SV), false, false, 0); 9052 MemOps.push_back(Store); 9053 9054 // Store fp_offset 9055 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9056 FIN, DAG.getIntPtrConstant(4)); 9057 Store = DAG.getStore(Op.getOperand(0), DL, 9058 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9059 MVT::i32), 9060 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9061 MemOps.push_back(Store); 9062 9063 // Store ptr to overflow_arg_area 9064 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9065 FIN, DAG.getIntPtrConstant(4)); 9066 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9067 getPointerTy()); 9068 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9069 MachinePointerInfo(SV, 8), 9070 false, false, 0); 9071 MemOps.push_back(Store); 9072 9073 // Store ptr to reg_save_area. 9074 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9075 FIN, DAG.getIntPtrConstant(8)); 9076 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9077 getPointerTy()); 9078 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9079 MachinePointerInfo(SV, 16), false, false, 0); 9080 MemOps.push_back(Store); 9081 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9082 &MemOps[0], MemOps.size()); 9083} 9084 9085SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9086 assert(Subtarget->is64Bit() && 9087 "LowerVAARG only handles 64-bit va_arg!"); 9088 assert((Subtarget->isTargetLinux() || 9089 Subtarget->isTargetDarwin()) && 9090 "Unhandled target in LowerVAARG"); 9091 assert(Op.getNode()->getNumOperands() == 4); 9092 SDValue Chain = Op.getOperand(0); 9093 SDValue SrcPtr = Op.getOperand(1); 9094 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9095 unsigned Align = Op.getConstantOperandVal(3); 9096 DebugLoc dl = Op.getDebugLoc(); 9097 9098 EVT ArgVT = Op.getNode()->getValueType(0); 9099 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9100 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9101 uint8_t ArgMode; 9102 9103 // Decide which area this value should be read from. 9104 // TODO: Implement the AMD64 ABI in its entirety. This simple 9105 // selection mechanism works only for the basic types. 9106 if (ArgVT == MVT::f80) { 9107 llvm_unreachable("va_arg for f80 not yet implemented"); 9108 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9109 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9110 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9111 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9112 } else { 9113 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9114 } 9115 9116 if (ArgMode == 2) { 9117 // Sanity Check: Make sure using fp_offset makes sense. 9118 assert(!getTargetMachine().Options.UseSoftFloat && 9119 !(DAG.getMachineFunction() 9120 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9121 Subtarget->hasXMM()); 9122 } 9123 9124 // Insert VAARG_64 node into the DAG 9125 // VAARG_64 returns two values: Variable Argument Address, Chain 9126 SmallVector<SDValue, 11> InstOps; 9127 InstOps.push_back(Chain); 9128 InstOps.push_back(SrcPtr); 9129 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9130 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9131 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9132 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9133 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9134 VTs, &InstOps[0], InstOps.size(), 9135 MVT::i64, 9136 MachinePointerInfo(SV), 9137 /*Align=*/0, 9138 /*Volatile=*/false, 9139 /*ReadMem=*/true, 9140 /*WriteMem=*/true); 9141 Chain = VAARG.getValue(1); 9142 9143 // Load the next argument and return it 9144 return DAG.getLoad(ArgVT, dl, 9145 Chain, 9146 VAARG, 9147 MachinePointerInfo(), 9148 false, false, false, 0); 9149} 9150 9151SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9152 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9153 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9154 SDValue Chain = Op.getOperand(0); 9155 SDValue DstPtr = Op.getOperand(1); 9156 SDValue SrcPtr = Op.getOperand(2); 9157 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9158 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9159 DebugLoc DL = Op.getDebugLoc(); 9160 9161 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9162 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9163 false, 9164 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9165} 9166 9167SDValue 9168X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9169 DebugLoc dl = Op.getDebugLoc(); 9170 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9171 switch (IntNo) { 9172 default: return SDValue(); // Don't custom lower most intrinsics. 9173 // Comparison intrinsics. 9174 case Intrinsic::x86_sse_comieq_ss: 9175 case Intrinsic::x86_sse_comilt_ss: 9176 case Intrinsic::x86_sse_comile_ss: 9177 case Intrinsic::x86_sse_comigt_ss: 9178 case Intrinsic::x86_sse_comige_ss: 9179 case Intrinsic::x86_sse_comineq_ss: 9180 case Intrinsic::x86_sse_ucomieq_ss: 9181 case Intrinsic::x86_sse_ucomilt_ss: 9182 case Intrinsic::x86_sse_ucomile_ss: 9183 case Intrinsic::x86_sse_ucomigt_ss: 9184 case Intrinsic::x86_sse_ucomige_ss: 9185 case Intrinsic::x86_sse_ucomineq_ss: 9186 case Intrinsic::x86_sse2_comieq_sd: 9187 case Intrinsic::x86_sse2_comilt_sd: 9188 case Intrinsic::x86_sse2_comile_sd: 9189 case Intrinsic::x86_sse2_comigt_sd: 9190 case Intrinsic::x86_sse2_comige_sd: 9191 case Intrinsic::x86_sse2_comineq_sd: 9192 case Intrinsic::x86_sse2_ucomieq_sd: 9193 case Intrinsic::x86_sse2_ucomilt_sd: 9194 case Intrinsic::x86_sse2_ucomile_sd: 9195 case Intrinsic::x86_sse2_ucomigt_sd: 9196 case Intrinsic::x86_sse2_ucomige_sd: 9197 case Intrinsic::x86_sse2_ucomineq_sd: { 9198 unsigned Opc = 0; 9199 ISD::CondCode CC = ISD::SETCC_INVALID; 9200 switch (IntNo) { 9201 default: break; 9202 case Intrinsic::x86_sse_comieq_ss: 9203 case Intrinsic::x86_sse2_comieq_sd: 9204 Opc = X86ISD::COMI; 9205 CC = ISD::SETEQ; 9206 break; 9207 case Intrinsic::x86_sse_comilt_ss: 9208 case Intrinsic::x86_sse2_comilt_sd: 9209 Opc = X86ISD::COMI; 9210 CC = ISD::SETLT; 9211 break; 9212 case Intrinsic::x86_sse_comile_ss: 9213 case Intrinsic::x86_sse2_comile_sd: 9214 Opc = X86ISD::COMI; 9215 CC = ISD::SETLE; 9216 break; 9217 case Intrinsic::x86_sse_comigt_ss: 9218 case Intrinsic::x86_sse2_comigt_sd: 9219 Opc = X86ISD::COMI; 9220 CC = ISD::SETGT; 9221 break; 9222 case Intrinsic::x86_sse_comige_ss: 9223 case Intrinsic::x86_sse2_comige_sd: 9224 Opc = X86ISD::COMI; 9225 CC = ISD::SETGE; 9226 break; 9227 case Intrinsic::x86_sse_comineq_ss: 9228 case Intrinsic::x86_sse2_comineq_sd: 9229 Opc = X86ISD::COMI; 9230 CC = ISD::SETNE; 9231 break; 9232 case Intrinsic::x86_sse_ucomieq_ss: 9233 case Intrinsic::x86_sse2_ucomieq_sd: 9234 Opc = X86ISD::UCOMI; 9235 CC = ISD::SETEQ; 9236 break; 9237 case Intrinsic::x86_sse_ucomilt_ss: 9238 case Intrinsic::x86_sse2_ucomilt_sd: 9239 Opc = X86ISD::UCOMI; 9240 CC = ISD::SETLT; 9241 break; 9242 case Intrinsic::x86_sse_ucomile_ss: 9243 case Intrinsic::x86_sse2_ucomile_sd: 9244 Opc = X86ISD::UCOMI; 9245 CC = ISD::SETLE; 9246 break; 9247 case Intrinsic::x86_sse_ucomigt_ss: 9248 case Intrinsic::x86_sse2_ucomigt_sd: 9249 Opc = X86ISD::UCOMI; 9250 CC = ISD::SETGT; 9251 break; 9252 case Intrinsic::x86_sse_ucomige_ss: 9253 case Intrinsic::x86_sse2_ucomige_sd: 9254 Opc = X86ISD::UCOMI; 9255 CC = ISD::SETGE; 9256 break; 9257 case Intrinsic::x86_sse_ucomineq_ss: 9258 case Intrinsic::x86_sse2_ucomineq_sd: 9259 Opc = X86ISD::UCOMI; 9260 CC = ISD::SETNE; 9261 break; 9262 } 9263 9264 SDValue LHS = Op.getOperand(1); 9265 SDValue RHS = Op.getOperand(2); 9266 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9267 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9268 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9269 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9270 DAG.getConstant(X86CC, MVT::i8), Cond); 9271 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9272 } 9273 // Arithmetic intrinsics. 9274 case Intrinsic::x86_sse3_hadd_ps: 9275 case Intrinsic::x86_sse3_hadd_pd: 9276 case Intrinsic::x86_avx_hadd_ps_256: 9277 case Intrinsic::x86_avx_hadd_pd_256: 9278 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9279 Op.getOperand(1), Op.getOperand(2)); 9280 case Intrinsic::x86_sse3_hsub_ps: 9281 case Intrinsic::x86_sse3_hsub_pd: 9282 case Intrinsic::x86_avx_hsub_ps_256: 9283 case Intrinsic::x86_avx_hsub_pd_256: 9284 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9285 Op.getOperand(1), Op.getOperand(2)); 9286 case Intrinsic::x86_avx2_psllv_d: 9287 case Intrinsic::x86_avx2_psllv_q: 9288 case Intrinsic::x86_avx2_psllv_d_256: 9289 case Intrinsic::x86_avx2_psllv_q_256: 9290 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9291 Op.getOperand(1), Op.getOperand(2)); 9292 case Intrinsic::x86_avx2_psrlv_d: 9293 case Intrinsic::x86_avx2_psrlv_q: 9294 case Intrinsic::x86_avx2_psrlv_d_256: 9295 case Intrinsic::x86_avx2_psrlv_q_256: 9296 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9297 Op.getOperand(1), Op.getOperand(2)); 9298 case Intrinsic::x86_avx2_psrav_d: 9299 case Intrinsic::x86_avx2_psrav_d_256: 9300 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9301 Op.getOperand(1), Op.getOperand(2)); 9302 9303 // ptest and testp intrinsics. The intrinsic these come from are designed to 9304 // return an integer value, not just an instruction so lower it to the ptest 9305 // or testp pattern and a setcc for the result. 9306 case Intrinsic::x86_sse41_ptestz: 9307 case Intrinsic::x86_sse41_ptestc: 9308 case Intrinsic::x86_sse41_ptestnzc: 9309 case Intrinsic::x86_avx_ptestz_256: 9310 case Intrinsic::x86_avx_ptestc_256: 9311 case Intrinsic::x86_avx_ptestnzc_256: 9312 case Intrinsic::x86_avx_vtestz_ps: 9313 case Intrinsic::x86_avx_vtestc_ps: 9314 case Intrinsic::x86_avx_vtestnzc_ps: 9315 case Intrinsic::x86_avx_vtestz_pd: 9316 case Intrinsic::x86_avx_vtestc_pd: 9317 case Intrinsic::x86_avx_vtestnzc_pd: 9318 case Intrinsic::x86_avx_vtestz_ps_256: 9319 case Intrinsic::x86_avx_vtestc_ps_256: 9320 case Intrinsic::x86_avx_vtestnzc_ps_256: 9321 case Intrinsic::x86_avx_vtestz_pd_256: 9322 case Intrinsic::x86_avx_vtestc_pd_256: 9323 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9324 bool IsTestPacked = false; 9325 unsigned X86CC = 0; 9326 switch (IntNo) { 9327 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9328 case Intrinsic::x86_avx_vtestz_ps: 9329 case Intrinsic::x86_avx_vtestz_pd: 9330 case Intrinsic::x86_avx_vtestz_ps_256: 9331 case Intrinsic::x86_avx_vtestz_pd_256: 9332 IsTestPacked = true; // Fallthrough 9333 case Intrinsic::x86_sse41_ptestz: 9334 case Intrinsic::x86_avx_ptestz_256: 9335 // ZF = 1 9336 X86CC = X86::COND_E; 9337 break; 9338 case Intrinsic::x86_avx_vtestc_ps: 9339 case Intrinsic::x86_avx_vtestc_pd: 9340 case Intrinsic::x86_avx_vtestc_ps_256: 9341 case Intrinsic::x86_avx_vtestc_pd_256: 9342 IsTestPacked = true; // Fallthrough 9343 case Intrinsic::x86_sse41_ptestc: 9344 case Intrinsic::x86_avx_ptestc_256: 9345 // CF = 1 9346 X86CC = X86::COND_B; 9347 break; 9348 case Intrinsic::x86_avx_vtestnzc_ps: 9349 case Intrinsic::x86_avx_vtestnzc_pd: 9350 case Intrinsic::x86_avx_vtestnzc_ps_256: 9351 case Intrinsic::x86_avx_vtestnzc_pd_256: 9352 IsTestPacked = true; // Fallthrough 9353 case Intrinsic::x86_sse41_ptestnzc: 9354 case Intrinsic::x86_avx_ptestnzc_256: 9355 // ZF and CF = 0 9356 X86CC = X86::COND_A; 9357 break; 9358 } 9359 9360 SDValue LHS = Op.getOperand(1); 9361 SDValue RHS = Op.getOperand(2); 9362 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9363 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9364 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9365 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9366 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9367 } 9368 9369 // Fix vector shift instructions where the last operand is a non-immediate 9370 // i32 value. 9371 case Intrinsic::x86_avx2_pslli_w: 9372 case Intrinsic::x86_avx2_pslli_d: 9373 case Intrinsic::x86_avx2_pslli_q: 9374 case Intrinsic::x86_avx2_psrli_w: 9375 case Intrinsic::x86_avx2_psrli_d: 9376 case Intrinsic::x86_avx2_psrli_q: 9377 case Intrinsic::x86_avx2_psrai_w: 9378 case Intrinsic::x86_avx2_psrai_d: 9379 case Intrinsic::x86_sse2_pslli_w: 9380 case Intrinsic::x86_sse2_pslli_d: 9381 case Intrinsic::x86_sse2_pslli_q: 9382 case Intrinsic::x86_sse2_psrli_w: 9383 case Intrinsic::x86_sse2_psrli_d: 9384 case Intrinsic::x86_sse2_psrli_q: 9385 case Intrinsic::x86_sse2_psrai_w: 9386 case Intrinsic::x86_sse2_psrai_d: 9387 case Intrinsic::x86_mmx_pslli_w: 9388 case Intrinsic::x86_mmx_pslli_d: 9389 case Intrinsic::x86_mmx_pslli_q: 9390 case Intrinsic::x86_mmx_psrli_w: 9391 case Intrinsic::x86_mmx_psrli_d: 9392 case Intrinsic::x86_mmx_psrli_q: 9393 case Intrinsic::x86_mmx_psrai_w: 9394 case Intrinsic::x86_mmx_psrai_d: { 9395 SDValue ShAmt = Op.getOperand(2); 9396 if (isa<ConstantSDNode>(ShAmt)) 9397 return SDValue(); 9398 9399 unsigned NewIntNo = 0; 9400 EVT ShAmtVT = MVT::v4i32; 9401 switch (IntNo) { 9402 case Intrinsic::x86_sse2_pslli_w: 9403 NewIntNo = Intrinsic::x86_sse2_psll_w; 9404 break; 9405 case Intrinsic::x86_sse2_pslli_d: 9406 NewIntNo = Intrinsic::x86_sse2_psll_d; 9407 break; 9408 case Intrinsic::x86_sse2_pslli_q: 9409 NewIntNo = Intrinsic::x86_sse2_psll_q; 9410 break; 9411 case Intrinsic::x86_sse2_psrli_w: 9412 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9413 break; 9414 case Intrinsic::x86_sse2_psrli_d: 9415 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9416 break; 9417 case Intrinsic::x86_sse2_psrli_q: 9418 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9419 break; 9420 case Intrinsic::x86_sse2_psrai_w: 9421 NewIntNo = Intrinsic::x86_sse2_psra_w; 9422 break; 9423 case Intrinsic::x86_sse2_psrai_d: 9424 NewIntNo = Intrinsic::x86_sse2_psra_d; 9425 break; 9426 case Intrinsic::x86_avx2_pslli_w: 9427 NewIntNo = Intrinsic::x86_avx2_psll_w; 9428 break; 9429 case Intrinsic::x86_avx2_pslli_d: 9430 NewIntNo = Intrinsic::x86_avx2_psll_d; 9431 break; 9432 case Intrinsic::x86_avx2_pslli_q: 9433 NewIntNo = Intrinsic::x86_avx2_psll_q; 9434 break; 9435 case Intrinsic::x86_avx2_psrli_w: 9436 NewIntNo = Intrinsic::x86_avx2_psrl_w; 9437 break; 9438 case Intrinsic::x86_avx2_psrli_d: 9439 NewIntNo = Intrinsic::x86_avx2_psrl_d; 9440 break; 9441 case Intrinsic::x86_avx2_psrli_q: 9442 NewIntNo = Intrinsic::x86_avx2_psrl_q; 9443 break; 9444 case Intrinsic::x86_avx2_psrai_w: 9445 NewIntNo = Intrinsic::x86_avx2_psra_w; 9446 break; 9447 case Intrinsic::x86_avx2_psrai_d: 9448 NewIntNo = Intrinsic::x86_avx2_psra_d; 9449 break; 9450 default: { 9451 ShAmtVT = MVT::v2i32; 9452 switch (IntNo) { 9453 case Intrinsic::x86_mmx_pslli_w: 9454 NewIntNo = Intrinsic::x86_mmx_psll_w; 9455 break; 9456 case Intrinsic::x86_mmx_pslli_d: 9457 NewIntNo = Intrinsic::x86_mmx_psll_d; 9458 break; 9459 case Intrinsic::x86_mmx_pslli_q: 9460 NewIntNo = Intrinsic::x86_mmx_psll_q; 9461 break; 9462 case Intrinsic::x86_mmx_psrli_w: 9463 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9464 break; 9465 case Intrinsic::x86_mmx_psrli_d: 9466 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9467 break; 9468 case Intrinsic::x86_mmx_psrli_q: 9469 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9470 break; 9471 case Intrinsic::x86_mmx_psrai_w: 9472 NewIntNo = Intrinsic::x86_mmx_psra_w; 9473 break; 9474 case Intrinsic::x86_mmx_psrai_d: 9475 NewIntNo = Intrinsic::x86_mmx_psra_d; 9476 break; 9477 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9478 } 9479 break; 9480 } 9481 } 9482 9483 // The vector shift intrinsics with scalars uses 32b shift amounts but 9484 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9485 // to be zero. 9486 SDValue ShOps[4]; 9487 ShOps[0] = ShAmt; 9488 ShOps[1] = DAG.getConstant(0, MVT::i32); 9489 if (ShAmtVT == MVT::v4i32) { 9490 ShOps[2] = DAG.getUNDEF(MVT::i32); 9491 ShOps[3] = DAG.getUNDEF(MVT::i32); 9492 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9493 } else { 9494 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9495// FIXME this must be lowered to get rid of the invalid type. 9496 } 9497 9498 EVT VT = Op.getValueType(); 9499 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9500 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9501 DAG.getConstant(NewIntNo, MVT::i32), 9502 Op.getOperand(1), ShAmt); 9503 } 9504 } 9505} 9506 9507SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9508 SelectionDAG &DAG) const { 9509 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9510 MFI->setReturnAddressIsTaken(true); 9511 9512 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9513 DebugLoc dl = Op.getDebugLoc(); 9514 9515 if (Depth > 0) { 9516 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9517 SDValue Offset = 9518 DAG.getConstant(TD->getPointerSize(), 9519 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9520 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9521 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9522 FrameAddr, Offset), 9523 MachinePointerInfo(), false, false, false, 0); 9524 } 9525 9526 // Just load the return address. 9527 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9528 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9529 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9530} 9531 9532SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9533 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9534 MFI->setFrameAddressIsTaken(true); 9535 9536 EVT VT = Op.getValueType(); 9537 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9538 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9539 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9540 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9541 while (Depth--) 9542 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9543 MachinePointerInfo(), 9544 false, false, false, 0); 9545 return FrameAddr; 9546} 9547 9548SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9549 SelectionDAG &DAG) const { 9550 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9551} 9552 9553SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9554 MachineFunction &MF = DAG.getMachineFunction(); 9555 SDValue Chain = Op.getOperand(0); 9556 SDValue Offset = Op.getOperand(1); 9557 SDValue Handler = Op.getOperand(2); 9558 DebugLoc dl = Op.getDebugLoc(); 9559 9560 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9561 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9562 getPointerTy()); 9563 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9564 9565 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9566 DAG.getIntPtrConstant(TD->getPointerSize())); 9567 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9568 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9569 false, false, 0); 9570 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9571 MF.getRegInfo().addLiveOut(StoreAddrReg); 9572 9573 return DAG.getNode(X86ISD::EH_RETURN, dl, 9574 MVT::Other, 9575 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9576} 9577 9578SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9579 SelectionDAG &DAG) const { 9580 return Op.getOperand(0); 9581} 9582 9583SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9584 SelectionDAG &DAG) const { 9585 SDValue Root = Op.getOperand(0); 9586 SDValue Trmp = Op.getOperand(1); // trampoline 9587 SDValue FPtr = Op.getOperand(2); // nested function 9588 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9589 DebugLoc dl = Op.getDebugLoc(); 9590 9591 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9592 9593 if (Subtarget->is64Bit()) { 9594 SDValue OutChains[6]; 9595 9596 // Large code-model. 9597 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9598 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9599 9600 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9601 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9602 9603 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9604 9605 // Load the pointer to the nested function into R11. 9606 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9607 SDValue Addr = Trmp; 9608 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9609 Addr, MachinePointerInfo(TrmpAddr), 9610 false, false, 0); 9611 9612 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9613 DAG.getConstant(2, MVT::i64)); 9614 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9615 MachinePointerInfo(TrmpAddr, 2), 9616 false, false, 2); 9617 9618 // Load the 'nest' parameter value into R10. 9619 // R10 is specified in X86CallingConv.td 9620 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9621 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9622 DAG.getConstant(10, MVT::i64)); 9623 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9624 Addr, MachinePointerInfo(TrmpAddr, 10), 9625 false, false, 0); 9626 9627 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9628 DAG.getConstant(12, MVT::i64)); 9629 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9630 MachinePointerInfo(TrmpAddr, 12), 9631 false, false, 2); 9632 9633 // Jump to the nested function. 9634 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9635 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9636 DAG.getConstant(20, MVT::i64)); 9637 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9638 Addr, MachinePointerInfo(TrmpAddr, 20), 9639 false, false, 0); 9640 9641 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9642 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9643 DAG.getConstant(22, MVT::i64)); 9644 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9645 MachinePointerInfo(TrmpAddr, 22), 9646 false, false, 0); 9647 9648 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9649 } else { 9650 const Function *Func = 9651 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9652 CallingConv::ID CC = Func->getCallingConv(); 9653 unsigned NestReg; 9654 9655 switch (CC) { 9656 default: 9657 llvm_unreachable("Unsupported calling convention"); 9658 case CallingConv::C: 9659 case CallingConv::X86_StdCall: { 9660 // Pass 'nest' parameter in ECX. 9661 // Must be kept in sync with X86CallingConv.td 9662 NestReg = X86::ECX; 9663 9664 // Check that ECX wasn't needed by an 'inreg' parameter. 9665 FunctionType *FTy = Func->getFunctionType(); 9666 const AttrListPtr &Attrs = Func->getAttributes(); 9667 9668 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9669 unsigned InRegCount = 0; 9670 unsigned Idx = 1; 9671 9672 for (FunctionType::param_iterator I = FTy->param_begin(), 9673 E = FTy->param_end(); I != E; ++I, ++Idx) 9674 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9675 // FIXME: should only count parameters that are lowered to integers. 9676 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9677 9678 if (InRegCount > 2) { 9679 report_fatal_error("Nest register in use - reduce number of inreg" 9680 " parameters!"); 9681 } 9682 } 9683 break; 9684 } 9685 case CallingConv::X86_FastCall: 9686 case CallingConv::X86_ThisCall: 9687 case CallingConv::Fast: 9688 // Pass 'nest' parameter in EAX. 9689 // Must be kept in sync with X86CallingConv.td 9690 NestReg = X86::EAX; 9691 break; 9692 } 9693 9694 SDValue OutChains[4]; 9695 SDValue Addr, Disp; 9696 9697 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9698 DAG.getConstant(10, MVT::i32)); 9699 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9700 9701 // This is storing the opcode for MOV32ri. 9702 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9703 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9704 OutChains[0] = DAG.getStore(Root, dl, 9705 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9706 Trmp, MachinePointerInfo(TrmpAddr), 9707 false, false, 0); 9708 9709 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9710 DAG.getConstant(1, MVT::i32)); 9711 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9712 MachinePointerInfo(TrmpAddr, 1), 9713 false, false, 1); 9714 9715 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9716 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9717 DAG.getConstant(5, MVT::i32)); 9718 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9719 MachinePointerInfo(TrmpAddr, 5), 9720 false, false, 1); 9721 9722 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9723 DAG.getConstant(6, MVT::i32)); 9724 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9725 MachinePointerInfo(TrmpAddr, 6), 9726 false, false, 1); 9727 9728 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9729 } 9730} 9731 9732SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9733 SelectionDAG &DAG) const { 9734 /* 9735 The rounding mode is in bits 11:10 of FPSR, and has the following 9736 settings: 9737 00 Round to nearest 9738 01 Round to -inf 9739 10 Round to +inf 9740 11 Round to 0 9741 9742 FLT_ROUNDS, on the other hand, expects the following: 9743 -1 Undefined 9744 0 Round to 0 9745 1 Round to nearest 9746 2 Round to +inf 9747 3 Round to -inf 9748 9749 To perform the conversion, we do: 9750 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9751 */ 9752 9753 MachineFunction &MF = DAG.getMachineFunction(); 9754 const TargetMachine &TM = MF.getTarget(); 9755 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9756 unsigned StackAlignment = TFI.getStackAlignment(); 9757 EVT VT = Op.getValueType(); 9758 DebugLoc DL = Op.getDebugLoc(); 9759 9760 // Save FP Control Word to stack slot 9761 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9762 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9763 9764 9765 MachineMemOperand *MMO = 9766 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9767 MachineMemOperand::MOStore, 2, 2); 9768 9769 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9770 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9771 DAG.getVTList(MVT::Other), 9772 Ops, 2, MVT::i16, MMO); 9773 9774 // Load FP Control Word from stack slot 9775 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9776 MachinePointerInfo(), false, false, false, 0); 9777 9778 // Transform as necessary 9779 SDValue CWD1 = 9780 DAG.getNode(ISD::SRL, DL, MVT::i16, 9781 DAG.getNode(ISD::AND, DL, MVT::i16, 9782 CWD, DAG.getConstant(0x800, MVT::i16)), 9783 DAG.getConstant(11, MVT::i8)); 9784 SDValue CWD2 = 9785 DAG.getNode(ISD::SRL, DL, MVT::i16, 9786 DAG.getNode(ISD::AND, DL, MVT::i16, 9787 CWD, DAG.getConstant(0x400, MVT::i16)), 9788 DAG.getConstant(9, MVT::i8)); 9789 9790 SDValue RetVal = 9791 DAG.getNode(ISD::AND, DL, MVT::i16, 9792 DAG.getNode(ISD::ADD, DL, MVT::i16, 9793 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9794 DAG.getConstant(1, MVT::i16)), 9795 DAG.getConstant(3, MVT::i16)); 9796 9797 9798 return DAG.getNode((VT.getSizeInBits() < 16 ? 9799 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9800} 9801 9802SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9803 EVT VT = Op.getValueType(); 9804 EVT OpVT = VT; 9805 unsigned NumBits = VT.getSizeInBits(); 9806 DebugLoc dl = Op.getDebugLoc(); 9807 9808 Op = Op.getOperand(0); 9809 if (VT == MVT::i8) { 9810 // Zero extend to i32 since there is not an i8 bsr. 9811 OpVT = MVT::i32; 9812 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9813 } 9814 9815 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9816 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9817 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9818 9819 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9820 SDValue Ops[] = { 9821 Op, 9822 DAG.getConstant(NumBits+NumBits-1, OpVT), 9823 DAG.getConstant(X86::COND_E, MVT::i8), 9824 Op.getValue(1) 9825 }; 9826 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9827 9828 // Finally xor with NumBits-1. 9829 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9830 9831 if (VT == MVT::i8) 9832 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9833 return Op; 9834} 9835 9836SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 9837 SelectionDAG &DAG) const { 9838 EVT VT = Op.getValueType(); 9839 EVT OpVT = VT; 9840 unsigned NumBits = VT.getSizeInBits(); 9841 DebugLoc dl = Op.getDebugLoc(); 9842 9843 Op = Op.getOperand(0); 9844 if (VT == MVT::i8) { 9845 // Zero extend to i32 since there is not an i8 bsr. 9846 OpVT = MVT::i32; 9847 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9848 } 9849 9850 // Issue a bsr (scan bits in reverse). 9851 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9852 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9853 9854 // And xor with NumBits-1. 9855 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9856 9857 if (VT == MVT::i8) 9858 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9859 return Op; 9860} 9861 9862SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9863 EVT VT = Op.getValueType(); 9864 unsigned NumBits = VT.getSizeInBits(); 9865 DebugLoc dl = Op.getDebugLoc(); 9866 Op = Op.getOperand(0); 9867 9868 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9869 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 9870 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9871 9872 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9873 SDValue Ops[] = { 9874 Op, 9875 DAG.getConstant(NumBits, VT), 9876 DAG.getConstant(X86::COND_E, MVT::i8), 9877 Op.getValue(1) 9878 }; 9879 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 9880} 9881 9882// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 9883// ones, and then concatenate the result back. 9884static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 9885 EVT VT = Op.getValueType(); 9886 9887 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 9888 "Unsupported value type for operation"); 9889 9890 int NumElems = VT.getVectorNumElements(); 9891 DebugLoc dl = Op.getDebugLoc(); 9892 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 9893 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 9894 9895 // Extract the LHS vectors 9896 SDValue LHS = Op.getOperand(0); 9897 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 9898 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 9899 9900 // Extract the RHS vectors 9901 SDValue RHS = Op.getOperand(1); 9902 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 9903 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 9904 9905 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9906 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9907 9908 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9909 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 9910 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 9911} 9912 9913SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 9914 assert(Op.getValueType().getSizeInBits() == 256 && 9915 Op.getValueType().isInteger() && 9916 "Only handle AVX 256-bit vector integer operation"); 9917 return Lower256IntArith(Op, DAG); 9918} 9919 9920SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 9921 assert(Op.getValueType().getSizeInBits() == 256 && 9922 Op.getValueType().isInteger() && 9923 "Only handle AVX 256-bit vector integer operation"); 9924 return Lower256IntArith(Op, DAG); 9925} 9926 9927SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 9928 EVT VT = Op.getValueType(); 9929 9930 // Decompose 256-bit ops into smaller 128-bit ops. 9931 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 9932 return Lower256IntArith(Op, DAG); 9933 9934 DebugLoc dl = Op.getDebugLoc(); 9935 9936 SDValue A = Op.getOperand(0); 9937 SDValue B = Op.getOperand(1); 9938 9939 if (VT == MVT::v4i64) { 9940 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2"); 9941 9942 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32); 9943 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32); 9944 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b ); 9945 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi ); 9946 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b ); 9947 // 9948 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 ); 9949 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 ); 9950 // return AloBlo + AloBhi + AhiBlo; 9951 9952 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9953 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 9954 A, DAG.getConstant(32, MVT::i32)); 9955 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9956 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 9957 B, DAG.getConstant(32, MVT::i32)); 9958 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9959 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9960 A, B); 9961 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9962 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9963 A, Bhi); 9964 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9965 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9966 Ahi, B); 9967 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9968 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 9969 AloBhi, DAG.getConstant(32, MVT::i32)); 9970 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9971 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 9972 AhiBlo, DAG.getConstant(32, MVT::i32)); 9973 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9974 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9975 return Res; 9976 } 9977 9978 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9979 9980 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9981 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9982 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9983 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9984 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9985 // 9986 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9987 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9988 // return AloBlo + AloBhi + AhiBlo; 9989 9990 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9991 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9992 A, DAG.getConstant(32, MVT::i32)); 9993 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9994 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9995 B, DAG.getConstant(32, MVT::i32)); 9996 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9997 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9998 A, B); 9999 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10000 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10001 A, Bhi); 10002 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10003 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10004 Ahi, B); 10005 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10006 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10007 AloBhi, DAG.getConstant(32, MVT::i32)); 10008 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10009 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10010 AhiBlo, DAG.getConstant(32, MVT::i32)); 10011 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10012 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10013 return Res; 10014} 10015 10016SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10017 10018 EVT VT = Op.getValueType(); 10019 DebugLoc dl = Op.getDebugLoc(); 10020 SDValue R = Op.getOperand(0); 10021 SDValue Amt = Op.getOperand(1); 10022 LLVMContext *Context = DAG.getContext(); 10023 10024 if (!Subtarget->hasXMMInt()) 10025 return SDValue(); 10026 10027 // Optimize shl/srl/sra with constant shift amount. 10028 if (isSplatVector(Amt.getNode())) { 10029 SDValue SclrAmt = Amt->getOperand(0); 10030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10031 uint64_t ShiftAmt = C->getZExtValue(); 10032 10033 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) { 10034 // Make a large shift. 10035 SDValue SHL = 10036 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10037 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10038 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10039 // Zero out the rightmost bits. 10040 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10041 MVT::i8)); 10042 return DAG.getNode(ISD::AND, dl, VT, SHL, 10043 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10044 } 10045 10046 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 10047 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10048 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10049 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10050 10051 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 10052 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10053 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10054 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10055 10056 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 10057 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10058 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10059 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10060 10061 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) { 10062 // Make a large shift. 10063 SDValue SRL = 10064 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10065 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10066 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10067 // Zero out the leftmost bits. 10068 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10069 MVT::i8)); 10070 return DAG.getNode(ISD::AND, dl, VT, SRL, 10071 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10072 } 10073 10074 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 10075 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10076 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10077 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10078 10079 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 10080 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10081 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 10082 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10083 10084 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 10085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10086 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10087 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10088 10089 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 10090 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10091 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 10092 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10093 10094 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 10095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10096 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 10097 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10098 10099 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) { 10100 if (ShiftAmt == 7) { 10101 // R s>> 7 === R s< 0 10102 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 10103 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10104 } 10105 10106 // R s>> a === ((R u>> a) ^ m) - m 10107 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10108 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10109 MVT::i8)); 10110 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10111 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10112 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10113 return Res; 10114 } 10115 10116 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10117 if (Op.getOpcode() == ISD::SHL) { 10118 // Make a large shift. 10119 SDValue SHL = 10120 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10121 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 10122 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10123 // Zero out the rightmost bits. 10124 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10125 MVT::i8)); 10126 return DAG.getNode(ISD::AND, dl, VT, SHL, 10127 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10128 } 10129 if (Op.getOpcode() == ISD::SRL) { 10130 // Make a large shift. 10131 SDValue SRL = 10132 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10133 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 10134 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10135 // Zero out the leftmost bits. 10136 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10137 MVT::i8)); 10138 return DAG.getNode(ISD::AND, dl, VT, SRL, 10139 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10140 } 10141 if (Op.getOpcode() == ISD::SRA) { 10142 if (ShiftAmt == 7) { 10143 // R s>> 7 === R s< 0 10144 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 10145 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10146 } 10147 10148 // R s>> a === ((R u>> a) ^ m) - m 10149 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10150 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10151 MVT::i8)); 10152 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10153 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10154 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10155 return Res; 10156 } 10157 } 10158 } 10159 } 10160 10161 // Lower SHL with variable shift amount. 10162 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10163 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10164 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10165 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 10166 10167 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 10168 10169 std::vector<Constant*> CV(4, CI); 10170 Constant *C = ConstantVector::get(CV); 10171 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10172 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10173 MachinePointerInfo::getConstantPool(), 10174 false, false, false, 16); 10175 10176 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10177 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10178 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10179 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10180 } 10181 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10182 assert((Subtarget->hasSSE2() || Subtarget->hasAVX()) && 10183 "Need SSE2 for pslli/pcmpeq."); 10184 10185 // a = a << 5; 10186 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10187 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10188 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 10189 10190 // Turn 'a' into a mask suitable for VSELECT 10191 SDValue VSelM = DAG.getConstant(0x80, VT); 10192 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10193 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10194 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10195 OpVSel, VSelM); 10196 10197 SDValue CM1 = DAG.getConstant(0x0f, VT); 10198 SDValue CM2 = DAG.getConstant(0x3f, VT); 10199 10200 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10201 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10202 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10203 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10204 DAG.getConstant(4, MVT::i32)); 10205 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10206 10207 // a += a 10208 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10209 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10210 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10211 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10212 OpVSel, VSelM); 10213 10214 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10215 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10216 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10217 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10218 DAG.getConstant(2, MVT::i32)); 10219 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10220 10221 // a += a 10222 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10223 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10224 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10225 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32), 10226 OpVSel, VSelM); 10227 10228 // return VSELECT(r, r+r, a); 10229 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10230 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10231 return R; 10232 } 10233 10234 // Decompose 256-bit shifts into smaller 128-bit shifts. 10235 if (VT.getSizeInBits() == 256) { 10236 int NumElems = VT.getVectorNumElements(); 10237 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10238 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10239 10240 // Extract the two vectors 10241 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10242 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10243 DAG, dl); 10244 10245 // Recreate the shift amount vectors 10246 SDValue Amt1, Amt2; 10247 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10248 // Constant shift amount 10249 SmallVector<SDValue, 4> Amt1Csts; 10250 SmallVector<SDValue, 4> Amt2Csts; 10251 for (int i = 0; i < NumElems/2; ++i) 10252 Amt1Csts.push_back(Amt->getOperand(i)); 10253 for (int i = NumElems/2; i < NumElems; ++i) 10254 Amt2Csts.push_back(Amt->getOperand(i)); 10255 10256 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10257 &Amt1Csts[0], NumElems/2); 10258 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10259 &Amt2Csts[0], NumElems/2); 10260 } else { 10261 // Variable shift amount 10262 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10263 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10264 DAG, dl); 10265 } 10266 10267 // Issue new vector shifts for the smaller types 10268 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10269 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10270 10271 // Concatenate the result back 10272 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10273 } 10274 10275 return SDValue(); 10276} 10277 10278SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10279 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10280 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10281 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10282 // has only one use. 10283 SDNode *N = Op.getNode(); 10284 SDValue LHS = N->getOperand(0); 10285 SDValue RHS = N->getOperand(1); 10286 unsigned BaseOp = 0; 10287 unsigned Cond = 0; 10288 DebugLoc DL = Op.getDebugLoc(); 10289 switch (Op.getOpcode()) { 10290 default: llvm_unreachable("Unknown ovf instruction!"); 10291 case ISD::SADDO: 10292 // A subtract of one will be selected as a INC. Note that INC doesn't 10293 // set CF, so we can't do this for UADDO. 10294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10295 if (C->isOne()) { 10296 BaseOp = X86ISD::INC; 10297 Cond = X86::COND_O; 10298 break; 10299 } 10300 BaseOp = X86ISD::ADD; 10301 Cond = X86::COND_O; 10302 break; 10303 case ISD::UADDO: 10304 BaseOp = X86ISD::ADD; 10305 Cond = X86::COND_B; 10306 break; 10307 case ISD::SSUBO: 10308 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10309 // set CF, so we can't do this for USUBO. 10310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10311 if (C->isOne()) { 10312 BaseOp = X86ISD::DEC; 10313 Cond = X86::COND_O; 10314 break; 10315 } 10316 BaseOp = X86ISD::SUB; 10317 Cond = X86::COND_O; 10318 break; 10319 case ISD::USUBO: 10320 BaseOp = X86ISD::SUB; 10321 Cond = X86::COND_B; 10322 break; 10323 case ISD::SMULO: 10324 BaseOp = X86ISD::SMUL; 10325 Cond = X86::COND_O; 10326 break; 10327 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10328 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10329 MVT::i32); 10330 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10331 10332 SDValue SetCC = 10333 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10334 DAG.getConstant(X86::COND_O, MVT::i32), 10335 SDValue(Sum.getNode(), 2)); 10336 10337 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10338 } 10339 } 10340 10341 // Also sets EFLAGS. 10342 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10343 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10344 10345 SDValue SetCC = 10346 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10347 DAG.getConstant(Cond, MVT::i32), 10348 SDValue(Sum.getNode(), 1)); 10349 10350 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10351} 10352 10353SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10354 SelectionDAG &DAG) const { 10355 DebugLoc dl = Op.getDebugLoc(); 10356 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10357 EVT VT = Op.getValueType(); 10358 10359 if (Subtarget->hasXMMInt() && VT.isVector()) { 10360 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10361 ExtraVT.getScalarType().getSizeInBits(); 10362 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10363 10364 unsigned SHLIntrinsicsID = 0; 10365 unsigned SRAIntrinsicsID = 0; 10366 switch (VT.getSimpleVT().SimpleTy) { 10367 default: 10368 return SDValue(); 10369 case MVT::v4i32: 10370 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 10371 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 10372 break; 10373 case MVT::v8i16: 10374 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 10375 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 10376 break; 10377 case MVT::v8i32: 10378 case MVT::v16i16: 10379 if (!Subtarget->hasAVX()) 10380 return SDValue(); 10381 if (!Subtarget->hasAVX2()) { 10382 // needs to be split 10383 int NumElems = VT.getVectorNumElements(); 10384 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10385 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10386 10387 // Extract the LHS vectors 10388 SDValue LHS = Op.getOperand(0); 10389 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10390 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10391 10392 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10393 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10394 10395 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10396 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10397 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10398 ExtraNumElems/2); 10399 SDValue Extra = DAG.getValueType(ExtraVT); 10400 10401 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10402 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10403 10404 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10405 } 10406 if (VT == MVT::v8i32) { 10407 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d; 10408 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d; 10409 } else { 10410 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w; 10411 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w; 10412 } 10413 } 10414 10415 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10416 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 10417 Op.getOperand(0), ShAmt); 10418 10419 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10420 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 10421 Tmp1, ShAmt); 10422 } 10423 10424 return SDValue(); 10425} 10426 10427 10428SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10429 DebugLoc dl = Op.getDebugLoc(); 10430 10431 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10432 // There isn't any reason to disable it if the target processor supports it. 10433 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) { 10434 SDValue Chain = Op.getOperand(0); 10435 SDValue Zero = DAG.getConstant(0, MVT::i32); 10436 SDValue Ops[] = { 10437 DAG.getRegister(X86::ESP, MVT::i32), // Base 10438 DAG.getTargetConstant(1, MVT::i8), // Scale 10439 DAG.getRegister(0, MVT::i32), // Index 10440 DAG.getTargetConstant(0, MVT::i32), // Disp 10441 DAG.getRegister(0, MVT::i32), // Segment. 10442 Zero, 10443 Chain 10444 }; 10445 SDNode *Res = 10446 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10447 array_lengthof(Ops)); 10448 return SDValue(Res, 0); 10449 } 10450 10451 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10452 if (!isDev) 10453 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10454 10455 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10456 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10457 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10458 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10459 10460 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10461 if (!Op1 && !Op2 && !Op3 && Op4) 10462 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10463 10464 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10465 if (Op1 && !Op2 && !Op3 && !Op4) 10466 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10467 10468 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10469 // (MFENCE)>; 10470 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10471} 10472 10473SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10474 SelectionDAG &DAG) const { 10475 DebugLoc dl = Op.getDebugLoc(); 10476 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10477 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10478 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10479 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10480 10481 // The only fence that needs an instruction is a sequentially-consistent 10482 // cross-thread fence. 10483 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10484 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10485 // no-sse2). There isn't any reason to disable it if the target processor 10486 // supports it. 10487 if (Subtarget->hasXMMInt() || Subtarget->is64Bit()) 10488 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10489 10490 SDValue Chain = Op.getOperand(0); 10491 SDValue Zero = DAG.getConstant(0, MVT::i32); 10492 SDValue Ops[] = { 10493 DAG.getRegister(X86::ESP, MVT::i32), // Base 10494 DAG.getTargetConstant(1, MVT::i8), // Scale 10495 DAG.getRegister(0, MVT::i32), // Index 10496 DAG.getTargetConstant(0, MVT::i32), // Disp 10497 DAG.getRegister(0, MVT::i32), // Segment. 10498 Zero, 10499 Chain 10500 }; 10501 SDNode *Res = 10502 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10503 array_lengthof(Ops)); 10504 return SDValue(Res, 0); 10505 } 10506 10507 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10508 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10509} 10510 10511 10512SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10513 EVT T = Op.getValueType(); 10514 DebugLoc DL = Op.getDebugLoc(); 10515 unsigned Reg = 0; 10516 unsigned size = 0; 10517 switch(T.getSimpleVT().SimpleTy) { 10518 default: 10519 assert(false && "Invalid value type!"); 10520 case MVT::i8: Reg = X86::AL; size = 1; break; 10521 case MVT::i16: Reg = X86::AX; size = 2; break; 10522 case MVT::i32: Reg = X86::EAX; size = 4; break; 10523 case MVT::i64: 10524 assert(Subtarget->is64Bit() && "Node not type legal!"); 10525 Reg = X86::RAX; size = 8; 10526 break; 10527 } 10528 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10529 Op.getOperand(2), SDValue()); 10530 SDValue Ops[] = { cpIn.getValue(0), 10531 Op.getOperand(1), 10532 Op.getOperand(3), 10533 DAG.getTargetConstant(size, MVT::i8), 10534 cpIn.getValue(1) }; 10535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10536 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10537 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10538 Ops, 5, T, MMO); 10539 SDValue cpOut = 10540 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10541 return cpOut; 10542} 10543 10544SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10545 SelectionDAG &DAG) const { 10546 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10547 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10548 SDValue TheChain = Op.getOperand(0); 10549 DebugLoc dl = Op.getDebugLoc(); 10550 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10551 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10552 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10553 rax.getValue(2)); 10554 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10555 DAG.getConstant(32, MVT::i8)); 10556 SDValue Ops[] = { 10557 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10558 rdx.getValue(1) 10559 }; 10560 return DAG.getMergeValues(Ops, 2, dl); 10561} 10562 10563SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10564 SelectionDAG &DAG) const { 10565 EVT SrcVT = Op.getOperand(0).getValueType(); 10566 EVT DstVT = Op.getValueType(); 10567 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() && 10568 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10569 assert((DstVT == MVT::i64 || 10570 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10571 "Unexpected custom BITCAST"); 10572 // i64 <=> MMX conversions are Legal. 10573 if (SrcVT==MVT::i64 && DstVT.isVector()) 10574 return Op; 10575 if (DstVT==MVT::i64 && SrcVT.isVector()) 10576 return Op; 10577 // MMX <=> MMX conversions are Legal. 10578 if (SrcVT.isVector() && DstVT.isVector()) 10579 return Op; 10580 // All other conversions need to be expanded. 10581 return SDValue(); 10582} 10583 10584SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10585 SDNode *Node = Op.getNode(); 10586 DebugLoc dl = Node->getDebugLoc(); 10587 EVT T = Node->getValueType(0); 10588 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10589 DAG.getConstant(0, T), Node->getOperand(2)); 10590 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10591 cast<AtomicSDNode>(Node)->getMemoryVT(), 10592 Node->getOperand(0), 10593 Node->getOperand(1), negOp, 10594 cast<AtomicSDNode>(Node)->getSrcValue(), 10595 cast<AtomicSDNode>(Node)->getAlignment(), 10596 cast<AtomicSDNode>(Node)->getOrdering(), 10597 cast<AtomicSDNode>(Node)->getSynchScope()); 10598} 10599 10600static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10601 SDNode *Node = Op.getNode(); 10602 DebugLoc dl = Node->getDebugLoc(); 10603 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10604 10605 // Convert seq_cst store -> xchg 10606 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10607 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10608 // (The only way to get a 16-byte store is cmpxchg16b) 10609 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10610 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10611 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10612 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10613 cast<AtomicSDNode>(Node)->getMemoryVT(), 10614 Node->getOperand(0), 10615 Node->getOperand(1), Node->getOperand(2), 10616 cast<AtomicSDNode>(Node)->getMemOperand(), 10617 cast<AtomicSDNode>(Node)->getOrdering(), 10618 cast<AtomicSDNode>(Node)->getSynchScope()); 10619 return Swap.getValue(1); 10620 } 10621 // Other atomic stores have a simple pattern. 10622 return Op; 10623} 10624 10625static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10626 EVT VT = Op.getNode()->getValueType(0); 10627 10628 // Let legalize expand this if it isn't a legal type yet. 10629 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10630 return SDValue(); 10631 10632 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10633 10634 unsigned Opc; 10635 bool ExtraOp = false; 10636 switch (Op.getOpcode()) { 10637 default: assert(0 && "Invalid code"); 10638 case ISD::ADDC: Opc = X86ISD::ADD; break; 10639 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10640 case ISD::SUBC: Opc = X86ISD::SUB; break; 10641 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10642 } 10643 10644 if (!ExtraOp) 10645 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10646 Op.getOperand(1)); 10647 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10648 Op.getOperand(1), Op.getOperand(2)); 10649} 10650 10651/// LowerOperation - Provide custom lowering hooks for some operations. 10652/// 10653SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10654 switch (Op.getOpcode()) { 10655 default: llvm_unreachable("Should not custom lower this!"); 10656 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10657 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10658 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10659 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10660 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10661 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10662 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10663 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10664 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10665 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10666 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10667 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10668 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10669 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10670 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10671 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10672 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10673 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10674 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10675 case ISD::SHL_PARTS: 10676 case ISD::SRA_PARTS: 10677 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10678 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10679 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10680 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10681 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10682 case ISD::FABS: return LowerFABS(Op, DAG); 10683 case ISD::FNEG: return LowerFNEG(Op, DAG); 10684 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10685 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10686 case ISD::SETCC: return LowerSETCC(Op, DAG); 10687 case ISD::SELECT: return LowerSELECT(Op, DAG); 10688 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10689 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10690 case ISD::VASTART: return LowerVASTART(Op, DAG); 10691 case ISD::VAARG: return LowerVAARG(Op, DAG); 10692 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10693 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10694 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10695 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10696 case ISD::FRAME_TO_ARGS_OFFSET: 10697 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10698 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10699 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10700 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10701 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10702 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10703 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10704 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10705 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10706 case ISD::MUL: return LowerMUL(Op, DAG); 10707 case ISD::SRA: 10708 case ISD::SRL: 10709 case ISD::SHL: return LowerShift(Op, DAG); 10710 case ISD::SADDO: 10711 case ISD::UADDO: 10712 case ISD::SSUBO: 10713 case ISD::USUBO: 10714 case ISD::SMULO: 10715 case ISD::UMULO: return LowerXALUO(Op, DAG); 10716 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10717 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10718 case ISD::ADDC: 10719 case ISD::ADDE: 10720 case ISD::SUBC: 10721 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10722 case ISD::ADD: return LowerADD(Op, DAG); 10723 case ISD::SUB: return LowerSUB(Op, DAG); 10724 } 10725} 10726 10727static void ReplaceATOMIC_LOAD(SDNode *Node, 10728 SmallVectorImpl<SDValue> &Results, 10729 SelectionDAG &DAG) { 10730 DebugLoc dl = Node->getDebugLoc(); 10731 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10732 10733 // Convert wide load -> cmpxchg8b/cmpxchg16b 10734 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10735 // (The only way to get a 16-byte load is cmpxchg16b) 10736 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10737 SDValue Zero = DAG.getConstant(0, VT); 10738 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10739 Node->getOperand(0), 10740 Node->getOperand(1), Zero, Zero, 10741 cast<AtomicSDNode>(Node)->getMemOperand(), 10742 cast<AtomicSDNode>(Node)->getOrdering(), 10743 cast<AtomicSDNode>(Node)->getSynchScope()); 10744 Results.push_back(Swap.getValue(0)); 10745 Results.push_back(Swap.getValue(1)); 10746} 10747 10748void X86TargetLowering:: 10749ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10750 SelectionDAG &DAG, unsigned NewOp) const { 10751 DebugLoc dl = Node->getDebugLoc(); 10752 assert (Node->getValueType(0) == MVT::i64 && 10753 "Only know how to expand i64 atomics"); 10754 10755 SDValue Chain = Node->getOperand(0); 10756 SDValue In1 = Node->getOperand(1); 10757 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10758 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10759 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10760 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10761 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10762 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10763 SDValue Result = 10764 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10765 cast<MemSDNode>(Node)->getMemOperand()); 10766 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10767 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10768 Results.push_back(Result.getValue(2)); 10769} 10770 10771/// ReplaceNodeResults - Replace a node with an illegal result type 10772/// with a new node built out of custom code. 10773void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10774 SmallVectorImpl<SDValue>&Results, 10775 SelectionDAG &DAG) const { 10776 DebugLoc dl = N->getDebugLoc(); 10777 switch (N->getOpcode()) { 10778 default: 10779 assert(false && "Do not know how to custom type legalize this operation!"); 10780 return; 10781 case ISD::SIGN_EXTEND_INREG: 10782 case ISD::ADDC: 10783 case ISD::ADDE: 10784 case ISD::SUBC: 10785 case ISD::SUBE: 10786 // We don't want to expand or promote these. 10787 return; 10788 case ISD::FP_TO_SINT: { 10789 std::pair<SDValue,SDValue> Vals = 10790 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10791 SDValue FIST = Vals.first, StackSlot = Vals.second; 10792 if (FIST.getNode() != 0) { 10793 EVT VT = N->getValueType(0); 10794 // Return a load from the stack slot. 10795 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10796 MachinePointerInfo(), 10797 false, false, false, 0)); 10798 } 10799 return; 10800 } 10801 case ISD::READCYCLECOUNTER: { 10802 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10803 SDValue TheChain = N->getOperand(0); 10804 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10805 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10806 rd.getValue(1)); 10807 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10808 eax.getValue(2)); 10809 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10810 SDValue Ops[] = { eax, edx }; 10811 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10812 Results.push_back(edx.getValue(1)); 10813 return; 10814 } 10815 case ISD::ATOMIC_CMP_SWAP: { 10816 EVT T = N->getValueType(0); 10817 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10818 bool Regs64bit = T == MVT::i128; 10819 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10820 SDValue cpInL, cpInH; 10821 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10822 DAG.getConstant(0, HalfT)); 10823 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10824 DAG.getConstant(1, HalfT)); 10825 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10826 Regs64bit ? X86::RAX : X86::EAX, 10827 cpInL, SDValue()); 10828 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10829 Regs64bit ? X86::RDX : X86::EDX, 10830 cpInH, cpInL.getValue(1)); 10831 SDValue swapInL, swapInH; 10832 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10833 DAG.getConstant(0, HalfT)); 10834 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10835 DAG.getConstant(1, HalfT)); 10836 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10837 Regs64bit ? X86::RBX : X86::EBX, 10838 swapInL, cpInH.getValue(1)); 10839 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10840 Regs64bit ? X86::RCX : X86::ECX, 10841 swapInH, swapInL.getValue(1)); 10842 SDValue Ops[] = { swapInH.getValue(0), 10843 N->getOperand(1), 10844 swapInH.getValue(1) }; 10845 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10846 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10847 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10848 X86ISD::LCMPXCHG8_DAG; 10849 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10850 Ops, 3, T, MMO); 10851 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10852 Regs64bit ? X86::RAX : X86::EAX, 10853 HalfT, Result.getValue(1)); 10854 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10855 Regs64bit ? X86::RDX : X86::EDX, 10856 HalfT, cpOutL.getValue(2)); 10857 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10858 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10859 Results.push_back(cpOutH.getValue(1)); 10860 return; 10861 } 10862 case ISD::ATOMIC_LOAD_ADD: 10863 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10864 return; 10865 case ISD::ATOMIC_LOAD_AND: 10866 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10867 return; 10868 case ISD::ATOMIC_LOAD_NAND: 10869 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10870 return; 10871 case ISD::ATOMIC_LOAD_OR: 10872 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10873 return; 10874 case ISD::ATOMIC_LOAD_SUB: 10875 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10876 return; 10877 case ISD::ATOMIC_LOAD_XOR: 10878 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10879 return; 10880 case ISD::ATOMIC_SWAP: 10881 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10882 return; 10883 case ISD::ATOMIC_LOAD: 10884 ReplaceATOMIC_LOAD(N, Results, DAG); 10885 } 10886} 10887 10888const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10889 switch (Opcode) { 10890 default: return NULL; 10891 case X86ISD::BSF: return "X86ISD::BSF"; 10892 case X86ISD::BSR: return "X86ISD::BSR"; 10893 case X86ISD::SHLD: return "X86ISD::SHLD"; 10894 case X86ISD::SHRD: return "X86ISD::SHRD"; 10895 case X86ISD::FAND: return "X86ISD::FAND"; 10896 case X86ISD::FOR: return "X86ISD::FOR"; 10897 case X86ISD::FXOR: return "X86ISD::FXOR"; 10898 case X86ISD::FSRL: return "X86ISD::FSRL"; 10899 case X86ISD::FILD: return "X86ISD::FILD"; 10900 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10901 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10902 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10903 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10904 case X86ISD::FLD: return "X86ISD::FLD"; 10905 case X86ISD::FST: return "X86ISD::FST"; 10906 case X86ISD::CALL: return "X86ISD::CALL"; 10907 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10908 case X86ISD::BT: return "X86ISD::BT"; 10909 case X86ISD::CMP: return "X86ISD::CMP"; 10910 case X86ISD::COMI: return "X86ISD::COMI"; 10911 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10912 case X86ISD::SETCC: return "X86ISD::SETCC"; 10913 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10914 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10915 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10916 case X86ISD::CMOV: return "X86ISD::CMOV"; 10917 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10918 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10919 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10920 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10921 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10922 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10923 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10924 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10925 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10926 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10927 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10928 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10929 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10930 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10931 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 10932 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 10933 case X86ISD::HADD: return "X86ISD::HADD"; 10934 case X86ISD::HSUB: return "X86ISD::HSUB"; 10935 case X86ISD::FHADD: return "X86ISD::FHADD"; 10936 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 10937 case X86ISD::FMAX: return "X86ISD::FMAX"; 10938 case X86ISD::FMIN: return "X86ISD::FMIN"; 10939 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10940 case X86ISD::FRCP: return "X86ISD::FRCP"; 10941 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 10942 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 10943 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 10944 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 10945 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 10946 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 10947 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 10948 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 10949 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 10950 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 10951 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 10952 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 10953 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 10954 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 10955 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 10956 case X86ISD::VSHL: return "X86ISD::VSHL"; 10957 case X86ISD::VSRL: return "X86ISD::VSRL"; 10958 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 10959 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 10960 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 10961 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 10962 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 10963 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 10964 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 10965 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 10966 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 10967 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 10968 case X86ISD::ADD: return "X86ISD::ADD"; 10969 case X86ISD::SUB: return "X86ISD::SUB"; 10970 case X86ISD::ADC: return "X86ISD::ADC"; 10971 case X86ISD::SBB: return "X86ISD::SBB"; 10972 case X86ISD::SMUL: return "X86ISD::SMUL"; 10973 case X86ISD::UMUL: return "X86ISD::UMUL"; 10974 case X86ISD::INC: return "X86ISD::INC"; 10975 case X86ISD::DEC: return "X86ISD::DEC"; 10976 case X86ISD::OR: return "X86ISD::OR"; 10977 case X86ISD::XOR: return "X86ISD::XOR"; 10978 case X86ISD::AND: return "X86ISD::AND"; 10979 case X86ISD::ANDN: return "X86ISD::ANDN"; 10980 case X86ISD::BLSI: return "X86ISD::BLSI"; 10981 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 10982 case X86ISD::BLSR: return "X86ISD::BLSR"; 10983 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 10984 case X86ISD::PTEST: return "X86ISD::PTEST"; 10985 case X86ISD::TESTP: return "X86ISD::TESTP"; 10986 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 10987 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 10988 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 10989 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 10990 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10991 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 10992 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 10993 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10994 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10995 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10996 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10997 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10998 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 10999 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11000 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11001 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 11002 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 11003 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11004 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11005 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11006 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11007 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11008 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11009 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11010 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11011 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11012 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11013 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11014 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11015 } 11016} 11017 11018// isLegalAddressingMode - Return true if the addressing mode represented 11019// by AM is legal for this target, for a load/store of the specified type. 11020bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11021 Type *Ty) const { 11022 // X86 supports extremely general addressing modes. 11023 CodeModel::Model M = getTargetMachine().getCodeModel(); 11024 Reloc::Model R = getTargetMachine().getRelocationModel(); 11025 11026 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11027 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11028 return false; 11029 11030 if (AM.BaseGV) { 11031 unsigned GVFlags = 11032 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11033 11034 // If a reference to this global requires an extra load, we can't fold it. 11035 if (isGlobalStubReference(GVFlags)) 11036 return false; 11037 11038 // If BaseGV requires a register for the PIC base, we cannot also have a 11039 // BaseReg specified. 11040 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11041 return false; 11042 11043 // If lower 4G is not available, then we must use rip-relative addressing. 11044 if ((M != CodeModel::Small || R != Reloc::Static) && 11045 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11046 return false; 11047 } 11048 11049 switch (AM.Scale) { 11050 case 0: 11051 case 1: 11052 case 2: 11053 case 4: 11054 case 8: 11055 // These scales always work. 11056 break; 11057 case 3: 11058 case 5: 11059 case 9: 11060 // These scales are formed with basereg+scalereg. Only accept if there is 11061 // no basereg yet. 11062 if (AM.HasBaseReg) 11063 return false; 11064 break; 11065 default: // Other stuff never works. 11066 return false; 11067 } 11068 11069 return true; 11070} 11071 11072 11073bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11074 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11075 return false; 11076 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11077 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11078 if (NumBits1 <= NumBits2) 11079 return false; 11080 return true; 11081} 11082 11083bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11084 if (!VT1.isInteger() || !VT2.isInteger()) 11085 return false; 11086 unsigned NumBits1 = VT1.getSizeInBits(); 11087 unsigned NumBits2 = VT2.getSizeInBits(); 11088 if (NumBits1 <= NumBits2) 11089 return false; 11090 return true; 11091} 11092 11093bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11094 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11095 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11096} 11097 11098bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11099 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11100 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11101} 11102 11103bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11104 // i16 instructions are longer (0x66 prefix) and potentially slower. 11105 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11106} 11107 11108/// isShuffleMaskLegal - Targets can use this to indicate that they only 11109/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11110/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11111/// are assumed to be legal. 11112bool 11113X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11114 EVT VT) const { 11115 // Very little shuffling can be done for 64-bit vectors right now. 11116 if (VT.getSizeInBits() == 64) 11117 return false; 11118 11119 // FIXME: pshufb, blends, shifts. 11120 return (VT.getVectorNumElements() == 2 || 11121 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11122 isMOVLMask(M, VT) || 11123 isSHUFPMask(M, VT) || 11124 isPSHUFDMask(M, VT) || 11125 isPSHUFHWMask(M, VT) || 11126 isPSHUFLWMask(M, VT) || 11127 isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()) || 11128 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11129 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11130 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11131 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11132} 11133 11134bool 11135X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11136 EVT VT) const { 11137 unsigned NumElts = VT.getVectorNumElements(); 11138 // FIXME: This collection of masks seems suspect. 11139 if (NumElts == 2) 11140 return true; 11141 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11142 return (isMOVLMask(Mask, VT) || 11143 isCommutedMOVLMask(Mask, VT, true) || 11144 isSHUFPMask(Mask, VT) || 11145 isSHUFPMask(Mask, VT, /* Commuted */ true)); 11146 } 11147 return false; 11148} 11149 11150//===----------------------------------------------------------------------===// 11151// X86 Scheduler Hooks 11152//===----------------------------------------------------------------------===// 11153 11154// private utility function 11155MachineBasicBlock * 11156X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11157 MachineBasicBlock *MBB, 11158 unsigned regOpc, 11159 unsigned immOpc, 11160 unsigned LoadOpc, 11161 unsigned CXchgOpc, 11162 unsigned notOpc, 11163 unsigned EAXreg, 11164 TargetRegisterClass *RC, 11165 bool invSrc) const { 11166 // For the atomic bitwise operator, we generate 11167 // thisMBB: 11168 // newMBB: 11169 // ld t1 = [bitinstr.addr] 11170 // op t2 = t1, [bitinstr.val] 11171 // mov EAX = t1 11172 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11173 // bz newMBB 11174 // fallthrough -->nextMBB 11175 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11176 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11177 MachineFunction::iterator MBBIter = MBB; 11178 ++MBBIter; 11179 11180 /// First build the CFG 11181 MachineFunction *F = MBB->getParent(); 11182 MachineBasicBlock *thisMBB = MBB; 11183 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11184 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11185 F->insert(MBBIter, newMBB); 11186 F->insert(MBBIter, nextMBB); 11187 11188 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11189 nextMBB->splice(nextMBB->begin(), thisMBB, 11190 llvm::next(MachineBasicBlock::iterator(bInstr)), 11191 thisMBB->end()); 11192 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11193 11194 // Update thisMBB to fall through to newMBB 11195 thisMBB->addSuccessor(newMBB); 11196 11197 // newMBB jumps to itself and fall through to nextMBB 11198 newMBB->addSuccessor(nextMBB); 11199 newMBB->addSuccessor(newMBB); 11200 11201 // Insert instructions into newMBB based on incoming instruction 11202 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11203 "unexpected number of operands"); 11204 DebugLoc dl = bInstr->getDebugLoc(); 11205 MachineOperand& destOper = bInstr->getOperand(0); 11206 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11207 int numArgs = bInstr->getNumOperands() - 1; 11208 for (int i=0; i < numArgs; ++i) 11209 argOpers[i] = &bInstr->getOperand(i+1); 11210 11211 // x86 address has 4 operands: base, index, scale, and displacement 11212 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11213 int valArgIndx = lastAddrIndx + 1; 11214 11215 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11216 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11217 for (int i=0; i <= lastAddrIndx; ++i) 11218 (*MIB).addOperand(*argOpers[i]); 11219 11220 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11221 if (invSrc) { 11222 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11223 } 11224 else 11225 tt = t1; 11226 11227 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11228 assert((argOpers[valArgIndx]->isReg() || 11229 argOpers[valArgIndx]->isImm()) && 11230 "invalid operand"); 11231 if (argOpers[valArgIndx]->isReg()) 11232 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11233 else 11234 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11235 MIB.addReg(tt); 11236 (*MIB).addOperand(*argOpers[valArgIndx]); 11237 11238 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11239 MIB.addReg(t1); 11240 11241 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11242 for (int i=0; i <= lastAddrIndx; ++i) 11243 (*MIB).addOperand(*argOpers[i]); 11244 MIB.addReg(t2); 11245 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11246 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11247 bInstr->memoperands_end()); 11248 11249 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11250 MIB.addReg(EAXreg); 11251 11252 // insert branch 11253 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11254 11255 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11256 return nextMBB; 11257} 11258 11259// private utility function: 64 bit atomics on 32 bit host. 11260MachineBasicBlock * 11261X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11262 MachineBasicBlock *MBB, 11263 unsigned regOpcL, 11264 unsigned regOpcH, 11265 unsigned immOpcL, 11266 unsigned immOpcH, 11267 bool invSrc) const { 11268 // For the atomic bitwise operator, we generate 11269 // thisMBB (instructions are in pairs, except cmpxchg8b) 11270 // ld t1,t2 = [bitinstr.addr] 11271 // newMBB: 11272 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11273 // op t5, t6 <- out1, out2, [bitinstr.val] 11274 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11275 // mov ECX, EBX <- t5, t6 11276 // mov EAX, EDX <- t1, t2 11277 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11278 // mov t3, t4 <- EAX, EDX 11279 // bz newMBB 11280 // result in out1, out2 11281 // fallthrough -->nextMBB 11282 11283 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11284 const unsigned LoadOpc = X86::MOV32rm; 11285 const unsigned NotOpc = X86::NOT32r; 11286 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11287 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11288 MachineFunction::iterator MBBIter = MBB; 11289 ++MBBIter; 11290 11291 /// First build the CFG 11292 MachineFunction *F = MBB->getParent(); 11293 MachineBasicBlock *thisMBB = MBB; 11294 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11295 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11296 F->insert(MBBIter, newMBB); 11297 F->insert(MBBIter, nextMBB); 11298 11299 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11300 nextMBB->splice(nextMBB->begin(), thisMBB, 11301 llvm::next(MachineBasicBlock::iterator(bInstr)), 11302 thisMBB->end()); 11303 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11304 11305 // Update thisMBB to fall through to newMBB 11306 thisMBB->addSuccessor(newMBB); 11307 11308 // newMBB jumps to itself and fall through to nextMBB 11309 newMBB->addSuccessor(nextMBB); 11310 newMBB->addSuccessor(newMBB); 11311 11312 DebugLoc dl = bInstr->getDebugLoc(); 11313 // Insert instructions into newMBB based on incoming instruction 11314 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11315 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11316 "unexpected number of operands"); 11317 MachineOperand& dest1Oper = bInstr->getOperand(0); 11318 MachineOperand& dest2Oper = bInstr->getOperand(1); 11319 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11320 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11321 argOpers[i] = &bInstr->getOperand(i+2); 11322 11323 // We use some of the operands multiple times, so conservatively just 11324 // clear any kill flags that might be present. 11325 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11326 argOpers[i]->setIsKill(false); 11327 } 11328 11329 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11330 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11331 11332 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11333 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11334 for (int i=0; i <= lastAddrIndx; ++i) 11335 (*MIB).addOperand(*argOpers[i]); 11336 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11337 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11338 // add 4 to displacement. 11339 for (int i=0; i <= lastAddrIndx-2; ++i) 11340 (*MIB).addOperand(*argOpers[i]); 11341 MachineOperand newOp3 = *(argOpers[3]); 11342 if (newOp3.isImm()) 11343 newOp3.setImm(newOp3.getImm()+4); 11344 else 11345 newOp3.setOffset(newOp3.getOffset()+4); 11346 (*MIB).addOperand(newOp3); 11347 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11348 11349 // t3/4 are defined later, at the bottom of the loop 11350 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11351 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11352 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11353 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11354 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11355 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11356 11357 // The subsequent operations should be using the destination registers of 11358 //the PHI instructions. 11359 if (invSrc) { 11360 t1 = F->getRegInfo().createVirtualRegister(RC); 11361 t2 = F->getRegInfo().createVirtualRegister(RC); 11362 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11363 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11364 } else { 11365 t1 = dest1Oper.getReg(); 11366 t2 = dest2Oper.getReg(); 11367 } 11368 11369 int valArgIndx = lastAddrIndx + 1; 11370 assert((argOpers[valArgIndx]->isReg() || 11371 argOpers[valArgIndx]->isImm()) && 11372 "invalid operand"); 11373 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11374 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11375 if (argOpers[valArgIndx]->isReg()) 11376 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11377 else 11378 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11379 if (regOpcL != X86::MOV32rr) 11380 MIB.addReg(t1); 11381 (*MIB).addOperand(*argOpers[valArgIndx]); 11382 assert(argOpers[valArgIndx + 1]->isReg() == 11383 argOpers[valArgIndx]->isReg()); 11384 assert(argOpers[valArgIndx + 1]->isImm() == 11385 argOpers[valArgIndx]->isImm()); 11386 if (argOpers[valArgIndx + 1]->isReg()) 11387 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11388 else 11389 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11390 if (regOpcH != X86::MOV32rr) 11391 MIB.addReg(t2); 11392 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11393 11394 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11395 MIB.addReg(t1); 11396 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11397 MIB.addReg(t2); 11398 11399 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11400 MIB.addReg(t5); 11401 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11402 MIB.addReg(t6); 11403 11404 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11405 for (int i=0; i <= lastAddrIndx; ++i) 11406 (*MIB).addOperand(*argOpers[i]); 11407 11408 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11409 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11410 bInstr->memoperands_end()); 11411 11412 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11413 MIB.addReg(X86::EAX); 11414 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11415 MIB.addReg(X86::EDX); 11416 11417 // insert branch 11418 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11419 11420 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11421 return nextMBB; 11422} 11423 11424// private utility function 11425MachineBasicBlock * 11426X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11427 MachineBasicBlock *MBB, 11428 unsigned cmovOpc) const { 11429 // For the atomic min/max operator, we generate 11430 // thisMBB: 11431 // newMBB: 11432 // ld t1 = [min/max.addr] 11433 // mov t2 = [min/max.val] 11434 // cmp t1, t2 11435 // cmov[cond] t2 = t1 11436 // mov EAX = t1 11437 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11438 // bz newMBB 11439 // fallthrough -->nextMBB 11440 // 11441 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11442 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11443 MachineFunction::iterator MBBIter = MBB; 11444 ++MBBIter; 11445 11446 /// First build the CFG 11447 MachineFunction *F = MBB->getParent(); 11448 MachineBasicBlock *thisMBB = MBB; 11449 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11450 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11451 F->insert(MBBIter, newMBB); 11452 F->insert(MBBIter, nextMBB); 11453 11454 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11455 nextMBB->splice(nextMBB->begin(), thisMBB, 11456 llvm::next(MachineBasicBlock::iterator(mInstr)), 11457 thisMBB->end()); 11458 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11459 11460 // Update thisMBB to fall through to newMBB 11461 thisMBB->addSuccessor(newMBB); 11462 11463 // newMBB jumps to newMBB and fall through to nextMBB 11464 newMBB->addSuccessor(nextMBB); 11465 newMBB->addSuccessor(newMBB); 11466 11467 DebugLoc dl = mInstr->getDebugLoc(); 11468 // Insert instructions into newMBB based on incoming instruction 11469 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11470 "unexpected number of operands"); 11471 MachineOperand& destOper = mInstr->getOperand(0); 11472 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11473 int numArgs = mInstr->getNumOperands() - 1; 11474 for (int i=0; i < numArgs; ++i) 11475 argOpers[i] = &mInstr->getOperand(i+1); 11476 11477 // x86 address has 4 operands: base, index, scale, and displacement 11478 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11479 int valArgIndx = lastAddrIndx + 1; 11480 11481 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11482 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11483 for (int i=0; i <= lastAddrIndx; ++i) 11484 (*MIB).addOperand(*argOpers[i]); 11485 11486 // We only support register and immediate values 11487 assert((argOpers[valArgIndx]->isReg() || 11488 argOpers[valArgIndx]->isImm()) && 11489 "invalid operand"); 11490 11491 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11492 if (argOpers[valArgIndx]->isReg()) 11493 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11494 else 11495 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11496 (*MIB).addOperand(*argOpers[valArgIndx]); 11497 11498 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11499 MIB.addReg(t1); 11500 11501 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11502 MIB.addReg(t1); 11503 MIB.addReg(t2); 11504 11505 // Generate movc 11506 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11507 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11508 MIB.addReg(t2); 11509 MIB.addReg(t1); 11510 11511 // Cmp and exchange if none has modified the memory location 11512 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11513 for (int i=0; i <= lastAddrIndx; ++i) 11514 (*MIB).addOperand(*argOpers[i]); 11515 MIB.addReg(t3); 11516 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11517 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11518 mInstr->memoperands_end()); 11519 11520 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11521 MIB.addReg(X86::EAX); 11522 11523 // insert branch 11524 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11525 11526 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11527 return nextMBB; 11528} 11529 11530// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11531// or XMM0_V32I8 in AVX all of this code can be replaced with that 11532// in the .td file. 11533MachineBasicBlock * 11534X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11535 unsigned numArgs, bool memArg) const { 11536 assert(Subtarget->hasSSE42orAVX() && 11537 "Target must have SSE4.2 or AVX features enabled"); 11538 11539 DebugLoc dl = MI->getDebugLoc(); 11540 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11541 unsigned Opc; 11542 if (!Subtarget->hasAVX()) { 11543 if (memArg) 11544 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11545 else 11546 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11547 } else { 11548 if (memArg) 11549 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11550 else 11551 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11552 } 11553 11554 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11555 for (unsigned i = 0; i < numArgs; ++i) { 11556 MachineOperand &Op = MI->getOperand(i+1); 11557 if (!(Op.isReg() && Op.isImplicit())) 11558 MIB.addOperand(Op); 11559 } 11560 BuildMI(*BB, MI, dl, 11561 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11562 MI->getOperand(0).getReg()) 11563 .addReg(X86::XMM0); 11564 11565 MI->eraseFromParent(); 11566 return BB; 11567} 11568 11569MachineBasicBlock * 11570X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11571 DebugLoc dl = MI->getDebugLoc(); 11572 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11573 11574 // Address into RAX/EAX, other two args into ECX, EDX. 11575 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11576 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11577 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11578 for (int i = 0; i < X86::AddrNumOperands; ++i) 11579 MIB.addOperand(MI->getOperand(i)); 11580 11581 unsigned ValOps = X86::AddrNumOperands; 11582 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11583 .addReg(MI->getOperand(ValOps).getReg()); 11584 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11585 .addReg(MI->getOperand(ValOps+1).getReg()); 11586 11587 // The instruction doesn't actually take any operands though. 11588 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11589 11590 MI->eraseFromParent(); // The pseudo is gone now. 11591 return BB; 11592} 11593 11594MachineBasicBlock * 11595X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11596 DebugLoc dl = MI->getDebugLoc(); 11597 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11598 11599 // First arg in ECX, the second in EAX. 11600 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11601 .addReg(MI->getOperand(0).getReg()); 11602 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11603 .addReg(MI->getOperand(1).getReg()); 11604 11605 // The instruction doesn't actually take any operands though. 11606 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11607 11608 MI->eraseFromParent(); // The pseudo is gone now. 11609 return BB; 11610} 11611 11612MachineBasicBlock * 11613X86TargetLowering::EmitVAARG64WithCustomInserter( 11614 MachineInstr *MI, 11615 MachineBasicBlock *MBB) const { 11616 // Emit va_arg instruction on X86-64. 11617 11618 // Operands to this pseudo-instruction: 11619 // 0 ) Output : destination address (reg) 11620 // 1-5) Input : va_list address (addr, i64mem) 11621 // 6 ) ArgSize : Size (in bytes) of vararg type 11622 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11623 // 8 ) Align : Alignment of type 11624 // 9 ) EFLAGS (implicit-def) 11625 11626 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11627 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11628 11629 unsigned DestReg = MI->getOperand(0).getReg(); 11630 MachineOperand &Base = MI->getOperand(1); 11631 MachineOperand &Scale = MI->getOperand(2); 11632 MachineOperand &Index = MI->getOperand(3); 11633 MachineOperand &Disp = MI->getOperand(4); 11634 MachineOperand &Segment = MI->getOperand(5); 11635 unsigned ArgSize = MI->getOperand(6).getImm(); 11636 unsigned ArgMode = MI->getOperand(7).getImm(); 11637 unsigned Align = MI->getOperand(8).getImm(); 11638 11639 // Memory Reference 11640 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11641 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11642 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11643 11644 // Machine Information 11645 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11646 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11647 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11648 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11649 DebugLoc DL = MI->getDebugLoc(); 11650 11651 // struct va_list { 11652 // i32 gp_offset 11653 // i32 fp_offset 11654 // i64 overflow_area (address) 11655 // i64 reg_save_area (address) 11656 // } 11657 // sizeof(va_list) = 24 11658 // alignment(va_list) = 8 11659 11660 unsigned TotalNumIntRegs = 6; 11661 unsigned TotalNumXMMRegs = 8; 11662 bool UseGPOffset = (ArgMode == 1); 11663 bool UseFPOffset = (ArgMode == 2); 11664 unsigned MaxOffset = TotalNumIntRegs * 8 + 11665 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11666 11667 /* Align ArgSize to a multiple of 8 */ 11668 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11669 bool NeedsAlign = (Align > 8); 11670 11671 MachineBasicBlock *thisMBB = MBB; 11672 MachineBasicBlock *overflowMBB; 11673 MachineBasicBlock *offsetMBB; 11674 MachineBasicBlock *endMBB; 11675 11676 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11677 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11678 unsigned OffsetReg = 0; 11679 11680 if (!UseGPOffset && !UseFPOffset) { 11681 // If we only pull from the overflow region, we don't create a branch. 11682 // We don't need to alter control flow. 11683 OffsetDestReg = 0; // unused 11684 OverflowDestReg = DestReg; 11685 11686 offsetMBB = NULL; 11687 overflowMBB = thisMBB; 11688 endMBB = thisMBB; 11689 } else { 11690 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11691 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11692 // If not, pull from overflow_area. (branch to overflowMBB) 11693 // 11694 // thisMBB 11695 // | . 11696 // | . 11697 // offsetMBB overflowMBB 11698 // | . 11699 // | . 11700 // endMBB 11701 11702 // Registers for the PHI in endMBB 11703 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11704 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11705 11706 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11707 MachineFunction *MF = MBB->getParent(); 11708 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11709 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11710 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11711 11712 MachineFunction::iterator MBBIter = MBB; 11713 ++MBBIter; 11714 11715 // Insert the new basic blocks 11716 MF->insert(MBBIter, offsetMBB); 11717 MF->insert(MBBIter, overflowMBB); 11718 MF->insert(MBBIter, endMBB); 11719 11720 // Transfer the remainder of MBB and its successor edges to endMBB. 11721 endMBB->splice(endMBB->begin(), thisMBB, 11722 llvm::next(MachineBasicBlock::iterator(MI)), 11723 thisMBB->end()); 11724 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11725 11726 // Make offsetMBB and overflowMBB successors of thisMBB 11727 thisMBB->addSuccessor(offsetMBB); 11728 thisMBB->addSuccessor(overflowMBB); 11729 11730 // endMBB is a successor of both offsetMBB and overflowMBB 11731 offsetMBB->addSuccessor(endMBB); 11732 overflowMBB->addSuccessor(endMBB); 11733 11734 // Load the offset value into a register 11735 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11736 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11737 .addOperand(Base) 11738 .addOperand(Scale) 11739 .addOperand(Index) 11740 .addDisp(Disp, UseFPOffset ? 4 : 0) 11741 .addOperand(Segment) 11742 .setMemRefs(MMOBegin, MMOEnd); 11743 11744 // Check if there is enough room left to pull this argument. 11745 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11746 .addReg(OffsetReg) 11747 .addImm(MaxOffset + 8 - ArgSizeA8); 11748 11749 // Branch to "overflowMBB" if offset >= max 11750 // Fall through to "offsetMBB" otherwise 11751 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11752 .addMBB(overflowMBB); 11753 } 11754 11755 // In offsetMBB, emit code to use the reg_save_area. 11756 if (offsetMBB) { 11757 assert(OffsetReg != 0); 11758 11759 // Read the reg_save_area address. 11760 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11761 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11762 .addOperand(Base) 11763 .addOperand(Scale) 11764 .addOperand(Index) 11765 .addDisp(Disp, 16) 11766 .addOperand(Segment) 11767 .setMemRefs(MMOBegin, MMOEnd); 11768 11769 // Zero-extend the offset 11770 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11771 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11772 .addImm(0) 11773 .addReg(OffsetReg) 11774 .addImm(X86::sub_32bit); 11775 11776 // Add the offset to the reg_save_area to get the final address. 11777 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11778 .addReg(OffsetReg64) 11779 .addReg(RegSaveReg); 11780 11781 // Compute the offset for the next argument 11782 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11783 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11784 .addReg(OffsetReg) 11785 .addImm(UseFPOffset ? 16 : 8); 11786 11787 // Store it back into the va_list. 11788 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11789 .addOperand(Base) 11790 .addOperand(Scale) 11791 .addOperand(Index) 11792 .addDisp(Disp, UseFPOffset ? 4 : 0) 11793 .addOperand(Segment) 11794 .addReg(NextOffsetReg) 11795 .setMemRefs(MMOBegin, MMOEnd); 11796 11797 // Jump to endMBB 11798 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11799 .addMBB(endMBB); 11800 } 11801 11802 // 11803 // Emit code to use overflow area 11804 // 11805 11806 // Load the overflow_area address into a register. 11807 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11808 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11809 .addOperand(Base) 11810 .addOperand(Scale) 11811 .addOperand(Index) 11812 .addDisp(Disp, 8) 11813 .addOperand(Segment) 11814 .setMemRefs(MMOBegin, MMOEnd); 11815 11816 // If we need to align it, do so. Otherwise, just copy the address 11817 // to OverflowDestReg. 11818 if (NeedsAlign) { 11819 // Align the overflow address 11820 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11821 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11822 11823 // aligned_addr = (addr + (align-1)) & ~(align-1) 11824 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11825 .addReg(OverflowAddrReg) 11826 .addImm(Align-1); 11827 11828 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11829 .addReg(TmpReg) 11830 .addImm(~(uint64_t)(Align-1)); 11831 } else { 11832 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11833 .addReg(OverflowAddrReg); 11834 } 11835 11836 // Compute the next overflow address after this argument. 11837 // (the overflow address should be kept 8-byte aligned) 11838 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11839 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11840 .addReg(OverflowDestReg) 11841 .addImm(ArgSizeA8); 11842 11843 // Store the new overflow address. 11844 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11845 .addOperand(Base) 11846 .addOperand(Scale) 11847 .addOperand(Index) 11848 .addDisp(Disp, 8) 11849 .addOperand(Segment) 11850 .addReg(NextAddrReg) 11851 .setMemRefs(MMOBegin, MMOEnd); 11852 11853 // If we branched, emit the PHI to the front of endMBB. 11854 if (offsetMBB) { 11855 BuildMI(*endMBB, endMBB->begin(), DL, 11856 TII->get(X86::PHI), DestReg) 11857 .addReg(OffsetDestReg).addMBB(offsetMBB) 11858 .addReg(OverflowDestReg).addMBB(overflowMBB); 11859 } 11860 11861 // Erase the pseudo instruction 11862 MI->eraseFromParent(); 11863 11864 return endMBB; 11865} 11866 11867MachineBasicBlock * 11868X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11869 MachineInstr *MI, 11870 MachineBasicBlock *MBB) const { 11871 // Emit code to save XMM registers to the stack. The ABI says that the 11872 // number of registers to save is given in %al, so it's theoretically 11873 // possible to do an indirect jump trick to avoid saving all of them, 11874 // however this code takes a simpler approach and just executes all 11875 // of the stores if %al is non-zero. It's less code, and it's probably 11876 // easier on the hardware branch predictor, and stores aren't all that 11877 // expensive anyway. 11878 11879 // Create the new basic blocks. One block contains all the XMM stores, 11880 // and one block is the final destination regardless of whether any 11881 // stores were performed. 11882 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11883 MachineFunction *F = MBB->getParent(); 11884 MachineFunction::iterator MBBIter = MBB; 11885 ++MBBIter; 11886 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11887 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11888 F->insert(MBBIter, XMMSaveMBB); 11889 F->insert(MBBIter, EndMBB); 11890 11891 // Transfer the remainder of MBB and its successor edges to EndMBB. 11892 EndMBB->splice(EndMBB->begin(), MBB, 11893 llvm::next(MachineBasicBlock::iterator(MI)), 11894 MBB->end()); 11895 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11896 11897 // The original block will now fall through to the XMM save block. 11898 MBB->addSuccessor(XMMSaveMBB); 11899 // The XMMSaveMBB will fall through to the end block. 11900 XMMSaveMBB->addSuccessor(EndMBB); 11901 11902 // Now add the instructions. 11903 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11904 DebugLoc DL = MI->getDebugLoc(); 11905 11906 unsigned CountReg = MI->getOperand(0).getReg(); 11907 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11908 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11909 11910 if (!Subtarget->isTargetWin64()) { 11911 // If %al is 0, branch around the XMM save block. 11912 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11913 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11914 MBB->addSuccessor(EndMBB); 11915 } 11916 11917 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11918 // In the XMM save block, save all the XMM argument registers. 11919 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11920 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11921 MachineMemOperand *MMO = 11922 F->getMachineMemOperand( 11923 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11924 MachineMemOperand::MOStore, 11925 /*Size=*/16, /*Align=*/16); 11926 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11927 .addFrameIndex(RegSaveFrameIndex) 11928 .addImm(/*Scale=*/1) 11929 .addReg(/*IndexReg=*/0) 11930 .addImm(/*Disp=*/Offset) 11931 .addReg(/*Segment=*/0) 11932 .addReg(MI->getOperand(i).getReg()) 11933 .addMemOperand(MMO); 11934 } 11935 11936 MI->eraseFromParent(); // The pseudo instruction is gone now. 11937 11938 return EndMBB; 11939} 11940 11941MachineBasicBlock * 11942X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 11943 MachineBasicBlock *BB) const { 11944 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11945 DebugLoc DL = MI->getDebugLoc(); 11946 11947 // To "insert" a SELECT_CC instruction, we actually have to insert the 11948 // diamond control-flow pattern. The incoming instruction knows the 11949 // destination vreg to set, the condition code register to branch on, the 11950 // true/false values to select between, and a branch opcode to use. 11951 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11952 MachineFunction::iterator It = BB; 11953 ++It; 11954 11955 // thisMBB: 11956 // ... 11957 // TrueVal = ... 11958 // cmpTY ccX, r1, r2 11959 // bCC copy1MBB 11960 // fallthrough --> copy0MBB 11961 MachineBasicBlock *thisMBB = BB; 11962 MachineFunction *F = BB->getParent(); 11963 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 11964 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 11965 F->insert(It, copy0MBB); 11966 F->insert(It, sinkMBB); 11967 11968 // If the EFLAGS register isn't dead in the terminator, then claim that it's 11969 // live into the sink and copy blocks. 11970 if (!MI->killsRegister(X86::EFLAGS)) { 11971 copy0MBB->addLiveIn(X86::EFLAGS); 11972 sinkMBB->addLiveIn(X86::EFLAGS); 11973 } 11974 11975 // Transfer the remainder of BB and its successor edges to sinkMBB. 11976 sinkMBB->splice(sinkMBB->begin(), BB, 11977 llvm::next(MachineBasicBlock::iterator(MI)), 11978 BB->end()); 11979 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11980 11981 // Add the true and fallthrough blocks as its successors. 11982 BB->addSuccessor(copy0MBB); 11983 BB->addSuccessor(sinkMBB); 11984 11985 // Create the conditional branch instruction. 11986 unsigned Opc = 11987 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11988 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11989 11990 // copy0MBB: 11991 // %FalseValue = ... 11992 // # fallthrough to sinkMBB 11993 copy0MBB->addSuccessor(sinkMBB); 11994 11995 // sinkMBB: 11996 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11997 // ... 11998 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 11999 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12000 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12001 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12002 12003 MI->eraseFromParent(); // The pseudo instruction is gone now. 12004 return sinkMBB; 12005} 12006 12007MachineBasicBlock * 12008X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12009 bool Is64Bit) const { 12010 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12011 DebugLoc DL = MI->getDebugLoc(); 12012 MachineFunction *MF = BB->getParent(); 12013 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12014 12015 assert(getTargetMachine().Options.EnableSegmentedStacks); 12016 12017 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12018 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12019 12020 // BB: 12021 // ... [Till the alloca] 12022 // If stacklet is not large enough, jump to mallocMBB 12023 // 12024 // bumpMBB: 12025 // Allocate by subtracting from RSP 12026 // Jump to continueMBB 12027 // 12028 // mallocMBB: 12029 // Allocate by call to runtime 12030 // 12031 // continueMBB: 12032 // ... 12033 // [rest of original BB] 12034 // 12035 12036 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12037 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12038 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12039 12040 MachineRegisterInfo &MRI = MF->getRegInfo(); 12041 const TargetRegisterClass *AddrRegClass = 12042 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12043 12044 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12045 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12046 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12047 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12048 sizeVReg = MI->getOperand(1).getReg(), 12049 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12050 12051 MachineFunction::iterator MBBIter = BB; 12052 ++MBBIter; 12053 12054 MF->insert(MBBIter, bumpMBB); 12055 MF->insert(MBBIter, mallocMBB); 12056 MF->insert(MBBIter, continueMBB); 12057 12058 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12059 (MachineBasicBlock::iterator(MI)), BB->end()); 12060 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12061 12062 // Add code to the main basic block to check if the stack limit has been hit, 12063 // and if so, jump to mallocMBB otherwise to bumpMBB. 12064 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12065 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12066 .addReg(tmpSPVReg).addReg(sizeVReg); 12067 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12068 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12069 .addReg(SPLimitVReg); 12070 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12071 12072 // bumpMBB simply decreases the stack pointer, since we know the current 12073 // stacklet has enough space. 12074 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12075 .addReg(SPLimitVReg); 12076 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12077 .addReg(SPLimitVReg); 12078 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12079 12080 // Calls into a routine in libgcc to allocate more space from the heap. 12081 if (Is64Bit) { 12082 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12083 .addReg(sizeVReg); 12084 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12085 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 12086 } else { 12087 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12088 .addImm(12); 12089 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12090 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12091 .addExternalSymbol("__morestack_allocate_stack_space"); 12092 } 12093 12094 if (!Is64Bit) 12095 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12096 .addImm(16); 12097 12098 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12099 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12100 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12101 12102 // Set up the CFG correctly. 12103 BB->addSuccessor(bumpMBB); 12104 BB->addSuccessor(mallocMBB); 12105 mallocMBB->addSuccessor(continueMBB); 12106 bumpMBB->addSuccessor(continueMBB); 12107 12108 // Take care of the PHI nodes. 12109 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12110 MI->getOperand(0).getReg()) 12111 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12112 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12113 12114 // Delete the original pseudo instruction. 12115 MI->eraseFromParent(); 12116 12117 // And we're done. 12118 return continueMBB; 12119} 12120 12121MachineBasicBlock * 12122X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12123 MachineBasicBlock *BB) const { 12124 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12125 DebugLoc DL = MI->getDebugLoc(); 12126 12127 assert(!Subtarget->isTargetEnvMacho()); 12128 12129 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12130 // non-trivial part is impdef of ESP. 12131 12132 if (Subtarget->isTargetWin64()) { 12133 if (Subtarget->isTargetCygMing()) { 12134 // ___chkstk(Mingw64): 12135 // Clobbers R10, R11, RAX and EFLAGS. 12136 // Updates RSP. 12137 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12138 .addExternalSymbol("___chkstk") 12139 .addReg(X86::RAX, RegState::Implicit) 12140 .addReg(X86::RSP, RegState::Implicit) 12141 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12142 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12143 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12144 } else { 12145 // __chkstk(MSVCRT): does not update stack pointer. 12146 // Clobbers R10, R11 and EFLAGS. 12147 // FIXME: RAX(allocated size) might be reused and not killed. 12148 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12149 .addExternalSymbol("__chkstk") 12150 .addReg(X86::RAX, RegState::Implicit) 12151 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12152 // RAX has the offset to subtracted from RSP. 12153 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12154 .addReg(X86::RSP) 12155 .addReg(X86::RAX); 12156 } 12157 } else { 12158 const char *StackProbeSymbol = 12159 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12160 12161 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12162 .addExternalSymbol(StackProbeSymbol) 12163 .addReg(X86::EAX, RegState::Implicit) 12164 .addReg(X86::ESP, RegState::Implicit) 12165 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12166 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12167 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12168 } 12169 12170 MI->eraseFromParent(); // The pseudo instruction is gone now. 12171 return BB; 12172} 12173 12174MachineBasicBlock * 12175X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12176 MachineBasicBlock *BB) const { 12177 // This is pretty easy. We're taking the value that we received from 12178 // our load from the relocation, sticking it in either RDI (x86-64) 12179 // or EAX and doing an indirect call. The return value will then 12180 // be in the normal return register. 12181 const X86InstrInfo *TII 12182 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12183 DebugLoc DL = MI->getDebugLoc(); 12184 MachineFunction *F = BB->getParent(); 12185 12186 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12187 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12188 12189 if (Subtarget->is64Bit()) { 12190 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12191 TII->get(X86::MOV64rm), X86::RDI) 12192 .addReg(X86::RIP) 12193 .addImm(0).addReg(0) 12194 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12195 MI->getOperand(3).getTargetFlags()) 12196 .addReg(0); 12197 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12198 addDirectMem(MIB, X86::RDI); 12199 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12200 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12201 TII->get(X86::MOV32rm), X86::EAX) 12202 .addReg(0) 12203 .addImm(0).addReg(0) 12204 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12205 MI->getOperand(3).getTargetFlags()) 12206 .addReg(0); 12207 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12208 addDirectMem(MIB, X86::EAX); 12209 } else { 12210 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12211 TII->get(X86::MOV32rm), X86::EAX) 12212 .addReg(TII->getGlobalBaseReg(F)) 12213 .addImm(0).addReg(0) 12214 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12215 MI->getOperand(3).getTargetFlags()) 12216 .addReg(0); 12217 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12218 addDirectMem(MIB, X86::EAX); 12219 } 12220 12221 MI->eraseFromParent(); // The pseudo instruction is gone now. 12222 return BB; 12223} 12224 12225MachineBasicBlock * 12226X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12227 MachineBasicBlock *BB) const { 12228 switch (MI->getOpcode()) { 12229 default: assert(0 && "Unexpected instr type to insert"); 12230 case X86::TAILJMPd64: 12231 case X86::TAILJMPr64: 12232 case X86::TAILJMPm64: 12233 assert(0 && "TAILJMP64 would not be touched here."); 12234 case X86::TCRETURNdi64: 12235 case X86::TCRETURNri64: 12236 case X86::TCRETURNmi64: 12237 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 12238 // On AMD64, additional defs should be added before register allocation. 12239 if (!Subtarget->isTargetWin64()) { 12240 MI->addRegisterDefined(X86::RSI); 12241 MI->addRegisterDefined(X86::RDI); 12242 MI->addRegisterDefined(X86::XMM6); 12243 MI->addRegisterDefined(X86::XMM7); 12244 MI->addRegisterDefined(X86::XMM8); 12245 MI->addRegisterDefined(X86::XMM9); 12246 MI->addRegisterDefined(X86::XMM10); 12247 MI->addRegisterDefined(X86::XMM11); 12248 MI->addRegisterDefined(X86::XMM12); 12249 MI->addRegisterDefined(X86::XMM13); 12250 MI->addRegisterDefined(X86::XMM14); 12251 MI->addRegisterDefined(X86::XMM15); 12252 } 12253 return BB; 12254 case X86::WIN_ALLOCA: 12255 return EmitLoweredWinAlloca(MI, BB); 12256 case X86::SEG_ALLOCA_32: 12257 return EmitLoweredSegAlloca(MI, BB, false); 12258 case X86::SEG_ALLOCA_64: 12259 return EmitLoweredSegAlloca(MI, BB, true); 12260 case X86::TLSCall_32: 12261 case X86::TLSCall_64: 12262 return EmitLoweredTLSCall(MI, BB); 12263 case X86::CMOV_GR8: 12264 case X86::CMOV_FR32: 12265 case X86::CMOV_FR64: 12266 case X86::CMOV_V4F32: 12267 case X86::CMOV_V2F64: 12268 case X86::CMOV_V2I64: 12269 case X86::CMOV_V8F32: 12270 case X86::CMOV_V4F64: 12271 case X86::CMOV_V4I64: 12272 case X86::CMOV_GR16: 12273 case X86::CMOV_GR32: 12274 case X86::CMOV_RFP32: 12275 case X86::CMOV_RFP64: 12276 case X86::CMOV_RFP80: 12277 return EmitLoweredSelect(MI, BB); 12278 12279 case X86::FP32_TO_INT16_IN_MEM: 12280 case X86::FP32_TO_INT32_IN_MEM: 12281 case X86::FP32_TO_INT64_IN_MEM: 12282 case X86::FP64_TO_INT16_IN_MEM: 12283 case X86::FP64_TO_INT32_IN_MEM: 12284 case X86::FP64_TO_INT64_IN_MEM: 12285 case X86::FP80_TO_INT16_IN_MEM: 12286 case X86::FP80_TO_INT32_IN_MEM: 12287 case X86::FP80_TO_INT64_IN_MEM: { 12288 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12289 DebugLoc DL = MI->getDebugLoc(); 12290 12291 // Change the floating point control register to use "round towards zero" 12292 // mode when truncating to an integer value. 12293 MachineFunction *F = BB->getParent(); 12294 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12295 addFrameReference(BuildMI(*BB, MI, DL, 12296 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12297 12298 // Load the old value of the high byte of the control word... 12299 unsigned OldCW = 12300 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12301 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12302 CWFrameIdx); 12303 12304 // Set the high part to be round to zero... 12305 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12306 .addImm(0xC7F); 12307 12308 // Reload the modified control word now... 12309 addFrameReference(BuildMI(*BB, MI, DL, 12310 TII->get(X86::FLDCW16m)), CWFrameIdx); 12311 12312 // Restore the memory image of control word to original value 12313 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12314 .addReg(OldCW); 12315 12316 // Get the X86 opcode to use. 12317 unsigned Opc; 12318 switch (MI->getOpcode()) { 12319 default: llvm_unreachable("illegal opcode!"); 12320 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12321 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12322 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12323 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12324 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12325 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12326 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12327 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12328 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12329 } 12330 12331 X86AddressMode AM; 12332 MachineOperand &Op = MI->getOperand(0); 12333 if (Op.isReg()) { 12334 AM.BaseType = X86AddressMode::RegBase; 12335 AM.Base.Reg = Op.getReg(); 12336 } else { 12337 AM.BaseType = X86AddressMode::FrameIndexBase; 12338 AM.Base.FrameIndex = Op.getIndex(); 12339 } 12340 Op = MI->getOperand(1); 12341 if (Op.isImm()) 12342 AM.Scale = Op.getImm(); 12343 Op = MI->getOperand(2); 12344 if (Op.isImm()) 12345 AM.IndexReg = Op.getImm(); 12346 Op = MI->getOperand(3); 12347 if (Op.isGlobal()) { 12348 AM.GV = Op.getGlobal(); 12349 } else { 12350 AM.Disp = Op.getImm(); 12351 } 12352 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12353 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12354 12355 // Reload the original control word now. 12356 addFrameReference(BuildMI(*BB, MI, DL, 12357 TII->get(X86::FLDCW16m)), CWFrameIdx); 12358 12359 MI->eraseFromParent(); // The pseudo instruction is gone now. 12360 return BB; 12361 } 12362 // String/text processing lowering. 12363 case X86::PCMPISTRM128REG: 12364 case X86::VPCMPISTRM128REG: 12365 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12366 case X86::PCMPISTRM128MEM: 12367 case X86::VPCMPISTRM128MEM: 12368 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12369 case X86::PCMPESTRM128REG: 12370 case X86::VPCMPESTRM128REG: 12371 return EmitPCMP(MI, BB, 5, false /* in mem */); 12372 case X86::PCMPESTRM128MEM: 12373 case X86::VPCMPESTRM128MEM: 12374 return EmitPCMP(MI, BB, 5, true /* in mem */); 12375 12376 // Thread synchronization. 12377 case X86::MONITOR: 12378 return EmitMonitor(MI, BB); 12379 case X86::MWAIT: 12380 return EmitMwait(MI, BB); 12381 12382 // Atomic Lowering. 12383 case X86::ATOMAND32: 12384 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12385 X86::AND32ri, X86::MOV32rm, 12386 X86::LCMPXCHG32, 12387 X86::NOT32r, X86::EAX, 12388 X86::GR32RegisterClass); 12389 case X86::ATOMOR32: 12390 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12391 X86::OR32ri, X86::MOV32rm, 12392 X86::LCMPXCHG32, 12393 X86::NOT32r, X86::EAX, 12394 X86::GR32RegisterClass); 12395 case X86::ATOMXOR32: 12396 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12397 X86::XOR32ri, X86::MOV32rm, 12398 X86::LCMPXCHG32, 12399 X86::NOT32r, X86::EAX, 12400 X86::GR32RegisterClass); 12401 case X86::ATOMNAND32: 12402 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12403 X86::AND32ri, X86::MOV32rm, 12404 X86::LCMPXCHG32, 12405 X86::NOT32r, X86::EAX, 12406 X86::GR32RegisterClass, true); 12407 case X86::ATOMMIN32: 12408 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12409 case X86::ATOMMAX32: 12410 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12411 case X86::ATOMUMIN32: 12412 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12413 case X86::ATOMUMAX32: 12414 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12415 12416 case X86::ATOMAND16: 12417 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12418 X86::AND16ri, X86::MOV16rm, 12419 X86::LCMPXCHG16, 12420 X86::NOT16r, X86::AX, 12421 X86::GR16RegisterClass); 12422 case X86::ATOMOR16: 12423 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12424 X86::OR16ri, X86::MOV16rm, 12425 X86::LCMPXCHG16, 12426 X86::NOT16r, X86::AX, 12427 X86::GR16RegisterClass); 12428 case X86::ATOMXOR16: 12429 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12430 X86::XOR16ri, X86::MOV16rm, 12431 X86::LCMPXCHG16, 12432 X86::NOT16r, X86::AX, 12433 X86::GR16RegisterClass); 12434 case X86::ATOMNAND16: 12435 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12436 X86::AND16ri, X86::MOV16rm, 12437 X86::LCMPXCHG16, 12438 X86::NOT16r, X86::AX, 12439 X86::GR16RegisterClass, true); 12440 case X86::ATOMMIN16: 12441 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12442 case X86::ATOMMAX16: 12443 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12444 case X86::ATOMUMIN16: 12445 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12446 case X86::ATOMUMAX16: 12447 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12448 12449 case X86::ATOMAND8: 12450 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12451 X86::AND8ri, X86::MOV8rm, 12452 X86::LCMPXCHG8, 12453 X86::NOT8r, X86::AL, 12454 X86::GR8RegisterClass); 12455 case X86::ATOMOR8: 12456 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12457 X86::OR8ri, X86::MOV8rm, 12458 X86::LCMPXCHG8, 12459 X86::NOT8r, X86::AL, 12460 X86::GR8RegisterClass); 12461 case X86::ATOMXOR8: 12462 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12463 X86::XOR8ri, X86::MOV8rm, 12464 X86::LCMPXCHG8, 12465 X86::NOT8r, X86::AL, 12466 X86::GR8RegisterClass); 12467 case X86::ATOMNAND8: 12468 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12469 X86::AND8ri, X86::MOV8rm, 12470 X86::LCMPXCHG8, 12471 X86::NOT8r, X86::AL, 12472 X86::GR8RegisterClass, true); 12473 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12474 // This group is for 64-bit host. 12475 case X86::ATOMAND64: 12476 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12477 X86::AND64ri32, X86::MOV64rm, 12478 X86::LCMPXCHG64, 12479 X86::NOT64r, X86::RAX, 12480 X86::GR64RegisterClass); 12481 case X86::ATOMOR64: 12482 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12483 X86::OR64ri32, X86::MOV64rm, 12484 X86::LCMPXCHG64, 12485 X86::NOT64r, X86::RAX, 12486 X86::GR64RegisterClass); 12487 case X86::ATOMXOR64: 12488 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12489 X86::XOR64ri32, X86::MOV64rm, 12490 X86::LCMPXCHG64, 12491 X86::NOT64r, X86::RAX, 12492 X86::GR64RegisterClass); 12493 case X86::ATOMNAND64: 12494 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12495 X86::AND64ri32, X86::MOV64rm, 12496 X86::LCMPXCHG64, 12497 X86::NOT64r, X86::RAX, 12498 X86::GR64RegisterClass, true); 12499 case X86::ATOMMIN64: 12500 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12501 case X86::ATOMMAX64: 12502 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12503 case X86::ATOMUMIN64: 12504 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12505 case X86::ATOMUMAX64: 12506 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12507 12508 // This group does 64-bit operations on a 32-bit host. 12509 case X86::ATOMAND6432: 12510 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12511 X86::AND32rr, X86::AND32rr, 12512 X86::AND32ri, X86::AND32ri, 12513 false); 12514 case X86::ATOMOR6432: 12515 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12516 X86::OR32rr, X86::OR32rr, 12517 X86::OR32ri, X86::OR32ri, 12518 false); 12519 case X86::ATOMXOR6432: 12520 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12521 X86::XOR32rr, X86::XOR32rr, 12522 X86::XOR32ri, X86::XOR32ri, 12523 false); 12524 case X86::ATOMNAND6432: 12525 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12526 X86::AND32rr, X86::AND32rr, 12527 X86::AND32ri, X86::AND32ri, 12528 true); 12529 case X86::ATOMADD6432: 12530 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12531 X86::ADD32rr, X86::ADC32rr, 12532 X86::ADD32ri, X86::ADC32ri, 12533 false); 12534 case X86::ATOMSUB6432: 12535 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12536 X86::SUB32rr, X86::SBB32rr, 12537 X86::SUB32ri, X86::SBB32ri, 12538 false); 12539 case X86::ATOMSWAP6432: 12540 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12541 X86::MOV32rr, X86::MOV32rr, 12542 X86::MOV32ri, X86::MOV32ri, 12543 false); 12544 case X86::VASTART_SAVE_XMM_REGS: 12545 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12546 12547 case X86::VAARG_64: 12548 return EmitVAARG64WithCustomInserter(MI, BB); 12549 } 12550} 12551 12552//===----------------------------------------------------------------------===// 12553// X86 Optimization Hooks 12554//===----------------------------------------------------------------------===// 12555 12556void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12557 const APInt &Mask, 12558 APInt &KnownZero, 12559 APInt &KnownOne, 12560 const SelectionDAG &DAG, 12561 unsigned Depth) const { 12562 unsigned Opc = Op.getOpcode(); 12563 assert((Opc >= ISD::BUILTIN_OP_END || 12564 Opc == ISD::INTRINSIC_WO_CHAIN || 12565 Opc == ISD::INTRINSIC_W_CHAIN || 12566 Opc == ISD::INTRINSIC_VOID) && 12567 "Should use MaskedValueIsZero if you don't know whether Op" 12568 " is a target node!"); 12569 12570 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12571 switch (Opc) { 12572 default: break; 12573 case X86ISD::ADD: 12574 case X86ISD::SUB: 12575 case X86ISD::ADC: 12576 case X86ISD::SBB: 12577 case X86ISD::SMUL: 12578 case X86ISD::UMUL: 12579 case X86ISD::INC: 12580 case X86ISD::DEC: 12581 case X86ISD::OR: 12582 case X86ISD::XOR: 12583 case X86ISD::AND: 12584 // These nodes' second result is a boolean. 12585 if (Op.getResNo() == 0) 12586 break; 12587 // Fallthrough 12588 case X86ISD::SETCC: 12589 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12590 Mask.getBitWidth() - 1); 12591 break; 12592 case ISD::INTRINSIC_WO_CHAIN: { 12593 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12594 unsigned NumLoBits = 0; 12595 switch (IntId) { 12596 default: break; 12597 case Intrinsic::x86_sse_movmsk_ps: 12598 case Intrinsic::x86_avx_movmsk_ps_256: 12599 case Intrinsic::x86_sse2_movmsk_pd: 12600 case Intrinsic::x86_avx_movmsk_pd_256: 12601 case Intrinsic::x86_mmx_pmovmskb: 12602 case Intrinsic::x86_sse2_pmovmskb_128: 12603 case Intrinsic::x86_avx2_pmovmskb: { 12604 // High bits of movmskp{s|d}, pmovmskb are known zero. 12605 switch (IntId) { 12606 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12607 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12608 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12609 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12610 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12611 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12612 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12613 } 12614 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12615 Mask.getBitWidth() - NumLoBits); 12616 break; 12617 } 12618 } 12619 break; 12620 } 12621 } 12622} 12623 12624unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12625 unsigned Depth) const { 12626 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12627 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12628 return Op.getValueType().getScalarType().getSizeInBits(); 12629 12630 // Fallback case. 12631 return 1; 12632} 12633 12634/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12635/// node is a GlobalAddress + offset. 12636bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12637 const GlobalValue* &GA, 12638 int64_t &Offset) const { 12639 if (N->getOpcode() == X86ISD::Wrapper) { 12640 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12641 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12642 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12643 return true; 12644 } 12645 } 12646 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12647} 12648 12649/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12650/// same as extracting the high 128-bit part of 256-bit vector and then 12651/// inserting the result into the low part of a new 256-bit vector 12652static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12653 EVT VT = SVOp->getValueType(0); 12654 int NumElems = VT.getVectorNumElements(); 12655 12656 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12657 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12658 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12659 SVOp->getMaskElt(j) >= 0) 12660 return false; 12661 12662 return true; 12663} 12664 12665/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12666/// same as extracting the low 128-bit part of 256-bit vector and then 12667/// inserting the result into the high part of a new 256-bit vector 12668static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12669 EVT VT = SVOp->getValueType(0); 12670 int NumElems = VT.getVectorNumElements(); 12671 12672 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12673 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12674 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12675 SVOp->getMaskElt(j) >= 0) 12676 return false; 12677 12678 return true; 12679} 12680 12681/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12682static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12683 TargetLowering::DAGCombinerInfo &DCI) { 12684 DebugLoc dl = N->getDebugLoc(); 12685 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12686 SDValue V1 = SVOp->getOperand(0); 12687 SDValue V2 = SVOp->getOperand(1); 12688 EVT VT = SVOp->getValueType(0); 12689 int NumElems = VT.getVectorNumElements(); 12690 12691 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12692 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12693 // 12694 // 0,0,0,... 12695 // | 12696 // V UNDEF BUILD_VECTOR UNDEF 12697 // \ / \ / 12698 // CONCAT_VECTOR CONCAT_VECTOR 12699 // \ / 12700 // \ / 12701 // RESULT: V + zero extended 12702 // 12703 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12704 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12705 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12706 return SDValue(); 12707 12708 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12709 return SDValue(); 12710 12711 // To match the shuffle mask, the first half of the mask should 12712 // be exactly the first vector, and all the rest a splat with the 12713 // first element of the second one. 12714 for (int i = 0; i < NumElems/2; ++i) 12715 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12716 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12717 return SDValue(); 12718 12719 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12720 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12721 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12722 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12723 SDValue ResNode = 12724 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12725 Ld->getMemoryVT(), 12726 Ld->getPointerInfo(), 12727 Ld->getAlignment(), 12728 false/*isVolatile*/, true/*ReadMem*/, 12729 false/*WriteMem*/); 12730 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12731 } 12732 12733 // Emit a zeroed vector and insert the desired subvector on its 12734 // first half. 12735 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 12736 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12737 DAG.getConstant(0, MVT::i32), DAG, dl); 12738 return DCI.CombineTo(N, InsV); 12739 } 12740 12741 //===--------------------------------------------------------------------===// 12742 // Combine some shuffles into subvector extracts and inserts: 12743 // 12744 12745 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12746 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12747 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12748 DAG, dl); 12749 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12750 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12751 return DCI.CombineTo(N, InsV); 12752 } 12753 12754 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12755 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12756 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12757 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12758 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12759 return DCI.CombineTo(N, InsV); 12760 } 12761 12762 return SDValue(); 12763} 12764 12765/// PerformShuffleCombine - Performs several different shuffle combines. 12766static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12767 TargetLowering::DAGCombinerInfo &DCI, 12768 const X86Subtarget *Subtarget) { 12769 DebugLoc dl = N->getDebugLoc(); 12770 EVT VT = N->getValueType(0); 12771 12772 // Don't create instructions with illegal types after legalize types has run. 12773 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12774 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12775 return SDValue(); 12776 12777 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12778 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12779 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12780 return PerformShuffleCombine256(N, DAG, DCI); 12781 12782 // Only handle 128 wide vector from here on. 12783 if (VT.getSizeInBits() != 128) 12784 return SDValue(); 12785 12786 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12787 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12788 // consecutive, non-overlapping, and in the right order. 12789 SmallVector<SDValue, 16> Elts; 12790 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12791 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12792 12793 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12794} 12795 12796/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12797/// generation and convert it from being a bunch of shuffles and extracts 12798/// to a simple store and scalar loads to extract the elements. 12799static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12800 const TargetLowering &TLI) { 12801 SDValue InputVector = N->getOperand(0); 12802 12803 // Only operate on vectors of 4 elements, where the alternative shuffling 12804 // gets to be more expensive. 12805 if (InputVector.getValueType() != MVT::v4i32) 12806 return SDValue(); 12807 12808 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12809 // single use which is a sign-extend or zero-extend, and all elements are 12810 // used. 12811 SmallVector<SDNode *, 4> Uses; 12812 unsigned ExtractedElements = 0; 12813 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12814 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12815 if (UI.getUse().getResNo() != InputVector.getResNo()) 12816 return SDValue(); 12817 12818 SDNode *Extract = *UI; 12819 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12820 return SDValue(); 12821 12822 if (Extract->getValueType(0) != MVT::i32) 12823 return SDValue(); 12824 if (!Extract->hasOneUse()) 12825 return SDValue(); 12826 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12827 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12828 return SDValue(); 12829 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 12830 return SDValue(); 12831 12832 // Record which element was extracted. 12833 ExtractedElements |= 12834 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 12835 12836 Uses.push_back(Extract); 12837 } 12838 12839 // If not all the elements were used, this may not be worthwhile. 12840 if (ExtractedElements != 15) 12841 return SDValue(); 12842 12843 // Ok, we've now decided to do the transformation. 12844 DebugLoc dl = InputVector.getDebugLoc(); 12845 12846 // Store the value to a temporary stack slot. 12847 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 12848 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 12849 MachinePointerInfo(), false, false, 0); 12850 12851 // Replace each use (extract) with a load of the appropriate element. 12852 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 12853 UE = Uses.end(); UI != UE; ++UI) { 12854 SDNode *Extract = *UI; 12855 12856 // cOMpute the element's address. 12857 SDValue Idx = Extract->getOperand(1); 12858 unsigned EltSize = 12859 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 12860 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 12861 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 12862 12863 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 12864 StackPtr, OffsetVal); 12865 12866 // Load the scalar. 12867 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 12868 ScalarAddr, MachinePointerInfo(), 12869 false, false, false, 0); 12870 12871 // Replace the exact with the load. 12872 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 12873 } 12874 12875 // The replacement was made in place; don't return anything. 12876 return SDValue(); 12877} 12878 12879/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 12880/// nodes. 12881static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 12882 const X86Subtarget *Subtarget) { 12883 DebugLoc DL = N->getDebugLoc(); 12884 SDValue Cond = N->getOperand(0); 12885 // Get the LHS/RHS of the select. 12886 SDValue LHS = N->getOperand(1); 12887 SDValue RHS = N->getOperand(2); 12888 EVT VT = LHS.getValueType(); 12889 12890 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 12891 // instructions match the semantics of the common C idiom x<y?x:y but not 12892 // x<=y?x:y, because of how they handle negative zero (which can be 12893 // ignored in unsafe-math mode). 12894 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 12895 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 12896 (Subtarget->hasXMMInt() || 12897 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 12898 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 12899 12900 unsigned Opcode = 0; 12901 // Check for x CC y ? x : y. 12902 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 12903 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 12904 switch (CC) { 12905 default: break; 12906 case ISD::SETULT: 12907 // Converting this to a min would handle NaNs incorrectly, and swapping 12908 // the operands would cause it to handle comparisons between positive 12909 // and negative zero incorrectly. 12910 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12911 if (!DAG.getTarget().Options.UnsafeFPMath && 12912 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12913 break; 12914 std::swap(LHS, RHS); 12915 } 12916 Opcode = X86ISD::FMIN; 12917 break; 12918 case ISD::SETOLE: 12919 // Converting this to a min would handle comparisons between positive 12920 // and negative zero incorrectly. 12921 if (!DAG.getTarget().Options.UnsafeFPMath && 12922 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12923 break; 12924 Opcode = X86ISD::FMIN; 12925 break; 12926 case ISD::SETULE: 12927 // Converting this to a min would handle both negative zeros and NaNs 12928 // incorrectly, but we can swap the operands to fix both. 12929 std::swap(LHS, RHS); 12930 case ISD::SETOLT: 12931 case ISD::SETLT: 12932 case ISD::SETLE: 12933 Opcode = X86ISD::FMIN; 12934 break; 12935 12936 case ISD::SETOGE: 12937 // Converting this to a max would handle comparisons between positive 12938 // and negative zero incorrectly. 12939 if (!DAG.getTarget().Options.UnsafeFPMath && 12940 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12941 break; 12942 Opcode = X86ISD::FMAX; 12943 break; 12944 case ISD::SETUGT: 12945 // Converting this to a max would handle NaNs incorrectly, and swapping 12946 // the operands would cause it to handle comparisons between positive 12947 // and negative zero incorrectly. 12948 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12949 if (!DAG.getTarget().Options.UnsafeFPMath && 12950 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12951 break; 12952 std::swap(LHS, RHS); 12953 } 12954 Opcode = X86ISD::FMAX; 12955 break; 12956 case ISD::SETUGE: 12957 // Converting this to a max would handle both negative zeros and NaNs 12958 // incorrectly, but we can swap the operands to fix both. 12959 std::swap(LHS, RHS); 12960 case ISD::SETOGT: 12961 case ISD::SETGT: 12962 case ISD::SETGE: 12963 Opcode = X86ISD::FMAX; 12964 break; 12965 } 12966 // Check for x CC y ? y : x -- a min/max with reversed arms. 12967 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 12968 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 12969 switch (CC) { 12970 default: break; 12971 case ISD::SETOGE: 12972 // Converting this to a min would handle comparisons between positive 12973 // and negative zero incorrectly, and swapping the operands would 12974 // cause it to handle NaNs incorrectly. 12975 if (!DAG.getTarget().Options.UnsafeFPMath && 12976 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 12977 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12978 break; 12979 std::swap(LHS, RHS); 12980 } 12981 Opcode = X86ISD::FMIN; 12982 break; 12983 case ISD::SETUGT: 12984 // Converting this to a min would handle NaNs incorrectly. 12985 if (!DAG.getTarget().Options.UnsafeFPMath && 12986 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 12987 break; 12988 Opcode = X86ISD::FMIN; 12989 break; 12990 case ISD::SETUGE: 12991 // Converting this to a min would handle both negative zeros and NaNs 12992 // incorrectly, but we can swap the operands to fix both. 12993 std::swap(LHS, RHS); 12994 case ISD::SETOGT: 12995 case ISD::SETGT: 12996 case ISD::SETGE: 12997 Opcode = X86ISD::FMIN; 12998 break; 12999 13000 case ISD::SETULT: 13001 // Converting this to a max would handle NaNs incorrectly. 13002 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13003 break; 13004 Opcode = X86ISD::FMAX; 13005 break; 13006 case ISD::SETOLE: 13007 // Converting this to a max would handle comparisons between positive 13008 // and negative zero incorrectly, and swapping the operands would 13009 // cause it to handle NaNs incorrectly. 13010 if (!DAG.getTarget().Options.UnsafeFPMath && 13011 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13012 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13013 break; 13014 std::swap(LHS, RHS); 13015 } 13016 Opcode = X86ISD::FMAX; 13017 break; 13018 case ISD::SETULE: 13019 // Converting this to a max would handle both negative zeros and NaNs 13020 // incorrectly, but we can swap the operands to fix both. 13021 std::swap(LHS, RHS); 13022 case ISD::SETOLT: 13023 case ISD::SETLT: 13024 case ISD::SETLE: 13025 Opcode = X86ISD::FMAX; 13026 break; 13027 } 13028 } 13029 13030 if (Opcode) 13031 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13032 } 13033 13034 // If this is a select between two integer constants, try to do some 13035 // optimizations. 13036 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13037 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13038 // Don't do this for crazy integer types. 13039 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13040 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13041 // so that TrueC (the true value) is larger than FalseC. 13042 bool NeedsCondInvert = false; 13043 13044 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13045 // Efficiently invertible. 13046 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13047 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13048 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13049 NeedsCondInvert = true; 13050 std::swap(TrueC, FalseC); 13051 } 13052 13053 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13054 if (FalseC->getAPIntValue() == 0 && 13055 TrueC->getAPIntValue().isPowerOf2()) { 13056 if (NeedsCondInvert) // Invert the condition if needed. 13057 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13058 DAG.getConstant(1, Cond.getValueType())); 13059 13060 // Zero extend the condition if needed. 13061 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13062 13063 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13064 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13065 DAG.getConstant(ShAmt, MVT::i8)); 13066 } 13067 13068 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13069 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13070 if (NeedsCondInvert) // Invert the condition if needed. 13071 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13072 DAG.getConstant(1, Cond.getValueType())); 13073 13074 // Zero extend the condition if needed. 13075 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13076 FalseC->getValueType(0), Cond); 13077 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13078 SDValue(FalseC, 0)); 13079 } 13080 13081 // Optimize cases that will turn into an LEA instruction. This requires 13082 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13083 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13084 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13085 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13086 13087 bool isFastMultiplier = false; 13088 if (Diff < 10) { 13089 switch ((unsigned char)Diff) { 13090 default: break; 13091 case 1: // result = add base, cond 13092 case 2: // result = lea base( , cond*2) 13093 case 3: // result = lea base(cond, cond*2) 13094 case 4: // result = lea base( , cond*4) 13095 case 5: // result = lea base(cond, cond*4) 13096 case 8: // result = lea base( , cond*8) 13097 case 9: // result = lea base(cond, cond*8) 13098 isFastMultiplier = true; 13099 break; 13100 } 13101 } 13102 13103 if (isFastMultiplier) { 13104 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13105 if (NeedsCondInvert) // Invert the condition if needed. 13106 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13107 DAG.getConstant(1, Cond.getValueType())); 13108 13109 // Zero extend the condition if needed. 13110 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13111 Cond); 13112 // Scale the condition by the difference. 13113 if (Diff != 1) 13114 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13115 DAG.getConstant(Diff, Cond.getValueType())); 13116 13117 // Add the base if non-zero. 13118 if (FalseC->getAPIntValue() != 0) 13119 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13120 SDValue(FalseC, 0)); 13121 return Cond; 13122 } 13123 } 13124 } 13125 } 13126 13127 // Canonicalize max and min: 13128 // (x > y) ? x : y -> (x >= y) ? x : y 13129 // (x < y) ? x : y -> (x <= y) ? x : y 13130 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13131 // the need for an extra compare 13132 // against zero. e.g. 13133 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13134 // subl %esi, %edi 13135 // testl %edi, %edi 13136 // movl $0, %eax 13137 // cmovgl %edi, %eax 13138 // => 13139 // xorl %eax, %eax 13140 // subl %esi, $edi 13141 // cmovsl %eax, %edi 13142 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13143 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13144 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13145 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13146 switch (CC) { 13147 default: break; 13148 case ISD::SETLT: 13149 case ISD::SETGT: { 13150 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13151 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13152 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13153 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13154 } 13155 } 13156 } 13157 13158 return SDValue(); 13159} 13160 13161/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13162static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13163 TargetLowering::DAGCombinerInfo &DCI) { 13164 DebugLoc DL = N->getDebugLoc(); 13165 13166 // If the flag operand isn't dead, don't touch this CMOV. 13167 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13168 return SDValue(); 13169 13170 SDValue FalseOp = N->getOperand(0); 13171 SDValue TrueOp = N->getOperand(1); 13172 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13173 SDValue Cond = N->getOperand(3); 13174 if (CC == X86::COND_E || CC == X86::COND_NE) { 13175 switch (Cond.getOpcode()) { 13176 default: break; 13177 case X86ISD::BSR: 13178 case X86ISD::BSF: 13179 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13180 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13181 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13182 } 13183 } 13184 13185 // If this is a select between two integer constants, try to do some 13186 // optimizations. Note that the operands are ordered the opposite of SELECT 13187 // operands. 13188 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13189 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13190 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13191 // larger than FalseC (the false value). 13192 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13193 CC = X86::GetOppositeBranchCondition(CC); 13194 std::swap(TrueC, FalseC); 13195 } 13196 13197 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13198 // This is efficient for any integer data type (including i8/i16) and 13199 // shift amount. 13200 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13201 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13202 DAG.getConstant(CC, MVT::i8), Cond); 13203 13204 // Zero extend the condition if needed. 13205 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13206 13207 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13208 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13209 DAG.getConstant(ShAmt, MVT::i8)); 13210 if (N->getNumValues() == 2) // Dead flag value? 13211 return DCI.CombineTo(N, Cond, SDValue()); 13212 return Cond; 13213 } 13214 13215 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13216 // for any integer data type, including i8/i16. 13217 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13218 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13219 DAG.getConstant(CC, MVT::i8), Cond); 13220 13221 // Zero extend the condition if needed. 13222 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13223 FalseC->getValueType(0), Cond); 13224 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13225 SDValue(FalseC, 0)); 13226 13227 if (N->getNumValues() == 2) // Dead flag value? 13228 return DCI.CombineTo(N, Cond, SDValue()); 13229 return Cond; 13230 } 13231 13232 // Optimize cases that will turn into an LEA instruction. This requires 13233 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13234 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13235 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13236 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13237 13238 bool isFastMultiplier = false; 13239 if (Diff < 10) { 13240 switch ((unsigned char)Diff) { 13241 default: break; 13242 case 1: // result = add base, cond 13243 case 2: // result = lea base( , cond*2) 13244 case 3: // result = lea base(cond, cond*2) 13245 case 4: // result = lea base( , cond*4) 13246 case 5: // result = lea base(cond, cond*4) 13247 case 8: // result = lea base( , cond*8) 13248 case 9: // result = lea base(cond, cond*8) 13249 isFastMultiplier = true; 13250 break; 13251 } 13252 } 13253 13254 if (isFastMultiplier) { 13255 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13256 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13257 DAG.getConstant(CC, MVT::i8), Cond); 13258 // Zero extend the condition if needed. 13259 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13260 Cond); 13261 // Scale the condition by the difference. 13262 if (Diff != 1) 13263 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13264 DAG.getConstant(Diff, Cond.getValueType())); 13265 13266 // Add the base if non-zero. 13267 if (FalseC->getAPIntValue() != 0) 13268 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13269 SDValue(FalseC, 0)); 13270 if (N->getNumValues() == 2) // Dead flag value? 13271 return DCI.CombineTo(N, Cond, SDValue()); 13272 return Cond; 13273 } 13274 } 13275 } 13276 } 13277 return SDValue(); 13278} 13279 13280 13281/// PerformMulCombine - Optimize a single multiply with constant into two 13282/// in order to implement it with two cheaper instructions, e.g. 13283/// LEA + SHL, LEA + LEA. 13284static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13285 TargetLowering::DAGCombinerInfo &DCI) { 13286 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13287 return SDValue(); 13288 13289 EVT VT = N->getValueType(0); 13290 if (VT != MVT::i64) 13291 return SDValue(); 13292 13293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13294 if (!C) 13295 return SDValue(); 13296 uint64_t MulAmt = C->getZExtValue(); 13297 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13298 return SDValue(); 13299 13300 uint64_t MulAmt1 = 0; 13301 uint64_t MulAmt2 = 0; 13302 if ((MulAmt % 9) == 0) { 13303 MulAmt1 = 9; 13304 MulAmt2 = MulAmt / 9; 13305 } else if ((MulAmt % 5) == 0) { 13306 MulAmt1 = 5; 13307 MulAmt2 = MulAmt / 5; 13308 } else if ((MulAmt % 3) == 0) { 13309 MulAmt1 = 3; 13310 MulAmt2 = MulAmt / 3; 13311 } 13312 if (MulAmt2 && 13313 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13314 DebugLoc DL = N->getDebugLoc(); 13315 13316 if (isPowerOf2_64(MulAmt2) && 13317 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13318 // If second multiplifer is pow2, issue it first. We want the multiply by 13319 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13320 // is an add. 13321 std::swap(MulAmt1, MulAmt2); 13322 13323 SDValue NewMul; 13324 if (isPowerOf2_64(MulAmt1)) 13325 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13326 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13327 else 13328 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13329 DAG.getConstant(MulAmt1, VT)); 13330 13331 if (isPowerOf2_64(MulAmt2)) 13332 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13333 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13334 else 13335 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13336 DAG.getConstant(MulAmt2, VT)); 13337 13338 // Do not add new nodes to DAG combiner worklist. 13339 DCI.CombineTo(N, NewMul, false); 13340 } 13341 return SDValue(); 13342} 13343 13344static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13345 SDValue N0 = N->getOperand(0); 13346 SDValue N1 = N->getOperand(1); 13347 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13348 EVT VT = N0.getValueType(); 13349 13350 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13351 // since the result of setcc_c is all zero's or all ones. 13352 if (VT.isInteger() && !VT.isVector() && 13353 N1C && N0.getOpcode() == ISD::AND && 13354 N0.getOperand(1).getOpcode() == ISD::Constant) { 13355 SDValue N00 = N0.getOperand(0); 13356 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13357 ((N00.getOpcode() == ISD::ANY_EXTEND || 13358 N00.getOpcode() == ISD::ZERO_EXTEND) && 13359 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13360 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13361 APInt ShAmt = N1C->getAPIntValue(); 13362 Mask = Mask.shl(ShAmt); 13363 if (Mask != 0) 13364 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13365 N00, DAG.getConstant(Mask, VT)); 13366 } 13367 } 13368 13369 13370 // Hardware support for vector shifts is sparse which makes us scalarize the 13371 // vector operations in many cases. Also, on sandybridge ADD is faster than 13372 // shl. 13373 // (shl V, 1) -> add V,V 13374 if (isSplatVector(N1.getNode())) { 13375 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13376 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13377 // We shift all of the values by one. In many cases we do not have 13378 // hardware support for this operation. This is better expressed as an ADD 13379 // of two values. 13380 if (N1C && (1 == N1C->getZExtValue())) { 13381 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13382 } 13383 } 13384 13385 return SDValue(); 13386} 13387 13388/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13389/// when possible. 13390static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13391 const X86Subtarget *Subtarget) { 13392 EVT VT = N->getValueType(0); 13393 if (N->getOpcode() == ISD::SHL) { 13394 SDValue V = PerformSHLCombine(N, DAG); 13395 if (V.getNode()) return V; 13396 } 13397 13398 // On X86 with SSE2 support, we can transform this to a vector shift if 13399 // all elements are shifted by the same amount. We can't do this in legalize 13400 // because the a constant vector is typically transformed to a constant pool 13401 // so we have no knowledge of the shift amount. 13402 if (!Subtarget->hasXMMInt()) 13403 return SDValue(); 13404 13405 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13406 (!Subtarget->hasAVX2() || 13407 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13408 return SDValue(); 13409 13410 SDValue ShAmtOp = N->getOperand(1); 13411 EVT EltVT = VT.getVectorElementType(); 13412 DebugLoc DL = N->getDebugLoc(); 13413 SDValue BaseShAmt = SDValue(); 13414 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13415 unsigned NumElts = VT.getVectorNumElements(); 13416 unsigned i = 0; 13417 for (; i != NumElts; ++i) { 13418 SDValue Arg = ShAmtOp.getOperand(i); 13419 if (Arg.getOpcode() == ISD::UNDEF) continue; 13420 BaseShAmt = Arg; 13421 break; 13422 } 13423 for (; i != NumElts; ++i) { 13424 SDValue Arg = ShAmtOp.getOperand(i); 13425 if (Arg.getOpcode() == ISD::UNDEF) continue; 13426 if (Arg != BaseShAmt) { 13427 return SDValue(); 13428 } 13429 } 13430 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13431 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13432 SDValue InVec = ShAmtOp.getOperand(0); 13433 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13434 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13435 unsigned i = 0; 13436 for (; i != NumElts; ++i) { 13437 SDValue Arg = InVec.getOperand(i); 13438 if (Arg.getOpcode() == ISD::UNDEF) continue; 13439 BaseShAmt = Arg; 13440 break; 13441 } 13442 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13443 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13444 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13445 if (C->getZExtValue() == SplatIdx) 13446 BaseShAmt = InVec.getOperand(1); 13447 } 13448 } 13449 if (BaseShAmt.getNode() == 0) 13450 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13451 DAG.getIntPtrConstant(0)); 13452 } else 13453 return SDValue(); 13454 13455 // The shift amount is an i32. 13456 if (EltVT.bitsGT(MVT::i32)) 13457 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13458 else if (EltVT.bitsLT(MVT::i32)) 13459 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13460 13461 // The shift amount is identical so we can do a vector shift. 13462 SDValue ValOp = N->getOperand(0); 13463 switch (N->getOpcode()) { 13464 default: 13465 llvm_unreachable("Unknown shift opcode!"); 13466 break; 13467 case ISD::SHL: 13468 if (VT == MVT::v2i64) 13469 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13470 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 13471 ValOp, BaseShAmt); 13472 if (VT == MVT::v4i32) 13473 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13474 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 13475 ValOp, BaseShAmt); 13476 if (VT == MVT::v8i16) 13477 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13478 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 13479 ValOp, BaseShAmt); 13480 if (VT == MVT::v4i64) 13481 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13482 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 13483 ValOp, BaseShAmt); 13484 if (VT == MVT::v8i32) 13485 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13486 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32), 13487 ValOp, BaseShAmt); 13488 if (VT == MVT::v16i16) 13489 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13490 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 13491 ValOp, BaseShAmt); 13492 break; 13493 case ISD::SRA: 13494 if (VT == MVT::v4i32) 13495 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13496 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 13497 ValOp, BaseShAmt); 13498 if (VT == MVT::v8i16) 13499 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13500 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 13501 ValOp, BaseShAmt); 13502 if (VT == MVT::v8i32) 13503 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13504 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32), 13505 ValOp, BaseShAmt); 13506 if (VT == MVT::v16i16) 13507 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13508 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32), 13509 ValOp, BaseShAmt); 13510 break; 13511 case ISD::SRL: 13512 if (VT == MVT::v2i64) 13513 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13514 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 13515 ValOp, BaseShAmt); 13516 if (VT == MVT::v4i32) 13517 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13518 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 13519 ValOp, BaseShAmt); 13520 if (VT == MVT::v8i16) 13521 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13522 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 13523 ValOp, BaseShAmt); 13524 if (VT == MVT::v4i64) 13525 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13526 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 13527 ValOp, BaseShAmt); 13528 if (VT == MVT::v8i32) 13529 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13530 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32), 13531 ValOp, BaseShAmt); 13532 if (VT == MVT::v16i16) 13533 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13534 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 13535 ValOp, BaseShAmt); 13536 break; 13537 } 13538 return SDValue(); 13539} 13540 13541 13542// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13543// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13544// and friends. Likewise for OR -> CMPNEQSS. 13545static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13546 TargetLowering::DAGCombinerInfo &DCI, 13547 const X86Subtarget *Subtarget) { 13548 unsigned opcode; 13549 13550 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13551 // we're requiring SSE2 for both. 13552 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13553 SDValue N0 = N->getOperand(0); 13554 SDValue N1 = N->getOperand(1); 13555 SDValue CMP0 = N0->getOperand(1); 13556 SDValue CMP1 = N1->getOperand(1); 13557 DebugLoc DL = N->getDebugLoc(); 13558 13559 // The SETCCs should both refer to the same CMP. 13560 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13561 return SDValue(); 13562 13563 SDValue CMP00 = CMP0->getOperand(0); 13564 SDValue CMP01 = CMP0->getOperand(1); 13565 EVT VT = CMP00.getValueType(); 13566 13567 if (VT == MVT::f32 || VT == MVT::f64) { 13568 bool ExpectingFlags = false; 13569 // Check for any users that want flags: 13570 for (SDNode::use_iterator UI = N->use_begin(), 13571 UE = N->use_end(); 13572 !ExpectingFlags && UI != UE; ++UI) 13573 switch (UI->getOpcode()) { 13574 default: 13575 case ISD::BR_CC: 13576 case ISD::BRCOND: 13577 case ISD::SELECT: 13578 ExpectingFlags = true; 13579 break; 13580 case ISD::CopyToReg: 13581 case ISD::SIGN_EXTEND: 13582 case ISD::ZERO_EXTEND: 13583 case ISD::ANY_EXTEND: 13584 break; 13585 } 13586 13587 if (!ExpectingFlags) { 13588 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13589 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13590 13591 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13592 X86::CondCode tmp = cc0; 13593 cc0 = cc1; 13594 cc1 = tmp; 13595 } 13596 13597 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13598 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13599 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13600 X86ISD::NodeType NTOperator = is64BitFP ? 13601 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13602 // FIXME: need symbolic constants for these magic numbers. 13603 // See X86ATTInstPrinter.cpp:printSSECC(). 13604 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13605 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13606 DAG.getConstant(x86cc, MVT::i8)); 13607 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13608 OnesOrZeroesF); 13609 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13610 DAG.getConstant(1, MVT::i32)); 13611 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13612 return OneBitOfTruth; 13613 } 13614 } 13615 } 13616 } 13617 return SDValue(); 13618} 13619 13620/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13621/// so it can be folded inside ANDNP. 13622static bool CanFoldXORWithAllOnes(const SDNode *N) { 13623 EVT VT = N->getValueType(0); 13624 13625 // Match direct AllOnes for 128 and 256-bit vectors 13626 if (ISD::isBuildVectorAllOnes(N)) 13627 return true; 13628 13629 // Look through a bit convert. 13630 if (N->getOpcode() == ISD::BITCAST) 13631 N = N->getOperand(0).getNode(); 13632 13633 // Sometimes the operand may come from a insert_subvector building a 256-bit 13634 // allones vector 13635 if (VT.getSizeInBits() == 256 && 13636 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13637 SDValue V1 = N->getOperand(0); 13638 SDValue V2 = N->getOperand(1); 13639 13640 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13641 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13642 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13643 ISD::isBuildVectorAllOnes(V2.getNode())) 13644 return true; 13645 } 13646 13647 return false; 13648} 13649 13650static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13651 TargetLowering::DAGCombinerInfo &DCI, 13652 const X86Subtarget *Subtarget) { 13653 if (DCI.isBeforeLegalizeOps()) 13654 return SDValue(); 13655 13656 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13657 if (R.getNode()) 13658 return R; 13659 13660 EVT VT = N->getValueType(0); 13661 13662 // Create ANDN, BLSI, and BLSR instructions 13663 // BLSI is X & (-X) 13664 // BLSR is X & (X-1) 13665 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13666 SDValue N0 = N->getOperand(0); 13667 SDValue N1 = N->getOperand(1); 13668 DebugLoc DL = N->getDebugLoc(); 13669 13670 // Check LHS for not 13671 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13672 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13673 // Check RHS for not 13674 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13675 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13676 13677 // Check LHS for neg 13678 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13679 isZero(N0.getOperand(0))) 13680 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13681 13682 // Check RHS for neg 13683 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13684 isZero(N1.getOperand(0))) 13685 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13686 13687 // Check LHS for X-1 13688 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13689 isAllOnes(N0.getOperand(1))) 13690 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13691 13692 // Check RHS for X-1 13693 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13694 isAllOnes(N1.getOperand(1))) 13695 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13696 13697 return SDValue(); 13698 } 13699 13700 // Want to form ANDNP nodes: 13701 // 1) In the hopes of then easily combining them with OR and AND nodes 13702 // to form PBLEND/PSIGN. 13703 // 2) To match ANDN packed intrinsics 13704 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13705 return SDValue(); 13706 13707 SDValue N0 = N->getOperand(0); 13708 SDValue N1 = N->getOperand(1); 13709 DebugLoc DL = N->getDebugLoc(); 13710 13711 // Check LHS for vnot 13712 if (N0.getOpcode() == ISD::XOR && 13713 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13714 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13715 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13716 13717 // Check RHS for vnot 13718 if (N1.getOpcode() == ISD::XOR && 13719 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13720 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13721 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13722 13723 return SDValue(); 13724} 13725 13726static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13727 TargetLowering::DAGCombinerInfo &DCI, 13728 const X86Subtarget *Subtarget) { 13729 if (DCI.isBeforeLegalizeOps()) 13730 return SDValue(); 13731 13732 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13733 if (R.getNode()) 13734 return R; 13735 13736 EVT VT = N->getValueType(0); 13737 13738 SDValue N0 = N->getOperand(0); 13739 SDValue N1 = N->getOperand(1); 13740 13741 // look for psign/blend 13742 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 13743 if (!Subtarget->hasSSSE3orAVX() || 13744 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 13745 return SDValue(); 13746 13747 // Canonicalize pandn to RHS 13748 if (N0.getOpcode() == X86ISD::ANDNP) 13749 std::swap(N0, N1); 13750 // or (and (m, x), (pandn m, y)) 13751 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13752 SDValue Mask = N1.getOperand(0); 13753 SDValue X = N1.getOperand(1); 13754 SDValue Y; 13755 if (N0.getOperand(0) == Mask) 13756 Y = N0.getOperand(1); 13757 if (N0.getOperand(1) == Mask) 13758 Y = N0.getOperand(0); 13759 13760 // Check to see if the mask appeared in both the AND and ANDNP and 13761 if (!Y.getNode()) 13762 return SDValue(); 13763 13764 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13765 if (Mask.getOpcode() != ISD::BITCAST || 13766 X.getOpcode() != ISD::BITCAST || 13767 Y.getOpcode() != ISD::BITCAST) 13768 return SDValue(); 13769 13770 // Look through mask bitcast. 13771 Mask = Mask.getOperand(0); 13772 EVT MaskVT = Mask.getValueType(); 13773 13774 // Validate that the Mask operand is a vector sra node. The sra node 13775 // will be an intrinsic. 13776 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 13777 return SDValue(); 13778 13779 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13780 // there is no psrai.b 13781 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 13782 case Intrinsic::x86_sse2_psrai_w: 13783 case Intrinsic::x86_sse2_psrai_d: 13784 case Intrinsic::x86_avx2_psrai_w: 13785 case Intrinsic::x86_avx2_psrai_d: 13786 break; 13787 default: return SDValue(); 13788 } 13789 13790 // Check that the SRA is all signbits. 13791 SDValue SraC = Mask.getOperand(2); 13792 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13793 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13794 if ((SraAmt + 1) != EltBits) 13795 return SDValue(); 13796 13797 DebugLoc DL = N->getDebugLoc(); 13798 13799 // Now we know we at least have a plendvb with the mask val. See if 13800 // we can form a psignb/w/d. 13801 // psign = x.type == y.type == mask.type && y = sub(0, x); 13802 X = X.getOperand(0); 13803 Y = Y.getOperand(0); 13804 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13805 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13806 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() && 13807 (EltBits == 8 || EltBits == 16 || EltBits == 32)) { 13808 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, 13809 Mask.getOperand(1)); 13810 return DAG.getNode(ISD::BITCAST, DL, VT, Sign); 13811 } 13812 // PBLENDVB only available on SSE 4.1 13813 if (!Subtarget->hasSSE41orAVX()) 13814 return SDValue(); 13815 13816 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 13817 13818 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 13819 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 13820 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 13821 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 13822 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13823 } 13824 } 13825 13826 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 13827 return SDValue(); 13828 13829 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13830 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13831 std::swap(N0, N1); 13832 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13833 return SDValue(); 13834 if (!N0.hasOneUse() || !N1.hasOneUse()) 13835 return SDValue(); 13836 13837 SDValue ShAmt0 = N0.getOperand(1); 13838 if (ShAmt0.getValueType() != MVT::i8) 13839 return SDValue(); 13840 SDValue ShAmt1 = N1.getOperand(1); 13841 if (ShAmt1.getValueType() != MVT::i8) 13842 return SDValue(); 13843 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13844 ShAmt0 = ShAmt0.getOperand(0); 13845 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13846 ShAmt1 = ShAmt1.getOperand(0); 13847 13848 DebugLoc DL = N->getDebugLoc(); 13849 unsigned Opc = X86ISD::SHLD; 13850 SDValue Op0 = N0.getOperand(0); 13851 SDValue Op1 = N1.getOperand(0); 13852 if (ShAmt0.getOpcode() == ISD::SUB) { 13853 Opc = X86ISD::SHRD; 13854 std::swap(Op0, Op1); 13855 std::swap(ShAmt0, ShAmt1); 13856 } 13857 13858 unsigned Bits = VT.getSizeInBits(); 13859 if (ShAmt1.getOpcode() == ISD::SUB) { 13860 SDValue Sum = ShAmt1.getOperand(0); 13861 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 13862 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 13863 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 13864 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 13865 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 13866 return DAG.getNode(Opc, DL, VT, 13867 Op0, Op1, 13868 DAG.getNode(ISD::TRUNCATE, DL, 13869 MVT::i8, ShAmt0)); 13870 } 13871 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 13872 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 13873 if (ShAmt0C && 13874 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 13875 return DAG.getNode(Opc, DL, VT, 13876 N0.getOperand(0), N1.getOperand(0), 13877 DAG.getNode(ISD::TRUNCATE, DL, 13878 MVT::i8, ShAmt0)); 13879 } 13880 13881 return SDValue(); 13882} 13883 13884// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 13885static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 13886 TargetLowering::DAGCombinerInfo &DCI, 13887 const X86Subtarget *Subtarget) { 13888 if (DCI.isBeforeLegalizeOps()) 13889 return SDValue(); 13890 13891 EVT VT = N->getValueType(0); 13892 13893 if (VT != MVT::i32 && VT != MVT::i64) 13894 return SDValue(); 13895 13896 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 13897 13898 // Create BLSMSK instructions by finding X ^ (X-1) 13899 SDValue N0 = N->getOperand(0); 13900 SDValue N1 = N->getOperand(1); 13901 DebugLoc DL = N->getDebugLoc(); 13902 13903 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13904 isAllOnes(N0.getOperand(1))) 13905 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 13906 13907 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13908 isAllOnes(N1.getOperand(1))) 13909 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 13910 13911 return SDValue(); 13912} 13913 13914/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 13915static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 13916 const X86Subtarget *Subtarget) { 13917 LoadSDNode *Ld = cast<LoadSDNode>(N); 13918 EVT RegVT = Ld->getValueType(0); 13919 EVT MemVT = Ld->getMemoryVT(); 13920 DebugLoc dl = Ld->getDebugLoc(); 13921 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13922 13923 ISD::LoadExtType Ext = Ld->getExtensionType(); 13924 13925 // If this is a vector EXT Load then attempt to optimize it using a 13926 // shuffle. We need SSE4 for the shuffles. 13927 // TODO: It is possible to support ZExt by zeroing the undef values 13928 // during the shuffle phase or after the shuffle. 13929 if (RegVT.isVector() && RegVT.isInteger() && 13930 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 13931 assert(MemVT != RegVT && "Cannot extend to the same type"); 13932 assert(MemVT.isVector() && "Must load a vector from memory"); 13933 13934 unsigned NumElems = RegVT.getVectorNumElements(); 13935 unsigned RegSz = RegVT.getSizeInBits(); 13936 unsigned MemSz = MemVT.getSizeInBits(); 13937 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 13938 // All sizes must be a power of two 13939 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 13940 13941 // Attempt to load the original value using a single load op. 13942 // Find a scalar type which is equal to the loaded word size. 13943 MVT SclrLoadTy = MVT::i8; 13944 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13945 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13946 MVT Tp = (MVT::SimpleValueType)tp; 13947 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 13948 SclrLoadTy = Tp; 13949 break; 13950 } 13951 } 13952 13953 // Proceed if a load word is found. 13954 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 13955 13956 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 13957 RegSz/SclrLoadTy.getSizeInBits()); 13958 13959 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 13960 RegSz/MemVT.getScalarType().getSizeInBits()); 13961 // Can't shuffle using an illegal type. 13962 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13963 13964 // Perform a single load. 13965 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 13966 Ld->getBasePtr(), 13967 Ld->getPointerInfo(), Ld->isVolatile(), 13968 Ld->isNonTemporal(), Ld->isInvariant(), 13969 Ld->getAlignment()); 13970 13971 // Insert the word loaded into a vector. 13972 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 13973 LoadUnitVecVT, ScalarLoad); 13974 13975 // Bitcast the loaded value to a vector of the original element type, in 13976 // the size of the target vector type. 13977 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 13978 ScalarInVector); 13979 unsigned SizeRatio = RegSz/MemSz; 13980 13981 // Redistribute the loaded elements into the different locations. 13982 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 13983 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 13984 13985 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 13986 DAG.getUNDEF(SlicedVec.getValueType()), 13987 ShuffleVec.data()); 13988 13989 // Bitcast to the requested type. 13990 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 13991 // Replace the original load with the new sequence 13992 // and return the new chain. 13993 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 13994 return SDValue(ScalarLoad.getNode(), 1); 13995 } 13996 13997 return SDValue(); 13998} 13999 14000/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14001static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14002 const X86Subtarget *Subtarget) { 14003 StoreSDNode *St = cast<StoreSDNode>(N); 14004 EVT VT = St->getValue().getValueType(); 14005 EVT StVT = St->getMemoryVT(); 14006 DebugLoc dl = St->getDebugLoc(); 14007 SDValue StoredVal = St->getOperand(1); 14008 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14009 14010 // If we are saving a concatenation of two XMM registers, perform two stores. 14011 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14012 // 128-bit ones. If in the future the cost becomes only one memory access the 14013 // first version would be better. 14014 if (VT.getSizeInBits() == 256 && 14015 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14016 StoredVal.getNumOperands() == 2) { 14017 14018 SDValue Value0 = StoredVal.getOperand(0); 14019 SDValue Value1 = StoredVal.getOperand(1); 14020 14021 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14022 SDValue Ptr0 = St->getBasePtr(); 14023 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14024 14025 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14026 St->getPointerInfo(), St->isVolatile(), 14027 St->isNonTemporal(), St->getAlignment()); 14028 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14029 St->getPointerInfo(), St->isVolatile(), 14030 St->isNonTemporal(), St->getAlignment()); 14031 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14032 } 14033 14034 // Optimize trunc store (of multiple scalars) to shuffle and store. 14035 // First, pack all of the elements in one place. Next, store to memory 14036 // in fewer chunks. 14037 if (St->isTruncatingStore() && VT.isVector()) { 14038 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14039 unsigned NumElems = VT.getVectorNumElements(); 14040 assert(StVT != VT && "Cannot truncate to the same type"); 14041 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14042 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14043 14044 // From, To sizes and ElemCount must be pow of two 14045 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14046 // We are going to use the original vector elt for storing. 14047 // Accumulated smaller vector elements must be a multiple of the store size. 14048 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14049 14050 unsigned SizeRatio = FromSz / ToSz; 14051 14052 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14053 14054 // Create a type on which we perform the shuffle 14055 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14056 StVT.getScalarType(), NumElems*SizeRatio); 14057 14058 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14059 14060 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14061 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14062 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14063 14064 // Can't shuffle using an illegal type 14065 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14066 14067 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14068 DAG.getUNDEF(WideVec.getValueType()), 14069 ShuffleVec.data()); 14070 // At this point all of the data is stored at the bottom of the 14071 // register. We now need to save it to mem. 14072 14073 // Find the largest store unit 14074 MVT StoreType = MVT::i8; 14075 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14076 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14077 MVT Tp = (MVT::SimpleValueType)tp; 14078 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14079 StoreType = Tp; 14080 } 14081 14082 // Bitcast the original vector into a vector of store-size units 14083 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14084 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14085 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14086 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14087 SmallVector<SDValue, 8> Chains; 14088 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14089 TLI.getPointerTy()); 14090 SDValue Ptr = St->getBasePtr(); 14091 14092 // Perform one or more big stores into memory. 14093 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14094 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14095 StoreType, ShuffWide, 14096 DAG.getIntPtrConstant(i)); 14097 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14098 St->getPointerInfo(), St->isVolatile(), 14099 St->isNonTemporal(), St->getAlignment()); 14100 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14101 Chains.push_back(Ch); 14102 } 14103 14104 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14105 Chains.size()); 14106 } 14107 14108 14109 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14110 // the FP state in cases where an emms may be missing. 14111 // A preferable solution to the general problem is to figure out the right 14112 // places to insert EMMS. This qualifies as a quick hack. 14113 14114 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14115 if (VT.getSizeInBits() != 64) 14116 return SDValue(); 14117 14118 const Function *F = DAG.getMachineFunction().getFunction(); 14119 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14120 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14121 && Subtarget->hasXMMInt(); 14122 if ((VT.isVector() || 14123 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14124 isa<LoadSDNode>(St->getValue()) && 14125 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14126 St->getChain().hasOneUse() && !St->isVolatile()) { 14127 SDNode* LdVal = St->getValue().getNode(); 14128 LoadSDNode *Ld = 0; 14129 int TokenFactorIndex = -1; 14130 SmallVector<SDValue, 8> Ops; 14131 SDNode* ChainVal = St->getChain().getNode(); 14132 // Must be a store of a load. We currently handle two cases: the load 14133 // is a direct child, and it's under an intervening TokenFactor. It is 14134 // possible to dig deeper under nested TokenFactors. 14135 if (ChainVal == LdVal) 14136 Ld = cast<LoadSDNode>(St->getChain()); 14137 else if (St->getValue().hasOneUse() && 14138 ChainVal->getOpcode() == ISD::TokenFactor) { 14139 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 14140 if (ChainVal->getOperand(i).getNode() == LdVal) { 14141 TokenFactorIndex = i; 14142 Ld = cast<LoadSDNode>(St->getValue()); 14143 } else 14144 Ops.push_back(ChainVal->getOperand(i)); 14145 } 14146 } 14147 14148 if (!Ld || !ISD::isNormalLoad(Ld)) 14149 return SDValue(); 14150 14151 // If this is not the MMX case, i.e. we are just turning i64 load/store 14152 // into f64 load/store, avoid the transformation if there are multiple 14153 // uses of the loaded value. 14154 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14155 return SDValue(); 14156 14157 DebugLoc LdDL = Ld->getDebugLoc(); 14158 DebugLoc StDL = N->getDebugLoc(); 14159 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14160 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14161 // pair instead. 14162 if (Subtarget->is64Bit() || F64IsLegal) { 14163 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14164 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14165 Ld->getPointerInfo(), Ld->isVolatile(), 14166 Ld->isNonTemporal(), Ld->isInvariant(), 14167 Ld->getAlignment()); 14168 SDValue NewChain = NewLd.getValue(1); 14169 if (TokenFactorIndex != -1) { 14170 Ops.push_back(NewChain); 14171 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14172 Ops.size()); 14173 } 14174 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14175 St->getPointerInfo(), 14176 St->isVolatile(), St->isNonTemporal(), 14177 St->getAlignment()); 14178 } 14179 14180 // Otherwise, lower to two pairs of 32-bit loads / stores. 14181 SDValue LoAddr = Ld->getBasePtr(); 14182 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14183 DAG.getConstant(4, MVT::i32)); 14184 14185 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14186 Ld->getPointerInfo(), 14187 Ld->isVolatile(), Ld->isNonTemporal(), 14188 Ld->isInvariant(), Ld->getAlignment()); 14189 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14190 Ld->getPointerInfo().getWithOffset(4), 14191 Ld->isVolatile(), Ld->isNonTemporal(), 14192 Ld->isInvariant(), 14193 MinAlign(Ld->getAlignment(), 4)); 14194 14195 SDValue NewChain = LoLd.getValue(1); 14196 if (TokenFactorIndex != -1) { 14197 Ops.push_back(LoLd); 14198 Ops.push_back(HiLd); 14199 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14200 Ops.size()); 14201 } 14202 14203 LoAddr = St->getBasePtr(); 14204 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14205 DAG.getConstant(4, MVT::i32)); 14206 14207 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14208 St->getPointerInfo(), 14209 St->isVolatile(), St->isNonTemporal(), 14210 St->getAlignment()); 14211 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14212 St->getPointerInfo().getWithOffset(4), 14213 St->isVolatile(), 14214 St->isNonTemporal(), 14215 MinAlign(St->getAlignment(), 4)); 14216 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14217 } 14218 return SDValue(); 14219} 14220 14221/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14222/// and return the operands for the horizontal operation in LHS and RHS. A 14223/// horizontal operation performs the binary operation on successive elements 14224/// of its first operand, then on successive elements of its second operand, 14225/// returning the resulting values in a vector. For example, if 14226/// A = < float a0, float a1, float a2, float a3 > 14227/// and 14228/// B = < float b0, float b1, float b2, float b3 > 14229/// then the result of doing a horizontal operation on A and B is 14230/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14231/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14232/// A horizontal-op B, for some already available A and B, and if so then LHS is 14233/// set to A, RHS to B, and the routine returns 'true'. 14234/// Note that the binary operation should have the property that if one of the 14235/// operands is UNDEF then the result is UNDEF. 14236static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14237 // Look for the following pattern: if 14238 // A = < float a0, float a1, float a2, float a3 > 14239 // B = < float b0, float b1, float b2, float b3 > 14240 // and 14241 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14242 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14243 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14244 // which is A horizontal-op B. 14245 14246 // At least one of the operands should be a vector shuffle. 14247 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14248 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14249 return false; 14250 14251 EVT VT = LHS.getValueType(); 14252 14253 assert((VT.is128BitVector() || VT.is256BitVector()) && 14254 "Unsupported vector type for horizontal add/sub"); 14255 14256 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14257 // operate independently on 128-bit lanes. 14258 unsigned NumElts = VT.getVectorNumElements(); 14259 unsigned NumLanes = VT.getSizeInBits()/128; 14260 unsigned NumLaneElts = NumElts / NumLanes; 14261 assert((NumLaneElts % 2 == 0) && 14262 "Vector type should have an even number of elements in each lane"); 14263 unsigned HalfLaneElts = NumLaneElts/2; 14264 14265 // View LHS in the form 14266 // LHS = VECTOR_SHUFFLE A, B, LMask 14267 // If LHS is not a shuffle then pretend it is the shuffle 14268 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14269 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14270 // type VT. 14271 SDValue A, B; 14272 SmallVector<int, 16> LMask(NumElts); 14273 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14274 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14275 A = LHS.getOperand(0); 14276 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14277 B = LHS.getOperand(1); 14278 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask); 14279 } else { 14280 if (LHS.getOpcode() != ISD::UNDEF) 14281 A = LHS; 14282 for (unsigned i = 0; i != NumElts; ++i) 14283 LMask[i] = i; 14284 } 14285 14286 // Likewise, view RHS in the form 14287 // RHS = VECTOR_SHUFFLE C, D, RMask 14288 SDValue C, D; 14289 SmallVector<int, 16> RMask(NumElts); 14290 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14291 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14292 C = RHS.getOperand(0); 14293 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14294 D = RHS.getOperand(1); 14295 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask); 14296 } else { 14297 if (RHS.getOpcode() != ISD::UNDEF) 14298 C = RHS; 14299 for (unsigned i = 0; i != NumElts; ++i) 14300 RMask[i] = i; 14301 } 14302 14303 // Check that the shuffles are both shuffling the same vectors. 14304 if (!(A == C && B == D) && !(A == D && B == C)) 14305 return false; 14306 14307 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14308 if (!A.getNode() && !B.getNode()) 14309 return false; 14310 14311 // If A and B occur in reverse order in RHS, then "swap" them (which means 14312 // rewriting the mask). 14313 if (A != C) 14314 CommuteVectorShuffleMask(RMask, NumElts); 14315 14316 // At this point LHS and RHS are equivalent to 14317 // LHS = VECTOR_SHUFFLE A, B, LMask 14318 // RHS = VECTOR_SHUFFLE A, B, RMask 14319 // Check that the masks correspond to performing a horizontal operation. 14320 for (unsigned i = 0; i != NumElts; ++i) { 14321 int LIdx = LMask[i], RIdx = RMask[i]; 14322 14323 // Ignore any UNDEF components. 14324 if (LIdx < 0 || RIdx < 0 || 14325 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14326 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14327 continue; 14328 14329 // Check that successive elements are being operated on. If not, this is 14330 // not a horizontal operation. 14331 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14332 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14333 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14334 if (!(LIdx == Index && RIdx == Index + 1) && 14335 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14336 return false; 14337 } 14338 14339 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14340 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14341 return true; 14342} 14343 14344/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14345static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14346 const X86Subtarget *Subtarget) { 14347 EVT VT = N->getValueType(0); 14348 SDValue LHS = N->getOperand(0); 14349 SDValue RHS = N->getOperand(1); 14350 14351 // Try to synthesize horizontal adds from adds of shuffles. 14352 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14353 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14354 isHorizontalBinOp(LHS, RHS, true)) 14355 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14356 return SDValue(); 14357} 14358 14359/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14360static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14361 const X86Subtarget *Subtarget) { 14362 EVT VT = N->getValueType(0); 14363 SDValue LHS = N->getOperand(0); 14364 SDValue RHS = N->getOperand(1); 14365 14366 // Try to synthesize horizontal subs from subs of shuffles. 14367 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14368 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14369 isHorizontalBinOp(LHS, RHS, false)) 14370 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14371 return SDValue(); 14372} 14373 14374/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14375/// X86ISD::FXOR nodes. 14376static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14377 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14378 // F[X]OR(0.0, x) -> x 14379 // F[X]OR(x, 0.0) -> x 14380 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14381 if (C->getValueAPF().isPosZero()) 14382 return N->getOperand(1); 14383 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14384 if (C->getValueAPF().isPosZero()) 14385 return N->getOperand(0); 14386 return SDValue(); 14387} 14388 14389/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14390static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14391 // FAND(0.0, x) -> 0.0 14392 // FAND(x, 0.0) -> 0.0 14393 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14394 if (C->getValueAPF().isPosZero()) 14395 return N->getOperand(0); 14396 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14397 if (C->getValueAPF().isPosZero()) 14398 return N->getOperand(1); 14399 return SDValue(); 14400} 14401 14402static SDValue PerformBTCombine(SDNode *N, 14403 SelectionDAG &DAG, 14404 TargetLowering::DAGCombinerInfo &DCI) { 14405 // BT ignores high bits in the bit index operand. 14406 SDValue Op1 = N->getOperand(1); 14407 if (Op1.hasOneUse()) { 14408 unsigned BitWidth = Op1.getValueSizeInBits(); 14409 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14410 APInt KnownZero, KnownOne; 14411 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14412 !DCI.isBeforeLegalizeOps()); 14413 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14414 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14415 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14416 DCI.CommitTargetLoweringOpt(TLO); 14417 } 14418 return SDValue(); 14419} 14420 14421static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14422 SDValue Op = N->getOperand(0); 14423 if (Op.getOpcode() == ISD::BITCAST) 14424 Op = Op.getOperand(0); 14425 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14426 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14427 VT.getVectorElementType().getSizeInBits() == 14428 OpVT.getVectorElementType().getSizeInBits()) { 14429 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14430 } 14431 return SDValue(); 14432} 14433 14434static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 14435 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14436 // (and (i32 x86isd::setcc_carry), 1) 14437 // This eliminates the zext. This transformation is necessary because 14438 // ISD::SETCC is always legalized to i8. 14439 DebugLoc dl = N->getDebugLoc(); 14440 SDValue N0 = N->getOperand(0); 14441 EVT VT = N->getValueType(0); 14442 if (N0.getOpcode() == ISD::AND && 14443 N0.hasOneUse() && 14444 N0.getOperand(0).hasOneUse()) { 14445 SDValue N00 = N0.getOperand(0); 14446 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14447 return SDValue(); 14448 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14449 if (!C || C->getZExtValue() != 1) 14450 return SDValue(); 14451 return DAG.getNode(ISD::AND, dl, VT, 14452 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14453 N00.getOperand(0), N00.getOperand(1)), 14454 DAG.getConstant(1, VT)); 14455 } 14456 14457 return SDValue(); 14458} 14459 14460// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14461static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14462 unsigned X86CC = N->getConstantOperandVal(0); 14463 SDValue EFLAG = N->getOperand(1); 14464 DebugLoc DL = N->getDebugLoc(); 14465 14466 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14467 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14468 // cases. 14469 if (X86CC == X86::COND_B) 14470 return DAG.getNode(ISD::AND, DL, MVT::i8, 14471 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14472 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14473 DAG.getConstant(1, MVT::i8)); 14474 14475 return SDValue(); 14476} 14477 14478static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14479 const X86TargetLowering *XTLI) { 14480 SDValue Op0 = N->getOperand(0); 14481 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14482 // a 32-bit target where SSE doesn't support i64->FP operations. 14483 if (Op0.getOpcode() == ISD::LOAD) { 14484 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14485 EVT VT = Ld->getValueType(0); 14486 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14487 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14488 !XTLI->getSubtarget()->is64Bit() && 14489 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14490 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14491 Ld->getChain(), Op0, DAG); 14492 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14493 return FILDChain; 14494 } 14495 } 14496 return SDValue(); 14497} 14498 14499// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14500static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14501 X86TargetLowering::DAGCombinerInfo &DCI) { 14502 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14503 // the result is either zero or one (depending on the input carry bit). 14504 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14505 if (X86::isZeroNode(N->getOperand(0)) && 14506 X86::isZeroNode(N->getOperand(1)) && 14507 // We don't have a good way to replace an EFLAGS use, so only do this when 14508 // dead right now. 14509 SDValue(N, 1).use_empty()) { 14510 DebugLoc DL = N->getDebugLoc(); 14511 EVT VT = N->getValueType(0); 14512 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14513 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14514 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14515 DAG.getConstant(X86::COND_B,MVT::i8), 14516 N->getOperand(2)), 14517 DAG.getConstant(1, VT)); 14518 return DCI.CombineTo(N, Res1, CarryOut); 14519 } 14520 14521 return SDValue(); 14522} 14523 14524// fold (add Y, (sete X, 0)) -> adc 0, Y 14525// (add Y, (setne X, 0)) -> sbb -1, Y 14526// (sub (sete X, 0), Y) -> sbb 0, Y 14527// (sub (setne X, 0), Y) -> adc -1, Y 14528static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14529 DebugLoc DL = N->getDebugLoc(); 14530 14531 // Look through ZExts. 14532 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14533 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14534 return SDValue(); 14535 14536 SDValue SetCC = Ext.getOperand(0); 14537 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14538 return SDValue(); 14539 14540 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14541 if (CC != X86::COND_E && CC != X86::COND_NE) 14542 return SDValue(); 14543 14544 SDValue Cmp = SetCC.getOperand(1); 14545 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14546 !X86::isZeroNode(Cmp.getOperand(1)) || 14547 !Cmp.getOperand(0).getValueType().isInteger()) 14548 return SDValue(); 14549 14550 SDValue CmpOp0 = Cmp.getOperand(0); 14551 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14552 DAG.getConstant(1, CmpOp0.getValueType())); 14553 14554 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14555 if (CC == X86::COND_NE) 14556 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14557 DL, OtherVal.getValueType(), OtherVal, 14558 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14559 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14560 DL, OtherVal.getValueType(), OtherVal, 14561 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14562} 14563 14564/// PerformADDCombine - Do target-specific dag combines on integer adds. 14565static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14566 const X86Subtarget *Subtarget) { 14567 EVT VT = N->getValueType(0); 14568 SDValue Op0 = N->getOperand(0); 14569 SDValue Op1 = N->getOperand(1); 14570 14571 // Try to synthesize horizontal adds from adds of shuffles. 14572 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14573 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || MVT::v8i32))) && 14574 isHorizontalBinOp(Op0, Op1, true)) 14575 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14576 14577 return OptimizeConditionalInDecrement(N, DAG); 14578} 14579 14580static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14581 const X86Subtarget *Subtarget) { 14582 SDValue Op0 = N->getOperand(0); 14583 SDValue Op1 = N->getOperand(1); 14584 14585 // X86 can't encode an immediate LHS of a sub. See if we can push the 14586 // negation into a preceding instruction. 14587 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14588 // If the RHS of the sub is a XOR with one use and a constant, invert the 14589 // immediate. Then add one to the LHS of the sub so we can turn 14590 // X-Y -> X+~Y+1, saving one register. 14591 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14592 isa<ConstantSDNode>(Op1.getOperand(1))) { 14593 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14594 EVT VT = Op0.getValueType(); 14595 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14596 Op1.getOperand(0), 14597 DAG.getConstant(~XorC, VT)); 14598 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14599 DAG.getConstant(C->getAPIntValue()+1, VT)); 14600 } 14601 } 14602 14603 // Try to synthesize horizontal adds from adds of shuffles. 14604 EVT VT = N->getValueType(0); 14605 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14606 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14607 isHorizontalBinOp(Op0, Op1, true)) 14608 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 14609 14610 return OptimizeConditionalInDecrement(N, DAG); 14611} 14612 14613// Helper which returns index of constant operand of a two-operand node. 14614static inline int GetConstOpIndexFor2OpNode(SDValue Op) { 14615 if (isa<ConstantSDNode>(Op.getOperand(0))) 14616 return 0; 14617 if (isa<ConstantSDNode>(Op.getOperand(1))) 14618 return 1; 14619 return -1; 14620} 14621 14622SDValue X86TargetLowering::PerformBrcondCombine(SDNode* N, SelectionDAG &DAG, 14623 DAGCombinerInfo &DCI) const { 14624 // Simplification of the PTEST-and-BRANCH pattern. 14625 // 14626 // The LLVM IR patterns targeted are: 14627 // %res = call i32 @llvm.x86.<func>(...) 14628 // %one = icmp {ne|eq} i32 %res, {0|1} 14629 // br i1 %one, label %bb1, label %bb2 14630 // and 14631 // %res = call i32 @llvm.x86.<func>(...) 14632 // %one = trunc i32 %res to i1 14633 // br i1 %one, label %bb1, label %bb2 14634 // where <func> is one of: 14635 // sse41.ptestz 14636 // sse41.ptestc 14637 // avx.ptestz.256 14638 // avx.ptestc.256 14639 // 14640 // The simplification is in folding of the following SDNode sequence: 14641 // X86ISD::PTEST 14642 // {X86ISD::SETCC | X86ISD::SETCC_CARRY} 14643 // [ISD::ZERO_EXTEND][[[ISD::AND,]ISD::TRUNCATE,]ISD::AND] 14644 // X86ISD::CMP 14645 // X86ISD::BRCOND(cond) 14646 // to the code sequence: 14647 // X86ISD::PTEST 14648 // X86ISD::BRCOND(!cond) 14649 14650 // The optimization is relevant only once the DAG contains x86 ISA (i.e. after 14651 // operation legalization). 14652 if (DCI.isBeforeLegalize() || DCI.isBeforeLegalizeOps() || DCI.isCalledByLegalizer()) 14653 return SDValue(); 14654 14655 // Below we iterate through DAG upwards, starting from BRCOND node and finishing 14656 // at PTEST node. We stop the iteration once we cannot find match with any of 14657 // the patterns which we are able to simplify. 14658 14659 // Indices for constant and variable operands in two-operand nodes 14660 int ConstOpIdx; 14661 unsigned int VarOpIdx; 14662 14663 // Validate that we're starting from the BRCOND node. 14664 assert(N->getOpcode() == X86ISD::BRCOND && "Should start from conditional branch!"); 14665 // Check that the BRCOND condition is ZF. 14666 if (!isa<ConstantSDNode>(N->getOperand(2))) 14667 return SDValue(); 14668 uint64_t BranchCond = N->getConstantOperandVal(2); 14669 if (BranchCond != X86::COND_NE && BranchCond != X86::COND_E) 14670 return SDValue(); 14671 14672 // 1st step upwards: verify CMP use. 14673 SDValue CmpValue = N->getOperand(3); 14674 if (CmpValue.getOpcode() != X86ISD::CMP) 14675 return SDValue(); 14676 // Check that the CMP comparison is with 0. 14677 if ((ConstOpIdx = GetConstOpIndexFor2OpNode(CmpValue)) == -1) 14678 return SDValue(); 14679 VarOpIdx = (ConstOpIdx == 0)? 1:0; 14680 uint64_t CompareWith = CmpValue.getConstantOperandVal((unsigned int)ConstOpIdx); 14681 if (CompareWith != 0 && CompareWith != 1) 14682 return SDValue(); 14683 14684 // 2rd step upwards: cover alternative paths between pre-BRCOND CMP and PTEST 14685 // return value analysis. 14686 14687 SDValue SVOp = CmpValue.getOperand(VarOpIdx); 14688 // Verify optional AND use. 14689 if (SVOp.getOpcode() == ISD::AND) { 14690 // Check that the AND is with 0x1. 14691 if ((ConstOpIdx = GetConstOpIndexFor2OpNode(SVOp)) == -1) 14692 return SDValue(); 14693 VarOpIdx = (ConstOpIdx == 0)? 1:0; 14694 if (SVOp.getConstantOperandVal((unsigned int)ConstOpIdx) != 1) 14695 return SDValue(); 14696 // Step upwards: verify optional TRUNCATE use. 14697 SVOp = SVOp.getOperand(VarOpIdx); 14698 if (SVOp.getOpcode() == ISD::TRUNCATE) { 14699 // Step upwards: verify optional AND or ZERO_EXTEND use. 14700 SVOp = SVOp.getOperand(0); 14701 if (SVOp.getOpcode() == ISD::AND) { 14702 // Check that the AND is with 0x1. 14703 if ((ConstOpIdx = GetConstOpIndexFor2OpNode(SVOp)) == -1) 14704 return SDValue(); 14705 VarOpIdx = (ConstOpIdx == 0)? 1:0; 14706 if (SVOp.getConstantOperandVal((unsigned int)ConstOpIdx) != 1) 14707 return SDValue(); 14708 // Step upwards. 14709 SVOp = SVOp.getOperand(VarOpIdx); 14710 } 14711 } 14712 } 14713 // Verify optional ZERO_EXTEND use 14714 if (SVOp.getOpcode() == ISD::ZERO_EXTEND) { 14715 // Step upwards. 14716 SVOp = SVOp.getOperand(0); 14717 } 14718 14719 // 3rd step upwards: verify SETCC or SETCC_CARRY use. 14720 unsigned SetCcOP = SVOp.getOpcode(); 14721 if (SetCcOP != X86ISD::SETCC && SetCcOP != X86ISD::SETCC_CARRY) 14722 return SDValue(); 14723 // Check that the SETCC/SETCC_CARRY flag is 'COND_E' (for ptestz) or 'COND_B' (for ptestc) 14724 if ((ConstOpIdx = GetConstOpIndexFor2OpNode(SVOp)) == -1) 14725 return SDValue(); 14726 VarOpIdx = (ConstOpIdx == 0)? 1:0; 14727 uint64_t SetCond = SVOp.getConstantOperandVal((unsigned int)ConstOpIdx); 14728 if (SetCond != X86::COND_E && SetCond != X86::COND_B) 14729 return SDValue(); 14730 14731 // 4th step upwards: verify PTEST use. 14732 SDValue PtestValue = SVOp.getOperand(VarOpIdx); 14733 if (PtestValue.getOpcode() != X86ISD::PTEST) 14734 return SDValue(); 14735 14736 // The chain to be folded is recognized. We can fold it now. 14737 14738 // At first - select the branch condition. 14739 SDValue CC = DAG.getConstant(SetCond, MVT::i8); 14740 if ((CompareWith == 1 && BranchCond == X86::COND_NE) || 14741 (CompareWith == 0 && BranchCond == X86::COND_E)) { 14742 // Invert branch condition. 14743 CC = (SetCond == X86::COND_E? DAG.getConstant(X86::COND_NE, MVT::i8): 14744 DAG.getConstant(X86::COND_AE, MVT::i8)); 14745 } 14746 // Then - update the BRCOND node. 14747 // Resno is set to 0 as X86ISD::BRCOND has single return value. 14748 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), 14749 CC, PtestValue), 0); 14750 14751} 14752 14753SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14754 DAGCombinerInfo &DCI) const { 14755 SelectionDAG &DAG = DCI.DAG; 14756 switch (N->getOpcode()) { 14757 default: break; 14758 case ISD::EXTRACT_VECTOR_ELT: 14759 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14760 case ISD::VSELECT: 14761 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 14762 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14763 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 14764 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 14765 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14766 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14767 case ISD::SHL: 14768 case ISD::SRA: 14769 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 14770 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14771 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14772 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14773 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14774 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14775 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14776 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14777 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14778 case X86ISD::FXOR: 14779 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14780 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14781 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14782 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14783 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 14784 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14785 case X86ISD::SHUFP: // Handle all target specific shuffles 14786 case X86ISD::PALIGN: 14787 case X86ISD::UNPCKH: 14788 case X86ISD::UNPCKL: 14789 case X86ISD::MOVHLPS: 14790 case X86ISD::MOVLHPS: 14791 case X86ISD::PSHUFD: 14792 case X86ISD::PSHUFHW: 14793 case X86ISD::PSHUFLW: 14794 case X86ISD::MOVSS: 14795 case X86ISD::MOVSD: 14796 case X86ISD::VPERMILP: 14797 case X86ISD::VPERM2X128: 14798 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14799 case X86ISD::BRCOND: return PerformBrcondCombine(N, DAG, DCI); 14800 } 14801 14802 return SDValue(); 14803} 14804 14805/// isTypeDesirableForOp - Return true if the target has native support for 14806/// the specified value type and it is 'desirable' to use the type for the 14807/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14808/// instruction encodings are longer and some i16 instructions are slow. 14809bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14810 if (!isTypeLegal(VT)) 14811 return false; 14812 if (VT != MVT::i16) 14813 return true; 14814 14815 switch (Opc) { 14816 default: 14817 return true; 14818 case ISD::LOAD: 14819 case ISD::SIGN_EXTEND: 14820 case ISD::ZERO_EXTEND: 14821 case ISD::ANY_EXTEND: 14822 case ISD::SHL: 14823 case ISD::SRL: 14824 case ISD::SUB: 14825 case ISD::ADD: 14826 case ISD::MUL: 14827 case ISD::AND: 14828 case ISD::OR: 14829 case ISD::XOR: 14830 return false; 14831 } 14832} 14833 14834/// IsDesirableToPromoteOp - This method query the target whether it is 14835/// beneficial for dag combiner to promote the specified node. If true, it 14836/// should return the desired promotion type by reference. 14837bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14838 EVT VT = Op.getValueType(); 14839 if (VT != MVT::i16) 14840 return false; 14841 14842 bool Promote = false; 14843 bool Commute = false; 14844 switch (Op.getOpcode()) { 14845 default: break; 14846 case ISD::LOAD: { 14847 LoadSDNode *LD = cast<LoadSDNode>(Op); 14848 // If the non-extending load has a single use and it's not live out, then it 14849 // might be folded. 14850 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14851 Op.hasOneUse()*/) { 14852 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14853 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14854 // The only case where we'd want to promote LOAD (rather then it being 14855 // promoted as an operand is when it's only use is liveout. 14856 if (UI->getOpcode() != ISD::CopyToReg) 14857 return false; 14858 } 14859 } 14860 Promote = true; 14861 break; 14862 } 14863 case ISD::SIGN_EXTEND: 14864 case ISD::ZERO_EXTEND: 14865 case ISD::ANY_EXTEND: 14866 Promote = true; 14867 break; 14868 case ISD::SHL: 14869 case ISD::SRL: { 14870 SDValue N0 = Op.getOperand(0); 14871 // Look out for (store (shl (load), x)). 14872 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14873 return false; 14874 Promote = true; 14875 break; 14876 } 14877 case ISD::ADD: 14878 case ISD::MUL: 14879 case ISD::AND: 14880 case ISD::OR: 14881 case ISD::XOR: 14882 Commute = true; 14883 // fallthrough 14884 case ISD::SUB: { 14885 SDValue N0 = Op.getOperand(0); 14886 SDValue N1 = Op.getOperand(1); 14887 if (!Commute && MayFoldLoad(N1)) 14888 return false; 14889 // Avoid disabling potential load folding opportunities. 14890 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 14891 return false; 14892 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 14893 return false; 14894 Promote = true; 14895 } 14896 } 14897 14898 PVT = MVT::i32; 14899 return Promote; 14900} 14901 14902//===----------------------------------------------------------------------===// 14903// X86 Inline Assembly Support 14904//===----------------------------------------------------------------------===// 14905 14906namespace { 14907 // Helper to match a string separated by whitespace. 14908 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 14909 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 14910 14911 for (unsigned i = 0, e = args.size(); i != e; ++i) { 14912 StringRef piece(*args[i]); 14913 if (!s.startswith(piece)) // Check if the piece matches. 14914 return false; 14915 14916 s = s.substr(piece.size()); 14917 StringRef::size_type pos = s.find_first_not_of(" \t"); 14918 if (pos == 0) // We matched a prefix. 14919 return false; 14920 14921 s = s.substr(pos); 14922 } 14923 14924 return s.empty(); 14925 } 14926 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 14927} 14928 14929bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 14930 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 14931 14932 std::string AsmStr = IA->getAsmString(); 14933 14934 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14935 if (!Ty || Ty->getBitWidth() % 16 != 0) 14936 return false; 14937 14938 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 14939 SmallVector<StringRef, 4> AsmPieces; 14940 SplitString(AsmStr, AsmPieces, ";\n"); 14941 14942 switch (AsmPieces.size()) { 14943 default: return false; 14944 case 1: 14945 // FIXME: this should verify that we are targeting a 486 or better. If not, 14946 // we will turn this bswap into something that will be lowered to logical 14947 // ops instead of emitting the bswap asm. For now, we don't support 486 or 14948 // lower so don't worry about this. 14949 // bswap $0 14950 if (matchAsm(AsmPieces[0], "bswap", "$0") || 14951 matchAsm(AsmPieces[0], "bswapl", "$0") || 14952 matchAsm(AsmPieces[0], "bswapq", "$0") || 14953 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 14954 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 14955 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 14956 // No need to check constraints, nothing other than the equivalent of 14957 // "=r,0" would be valid here. 14958 return IntrinsicLowering::LowerToByteSwap(CI); 14959 } 14960 14961 // rorw $$8, ${0:w} --> llvm.bswap.i16 14962 if (CI->getType()->isIntegerTy(16) && 14963 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 14964 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 14965 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 14966 AsmPieces.clear(); 14967 const std::string &ConstraintsStr = IA->getConstraintString(); 14968 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14969 std::sort(AsmPieces.begin(), AsmPieces.end()); 14970 if (AsmPieces.size() == 4 && 14971 AsmPieces[0] == "~{cc}" && 14972 AsmPieces[1] == "~{dirflag}" && 14973 AsmPieces[2] == "~{flags}" && 14974 AsmPieces[3] == "~{fpsr}") 14975 return IntrinsicLowering::LowerToByteSwap(CI); 14976 } 14977 break; 14978 case 3: 14979 if (CI->getType()->isIntegerTy(32) && 14980 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 14981 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 14982 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 14983 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 14984 AsmPieces.clear(); 14985 const std::string &ConstraintsStr = IA->getConstraintString(); 14986 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14987 std::sort(AsmPieces.begin(), AsmPieces.end()); 14988 if (AsmPieces.size() == 4 && 14989 AsmPieces[0] == "~{cc}" && 14990 AsmPieces[1] == "~{dirflag}" && 14991 AsmPieces[2] == "~{flags}" && 14992 AsmPieces[3] == "~{fpsr}") 14993 return IntrinsicLowering::LowerToByteSwap(CI); 14994 } 14995 14996 if (CI->getType()->isIntegerTy(64)) { 14997 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 14998 if (Constraints.size() >= 2 && 14999 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15000 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15001 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15002 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15003 matchAsm(AsmPieces[1], "bswap", "%edx") && 15004 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15005 return IntrinsicLowering::LowerToByteSwap(CI); 15006 } 15007 } 15008 break; 15009 } 15010 return false; 15011} 15012 15013 15014 15015/// getConstraintType - Given a constraint letter, return the type of 15016/// constraint it is for this target. 15017X86TargetLowering::ConstraintType 15018X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15019 if (Constraint.size() == 1) { 15020 switch (Constraint[0]) { 15021 case 'R': 15022 case 'q': 15023 case 'Q': 15024 case 'f': 15025 case 't': 15026 case 'u': 15027 case 'y': 15028 case 'x': 15029 case 'Y': 15030 case 'l': 15031 return C_RegisterClass; 15032 case 'a': 15033 case 'b': 15034 case 'c': 15035 case 'd': 15036 case 'S': 15037 case 'D': 15038 case 'A': 15039 return C_Register; 15040 case 'I': 15041 case 'J': 15042 case 'K': 15043 case 'L': 15044 case 'M': 15045 case 'N': 15046 case 'G': 15047 case 'C': 15048 case 'e': 15049 case 'Z': 15050 return C_Other; 15051 default: 15052 break; 15053 } 15054 } 15055 return TargetLowering::getConstraintType(Constraint); 15056} 15057 15058/// Examine constraint type and operand type and determine a weight value. 15059/// This object must already have been set up with the operand type 15060/// and the current alternative constraint selected. 15061TargetLowering::ConstraintWeight 15062 X86TargetLowering::getSingleConstraintMatchWeight( 15063 AsmOperandInfo &info, const char *constraint) const { 15064 ConstraintWeight weight = CW_Invalid; 15065 Value *CallOperandVal = info.CallOperandVal; 15066 // If we don't have a value, we can't do a match, 15067 // but allow it at the lowest weight. 15068 if (CallOperandVal == NULL) 15069 return CW_Default; 15070 Type *type = CallOperandVal->getType(); 15071 // Look at the constraint type. 15072 switch (*constraint) { 15073 default: 15074 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15075 case 'R': 15076 case 'q': 15077 case 'Q': 15078 case 'a': 15079 case 'b': 15080 case 'c': 15081 case 'd': 15082 case 'S': 15083 case 'D': 15084 case 'A': 15085 if (CallOperandVal->getType()->isIntegerTy()) 15086 weight = CW_SpecificReg; 15087 break; 15088 case 'f': 15089 case 't': 15090 case 'u': 15091 if (type->isFloatingPointTy()) 15092 weight = CW_SpecificReg; 15093 break; 15094 case 'y': 15095 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15096 weight = CW_SpecificReg; 15097 break; 15098 case 'x': 15099 case 'Y': 15100 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) || 15101 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15102 weight = CW_Register; 15103 break; 15104 case 'I': 15105 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15106 if (C->getZExtValue() <= 31) 15107 weight = CW_Constant; 15108 } 15109 break; 15110 case 'J': 15111 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15112 if (C->getZExtValue() <= 63) 15113 weight = CW_Constant; 15114 } 15115 break; 15116 case 'K': 15117 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15118 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15119 weight = CW_Constant; 15120 } 15121 break; 15122 case 'L': 15123 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15124 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15125 weight = CW_Constant; 15126 } 15127 break; 15128 case 'M': 15129 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15130 if (C->getZExtValue() <= 3) 15131 weight = CW_Constant; 15132 } 15133 break; 15134 case 'N': 15135 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15136 if (C->getZExtValue() <= 0xff) 15137 weight = CW_Constant; 15138 } 15139 break; 15140 case 'G': 15141 case 'C': 15142 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15143 weight = CW_Constant; 15144 } 15145 break; 15146 case 'e': 15147 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15148 if ((C->getSExtValue() >= -0x80000000LL) && 15149 (C->getSExtValue() <= 0x7fffffffLL)) 15150 weight = CW_Constant; 15151 } 15152 break; 15153 case 'Z': 15154 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15155 if (C->getZExtValue() <= 0xffffffff) 15156 weight = CW_Constant; 15157 } 15158 break; 15159 } 15160 return weight; 15161} 15162 15163/// LowerXConstraint - try to replace an X constraint, which matches anything, 15164/// with another that has more specific requirements based on the type of the 15165/// corresponding operand. 15166const char *X86TargetLowering:: 15167LowerXConstraint(EVT ConstraintVT) const { 15168 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15169 // 'f' like normal targets. 15170 if (ConstraintVT.isFloatingPoint()) { 15171 if (Subtarget->hasXMMInt()) 15172 return "Y"; 15173 if (Subtarget->hasXMM()) 15174 return "x"; 15175 } 15176 15177 return TargetLowering::LowerXConstraint(ConstraintVT); 15178} 15179 15180/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15181/// vector. If it is invalid, don't add anything to Ops. 15182void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15183 std::string &Constraint, 15184 std::vector<SDValue>&Ops, 15185 SelectionDAG &DAG) const { 15186 SDValue Result(0, 0); 15187 15188 // Only support length 1 constraints for now. 15189 if (Constraint.length() > 1) return; 15190 15191 char ConstraintLetter = Constraint[0]; 15192 switch (ConstraintLetter) { 15193 default: break; 15194 case 'I': 15195 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15196 if (C->getZExtValue() <= 31) { 15197 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15198 break; 15199 } 15200 } 15201 return; 15202 case 'J': 15203 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15204 if (C->getZExtValue() <= 63) { 15205 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15206 break; 15207 } 15208 } 15209 return; 15210 case 'K': 15211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15212 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15213 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15214 break; 15215 } 15216 } 15217 return; 15218 case 'N': 15219 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15220 if (C->getZExtValue() <= 255) { 15221 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15222 break; 15223 } 15224 } 15225 return; 15226 case 'e': { 15227 // 32-bit signed value 15228 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15229 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15230 C->getSExtValue())) { 15231 // Widen to 64 bits here to get it sign extended. 15232 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15233 break; 15234 } 15235 // FIXME gcc accepts some relocatable values here too, but only in certain 15236 // memory models; it's complicated. 15237 } 15238 return; 15239 } 15240 case 'Z': { 15241 // 32-bit unsigned value 15242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15243 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15244 C->getZExtValue())) { 15245 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15246 break; 15247 } 15248 } 15249 // FIXME gcc accepts some relocatable values here too, but only in certain 15250 // memory models; it's complicated. 15251 return; 15252 } 15253 case 'i': { 15254 // Literal immediates are always ok. 15255 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15256 // Widen to 64 bits here to get it sign extended. 15257 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15258 break; 15259 } 15260 15261 // In any sort of PIC mode addresses need to be computed at runtime by 15262 // adding in a register or some sort of table lookup. These can't 15263 // be used as immediates. 15264 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15265 return; 15266 15267 // If we are in non-pic codegen mode, we allow the address of a global (with 15268 // an optional displacement) to be used with 'i'. 15269 GlobalAddressSDNode *GA = 0; 15270 int64_t Offset = 0; 15271 15272 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15273 while (1) { 15274 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15275 Offset += GA->getOffset(); 15276 break; 15277 } else if (Op.getOpcode() == ISD::ADD) { 15278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15279 Offset += C->getZExtValue(); 15280 Op = Op.getOperand(0); 15281 continue; 15282 } 15283 } else if (Op.getOpcode() == ISD::SUB) { 15284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15285 Offset += -C->getZExtValue(); 15286 Op = Op.getOperand(0); 15287 continue; 15288 } 15289 } 15290 15291 // Otherwise, this isn't something we can handle, reject it. 15292 return; 15293 } 15294 15295 const GlobalValue *GV = GA->getGlobal(); 15296 // If we require an extra load to get this address, as in PIC mode, we 15297 // can't accept it. 15298 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15299 getTargetMachine()))) 15300 return; 15301 15302 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15303 GA->getValueType(0), Offset); 15304 break; 15305 } 15306 } 15307 15308 if (Result.getNode()) { 15309 Ops.push_back(Result); 15310 return; 15311 } 15312 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15313} 15314 15315std::pair<unsigned, const TargetRegisterClass*> 15316X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15317 EVT VT) const { 15318 // First, see if this is a constraint that directly corresponds to an LLVM 15319 // register class. 15320 if (Constraint.size() == 1) { 15321 // GCC Constraint Letters 15322 switch (Constraint[0]) { 15323 default: break; 15324 // TODO: Slight differences here in allocation order and leaving 15325 // RIP in the class. Do they matter any more here than they do 15326 // in the normal allocation? 15327 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15328 if (Subtarget->is64Bit()) { 15329 if (VT == MVT::i32 || VT == MVT::f32) 15330 return std::make_pair(0U, X86::GR32RegisterClass); 15331 else if (VT == MVT::i16) 15332 return std::make_pair(0U, X86::GR16RegisterClass); 15333 else if (VT == MVT::i8 || VT == MVT::i1) 15334 return std::make_pair(0U, X86::GR8RegisterClass); 15335 else if (VT == MVT::i64 || VT == MVT::f64) 15336 return std::make_pair(0U, X86::GR64RegisterClass); 15337 break; 15338 } 15339 // 32-bit fallthrough 15340 case 'Q': // Q_REGS 15341 if (VT == MVT::i32 || VT == MVT::f32) 15342 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15343 else if (VT == MVT::i16) 15344 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15345 else if (VT == MVT::i8 || VT == MVT::i1) 15346 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15347 else if (VT == MVT::i64) 15348 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15349 break; 15350 case 'r': // GENERAL_REGS 15351 case 'l': // INDEX_REGS 15352 if (VT == MVT::i8 || VT == MVT::i1) 15353 return std::make_pair(0U, X86::GR8RegisterClass); 15354 if (VT == MVT::i16) 15355 return std::make_pair(0U, X86::GR16RegisterClass); 15356 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15357 return std::make_pair(0U, X86::GR32RegisterClass); 15358 return std::make_pair(0U, X86::GR64RegisterClass); 15359 case 'R': // LEGACY_REGS 15360 if (VT == MVT::i8 || VT == MVT::i1) 15361 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15362 if (VT == MVT::i16) 15363 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15364 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15365 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15366 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15367 case 'f': // FP Stack registers. 15368 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15369 // value to the correct fpstack register class. 15370 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15371 return std::make_pair(0U, X86::RFP32RegisterClass); 15372 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15373 return std::make_pair(0U, X86::RFP64RegisterClass); 15374 return std::make_pair(0U, X86::RFP80RegisterClass); 15375 case 'y': // MMX_REGS if MMX allowed. 15376 if (!Subtarget->hasMMX()) break; 15377 return std::make_pair(0U, X86::VR64RegisterClass); 15378 case 'Y': // SSE_REGS if SSE2 allowed 15379 if (!Subtarget->hasXMMInt()) break; 15380 // FALL THROUGH. 15381 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15382 if (!Subtarget->hasXMM()) break; 15383 15384 switch (VT.getSimpleVT().SimpleTy) { 15385 default: break; 15386 // Scalar SSE types. 15387 case MVT::f32: 15388 case MVT::i32: 15389 return std::make_pair(0U, X86::FR32RegisterClass); 15390 case MVT::f64: 15391 case MVT::i64: 15392 return std::make_pair(0U, X86::FR64RegisterClass); 15393 // Vector types. 15394 case MVT::v16i8: 15395 case MVT::v8i16: 15396 case MVT::v4i32: 15397 case MVT::v2i64: 15398 case MVT::v4f32: 15399 case MVT::v2f64: 15400 return std::make_pair(0U, X86::VR128RegisterClass); 15401 // AVX types. 15402 case MVT::v32i8: 15403 case MVT::v16i16: 15404 case MVT::v8i32: 15405 case MVT::v4i64: 15406 case MVT::v8f32: 15407 case MVT::v4f64: 15408 return std::make_pair(0U, X86::VR256RegisterClass); 15409 15410 } 15411 break; 15412 } 15413 } 15414 15415 // Use the default implementation in TargetLowering to convert the register 15416 // constraint into a member of a register class. 15417 std::pair<unsigned, const TargetRegisterClass*> Res; 15418 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15419 15420 // Not found as a standard register? 15421 if (Res.second == 0) { 15422 // Map st(0) -> st(7) -> ST0 15423 if (Constraint.size() == 7 && Constraint[0] == '{' && 15424 tolower(Constraint[1]) == 's' && 15425 tolower(Constraint[2]) == 't' && 15426 Constraint[3] == '(' && 15427 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15428 Constraint[5] == ')' && 15429 Constraint[6] == '}') { 15430 15431 Res.first = X86::ST0+Constraint[4]-'0'; 15432 Res.second = X86::RFP80RegisterClass; 15433 return Res; 15434 } 15435 15436 // GCC allows "st(0)" to be called just plain "st". 15437 if (StringRef("{st}").equals_lower(Constraint)) { 15438 Res.first = X86::ST0; 15439 Res.second = X86::RFP80RegisterClass; 15440 return Res; 15441 } 15442 15443 // flags -> EFLAGS 15444 if (StringRef("{flags}").equals_lower(Constraint)) { 15445 Res.first = X86::EFLAGS; 15446 Res.second = X86::CCRRegisterClass; 15447 return Res; 15448 } 15449 15450 // 'A' means EAX + EDX. 15451 if (Constraint == "A") { 15452 Res.first = X86::EAX; 15453 Res.second = X86::GR32_ADRegisterClass; 15454 return Res; 15455 } 15456 return Res; 15457 } 15458 15459 // Otherwise, check to see if this is a register class of the wrong value 15460 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15461 // turn into {ax},{dx}. 15462 if (Res.second->hasType(VT)) 15463 return Res; // Correct type already, nothing to do. 15464 15465 // All of the single-register GCC register classes map their values onto 15466 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15467 // really want an 8-bit or 32-bit register, map to the appropriate register 15468 // class and return the appropriate register. 15469 if (Res.second == X86::GR16RegisterClass) { 15470 if (VT == MVT::i8) { 15471 unsigned DestReg = 0; 15472 switch (Res.first) { 15473 default: break; 15474 case X86::AX: DestReg = X86::AL; break; 15475 case X86::DX: DestReg = X86::DL; break; 15476 case X86::CX: DestReg = X86::CL; break; 15477 case X86::BX: DestReg = X86::BL; break; 15478 } 15479 if (DestReg) { 15480 Res.first = DestReg; 15481 Res.second = X86::GR8RegisterClass; 15482 } 15483 } else if (VT == MVT::i32) { 15484 unsigned DestReg = 0; 15485 switch (Res.first) { 15486 default: break; 15487 case X86::AX: DestReg = X86::EAX; break; 15488 case X86::DX: DestReg = X86::EDX; break; 15489 case X86::CX: DestReg = X86::ECX; break; 15490 case X86::BX: DestReg = X86::EBX; break; 15491 case X86::SI: DestReg = X86::ESI; break; 15492 case X86::DI: DestReg = X86::EDI; break; 15493 case X86::BP: DestReg = X86::EBP; break; 15494 case X86::SP: DestReg = X86::ESP; break; 15495 } 15496 if (DestReg) { 15497 Res.first = DestReg; 15498 Res.second = X86::GR32RegisterClass; 15499 } 15500 } else if (VT == MVT::i64) { 15501 unsigned DestReg = 0; 15502 switch (Res.first) { 15503 default: break; 15504 case X86::AX: DestReg = X86::RAX; break; 15505 case X86::DX: DestReg = X86::RDX; break; 15506 case X86::CX: DestReg = X86::RCX; break; 15507 case X86::BX: DestReg = X86::RBX; break; 15508 case X86::SI: DestReg = X86::RSI; break; 15509 case X86::DI: DestReg = X86::RDI; break; 15510 case X86::BP: DestReg = X86::RBP; break; 15511 case X86::SP: DestReg = X86::RSP; break; 15512 } 15513 if (DestReg) { 15514 Res.first = DestReg; 15515 Res.second = X86::GR64RegisterClass; 15516 } 15517 } 15518 } else if (Res.second == X86::FR32RegisterClass || 15519 Res.second == X86::FR64RegisterClass || 15520 Res.second == X86::VR128RegisterClass) { 15521 // Handle references to XMM physical registers that got mapped into the 15522 // wrong class. This can happen with constraints like {xmm0} where the 15523 // target independent register mapper will just pick the first match it can 15524 // find, ignoring the required type. 15525 if (VT == MVT::f32) 15526 Res.second = X86::FR32RegisterClass; 15527 else if (VT == MVT::f64) 15528 Res.second = X86::FR64RegisterClass; 15529 else if (X86::VR128RegisterClass->hasType(VT)) 15530 Res.second = X86::VR128RegisterClass; 15531 } 15532 15533 return Res; 15534} 15535