X86ISelLowering.cpp revision f5b9d6cc82d46dbac7fc469e316a7f1cadd8277f
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalAlias.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Function.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/LLVMContext.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/PseudoSourceValue.h" 37#include "llvm/MC/MCAsmInfo.h" 38#include "llvm/MC/MCContext.h" 39#include "llvm/MC/MCExpr.h" 40#include "llvm/MC/MCSymbol.h" 41#include "llvm/ADT/BitVector.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/Support/CommandLine.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/Dwarf.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/raw_ostream.h" 52using namespace llvm; 53using namespace dwarf; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57static cl::opt<bool> 58DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 59 60// Disable16Bit - 16-bit operations typically have a larger encoding than 61// corresponding 32-bit instructions, and 16-bit code is slow on some 62// processors. This is an experimental flag to disable 16-bit operations 63// (which forces them to be Legalized to 32-bit operations). 64static cl::opt<bool> 65Disable16Bit("disable-16bit", cl::Hidden, 66 cl::desc("Disable use of 16-bit instructions")); 67 68// Forward declarations. 69static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 70 SDValue V2); 71 72static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 73 switch (TM.getSubtarget<X86Subtarget>().TargetType) { 74 default: llvm_unreachable("unknown subtarget type"); 75 case X86Subtarget::isDarwin: 76 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 77 return new X8664_MachoTargetObjectFile(); 78 return new TargetLoweringObjectFileMachO(); 79 case X86Subtarget::isELF: 80 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 81 return new X8664_ELFTargetObjectFile(TM); 82 return new X8632_ELFTargetObjectFile(TM); 83 case X86Subtarget::isMingw: 84 case X86Subtarget::isCygwin: 85 case X86Subtarget::isWindows: 86 return new TargetLoweringObjectFileCOFF(); 87 } 88} 89 90X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 91 : TargetLowering(TM, createTLOF(TM)) { 92 Subtarget = &TM.getSubtarget<X86Subtarget>(); 93 X86ScalarSSEf64 = Subtarget->hasSSE2(); 94 X86ScalarSSEf32 = Subtarget->hasSSE1(); 95 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 96 97 RegInfo = TM.getRegisterInfo(); 98 TD = getTargetData(); 99 100 // Set up the TargetLowering object. 101 102 // X86 is weird, it always uses i8 for shift amounts and setcc results. 103 setShiftAmountType(MVT::i8); 104 setBooleanContents(ZeroOrOneBooleanContent); 105 setSchedulingPreference(SchedulingForRegPressure); 106 setStackPointerRegisterToSaveRestore(X86StackPtr); 107 108 if (Subtarget->isTargetDarwin()) { 109 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 110 setUseUnderscoreSetJmp(false); 111 setUseUnderscoreLongJmp(false); 112 } else if (Subtarget->isTargetMingw()) { 113 // MS runtime is weird: it exports _setjmp, but longjmp! 114 setUseUnderscoreSetJmp(true); 115 setUseUnderscoreLongJmp(false); 116 } else { 117 setUseUnderscoreSetJmp(true); 118 setUseUnderscoreLongJmp(true); 119 } 120 121 // Set up the register classes. 122 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 123 if (!Disable16Bit) 124 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 125 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 126 if (Subtarget->is64Bit()) 127 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 128 129 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 130 131 // We don't accept any truncstore of integer registers. 132 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 133 if (!Disable16Bit) 134 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 135 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 136 if (!Disable16Bit) 137 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 138 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 139 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 140 141 // SETOEQ and SETUNE require checking two conditions. 142 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 143 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 144 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 145 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 146 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 147 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 148 149 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 150 // operation. 151 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 152 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 153 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 154 155 if (Subtarget->is64Bit()) { 156 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 157 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 158 } else if (!UseSoftFloat) { 159 if (X86ScalarSSEf64) { 160 // We have an impenetrably clever algorithm for ui64->double only. 161 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 162 } 163 // We have an algorithm for SSE2, and we turn this into a 64-bit 164 // FILD for other targets. 165 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 166 } 167 168 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 169 // this operation. 170 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 171 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 172 173 if (!UseSoftFloat) { 174 // SSE has no i16 to fp conversion, only i32 175 if (X86ScalarSSEf32) { 176 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 177 // f32 and f64 cases are Legal, f80 case is not 178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 179 } else { 180 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 181 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 182 } 183 } else { 184 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 185 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 186 } 187 188 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 189 // are Legal, f80 is custom lowered. 190 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 191 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 192 193 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 194 // this operation. 195 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 196 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 197 198 if (X86ScalarSSEf32) { 199 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 200 // f32 and f64 cases are Legal, f80 case is not 201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 202 } else { 203 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 204 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 205 } 206 207 // Handle FP_TO_UINT by promoting the destination to a larger signed 208 // conversion. 209 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 210 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 211 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 212 213 if (Subtarget->is64Bit()) { 214 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 215 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 216 } else if (!UseSoftFloat) { 217 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 218 // Expand FP_TO_UINT into a select. 219 // FIXME: We would like to use a Custom expander here eventually to do 220 // the optimal thing for SSE vs. the default expansion in the legalizer. 221 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 222 else 223 // With SSE3 we can use fisttpll to convert to a signed i64; without 224 // SSE, we're stuck with a fistpll. 225 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 226 } 227 228 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 229 if (!X86ScalarSSEf64) { 230 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 231 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 232 } 233 234 // Scalar integer divide and remainder are lowered to use operations that 235 // produce two results, to match the available instructions. This exposes 236 // the two-result form to trivial CSE, which is able to combine x/y and x%y 237 // into a single instruction. 238 // 239 // Scalar integer multiply-high is also lowered to use two-result 240 // operations, to match the available instructions. However, plain multiply 241 // (low) operations are left as Legal, as there are single-result 242 // instructions for this in x86. Using the two-result multiply instructions 243 // when both high and low results are needed must be arranged by dagcombine. 244 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 245 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 246 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 247 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 248 setOperationAction(ISD::SREM , MVT::i8 , Expand); 249 setOperationAction(ISD::UREM , MVT::i8 , Expand); 250 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 251 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 252 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 253 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 254 setOperationAction(ISD::SREM , MVT::i16 , Expand); 255 setOperationAction(ISD::UREM , MVT::i16 , Expand); 256 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 257 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 258 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 259 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 260 setOperationAction(ISD::SREM , MVT::i32 , Expand); 261 setOperationAction(ISD::UREM , MVT::i32 , Expand); 262 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 263 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 264 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 265 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 266 setOperationAction(ISD::SREM , MVT::i64 , Expand); 267 setOperationAction(ISD::UREM , MVT::i64 , Expand); 268 269 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 270 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 271 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 272 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 273 if (Subtarget->is64Bit()) 274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 276 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 277 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 278 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 279 setOperationAction(ISD::FREM , MVT::f32 , Expand); 280 setOperationAction(ISD::FREM , MVT::f64 , Expand); 281 setOperationAction(ISD::FREM , MVT::f80 , Expand); 282 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 283 284 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 285 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 286 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 287 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 288 if (Disable16Bit) { 289 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 290 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 291 } else { 292 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 293 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 294 } 295 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 296 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 297 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 298 if (Subtarget->is64Bit()) { 299 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 300 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 301 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 302 } 303 304 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 305 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 306 307 // These should be promoted to a larger select which is supported. 308 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 309 // X86 wants to expand cmov itself. 310 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 311 if (Disable16Bit) 312 setOperationAction(ISD::SELECT , MVT::i16 , Expand); 313 else 314 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 315 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 316 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 317 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 318 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 319 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 320 if (Disable16Bit) 321 setOperationAction(ISD::SETCC , MVT::i16 , Expand); 322 else 323 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 324 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 325 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 326 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 327 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 328 if (Subtarget->is64Bit()) { 329 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 330 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 331 } 332 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 333 334 // Darwin ABI issue. 335 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 336 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 337 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 338 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 339 if (Subtarget->is64Bit()) 340 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 341 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 342 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 343 if (Subtarget->is64Bit()) { 344 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 345 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 346 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 347 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 348 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 349 } 350 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 351 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 352 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 353 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 354 if (Subtarget->is64Bit()) { 355 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 356 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 357 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 358 } 359 360 if (Subtarget->hasSSE1()) 361 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 362 363 if (!Subtarget->hasSSE2()) 364 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 365 366 // Expand certain atomics 367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 369 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 370 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 371 372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 376 377 if (!Subtarget->is64Bit()) { 378 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 379 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 380 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 381 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 382 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 383 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 384 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 385 } 386 387 // FIXME - use subtarget debug flags 388 if (!Subtarget->isTargetDarwin() && 389 !Subtarget->isTargetELF() && 390 !Subtarget->isTargetCygMing()) { 391 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 392 } 393 394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 395 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 396 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 397 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 398 if (Subtarget->is64Bit()) { 399 setExceptionPointerRegister(X86::RAX); 400 setExceptionSelectorRegister(X86::RDX); 401 } else { 402 setExceptionPointerRegister(X86::EAX); 403 setExceptionSelectorRegister(X86::EDX); 404 } 405 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 406 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 407 408 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 409 410 setOperationAction(ISD::TRAP, MVT::Other, Legal); 411 412 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 413 setOperationAction(ISD::VASTART , MVT::Other, Custom); 414 setOperationAction(ISD::VAEND , MVT::Other, Expand); 415 if (Subtarget->is64Bit()) { 416 setOperationAction(ISD::VAARG , MVT::Other, Custom); 417 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 418 } else { 419 setOperationAction(ISD::VAARG , MVT::Other, Expand); 420 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 421 } 422 423 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 424 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 425 if (Subtarget->is64Bit()) 426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 427 if (Subtarget->isTargetCygMing()) 428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 429 else 430 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 431 432 if (!UseSoftFloat && X86ScalarSSEf64) { 433 // f32 and f64 use SSE. 434 // Set up the FP register classes. 435 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 436 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 437 438 // Use ANDPD to simulate FABS. 439 setOperationAction(ISD::FABS , MVT::f64, Custom); 440 setOperationAction(ISD::FABS , MVT::f32, Custom); 441 442 // Use XORP to simulate FNEG. 443 setOperationAction(ISD::FNEG , MVT::f64, Custom); 444 setOperationAction(ISD::FNEG , MVT::f32, Custom); 445 446 // Use ANDPD and ORPD to simulate FCOPYSIGN. 447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 449 450 // We don't support sin/cos/fmod 451 setOperationAction(ISD::FSIN , MVT::f64, Expand); 452 setOperationAction(ISD::FCOS , MVT::f64, Expand); 453 setOperationAction(ISD::FSIN , MVT::f32, Expand); 454 setOperationAction(ISD::FCOS , MVT::f32, Expand); 455 456 // Expand FP immediates into loads from the stack, except for the special 457 // cases we handle. 458 addLegalFPImmediate(APFloat(+0.0)); // xorpd 459 addLegalFPImmediate(APFloat(+0.0f)); // xorps 460 } else if (!UseSoftFloat && X86ScalarSSEf32) { 461 // Use SSE for f32, x87 for f64. 462 // Set up the FP register classes. 463 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 465 466 // Use ANDPS to simulate FABS. 467 setOperationAction(ISD::FABS , MVT::f32, Custom); 468 469 // Use XORP to simulate FNEG. 470 setOperationAction(ISD::FNEG , MVT::f32, Custom); 471 472 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 473 474 // Use ANDPS and ORPS to simulate FCOPYSIGN. 475 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 476 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 477 478 // We don't support sin/cos/fmod 479 setOperationAction(ISD::FSIN , MVT::f32, Expand); 480 setOperationAction(ISD::FCOS , MVT::f32, Expand); 481 482 // Special cases we handle for FP constants. 483 addLegalFPImmediate(APFloat(+0.0f)); // xorps 484 addLegalFPImmediate(APFloat(+0.0)); // FLD0 485 addLegalFPImmediate(APFloat(+1.0)); // FLD1 486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 488 489 if (!UnsafeFPMath) { 490 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 491 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 492 } 493 } else if (!UseSoftFloat) { 494 // f32 and f64 in x87. 495 // Set up the FP register classes. 496 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 497 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 498 499 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 500 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 501 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 502 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 503 504 if (!UnsafeFPMath) { 505 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 506 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 507 } 508 addLegalFPImmediate(APFloat(+0.0)); // FLD0 509 addLegalFPImmediate(APFloat(+1.0)); // FLD1 510 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 511 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 512 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 513 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 514 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 515 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 516 } 517 518 // Long double always uses X87. 519 if (!UseSoftFloat) { 520 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 521 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 522 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 523 { 524 bool ignored; 525 APFloat TmpFlt(+0.0); 526 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 527 &ignored); 528 addLegalFPImmediate(TmpFlt); // FLD0 529 TmpFlt.changeSign(); 530 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 531 APFloat TmpFlt2(+1.0); 532 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 533 &ignored); 534 addLegalFPImmediate(TmpFlt2); // FLD1 535 TmpFlt2.changeSign(); 536 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 537 } 538 539 if (!UnsafeFPMath) { 540 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 541 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 542 } 543 } 544 545 // Always use a library call for pow. 546 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 547 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 548 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 549 550 setOperationAction(ISD::FLOG, MVT::f80, Expand); 551 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 552 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 553 setOperationAction(ISD::FEXP, MVT::f80, Expand); 554 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 555 556 // First set operation action for all vector types to either promote 557 // (for widening) or expand (for scalarization). Then we will selectively 558 // turn on ones that can be effectively codegen'd. 559 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 560 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 561 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 576 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 577 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 600 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 604 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 605 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 606 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 607 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 608 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 609 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 610 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 611 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 612 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 613 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 614 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 615 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 616 setTruncStoreAction((MVT::SimpleValueType)VT, 617 (MVT::SimpleValueType)InnerVT, Expand); 618 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 619 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 620 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 621 } 622 623 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 624 // with -msoft-float, disable use of MMX as well. 625 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 626 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 627 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 628 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 629 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 630 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 631 632 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 633 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 634 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 635 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 636 637 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 638 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 639 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 640 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 641 642 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 643 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 644 645 setOperationAction(ISD::AND, MVT::v8i8, Promote); 646 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 647 setOperationAction(ISD::AND, MVT::v4i16, Promote); 648 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 649 setOperationAction(ISD::AND, MVT::v2i32, Promote); 650 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 651 setOperationAction(ISD::AND, MVT::v1i64, Legal); 652 653 setOperationAction(ISD::OR, MVT::v8i8, Promote); 654 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 655 setOperationAction(ISD::OR, MVT::v4i16, Promote); 656 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 657 setOperationAction(ISD::OR, MVT::v2i32, Promote); 658 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 659 setOperationAction(ISD::OR, MVT::v1i64, Legal); 660 661 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 662 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 663 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 664 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 665 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 666 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 667 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 668 669 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 670 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 671 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 672 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 673 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 674 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 675 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 676 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 677 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 678 679 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 680 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 681 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 683 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 684 685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 686 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 689 690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 692 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 693 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 694 695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 696 697 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 698 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 699 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 700 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 701 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 702 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 703 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 704 } 705 706 if (!UseSoftFloat && Subtarget->hasSSE1()) { 707 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 708 709 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 710 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 711 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 712 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 713 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 714 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 715 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 716 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 717 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 718 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 719 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 720 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 721 } 722 723 if (!UseSoftFloat && Subtarget->hasSSE2()) { 724 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 725 726 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 727 // registers cannot be used even for integer operations. 728 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 729 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 730 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 731 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 732 733 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 734 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 735 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 736 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 737 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 738 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 739 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 740 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 741 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 742 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 743 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 744 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 745 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 746 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 747 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 748 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 749 750 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 751 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 752 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 753 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 754 755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 756 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 758 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 759 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 760 761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 764 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 765 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 766 767 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 768 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 769 EVT VT = (MVT::SimpleValueType)i; 770 // Do not attempt to custom lower non-power-of-2 vectors 771 if (!isPowerOf2_32(VT.getVectorNumElements())) 772 continue; 773 // Do not attempt to custom lower non-128-bit vectors 774 if (!VT.is128BitVector()) 775 continue; 776 setOperationAction(ISD::BUILD_VECTOR, 777 VT.getSimpleVT().SimpleTy, Custom); 778 setOperationAction(ISD::VECTOR_SHUFFLE, 779 VT.getSimpleVT().SimpleTy, Custom); 780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 781 VT.getSimpleVT().SimpleTy, Custom); 782 } 783 784 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 785 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 786 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 788 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 790 791 if (Subtarget->is64Bit()) { 792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 793 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 794 } 795 796 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 797 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 798 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 799 EVT VT = SVT; 800 801 // Do not attempt to promote non-128-bit vectors 802 if (!VT.is128BitVector()) { 803 continue; 804 } 805 setOperationAction(ISD::AND, SVT, Promote); 806 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 807 setOperationAction(ISD::OR, SVT, Promote); 808 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 809 setOperationAction(ISD::XOR, SVT, Promote); 810 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 811 setOperationAction(ISD::LOAD, SVT, Promote); 812 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 813 setOperationAction(ISD::SELECT, SVT, Promote); 814 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 815 } 816 817 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 818 819 // Custom lower v2i64 and v2f64 selects. 820 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 821 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 822 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 823 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 824 825 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 826 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 827 if (!DisableMMX && Subtarget->hasMMX()) { 828 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 829 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 830 } 831 } 832 833 if (Subtarget->hasSSE41()) { 834 // FIXME: Do we need to handle scalar-to-vector here? 835 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 836 837 // i8 and i16 vectors are custom , because the source register and source 838 // source memory operand types are not the same width. f32 vectors are 839 // custom since the immediate controlling the insert encodes additional 840 // information. 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 845 846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 848 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 849 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 850 851 if (Subtarget->is64Bit()) { 852 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 854 } 855 } 856 857 if (Subtarget->hasSSE42()) { 858 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 859 } 860 861 if (!UseSoftFloat && Subtarget->hasAVX()) { 862 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 863 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 864 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 865 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 866 867 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 868 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 869 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 870 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 871 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 872 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 873 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 874 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 875 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 876 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 877 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 878 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 879 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 880 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 881 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 882 883 // Operations to consider commented out -v16i16 v32i8 884 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 885 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 886 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 887 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 888 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 889 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 890 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 891 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 892 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 893 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 894 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 895 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 896 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 897 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 898 899 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 900 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 901 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 902 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 903 904 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 905 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 906 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 908 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 909 910 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 911 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 912 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 913 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 914 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 916 917#if 0 918 // Not sure we want to do this since there are no 256-bit integer 919 // operations in AVX 920 921 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 922 // This includes 256-bit vectors 923 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 924 EVT VT = (MVT::SimpleValueType)i; 925 926 // Do not attempt to custom lower non-power-of-2 vectors 927 if (!isPowerOf2_32(VT.getVectorNumElements())) 928 continue; 929 930 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 931 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 932 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 933 } 934 935 if (Subtarget->is64Bit()) { 936 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 938 } 939#endif 940 941#if 0 942 // Not sure we want to do this since there are no 256-bit integer 943 // operations in AVX 944 945 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 946 // Including 256-bit vectors 947 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 948 EVT VT = (MVT::SimpleValueType)i; 949 950 if (!VT.is256BitVector()) { 951 continue; 952 } 953 setOperationAction(ISD::AND, VT, Promote); 954 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 955 setOperationAction(ISD::OR, VT, Promote); 956 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 957 setOperationAction(ISD::XOR, VT, Promote); 958 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 959 setOperationAction(ISD::LOAD, VT, Promote); 960 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 961 setOperationAction(ISD::SELECT, VT, Promote); 962 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 963 } 964 965 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 966#endif 967 } 968 969 // We want to custom lower some of our intrinsics. 970 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 971 972 // Add/Sub/Mul with overflow operations are custom lowered. 973 setOperationAction(ISD::SADDO, MVT::i32, Custom); 974 setOperationAction(ISD::SADDO, MVT::i64, Custom); 975 setOperationAction(ISD::UADDO, MVT::i32, Custom); 976 setOperationAction(ISD::UADDO, MVT::i64, Custom); 977 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 978 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 979 setOperationAction(ISD::USUBO, MVT::i32, Custom); 980 setOperationAction(ISD::USUBO, MVT::i64, Custom); 981 setOperationAction(ISD::SMULO, MVT::i32, Custom); 982 setOperationAction(ISD::SMULO, MVT::i64, Custom); 983 984 if (!Subtarget->is64Bit()) { 985 // These libcalls are not available in 32-bit. 986 setLibcallName(RTLIB::SHL_I128, 0); 987 setLibcallName(RTLIB::SRL_I128, 0); 988 setLibcallName(RTLIB::SRA_I128, 0); 989 } 990 991 // We have target-specific dag combine patterns for the following nodes: 992 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 993 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 994 setTargetDAGCombine(ISD::BUILD_VECTOR); 995 setTargetDAGCombine(ISD::SELECT); 996 setTargetDAGCombine(ISD::SHL); 997 setTargetDAGCombine(ISD::SRA); 998 setTargetDAGCombine(ISD::SRL); 999 setTargetDAGCombine(ISD::OR); 1000 setTargetDAGCombine(ISD::STORE); 1001 setTargetDAGCombine(ISD::MEMBARRIER); 1002 setTargetDAGCombine(ISD::ZERO_EXTEND); 1003 if (Subtarget->is64Bit()) 1004 setTargetDAGCombine(ISD::MUL); 1005 1006 computeRegisterProperties(); 1007 1008 // FIXME: These should be based on subtarget info. Plus, the values should 1009 // be smaller when we are in optimizing for size mode. 1010 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1011 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 1012 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 1013 setPrefLoopAlignment(16); 1014 benefitFromCodePlacementOpt = true; 1015} 1016 1017 1018MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1019 return MVT::i8; 1020} 1021 1022 1023/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1024/// the desired ByVal argument alignment. 1025static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1026 if (MaxAlign == 16) 1027 return; 1028 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1029 if (VTy->getBitWidth() == 128) 1030 MaxAlign = 16; 1031 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1032 unsigned EltAlign = 0; 1033 getMaxByValAlign(ATy->getElementType(), EltAlign); 1034 if (EltAlign > MaxAlign) 1035 MaxAlign = EltAlign; 1036 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1037 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1038 unsigned EltAlign = 0; 1039 getMaxByValAlign(STy->getElementType(i), EltAlign); 1040 if (EltAlign > MaxAlign) 1041 MaxAlign = EltAlign; 1042 if (MaxAlign == 16) 1043 break; 1044 } 1045 } 1046 return; 1047} 1048 1049/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1050/// function arguments in the caller parameter area. For X86, aggregates 1051/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1052/// are at 4-byte boundaries. 1053unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1054 if (Subtarget->is64Bit()) { 1055 // Max of 8 and alignment of type. 1056 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1057 if (TyAlign > 8) 1058 return TyAlign; 1059 return 8; 1060 } 1061 1062 unsigned Align = 4; 1063 if (Subtarget->hasSSE1()) 1064 getMaxByValAlign(Ty, Align); 1065 return Align; 1066} 1067 1068/// getOptimalMemOpType - Returns the target specific optimal type for load 1069/// and store operations as a result of memset, memcpy, and memmove 1070/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 1071/// determining it. 1072EVT 1073X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 1074 bool isSrcConst, bool isSrcStr, 1075 SelectionDAG &DAG) const { 1076 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1077 // linux. This is because the stack realignment code can't handle certain 1078 // cases like PR2962. This should be removed when PR2962 is fixed. 1079 const Function *F = DAG.getMachineFunction().getFunction(); 1080 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 1081 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) { 1082 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 1083 return MVT::v4i32; 1084 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 1085 return MVT::v4f32; 1086 } 1087 if (Subtarget->is64Bit() && Size >= 8) 1088 return MVT::i64; 1089 return MVT::i32; 1090} 1091 1092/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1093/// current function. The returned value is a member of the 1094/// MachineJumpTableInfo::JTEntryKind enum. 1095unsigned X86TargetLowering::getJumpTableEncoding() const { 1096 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1097 // symbol. 1098 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1099 Subtarget->isPICStyleGOT()) 1100 return MachineJumpTableInfo::EK_Custom32; 1101 1102 // Otherwise, use the normal jump table encoding heuristics. 1103 return TargetLowering::getJumpTableEncoding(); 1104} 1105 1106/// getPICBaseSymbol - Return the X86-32 PIC base. 1107MCSymbol * 1108X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF, 1109 MCContext &Ctx) const { 1110 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo(); 1111 return Ctx.GetOrCreateTemporarySymbol(Twine(MAI.getPrivateGlobalPrefix())+ 1112 Twine(MF->getFunctionNumber())+"$pb"); 1113} 1114 1115 1116const MCExpr * 1117X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1118 const MachineBasicBlock *MBB, 1119 unsigned uid,MCContext &Ctx) const{ 1120 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1121 Subtarget->isPICStyleGOT()); 1122 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1123 // entries. 1124 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1125 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1126} 1127 1128/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1129/// jumptable. 1130SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1131 SelectionDAG &DAG) const { 1132 if (!Subtarget->is64Bit()) 1133 // This doesn't have DebugLoc associated with it, but is not really the 1134 // same as a Register. 1135 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 1136 getPointerTy()); 1137 return Table; 1138} 1139 1140/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1141/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1142/// MCExpr. 1143const MCExpr *X86TargetLowering:: 1144getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1145 MCContext &Ctx) const { 1146 // X86-64 uses RIP relative addressing based on the jump table label. 1147 if (Subtarget->isPICStyleRIPRel()) 1148 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1149 1150 // Otherwise, the reference is relative to the PIC base. 1151 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx); 1152} 1153 1154/// getFunctionAlignment - Return the Log2 alignment of this function. 1155unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1156 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1157} 1158 1159//===----------------------------------------------------------------------===// 1160// Return Value Calling Convention Implementation 1161//===----------------------------------------------------------------------===// 1162 1163#include "X86GenCallingConv.inc" 1164 1165bool 1166X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1167 const SmallVectorImpl<EVT> &OutTys, 1168 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1169 SelectionDAG &DAG) { 1170 SmallVector<CCValAssign, 16> RVLocs; 1171 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1172 RVLocs, *DAG.getContext()); 1173 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86); 1174} 1175 1176SDValue 1177X86TargetLowering::LowerReturn(SDValue Chain, 1178 CallingConv::ID CallConv, bool isVarArg, 1179 const SmallVectorImpl<ISD::OutputArg> &Outs, 1180 DebugLoc dl, SelectionDAG &DAG) { 1181 1182 SmallVector<CCValAssign, 16> RVLocs; 1183 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1184 RVLocs, *DAG.getContext()); 1185 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1186 1187 // Add the regs to the liveout set for the function. 1188 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1189 for (unsigned i = 0; i != RVLocs.size(); ++i) 1190 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1191 MRI.addLiveOut(RVLocs[i].getLocReg()); 1192 1193 SDValue Flag; 1194 1195 SmallVector<SDValue, 6> RetOps; 1196 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1197 // Operand #1 = Bytes To Pop 1198 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16)); 1199 1200 // Copy the result values into the output registers. 1201 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1202 CCValAssign &VA = RVLocs[i]; 1203 assert(VA.isRegLoc() && "Can only return in registers!"); 1204 SDValue ValToCopy = Outs[i].Val; 1205 1206 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1207 // the RET instruction and handled by the FP Stackifier. 1208 if (VA.getLocReg() == X86::ST0 || 1209 VA.getLocReg() == X86::ST1) { 1210 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1211 // change the value to the FP stack register class. 1212 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1213 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1214 RetOps.push_back(ValToCopy); 1215 // Don't emit a copytoreg. 1216 continue; 1217 } 1218 1219 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1220 // which is returned in RAX / RDX. 1221 if (Subtarget->is64Bit()) { 1222 EVT ValVT = ValToCopy.getValueType(); 1223 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1224 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1225 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1226 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1227 } 1228 } 1229 1230 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1231 Flag = Chain.getValue(1); 1232 } 1233 1234 // The x86-64 ABI for returning structs by value requires that we copy 1235 // the sret argument into %rax for the return. We saved the argument into 1236 // a virtual register in the entry block, so now we copy the value out 1237 // and into %rax. 1238 if (Subtarget->is64Bit() && 1239 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1240 MachineFunction &MF = DAG.getMachineFunction(); 1241 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1242 unsigned Reg = FuncInfo->getSRetReturnReg(); 1243 if (!Reg) { 1244 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64)); 1245 FuncInfo->setSRetReturnReg(Reg); 1246 } 1247 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1248 1249 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1250 Flag = Chain.getValue(1); 1251 1252 // RAX now acts like a return value. 1253 MRI.addLiveOut(X86::RAX); 1254 } 1255 1256 RetOps[0] = Chain; // Update chain. 1257 1258 // Add the flag if we have it. 1259 if (Flag.getNode()) 1260 RetOps.push_back(Flag); 1261 1262 return DAG.getNode(X86ISD::RET_FLAG, dl, 1263 MVT::Other, &RetOps[0], RetOps.size()); 1264} 1265 1266/// LowerCallResult - Lower the result values of a call into the 1267/// appropriate copies out of appropriate physical registers. 1268/// 1269SDValue 1270X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1271 CallingConv::ID CallConv, bool isVarArg, 1272 const SmallVectorImpl<ISD::InputArg> &Ins, 1273 DebugLoc dl, SelectionDAG &DAG, 1274 SmallVectorImpl<SDValue> &InVals) { 1275 1276 // Assign locations to each value returned by this call. 1277 SmallVector<CCValAssign, 16> RVLocs; 1278 bool Is64Bit = Subtarget->is64Bit(); 1279 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1280 RVLocs, *DAG.getContext()); 1281 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1282 1283 // Copy all of the result registers out of their specified physreg. 1284 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1285 CCValAssign &VA = RVLocs[i]; 1286 EVT CopyVT = VA.getValVT(); 1287 1288 // If this is x86-64, and we disabled SSE, we can't return FP values 1289 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1290 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1291 llvm_report_error("SSE register return with SSE disabled"); 1292 } 1293 1294 // If this is a call to a function that returns an fp value on the floating 1295 // point stack, but where we prefer to use the value in xmm registers, copy 1296 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1297 if ((VA.getLocReg() == X86::ST0 || 1298 VA.getLocReg() == X86::ST1) && 1299 isScalarFPTypeInSSEReg(VA.getValVT())) { 1300 CopyVT = MVT::f80; 1301 } 1302 1303 SDValue Val; 1304 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1305 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1306 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1307 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1308 MVT::v2i64, InFlag).getValue(1); 1309 Val = Chain.getValue(0); 1310 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1311 Val, DAG.getConstant(0, MVT::i64)); 1312 } else { 1313 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1314 MVT::i64, InFlag).getValue(1); 1315 Val = Chain.getValue(0); 1316 } 1317 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1318 } else { 1319 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1320 CopyVT, InFlag).getValue(1); 1321 Val = Chain.getValue(0); 1322 } 1323 InFlag = Chain.getValue(2); 1324 1325 if (CopyVT != VA.getValVT()) { 1326 // Round the F80 the right size, which also moves to the appropriate xmm 1327 // register. 1328 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1329 // This truncation won't change the value. 1330 DAG.getIntPtrConstant(1)); 1331 } 1332 1333 InVals.push_back(Val); 1334 } 1335 1336 return Chain; 1337} 1338 1339 1340//===----------------------------------------------------------------------===// 1341// C & StdCall & Fast Calling Convention implementation 1342//===----------------------------------------------------------------------===// 1343// StdCall calling convention seems to be standard for many Windows' API 1344// routines and around. It differs from C calling convention just a little: 1345// callee should clean up the stack, not caller. Symbols should be also 1346// decorated in some fancy way :) It doesn't support any vector arguments. 1347// For info on fast calling convention see Fast Calling Convention (tail call) 1348// implementation LowerX86_32FastCCCallTo. 1349 1350/// CallIsStructReturn - Determines whether a call uses struct return 1351/// semantics. 1352static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1353 if (Outs.empty()) 1354 return false; 1355 1356 return Outs[0].Flags.isSRet(); 1357} 1358 1359/// ArgsAreStructReturn - Determines whether a function uses struct 1360/// return semantics. 1361static bool 1362ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1363 if (Ins.empty()) 1364 return false; 1365 1366 return Ins[0].Flags.isSRet(); 1367} 1368 1369/// IsCalleePop - Determines whether the callee is required to pop its 1370/// own arguments. Callee pop is necessary to support tail calls. 1371bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){ 1372 if (IsVarArg) 1373 return false; 1374 1375 switch (CallingConv) { 1376 default: 1377 return false; 1378 case CallingConv::X86_StdCall: 1379 return !Subtarget->is64Bit(); 1380 case CallingConv::X86_FastCall: 1381 return !Subtarget->is64Bit(); 1382 case CallingConv::Fast: 1383 return GuaranteedTailCallOpt; 1384 case CallingConv::GHC: 1385 return GuaranteedTailCallOpt; 1386 } 1387} 1388 1389/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1390/// given CallingConvention value. 1391CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1392 if (Subtarget->is64Bit()) { 1393 if (CC == CallingConv::GHC) 1394 return CC_X86_64_GHC; 1395 else if (Subtarget->isTargetWin64()) 1396 return CC_X86_Win64_C; 1397 else 1398 return CC_X86_64_C; 1399 } 1400 1401 if (CC == CallingConv::X86_FastCall) 1402 return CC_X86_32_FastCall; 1403 else if (CC == CallingConv::Fast) 1404 return CC_X86_32_FastCC; 1405 else if (CC == CallingConv::GHC) 1406 return CC_X86_32_GHC; 1407 else 1408 return CC_X86_32_C; 1409} 1410 1411/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1412/// by "Src" to address "Dst" with size and alignment information specified by 1413/// the specific parameter attribute. The copy will be passed as a byval 1414/// function parameter. 1415static SDValue 1416CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1417 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1418 DebugLoc dl) { 1419 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1420 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1421 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1422} 1423 1424/// IsTailCallConvention - Return true if the calling convention is one that 1425/// supports tail call optimization. 1426static bool IsTailCallConvention(CallingConv::ID CC) { 1427 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1428} 1429 1430/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1431/// a tailcall target by changing its ABI. 1432static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1433 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1434} 1435 1436SDValue 1437X86TargetLowering::LowerMemArgument(SDValue Chain, 1438 CallingConv::ID CallConv, 1439 const SmallVectorImpl<ISD::InputArg> &Ins, 1440 DebugLoc dl, SelectionDAG &DAG, 1441 const CCValAssign &VA, 1442 MachineFrameInfo *MFI, 1443 unsigned i) { 1444 // Create the nodes corresponding to a load from this parameter slot. 1445 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1446 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1447 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1448 EVT ValVT; 1449 1450 // If value is passed by pointer we have address passed instead of the value 1451 // itself. 1452 if (VA.getLocInfo() == CCValAssign::Indirect) 1453 ValVT = VA.getLocVT(); 1454 else 1455 ValVT = VA.getValVT(); 1456 1457 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1458 // changed with more analysis. 1459 // In case of tail call optimization mark all arguments mutable. Since they 1460 // could be overwritten by lowering of arguments in case of a tail call. 1461 if (Flags.isByVal()) { 1462 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1463 VA.getLocMemOffset(), isImmutable, false); 1464 return DAG.getFrameIndex(FI, getPointerTy()); 1465 } else { 1466 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1467 VA.getLocMemOffset(), isImmutable, false); 1468 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1469 return DAG.getLoad(ValVT, dl, Chain, FIN, 1470 PseudoSourceValue::getFixedStack(FI), 0, 1471 false, false, 0); 1472 } 1473} 1474 1475SDValue 1476X86TargetLowering::LowerFormalArguments(SDValue Chain, 1477 CallingConv::ID CallConv, 1478 bool isVarArg, 1479 const SmallVectorImpl<ISD::InputArg> &Ins, 1480 DebugLoc dl, 1481 SelectionDAG &DAG, 1482 SmallVectorImpl<SDValue> &InVals) { 1483 MachineFunction &MF = DAG.getMachineFunction(); 1484 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1485 1486 const Function* Fn = MF.getFunction(); 1487 if (Fn->hasExternalLinkage() && 1488 Subtarget->isTargetCygMing() && 1489 Fn->getName() == "main") 1490 FuncInfo->setForceFramePointer(true); 1491 1492 MachineFrameInfo *MFI = MF.getFrameInfo(); 1493 bool Is64Bit = Subtarget->is64Bit(); 1494 bool IsWin64 = Subtarget->isTargetWin64(); 1495 1496 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1497 "Var args not supported with calling convention fastcc or ghc"); 1498 1499 // Assign locations to all of the incoming arguments. 1500 SmallVector<CCValAssign, 16> ArgLocs; 1501 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1502 ArgLocs, *DAG.getContext()); 1503 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1504 1505 unsigned LastVal = ~0U; 1506 SDValue ArgValue; 1507 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1508 CCValAssign &VA = ArgLocs[i]; 1509 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1510 // places. 1511 assert(VA.getValNo() != LastVal && 1512 "Don't support value assigned to multiple locs yet"); 1513 LastVal = VA.getValNo(); 1514 1515 if (VA.isRegLoc()) { 1516 EVT RegVT = VA.getLocVT(); 1517 TargetRegisterClass *RC = NULL; 1518 if (RegVT == MVT::i32) 1519 RC = X86::GR32RegisterClass; 1520 else if (Is64Bit && RegVT == MVT::i64) 1521 RC = X86::GR64RegisterClass; 1522 else if (RegVT == MVT::f32) 1523 RC = X86::FR32RegisterClass; 1524 else if (RegVT == MVT::f64) 1525 RC = X86::FR64RegisterClass; 1526 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1527 RC = X86::VR128RegisterClass; 1528 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1529 RC = X86::VR64RegisterClass; 1530 else 1531 llvm_unreachable("Unknown argument type!"); 1532 1533 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1534 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1535 1536 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1537 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1538 // right size. 1539 if (VA.getLocInfo() == CCValAssign::SExt) 1540 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1541 DAG.getValueType(VA.getValVT())); 1542 else if (VA.getLocInfo() == CCValAssign::ZExt) 1543 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1544 DAG.getValueType(VA.getValVT())); 1545 else if (VA.getLocInfo() == CCValAssign::BCvt) 1546 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1547 1548 if (VA.isExtInLoc()) { 1549 // Handle MMX values passed in XMM regs. 1550 if (RegVT.isVector()) { 1551 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1552 ArgValue, DAG.getConstant(0, MVT::i64)); 1553 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1554 } else 1555 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1556 } 1557 } else { 1558 assert(VA.isMemLoc()); 1559 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1560 } 1561 1562 // If value is passed via pointer - do a load. 1563 if (VA.getLocInfo() == CCValAssign::Indirect) 1564 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0, 1565 false, false, 0); 1566 1567 InVals.push_back(ArgValue); 1568 } 1569 1570 // The x86-64 ABI for returning structs by value requires that we copy 1571 // the sret argument into %rax for the return. Save the argument into 1572 // a virtual register so that we can access it from the return points. 1573 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1574 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1575 unsigned Reg = FuncInfo->getSRetReturnReg(); 1576 if (!Reg) { 1577 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1578 FuncInfo->setSRetReturnReg(Reg); 1579 } 1580 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1581 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1582 } 1583 1584 unsigned StackSize = CCInfo.getNextStackOffset(); 1585 // Align stack specially for tail calls. 1586 if (FuncIsMadeTailCallSafe(CallConv)) 1587 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1588 1589 // If the function takes variable number of arguments, make a frame index for 1590 // the start of the first vararg value... for expansion of llvm.va_start. 1591 if (isVarArg) { 1592 if (Is64Bit || CallConv != CallingConv::X86_FastCall) { 1593 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false); 1594 } 1595 if (Is64Bit) { 1596 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1597 1598 // FIXME: We should really autogenerate these arrays 1599 static const unsigned GPR64ArgRegsWin64[] = { 1600 X86::RCX, X86::RDX, X86::R8, X86::R9 1601 }; 1602 static const unsigned XMMArgRegsWin64[] = { 1603 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1604 }; 1605 static const unsigned GPR64ArgRegs64Bit[] = { 1606 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1607 }; 1608 static const unsigned XMMArgRegs64Bit[] = { 1609 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1610 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1611 }; 1612 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1613 1614 if (IsWin64) { 1615 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1616 GPR64ArgRegs = GPR64ArgRegsWin64; 1617 XMMArgRegs = XMMArgRegsWin64; 1618 } else { 1619 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1620 GPR64ArgRegs = GPR64ArgRegs64Bit; 1621 XMMArgRegs = XMMArgRegs64Bit; 1622 } 1623 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1624 TotalNumIntRegs); 1625 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1626 TotalNumXMMRegs); 1627 1628 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1629 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1630 "SSE register cannot be used when SSE is disabled!"); 1631 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1632 "SSE register cannot be used when SSE is disabled!"); 1633 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1634 // Kernel mode asks for SSE to be disabled, so don't push them 1635 // on the stack. 1636 TotalNumXMMRegs = 0; 1637 1638 // For X86-64, if there are vararg parameters that are passed via 1639 // registers, then we must store them to their spots on the stack so they 1640 // may be loaded by deferencing the result of va_next. 1641 VarArgsGPOffset = NumIntRegs * 8; 1642 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1643 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1644 TotalNumXMMRegs * 16, 16, 1645 false); 1646 1647 // Store the integer parameter registers. 1648 SmallVector<SDValue, 8> MemOps; 1649 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1650 unsigned Offset = VarArgsGPOffset; 1651 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1652 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1653 DAG.getIntPtrConstant(Offset)); 1654 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1655 X86::GR64RegisterClass); 1656 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1657 SDValue Store = 1658 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1659 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 1660 Offset, false, false, 0); 1661 MemOps.push_back(Store); 1662 Offset += 8; 1663 } 1664 1665 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1666 // Now store the XMM (fp + vector) parameter registers. 1667 SmallVector<SDValue, 11> SaveXMMOps; 1668 SaveXMMOps.push_back(Chain); 1669 1670 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1671 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1672 SaveXMMOps.push_back(ALVal); 1673 1674 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex)); 1675 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset)); 1676 1677 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1678 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1679 X86::VR128RegisterClass); 1680 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1681 SaveXMMOps.push_back(Val); 1682 } 1683 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1684 MVT::Other, 1685 &SaveXMMOps[0], SaveXMMOps.size())); 1686 } 1687 1688 if (!MemOps.empty()) 1689 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1690 &MemOps[0], MemOps.size()); 1691 } 1692 } 1693 1694 // Some CCs need callee pop. 1695 if (IsCalleePop(isVarArg, CallConv)) { 1696 BytesToPopOnReturn = StackSize; // Callee pops everything. 1697 } else { 1698 BytesToPopOnReturn = 0; // Callee pops nothing. 1699 // If this is an sret function, the return should pop the hidden pointer. 1700 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1701 BytesToPopOnReturn = 4; 1702 } 1703 1704 if (!Is64Bit) { 1705 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1706 if (CallConv == CallingConv::X86_FastCall) 1707 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1708 } 1709 1710 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1711 1712 return Chain; 1713} 1714 1715SDValue 1716X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1717 SDValue StackPtr, SDValue Arg, 1718 DebugLoc dl, SelectionDAG &DAG, 1719 const CCValAssign &VA, 1720 ISD::ArgFlagsTy Flags) { 1721 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1722 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1723 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1724 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1725 if (Flags.isByVal()) { 1726 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1727 } 1728 return DAG.getStore(Chain, dl, Arg, PtrOff, 1729 PseudoSourceValue::getStack(), LocMemOffset, 1730 false, false, 0); 1731} 1732 1733/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1734/// optimization is performed and it is required. 1735SDValue 1736X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1737 SDValue &OutRetAddr, SDValue Chain, 1738 bool IsTailCall, bool Is64Bit, 1739 int FPDiff, DebugLoc dl) { 1740 // Adjust the Return address stack slot. 1741 EVT VT = getPointerTy(); 1742 OutRetAddr = getReturnAddressFrameIndex(DAG); 1743 1744 // Load the "old" Return address. 1745 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0); 1746 return SDValue(OutRetAddr.getNode(), 1); 1747} 1748 1749/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1750/// optimization is performed and it is required (FPDiff!=0). 1751static SDValue 1752EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1753 SDValue Chain, SDValue RetAddrFrIdx, 1754 bool Is64Bit, int FPDiff, DebugLoc dl) { 1755 // Store the return address to the appropriate stack slot. 1756 if (!FPDiff) return Chain; 1757 // Calculate the new stack slot for the return address. 1758 int SlotSize = Is64Bit ? 8 : 4; 1759 int NewReturnAddrFI = 1760 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false); 1761 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1762 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1763 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1764 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0, 1765 false, false, 0); 1766 return Chain; 1767} 1768 1769SDValue 1770X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1771 CallingConv::ID CallConv, bool isVarArg, 1772 bool &isTailCall, 1773 const SmallVectorImpl<ISD::OutputArg> &Outs, 1774 const SmallVectorImpl<ISD::InputArg> &Ins, 1775 DebugLoc dl, SelectionDAG &DAG, 1776 SmallVectorImpl<SDValue> &InVals) { 1777 MachineFunction &MF = DAG.getMachineFunction(); 1778 bool Is64Bit = Subtarget->is64Bit(); 1779 bool IsStructRet = CallIsStructReturn(Outs); 1780 bool IsSibcall = false; 1781 1782 if (isTailCall) { 1783 // Check if it's really possible to do a tail call. 1784 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1785 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1786 Outs, Ins, DAG); 1787 1788 // Sibcalls are automatically detected tailcalls which do not require 1789 // ABI changes. 1790 if (!GuaranteedTailCallOpt && isTailCall) 1791 IsSibcall = true; 1792 1793 if (isTailCall) 1794 ++NumTailCalls; 1795 } 1796 1797 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1798 "Var args not supported with calling convention fastcc or ghc"); 1799 1800 // Analyze operands of the call, assigning locations to each operand. 1801 SmallVector<CCValAssign, 16> ArgLocs; 1802 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1803 ArgLocs, *DAG.getContext()); 1804 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1805 1806 // Get a count of how many bytes are to be pushed on the stack. 1807 unsigned NumBytes = CCInfo.getNextStackOffset(); 1808 if (IsSibcall) 1809 // This is a sibcall. The memory operands are available in caller's 1810 // own caller's stack. 1811 NumBytes = 0; 1812 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 1813 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1814 1815 int FPDiff = 0; 1816 if (isTailCall && !IsSibcall) { 1817 // Lower arguments at fp - stackoffset + fpdiff. 1818 unsigned NumBytesCallerPushed = 1819 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1820 FPDiff = NumBytesCallerPushed - NumBytes; 1821 1822 // Set the delta of movement of the returnaddr stackslot. 1823 // But only set if delta is greater than previous delta. 1824 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1825 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1826 } 1827 1828 if (!IsSibcall) 1829 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1830 1831 SDValue RetAddrFrIdx; 1832 // Load return adress for tail calls. 1833 if (isTailCall && FPDiff) 1834 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1835 Is64Bit, FPDiff, dl); 1836 1837 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1838 SmallVector<SDValue, 8> MemOpChains; 1839 SDValue StackPtr; 1840 1841 // Walk the register/memloc assignments, inserting copies/loads. In the case 1842 // of tail call optimization arguments are handle later. 1843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1844 CCValAssign &VA = ArgLocs[i]; 1845 EVT RegVT = VA.getLocVT(); 1846 SDValue Arg = Outs[i].Val; 1847 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1848 bool isByVal = Flags.isByVal(); 1849 1850 // Promote the value if needed. 1851 switch (VA.getLocInfo()) { 1852 default: llvm_unreachable("Unknown loc info!"); 1853 case CCValAssign::Full: break; 1854 case CCValAssign::SExt: 1855 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1856 break; 1857 case CCValAssign::ZExt: 1858 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1859 break; 1860 case CCValAssign::AExt: 1861 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1862 // Special case: passing MMX values in XMM registers. 1863 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1864 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1865 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1866 } else 1867 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1868 break; 1869 case CCValAssign::BCvt: 1870 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1871 break; 1872 case CCValAssign::Indirect: { 1873 // Store the argument. 1874 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1875 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1876 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1877 PseudoSourceValue::getFixedStack(FI), 0, 1878 false, false, 0); 1879 Arg = SpillSlot; 1880 break; 1881 } 1882 } 1883 1884 if (VA.isRegLoc()) { 1885 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1886 } else if (!IsSibcall && (!isTailCall || isByVal)) { 1887 assert(VA.isMemLoc()); 1888 if (StackPtr.getNode() == 0) 1889 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1890 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1891 dl, DAG, VA, Flags)); 1892 } 1893 } 1894 1895 if (!MemOpChains.empty()) 1896 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1897 &MemOpChains[0], MemOpChains.size()); 1898 1899 // Build a sequence of copy-to-reg nodes chained together with token chain 1900 // and flag operands which copy the outgoing args into registers. 1901 SDValue InFlag; 1902 // Tail call byval lowering might overwrite argument registers so in case of 1903 // tail call optimization the copies to registers are lowered later. 1904 if (!isTailCall) 1905 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1906 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1907 RegsToPass[i].second, InFlag); 1908 InFlag = Chain.getValue(1); 1909 } 1910 1911 if (Subtarget->isPICStyleGOT()) { 1912 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1913 // GOT pointer. 1914 if (!isTailCall) { 1915 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1916 DAG.getNode(X86ISD::GlobalBaseReg, 1917 DebugLoc::getUnknownLoc(), 1918 getPointerTy()), 1919 InFlag); 1920 InFlag = Chain.getValue(1); 1921 } else { 1922 // If we are tail calling and generating PIC/GOT style code load the 1923 // address of the callee into ECX. The value in ecx is used as target of 1924 // the tail jump. This is done to circumvent the ebx/callee-saved problem 1925 // for tail calls on PIC/GOT architectures. Normally we would just put the 1926 // address of GOT into ebx and then call target@PLT. But for tail calls 1927 // ebx would be restored (since ebx is callee saved) before jumping to the 1928 // target@PLT. 1929 1930 // Note: The actual moving to ECX is done further down. 1931 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1932 if (G && !G->getGlobal()->hasHiddenVisibility() && 1933 !G->getGlobal()->hasProtectedVisibility()) 1934 Callee = LowerGlobalAddress(Callee, DAG); 1935 else if (isa<ExternalSymbolSDNode>(Callee)) 1936 Callee = LowerExternalSymbol(Callee, DAG); 1937 } 1938 } 1939 1940 if (Is64Bit && isVarArg) { 1941 // From AMD64 ABI document: 1942 // For calls that may call functions that use varargs or stdargs 1943 // (prototype-less calls or calls to functions containing ellipsis (...) in 1944 // the declaration) %al is used as hidden argument to specify the number 1945 // of SSE registers used. The contents of %al do not need to match exactly 1946 // the number of registers, but must be an ubound on the number of SSE 1947 // registers used and is in the range 0 - 8 inclusive. 1948 1949 // FIXME: Verify this on Win64 1950 // Count the number of XMM registers allocated. 1951 static const unsigned XMMArgRegs[] = { 1952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1954 }; 1955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1956 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1957 && "SSE registers cannot be used when SSE is disabled"); 1958 1959 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1960 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1961 InFlag = Chain.getValue(1); 1962 } 1963 1964 1965 // For tail calls lower the arguments to the 'real' stack slot. 1966 if (isTailCall) { 1967 // Force all the incoming stack arguments to be loaded from the stack 1968 // before any new outgoing arguments are stored to the stack, because the 1969 // outgoing stack slots may alias the incoming argument stack slots, and 1970 // the alias isn't otherwise explicit. This is slightly more conservative 1971 // than necessary, because it means that each store effectively depends 1972 // on every argument instead of just those arguments it would clobber. 1973 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 1974 1975 SmallVector<SDValue, 8> MemOpChains2; 1976 SDValue FIN; 1977 int FI = 0; 1978 // Do not flag preceeding copytoreg stuff together with the following stuff. 1979 InFlag = SDValue(); 1980 if (GuaranteedTailCallOpt) { 1981 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1982 CCValAssign &VA = ArgLocs[i]; 1983 if (VA.isRegLoc()) 1984 continue; 1985 assert(VA.isMemLoc()); 1986 SDValue Arg = Outs[i].Val; 1987 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1988 // Create frame index. 1989 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1990 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1991 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false); 1992 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1993 1994 if (Flags.isByVal()) { 1995 // Copy relative to framepointer. 1996 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1997 if (StackPtr.getNode() == 0) 1998 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 1999 getPointerTy()); 2000 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2001 2002 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2003 ArgChain, 2004 Flags, DAG, dl)); 2005 } else { 2006 // Store relative to framepointer. 2007 MemOpChains2.push_back( 2008 DAG.getStore(ArgChain, dl, Arg, FIN, 2009 PseudoSourceValue::getFixedStack(FI), 0, 2010 false, false, 0)); 2011 } 2012 } 2013 } 2014 2015 if (!MemOpChains2.empty()) 2016 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2017 &MemOpChains2[0], MemOpChains2.size()); 2018 2019 // Copy arguments to their registers. 2020 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2021 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2022 RegsToPass[i].second, InFlag); 2023 InFlag = Chain.getValue(1); 2024 } 2025 InFlag =SDValue(); 2026 2027 // Store the return address to the appropriate stack slot. 2028 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2029 FPDiff, dl); 2030 } 2031 2032 bool WasGlobalOrExternal = false; 2033 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2034 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2035 // In the 64-bit large code model, we have to make all calls 2036 // through a register, since the call instruction's 32-bit 2037 // pc-relative offset may not be large enough to hold the whole 2038 // address. 2039 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2040 WasGlobalOrExternal = true; 2041 // If the callee is a GlobalAddress node (quite common, every direct call 2042 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2043 // it. 2044 2045 // We should use extra load for direct calls to dllimported functions in 2046 // non-JIT mode. 2047 GlobalValue *GV = G->getGlobal(); 2048 if (!GV->hasDLLImportLinkage()) { 2049 unsigned char OpFlags = 0; 2050 2051 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2052 // external symbols most go through the PLT in PIC mode. If the symbol 2053 // has hidden or protected visibility, or if it is static or local, then 2054 // we don't need to use the PLT - we can directly call it. 2055 if (Subtarget->isTargetELF() && 2056 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2057 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2058 OpFlags = X86II::MO_PLT; 2059 } else if (Subtarget->isPICStyleStubAny() && 2060 (GV->isDeclaration() || GV->isWeakForLinker()) && 2061 Subtarget->getDarwinVers() < 9) { 2062 // PC-relative references to external symbols should go through $stub, 2063 // unless we're building with the leopard linker or later, which 2064 // automatically synthesizes these stubs. 2065 OpFlags = X86II::MO_DARWIN_STUB; 2066 } 2067 2068 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(), 2069 G->getOffset(), OpFlags); 2070 } 2071 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2072 WasGlobalOrExternal = true; 2073 unsigned char OpFlags = 0; 2074 2075 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 2076 // symbols should go through the PLT. 2077 if (Subtarget->isTargetELF() && 2078 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2079 OpFlags = X86II::MO_PLT; 2080 } else if (Subtarget->isPICStyleStubAny() && 2081 Subtarget->getDarwinVers() < 9) { 2082 // PC-relative references to external symbols should go through $stub, 2083 // unless we're building with the leopard linker or later, which 2084 // automatically synthesizes these stubs. 2085 OpFlags = X86II::MO_DARWIN_STUB; 2086 } 2087 2088 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2089 OpFlags); 2090 } 2091 2092 // Returns a chain & a flag for retval copy to use. 2093 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2094 SmallVector<SDValue, 8> Ops; 2095 2096 if (!IsSibcall && isTailCall) { 2097 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2098 DAG.getIntPtrConstant(0, true), InFlag); 2099 InFlag = Chain.getValue(1); 2100 } 2101 2102 Ops.push_back(Chain); 2103 Ops.push_back(Callee); 2104 2105 if (isTailCall) 2106 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2107 2108 // Add argument registers to the end of the list so that they are known live 2109 // into the call. 2110 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2111 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2112 RegsToPass[i].second.getValueType())); 2113 2114 // Add an implicit use GOT pointer in EBX. 2115 if (!isTailCall && Subtarget->isPICStyleGOT()) 2116 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2117 2118 // Add an implicit use of AL for x86 vararg functions. 2119 if (Is64Bit && isVarArg) 2120 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2121 2122 if (InFlag.getNode()) 2123 Ops.push_back(InFlag); 2124 2125 if (isTailCall) { 2126 // If this is the first return lowered for this function, add the regs 2127 // to the liveout set for the function. 2128 if (MF.getRegInfo().liveout_empty()) { 2129 SmallVector<CCValAssign, 16> RVLocs; 2130 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2131 *DAG.getContext()); 2132 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2133 for (unsigned i = 0; i != RVLocs.size(); ++i) 2134 if (RVLocs[i].isRegLoc()) 2135 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2136 } 2137 return DAG.getNode(X86ISD::TC_RETURN, dl, 2138 NodeTys, &Ops[0], Ops.size()); 2139 } 2140 2141 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2142 InFlag = Chain.getValue(1); 2143 2144 // Create the CALLSEQ_END node. 2145 unsigned NumBytesForCalleeToPush; 2146 if (IsCalleePop(isVarArg, CallConv)) 2147 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2148 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2149 // If this is a call to a struct-return function, the callee 2150 // pops the hidden struct pointer, so we have to push it back. 2151 // This is common for Darwin/X86, Linux & Mingw32 targets. 2152 NumBytesForCalleeToPush = 4; 2153 else 2154 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2155 2156 // Returns a flag for retval copy to use. 2157 if (!IsSibcall) { 2158 Chain = DAG.getCALLSEQ_END(Chain, 2159 DAG.getIntPtrConstant(NumBytes, true), 2160 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2161 true), 2162 InFlag); 2163 InFlag = Chain.getValue(1); 2164 } 2165 2166 // Handle result values, copying them out of physregs into vregs that we 2167 // return. 2168 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2169 Ins, dl, DAG, InVals); 2170} 2171 2172 2173//===----------------------------------------------------------------------===// 2174// Fast Calling Convention (tail call) implementation 2175//===----------------------------------------------------------------------===// 2176 2177// Like std call, callee cleans arguments, convention except that ECX is 2178// reserved for storing the tail called function address. Only 2 registers are 2179// free for argument passing (inreg). Tail call optimization is performed 2180// provided: 2181// * tailcallopt is enabled 2182// * caller/callee are fastcc 2183// On X86_64 architecture with GOT-style position independent code only local 2184// (within module) calls are supported at the moment. 2185// To keep the stack aligned according to platform abi the function 2186// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2187// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2188// If a tail called function callee has more arguments than the caller the 2189// caller needs to make sure that there is room to move the RETADDR to. This is 2190// achieved by reserving an area the size of the argument delta right after the 2191// original REtADDR, but before the saved framepointer or the spilled registers 2192// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2193// stack layout: 2194// arg1 2195// arg2 2196// RETADDR 2197// [ new RETADDR 2198// move area ] 2199// (possible EBP) 2200// ESI 2201// EDI 2202// local1 .. 2203 2204/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2205/// for a 16 byte align requirement. 2206unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2207 SelectionDAG& DAG) { 2208 MachineFunction &MF = DAG.getMachineFunction(); 2209 const TargetMachine &TM = MF.getTarget(); 2210 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2211 unsigned StackAlignment = TFI.getStackAlignment(); 2212 uint64_t AlignMask = StackAlignment - 1; 2213 int64_t Offset = StackSize; 2214 uint64_t SlotSize = TD->getPointerSize(); 2215 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2216 // Number smaller than 12 so just add the difference. 2217 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2218 } else { 2219 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2220 Offset = ((~AlignMask) & Offset) + StackAlignment + 2221 (StackAlignment-SlotSize); 2222 } 2223 return Offset; 2224} 2225 2226/// MatchingStackOffset - Return true if the given stack call argument is 2227/// already available in the same position (relatively) of the caller's 2228/// incoming argument stack. 2229static 2230bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2231 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2232 const X86InstrInfo *TII) { 2233 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2234 int FI = INT_MAX; 2235 if (Arg.getOpcode() == ISD::CopyFromReg) { 2236 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2237 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2238 return false; 2239 MachineInstr *Def = MRI->getVRegDef(VR); 2240 if (!Def) 2241 return false; 2242 if (!Flags.isByVal()) { 2243 if (!TII->isLoadFromStackSlot(Def, FI)) 2244 return false; 2245 } else { 2246 unsigned Opcode = Def->getOpcode(); 2247 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2248 Def->getOperand(1).isFI()) { 2249 FI = Def->getOperand(1).getIndex(); 2250 Bytes = Flags.getByValSize(); 2251 } else 2252 return false; 2253 } 2254 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2255 if (Flags.isByVal()) 2256 // ByVal argument is passed in as a pointer but it's now being 2257 // dereferenced. e.g. 2258 // define @foo(%struct.X* %A) { 2259 // tail call @bar(%struct.X* byval %A) 2260 // } 2261 return false; 2262 SDValue Ptr = Ld->getBasePtr(); 2263 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2264 if (!FINode) 2265 return false; 2266 FI = FINode->getIndex(); 2267 } else 2268 return false; 2269 2270 assert(FI != INT_MAX); 2271 if (!MFI->isFixedObjectIndex(FI)) 2272 return false; 2273 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2274} 2275 2276/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2277/// for tail call optimization. Targets which want to do tail call 2278/// optimization should implement this function. 2279bool 2280X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2281 CallingConv::ID CalleeCC, 2282 bool isVarArg, 2283 bool isCalleeStructRet, 2284 bool isCallerStructRet, 2285 const SmallVectorImpl<ISD::OutputArg> &Outs, 2286 const SmallVectorImpl<ISD::InputArg> &Ins, 2287 SelectionDAG& DAG) const { 2288 if (!IsTailCallConvention(CalleeCC) && 2289 CalleeCC != CallingConv::C) 2290 return false; 2291 2292 // If -tailcallopt is specified, make fastcc functions tail-callable. 2293 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2294 if (GuaranteedTailCallOpt) { 2295 if (IsTailCallConvention(CalleeCC) && 2296 CallerF->getCallingConv() == CalleeCC) 2297 return true; 2298 return false; 2299 } 2300 2301 // Look for obvious safe cases to perform tail call optimization that does not 2302 // requite ABI changes. This is what gcc calls sibcall. 2303 2304 // Do not sibcall optimize vararg calls for now. 2305 if (isVarArg) 2306 return false; 2307 2308 // Also avoid sibcall optimization if either caller or callee uses struct 2309 // return semantics. 2310 if (isCalleeStructRet || isCallerStructRet) 2311 return false; 2312 2313 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2314 // Therefore if it's not used by the call it is not safe to optimize this into 2315 // a sibcall. 2316 bool Unused = false; 2317 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2318 if (!Ins[i].Used) { 2319 Unused = true; 2320 break; 2321 } 2322 } 2323 if (Unused) { 2324 SmallVector<CCValAssign, 16> RVLocs; 2325 CCState CCInfo(CalleeCC, false, getTargetMachine(), 2326 RVLocs, *DAG.getContext()); 2327 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2328 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2329 CCValAssign &VA = RVLocs[i]; 2330 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2331 return false; 2332 } 2333 } 2334 2335 // If the callee takes no arguments then go on to check the results of the 2336 // call. 2337 if (!Outs.empty()) { 2338 // Check if stack adjustment is needed. For now, do not do this if any 2339 // argument is passed on the stack. 2340 SmallVector<CCValAssign, 16> ArgLocs; 2341 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2342 ArgLocs, *DAG.getContext()); 2343 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 2344 if (CCInfo.getNextStackOffset()) { 2345 MachineFunction &MF = DAG.getMachineFunction(); 2346 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2347 return false; 2348 if (Subtarget->isTargetWin64()) 2349 // Win64 ABI has additional complications. 2350 return false; 2351 2352 // Check if the arguments are already laid out in the right way as 2353 // the caller's fixed stack objects. 2354 MachineFrameInfo *MFI = MF.getFrameInfo(); 2355 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2356 const X86InstrInfo *TII = 2357 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2358 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2359 CCValAssign &VA = ArgLocs[i]; 2360 EVT RegVT = VA.getLocVT(); 2361 SDValue Arg = Outs[i].Val; 2362 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2363 if (VA.getLocInfo() == CCValAssign::Indirect) 2364 return false; 2365 if (!VA.isRegLoc()) { 2366 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2367 MFI, MRI, TII)) 2368 return false; 2369 } 2370 } 2371 } 2372 } 2373 2374 return true; 2375} 2376 2377FastISel * 2378X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo, 2379 DwarfWriter *dw, 2380 DenseMap<const Value *, unsigned> &vm, 2381 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm, 2382 DenseMap<const AllocaInst *, int> &am 2383#ifndef NDEBUG 2384 , SmallSet<Instruction*, 8> &cil 2385#endif 2386 ) { 2387 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2388#ifndef NDEBUG 2389 , cil 2390#endif 2391 ); 2392} 2393 2394 2395//===----------------------------------------------------------------------===// 2396// Other Lowering Hooks 2397//===----------------------------------------------------------------------===// 2398 2399 2400SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2401 MachineFunction &MF = DAG.getMachineFunction(); 2402 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2403 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2404 2405 if (ReturnAddrIndex == 0) { 2406 // Set up a frame object for the return address. 2407 uint64_t SlotSize = TD->getPointerSize(); 2408 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2409 false, false); 2410 FuncInfo->setRAIndex(ReturnAddrIndex); 2411 } 2412 2413 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2414} 2415 2416 2417bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2418 bool hasSymbolicDisplacement) { 2419 // Offset should fit into 32 bit immediate field. 2420 if (!isInt32(Offset)) 2421 return false; 2422 2423 // If we don't have a symbolic displacement - we don't have any extra 2424 // restrictions. 2425 if (!hasSymbolicDisplacement) 2426 return true; 2427 2428 // FIXME: Some tweaks might be needed for medium code model. 2429 if (M != CodeModel::Small && M != CodeModel::Kernel) 2430 return false; 2431 2432 // For small code model we assume that latest object is 16MB before end of 31 2433 // bits boundary. We may also accept pretty large negative constants knowing 2434 // that all objects are in the positive half of address space. 2435 if (M == CodeModel::Small && Offset < 16*1024*1024) 2436 return true; 2437 2438 // For kernel code model we know that all object resist in the negative half 2439 // of 32bits address space. We may not accept negative offsets, since they may 2440 // be just off and we may accept pretty large positive ones. 2441 if (M == CodeModel::Kernel && Offset > 0) 2442 return true; 2443 2444 return false; 2445} 2446 2447/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2448/// specific condition code, returning the condition code and the LHS/RHS of the 2449/// comparison to make. 2450static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2451 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2452 if (!isFP) { 2453 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2454 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2455 // X > -1 -> X == 0, jump !sign. 2456 RHS = DAG.getConstant(0, RHS.getValueType()); 2457 return X86::COND_NS; 2458 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2459 // X < 0 -> X == 0, jump on sign. 2460 return X86::COND_S; 2461 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2462 // X < 1 -> X <= 0 2463 RHS = DAG.getConstant(0, RHS.getValueType()); 2464 return X86::COND_LE; 2465 } 2466 } 2467 2468 switch (SetCCOpcode) { 2469 default: llvm_unreachable("Invalid integer condition!"); 2470 case ISD::SETEQ: return X86::COND_E; 2471 case ISD::SETGT: return X86::COND_G; 2472 case ISD::SETGE: return X86::COND_GE; 2473 case ISD::SETLT: return X86::COND_L; 2474 case ISD::SETLE: return X86::COND_LE; 2475 case ISD::SETNE: return X86::COND_NE; 2476 case ISD::SETULT: return X86::COND_B; 2477 case ISD::SETUGT: return X86::COND_A; 2478 case ISD::SETULE: return X86::COND_BE; 2479 case ISD::SETUGE: return X86::COND_AE; 2480 } 2481 } 2482 2483 // First determine if it is required or is profitable to flip the operands. 2484 2485 // If LHS is a foldable load, but RHS is not, flip the condition. 2486 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2487 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2488 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2489 std::swap(LHS, RHS); 2490 } 2491 2492 switch (SetCCOpcode) { 2493 default: break; 2494 case ISD::SETOLT: 2495 case ISD::SETOLE: 2496 case ISD::SETUGT: 2497 case ISD::SETUGE: 2498 std::swap(LHS, RHS); 2499 break; 2500 } 2501 2502 // On a floating point condition, the flags are set as follows: 2503 // ZF PF CF op 2504 // 0 | 0 | 0 | X > Y 2505 // 0 | 0 | 1 | X < Y 2506 // 1 | 0 | 0 | X == Y 2507 // 1 | 1 | 1 | unordered 2508 switch (SetCCOpcode) { 2509 default: llvm_unreachable("Condcode should be pre-legalized away"); 2510 case ISD::SETUEQ: 2511 case ISD::SETEQ: return X86::COND_E; 2512 case ISD::SETOLT: // flipped 2513 case ISD::SETOGT: 2514 case ISD::SETGT: return X86::COND_A; 2515 case ISD::SETOLE: // flipped 2516 case ISD::SETOGE: 2517 case ISD::SETGE: return X86::COND_AE; 2518 case ISD::SETUGT: // flipped 2519 case ISD::SETULT: 2520 case ISD::SETLT: return X86::COND_B; 2521 case ISD::SETUGE: // flipped 2522 case ISD::SETULE: 2523 case ISD::SETLE: return X86::COND_BE; 2524 case ISD::SETONE: 2525 case ISD::SETNE: return X86::COND_NE; 2526 case ISD::SETUO: return X86::COND_P; 2527 case ISD::SETO: return X86::COND_NP; 2528 case ISD::SETOEQ: 2529 case ISD::SETUNE: return X86::COND_INVALID; 2530 } 2531} 2532 2533/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2534/// code. Current x86 isa includes the following FP cmov instructions: 2535/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2536static bool hasFPCMov(unsigned X86CC) { 2537 switch (X86CC) { 2538 default: 2539 return false; 2540 case X86::COND_B: 2541 case X86::COND_BE: 2542 case X86::COND_E: 2543 case X86::COND_P: 2544 case X86::COND_A: 2545 case X86::COND_AE: 2546 case X86::COND_NE: 2547 case X86::COND_NP: 2548 return true; 2549 } 2550} 2551 2552/// isFPImmLegal - Returns true if the target can instruction select the 2553/// specified FP immediate natively. If false, the legalizer will 2554/// materialize the FP immediate as a load from a constant pool. 2555bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2556 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2557 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2558 return true; 2559 } 2560 return false; 2561} 2562 2563/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2564/// the specified range (L, H]. 2565static bool isUndefOrInRange(int Val, int Low, int Hi) { 2566 return (Val < 0) || (Val >= Low && Val < Hi); 2567} 2568 2569/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2570/// specified value. 2571static bool isUndefOrEqual(int Val, int CmpVal) { 2572 if (Val < 0 || Val == CmpVal) 2573 return true; 2574 return false; 2575} 2576 2577/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2578/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2579/// the second operand. 2580static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2581 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2582 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2583 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2584 return (Mask[0] < 2 && Mask[1] < 2); 2585 return false; 2586} 2587 2588bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2589 SmallVector<int, 8> M; 2590 N->getMask(M); 2591 return ::isPSHUFDMask(M, N->getValueType(0)); 2592} 2593 2594/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2595/// is suitable for input to PSHUFHW. 2596static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2597 if (VT != MVT::v8i16) 2598 return false; 2599 2600 // Lower quadword copied in order or undef. 2601 for (int i = 0; i != 4; ++i) 2602 if (Mask[i] >= 0 && Mask[i] != i) 2603 return false; 2604 2605 // Upper quadword shuffled. 2606 for (int i = 4; i != 8; ++i) 2607 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2608 return false; 2609 2610 return true; 2611} 2612 2613bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2614 SmallVector<int, 8> M; 2615 N->getMask(M); 2616 return ::isPSHUFHWMask(M, N->getValueType(0)); 2617} 2618 2619/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2620/// is suitable for input to PSHUFLW. 2621static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2622 if (VT != MVT::v8i16) 2623 return false; 2624 2625 // Upper quadword copied in order. 2626 for (int i = 4; i != 8; ++i) 2627 if (Mask[i] >= 0 && Mask[i] != i) 2628 return false; 2629 2630 // Lower quadword shuffled. 2631 for (int i = 0; i != 4; ++i) 2632 if (Mask[i] >= 4) 2633 return false; 2634 2635 return true; 2636} 2637 2638bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2639 SmallVector<int, 8> M; 2640 N->getMask(M); 2641 return ::isPSHUFLWMask(M, N->getValueType(0)); 2642} 2643 2644/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2645/// is suitable for input to PALIGNR. 2646static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2647 bool hasSSSE3) { 2648 int i, e = VT.getVectorNumElements(); 2649 2650 // Do not handle v2i64 / v2f64 shuffles with palignr. 2651 if (e < 4 || !hasSSSE3) 2652 return false; 2653 2654 for (i = 0; i != e; ++i) 2655 if (Mask[i] >= 0) 2656 break; 2657 2658 // All undef, not a palignr. 2659 if (i == e) 2660 return false; 2661 2662 // Determine if it's ok to perform a palignr with only the LHS, since we 2663 // don't have access to the actual shuffle elements to see if RHS is undef. 2664 bool Unary = Mask[i] < (int)e; 2665 bool NeedsUnary = false; 2666 2667 int s = Mask[i] - i; 2668 2669 // Check the rest of the elements to see if they are consecutive. 2670 for (++i; i != e; ++i) { 2671 int m = Mask[i]; 2672 if (m < 0) 2673 continue; 2674 2675 Unary = Unary && (m < (int)e); 2676 NeedsUnary = NeedsUnary || (m < s); 2677 2678 if (NeedsUnary && !Unary) 2679 return false; 2680 if (Unary && m != ((s+i) & (e-1))) 2681 return false; 2682 if (!Unary && m != (s+i)) 2683 return false; 2684 } 2685 return true; 2686} 2687 2688bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2689 SmallVector<int, 8> M; 2690 N->getMask(M); 2691 return ::isPALIGNRMask(M, N->getValueType(0), true); 2692} 2693 2694/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2695/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2696static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2697 int NumElems = VT.getVectorNumElements(); 2698 if (NumElems != 2 && NumElems != 4) 2699 return false; 2700 2701 int Half = NumElems / 2; 2702 for (int i = 0; i < Half; ++i) 2703 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2704 return false; 2705 for (int i = Half; i < NumElems; ++i) 2706 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2707 return false; 2708 2709 return true; 2710} 2711 2712bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2713 SmallVector<int, 8> M; 2714 N->getMask(M); 2715 return ::isSHUFPMask(M, N->getValueType(0)); 2716} 2717 2718/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2719/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2720/// half elements to come from vector 1 (which would equal the dest.) and 2721/// the upper half to come from vector 2. 2722static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2723 int NumElems = VT.getVectorNumElements(); 2724 2725 if (NumElems != 2 && NumElems != 4) 2726 return false; 2727 2728 int Half = NumElems / 2; 2729 for (int i = 0; i < Half; ++i) 2730 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2731 return false; 2732 for (int i = Half; i < NumElems; ++i) 2733 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2734 return false; 2735 return true; 2736} 2737 2738static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2739 SmallVector<int, 8> M; 2740 N->getMask(M); 2741 return isCommutedSHUFPMask(M, N->getValueType(0)); 2742} 2743 2744/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2745/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2746bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2747 if (N->getValueType(0).getVectorNumElements() != 4) 2748 return false; 2749 2750 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2751 return isUndefOrEqual(N->getMaskElt(0), 6) && 2752 isUndefOrEqual(N->getMaskElt(1), 7) && 2753 isUndefOrEqual(N->getMaskElt(2), 2) && 2754 isUndefOrEqual(N->getMaskElt(3), 3); 2755} 2756 2757/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2758/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2759/// <2, 3, 2, 3> 2760bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2761 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2762 2763 if (NumElems != 4) 2764 return false; 2765 2766 return isUndefOrEqual(N->getMaskElt(0), 2) && 2767 isUndefOrEqual(N->getMaskElt(1), 3) && 2768 isUndefOrEqual(N->getMaskElt(2), 2) && 2769 isUndefOrEqual(N->getMaskElt(3), 3); 2770} 2771 2772/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2773/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2774bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2775 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2776 2777 if (NumElems != 2 && NumElems != 4) 2778 return false; 2779 2780 for (unsigned i = 0; i < NumElems/2; ++i) 2781 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2782 return false; 2783 2784 for (unsigned i = NumElems/2; i < NumElems; ++i) 2785 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2786 return false; 2787 2788 return true; 2789} 2790 2791/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 2792/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 2793bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 2794 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2795 2796 if (NumElems != 2 && NumElems != 4) 2797 return false; 2798 2799 for (unsigned i = 0; i < NumElems/2; ++i) 2800 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2801 return false; 2802 2803 for (unsigned i = 0; i < NumElems/2; ++i) 2804 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2805 return false; 2806 2807 return true; 2808} 2809 2810/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2811/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2812static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2813 bool V2IsSplat = false) { 2814 int NumElts = VT.getVectorNumElements(); 2815 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2816 return false; 2817 2818 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2819 int BitI = Mask[i]; 2820 int BitI1 = Mask[i+1]; 2821 if (!isUndefOrEqual(BitI, j)) 2822 return false; 2823 if (V2IsSplat) { 2824 if (!isUndefOrEqual(BitI1, NumElts)) 2825 return false; 2826 } else { 2827 if (!isUndefOrEqual(BitI1, j + NumElts)) 2828 return false; 2829 } 2830 } 2831 return true; 2832} 2833 2834bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2835 SmallVector<int, 8> M; 2836 N->getMask(M); 2837 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2838} 2839 2840/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2841/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2842static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 2843 bool V2IsSplat = false) { 2844 int NumElts = VT.getVectorNumElements(); 2845 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2846 return false; 2847 2848 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2849 int BitI = Mask[i]; 2850 int BitI1 = Mask[i+1]; 2851 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2852 return false; 2853 if (V2IsSplat) { 2854 if (isUndefOrEqual(BitI1, NumElts)) 2855 return false; 2856 } else { 2857 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2858 return false; 2859 } 2860 } 2861 return true; 2862} 2863 2864bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2865 SmallVector<int, 8> M; 2866 N->getMask(M); 2867 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2868} 2869 2870/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2871/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2872/// <0, 0, 1, 1> 2873static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2874 int NumElems = VT.getVectorNumElements(); 2875 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2876 return false; 2877 2878 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2879 int BitI = Mask[i]; 2880 int BitI1 = Mask[i+1]; 2881 if (!isUndefOrEqual(BitI, j)) 2882 return false; 2883 if (!isUndefOrEqual(BitI1, j)) 2884 return false; 2885 } 2886 return true; 2887} 2888 2889bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 2890 SmallVector<int, 8> M; 2891 N->getMask(M); 2892 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 2893} 2894 2895/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2896/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2897/// <2, 2, 3, 3> 2898static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2899 int NumElems = VT.getVectorNumElements(); 2900 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2901 return false; 2902 2903 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2904 int BitI = Mask[i]; 2905 int BitI1 = Mask[i+1]; 2906 if (!isUndefOrEqual(BitI, j)) 2907 return false; 2908 if (!isUndefOrEqual(BitI1, j)) 2909 return false; 2910 } 2911 return true; 2912} 2913 2914bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 2915 SmallVector<int, 8> M; 2916 N->getMask(M); 2917 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 2918} 2919 2920/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2921/// specifies a shuffle of elements that is suitable for input to MOVSS, 2922/// MOVSD, and MOVD, i.e. setting the lowest element. 2923static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2924 if (VT.getVectorElementType().getSizeInBits() < 32) 2925 return false; 2926 2927 int NumElts = VT.getVectorNumElements(); 2928 2929 if (!isUndefOrEqual(Mask[0], NumElts)) 2930 return false; 2931 2932 for (int i = 1; i < NumElts; ++i) 2933 if (!isUndefOrEqual(Mask[i], i)) 2934 return false; 2935 2936 return true; 2937} 2938 2939bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 2940 SmallVector<int, 8> M; 2941 N->getMask(M); 2942 return ::isMOVLMask(M, N->getValueType(0)); 2943} 2944 2945/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2946/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2947/// element of vector 2 and the other elements to come from vector 1 in order. 2948static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2949 bool V2IsSplat = false, bool V2IsUndef = false) { 2950 int NumOps = VT.getVectorNumElements(); 2951 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2952 return false; 2953 2954 if (!isUndefOrEqual(Mask[0], 0)) 2955 return false; 2956 2957 for (int i = 1; i < NumOps; ++i) 2958 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 2959 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 2960 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 2961 return false; 2962 2963 return true; 2964} 2965 2966static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 2967 bool V2IsUndef = false) { 2968 SmallVector<int, 8> M; 2969 N->getMask(M); 2970 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 2971} 2972 2973/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2974/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2975bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 2976 if (N->getValueType(0).getVectorNumElements() != 4) 2977 return false; 2978 2979 // Expect 1, 1, 3, 3 2980 for (unsigned i = 0; i < 2; ++i) { 2981 int Elt = N->getMaskElt(i); 2982 if (Elt >= 0 && Elt != 1) 2983 return false; 2984 } 2985 2986 bool HasHi = false; 2987 for (unsigned i = 2; i < 4; ++i) { 2988 int Elt = N->getMaskElt(i); 2989 if (Elt >= 0 && Elt != 3) 2990 return false; 2991 if (Elt == 3) 2992 HasHi = true; 2993 } 2994 // Don't use movshdup if it can be done with a shufps. 2995 // FIXME: verify that matching u, u, 3, 3 is what we want. 2996 return HasHi; 2997} 2998 2999/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3000/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3001bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 3002 if (N->getValueType(0).getVectorNumElements() != 4) 3003 return false; 3004 3005 // Expect 0, 0, 2, 2 3006 for (unsigned i = 0; i < 2; ++i) 3007 if (N->getMaskElt(i) > 0) 3008 return false; 3009 3010 bool HasHi = false; 3011 for (unsigned i = 2; i < 4; ++i) { 3012 int Elt = N->getMaskElt(i); 3013 if (Elt >= 0 && Elt != 2) 3014 return false; 3015 if (Elt == 2) 3016 HasHi = true; 3017 } 3018 // Don't use movsldup if it can be done with a shufps. 3019 return HasHi; 3020} 3021 3022/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3023/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3024bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3025 int e = N->getValueType(0).getVectorNumElements() / 2; 3026 3027 for (int i = 0; i < e; ++i) 3028 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3029 return false; 3030 for (int i = 0; i < e; ++i) 3031 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3032 return false; 3033 return true; 3034} 3035 3036/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3037/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3038unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3040 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3041 3042 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3043 unsigned Mask = 0; 3044 for (int i = 0; i < NumOperands; ++i) { 3045 int Val = SVOp->getMaskElt(NumOperands-i-1); 3046 if (Val < 0) Val = 0; 3047 if (Val >= NumOperands) Val -= NumOperands; 3048 Mask |= Val; 3049 if (i != NumOperands - 1) 3050 Mask <<= Shift; 3051 } 3052 return Mask; 3053} 3054 3055/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3056/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3057unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3059 unsigned Mask = 0; 3060 // 8 nodes, but we only care about the last 4. 3061 for (unsigned i = 7; i >= 4; --i) { 3062 int Val = SVOp->getMaskElt(i); 3063 if (Val >= 0) 3064 Mask |= (Val - 4); 3065 if (i != 4) 3066 Mask <<= 2; 3067 } 3068 return Mask; 3069} 3070 3071/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3072/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3073unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3074 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3075 unsigned Mask = 0; 3076 // 8 nodes, but we only care about the first 4. 3077 for (int i = 3; i >= 0; --i) { 3078 int Val = SVOp->getMaskElt(i); 3079 if (Val >= 0) 3080 Mask |= Val; 3081 if (i != 0) 3082 Mask <<= 2; 3083 } 3084 return Mask; 3085} 3086 3087/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3088/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3089unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3091 EVT VVT = N->getValueType(0); 3092 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3093 int Val = 0; 3094 3095 unsigned i, e; 3096 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3097 Val = SVOp->getMaskElt(i); 3098 if (Val >= 0) 3099 break; 3100 } 3101 return (Val - i) * EltSize; 3102} 3103 3104/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3105/// constant +0.0. 3106bool X86::isZeroNode(SDValue Elt) { 3107 return ((isa<ConstantSDNode>(Elt) && 3108 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 3109 (isa<ConstantFPSDNode>(Elt) && 3110 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3111} 3112 3113/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3114/// their permute mask. 3115static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3116 SelectionDAG &DAG) { 3117 EVT VT = SVOp->getValueType(0); 3118 unsigned NumElems = VT.getVectorNumElements(); 3119 SmallVector<int, 8> MaskVec; 3120 3121 for (unsigned i = 0; i != NumElems; ++i) { 3122 int idx = SVOp->getMaskElt(i); 3123 if (idx < 0) 3124 MaskVec.push_back(idx); 3125 else if (idx < (int)NumElems) 3126 MaskVec.push_back(idx + NumElems); 3127 else 3128 MaskVec.push_back(idx - NumElems); 3129 } 3130 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3131 SVOp->getOperand(0), &MaskVec[0]); 3132} 3133 3134/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3135/// the two vector operands have swapped position. 3136static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3137 unsigned NumElems = VT.getVectorNumElements(); 3138 for (unsigned i = 0; i != NumElems; ++i) { 3139 int idx = Mask[i]; 3140 if (idx < 0) 3141 continue; 3142 else if (idx < (int)NumElems) 3143 Mask[i] = idx + NumElems; 3144 else 3145 Mask[i] = idx - NumElems; 3146 } 3147} 3148 3149/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3150/// match movhlps. The lower half elements should come from upper half of 3151/// V1 (and in order), and the upper half elements should come from the upper 3152/// half of V2 (and in order). 3153static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3154 if (Op->getValueType(0).getVectorNumElements() != 4) 3155 return false; 3156 for (unsigned i = 0, e = 2; i != e; ++i) 3157 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3158 return false; 3159 for (unsigned i = 2; i != 4; ++i) 3160 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3161 return false; 3162 return true; 3163} 3164 3165/// isScalarLoadToVector - Returns true if the node is a scalar load that 3166/// is promoted to a vector. It also returns the LoadSDNode by reference if 3167/// required. 3168static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3169 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3170 return false; 3171 N = N->getOperand(0).getNode(); 3172 if (!ISD::isNON_EXTLoad(N)) 3173 return false; 3174 if (LD) 3175 *LD = cast<LoadSDNode>(N); 3176 return true; 3177} 3178 3179/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3180/// match movlp{s|d}. The lower half elements should come from lower half of 3181/// V1 (and in order), and the upper half elements should come from the upper 3182/// half of V2 (and in order). And since V1 will become the source of the 3183/// MOVLP, it must be either a vector load or a scalar load to vector. 3184static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3185 ShuffleVectorSDNode *Op) { 3186 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3187 return false; 3188 // Is V2 is a vector load, don't do this transformation. We will try to use 3189 // load folding shufps op. 3190 if (ISD::isNON_EXTLoad(V2)) 3191 return false; 3192 3193 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3194 3195 if (NumElems != 2 && NumElems != 4) 3196 return false; 3197 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3198 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3199 return false; 3200 for (unsigned i = NumElems/2; i != NumElems; ++i) 3201 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3202 return false; 3203 return true; 3204} 3205 3206/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3207/// all the same. 3208static bool isSplatVector(SDNode *N) { 3209 if (N->getOpcode() != ISD::BUILD_VECTOR) 3210 return false; 3211 3212 SDValue SplatValue = N->getOperand(0); 3213 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3214 if (N->getOperand(i) != SplatValue) 3215 return false; 3216 return true; 3217} 3218 3219/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3220/// to an zero vector. 3221/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3222static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3223 SDValue V1 = N->getOperand(0); 3224 SDValue V2 = N->getOperand(1); 3225 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3226 for (unsigned i = 0; i != NumElems; ++i) { 3227 int Idx = N->getMaskElt(i); 3228 if (Idx >= (int)NumElems) { 3229 unsigned Opc = V2.getOpcode(); 3230 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3231 continue; 3232 if (Opc != ISD::BUILD_VECTOR || 3233 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3234 return false; 3235 } else if (Idx >= 0) { 3236 unsigned Opc = V1.getOpcode(); 3237 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3238 continue; 3239 if (Opc != ISD::BUILD_VECTOR || 3240 !X86::isZeroNode(V1.getOperand(Idx))) 3241 return false; 3242 } 3243 } 3244 return true; 3245} 3246 3247/// getZeroVector - Returns a vector of specified type with all zero elements. 3248/// 3249static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3250 DebugLoc dl) { 3251 assert(VT.isVector() && "Expected a vector type"); 3252 3253 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3254 // type. This ensures they get CSE'd. 3255 SDValue Vec; 3256 if (VT.getSizeInBits() == 64) { // MMX 3257 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3259 } else if (HasSSE2) { // SSE2 3260 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3262 } else { // SSE1 3263 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3264 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3265 } 3266 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3267} 3268 3269/// getOnesVector - Returns a vector of specified type with all bits set. 3270/// 3271static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3272 assert(VT.isVector() && "Expected a vector type"); 3273 3274 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3275 // type. This ensures they get CSE'd. 3276 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3277 SDValue Vec; 3278 if (VT.getSizeInBits() == 64) // MMX 3279 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3280 else // SSE 3281 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3282 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3283} 3284 3285 3286/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3287/// that point to V2 points to its first element. 3288static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3289 EVT VT = SVOp->getValueType(0); 3290 unsigned NumElems = VT.getVectorNumElements(); 3291 3292 bool Changed = false; 3293 SmallVector<int, 8> MaskVec; 3294 SVOp->getMask(MaskVec); 3295 3296 for (unsigned i = 0; i != NumElems; ++i) { 3297 if (MaskVec[i] > (int)NumElems) { 3298 MaskVec[i] = NumElems; 3299 Changed = true; 3300 } 3301 } 3302 if (Changed) 3303 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3304 SVOp->getOperand(1), &MaskVec[0]); 3305 return SDValue(SVOp, 0); 3306} 3307 3308/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3309/// operation of specified width. 3310static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3311 SDValue V2) { 3312 unsigned NumElems = VT.getVectorNumElements(); 3313 SmallVector<int, 8> Mask; 3314 Mask.push_back(NumElems); 3315 for (unsigned i = 1; i != NumElems; ++i) 3316 Mask.push_back(i); 3317 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3318} 3319 3320/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3321static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3322 SDValue V2) { 3323 unsigned NumElems = VT.getVectorNumElements(); 3324 SmallVector<int, 8> Mask; 3325 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3326 Mask.push_back(i); 3327 Mask.push_back(i + NumElems); 3328 } 3329 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3330} 3331 3332/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3333static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3334 SDValue V2) { 3335 unsigned NumElems = VT.getVectorNumElements(); 3336 unsigned Half = NumElems/2; 3337 SmallVector<int, 8> Mask; 3338 for (unsigned i = 0; i != Half; ++i) { 3339 Mask.push_back(i + Half); 3340 Mask.push_back(i + NumElems + Half); 3341 } 3342 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3343} 3344 3345/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3346static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 3347 bool HasSSE2) { 3348 if (SV->getValueType(0).getVectorNumElements() <= 4) 3349 return SDValue(SV, 0); 3350 3351 EVT PVT = MVT::v4f32; 3352 EVT VT = SV->getValueType(0); 3353 DebugLoc dl = SV->getDebugLoc(); 3354 SDValue V1 = SV->getOperand(0); 3355 int NumElems = VT.getVectorNumElements(); 3356 int EltNo = SV->getSplatIndex(); 3357 3358 // unpack elements to the correct location 3359 while (NumElems > 4) { 3360 if (EltNo < NumElems/2) { 3361 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3362 } else { 3363 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3364 EltNo -= NumElems/2; 3365 } 3366 NumElems >>= 1; 3367 } 3368 3369 // Perform the splat. 3370 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3371 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3372 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3373 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3374} 3375 3376/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3377/// vector of zero or undef vector. This produces a shuffle where the low 3378/// element of V2 is swizzled into the zero/undef vector, landing at element 3379/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3380static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3381 bool isZero, bool HasSSE2, 3382 SelectionDAG &DAG) { 3383 EVT VT = V2.getValueType(); 3384 SDValue V1 = isZero 3385 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3386 unsigned NumElems = VT.getVectorNumElements(); 3387 SmallVector<int, 16> MaskVec; 3388 for (unsigned i = 0; i != NumElems; ++i) 3389 // If this is the insertion idx, put the low elt of V2 here. 3390 MaskVec.push_back(i == Idx ? NumElems : i); 3391 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3392} 3393 3394/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3395/// a shuffle that is zero. 3396static 3397unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3398 bool Low, SelectionDAG &DAG) { 3399 unsigned NumZeros = 0; 3400 for (int i = 0; i < NumElems; ++i) { 3401 unsigned Index = Low ? i : NumElems-i-1; 3402 int Idx = SVOp->getMaskElt(Index); 3403 if (Idx < 0) { 3404 ++NumZeros; 3405 continue; 3406 } 3407 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3408 if (Elt.getNode() && X86::isZeroNode(Elt)) 3409 ++NumZeros; 3410 else 3411 break; 3412 } 3413 return NumZeros; 3414} 3415 3416/// isVectorShift - Returns true if the shuffle can be implemented as a 3417/// logical left or right shift of a vector. 3418/// FIXME: split into pslldqi, psrldqi, palignr variants. 3419static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3420 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3421 int NumElems = SVOp->getValueType(0).getVectorNumElements(); 3422 3423 isLeft = true; 3424 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3425 if (!NumZeros) { 3426 isLeft = false; 3427 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3428 if (!NumZeros) 3429 return false; 3430 } 3431 bool SeenV1 = false; 3432 bool SeenV2 = false; 3433 for (int i = NumZeros; i < NumElems; ++i) { 3434 int Val = isLeft ? (i - NumZeros) : i; 3435 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3436 if (Idx < 0) 3437 continue; 3438 if (Idx < NumElems) 3439 SeenV1 = true; 3440 else { 3441 Idx -= NumElems; 3442 SeenV2 = true; 3443 } 3444 if (Idx != Val) 3445 return false; 3446 } 3447 if (SeenV1 && SeenV2) 3448 return false; 3449 3450 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3451 ShAmt = NumZeros; 3452 return true; 3453} 3454 3455 3456/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3457/// 3458static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3459 unsigned NumNonZero, unsigned NumZero, 3460 SelectionDAG &DAG, TargetLowering &TLI) { 3461 if (NumNonZero > 8) 3462 return SDValue(); 3463 3464 DebugLoc dl = Op.getDebugLoc(); 3465 SDValue V(0, 0); 3466 bool First = true; 3467 for (unsigned i = 0; i < 16; ++i) { 3468 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3469 if (ThisIsNonZero && First) { 3470 if (NumZero) 3471 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3472 else 3473 V = DAG.getUNDEF(MVT::v8i16); 3474 First = false; 3475 } 3476 3477 if ((i & 1) != 0) { 3478 SDValue ThisElt(0, 0), LastElt(0, 0); 3479 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3480 if (LastIsNonZero) { 3481 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3482 MVT::i16, Op.getOperand(i-1)); 3483 } 3484 if (ThisIsNonZero) { 3485 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3486 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3487 ThisElt, DAG.getConstant(8, MVT::i8)); 3488 if (LastIsNonZero) 3489 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3490 } else 3491 ThisElt = LastElt; 3492 3493 if (ThisElt.getNode()) 3494 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3495 DAG.getIntPtrConstant(i/2)); 3496 } 3497 } 3498 3499 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3500} 3501 3502/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3503/// 3504static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3505 unsigned NumNonZero, unsigned NumZero, 3506 SelectionDAG &DAG, TargetLowering &TLI) { 3507 if (NumNonZero > 4) 3508 return SDValue(); 3509 3510 DebugLoc dl = Op.getDebugLoc(); 3511 SDValue V(0, 0); 3512 bool First = true; 3513 for (unsigned i = 0; i < 8; ++i) { 3514 bool isNonZero = (NonZeros & (1 << i)) != 0; 3515 if (isNonZero) { 3516 if (First) { 3517 if (NumZero) 3518 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3519 else 3520 V = DAG.getUNDEF(MVT::v8i16); 3521 First = false; 3522 } 3523 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3524 MVT::v8i16, V, Op.getOperand(i), 3525 DAG.getIntPtrConstant(i)); 3526 } 3527 } 3528 3529 return V; 3530} 3531 3532/// getVShift - Return a vector logical shift node. 3533/// 3534static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3535 unsigned NumBits, SelectionDAG &DAG, 3536 const TargetLowering &TLI, DebugLoc dl) { 3537 bool isMMX = VT.getSizeInBits() == 64; 3538 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3539 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3540 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3541 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3542 DAG.getNode(Opc, dl, ShVT, SrcOp, 3543 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3544} 3545 3546SDValue 3547X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3548 SelectionDAG &DAG) { 3549 3550 // Check if the scalar load can be widened into a vector load. And if 3551 // the address is "base + cst" see if the cst can be "absorbed" into 3552 // the shuffle mask. 3553 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3554 SDValue Ptr = LD->getBasePtr(); 3555 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 3556 return SDValue(); 3557 EVT PVT = LD->getValueType(0); 3558 if (PVT != MVT::i32 && PVT != MVT::f32) 3559 return SDValue(); 3560 3561 int FI = -1; 3562 int64_t Offset = 0; 3563 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 3564 FI = FINode->getIndex(); 3565 Offset = 0; 3566 } else if (Ptr.getOpcode() == ISD::ADD && 3567 isa<ConstantSDNode>(Ptr.getOperand(1)) && 3568 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 3569 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 3570 Offset = Ptr.getConstantOperandVal(1); 3571 Ptr = Ptr.getOperand(0); 3572 } else { 3573 return SDValue(); 3574 } 3575 3576 SDValue Chain = LD->getChain(); 3577 // Make sure the stack object alignment is at least 16. 3578 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3579 if (DAG.InferPtrAlignment(Ptr) < 16) { 3580 if (MFI->isFixedObjectIndex(FI)) { 3581 // Can't change the alignment. FIXME: It's possible to compute 3582 // the exact stack offset and reference FI + adjust offset instead. 3583 // If someone *really* cares about this. That's the way to implement it. 3584 return SDValue(); 3585 } else { 3586 MFI->setObjectAlignment(FI, 16); 3587 } 3588 } 3589 3590 // (Offset % 16) must be multiple of 4. Then address is then 3591 // Ptr + (Offset & ~15). 3592 if (Offset < 0) 3593 return SDValue(); 3594 if ((Offset % 16) & 3) 3595 return SDValue(); 3596 int64_t StartOffset = Offset & ~15; 3597 if (StartOffset) 3598 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 3599 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 3600 3601 int EltNo = (Offset - StartOffset) >> 2; 3602 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 3603 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 3604 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0, 3605 false, false, 0); 3606 // Canonicalize it to a v4i32 shuffle. 3607 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); 3608 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3609 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 3610 DAG.getUNDEF(MVT::v4i32), &Mask[0])); 3611 } 3612 3613 return SDValue(); 3614} 3615 3616SDValue 3617X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3618 DebugLoc dl = Op.getDebugLoc(); 3619 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3620 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3621 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3622 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3623 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3624 // eliminated on x86-32 hosts. 3625 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3626 return Op; 3627 3628 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3629 return getOnesVector(Op.getValueType(), DAG, dl); 3630 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3631 } 3632 3633 EVT VT = Op.getValueType(); 3634 EVT ExtVT = VT.getVectorElementType(); 3635 unsigned EVTBits = ExtVT.getSizeInBits(); 3636 3637 unsigned NumElems = Op.getNumOperands(); 3638 unsigned NumZero = 0; 3639 unsigned NumNonZero = 0; 3640 unsigned NonZeros = 0; 3641 bool IsAllConstants = true; 3642 SmallSet<SDValue, 8> Values; 3643 for (unsigned i = 0; i < NumElems; ++i) { 3644 SDValue Elt = Op.getOperand(i); 3645 if (Elt.getOpcode() == ISD::UNDEF) 3646 continue; 3647 Values.insert(Elt); 3648 if (Elt.getOpcode() != ISD::Constant && 3649 Elt.getOpcode() != ISD::ConstantFP) 3650 IsAllConstants = false; 3651 if (X86::isZeroNode(Elt)) 3652 NumZero++; 3653 else { 3654 NonZeros |= (1 << i); 3655 NumNonZero++; 3656 } 3657 } 3658 3659 if (NumNonZero == 0) { 3660 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3661 return DAG.getUNDEF(VT); 3662 } 3663 3664 // Special case for single non-zero, non-undef, element. 3665 if (NumNonZero == 1) { 3666 unsigned Idx = CountTrailingZeros_32(NonZeros); 3667 SDValue Item = Op.getOperand(Idx); 3668 3669 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3670 // the value are obviously zero, truncate the value to i32 and do the 3671 // insertion that way. Only do this if the value is non-constant or if the 3672 // value is a constant being inserted into element 0. It is cheaper to do 3673 // a constant pool load than it is to do a movd + shuffle. 3674 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 3675 (!IsAllConstants || Idx == 0)) { 3676 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3677 // Handle MMX and SSE both. 3678 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3679 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3680 3681 // Truncate the value (which may itself be a constant) to i32, and 3682 // convert it to a vector with movd (S2V+shuffle to zero extend). 3683 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3684 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3685 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3686 Subtarget->hasSSE2(), DAG); 3687 3688 // Now we have our 32-bit value zero extended in the low element of 3689 // a vector. If Idx != 0, swizzle it into place. 3690 if (Idx != 0) { 3691 SmallVector<int, 4> Mask; 3692 Mask.push_back(Idx); 3693 for (unsigned i = 1; i != VecElts; ++i) 3694 Mask.push_back(i); 3695 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3696 DAG.getUNDEF(Item.getValueType()), 3697 &Mask[0]); 3698 } 3699 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3700 } 3701 } 3702 3703 // If we have a constant or non-constant insertion into the low element of 3704 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3705 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3706 // depending on what the source datatype is. 3707 if (Idx == 0) { 3708 if (NumZero == 0) { 3709 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3710 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 3711 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 3712 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3713 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3714 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3715 DAG); 3716 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 3717 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3718 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3719 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3720 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3721 Subtarget->hasSSE2(), DAG); 3722 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3723 } 3724 } 3725 3726 // Is it a vector logical left shift? 3727 if (NumElems == 2 && Idx == 1 && 3728 X86::isZeroNode(Op.getOperand(0)) && 3729 !X86::isZeroNode(Op.getOperand(1))) { 3730 unsigned NumBits = VT.getSizeInBits(); 3731 return getVShift(true, VT, 3732 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3733 VT, Op.getOperand(1)), 3734 NumBits/2, DAG, *this, dl); 3735 } 3736 3737 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3738 return SDValue(); 3739 3740 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3741 // is a non-constant being inserted into an element other than the low one, 3742 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3743 // movd/movss) to move this into the low element, then shuffle it into 3744 // place. 3745 if (EVTBits == 32) { 3746 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3747 3748 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3749 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3750 Subtarget->hasSSE2(), DAG); 3751 SmallVector<int, 8> MaskVec; 3752 for (unsigned i = 0; i < NumElems; i++) 3753 MaskVec.push_back(i == Idx ? 0 : 1); 3754 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3755 } 3756 } 3757 3758 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3759 if (Values.size() == 1) { 3760 if (EVTBits == 32) { 3761 // Instead of a shuffle like this: 3762 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 3763 // Check if it's possible to issue this instead. 3764 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 3765 unsigned Idx = CountTrailingZeros_32(NonZeros); 3766 SDValue Item = Op.getOperand(Idx); 3767 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 3768 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 3769 } 3770 return SDValue(); 3771 } 3772 3773 // A vector full of immediates; various special cases are already 3774 // handled, so this is best done with a single constant-pool load. 3775 if (IsAllConstants) 3776 return SDValue(); 3777 3778 // Let legalizer expand 2-wide build_vectors. 3779 if (EVTBits == 64) { 3780 if (NumNonZero == 1) { 3781 // One half is zero or undef. 3782 unsigned Idx = CountTrailingZeros_32(NonZeros); 3783 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3784 Op.getOperand(Idx)); 3785 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3786 Subtarget->hasSSE2(), DAG); 3787 } 3788 return SDValue(); 3789 } 3790 3791 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3792 if (EVTBits == 8 && NumElems == 16) { 3793 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3794 *this); 3795 if (V.getNode()) return V; 3796 } 3797 3798 if (EVTBits == 16 && NumElems == 8) { 3799 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3800 *this); 3801 if (V.getNode()) return V; 3802 } 3803 3804 // If element VT is == 32 bits, turn it into a number of shuffles. 3805 SmallVector<SDValue, 8> V; 3806 V.resize(NumElems); 3807 if (NumElems == 4 && NumZero > 0) { 3808 for (unsigned i = 0; i < 4; ++i) { 3809 bool isZero = !(NonZeros & (1 << i)); 3810 if (isZero) 3811 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3812 else 3813 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3814 } 3815 3816 for (unsigned i = 0; i < 2; ++i) { 3817 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3818 default: break; 3819 case 0: 3820 V[i] = V[i*2]; // Must be a zero vector. 3821 break; 3822 case 1: 3823 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 3824 break; 3825 case 2: 3826 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 3827 break; 3828 case 3: 3829 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 3830 break; 3831 } 3832 } 3833 3834 SmallVector<int, 8> MaskVec; 3835 bool Reverse = (NonZeros & 0x3) == 2; 3836 for (unsigned i = 0; i < 2; ++i) 3837 MaskVec.push_back(Reverse ? 1-i : i); 3838 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3839 for (unsigned i = 0; i < 2; ++i) 3840 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 3841 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 3842 } 3843 3844 if (Values.size() > 2) { 3845 // If we have SSE 4.1, Expand into a number of inserts unless the number of 3846 // values to be inserted is equal to the number of elements, in which case 3847 // use the unpack code below in the hopes of matching the consecutive elts 3848 // load merge pattern for shuffles. 3849 // FIXME: We could probably just check that here directly. 3850 if (Values.size() < NumElems && VT.getSizeInBits() == 128 && 3851 getSubtarget()->hasSSE41()) { 3852 V[0] = DAG.getUNDEF(VT); 3853 for (unsigned i = 0; i < NumElems; ++i) 3854 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 3855 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 3856 Op.getOperand(i), DAG.getIntPtrConstant(i)); 3857 return V[0]; 3858 } 3859 // Expand into a number of unpckl*. 3860 // e.g. for v4f32 3861 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3862 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3863 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3864 for (unsigned i = 0; i < NumElems; ++i) 3865 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3866 NumElems >>= 1; 3867 while (NumElems != 0) { 3868 for (unsigned i = 0; i < NumElems; ++i) 3869 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 3870 NumElems >>= 1; 3871 } 3872 return V[0]; 3873 } 3874 3875 return SDValue(); 3876} 3877 3878SDValue 3879X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 3880 // We support concatenate two MMX registers and place them in a MMX 3881 // register. This is better than doing a stack convert. 3882 DebugLoc dl = Op.getDebugLoc(); 3883 EVT ResVT = Op.getValueType(); 3884 assert(Op.getNumOperands() == 2); 3885 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 3886 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 3887 int Mask[2]; 3888 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); 3889 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3890 InVec = Op.getOperand(1); 3891 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 3892 unsigned NumElts = ResVT.getVectorNumElements(); 3893 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3894 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 3895 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 3896 } else { 3897 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); 3898 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3899 Mask[0] = 0; Mask[1] = 2; 3900 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 3901 } 3902 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3903} 3904 3905// v8i16 shuffles - Prefer shuffles in the following order: 3906// 1. [all] pshuflw, pshufhw, optional move 3907// 2. [ssse3] 1 x pshufb 3908// 3. [ssse3] 2 x pshufb + 1 x por 3909// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 3910static 3911SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 3912 SelectionDAG &DAG, X86TargetLowering &TLI) { 3913 SDValue V1 = SVOp->getOperand(0); 3914 SDValue V2 = SVOp->getOperand(1); 3915 DebugLoc dl = SVOp->getDebugLoc(); 3916 SmallVector<int, 8> MaskVals; 3917 3918 // Determine if more than 1 of the words in each of the low and high quadwords 3919 // of the result come from the same quadword of one of the two inputs. Undef 3920 // mask values count as coming from any quadword, for better codegen. 3921 SmallVector<unsigned, 4> LoQuad(4); 3922 SmallVector<unsigned, 4> HiQuad(4); 3923 BitVector InputQuads(4); 3924 for (unsigned i = 0; i < 8; ++i) { 3925 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 3926 int EltIdx = SVOp->getMaskElt(i); 3927 MaskVals.push_back(EltIdx); 3928 if (EltIdx < 0) { 3929 ++Quad[0]; 3930 ++Quad[1]; 3931 ++Quad[2]; 3932 ++Quad[3]; 3933 continue; 3934 } 3935 ++Quad[EltIdx / 4]; 3936 InputQuads.set(EltIdx / 4); 3937 } 3938 3939 int BestLoQuad = -1; 3940 unsigned MaxQuad = 1; 3941 for (unsigned i = 0; i < 4; ++i) { 3942 if (LoQuad[i] > MaxQuad) { 3943 BestLoQuad = i; 3944 MaxQuad = LoQuad[i]; 3945 } 3946 } 3947 3948 int BestHiQuad = -1; 3949 MaxQuad = 1; 3950 for (unsigned i = 0; i < 4; ++i) { 3951 if (HiQuad[i] > MaxQuad) { 3952 BestHiQuad = i; 3953 MaxQuad = HiQuad[i]; 3954 } 3955 } 3956 3957 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 3958 // of the two input vectors, shuffle them into one input vector so only a 3959 // single pshufb instruction is necessary. If There are more than 2 input 3960 // quads, disable the next transformation since it does not help SSSE3. 3961 bool V1Used = InputQuads[0] || InputQuads[1]; 3962 bool V2Used = InputQuads[2] || InputQuads[3]; 3963 if (TLI.getSubtarget()->hasSSSE3()) { 3964 if (InputQuads.count() == 2 && V1Used && V2Used) { 3965 BestLoQuad = InputQuads.find_first(); 3966 BestHiQuad = InputQuads.find_next(BestLoQuad); 3967 } 3968 if (InputQuads.count() > 2) { 3969 BestLoQuad = -1; 3970 BestHiQuad = -1; 3971 } 3972 } 3973 3974 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 3975 // the shuffle mask. If a quad is scored as -1, that means that it contains 3976 // words from all 4 input quadwords. 3977 SDValue NewV; 3978 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 3979 SmallVector<int, 8> MaskV; 3980 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 3981 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 3982 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 3983 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 3984 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 3985 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 3986 3987 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 3988 // source words for the shuffle, to aid later transformations. 3989 bool AllWordsInNewV = true; 3990 bool InOrder[2] = { true, true }; 3991 for (unsigned i = 0; i != 8; ++i) { 3992 int idx = MaskVals[i]; 3993 if (idx != (int)i) 3994 InOrder[i/4] = false; 3995 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 3996 continue; 3997 AllWordsInNewV = false; 3998 break; 3999 } 4000 4001 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 4002 if (AllWordsInNewV) { 4003 for (int i = 0; i != 8; ++i) { 4004 int idx = MaskVals[i]; 4005 if (idx < 0) 4006 continue; 4007 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 4008 if ((idx != i) && idx < 4) 4009 pshufhw = false; 4010 if ((idx != i) && idx > 3) 4011 pshuflw = false; 4012 } 4013 V1 = NewV; 4014 V2Used = false; 4015 BestLoQuad = 0; 4016 BestHiQuad = 1; 4017 } 4018 4019 // If we've eliminated the use of V2, and the new mask is a pshuflw or 4020 // pshufhw, that's as cheap as it gets. Return the new shuffle. 4021 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 4022 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 4023 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 4024 } 4025 } 4026 4027 // If we have SSSE3, and all words of the result are from 1 input vector, 4028 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4029 // is present, fall back to case 4. 4030 if (TLI.getSubtarget()->hasSSSE3()) { 4031 SmallVector<SDValue,16> pshufbMask; 4032 4033 // If we have elements from both input vectors, set the high bit of the 4034 // shuffle mask element to zero out elements that come from V2 in the V1 4035 // mask, and elements that come from V1 in the V2 mask, so that the two 4036 // results can be OR'd together. 4037 bool TwoInputs = V1Used && V2Used; 4038 for (unsigned i = 0; i != 8; ++i) { 4039 int EltIdx = MaskVals[i] * 2; 4040 if (TwoInputs && (EltIdx >= 16)) { 4041 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4042 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4043 continue; 4044 } 4045 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4046 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4047 } 4048 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 4049 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4050 DAG.getNode(ISD::BUILD_VECTOR, dl, 4051 MVT::v16i8, &pshufbMask[0], 16)); 4052 if (!TwoInputs) 4053 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4054 4055 // Calculate the shuffle mask for the second input, shuffle it, and 4056 // OR it with the first shuffled input. 4057 pshufbMask.clear(); 4058 for (unsigned i = 0; i != 8; ++i) { 4059 int EltIdx = MaskVals[i] * 2; 4060 if (EltIdx < 16) { 4061 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4062 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4063 continue; 4064 } 4065 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4066 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4067 } 4068 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 4069 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4070 DAG.getNode(ISD::BUILD_VECTOR, dl, 4071 MVT::v16i8, &pshufbMask[0], 16)); 4072 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4073 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4074 } 4075 4076 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4077 // and update MaskVals with new element order. 4078 BitVector InOrder(8); 4079 if (BestLoQuad >= 0) { 4080 SmallVector<int, 8> MaskV; 4081 for (int i = 0; i != 4; ++i) { 4082 int idx = MaskVals[i]; 4083 if (idx < 0) { 4084 MaskV.push_back(-1); 4085 InOrder.set(i); 4086 } else if ((idx / 4) == BestLoQuad) { 4087 MaskV.push_back(idx & 3); 4088 InOrder.set(i); 4089 } else { 4090 MaskV.push_back(-1); 4091 } 4092 } 4093 for (unsigned i = 4; i != 8; ++i) 4094 MaskV.push_back(i); 4095 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4096 &MaskV[0]); 4097 } 4098 4099 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4100 // and update MaskVals with the new element order. 4101 if (BestHiQuad >= 0) { 4102 SmallVector<int, 8> MaskV; 4103 for (unsigned i = 0; i != 4; ++i) 4104 MaskV.push_back(i); 4105 for (unsigned i = 4; i != 8; ++i) { 4106 int idx = MaskVals[i]; 4107 if (idx < 0) { 4108 MaskV.push_back(-1); 4109 InOrder.set(i); 4110 } else if ((idx / 4) == BestHiQuad) { 4111 MaskV.push_back((idx & 3) + 4); 4112 InOrder.set(i); 4113 } else { 4114 MaskV.push_back(-1); 4115 } 4116 } 4117 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4118 &MaskV[0]); 4119 } 4120 4121 // In case BestHi & BestLo were both -1, which means each quadword has a word 4122 // from each of the four input quadwords, calculate the InOrder bitvector now 4123 // before falling through to the insert/extract cleanup. 4124 if (BestLoQuad == -1 && BestHiQuad == -1) { 4125 NewV = V1; 4126 for (int i = 0; i != 8; ++i) 4127 if (MaskVals[i] < 0 || MaskVals[i] == i) 4128 InOrder.set(i); 4129 } 4130 4131 // The other elements are put in the right place using pextrw and pinsrw. 4132 for (unsigned i = 0; i != 8; ++i) { 4133 if (InOrder[i]) 4134 continue; 4135 int EltIdx = MaskVals[i]; 4136 if (EltIdx < 0) 4137 continue; 4138 SDValue ExtOp = (EltIdx < 8) 4139 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4140 DAG.getIntPtrConstant(EltIdx)) 4141 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4142 DAG.getIntPtrConstant(EltIdx - 8)); 4143 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4144 DAG.getIntPtrConstant(i)); 4145 } 4146 return NewV; 4147} 4148 4149// v16i8 shuffles - Prefer shuffles in the following order: 4150// 1. [ssse3] 1 x pshufb 4151// 2. [ssse3] 2 x pshufb + 1 x por 4152// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4153static 4154SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4155 SelectionDAG &DAG, X86TargetLowering &TLI) { 4156 SDValue V1 = SVOp->getOperand(0); 4157 SDValue V2 = SVOp->getOperand(1); 4158 DebugLoc dl = SVOp->getDebugLoc(); 4159 SmallVector<int, 16> MaskVals; 4160 SVOp->getMask(MaskVals); 4161 4162 // If we have SSSE3, case 1 is generated when all result bytes come from 4163 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4164 // present, fall back to case 3. 4165 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4166 bool V1Only = true; 4167 bool V2Only = true; 4168 for (unsigned i = 0; i < 16; ++i) { 4169 int EltIdx = MaskVals[i]; 4170 if (EltIdx < 0) 4171 continue; 4172 if (EltIdx < 16) 4173 V2Only = false; 4174 else 4175 V1Only = false; 4176 } 4177 4178 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4179 if (TLI.getSubtarget()->hasSSSE3()) { 4180 SmallVector<SDValue,16> pshufbMask; 4181 4182 // If all result elements are from one input vector, then only translate 4183 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4184 // 4185 // Otherwise, we have elements from both input vectors, and must zero out 4186 // elements that come from V2 in the first mask, and V1 in the second mask 4187 // so that we can OR them together. 4188 bool TwoInputs = !(V1Only || V2Only); 4189 for (unsigned i = 0; i != 16; ++i) { 4190 int EltIdx = MaskVals[i]; 4191 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4192 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4193 continue; 4194 } 4195 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4196 } 4197 // If all the elements are from V2, assign it to V1 and return after 4198 // building the first pshufb. 4199 if (V2Only) 4200 V1 = V2; 4201 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4202 DAG.getNode(ISD::BUILD_VECTOR, dl, 4203 MVT::v16i8, &pshufbMask[0], 16)); 4204 if (!TwoInputs) 4205 return V1; 4206 4207 // Calculate the shuffle mask for the second input, shuffle it, and 4208 // OR it with the first shuffled input. 4209 pshufbMask.clear(); 4210 for (unsigned i = 0; i != 16; ++i) { 4211 int EltIdx = MaskVals[i]; 4212 if (EltIdx < 16) { 4213 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4214 continue; 4215 } 4216 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4217 } 4218 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4219 DAG.getNode(ISD::BUILD_VECTOR, dl, 4220 MVT::v16i8, &pshufbMask[0], 16)); 4221 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4222 } 4223 4224 // No SSSE3 - Calculate in place words and then fix all out of place words 4225 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4226 // the 16 different words that comprise the two doublequadword input vectors. 4227 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4228 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 4229 SDValue NewV = V2Only ? V2 : V1; 4230 for (int i = 0; i != 8; ++i) { 4231 int Elt0 = MaskVals[i*2]; 4232 int Elt1 = MaskVals[i*2+1]; 4233 4234 // This word of the result is all undef, skip it. 4235 if (Elt0 < 0 && Elt1 < 0) 4236 continue; 4237 4238 // This word of the result is already in the correct place, skip it. 4239 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4240 continue; 4241 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4242 continue; 4243 4244 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4245 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4246 SDValue InsElt; 4247 4248 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4249 // using a single extract together, load it and store it. 4250 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4251 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4252 DAG.getIntPtrConstant(Elt1 / 2)); 4253 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4254 DAG.getIntPtrConstant(i)); 4255 continue; 4256 } 4257 4258 // If Elt1 is defined, extract it from the appropriate source. If the 4259 // source byte is not also odd, shift the extracted word left 8 bits 4260 // otherwise clear the bottom 8 bits if we need to do an or. 4261 if (Elt1 >= 0) { 4262 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4263 DAG.getIntPtrConstant(Elt1 / 2)); 4264 if ((Elt1 & 1) == 0) 4265 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4266 DAG.getConstant(8, TLI.getShiftAmountTy())); 4267 else if (Elt0 >= 0) 4268 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4269 DAG.getConstant(0xFF00, MVT::i16)); 4270 } 4271 // If Elt0 is defined, extract it from the appropriate source. If the 4272 // source byte is not also even, shift the extracted word right 8 bits. If 4273 // Elt1 was also defined, OR the extracted values together before 4274 // inserting them in the result. 4275 if (Elt0 >= 0) { 4276 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4277 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4278 if ((Elt0 & 1) != 0) 4279 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4280 DAG.getConstant(8, TLI.getShiftAmountTy())); 4281 else if (Elt1 >= 0) 4282 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4283 DAG.getConstant(0x00FF, MVT::i16)); 4284 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4285 : InsElt0; 4286 } 4287 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4288 DAG.getIntPtrConstant(i)); 4289 } 4290 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 4291} 4292 4293/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4294/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 4295/// done when every pair / quad of shuffle mask elements point to elements in 4296/// the right sequence. e.g. 4297/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 4298static 4299SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4300 SelectionDAG &DAG, 4301 TargetLowering &TLI, DebugLoc dl) { 4302 EVT VT = SVOp->getValueType(0); 4303 SDValue V1 = SVOp->getOperand(0); 4304 SDValue V2 = SVOp->getOperand(1); 4305 unsigned NumElems = VT.getVectorNumElements(); 4306 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4307 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 4308 EVT MaskEltVT = MaskVT.getVectorElementType(); 4309 EVT NewVT = MaskVT; 4310 switch (VT.getSimpleVT().SimpleTy) { 4311 default: assert(false && "Unexpected!"); 4312 case MVT::v4f32: NewVT = MVT::v2f64; break; 4313 case MVT::v4i32: NewVT = MVT::v2i64; break; 4314 case MVT::v8i16: NewVT = MVT::v4i32; break; 4315 case MVT::v16i8: NewVT = MVT::v4i32; break; 4316 } 4317 4318 if (NewWidth == 2) { 4319 if (VT.isInteger()) 4320 NewVT = MVT::v2i64; 4321 else 4322 NewVT = MVT::v2f64; 4323 } 4324 int Scale = NumElems / NewWidth; 4325 SmallVector<int, 8> MaskVec; 4326 for (unsigned i = 0; i < NumElems; i += Scale) { 4327 int StartIdx = -1; 4328 for (int j = 0; j < Scale; ++j) { 4329 int EltIdx = SVOp->getMaskElt(i+j); 4330 if (EltIdx < 0) 4331 continue; 4332 if (StartIdx == -1) 4333 StartIdx = EltIdx - (EltIdx % Scale); 4334 if (EltIdx != StartIdx + j) 4335 return SDValue(); 4336 } 4337 if (StartIdx == -1) 4338 MaskVec.push_back(-1); 4339 else 4340 MaskVec.push_back(StartIdx / Scale); 4341 } 4342 4343 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 4344 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 4345 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4346} 4347 4348/// getVZextMovL - Return a zero-extending vector move low node. 4349/// 4350static SDValue getVZextMovL(EVT VT, EVT OpVT, 4351 SDValue SrcOp, SelectionDAG &DAG, 4352 const X86Subtarget *Subtarget, DebugLoc dl) { 4353 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4354 LoadSDNode *LD = NULL; 4355 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4356 LD = dyn_cast<LoadSDNode>(SrcOp); 4357 if (!LD) { 4358 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4359 // instead. 4360 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4361 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 4362 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4363 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4364 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4365 // PR2108 4366 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4367 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4368 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4369 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4370 OpVT, 4371 SrcOp.getOperand(0) 4372 .getOperand(0)))); 4373 } 4374 } 4375 } 4376 4377 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4378 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4379 DAG.getNode(ISD::BIT_CONVERT, dl, 4380 OpVT, SrcOp))); 4381} 4382 4383/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4384/// shuffles. 4385static SDValue 4386LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4387 SDValue V1 = SVOp->getOperand(0); 4388 SDValue V2 = SVOp->getOperand(1); 4389 DebugLoc dl = SVOp->getDebugLoc(); 4390 EVT VT = SVOp->getValueType(0); 4391 4392 SmallVector<std::pair<int, int>, 8> Locs; 4393 Locs.resize(4); 4394 SmallVector<int, 8> Mask1(4U, -1); 4395 SmallVector<int, 8> PermMask; 4396 SVOp->getMask(PermMask); 4397 4398 unsigned NumHi = 0; 4399 unsigned NumLo = 0; 4400 for (unsigned i = 0; i != 4; ++i) { 4401 int Idx = PermMask[i]; 4402 if (Idx < 0) { 4403 Locs[i] = std::make_pair(-1, -1); 4404 } else { 4405 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4406 if (Idx < 4) { 4407 Locs[i] = std::make_pair(0, NumLo); 4408 Mask1[NumLo] = Idx; 4409 NumLo++; 4410 } else { 4411 Locs[i] = std::make_pair(1, NumHi); 4412 if (2+NumHi < 4) 4413 Mask1[2+NumHi] = Idx; 4414 NumHi++; 4415 } 4416 } 4417 } 4418 4419 if (NumLo <= 2 && NumHi <= 2) { 4420 // If no more than two elements come from either vector. This can be 4421 // implemented with two shuffles. First shuffle gather the elements. 4422 // The second shuffle, which takes the first shuffle as both of its 4423 // vector operands, put the elements into the right order. 4424 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4425 4426 SmallVector<int, 8> Mask2(4U, -1); 4427 4428 for (unsigned i = 0; i != 4; ++i) { 4429 if (Locs[i].first == -1) 4430 continue; 4431 else { 4432 unsigned Idx = (i < 2) ? 0 : 4; 4433 Idx += Locs[i].first * 2 + Locs[i].second; 4434 Mask2[i] = Idx; 4435 } 4436 } 4437 4438 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4439 } else if (NumLo == 3 || NumHi == 3) { 4440 // Otherwise, we must have three elements from one vector, call it X, and 4441 // one element from the other, call it Y. First, use a shufps to build an 4442 // intermediate vector with the one element from Y and the element from X 4443 // that will be in the same half in the final destination (the indexes don't 4444 // matter). Then, use a shufps to build the final vector, taking the half 4445 // containing the element from Y from the intermediate, and the other half 4446 // from X. 4447 if (NumHi == 3) { 4448 // Normalize it so the 3 elements come from V1. 4449 CommuteVectorShuffleMask(PermMask, VT); 4450 std::swap(V1, V2); 4451 } 4452 4453 // Find the element from V2. 4454 unsigned HiIndex; 4455 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4456 int Val = PermMask[HiIndex]; 4457 if (Val < 0) 4458 continue; 4459 if (Val >= 4) 4460 break; 4461 } 4462 4463 Mask1[0] = PermMask[HiIndex]; 4464 Mask1[1] = -1; 4465 Mask1[2] = PermMask[HiIndex^1]; 4466 Mask1[3] = -1; 4467 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4468 4469 if (HiIndex >= 2) { 4470 Mask1[0] = PermMask[0]; 4471 Mask1[1] = PermMask[1]; 4472 Mask1[2] = HiIndex & 1 ? 6 : 4; 4473 Mask1[3] = HiIndex & 1 ? 4 : 6; 4474 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4475 } else { 4476 Mask1[0] = HiIndex & 1 ? 2 : 0; 4477 Mask1[1] = HiIndex & 1 ? 0 : 2; 4478 Mask1[2] = PermMask[2]; 4479 Mask1[3] = PermMask[3]; 4480 if (Mask1[2] >= 0) 4481 Mask1[2] += 4; 4482 if (Mask1[3] >= 0) 4483 Mask1[3] += 4; 4484 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4485 } 4486 } 4487 4488 // Break it into (shuffle shuffle_hi, shuffle_lo). 4489 Locs.clear(); 4490 SmallVector<int,8> LoMask(4U, -1); 4491 SmallVector<int,8> HiMask(4U, -1); 4492 4493 SmallVector<int,8> *MaskPtr = &LoMask; 4494 unsigned MaskIdx = 0; 4495 unsigned LoIdx = 0; 4496 unsigned HiIdx = 2; 4497 for (unsigned i = 0; i != 4; ++i) { 4498 if (i == 2) { 4499 MaskPtr = &HiMask; 4500 MaskIdx = 1; 4501 LoIdx = 0; 4502 HiIdx = 2; 4503 } 4504 int Idx = PermMask[i]; 4505 if (Idx < 0) { 4506 Locs[i] = std::make_pair(-1, -1); 4507 } else if (Idx < 4) { 4508 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4509 (*MaskPtr)[LoIdx] = Idx; 4510 LoIdx++; 4511 } else { 4512 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4513 (*MaskPtr)[HiIdx] = Idx; 4514 HiIdx++; 4515 } 4516 } 4517 4518 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4519 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4520 SmallVector<int, 8> MaskOps; 4521 for (unsigned i = 0; i != 4; ++i) { 4522 if (Locs[i].first == -1) { 4523 MaskOps.push_back(-1); 4524 } else { 4525 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4526 MaskOps.push_back(Idx); 4527 } 4528 } 4529 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4530} 4531 4532SDValue 4533X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4534 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4535 SDValue V1 = Op.getOperand(0); 4536 SDValue V2 = Op.getOperand(1); 4537 EVT VT = Op.getValueType(); 4538 DebugLoc dl = Op.getDebugLoc(); 4539 unsigned NumElems = VT.getVectorNumElements(); 4540 bool isMMX = VT.getSizeInBits() == 64; 4541 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4542 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4543 bool V1IsSplat = false; 4544 bool V2IsSplat = false; 4545 4546 if (isZeroShuffle(SVOp)) 4547 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4548 4549 // Promote splats to v4f32. 4550 if (SVOp->isSplat()) { 4551 if (isMMX || NumElems < 4) 4552 return Op; 4553 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4554 } 4555 4556 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4557 // do it! 4558 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4559 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4560 if (NewOp.getNode()) 4561 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4562 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4563 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4564 // FIXME: Figure out a cleaner way to do this. 4565 // Try to make use of movq to zero out the top part. 4566 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4567 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4568 if (NewOp.getNode()) { 4569 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4570 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4571 DAG, Subtarget, dl); 4572 } 4573 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4574 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4575 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4576 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4577 DAG, Subtarget, dl); 4578 } 4579 } 4580 4581 if (X86::isPSHUFDMask(SVOp)) 4582 return Op; 4583 4584 // Check if this can be converted into a logical shift. 4585 bool isLeft = false; 4586 unsigned ShAmt = 0; 4587 SDValue ShVal; 4588 bool isShift = getSubtarget()->hasSSE2() && 4589 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4590 if (isShift && ShVal.hasOneUse()) { 4591 // If the shifted value has multiple uses, it may be cheaper to use 4592 // v_set0 + movlhps or movhlps, etc. 4593 EVT EltVT = VT.getVectorElementType(); 4594 ShAmt *= EltVT.getSizeInBits(); 4595 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4596 } 4597 4598 if (X86::isMOVLMask(SVOp)) { 4599 if (V1IsUndef) 4600 return V2; 4601 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4602 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4603 if (!isMMX) 4604 return Op; 4605 } 4606 4607 // FIXME: fold these into legal mask. 4608 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4609 X86::isMOVSLDUPMask(SVOp) || 4610 X86::isMOVHLPSMask(SVOp) || 4611 X86::isMOVLHPSMask(SVOp) || 4612 X86::isMOVLPMask(SVOp))) 4613 return Op; 4614 4615 if (ShouldXformToMOVHLPS(SVOp) || 4616 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4617 return CommuteVectorShuffle(SVOp, DAG); 4618 4619 if (isShift) { 4620 // No better options. Use a vshl / vsrl. 4621 EVT EltVT = VT.getVectorElementType(); 4622 ShAmt *= EltVT.getSizeInBits(); 4623 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4624 } 4625 4626 bool Commuted = false; 4627 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4628 // 1,1,1,1 -> v8i16 though. 4629 V1IsSplat = isSplatVector(V1.getNode()); 4630 V2IsSplat = isSplatVector(V2.getNode()); 4631 4632 // Canonicalize the splat or undef, if present, to be on the RHS. 4633 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4634 Op = CommuteVectorShuffle(SVOp, DAG); 4635 SVOp = cast<ShuffleVectorSDNode>(Op); 4636 V1 = SVOp->getOperand(0); 4637 V2 = SVOp->getOperand(1); 4638 std::swap(V1IsSplat, V2IsSplat); 4639 std::swap(V1IsUndef, V2IsUndef); 4640 Commuted = true; 4641 } 4642 4643 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4644 // Shuffling low element of v1 into undef, just return v1. 4645 if (V2IsUndef) 4646 return V1; 4647 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4648 // the instruction selector will not match, so get a canonical MOVL with 4649 // swapped operands to undo the commute. 4650 return getMOVL(DAG, dl, VT, V2, V1); 4651 } 4652 4653 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4654 X86::isUNPCKH_v_undef_Mask(SVOp) || 4655 X86::isUNPCKLMask(SVOp) || 4656 X86::isUNPCKHMask(SVOp)) 4657 return Op; 4658 4659 if (V2IsSplat) { 4660 // Normalize mask so all entries that point to V2 points to its first 4661 // element then try to match unpck{h|l} again. If match, return a 4662 // new vector_shuffle with the corrected mask. 4663 SDValue NewMask = NormalizeMask(SVOp, DAG); 4664 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4665 if (NSVOp != SVOp) { 4666 if (X86::isUNPCKLMask(NSVOp, true)) { 4667 return NewMask; 4668 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4669 return NewMask; 4670 } 4671 } 4672 } 4673 4674 if (Commuted) { 4675 // Commute is back and try unpck* again. 4676 // FIXME: this seems wrong. 4677 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4678 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4679 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4680 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4681 X86::isUNPCKLMask(NewSVOp) || 4682 X86::isUNPCKHMask(NewSVOp)) 4683 return NewOp; 4684 } 4685 4686 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4687 4688 // Normalize the node to match x86 shuffle ops if needed 4689 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4690 return CommuteVectorShuffle(SVOp, DAG); 4691 4692 // Check for legal shuffle and return? 4693 SmallVector<int, 16> PermMask; 4694 SVOp->getMask(PermMask); 4695 if (isShuffleMaskLegal(PermMask, VT)) 4696 return Op; 4697 4698 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4699 if (VT == MVT::v8i16) { 4700 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4701 if (NewOp.getNode()) 4702 return NewOp; 4703 } 4704 4705 if (VT == MVT::v16i8) { 4706 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4707 if (NewOp.getNode()) 4708 return NewOp; 4709 } 4710 4711 // Handle all 4 wide cases with a number of shuffles except for MMX. 4712 if (NumElems == 4 && !isMMX) 4713 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4714 4715 return SDValue(); 4716} 4717 4718SDValue 4719X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4720 SelectionDAG &DAG) { 4721 EVT VT = Op.getValueType(); 4722 DebugLoc dl = Op.getDebugLoc(); 4723 if (VT.getSizeInBits() == 8) { 4724 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4725 Op.getOperand(0), Op.getOperand(1)); 4726 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4727 DAG.getValueType(VT)); 4728 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4729 } else if (VT.getSizeInBits() == 16) { 4730 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4731 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4732 if (Idx == 0) 4733 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4734 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4735 DAG.getNode(ISD::BIT_CONVERT, dl, 4736 MVT::v4i32, 4737 Op.getOperand(0)), 4738 Op.getOperand(1))); 4739 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4740 Op.getOperand(0), Op.getOperand(1)); 4741 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4742 DAG.getValueType(VT)); 4743 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4744 } else if (VT == MVT::f32) { 4745 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4746 // the result back to FR32 register. It's only worth matching if the 4747 // result has a single use which is a store or a bitcast to i32. And in 4748 // the case of a store, it's not worth it if the index is a constant 0, 4749 // because a MOVSSmr can be used instead, which is smaller and faster. 4750 if (!Op.hasOneUse()) 4751 return SDValue(); 4752 SDNode *User = *Op.getNode()->use_begin(); 4753 if ((User->getOpcode() != ISD::STORE || 4754 (isa<ConstantSDNode>(Op.getOperand(1)) && 4755 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4756 (User->getOpcode() != ISD::BIT_CONVERT || 4757 User->getValueType(0) != MVT::i32)) 4758 return SDValue(); 4759 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4760 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4761 Op.getOperand(0)), 4762 Op.getOperand(1)); 4763 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4764 } else if (VT == MVT::i32) { 4765 // ExtractPS works with constant index. 4766 if (isa<ConstantSDNode>(Op.getOperand(1))) 4767 return Op; 4768 } 4769 return SDValue(); 4770} 4771 4772 4773SDValue 4774X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4775 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4776 return SDValue(); 4777 4778 if (Subtarget->hasSSE41()) { 4779 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4780 if (Res.getNode()) 4781 return Res; 4782 } 4783 4784 EVT VT = Op.getValueType(); 4785 DebugLoc dl = Op.getDebugLoc(); 4786 // TODO: handle v16i8. 4787 if (VT.getSizeInBits() == 16) { 4788 SDValue Vec = Op.getOperand(0); 4789 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4790 if (Idx == 0) 4791 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4792 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4793 DAG.getNode(ISD::BIT_CONVERT, dl, 4794 MVT::v4i32, Vec), 4795 Op.getOperand(1))); 4796 // Transform it so it match pextrw which produces a 32-bit result. 4797 EVT EltVT = MVT::i32; 4798 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 4799 Op.getOperand(0), Op.getOperand(1)); 4800 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 4801 DAG.getValueType(VT)); 4802 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4803 } else if (VT.getSizeInBits() == 32) { 4804 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4805 if (Idx == 0) 4806 return Op; 4807 4808 // SHUFPS the element to the lowest double word, then movss. 4809 int Mask[4] = { Idx, -1, -1, -1 }; 4810 EVT VVT = Op.getOperand(0).getValueType(); 4811 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4812 DAG.getUNDEF(VVT), Mask); 4813 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4814 DAG.getIntPtrConstant(0)); 4815 } else if (VT.getSizeInBits() == 64) { 4816 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4817 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4818 // to match extract_elt for f64. 4819 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4820 if (Idx == 0) 4821 return Op; 4822 4823 // UNPCKHPD the element to the lowest double word, then movsd. 4824 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4825 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4826 int Mask[2] = { 1, -1 }; 4827 EVT VVT = Op.getOperand(0).getValueType(); 4828 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4829 DAG.getUNDEF(VVT), Mask); 4830 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4831 DAG.getIntPtrConstant(0)); 4832 } 4833 4834 return SDValue(); 4835} 4836 4837SDValue 4838X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4839 EVT VT = Op.getValueType(); 4840 EVT EltVT = VT.getVectorElementType(); 4841 DebugLoc dl = Op.getDebugLoc(); 4842 4843 SDValue N0 = Op.getOperand(0); 4844 SDValue N1 = Op.getOperand(1); 4845 SDValue N2 = Op.getOperand(2); 4846 4847 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 4848 isa<ConstantSDNode>(N2)) { 4849 unsigned Opc; 4850 if (VT == MVT::v8i16) 4851 Opc = X86ISD::PINSRW; 4852 else if (VT == MVT::v4i16) 4853 Opc = X86ISD::MMX_PINSRW; 4854 else if (VT == MVT::v16i8) 4855 Opc = X86ISD::PINSRB; 4856 else 4857 Opc = X86ISD::PINSRB; 4858 4859 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4860 // argument. 4861 if (N1.getValueType() != MVT::i32) 4862 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4863 if (N2.getValueType() != MVT::i32) 4864 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4865 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4866 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4867 // Bits [7:6] of the constant are the source select. This will always be 4868 // zero here. The DAG Combiner may combine an extract_elt index into these 4869 // bits. For example (insert (extract, 3), 2) could be matched by putting 4870 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4871 // Bits [5:4] of the constant are the destination select. This is the 4872 // value of the incoming immediate. 4873 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4874 // combine either bitwise AND or insert of float 0.0 to set these bits. 4875 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4876 // Create this as a scalar to vector.. 4877 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 4878 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4879 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 4880 // PINSR* works with constant index. 4881 return Op; 4882 } 4883 return SDValue(); 4884} 4885 4886SDValue 4887X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4888 EVT VT = Op.getValueType(); 4889 EVT EltVT = VT.getVectorElementType(); 4890 4891 if (Subtarget->hasSSE41()) 4892 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4893 4894 if (EltVT == MVT::i8) 4895 return SDValue(); 4896 4897 DebugLoc dl = Op.getDebugLoc(); 4898 SDValue N0 = Op.getOperand(0); 4899 SDValue N1 = Op.getOperand(1); 4900 SDValue N2 = Op.getOperand(2); 4901 4902 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 4903 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4904 // as its second argument. 4905 if (N1.getValueType() != MVT::i32) 4906 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4907 if (N2.getValueType() != MVT::i32) 4908 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4909 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW, 4910 dl, VT, N0, N1, N2); 4911 } 4912 return SDValue(); 4913} 4914 4915SDValue 4916X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4917 DebugLoc dl = Op.getDebugLoc(); 4918 if (Op.getValueType() == MVT::v2f32) 4919 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 4920 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 4921 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 4922 Op.getOperand(0)))); 4923 4924 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) 4925 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 4926 4927 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 4928 EVT VT = MVT::v2i32; 4929 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4930 default: break; 4931 case MVT::v16i8: 4932 case MVT::v8i16: 4933 VT = MVT::v4i32; 4934 break; 4935 } 4936 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 4937 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 4938} 4939 4940// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4941// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4942// one of the above mentioned nodes. It has to be wrapped because otherwise 4943// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4944// be used to form addressing mode. These wrapped nodes will be selected 4945// into MOV32ri. 4946SDValue 4947X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4948 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4949 4950 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4951 // global base reg. 4952 unsigned char OpFlag = 0; 4953 unsigned WrapperKind = X86ISD::Wrapper; 4954 CodeModel::Model M = getTargetMachine().getCodeModel(); 4955 4956 if (Subtarget->isPICStyleRIPRel() && 4957 (M == CodeModel::Small || M == CodeModel::Kernel)) 4958 WrapperKind = X86ISD::WrapperRIP; 4959 else if (Subtarget->isPICStyleGOT()) 4960 OpFlag = X86II::MO_GOTOFF; 4961 else if (Subtarget->isPICStyleStubPIC()) 4962 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4963 4964 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 4965 CP->getAlignment(), 4966 CP->getOffset(), OpFlag); 4967 DebugLoc DL = CP->getDebugLoc(); 4968 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4969 // With PIC, the address is actually $g + Offset. 4970 if (OpFlag) { 4971 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4972 DAG.getNode(X86ISD::GlobalBaseReg, 4973 DebugLoc::getUnknownLoc(), getPointerTy()), 4974 Result); 4975 } 4976 4977 return Result; 4978} 4979 4980SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4981 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4982 4983 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4984 // global base reg. 4985 unsigned char OpFlag = 0; 4986 unsigned WrapperKind = X86ISD::Wrapper; 4987 CodeModel::Model M = getTargetMachine().getCodeModel(); 4988 4989 if (Subtarget->isPICStyleRIPRel() && 4990 (M == CodeModel::Small || M == CodeModel::Kernel)) 4991 WrapperKind = X86ISD::WrapperRIP; 4992 else if (Subtarget->isPICStyleGOT()) 4993 OpFlag = X86II::MO_GOTOFF; 4994 else if (Subtarget->isPICStyleStubPIC()) 4995 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4996 4997 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 4998 OpFlag); 4999 DebugLoc DL = JT->getDebugLoc(); 5000 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5001 5002 // With PIC, the address is actually $g + Offset. 5003 if (OpFlag) { 5004 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5005 DAG.getNode(X86ISD::GlobalBaseReg, 5006 DebugLoc::getUnknownLoc(), getPointerTy()), 5007 Result); 5008 } 5009 5010 return Result; 5011} 5012 5013SDValue 5014X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 5015 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 5016 5017 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5018 // global base reg. 5019 unsigned char OpFlag = 0; 5020 unsigned WrapperKind = X86ISD::Wrapper; 5021 CodeModel::Model M = getTargetMachine().getCodeModel(); 5022 5023 if (Subtarget->isPICStyleRIPRel() && 5024 (M == CodeModel::Small || M == CodeModel::Kernel)) 5025 WrapperKind = X86ISD::WrapperRIP; 5026 else if (Subtarget->isPICStyleGOT()) 5027 OpFlag = X86II::MO_GOTOFF; 5028 else if (Subtarget->isPICStyleStubPIC()) 5029 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5030 5031 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 5032 5033 DebugLoc DL = Op.getDebugLoc(); 5034 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5035 5036 5037 // With PIC, the address is actually $g + Offset. 5038 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 5039 !Subtarget->is64Bit()) { 5040 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5041 DAG.getNode(X86ISD::GlobalBaseReg, 5042 DebugLoc::getUnknownLoc(), 5043 getPointerTy()), 5044 Result); 5045 } 5046 5047 return Result; 5048} 5049 5050SDValue 5051X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { 5052 // Create the TargetBlockAddressAddress node. 5053 unsigned char OpFlags = 5054 Subtarget->ClassifyBlockAddressReference(); 5055 CodeModel::Model M = getTargetMachine().getCodeModel(); 5056 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5057 DebugLoc dl = Op.getDebugLoc(); 5058 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5059 /*isTarget=*/true, OpFlags); 5060 5061 if (Subtarget->isPICStyleRIPRel() && 5062 (M == CodeModel::Small || M == CodeModel::Kernel)) 5063 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5064 else 5065 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5066 5067 // With PIC, the address is actually $g + Offset. 5068 if (isGlobalRelativeToPICBase(OpFlags)) { 5069 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5070 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5071 Result); 5072 } 5073 5074 return Result; 5075} 5076 5077SDValue 5078X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5079 int64_t Offset, 5080 SelectionDAG &DAG) const { 5081 // Create the TargetGlobalAddress node, folding in the constant 5082 // offset if it is legal. 5083 unsigned char OpFlags = 5084 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5085 CodeModel::Model M = getTargetMachine().getCodeModel(); 5086 SDValue Result; 5087 if (OpFlags == X86II::MO_NO_FLAG && 5088 X86::isOffsetSuitableForCodeModel(Offset, M)) { 5089 // A direct static reference to a global. 5090 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 5091 Offset = 0; 5092 } else { 5093 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 5094 } 5095 5096 if (Subtarget->isPICStyleRIPRel() && 5097 (M == CodeModel::Small || M == CodeModel::Kernel)) 5098 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5099 else 5100 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5101 5102 // With PIC, the address is actually $g + Offset. 5103 if (isGlobalRelativeToPICBase(OpFlags)) { 5104 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5105 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5106 Result); 5107 } 5108 5109 // For globals that require a load from a stub to get the address, emit the 5110 // load. 5111 if (isGlobalStubReference(OpFlags)) 5112 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 5113 PseudoSourceValue::getGOT(), 0, false, false, 0); 5114 5115 // If there was a non-zero offset that we didn't fold, create an explicit 5116 // addition for it. 5117 if (Offset != 0) 5118 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 5119 DAG.getConstant(Offset, getPointerTy())); 5120 5121 return Result; 5122} 5123 5124SDValue 5125X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 5126 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 5127 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 5128 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 5129} 5130 5131static SDValue 5132GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 5133 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 5134 unsigned char OperandFlags) { 5135 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5136 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5137 DebugLoc dl = GA->getDebugLoc(); 5138 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 5139 GA->getValueType(0), 5140 GA->getOffset(), 5141 OperandFlags); 5142 if (InFlag) { 5143 SDValue Ops[] = { Chain, TGA, *InFlag }; 5144 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 5145 } else { 5146 SDValue Ops[] = { Chain, TGA }; 5147 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 5148 } 5149 5150 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 5151 MFI->setHasCalls(true); 5152 5153 SDValue Flag = Chain.getValue(1); 5154 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 5155} 5156 5157// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 5158static SDValue 5159LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5160 const EVT PtrVT) { 5161 SDValue InFlag; 5162 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 5163 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 5164 DAG.getNode(X86ISD::GlobalBaseReg, 5165 DebugLoc::getUnknownLoc(), 5166 PtrVT), InFlag); 5167 InFlag = Chain.getValue(1); 5168 5169 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 5170} 5171 5172// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 5173static SDValue 5174LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5175 const EVT PtrVT) { 5176 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 5177 X86::RAX, X86II::MO_TLSGD); 5178} 5179 5180// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 5181// "local exec" model. 5182static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5183 const EVT PtrVT, TLSModel::Model model, 5184 bool is64Bit) { 5185 DebugLoc dl = GA->getDebugLoc(); 5186 // Get the Thread Pointer 5187 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 5188 DebugLoc::getUnknownLoc(), PtrVT, 5189 DAG.getRegister(is64Bit? X86::FS : X86::GS, 5190 MVT::i32)); 5191 5192 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 5193 NULL, 0, false, false, 0); 5194 5195 unsigned char OperandFlags = 0; 5196 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 5197 // initialexec. 5198 unsigned WrapperKind = X86ISD::Wrapper; 5199 if (model == TLSModel::LocalExec) { 5200 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 5201 } else if (is64Bit) { 5202 assert(model == TLSModel::InitialExec); 5203 OperandFlags = X86II::MO_GOTTPOFF; 5204 WrapperKind = X86ISD::WrapperRIP; 5205 } else { 5206 assert(model == TLSModel::InitialExec); 5207 OperandFlags = X86II::MO_INDNTPOFF; 5208 } 5209 5210 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 5211 // exec) 5212 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 5213 GA->getOffset(), OperandFlags); 5214 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 5215 5216 if (model == TLSModel::InitialExec) 5217 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 5218 PseudoSourceValue::getGOT(), 0, false, false, 0); 5219 5220 // The address of the thread local variable is the add of the thread 5221 // pointer with the offset of the variable. 5222 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 5223} 5224 5225SDValue 5226X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 5227 // TODO: implement the "local dynamic" model 5228 // TODO: implement the "initial exec"model for pic executables 5229 assert(Subtarget->isTargetELF() && 5230 "TLS not implemented for non-ELF targets"); 5231 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 5232 const GlobalValue *GV = GA->getGlobal(); 5233 5234 // If GV is an alias then use the aliasee for determining 5235 // thread-localness. 5236 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 5237 GV = GA->resolveAliasedGlobal(false); 5238 5239 TLSModel::Model model = getTLSModel(GV, 5240 getTargetMachine().getRelocationModel()); 5241 5242 switch (model) { 5243 case TLSModel::GeneralDynamic: 5244 case TLSModel::LocalDynamic: // not implemented 5245 if (Subtarget->is64Bit()) 5246 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 5247 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 5248 5249 case TLSModel::InitialExec: 5250 case TLSModel::LocalExec: 5251 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 5252 Subtarget->is64Bit()); 5253 } 5254 5255 llvm_unreachable("Unreachable"); 5256 return SDValue(); 5257} 5258 5259 5260/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 5261/// take a 2 x i32 value to shift plus a shift amount. 5262SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 5263 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 5264 EVT VT = Op.getValueType(); 5265 unsigned VTBits = VT.getSizeInBits(); 5266 DebugLoc dl = Op.getDebugLoc(); 5267 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 5268 SDValue ShOpLo = Op.getOperand(0); 5269 SDValue ShOpHi = Op.getOperand(1); 5270 SDValue ShAmt = Op.getOperand(2); 5271 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 5272 DAG.getConstant(VTBits - 1, MVT::i8)) 5273 : DAG.getConstant(0, VT); 5274 5275 SDValue Tmp2, Tmp3; 5276 if (Op.getOpcode() == ISD::SHL_PARTS) { 5277 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 5278 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 5279 } else { 5280 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 5281 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 5282 } 5283 5284 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 5285 DAG.getConstant(VTBits, MVT::i8)); 5286 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 5287 AndNode, DAG.getConstant(0, MVT::i8)); 5288 5289 SDValue Hi, Lo; 5290 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5291 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 5292 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 5293 5294 if (Op.getOpcode() == ISD::SHL_PARTS) { 5295 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5296 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5297 } else { 5298 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5299 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5300 } 5301 5302 SDValue Ops[2] = { Lo, Hi }; 5303 return DAG.getMergeValues(Ops, 2, dl); 5304} 5305 5306SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5307 EVT SrcVT = Op.getOperand(0).getValueType(); 5308 5309 if (SrcVT.isVector()) { 5310 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 5311 return Op; 5312 } 5313 return SDValue(); 5314 } 5315 5316 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 5317 "Unknown SINT_TO_FP to lower!"); 5318 5319 // These are really Legal; return the operand so the caller accepts it as 5320 // Legal. 5321 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 5322 return Op; 5323 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 5324 Subtarget->is64Bit()) { 5325 return Op; 5326 } 5327 5328 DebugLoc dl = Op.getDebugLoc(); 5329 unsigned Size = SrcVT.getSizeInBits()/8; 5330 MachineFunction &MF = DAG.getMachineFunction(); 5331 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 5332 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5333 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5334 StackSlot, 5335 PseudoSourceValue::getFixedStack(SSFI), 0, 5336 false, false, 0); 5337 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 5338} 5339 5340SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 5341 SDValue StackSlot, 5342 SelectionDAG &DAG) { 5343 // Build the FILD 5344 DebugLoc dl = Op.getDebugLoc(); 5345 SDVTList Tys; 5346 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 5347 if (useSSE) 5348 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 5349 else 5350 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 5351 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 5352 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 5353 Tys, Ops, array_lengthof(Ops)); 5354 5355 if (useSSE) { 5356 Chain = Result.getValue(1); 5357 SDValue InFlag = Result.getValue(2); 5358 5359 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 5360 // shouldn't be necessary except that RFP cannot be live across 5361 // multiple blocks. When stackifier is fixed, they can be uncoupled. 5362 MachineFunction &MF = DAG.getMachineFunction(); 5363 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 5364 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5365 Tys = DAG.getVTList(MVT::Other); 5366 SDValue Ops[] = { 5367 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 5368 }; 5369 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops)); 5370 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 5371 PseudoSourceValue::getFixedStack(SSFI), 0, 5372 false, false, 0); 5373 } 5374 5375 return Result; 5376} 5377 5378// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 5379SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 5380 // This algorithm is not obvious. Here it is in C code, more or less: 5381 /* 5382 double uint64_to_double( uint32_t hi, uint32_t lo ) { 5383 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 5384 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 5385 5386 // Copy ints to xmm registers. 5387 __m128i xh = _mm_cvtsi32_si128( hi ); 5388 __m128i xl = _mm_cvtsi32_si128( lo ); 5389 5390 // Combine into low half of a single xmm register. 5391 __m128i x = _mm_unpacklo_epi32( xh, xl ); 5392 __m128d d; 5393 double sd; 5394 5395 // Merge in appropriate exponents to give the integer bits the right 5396 // magnitude. 5397 x = _mm_unpacklo_epi32( x, exp ); 5398 5399 // Subtract away the biases to deal with the IEEE-754 double precision 5400 // implicit 1. 5401 d = _mm_sub_pd( (__m128d) x, bias ); 5402 5403 // All conversions up to here are exact. The correctly rounded result is 5404 // calculated using the current rounding mode using the following 5405 // horizontal add. 5406 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 5407 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 5408 // store doesn't really need to be here (except 5409 // maybe to zero the other double) 5410 return sd; 5411 } 5412 */ 5413 5414 DebugLoc dl = Op.getDebugLoc(); 5415 LLVMContext *Context = DAG.getContext(); 5416 5417 // Build some magic constants. 5418 std::vector<Constant*> CV0; 5419 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 5420 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 5421 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5422 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5423 Constant *C0 = ConstantVector::get(CV0); 5424 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 5425 5426 std::vector<Constant*> CV1; 5427 CV1.push_back( 5428 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 5429 CV1.push_back( 5430 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 5431 Constant *C1 = ConstantVector::get(CV1); 5432 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 5433 5434 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5435 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5436 Op.getOperand(0), 5437 DAG.getIntPtrConstant(1))); 5438 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5439 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5440 Op.getOperand(0), 5441 DAG.getIntPtrConstant(0))); 5442 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 5443 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 5444 PseudoSourceValue::getConstantPool(), 0, 5445 false, false, 16); 5446 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 5447 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 5448 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 5449 PseudoSourceValue::getConstantPool(), 0, 5450 false, false, 16); 5451 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 5452 5453 // Add the halves; easiest way is to swap them into another reg first. 5454 int ShufMask[2] = { 1, -1 }; 5455 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 5456 DAG.getUNDEF(MVT::v2f64), ShufMask); 5457 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 5458 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 5459 DAG.getIntPtrConstant(0)); 5460} 5461 5462// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 5463SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 5464 DebugLoc dl = Op.getDebugLoc(); 5465 // FP constant to bias correct the final result. 5466 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 5467 MVT::f64); 5468 5469 // Load the 32-bit value into an XMM register. 5470 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5471 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5472 Op.getOperand(0), 5473 DAG.getIntPtrConstant(0))); 5474 5475 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5476 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 5477 DAG.getIntPtrConstant(0)); 5478 5479 // Or the load with the bias. 5480 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 5481 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5482 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5483 MVT::v2f64, Load)), 5484 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5485 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5486 MVT::v2f64, Bias))); 5487 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5488 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 5489 DAG.getIntPtrConstant(0)); 5490 5491 // Subtract the bias. 5492 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5493 5494 // Handle final rounding. 5495 EVT DestVT = Op.getValueType(); 5496 5497 if (DestVT.bitsLT(MVT::f64)) { 5498 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5499 DAG.getIntPtrConstant(0)); 5500 } else if (DestVT.bitsGT(MVT::f64)) { 5501 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5502 } 5503 5504 // Handle final rounding. 5505 return Sub; 5506} 5507 5508SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5509 SDValue N0 = Op.getOperand(0); 5510 DebugLoc dl = Op.getDebugLoc(); 5511 5512 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 5513 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5514 // the optimization here. 5515 if (DAG.SignBitIsZero(N0)) 5516 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5517 5518 EVT SrcVT = N0.getValueType(); 5519 if (SrcVT == MVT::i64) { 5520 // We only handle SSE2 f64 target here; caller can expand the rest. 5521 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 5522 return SDValue(); 5523 5524 return LowerUINT_TO_FP_i64(Op, DAG); 5525 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { 5526 return LowerUINT_TO_FP_i32(Op, DAG); 5527 } 5528 5529 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); 5530 5531 // Make a 64-bit buffer, and use it to build an FILD. 5532 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5533 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5534 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5535 getPointerTy(), StackSlot, WordOff); 5536 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5537 StackSlot, NULL, 0, false, false, 0); 5538 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5539 OffsetSlot, NULL, 0, false, false, 0); 5540 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5541} 5542 5543std::pair<SDValue,SDValue> X86TargetLowering:: 5544FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { 5545 DebugLoc dl = Op.getDebugLoc(); 5546 5547 EVT DstTy = Op.getValueType(); 5548 5549 if (!IsSigned) { 5550 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5551 DstTy = MVT::i64; 5552 } 5553 5554 assert(DstTy.getSimpleVT() <= MVT::i64 && 5555 DstTy.getSimpleVT() >= MVT::i16 && 5556 "Unknown FP_TO_SINT to lower!"); 5557 5558 // These are really Legal. 5559 if (DstTy == MVT::i32 && 5560 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5561 return std::make_pair(SDValue(), SDValue()); 5562 if (Subtarget->is64Bit() && 5563 DstTy == MVT::i64 && 5564 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5565 return std::make_pair(SDValue(), SDValue()); 5566 5567 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5568 // stack slot. 5569 MachineFunction &MF = DAG.getMachineFunction(); 5570 unsigned MemSize = DstTy.getSizeInBits()/8; 5571 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5572 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5573 5574 unsigned Opc; 5575 switch (DstTy.getSimpleVT().SimpleTy) { 5576 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 5577 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5578 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5579 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5580 } 5581 5582 SDValue Chain = DAG.getEntryNode(); 5583 SDValue Value = Op.getOperand(0); 5584 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5585 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5586 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5587 PseudoSourceValue::getFixedStack(SSFI), 0, 5588 false, false, 0); 5589 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5590 SDValue Ops[] = { 5591 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5592 }; 5593 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5594 Chain = Value.getValue(1); 5595 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5596 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5597 } 5598 5599 // Build the FP_TO_INT*_IN_MEM 5600 SDValue Ops[] = { Chain, Value, StackSlot }; 5601 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5602 5603 return std::make_pair(FIST, StackSlot); 5604} 5605 5606SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5607 if (Op.getValueType().isVector()) { 5608 if (Op.getValueType() == MVT::v2i32 && 5609 Op.getOperand(0).getValueType() == MVT::v2f64) { 5610 return Op; 5611 } 5612 return SDValue(); 5613 } 5614 5615 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5616 SDValue FIST = Vals.first, StackSlot = Vals.second; 5617 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5618 if (FIST.getNode() == 0) return Op; 5619 5620 // Load the result. 5621 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5622 FIST, StackSlot, NULL, 0, false, false, 0); 5623} 5624 5625SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { 5626 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5627 SDValue FIST = Vals.first, StackSlot = Vals.second; 5628 assert(FIST.getNode() && "Unexpected failure"); 5629 5630 // Load the result. 5631 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5632 FIST, StackSlot, NULL, 0, false, false, 0); 5633} 5634 5635SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5636 LLVMContext *Context = DAG.getContext(); 5637 DebugLoc dl = Op.getDebugLoc(); 5638 EVT VT = Op.getValueType(); 5639 EVT EltVT = VT; 5640 if (VT.isVector()) 5641 EltVT = VT.getVectorElementType(); 5642 std::vector<Constant*> CV; 5643 if (EltVT == MVT::f64) { 5644 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 5645 CV.push_back(C); 5646 CV.push_back(C); 5647 } else { 5648 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 5649 CV.push_back(C); 5650 CV.push_back(C); 5651 CV.push_back(C); 5652 CV.push_back(C); 5653 } 5654 Constant *C = ConstantVector::get(CV); 5655 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5656 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5657 PseudoSourceValue::getConstantPool(), 0, 5658 false, false, 16); 5659 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5660} 5661 5662SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5663 LLVMContext *Context = DAG.getContext(); 5664 DebugLoc dl = Op.getDebugLoc(); 5665 EVT VT = Op.getValueType(); 5666 EVT EltVT = VT; 5667 if (VT.isVector()) 5668 EltVT = VT.getVectorElementType(); 5669 std::vector<Constant*> CV; 5670 if (EltVT == MVT::f64) { 5671 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 5672 CV.push_back(C); 5673 CV.push_back(C); 5674 } else { 5675 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 5676 CV.push_back(C); 5677 CV.push_back(C); 5678 CV.push_back(C); 5679 CV.push_back(C); 5680 } 5681 Constant *C = ConstantVector::get(CV); 5682 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5683 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5684 PseudoSourceValue::getConstantPool(), 0, 5685 false, false, 16); 5686 if (VT.isVector()) { 5687 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5688 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5689 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5690 Op.getOperand(0)), 5691 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5692 } else { 5693 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5694 } 5695} 5696 5697SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5698 LLVMContext *Context = DAG.getContext(); 5699 SDValue Op0 = Op.getOperand(0); 5700 SDValue Op1 = Op.getOperand(1); 5701 DebugLoc dl = Op.getDebugLoc(); 5702 EVT VT = Op.getValueType(); 5703 EVT SrcVT = Op1.getValueType(); 5704 5705 // If second operand is smaller, extend it first. 5706 if (SrcVT.bitsLT(VT)) { 5707 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5708 SrcVT = VT; 5709 } 5710 // And if it is bigger, shrink it first. 5711 if (SrcVT.bitsGT(VT)) { 5712 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5713 SrcVT = VT; 5714 } 5715 5716 // At this point the operands and the result should have the same 5717 // type, and that won't be f80 since that is not custom lowered. 5718 5719 // First get the sign bit of second operand. 5720 std::vector<Constant*> CV; 5721 if (SrcVT == MVT::f64) { 5722 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 5723 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5724 } else { 5725 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 5726 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5727 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5728 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5729 } 5730 Constant *C = ConstantVector::get(CV); 5731 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5732 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5733 PseudoSourceValue::getConstantPool(), 0, 5734 false, false, 16); 5735 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5736 5737 // Shift sign bit right or left if the two operands have different types. 5738 if (SrcVT.bitsGT(VT)) { 5739 // Op0 is MVT::f32, Op1 is MVT::f64. 5740 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5741 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5742 DAG.getConstant(32, MVT::i32)); 5743 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5744 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5745 DAG.getIntPtrConstant(0)); 5746 } 5747 5748 // Clear first operand sign bit. 5749 CV.clear(); 5750 if (VT == MVT::f64) { 5751 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 5752 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5753 } else { 5754 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 5755 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5756 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5757 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5758 } 5759 C = ConstantVector::get(CV); 5760 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5761 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5762 PseudoSourceValue::getConstantPool(), 0, 5763 false, false, 16); 5764 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5765 5766 // Or the value with the sign bit. 5767 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5768} 5769 5770/// Emit nodes that will be selected as "test Op0,Op0", or something 5771/// equivalent. 5772SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 5773 SelectionDAG &DAG) { 5774 DebugLoc dl = Op.getDebugLoc(); 5775 5776 // CF and OF aren't always set the way we want. Determine which 5777 // of these we need. 5778 bool NeedCF = false; 5779 bool NeedOF = false; 5780 switch (X86CC) { 5781 case X86::COND_A: case X86::COND_AE: 5782 case X86::COND_B: case X86::COND_BE: 5783 NeedCF = true; 5784 break; 5785 case X86::COND_G: case X86::COND_GE: 5786 case X86::COND_L: case X86::COND_LE: 5787 case X86::COND_O: case X86::COND_NO: 5788 NeedOF = true; 5789 break; 5790 default: break; 5791 } 5792 5793 // See if we can use the EFLAGS value from the operand instead of 5794 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 5795 // we prove that the arithmetic won't overflow, we can't use OF or CF. 5796 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) { 5797 unsigned Opcode = 0; 5798 unsigned NumOperands = 0; 5799 switch (Op.getNode()->getOpcode()) { 5800 case ISD::ADD: 5801 // Due to an isel shortcoming, be conservative if this add is likely to 5802 // be selected as part of a load-modify-store instruction. When the root 5803 // node in a match is a store, isel doesn't know how to remap non-chain 5804 // non-flag uses of other nodes in the match, such as the ADD in this 5805 // case. This leads to the ADD being left around and reselected, with 5806 // the result being two adds in the output. 5807 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5808 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5809 if (UI->getOpcode() == ISD::STORE) 5810 goto default_case; 5811 if (ConstantSDNode *C = 5812 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 5813 // An add of one will be selected as an INC. 5814 if (C->getAPIntValue() == 1) { 5815 Opcode = X86ISD::INC; 5816 NumOperands = 1; 5817 break; 5818 } 5819 // An add of negative one (subtract of one) will be selected as a DEC. 5820 if (C->getAPIntValue().isAllOnesValue()) { 5821 Opcode = X86ISD::DEC; 5822 NumOperands = 1; 5823 break; 5824 } 5825 } 5826 // Otherwise use a regular EFLAGS-setting add. 5827 Opcode = X86ISD::ADD; 5828 NumOperands = 2; 5829 break; 5830 case ISD::AND: { 5831 // If the primary and result isn't used, don't bother using X86ISD::AND, 5832 // because a TEST instruction will be better. 5833 bool NonFlagUse = false; 5834 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5835 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 5836 SDNode *User = *UI; 5837 unsigned UOpNo = UI.getOperandNo(); 5838 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 5839 // Look pass truncate. 5840 UOpNo = User->use_begin().getOperandNo(); 5841 User = *User->use_begin(); 5842 } 5843 if (User->getOpcode() != ISD::BRCOND && 5844 User->getOpcode() != ISD::SETCC && 5845 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 5846 NonFlagUse = true; 5847 break; 5848 } 5849 } 5850 if (!NonFlagUse) 5851 break; 5852 } 5853 // FALL THROUGH 5854 case ISD::SUB: 5855 case ISD::OR: 5856 case ISD::XOR: 5857 // Due to the ISEL shortcoming noted above, be conservative if this op is 5858 // likely to be selected as part of a load-modify-store instruction. 5859 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5860 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5861 if (UI->getOpcode() == ISD::STORE) 5862 goto default_case; 5863 // Otherwise use a regular EFLAGS-setting instruction. 5864 switch (Op.getNode()->getOpcode()) { 5865 case ISD::SUB: Opcode = X86ISD::SUB; break; 5866 case ISD::OR: Opcode = X86ISD::OR; break; 5867 case ISD::XOR: Opcode = X86ISD::XOR; break; 5868 case ISD::AND: Opcode = X86ISD::AND; break; 5869 default: llvm_unreachable("unexpected operator!"); 5870 } 5871 NumOperands = 2; 5872 break; 5873 case X86ISD::ADD: 5874 case X86ISD::SUB: 5875 case X86ISD::INC: 5876 case X86ISD::DEC: 5877 case X86ISD::OR: 5878 case X86ISD::XOR: 5879 case X86ISD::AND: 5880 return SDValue(Op.getNode(), 1); 5881 default: 5882 default_case: 5883 break; 5884 } 5885 if (Opcode != 0) { 5886 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 5887 SmallVector<SDValue, 4> Ops; 5888 for (unsigned i = 0; i != NumOperands; ++i) 5889 Ops.push_back(Op.getOperand(i)); 5890 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 5891 DAG.ReplaceAllUsesWith(Op, New); 5892 return SDValue(New.getNode(), 1); 5893 } 5894 } 5895 5896 // Otherwise just emit a CMP with 0, which is the TEST pattern. 5897 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 5898 DAG.getConstant(0, Op.getValueType())); 5899} 5900 5901/// Emit nodes that will be selected as "cmp Op0,Op1", or something 5902/// equivalent. 5903SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 5904 SelectionDAG &DAG) { 5905 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 5906 if (C->getAPIntValue() == 0) 5907 return EmitTest(Op0, X86CC, DAG); 5908 5909 DebugLoc dl = Op0.getDebugLoc(); 5910 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 5911} 5912 5913/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 5914/// if it's possible. 5915static SDValue LowerToBT(SDValue And, ISD::CondCode CC, 5916 DebugLoc dl, SelectionDAG &DAG) { 5917 SDValue Op0 = And.getOperand(0); 5918 SDValue Op1 = And.getOperand(1); 5919 if (Op0.getOpcode() == ISD::TRUNCATE) 5920 Op0 = Op0.getOperand(0); 5921 if (Op1.getOpcode() == ISD::TRUNCATE) 5922 Op1 = Op1.getOperand(0); 5923 5924 SDValue LHS, RHS; 5925 if (Op1.getOpcode() == ISD::SHL) { 5926 if (ConstantSDNode *And10C = dyn_cast<ConstantSDNode>(Op1.getOperand(0))) 5927 if (And10C->getZExtValue() == 1) { 5928 LHS = Op0; 5929 RHS = Op1.getOperand(1); 5930 } 5931 } else if (Op0.getOpcode() == ISD::SHL) { 5932 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 5933 if (And00C->getZExtValue() == 1) { 5934 LHS = Op1; 5935 RHS = Op0.getOperand(1); 5936 } 5937 } else if (Op1.getOpcode() == ISD::Constant) { 5938 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 5939 SDValue AndLHS = Op0; 5940 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 5941 LHS = AndLHS.getOperand(0); 5942 RHS = AndLHS.getOperand(1); 5943 } 5944 } 5945 5946 if (LHS.getNode()) { 5947 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 5948 // instruction. Since the shift amount is in-range-or-undefined, we know 5949 // that doing a bittest on the i16 value is ok. We extend to i32 because 5950 // the encoding for the i16 version is larger than the i32 version. 5951 if (LHS.getValueType() == MVT::i8) 5952 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 5953 5954 // If the operand types disagree, extend the shift amount to match. Since 5955 // BT ignores high bits (like shifts) we can use anyextend. 5956 if (LHS.getValueType() != RHS.getValueType()) 5957 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 5958 5959 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 5960 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 5961 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5962 DAG.getConstant(Cond, MVT::i8), BT); 5963 } 5964 5965 return SDValue(); 5966} 5967 5968SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5969 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5970 SDValue Op0 = Op.getOperand(0); 5971 SDValue Op1 = Op.getOperand(1); 5972 DebugLoc dl = Op.getDebugLoc(); 5973 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5974 5975 // Optimize to BT if possible. 5976 // Lower (X & (1 << N)) == 0 to BT(X, N). 5977 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 5978 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 5979 if (Op0.getOpcode() == ISD::AND && 5980 Op0.hasOneUse() && 5981 Op1.getOpcode() == ISD::Constant && 5982 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 5983 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5984 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 5985 if (NewSetCC.getNode()) 5986 return NewSetCC; 5987 } 5988 5989 // Look for "(setcc) == / != 1" to avoid unncessary setcc. 5990 if (Op0.getOpcode() == X86ISD::SETCC && 5991 Op1.getOpcode() == ISD::Constant && 5992 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 5993 cast<ConstantSDNode>(Op1)->isNullValue()) && 5994 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5995 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 5996 bool Invert = (CC == ISD::SETNE) ^ 5997 cast<ConstantSDNode>(Op1)->isNullValue(); 5998 if (Invert) 5999 CCode = X86::GetOppositeBranchCondition(CCode); 6000 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6001 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 6002 } 6003 6004 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6005 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 6006 if (X86CC == X86::COND_INVALID) 6007 return SDValue(); 6008 6009 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 6010 6011 // Use sbb x, x to materialize carry bit into a GPR. 6012 if (X86CC == X86::COND_B) 6013 return DAG.getNode(ISD::AND, dl, MVT::i8, 6014 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 6015 DAG.getConstant(X86CC, MVT::i8), Cond), 6016 DAG.getConstant(1, MVT::i8)); 6017 6018 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6019 DAG.getConstant(X86CC, MVT::i8), Cond); 6020} 6021 6022SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 6023 SDValue Cond; 6024 SDValue Op0 = Op.getOperand(0); 6025 SDValue Op1 = Op.getOperand(1); 6026 SDValue CC = Op.getOperand(2); 6027 EVT VT = Op.getValueType(); 6028 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 6029 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6030 DebugLoc dl = Op.getDebugLoc(); 6031 6032 if (isFP) { 6033 unsigned SSECC = 8; 6034 EVT VT0 = Op0.getValueType(); 6035 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 6036 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 6037 bool Swap = false; 6038 6039 switch (SetCCOpcode) { 6040 default: break; 6041 case ISD::SETOEQ: 6042 case ISD::SETEQ: SSECC = 0; break; 6043 case ISD::SETOGT: 6044 case ISD::SETGT: Swap = true; // Fallthrough 6045 case ISD::SETLT: 6046 case ISD::SETOLT: SSECC = 1; break; 6047 case ISD::SETOGE: 6048 case ISD::SETGE: Swap = true; // Fallthrough 6049 case ISD::SETLE: 6050 case ISD::SETOLE: SSECC = 2; break; 6051 case ISD::SETUO: SSECC = 3; break; 6052 case ISD::SETUNE: 6053 case ISD::SETNE: SSECC = 4; break; 6054 case ISD::SETULE: Swap = true; 6055 case ISD::SETUGE: SSECC = 5; break; 6056 case ISD::SETULT: Swap = true; 6057 case ISD::SETUGT: SSECC = 6; break; 6058 case ISD::SETO: SSECC = 7; break; 6059 } 6060 if (Swap) 6061 std::swap(Op0, Op1); 6062 6063 // In the two special cases we can't handle, emit two comparisons. 6064 if (SSECC == 8) { 6065 if (SetCCOpcode == ISD::SETUEQ) { 6066 SDValue UNORD, EQ; 6067 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 6068 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 6069 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 6070 } 6071 else if (SetCCOpcode == ISD::SETONE) { 6072 SDValue ORD, NEQ; 6073 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 6074 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 6075 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 6076 } 6077 llvm_unreachable("Illegal FP comparison"); 6078 } 6079 // Handle all other FP comparisons here. 6080 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 6081 } 6082 6083 // We are handling one of the integer comparisons here. Since SSE only has 6084 // GT and EQ comparisons for integer, swapping operands and multiple 6085 // operations may be required for some comparisons. 6086 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 6087 bool Swap = false, Invert = false, FlipSigns = false; 6088 6089 switch (VT.getSimpleVT().SimpleTy) { 6090 default: break; 6091 case MVT::v8i8: 6092 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 6093 case MVT::v4i16: 6094 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 6095 case MVT::v2i32: 6096 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 6097 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 6098 } 6099 6100 switch (SetCCOpcode) { 6101 default: break; 6102 case ISD::SETNE: Invert = true; 6103 case ISD::SETEQ: Opc = EQOpc; break; 6104 case ISD::SETLT: Swap = true; 6105 case ISD::SETGT: Opc = GTOpc; break; 6106 case ISD::SETGE: Swap = true; 6107 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 6108 case ISD::SETULT: Swap = true; 6109 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 6110 case ISD::SETUGE: Swap = true; 6111 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 6112 } 6113 if (Swap) 6114 std::swap(Op0, Op1); 6115 6116 // Since SSE has no unsigned integer comparisons, we need to flip the sign 6117 // bits of the inputs before performing those operations. 6118 if (FlipSigns) { 6119 EVT EltVT = VT.getVectorElementType(); 6120 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 6121 EltVT); 6122 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 6123 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 6124 SignBits.size()); 6125 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 6126 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 6127 } 6128 6129 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 6130 6131 // If the logical-not of the result is required, perform that now. 6132 if (Invert) 6133 Result = DAG.getNOT(dl, Result, VT); 6134 6135 return Result; 6136} 6137 6138// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 6139static bool isX86LogicalCmp(SDValue Op) { 6140 unsigned Opc = Op.getNode()->getOpcode(); 6141 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 6142 return true; 6143 if (Op.getResNo() == 1 && 6144 (Opc == X86ISD::ADD || 6145 Opc == X86ISD::SUB || 6146 Opc == X86ISD::SMUL || 6147 Opc == X86ISD::UMUL || 6148 Opc == X86ISD::INC || 6149 Opc == X86ISD::DEC || 6150 Opc == X86ISD::OR || 6151 Opc == X86ISD::XOR || 6152 Opc == X86ISD::AND)) 6153 return true; 6154 6155 return false; 6156} 6157 6158SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 6159 bool addTest = true; 6160 SDValue Cond = Op.getOperand(0); 6161 DebugLoc dl = Op.getDebugLoc(); 6162 SDValue CC; 6163 6164 if (Cond.getOpcode() == ISD::SETCC) { 6165 SDValue NewCond = LowerSETCC(Cond, DAG); 6166 if (NewCond.getNode()) 6167 Cond = NewCond; 6168 } 6169 6170 // (select (x == 0), -1, 0) -> (sign_bit (x - 1)) 6171 SDValue Op1 = Op.getOperand(1); 6172 SDValue Op2 = Op.getOperand(2); 6173 if (Cond.getOpcode() == X86ISD::SETCC && 6174 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) { 6175 SDValue Cmp = Cond.getOperand(1); 6176 if (Cmp.getOpcode() == X86ISD::CMP) { 6177 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1); 6178 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 6179 ConstantSDNode *RHSC = 6180 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode()); 6181 if (N1C && N1C->isAllOnesValue() && 6182 N2C && N2C->isNullValue() && 6183 RHSC && RHSC->isNullValue()) { 6184 SDValue CmpOp0 = Cmp.getOperand(0); 6185 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 6186 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 6187 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(), 6188 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 6189 } 6190 } 6191 } 6192 6193 // Look pass (and (setcc_carry (cmp ...)), 1). 6194 if (Cond.getOpcode() == ISD::AND && 6195 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6196 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6197 if (C && C->getAPIntValue() == 1) 6198 Cond = Cond.getOperand(0); 6199 } 6200 6201 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6202 // setting operand in place of the X86ISD::SETCC. 6203 if (Cond.getOpcode() == X86ISD::SETCC || 6204 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6205 CC = Cond.getOperand(0); 6206 6207 SDValue Cmp = Cond.getOperand(1); 6208 unsigned Opc = Cmp.getOpcode(); 6209 EVT VT = Op.getValueType(); 6210 6211 bool IllegalFPCMov = false; 6212 if (VT.isFloatingPoint() && !VT.isVector() && 6213 !isScalarFPTypeInSSEReg(VT)) // FPStack? 6214 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 6215 6216 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 6217 Opc == X86ISD::BT) { // FIXME 6218 Cond = Cmp; 6219 addTest = false; 6220 } 6221 } 6222 6223 if (addTest) { 6224 // Look pass the truncate. 6225 if (Cond.getOpcode() == ISD::TRUNCATE) 6226 Cond = Cond.getOperand(0); 6227 6228 // We know the result of AND is compared against zero. Try to match 6229 // it to BT. 6230 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6231 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6232 if (NewSetCC.getNode()) { 6233 CC = NewSetCC.getOperand(0); 6234 Cond = NewSetCC.getOperand(1); 6235 addTest = false; 6236 } 6237 } 6238 } 6239 6240 if (addTest) { 6241 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6242 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6243 } 6244 6245 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 6246 // condition is true. 6247 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 6248 SDValue Ops[] = { Op2, Op1, CC, Cond }; 6249 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops)); 6250} 6251 6252// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 6253// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 6254// from the AND / OR. 6255static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 6256 Opc = Op.getOpcode(); 6257 if (Opc != ISD::OR && Opc != ISD::AND) 6258 return false; 6259 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6260 Op.getOperand(0).hasOneUse() && 6261 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 6262 Op.getOperand(1).hasOneUse()); 6263} 6264 6265// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 6266// 1 and that the SETCC node has a single use. 6267static bool isXor1OfSetCC(SDValue Op) { 6268 if (Op.getOpcode() != ISD::XOR) 6269 return false; 6270 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6271 if (N1C && N1C->getAPIntValue() == 1) { 6272 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6273 Op.getOperand(0).hasOneUse(); 6274 } 6275 return false; 6276} 6277 6278SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 6279 bool addTest = true; 6280 SDValue Chain = Op.getOperand(0); 6281 SDValue Cond = Op.getOperand(1); 6282 SDValue Dest = Op.getOperand(2); 6283 DebugLoc dl = Op.getDebugLoc(); 6284 SDValue CC; 6285 6286 if (Cond.getOpcode() == ISD::SETCC) { 6287 SDValue NewCond = LowerSETCC(Cond, DAG); 6288 if (NewCond.getNode()) 6289 Cond = NewCond; 6290 } 6291#if 0 6292 // FIXME: LowerXALUO doesn't handle these!! 6293 else if (Cond.getOpcode() == X86ISD::ADD || 6294 Cond.getOpcode() == X86ISD::SUB || 6295 Cond.getOpcode() == X86ISD::SMUL || 6296 Cond.getOpcode() == X86ISD::UMUL) 6297 Cond = LowerXALUO(Cond, DAG); 6298#endif 6299 6300 // Look pass (and (setcc_carry (cmp ...)), 1). 6301 if (Cond.getOpcode() == ISD::AND && 6302 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6303 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6304 if (C && C->getAPIntValue() == 1) 6305 Cond = Cond.getOperand(0); 6306 } 6307 6308 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6309 // setting operand in place of the X86ISD::SETCC. 6310 if (Cond.getOpcode() == X86ISD::SETCC || 6311 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6312 CC = Cond.getOperand(0); 6313 6314 SDValue Cmp = Cond.getOperand(1); 6315 unsigned Opc = Cmp.getOpcode(); 6316 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 6317 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 6318 Cond = Cmp; 6319 addTest = false; 6320 } else { 6321 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 6322 default: break; 6323 case X86::COND_O: 6324 case X86::COND_B: 6325 // These can only come from an arithmetic instruction with overflow, 6326 // e.g. SADDO, UADDO. 6327 Cond = Cond.getNode()->getOperand(1); 6328 addTest = false; 6329 break; 6330 } 6331 } 6332 } else { 6333 unsigned CondOpc; 6334 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 6335 SDValue Cmp = Cond.getOperand(0).getOperand(1); 6336 if (CondOpc == ISD::OR) { 6337 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 6338 // two branches instead of an explicit OR instruction with a 6339 // separate test. 6340 if (Cmp == Cond.getOperand(1).getOperand(1) && 6341 isX86LogicalCmp(Cmp)) { 6342 CC = Cond.getOperand(0).getOperand(0); 6343 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6344 Chain, Dest, CC, Cmp); 6345 CC = Cond.getOperand(1).getOperand(0); 6346 Cond = Cmp; 6347 addTest = false; 6348 } 6349 } else { // ISD::AND 6350 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 6351 // two branches instead of an explicit AND instruction with a 6352 // separate test. However, we only do this if this block doesn't 6353 // have a fall-through edge, because this requires an explicit 6354 // jmp when the condition is false. 6355 if (Cmp == Cond.getOperand(1).getOperand(1) && 6356 isX86LogicalCmp(Cmp) && 6357 Op.getNode()->hasOneUse()) { 6358 X86::CondCode CCode = 6359 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6360 CCode = X86::GetOppositeBranchCondition(CCode); 6361 CC = DAG.getConstant(CCode, MVT::i8); 6362 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 6363 // Look for an unconditional branch following this conditional branch. 6364 // We need this because we need to reverse the successors in order 6365 // to implement FCMP_OEQ. 6366 if (User.getOpcode() == ISD::BR) { 6367 SDValue FalseBB = User.getOperand(1); 6368 SDValue NewBR = 6369 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 6370 assert(NewBR == User); 6371 Dest = FalseBB; 6372 6373 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6374 Chain, Dest, CC, Cmp); 6375 X86::CondCode CCode = 6376 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 6377 CCode = X86::GetOppositeBranchCondition(CCode); 6378 CC = DAG.getConstant(CCode, MVT::i8); 6379 Cond = Cmp; 6380 addTest = false; 6381 } 6382 } 6383 } 6384 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 6385 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 6386 // It should be transformed during dag combiner except when the condition 6387 // is set by a arithmetics with overflow node. 6388 X86::CondCode CCode = 6389 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6390 CCode = X86::GetOppositeBranchCondition(CCode); 6391 CC = DAG.getConstant(CCode, MVT::i8); 6392 Cond = Cond.getOperand(0).getOperand(1); 6393 addTest = false; 6394 } 6395 } 6396 6397 if (addTest) { 6398 // Look pass the truncate. 6399 if (Cond.getOpcode() == ISD::TRUNCATE) 6400 Cond = Cond.getOperand(0); 6401 6402 // We know the result of AND is compared against zero. Try to match 6403 // it to BT. 6404 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6405 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6406 if (NewSetCC.getNode()) { 6407 CC = NewSetCC.getOperand(0); 6408 Cond = NewSetCC.getOperand(1); 6409 addTest = false; 6410 } 6411 } 6412 } 6413 6414 if (addTest) { 6415 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6416 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6417 } 6418 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6419 Chain, Dest, CC, Cond); 6420} 6421 6422 6423// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 6424// Calls to _alloca is needed to probe the stack when allocating more than 4k 6425// bytes in one go. Touching the stack at 4K increments is necessary to ensure 6426// that the guard pages used by the OS virtual memory manager are allocated in 6427// correct sequence. 6428SDValue 6429X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 6430 SelectionDAG &DAG) { 6431 assert(Subtarget->isTargetCygMing() && 6432 "This should be used only on Cygwin/Mingw targets"); 6433 DebugLoc dl = Op.getDebugLoc(); 6434 6435 // Get the inputs. 6436 SDValue Chain = Op.getOperand(0); 6437 SDValue Size = Op.getOperand(1); 6438 // FIXME: Ensure alignment here 6439 6440 SDValue Flag; 6441 6442 EVT IntPtr = getPointerTy(); 6443 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 6444 6445 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 6446 Flag = Chain.getValue(1); 6447 6448 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 6449 6450 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag); 6451 Flag = Chain.getValue(1); 6452 6453 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 6454 6455 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 6456 return DAG.getMergeValues(Ops1, 2, dl); 6457} 6458 6459SDValue 6460X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 6461 SDValue Chain, 6462 SDValue Dst, SDValue Src, 6463 SDValue Size, unsigned Align, 6464 const Value *DstSV, 6465 uint64_t DstSVOff) { 6466 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6467 6468 // If not DWORD aligned or size is more than the threshold, call the library. 6469 // The libc version is likely to be faster for these cases. It can use the 6470 // address value and run time information about the CPU. 6471 if ((Align & 3) != 0 || 6472 !ConstantSize || 6473 ConstantSize->getZExtValue() > 6474 getSubtarget()->getMaxInlineSizeThreshold()) { 6475 SDValue InFlag(0, 0); 6476 6477 // Check to see if there is a specialized entry-point for memory zeroing. 6478 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 6479 6480 if (const char *bzeroEntry = V && 6481 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 6482 EVT IntPtr = getPointerTy(); 6483 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext()); 6484 TargetLowering::ArgListTy Args; 6485 TargetLowering::ArgListEntry Entry; 6486 Entry.Node = Dst; 6487 Entry.Ty = IntPtrTy; 6488 Args.push_back(Entry); 6489 Entry.Node = Size; 6490 Args.push_back(Entry); 6491 std::pair<SDValue,SDValue> CallResult = 6492 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), 6493 false, false, false, false, 6494 0, CallingConv::C, false, /*isReturnValueUsed=*/false, 6495 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); 6496 return CallResult.second; 6497 } 6498 6499 // Otherwise have the target-independent code call memset. 6500 return SDValue(); 6501 } 6502 6503 uint64_t SizeVal = ConstantSize->getZExtValue(); 6504 SDValue InFlag(0, 0); 6505 EVT AVT; 6506 SDValue Count; 6507 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 6508 unsigned BytesLeft = 0; 6509 bool TwoRepStos = false; 6510 if (ValC) { 6511 unsigned ValReg; 6512 uint64_t Val = ValC->getZExtValue() & 255; 6513 6514 // If the value is a constant, then we can potentially use larger sets. 6515 switch (Align & 3) { 6516 case 2: // WORD aligned 6517 AVT = MVT::i16; 6518 ValReg = X86::AX; 6519 Val = (Val << 8) | Val; 6520 break; 6521 case 0: // DWORD aligned 6522 AVT = MVT::i32; 6523 ValReg = X86::EAX; 6524 Val = (Val << 8) | Val; 6525 Val = (Val << 16) | Val; 6526 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 6527 AVT = MVT::i64; 6528 ValReg = X86::RAX; 6529 Val = (Val << 32) | Val; 6530 } 6531 break; 6532 default: // Byte aligned 6533 AVT = MVT::i8; 6534 ValReg = X86::AL; 6535 Count = DAG.getIntPtrConstant(SizeVal); 6536 break; 6537 } 6538 6539 if (AVT.bitsGT(MVT::i8)) { 6540 unsigned UBytes = AVT.getSizeInBits() / 8; 6541 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 6542 BytesLeft = SizeVal % UBytes; 6543 } 6544 6545 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 6546 InFlag); 6547 InFlag = Chain.getValue(1); 6548 } else { 6549 AVT = MVT::i8; 6550 Count = DAG.getIntPtrConstant(SizeVal); 6551 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 6552 InFlag = Chain.getValue(1); 6553 } 6554 6555 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6556 X86::ECX, 6557 Count, InFlag); 6558 InFlag = Chain.getValue(1); 6559 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6560 X86::EDI, 6561 Dst, InFlag); 6562 InFlag = Chain.getValue(1); 6563 6564 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6565 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6566 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6567 6568 if (TwoRepStos) { 6569 InFlag = Chain.getValue(1); 6570 Count = Size; 6571 EVT CVT = Count.getValueType(); 6572 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 6573 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 6574 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 6575 X86::ECX, 6576 Left, InFlag); 6577 InFlag = Chain.getValue(1); 6578 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6579 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag }; 6580 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6581 } else if (BytesLeft) { 6582 // Handle the last 1 - 7 bytes. 6583 unsigned Offset = SizeVal - BytesLeft; 6584 EVT AddrVT = Dst.getValueType(); 6585 EVT SizeVT = Size.getValueType(); 6586 6587 Chain = DAG.getMemset(Chain, dl, 6588 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 6589 DAG.getConstant(Offset, AddrVT)), 6590 Src, 6591 DAG.getConstant(BytesLeft, SizeVT), 6592 Align, DstSV, DstSVOff + Offset); 6593 } 6594 6595 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 6596 return Chain; 6597} 6598 6599SDValue 6600X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 6601 SDValue Chain, SDValue Dst, SDValue Src, 6602 SDValue Size, unsigned Align, 6603 bool AlwaysInline, 6604 const Value *DstSV, uint64_t DstSVOff, 6605 const Value *SrcSV, uint64_t SrcSVOff) { 6606 // This requires the copy size to be a constant, preferrably 6607 // within a subtarget-specific limit. 6608 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6609 if (!ConstantSize) 6610 return SDValue(); 6611 uint64_t SizeVal = ConstantSize->getZExtValue(); 6612 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 6613 return SDValue(); 6614 6615 /// If not DWORD aligned, call the library. 6616 if ((Align & 3) != 0) 6617 return SDValue(); 6618 6619 // DWORD aligned 6620 EVT AVT = MVT::i32; 6621 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 6622 AVT = MVT::i64; 6623 6624 unsigned UBytes = AVT.getSizeInBits() / 8; 6625 unsigned CountVal = SizeVal / UBytes; 6626 SDValue Count = DAG.getIntPtrConstant(CountVal); 6627 unsigned BytesLeft = SizeVal % UBytes; 6628 6629 SDValue InFlag(0, 0); 6630 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6631 X86::ECX, 6632 Count, InFlag); 6633 InFlag = Chain.getValue(1); 6634 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6635 X86::EDI, 6636 Dst, InFlag); 6637 InFlag = Chain.getValue(1); 6638 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 6639 X86::ESI, 6640 Src, InFlag); 6641 InFlag = Chain.getValue(1); 6642 6643 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6644 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6645 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops, 6646 array_lengthof(Ops)); 6647 6648 SmallVector<SDValue, 4> Results; 6649 Results.push_back(RepMovs); 6650 if (BytesLeft) { 6651 // Handle the last 1 - 7 bytes. 6652 unsigned Offset = SizeVal - BytesLeft; 6653 EVT DstVT = Dst.getValueType(); 6654 EVT SrcVT = Src.getValueType(); 6655 EVT SizeVT = Size.getValueType(); 6656 Results.push_back(DAG.getMemcpy(Chain, dl, 6657 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 6658 DAG.getConstant(Offset, DstVT)), 6659 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 6660 DAG.getConstant(Offset, SrcVT)), 6661 DAG.getConstant(BytesLeft, SizeVT), 6662 Align, AlwaysInline, 6663 DstSV, DstSVOff + Offset, 6664 SrcSV, SrcSVOff + Offset)); 6665 } 6666 6667 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6668 &Results[0], Results.size()); 6669} 6670 6671SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6672 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6673 DebugLoc dl = Op.getDebugLoc(); 6674 6675 if (!Subtarget->is64Bit()) { 6676 // vastart just stores the address of the VarArgsFrameIndex slot into the 6677 // memory location argument. 6678 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6679 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 6680 false, false, 0); 6681 } 6682 6683 // __va_list_tag: 6684 // gp_offset (0 - 6 * 8) 6685 // fp_offset (48 - 48 + 8 * 16) 6686 // overflow_arg_area (point to parameters coming in memory). 6687 // reg_save_area 6688 SmallVector<SDValue, 8> MemOps; 6689 SDValue FIN = Op.getOperand(1); 6690 // Store gp_offset 6691 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6692 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6693 FIN, SV, 0, false, false, 0); 6694 MemOps.push_back(Store); 6695 6696 // Store fp_offset 6697 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6698 FIN, DAG.getIntPtrConstant(4)); 6699 Store = DAG.getStore(Op.getOperand(0), dl, 6700 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6701 FIN, SV, 0, false, false, 0); 6702 MemOps.push_back(Store); 6703 6704 // Store ptr to overflow_arg_area 6705 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6706 FIN, DAG.getIntPtrConstant(4)); 6707 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6708 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0, 6709 false, false, 0); 6710 MemOps.push_back(Store); 6711 6712 // Store ptr to reg_save_area. 6713 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6714 FIN, DAG.getIntPtrConstant(8)); 6715 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6716 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0, 6717 false, false, 0); 6718 MemOps.push_back(Store); 6719 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6720 &MemOps[0], MemOps.size()); 6721} 6722 6723SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6724 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6725 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6726 SDValue Chain = Op.getOperand(0); 6727 SDValue SrcPtr = Op.getOperand(1); 6728 SDValue SrcSV = Op.getOperand(2); 6729 6730 llvm_report_error("VAArgInst is not yet implemented for x86-64!"); 6731 return SDValue(); 6732} 6733 6734SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6735 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6736 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6737 SDValue Chain = Op.getOperand(0); 6738 SDValue DstPtr = Op.getOperand(1); 6739 SDValue SrcPtr = Op.getOperand(2); 6740 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6741 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6742 DebugLoc dl = Op.getDebugLoc(); 6743 6744 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6745 DAG.getIntPtrConstant(24), 8, false, 6746 DstSV, 0, SrcSV, 0); 6747} 6748 6749SDValue 6750X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6751 DebugLoc dl = Op.getDebugLoc(); 6752 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6753 switch (IntNo) { 6754 default: return SDValue(); // Don't custom lower most intrinsics. 6755 // Comparison intrinsics. 6756 case Intrinsic::x86_sse_comieq_ss: 6757 case Intrinsic::x86_sse_comilt_ss: 6758 case Intrinsic::x86_sse_comile_ss: 6759 case Intrinsic::x86_sse_comigt_ss: 6760 case Intrinsic::x86_sse_comige_ss: 6761 case Intrinsic::x86_sse_comineq_ss: 6762 case Intrinsic::x86_sse_ucomieq_ss: 6763 case Intrinsic::x86_sse_ucomilt_ss: 6764 case Intrinsic::x86_sse_ucomile_ss: 6765 case Intrinsic::x86_sse_ucomigt_ss: 6766 case Intrinsic::x86_sse_ucomige_ss: 6767 case Intrinsic::x86_sse_ucomineq_ss: 6768 case Intrinsic::x86_sse2_comieq_sd: 6769 case Intrinsic::x86_sse2_comilt_sd: 6770 case Intrinsic::x86_sse2_comile_sd: 6771 case Intrinsic::x86_sse2_comigt_sd: 6772 case Intrinsic::x86_sse2_comige_sd: 6773 case Intrinsic::x86_sse2_comineq_sd: 6774 case Intrinsic::x86_sse2_ucomieq_sd: 6775 case Intrinsic::x86_sse2_ucomilt_sd: 6776 case Intrinsic::x86_sse2_ucomile_sd: 6777 case Intrinsic::x86_sse2_ucomigt_sd: 6778 case Intrinsic::x86_sse2_ucomige_sd: 6779 case Intrinsic::x86_sse2_ucomineq_sd: { 6780 unsigned Opc = 0; 6781 ISD::CondCode CC = ISD::SETCC_INVALID; 6782 switch (IntNo) { 6783 default: break; 6784 case Intrinsic::x86_sse_comieq_ss: 6785 case Intrinsic::x86_sse2_comieq_sd: 6786 Opc = X86ISD::COMI; 6787 CC = ISD::SETEQ; 6788 break; 6789 case Intrinsic::x86_sse_comilt_ss: 6790 case Intrinsic::x86_sse2_comilt_sd: 6791 Opc = X86ISD::COMI; 6792 CC = ISD::SETLT; 6793 break; 6794 case Intrinsic::x86_sse_comile_ss: 6795 case Intrinsic::x86_sse2_comile_sd: 6796 Opc = X86ISD::COMI; 6797 CC = ISD::SETLE; 6798 break; 6799 case Intrinsic::x86_sse_comigt_ss: 6800 case Intrinsic::x86_sse2_comigt_sd: 6801 Opc = X86ISD::COMI; 6802 CC = ISD::SETGT; 6803 break; 6804 case Intrinsic::x86_sse_comige_ss: 6805 case Intrinsic::x86_sse2_comige_sd: 6806 Opc = X86ISD::COMI; 6807 CC = ISD::SETGE; 6808 break; 6809 case Intrinsic::x86_sse_comineq_ss: 6810 case Intrinsic::x86_sse2_comineq_sd: 6811 Opc = X86ISD::COMI; 6812 CC = ISD::SETNE; 6813 break; 6814 case Intrinsic::x86_sse_ucomieq_ss: 6815 case Intrinsic::x86_sse2_ucomieq_sd: 6816 Opc = X86ISD::UCOMI; 6817 CC = ISD::SETEQ; 6818 break; 6819 case Intrinsic::x86_sse_ucomilt_ss: 6820 case Intrinsic::x86_sse2_ucomilt_sd: 6821 Opc = X86ISD::UCOMI; 6822 CC = ISD::SETLT; 6823 break; 6824 case Intrinsic::x86_sse_ucomile_ss: 6825 case Intrinsic::x86_sse2_ucomile_sd: 6826 Opc = X86ISD::UCOMI; 6827 CC = ISD::SETLE; 6828 break; 6829 case Intrinsic::x86_sse_ucomigt_ss: 6830 case Intrinsic::x86_sse2_ucomigt_sd: 6831 Opc = X86ISD::UCOMI; 6832 CC = ISD::SETGT; 6833 break; 6834 case Intrinsic::x86_sse_ucomige_ss: 6835 case Intrinsic::x86_sse2_ucomige_sd: 6836 Opc = X86ISD::UCOMI; 6837 CC = ISD::SETGE; 6838 break; 6839 case Intrinsic::x86_sse_ucomineq_ss: 6840 case Intrinsic::x86_sse2_ucomineq_sd: 6841 Opc = X86ISD::UCOMI; 6842 CC = ISD::SETNE; 6843 break; 6844 } 6845 6846 SDValue LHS = Op.getOperand(1); 6847 SDValue RHS = Op.getOperand(2); 6848 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6849 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 6850 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6851 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6852 DAG.getConstant(X86CC, MVT::i8), Cond); 6853 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6854 } 6855 // ptest intrinsics. The intrinsic these come from are designed to return 6856 // an integer value, not just an instruction so lower it to the ptest 6857 // pattern and a setcc for the result. 6858 case Intrinsic::x86_sse41_ptestz: 6859 case Intrinsic::x86_sse41_ptestc: 6860 case Intrinsic::x86_sse41_ptestnzc:{ 6861 unsigned X86CC = 0; 6862 switch (IntNo) { 6863 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 6864 case Intrinsic::x86_sse41_ptestz: 6865 // ZF = 1 6866 X86CC = X86::COND_E; 6867 break; 6868 case Intrinsic::x86_sse41_ptestc: 6869 // CF = 1 6870 X86CC = X86::COND_B; 6871 break; 6872 case Intrinsic::x86_sse41_ptestnzc: 6873 // ZF and CF = 0 6874 X86CC = X86::COND_A; 6875 break; 6876 } 6877 6878 SDValue LHS = Op.getOperand(1); 6879 SDValue RHS = Op.getOperand(2); 6880 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); 6881 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 6882 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 6883 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6884 } 6885 6886 // Fix vector shift instructions where the last operand is a non-immediate 6887 // i32 value. 6888 case Intrinsic::x86_sse2_pslli_w: 6889 case Intrinsic::x86_sse2_pslli_d: 6890 case Intrinsic::x86_sse2_pslli_q: 6891 case Intrinsic::x86_sse2_psrli_w: 6892 case Intrinsic::x86_sse2_psrli_d: 6893 case Intrinsic::x86_sse2_psrli_q: 6894 case Intrinsic::x86_sse2_psrai_w: 6895 case Intrinsic::x86_sse2_psrai_d: 6896 case Intrinsic::x86_mmx_pslli_w: 6897 case Intrinsic::x86_mmx_pslli_d: 6898 case Intrinsic::x86_mmx_pslli_q: 6899 case Intrinsic::x86_mmx_psrli_w: 6900 case Intrinsic::x86_mmx_psrli_d: 6901 case Intrinsic::x86_mmx_psrli_q: 6902 case Intrinsic::x86_mmx_psrai_w: 6903 case Intrinsic::x86_mmx_psrai_d: { 6904 SDValue ShAmt = Op.getOperand(2); 6905 if (isa<ConstantSDNode>(ShAmt)) 6906 return SDValue(); 6907 6908 unsigned NewIntNo = 0; 6909 EVT ShAmtVT = MVT::v4i32; 6910 switch (IntNo) { 6911 case Intrinsic::x86_sse2_pslli_w: 6912 NewIntNo = Intrinsic::x86_sse2_psll_w; 6913 break; 6914 case Intrinsic::x86_sse2_pslli_d: 6915 NewIntNo = Intrinsic::x86_sse2_psll_d; 6916 break; 6917 case Intrinsic::x86_sse2_pslli_q: 6918 NewIntNo = Intrinsic::x86_sse2_psll_q; 6919 break; 6920 case Intrinsic::x86_sse2_psrli_w: 6921 NewIntNo = Intrinsic::x86_sse2_psrl_w; 6922 break; 6923 case Intrinsic::x86_sse2_psrli_d: 6924 NewIntNo = Intrinsic::x86_sse2_psrl_d; 6925 break; 6926 case Intrinsic::x86_sse2_psrli_q: 6927 NewIntNo = Intrinsic::x86_sse2_psrl_q; 6928 break; 6929 case Intrinsic::x86_sse2_psrai_w: 6930 NewIntNo = Intrinsic::x86_sse2_psra_w; 6931 break; 6932 case Intrinsic::x86_sse2_psrai_d: 6933 NewIntNo = Intrinsic::x86_sse2_psra_d; 6934 break; 6935 default: { 6936 ShAmtVT = MVT::v2i32; 6937 switch (IntNo) { 6938 case Intrinsic::x86_mmx_pslli_w: 6939 NewIntNo = Intrinsic::x86_mmx_psll_w; 6940 break; 6941 case Intrinsic::x86_mmx_pslli_d: 6942 NewIntNo = Intrinsic::x86_mmx_psll_d; 6943 break; 6944 case Intrinsic::x86_mmx_pslli_q: 6945 NewIntNo = Intrinsic::x86_mmx_psll_q; 6946 break; 6947 case Intrinsic::x86_mmx_psrli_w: 6948 NewIntNo = Intrinsic::x86_mmx_psrl_w; 6949 break; 6950 case Intrinsic::x86_mmx_psrli_d: 6951 NewIntNo = Intrinsic::x86_mmx_psrl_d; 6952 break; 6953 case Intrinsic::x86_mmx_psrli_q: 6954 NewIntNo = Intrinsic::x86_mmx_psrl_q; 6955 break; 6956 case Intrinsic::x86_mmx_psrai_w: 6957 NewIntNo = Intrinsic::x86_mmx_psra_w; 6958 break; 6959 case Intrinsic::x86_mmx_psrai_d: 6960 NewIntNo = Intrinsic::x86_mmx_psra_d; 6961 break; 6962 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 6963 } 6964 break; 6965 } 6966 } 6967 6968 // The vector shift intrinsics with scalars uses 32b shift amounts but 6969 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 6970 // to be zero. 6971 SDValue ShOps[4]; 6972 ShOps[0] = ShAmt; 6973 ShOps[1] = DAG.getConstant(0, MVT::i32); 6974 if (ShAmtVT == MVT::v4i32) { 6975 ShOps[2] = DAG.getUNDEF(MVT::i32); 6976 ShOps[3] = DAG.getUNDEF(MVT::i32); 6977 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 6978 } else { 6979 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 6980 } 6981 6982 EVT VT = Op.getValueType(); 6983 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 6984 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6985 DAG.getConstant(NewIntNo, MVT::i32), 6986 Op.getOperand(1), ShAmt); 6987 } 6988 } 6989} 6990 6991SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 6992 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6993 DebugLoc dl = Op.getDebugLoc(); 6994 6995 if (Depth > 0) { 6996 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6997 SDValue Offset = 6998 DAG.getConstant(TD->getPointerSize(), 6999 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 7000 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7001 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7002 FrameAddr, Offset), 7003 NULL, 0, false, false, 0); 7004 } 7005 7006 // Just load the return address. 7007 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 7008 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7009 RetAddrFI, NULL, 0, false, false, 0); 7010} 7011 7012SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 7013 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7014 MFI->setFrameAddressIsTaken(true); 7015 EVT VT = Op.getValueType(); 7016 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 7017 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7018 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 7019 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 7020 while (Depth--) 7021 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 7022 false, false, 0); 7023 return FrameAddr; 7024} 7025 7026SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 7027 SelectionDAG &DAG) { 7028 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 7029} 7030 7031SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 7032{ 7033 MachineFunction &MF = DAG.getMachineFunction(); 7034 SDValue Chain = Op.getOperand(0); 7035 SDValue Offset = Op.getOperand(1); 7036 SDValue Handler = Op.getOperand(2); 7037 DebugLoc dl = Op.getDebugLoc(); 7038 7039 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 7040 getPointerTy()); 7041 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 7042 7043 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 7044 DAG.getIntPtrConstant(-TD->getPointerSize())); 7045 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 7046 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0); 7047 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 7048 MF.getRegInfo().addLiveOut(StoreAddrReg); 7049 7050 return DAG.getNode(X86ISD::EH_RETURN, dl, 7051 MVT::Other, 7052 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 7053} 7054 7055SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 7056 SelectionDAG &DAG) { 7057 SDValue Root = Op.getOperand(0); 7058 SDValue Trmp = Op.getOperand(1); // trampoline 7059 SDValue FPtr = Op.getOperand(2); // nested function 7060 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 7061 DebugLoc dl = Op.getDebugLoc(); 7062 7063 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7064 7065 if (Subtarget->is64Bit()) { 7066 SDValue OutChains[6]; 7067 7068 // Large code-model. 7069 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 7070 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 7071 7072 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 7073 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 7074 7075 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 7076 7077 // Load the pointer to the nested function into R11. 7078 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 7079 SDValue Addr = Trmp; 7080 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7081 Addr, TrmpAddr, 0, false, false, 0); 7082 7083 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7084 DAG.getConstant(2, MVT::i64)); 7085 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, 7086 false, false, 2); 7087 7088 // Load the 'nest' parameter value into R10. 7089 // R10 is specified in X86CallingConv.td 7090 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 7091 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7092 DAG.getConstant(10, MVT::i64)); 7093 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7094 Addr, TrmpAddr, 10, false, false, 0); 7095 7096 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7097 DAG.getConstant(12, MVT::i64)); 7098 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, 7099 false, false, 2); 7100 7101 // Jump to the nested function. 7102 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 7103 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7104 DAG.getConstant(20, MVT::i64)); 7105 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7106 Addr, TrmpAddr, 20, false, false, 0); 7107 7108 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 7109 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7110 DAG.getConstant(22, MVT::i64)); 7111 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 7112 TrmpAddr, 22, false, false, 0); 7113 7114 SDValue Ops[] = 7115 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 7116 return DAG.getMergeValues(Ops, 2, dl); 7117 } else { 7118 const Function *Func = 7119 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 7120 CallingConv::ID CC = Func->getCallingConv(); 7121 unsigned NestReg; 7122 7123 switch (CC) { 7124 default: 7125 llvm_unreachable("Unsupported calling convention"); 7126 case CallingConv::C: 7127 case CallingConv::X86_StdCall: { 7128 // Pass 'nest' parameter in ECX. 7129 // Must be kept in sync with X86CallingConv.td 7130 NestReg = X86::ECX; 7131 7132 // Check that ECX wasn't needed by an 'inreg' parameter. 7133 const FunctionType *FTy = Func->getFunctionType(); 7134 const AttrListPtr &Attrs = Func->getAttributes(); 7135 7136 if (!Attrs.isEmpty() && !Func->isVarArg()) { 7137 unsigned InRegCount = 0; 7138 unsigned Idx = 1; 7139 7140 for (FunctionType::param_iterator I = FTy->param_begin(), 7141 E = FTy->param_end(); I != E; ++I, ++Idx) 7142 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 7143 // FIXME: should only count parameters that are lowered to integers. 7144 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 7145 7146 if (InRegCount > 2) { 7147 llvm_report_error("Nest register in use - reduce number of inreg parameters!"); 7148 } 7149 } 7150 break; 7151 } 7152 case CallingConv::X86_FastCall: 7153 case CallingConv::Fast: 7154 // Pass 'nest' parameter in EAX. 7155 // Must be kept in sync with X86CallingConv.td 7156 NestReg = X86::EAX; 7157 break; 7158 } 7159 7160 SDValue OutChains[4]; 7161 SDValue Addr, Disp; 7162 7163 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7164 DAG.getConstant(10, MVT::i32)); 7165 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 7166 7167 // This is storing the opcode for MOV32ri. 7168 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 7169 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 7170 OutChains[0] = DAG.getStore(Root, dl, 7171 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 7172 Trmp, TrmpAddr, 0, false, false, 0); 7173 7174 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7175 DAG.getConstant(1, MVT::i32)); 7176 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, 7177 false, false, 1); 7178 7179 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 7180 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7181 DAG.getConstant(5, MVT::i32)); 7182 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 7183 TrmpAddr, 5, false, false, 1); 7184 7185 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7186 DAG.getConstant(6, MVT::i32)); 7187 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, 7188 false, false, 1); 7189 7190 SDValue Ops[] = 7191 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 7192 return DAG.getMergeValues(Ops, 2, dl); 7193 } 7194} 7195 7196SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 7197 /* 7198 The rounding mode is in bits 11:10 of FPSR, and has the following 7199 settings: 7200 00 Round to nearest 7201 01 Round to -inf 7202 10 Round to +inf 7203 11 Round to 0 7204 7205 FLT_ROUNDS, on the other hand, expects the following: 7206 -1 Undefined 7207 0 Round to 0 7208 1 Round to nearest 7209 2 Round to +inf 7210 3 Round to -inf 7211 7212 To perform the conversion, we do: 7213 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 7214 */ 7215 7216 MachineFunction &MF = DAG.getMachineFunction(); 7217 const TargetMachine &TM = MF.getTarget(); 7218 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 7219 unsigned StackAlignment = TFI.getStackAlignment(); 7220 EVT VT = Op.getValueType(); 7221 DebugLoc dl = Op.getDebugLoc(); 7222 7223 // Save FP Control Word to stack slot 7224 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 7225 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7226 7227 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 7228 DAG.getEntryNode(), StackSlot); 7229 7230 // Load FP Control Word from stack slot 7231 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0, 7232 false, false, 0); 7233 7234 // Transform as necessary 7235 SDValue CWD1 = 7236 DAG.getNode(ISD::SRL, dl, MVT::i16, 7237 DAG.getNode(ISD::AND, dl, MVT::i16, 7238 CWD, DAG.getConstant(0x800, MVT::i16)), 7239 DAG.getConstant(11, MVT::i8)); 7240 SDValue CWD2 = 7241 DAG.getNode(ISD::SRL, dl, MVT::i16, 7242 DAG.getNode(ISD::AND, dl, MVT::i16, 7243 CWD, DAG.getConstant(0x400, MVT::i16)), 7244 DAG.getConstant(9, MVT::i8)); 7245 7246 SDValue RetVal = 7247 DAG.getNode(ISD::AND, dl, MVT::i16, 7248 DAG.getNode(ISD::ADD, dl, MVT::i16, 7249 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 7250 DAG.getConstant(1, MVT::i16)), 7251 DAG.getConstant(3, MVT::i16)); 7252 7253 7254 return DAG.getNode((VT.getSizeInBits() < 16 ? 7255 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 7256} 7257 7258SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 7259 EVT VT = Op.getValueType(); 7260 EVT OpVT = VT; 7261 unsigned NumBits = VT.getSizeInBits(); 7262 DebugLoc dl = Op.getDebugLoc(); 7263 7264 Op = Op.getOperand(0); 7265 if (VT == MVT::i8) { 7266 // Zero extend to i32 since there is not an i8 bsr. 7267 OpVT = MVT::i32; 7268 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7269 } 7270 7271 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 7272 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7273 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 7274 7275 // If src is zero (i.e. bsr sets ZF), returns NumBits. 7276 SDValue Ops[] = { 7277 Op, 7278 DAG.getConstant(NumBits+NumBits-1, OpVT), 7279 DAG.getConstant(X86::COND_E, MVT::i8), 7280 Op.getValue(1) 7281 }; 7282 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7283 7284 // Finally xor with NumBits-1. 7285 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 7286 7287 if (VT == MVT::i8) 7288 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7289 return Op; 7290} 7291 7292SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 7293 EVT VT = Op.getValueType(); 7294 EVT OpVT = VT; 7295 unsigned NumBits = VT.getSizeInBits(); 7296 DebugLoc dl = Op.getDebugLoc(); 7297 7298 Op = Op.getOperand(0); 7299 if (VT == MVT::i8) { 7300 OpVT = MVT::i32; 7301 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7302 } 7303 7304 // Issue a bsf (scan bits forward) which also sets EFLAGS. 7305 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7306 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 7307 7308 // If src is zero (i.e. bsf sets ZF), returns NumBits. 7309 SDValue Ops[] = { 7310 Op, 7311 DAG.getConstant(NumBits, OpVT), 7312 DAG.getConstant(X86::COND_E, MVT::i8), 7313 Op.getValue(1) 7314 }; 7315 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7316 7317 if (VT == MVT::i8) 7318 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7319 return Op; 7320} 7321 7322SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 7323 EVT VT = Op.getValueType(); 7324 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 7325 DebugLoc dl = Op.getDebugLoc(); 7326 7327 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 7328 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 7329 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 7330 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 7331 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 7332 // 7333 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 7334 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 7335 // return AloBlo + AloBhi + AhiBlo; 7336 7337 SDValue A = Op.getOperand(0); 7338 SDValue B = Op.getOperand(1); 7339 7340 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7341 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7342 A, DAG.getConstant(32, MVT::i32)); 7343 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7344 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7345 B, DAG.getConstant(32, MVT::i32)); 7346 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7347 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7348 A, B); 7349 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7350 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7351 A, Bhi); 7352 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7353 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7354 Ahi, B); 7355 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7356 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7357 AloBhi, DAG.getConstant(32, MVT::i32)); 7358 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7359 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7360 AhiBlo, DAG.getConstant(32, MVT::i32)); 7361 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 7362 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 7363 return Res; 7364} 7365 7366 7367SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 7368 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 7369 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 7370 // looks for this combo and may remove the "setcc" instruction if the "setcc" 7371 // has only one use. 7372 SDNode *N = Op.getNode(); 7373 SDValue LHS = N->getOperand(0); 7374 SDValue RHS = N->getOperand(1); 7375 unsigned BaseOp = 0; 7376 unsigned Cond = 0; 7377 DebugLoc dl = Op.getDebugLoc(); 7378 7379 switch (Op.getOpcode()) { 7380 default: llvm_unreachable("Unknown ovf instruction!"); 7381 case ISD::SADDO: 7382 // A subtract of one will be selected as a INC. Note that INC doesn't 7383 // set CF, so we can't do this for UADDO. 7384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7385 if (C->getAPIntValue() == 1) { 7386 BaseOp = X86ISD::INC; 7387 Cond = X86::COND_O; 7388 break; 7389 } 7390 BaseOp = X86ISD::ADD; 7391 Cond = X86::COND_O; 7392 break; 7393 case ISD::UADDO: 7394 BaseOp = X86ISD::ADD; 7395 Cond = X86::COND_B; 7396 break; 7397 case ISD::SSUBO: 7398 // A subtract of one will be selected as a DEC. Note that DEC doesn't 7399 // set CF, so we can't do this for USUBO. 7400 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7401 if (C->getAPIntValue() == 1) { 7402 BaseOp = X86ISD::DEC; 7403 Cond = X86::COND_O; 7404 break; 7405 } 7406 BaseOp = X86ISD::SUB; 7407 Cond = X86::COND_O; 7408 break; 7409 case ISD::USUBO: 7410 BaseOp = X86ISD::SUB; 7411 Cond = X86::COND_B; 7412 break; 7413 case ISD::SMULO: 7414 BaseOp = X86ISD::SMUL; 7415 Cond = X86::COND_O; 7416 break; 7417 case ISD::UMULO: 7418 BaseOp = X86ISD::UMUL; 7419 Cond = X86::COND_B; 7420 break; 7421 } 7422 7423 // Also sets EFLAGS. 7424 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 7425 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 7426 7427 SDValue SetCC = 7428 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 7429 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 7430 7431 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 7432 return Sum; 7433} 7434 7435SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 7436 EVT T = Op.getValueType(); 7437 DebugLoc dl = Op.getDebugLoc(); 7438 unsigned Reg = 0; 7439 unsigned size = 0; 7440 switch(T.getSimpleVT().SimpleTy) { 7441 default: 7442 assert(false && "Invalid value type!"); 7443 case MVT::i8: Reg = X86::AL; size = 1; break; 7444 case MVT::i16: Reg = X86::AX; size = 2; break; 7445 case MVT::i32: Reg = X86::EAX; size = 4; break; 7446 case MVT::i64: 7447 assert(Subtarget->is64Bit() && "Node not type legal!"); 7448 Reg = X86::RAX; size = 8; 7449 break; 7450 } 7451 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 7452 Op.getOperand(2), SDValue()); 7453 SDValue Ops[] = { cpIn.getValue(0), 7454 Op.getOperand(1), 7455 Op.getOperand(3), 7456 DAG.getTargetConstant(size, MVT::i8), 7457 cpIn.getValue(1) }; 7458 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7459 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 7460 SDValue cpOut = 7461 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 7462 return cpOut; 7463} 7464 7465SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 7466 SelectionDAG &DAG) { 7467 assert(Subtarget->is64Bit() && "Result not type legalized?"); 7468 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7469 SDValue TheChain = Op.getOperand(0); 7470 DebugLoc dl = Op.getDebugLoc(); 7471 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7472 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 7473 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 7474 rax.getValue(2)); 7475 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 7476 DAG.getConstant(32, MVT::i8)); 7477 SDValue Ops[] = { 7478 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 7479 rdx.getValue(1) 7480 }; 7481 return DAG.getMergeValues(Ops, 2, dl); 7482} 7483 7484SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 7485 SDNode *Node = Op.getNode(); 7486 DebugLoc dl = Node->getDebugLoc(); 7487 EVT T = Node->getValueType(0); 7488 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 7489 DAG.getConstant(0, T), Node->getOperand(2)); 7490 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 7491 cast<AtomicSDNode>(Node)->getMemoryVT(), 7492 Node->getOperand(0), 7493 Node->getOperand(1), negOp, 7494 cast<AtomicSDNode>(Node)->getSrcValue(), 7495 cast<AtomicSDNode>(Node)->getAlignment()); 7496} 7497 7498/// LowerOperation - Provide custom lowering hooks for some operations. 7499/// 7500SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 7501 switch (Op.getOpcode()) { 7502 default: llvm_unreachable("Should not custom lower this!"); 7503 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 7504 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 7505 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 7506 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 7507 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 7508 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 7509 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 7510 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 7511 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 7512 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 7513 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 7514 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 7515 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 7516 case ISD::SHL_PARTS: 7517 case ISD::SRA_PARTS: 7518 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 7519 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 7520 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 7521 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 7522 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 7523 case ISD::FABS: return LowerFABS(Op, DAG); 7524 case ISD::FNEG: return LowerFNEG(Op, DAG); 7525 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 7526 case ISD::SETCC: return LowerSETCC(Op, DAG); 7527 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 7528 case ISD::SELECT: return LowerSELECT(Op, DAG); 7529 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 7530 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 7531 case ISD::VASTART: return LowerVASTART(Op, DAG); 7532 case ISD::VAARG: return LowerVAARG(Op, DAG); 7533 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 7534 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 7535 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 7536 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 7537 case ISD::FRAME_TO_ARGS_OFFSET: 7538 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 7539 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 7540 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 7541 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 7542 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 7543 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 7544 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 7545 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 7546 case ISD::SADDO: 7547 case ISD::UADDO: 7548 case ISD::SSUBO: 7549 case ISD::USUBO: 7550 case ISD::SMULO: 7551 case ISD::UMULO: return LowerXALUO(Op, DAG); 7552 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 7553 } 7554} 7555 7556void X86TargetLowering:: 7557ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 7558 SelectionDAG &DAG, unsigned NewOp) { 7559 EVT T = Node->getValueType(0); 7560 DebugLoc dl = Node->getDebugLoc(); 7561 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 7562 7563 SDValue Chain = Node->getOperand(0); 7564 SDValue In1 = Node->getOperand(1); 7565 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7566 Node->getOperand(2), DAG.getIntPtrConstant(0)); 7567 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7568 Node->getOperand(2), DAG.getIntPtrConstant(1)); 7569 SDValue Ops[] = { Chain, In1, In2L, In2H }; 7570 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 7571 SDValue Result = 7572 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 7573 cast<MemSDNode>(Node)->getMemOperand()); 7574 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 7575 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7576 Results.push_back(Result.getValue(2)); 7577} 7578 7579/// ReplaceNodeResults - Replace a node with an illegal result type 7580/// with a new node built out of custom code. 7581void X86TargetLowering::ReplaceNodeResults(SDNode *N, 7582 SmallVectorImpl<SDValue>&Results, 7583 SelectionDAG &DAG) { 7584 DebugLoc dl = N->getDebugLoc(); 7585 switch (N->getOpcode()) { 7586 default: 7587 assert(false && "Do not know how to custom type legalize this operation!"); 7588 return; 7589 case ISD::FP_TO_SINT: { 7590 std::pair<SDValue,SDValue> Vals = 7591 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 7592 SDValue FIST = Vals.first, StackSlot = Vals.second; 7593 if (FIST.getNode() != 0) { 7594 EVT VT = N->getValueType(0); 7595 // Return a load from the stack slot. 7596 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0, 7597 false, false, 0)); 7598 } 7599 return; 7600 } 7601 case ISD::READCYCLECOUNTER: { 7602 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7603 SDValue TheChain = N->getOperand(0); 7604 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7605 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 7606 rd.getValue(1)); 7607 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 7608 eax.getValue(2)); 7609 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 7610 SDValue Ops[] = { eax, edx }; 7611 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 7612 Results.push_back(edx.getValue(1)); 7613 return; 7614 } 7615 case ISD::ATOMIC_CMP_SWAP: { 7616 EVT T = N->getValueType(0); 7617 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 7618 SDValue cpInL, cpInH; 7619 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7620 DAG.getConstant(0, MVT::i32)); 7621 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7622 DAG.getConstant(1, MVT::i32)); 7623 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 7624 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 7625 cpInL.getValue(1)); 7626 SDValue swapInL, swapInH; 7627 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7628 DAG.getConstant(0, MVT::i32)); 7629 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7630 DAG.getConstant(1, MVT::i32)); 7631 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 7632 cpInH.getValue(1)); 7633 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 7634 swapInL.getValue(1)); 7635 SDValue Ops[] = { swapInH.getValue(0), 7636 N->getOperand(1), 7637 swapInH.getValue(1) }; 7638 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7639 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 7640 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 7641 MVT::i32, Result.getValue(1)); 7642 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 7643 MVT::i32, cpOutL.getValue(2)); 7644 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 7645 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7646 Results.push_back(cpOutH.getValue(1)); 7647 return; 7648 } 7649 case ISD::ATOMIC_LOAD_ADD: 7650 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 7651 return; 7652 case ISD::ATOMIC_LOAD_AND: 7653 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 7654 return; 7655 case ISD::ATOMIC_LOAD_NAND: 7656 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 7657 return; 7658 case ISD::ATOMIC_LOAD_OR: 7659 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 7660 return; 7661 case ISD::ATOMIC_LOAD_SUB: 7662 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 7663 return; 7664 case ISD::ATOMIC_LOAD_XOR: 7665 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 7666 return; 7667 case ISD::ATOMIC_SWAP: 7668 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 7669 return; 7670 } 7671} 7672 7673const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 7674 switch (Opcode) { 7675 default: return NULL; 7676 case X86ISD::BSF: return "X86ISD::BSF"; 7677 case X86ISD::BSR: return "X86ISD::BSR"; 7678 case X86ISD::SHLD: return "X86ISD::SHLD"; 7679 case X86ISD::SHRD: return "X86ISD::SHRD"; 7680 case X86ISD::FAND: return "X86ISD::FAND"; 7681 case X86ISD::FOR: return "X86ISD::FOR"; 7682 case X86ISD::FXOR: return "X86ISD::FXOR"; 7683 case X86ISD::FSRL: return "X86ISD::FSRL"; 7684 case X86ISD::FILD: return "X86ISD::FILD"; 7685 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 7686 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 7687 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 7688 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 7689 case X86ISD::FLD: return "X86ISD::FLD"; 7690 case X86ISD::FST: return "X86ISD::FST"; 7691 case X86ISD::CALL: return "X86ISD::CALL"; 7692 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 7693 case X86ISD::BT: return "X86ISD::BT"; 7694 case X86ISD::CMP: return "X86ISD::CMP"; 7695 case X86ISD::COMI: return "X86ISD::COMI"; 7696 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 7697 case X86ISD::SETCC: return "X86ISD::SETCC"; 7698 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 7699 case X86ISD::CMOV: return "X86ISD::CMOV"; 7700 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 7701 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 7702 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 7703 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 7704 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 7705 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 7706 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 7707 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 7708 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 7709 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 7710 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 7711 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 7712 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW"; 7713 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 7714 case X86ISD::FMAX: return "X86ISD::FMAX"; 7715 case X86ISD::FMIN: return "X86ISD::FMIN"; 7716 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 7717 case X86ISD::FRCP: return "X86ISD::FRCP"; 7718 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7719 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7720 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7721 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7722 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7723 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7724 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7725 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7726 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7727 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7728 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7729 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7730 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7731 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7732 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7733 case X86ISD::VSHL: return "X86ISD::VSHL"; 7734 case X86ISD::VSRL: return "X86ISD::VSRL"; 7735 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7736 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7737 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7738 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7739 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7740 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7741 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7742 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7743 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7744 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7745 case X86ISD::ADD: return "X86ISD::ADD"; 7746 case X86ISD::SUB: return "X86ISD::SUB"; 7747 case X86ISD::SMUL: return "X86ISD::SMUL"; 7748 case X86ISD::UMUL: return "X86ISD::UMUL"; 7749 case X86ISD::INC: return "X86ISD::INC"; 7750 case X86ISD::DEC: return "X86ISD::DEC"; 7751 case X86ISD::OR: return "X86ISD::OR"; 7752 case X86ISD::XOR: return "X86ISD::XOR"; 7753 case X86ISD::AND: return "X86ISD::AND"; 7754 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7755 case X86ISD::PTEST: return "X86ISD::PTEST"; 7756 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 7757 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA"; 7758 } 7759} 7760 7761// isLegalAddressingMode - Return true if the addressing mode represented 7762// by AM is legal for this target, for a load/store of the specified type. 7763bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7764 const Type *Ty) const { 7765 // X86 supports extremely general addressing modes. 7766 CodeModel::Model M = getTargetMachine().getCodeModel(); 7767 7768 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7769 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 7770 return false; 7771 7772 if (AM.BaseGV) { 7773 unsigned GVFlags = 7774 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 7775 7776 // If a reference to this global requires an extra load, we can't fold it. 7777 if (isGlobalStubReference(GVFlags)) 7778 return false; 7779 7780 // If BaseGV requires a register for the PIC base, we cannot also have a 7781 // BaseReg specified. 7782 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 7783 return false; 7784 7785 // If lower 4G is not available, then we must use rip-relative addressing. 7786 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 7787 return false; 7788 } 7789 7790 switch (AM.Scale) { 7791 case 0: 7792 case 1: 7793 case 2: 7794 case 4: 7795 case 8: 7796 // These scales always work. 7797 break; 7798 case 3: 7799 case 5: 7800 case 9: 7801 // These scales are formed with basereg+scalereg. Only accept if there is 7802 // no basereg yet. 7803 if (AM.HasBaseReg) 7804 return false; 7805 break; 7806 default: // Other stuff never works. 7807 return false; 7808 } 7809 7810 return true; 7811} 7812 7813 7814bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7815 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 7816 return false; 7817 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7818 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7819 if (NumBits1 <= NumBits2) 7820 return false; 7821 return true; 7822} 7823 7824bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 7825 if (!VT1.isInteger() || !VT2.isInteger()) 7826 return false; 7827 unsigned NumBits1 = VT1.getSizeInBits(); 7828 unsigned NumBits2 = VT2.getSizeInBits(); 7829 if (NumBits1 <= NumBits2) 7830 return false; 7831 return true; 7832} 7833 7834bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7835 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7836 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 7837} 7838 7839bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 7840 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7841 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7842} 7843 7844bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 7845 // i16 instructions are longer (0x66 prefix) and potentially slower. 7846 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7847} 7848 7849/// isShuffleMaskLegal - Targets can use this to indicate that they only 7850/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7851/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7852/// are assumed to be legal. 7853bool 7854X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 7855 EVT VT) const { 7856 // Only do shuffles on 128-bit vector types for now. 7857 if (VT.getSizeInBits() == 64) 7858 return false; 7859 7860 // FIXME: pshufb, blends, shifts. 7861 return (VT.getVectorNumElements() == 2 || 7862 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 7863 isMOVLMask(M, VT) || 7864 isSHUFPMask(M, VT) || 7865 isPSHUFDMask(M, VT) || 7866 isPSHUFHWMask(M, VT) || 7867 isPSHUFLWMask(M, VT) || 7868 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 7869 isUNPCKLMask(M, VT) || 7870 isUNPCKHMask(M, VT) || 7871 isUNPCKL_v_undef_Mask(M, VT) || 7872 isUNPCKH_v_undef_Mask(M, VT)); 7873} 7874 7875bool 7876X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 7877 EVT VT) const { 7878 unsigned NumElts = VT.getVectorNumElements(); 7879 // FIXME: This collection of masks seems suspect. 7880 if (NumElts == 2) 7881 return true; 7882 if (NumElts == 4 && VT.getSizeInBits() == 128) { 7883 return (isMOVLMask(Mask, VT) || 7884 isCommutedMOVLMask(Mask, VT, true) || 7885 isSHUFPMask(Mask, VT) || 7886 isCommutedSHUFPMask(Mask, VT)); 7887 } 7888 return false; 7889} 7890 7891//===----------------------------------------------------------------------===// 7892// X86 Scheduler Hooks 7893//===----------------------------------------------------------------------===// 7894 7895// private utility function 7896MachineBasicBlock * 7897X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7898 MachineBasicBlock *MBB, 7899 unsigned regOpc, 7900 unsigned immOpc, 7901 unsigned LoadOpc, 7902 unsigned CXchgOpc, 7903 unsigned copyOpc, 7904 unsigned notOpc, 7905 unsigned EAXreg, 7906 TargetRegisterClass *RC, 7907 bool invSrc) const { 7908 // For the atomic bitwise operator, we generate 7909 // thisMBB: 7910 // newMBB: 7911 // ld t1 = [bitinstr.addr] 7912 // op t2 = t1, [bitinstr.val] 7913 // mov EAX = t1 7914 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7915 // bz newMBB 7916 // fallthrough -->nextMBB 7917 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7918 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7919 MachineFunction::iterator MBBIter = MBB; 7920 ++MBBIter; 7921 7922 /// First build the CFG 7923 MachineFunction *F = MBB->getParent(); 7924 MachineBasicBlock *thisMBB = MBB; 7925 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7926 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7927 F->insert(MBBIter, newMBB); 7928 F->insert(MBBIter, nextMBB); 7929 7930 // Move all successors to thisMBB to nextMBB 7931 nextMBB->transferSuccessors(thisMBB); 7932 7933 // Update thisMBB to fall through to newMBB 7934 thisMBB->addSuccessor(newMBB); 7935 7936 // newMBB jumps to itself and fall through to nextMBB 7937 newMBB->addSuccessor(nextMBB); 7938 newMBB->addSuccessor(newMBB); 7939 7940 // Insert instructions into newMBB based on incoming instruction 7941 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && 7942 "unexpected number of operands"); 7943 DebugLoc dl = bInstr->getDebugLoc(); 7944 MachineOperand& destOper = bInstr->getOperand(0); 7945 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7946 int numArgs = bInstr->getNumOperands() - 1; 7947 for (int i=0; i < numArgs; ++i) 7948 argOpers[i] = &bInstr->getOperand(i+1); 7949 7950 // x86 address has 4 operands: base, index, scale, and displacement 7951 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7952 int valArgIndx = lastAddrIndx + 1; 7953 7954 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7955 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 7956 for (int i=0; i <= lastAddrIndx; ++i) 7957 (*MIB).addOperand(*argOpers[i]); 7958 7959 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 7960 if (invSrc) { 7961 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 7962 } 7963 else 7964 tt = t1; 7965 7966 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7967 assert((argOpers[valArgIndx]->isReg() || 7968 argOpers[valArgIndx]->isImm()) && 7969 "invalid operand"); 7970 if (argOpers[valArgIndx]->isReg()) 7971 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 7972 else 7973 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 7974 MIB.addReg(tt); 7975 (*MIB).addOperand(*argOpers[valArgIndx]); 7976 7977 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 7978 MIB.addReg(t1); 7979 7980 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 7981 for (int i=0; i <= lastAddrIndx; ++i) 7982 (*MIB).addOperand(*argOpers[i]); 7983 MIB.addReg(t2); 7984 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7985 (*MIB).setMemRefs(bInstr->memoperands_begin(), 7986 bInstr->memoperands_end()); 7987 7988 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 7989 MIB.addReg(EAXreg); 7990 7991 // insert branch 7992 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 7993 7994 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7995 return nextMBB; 7996} 7997 7998// private utility function: 64 bit atomics on 32 bit host. 7999MachineBasicBlock * 8000X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 8001 MachineBasicBlock *MBB, 8002 unsigned regOpcL, 8003 unsigned regOpcH, 8004 unsigned immOpcL, 8005 unsigned immOpcH, 8006 bool invSrc) const { 8007 // For the atomic bitwise operator, we generate 8008 // thisMBB (instructions are in pairs, except cmpxchg8b) 8009 // ld t1,t2 = [bitinstr.addr] 8010 // newMBB: 8011 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 8012 // op t5, t6 <- out1, out2, [bitinstr.val] 8013 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 8014 // mov ECX, EBX <- t5, t6 8015 // mov EAX, EDX <- t1, t2 8016 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 8017 // mov t3, t4 <- EAX, EDX 8018 // bz newMBB 8019 // result in out1, out2 8020 // fallthrough -->nextMBB 8021 8022 const TargetRegisterClass *RC = X86::GR32RegisterClass; 8023 const unsigned LoadOpc = X86::MOV32rm; 8024 const unsigned copyOpc = X86::MOV32rr; 8025 const unsigned NotOpc = X86::NOT32r; 8026 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8027 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8028 MachineFunction::iterator MBBIter = MBB; 8029 ++MBBIter; 8030 8031 /// First build the CFG 8032 MachineFunction *F = MBB->getParent(); 8033 MachineBasicBlock *thisMBB = MBB; 8034 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8035 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8036 F->insert(MBBIter, newMBB); 8037 F->insert(MBBIter, nextMBB); 8038 8039 // Move all successors to thisMBB to nextMBB 8040 nextMBB->transferSuccessors(thisMBB); 8041 8042 // Update thisMBB to fall through to newMBB 8043 thisMBB->addSuccessor(newMBB); 8044 8045 // newMBB jumps to itself and fall through to nextMBB 8046 newMBB->addSuccessor(nextMBB); 8047 newMBB->addSuccessor(newMBB); 8048 8049 DebugLoc dl = bInstr->getDebugLoc(); 8050 // Insert instructions into newMBB based on incoming instruction 8051 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 8052 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && 8053 "unexpected number of operands"); 8054 MachineOperand& dest1Oper = bInstr->getOperand(0); 8055 MachineOperand& dest2Oper = bInstr->getOperand(1); 8056 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8057 for (int i=0; i < 2 + X86AddrNumOperands; ++i) 8058 argOpers[i] = &bInstr->getOperand(i+2); 8059 8060 // x86 address has 5 operands: base, index, scale, displacement, and segment. 8061 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8062 8063 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8064 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 8065 for (int i=0; i <= lastAddrIndx; ++i) 8066 (*MIB).addOperand(*argOpers[i]); 8067 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8068 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 8069 // add 4 to displacement. 8070 for (int i=0; i <= lastAddrIndx-2; ++i) 8071 (*MIB).addOperand(*argOpers[i]); 8072 MachineOperand newOp3 = *(argOpers[3]); 8073 if (newOp3.isImm()) 8074 newOp3.setImm(newOp3.getImm()+4); 8075 else 8076 newOp3.setOffset(newOp3.getOffset()+4); 8077 (*MIB).addOperand(newOp3); 8078 (*MIB).addOperand(*argOpers[lastAddrIndx]); 8079 8080 // t3/4 are defined later, at the bottom of the loop 8081 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 8082 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 8083 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 8084 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 8085 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 8086 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 8087 8088 // The subsequent operations should be using the destination registers of 8089 //the PHI instructions. 8090 if (invSrc) { 8091 t1 = F->getRegInfo().createVirtualRegister(RC); 8092 t2 = F->getRegInfo().createVirtualRegister(RC); 8093 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 8094 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 8095 } else { 8096 t1 = dest1Oper.getReg(); 8097 t2 = dest2Oper.getReg(); 8098 } 8099 8100 int valArgIndx = lastAddrIndx + 1; 8101 assert((argOpers[valArgIndx]->isReg() || 8102 argOpers[valArgIndx]->isImm()) && 8103 "invalid operand"); 8104 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 8105 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 8106 if (argOpers[valArgIndx]->isReg()) 8107 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 8108 else 8109 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 8110 if (regOpcL != X86::MOV32rr) 8111 MIB.addReg(t1); 8112 (*MIB).addOperand(*argOpers[valArgIndx]); 8113 assert(argOpers[valArgIndx + 1]->isReg() == 8114 argOpers[valArgIndx]->isReg()); 8115 assert(argOpers[valArgIndx + 1]->isImm() == 8116 argOpers[valArgIndx]->isImm()); 8117 if (argOpers[valArgIndx + 1]->isReg()) 8118 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 8119 else 8120 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 8121 if (regOpcH != X86::MOV32rr) 8122 MIB.addReg(t2); 8123 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 8124 8125 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 8126 MIB.addReg(t1); 8127 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 8128 MIB.addReg(t2); 8129 8130 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 8131 MIB.addReg(t5); 8132 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 8133 MIB.addReg(t6); 8134 8135 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 8136 for (int i=0; i <= lastAddrIndx; ++i) 8137 (*MIB).addOperand(*argOpers[i]); 8138 8139 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8140 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8141 bInstr->memoperands_end()); 8142 8143 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 8144 MIB.addReg(X86::EAX); 8145 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 8146 MIB.addReg(X86::EDX); 8147 8148 // insert branch 8149 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8150 8151 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 8152 return nextMBB; 8153} 8154 8155// private utility function 8156MachineBasicBlock * 8157X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 8158 MachineBasicBlock *MBB, 8159 unsigned cmovOpc) const { 8160 // For the atomic min/max operator, we generate 8161 // thisMBB: 8162 // newMBB: 8163 // ld t1 = [min/max.addr] 8164 // mov t2 = [min/max.val] 8165 // cmp t1, t2 8166 // cmov[cond] t2 = t1 8167 // mov EAX = t1 8168 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8169 // bz newMBB 8170 // fallthrough -->nextMBB 8171 // 8172 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8173 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8174 MachineFunction::iterator MBBIter = MBB; 8175 ++MBBIter; 8176 8177 /// First build the CFG 8178 MachineFunction *F = MBB->getParent(); 8179 MachineBasicBlock *thisMBB = MBB; 8180 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8181 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8182 F->insert(MBBIter, newMBB); 8183 F->insert(MBBIter, nextMBB); 8184 8185 // Move all successors of thisMBB to nextMBB 8186 nextMBB->transferSuccessors(thisMBB); 8187 8188 // Update thisMBB to fall through to newMBB 8189 thisMBB->addSuccessor(newMBB); 8190 8191 // newMBB jumps to newMBB and fall through to nextMBB 8192 newMBB->addSuccessor(nextMBB); 8193 newMBB->addSuccessor(newMBB); 8194 8195 DebugLoc dl = mInstr->getDebugLoc(); 8196 // Insert instructions into newMBB based on incoming instruction 8197 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && 8198 "unexpected number of operands"); 8199 MachineOperand& destOper = mInstr->getOperand(0); 8200 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8201 int numArgs = mInstr->getNumOperands() - 1; 8202 for (int i=0; i < numArgs; ++i) 8203 argOpers[i] = &mInstr->getOperand(i+1); 8204 8205 // x86 address has 4 operands: base, index, scale, and displacement 8206 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8207 int valArgIndx = lastAddrIndx + 1; 8208 8209 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8210 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 8211 for (int i=0; i <= lastAddrIndx; ++i) 8212 (*MIB).addOperand(*argOpers[i]); 8213 8214 // We only support register and immediate values 8215 assert((argOpers[valArgIndx]->isReg() || 8216 argOpers[valArgIndx]->isImm()) && 8217 "invalid operand"); 8218 8219 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8220 if (argOpers[valArgIndx]->isReg()) 8221 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8222 else 8223 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8224 (*MIB).addOperand(*argOpers[valArgIndx]); 8225 8226 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 8227 MIB.addReg(t1); 8228 8229 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 8230 MIB.addReg(t1); 8231 MIB.addReg(t2); 8232 8233 // Generate movc 8234 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8235 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 8236 MIB.addReg(t2); 8237 MIB.addReg(t1); 8238 8239 // Cmp and exchange if none has modified the memory location 8240 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 8241 for (int i=0; i <= lastAddrIndx; ++i) 8242 (*MIB).addOperand(*argOpers[i]); 8243 MIB.addReg(t3); 8244 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8245 (*MIB).setMemRefs(mInstr->memoperands_begin(), 8246 mInstr->memoperands_end()); 8247 8248 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 8249 MIB.addReg(X86::EAX); 8250 8251 // insert branch 8252 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8253 8254 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 8255 return nextMBB; 8256} 8257 8258// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 8259// all of this code can be replaced with that in the .td file. 8260MachineBasicBlock * 8261X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 8262 unsigned numArgs, bool memArg) const { 8263 8264 MachineFunction *F = BB->getParent(); 8265 DebugLoc dl = MI->getDebugLoc(); 8266 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8267 8268 unsigned Opc; 8269 if (memArg) 8270 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 8271 else 8272 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 8273 8274 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 8275 8276 for (unsigned i = 0; i < numArgs; ++i) { 8277 MachineOperand &Op = MI->getOperand(i+1); 8278 8279 if (!(Op.isReg() && Op.isImplicit())) 8280 MIB.addOperand(Op); 8281 } 8282 8283 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 8284 .addReg(X86::XMM0); 8285 8286 F->DeleteMachineInstr(MI); 8287 8288 return BB; 8289} 8290 8291MachineBasicBlock * 8292X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 8293 MachineInstr *MI, 8294 MachineBasicBlock *MBB) const { 8295 // Emit code to save XMM registers to the stack. The ABI says that the 8296 // number of registers to save is given in %al, so it's theoretically 8297 // possible to do an indirect jump trick to avoid saving all of them, 8298 // however this code takes a simpler approach and just executes all 8299 // of the stores if %al is non-zero. It's less code, and it's probably 8300 // easier on the hardware branch predictor, and stores aren't all that 8301 // expensive anyway. 8302 8303 // Create the new basic blocks. One block contains all the XMM stores, 8304 // and one block is the final destination regardless of whether any 8305 // stores were performed. 8306 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8307 MachineFunction *F = MBB->getParent(); 8308 MachineFunction::iterator MBBIter = MBB; 8309 ++MBBIter; 8310 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 8311 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 8312 F->insert(MBBIter, XMMSaveMBB); 8313 F->insert(MBBIter, EndMBB); 8314 8315 // Set up the CFG. 8316 // Move any original successors of MBB to the end block. 8317 EndMBB->transferSuccessors(MBB); 8318 // The original block will now fall through to the XMM save block. 8319 MBB->addSuccessor(XMMSaveMBB); 8320 // The XMMSaveMBB will fall through to the end block. 8321 XMMSaveMBB->addSuccessor(EndMBB); 8322 8323 // Now add the instructions. 8324 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8325 DebugLoc DL = MI->getDebugLoc(); 8326 8327 unsigned CountReg = MI->getOperand(0).getReg(); 8328 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 8329 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 8330 8331 if (!Subtarget->isTargetWin64()) { 8332 // If %al is 0, branch around the XMM save block. 8333 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 8334 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 8335 MBB->addSuccessor(EndMBB); 8336 } 8337 8338 // In the XMM save block, save all the XMM argument registers. 8339 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 8340 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 8341 MachineMemOperand *MMO = 8342 F->getMachineMemOperand( 8343 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 8344 MachineMemOperand::MOStore, Offset, 8345 /*Size=*/16, /*Align=*/16); 8346 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 8347 .addFrameIndex(RegSaveFrameIndex) 8348 .addImm(/*Scale=*/1) 8349 .addReg(/*IndexReg=*/0) 8350 .addImm(/*Disp=*/Offset) 8351 .addReg(/*Segment=*/0) 8352 .addReg(MI->getOperand(i).getReg()) 8353 .addMemOperand(MMO); 8354 } 8355 8356 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8357 8358 return EndMBB; 8359} 8360 8361MachineBasicBlock * 8362X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 8363 MachineBasicBlock *BB, 8364 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8365 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8366 DebugLoc DL = MI->getDebugLoc(); 8367 8368 // To "insert" a SELECT_CC instruction, we actually have to insert the 8369 // diamond control-flow pattern. The incoming instruction knows the 8370 // destination vreg to set, the condition code register to branch on, the 8371 // true/false values to select between, and a branch opcode to use. 8372 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 8373 MachineFunction::iterator It = BB; 8374 ++It; 8375 8376 // thisMBB: 8377 // ... 8378 // TrueVal = ... 8379 // cmpTY ccX, r1, r2 8380 // bCC copy1MBB 8381 // fallthrough --> copy0MBB 8382 MachineBasicBlock *thisMBB = BB; 8383 MachineFunction *F = BB->getParent(); 8384 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 8385 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 8386 unsigned Opc = 8387 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 8388 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 8389 F->insert(It, copy0MBB); 8390 F->insert(It, sinkMBB); 8391 // Update machine-CFG edges by first adding all successors of the current 8392 // block to the new block which will contain the Phi node for the select. 8393 // Also inform sdisel of the edge changes. 8394 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 8395 E = BB->succ_end(); I != E; ++I) { 8396 EM->insert(std::make_pair(*I, sinkMBB)); 8397 sinkMBB->addSuccessor(*I); 8398 } 8399 // Next, remove all successors of the current block, and add the true 8400 // and fallthrough blocks as its successors. 8401 while (!BB->succ_empty()) 8402 BB->removeSuccessor(BB->succ_begin()); 8403 // Add the true and fallthrough blocks as its successors. 8404 BB->addSuccessor(copy0MBB); 8405 BB->addSuccessor(sinkMBB); 8406 8407 // copy0MBB: 8408 // %FalseValue = ... 8409 // # fallthrough to sinkMBB 8410 BB = copy0MBB; 8411 8412 // Update machine-CFG edges 8413 BB->addSuccessor(sinkMBB); 8414 8415 // sinkMBB: 8416 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 8417 // ... 8418 BB = sinkMBB; 8419 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg()) 8420 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 8421 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 8422 8423 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8424 return BB; 8425} 8426 8427MachineBasicBlock * 8428X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI, 8429 MachineBasicBlock *BB, 8430 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8431 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8432 DebugLoc DL = MI->getDebugLoc(); 8433 MachineFunction *F = BB->getParent(); 8434 8435 // The lowering is pretty easy: we're just emitting the call to _alloca. The 8436 // non-trivial part is impdef of ESP. 8437 // FIXME: The code should be tweaked as soon as we'll try to do codegen for 8438 // mingw-w64. 8439 8440 BuildMI(BB, DL, TII->get(X86::CALLpcrel32)) 8441 .addExternalSymbol("_alloca") 8442 .addReg(X86::EAX, RegState::Implicit) 8443 .addReg(X86::ESP, RegState::Implicit) 8444 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 8445 .addReg(X86::ESP, RegState::Define | RegState::Implicit); 8446 8447 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8448 return BB; 8449} 8450 8451MachineBasicBlock * 8452X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 8453 MachineBasicBlock *BB, 8454 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8455 switch (MI->getOpcode()) { 8456 default: assert(false && "Unexpected instr type to insert"); 8457 case X86::MINGW_ALLOCA: 8458 return EmitLoweredMingwAlloca(MI, BB, EM); 8459 case X86::CMOV_GR8: 8460 case X86::CMOV_V1I64: 8461 case X86::CMOV_FR32: 8462 case X86::CMOV_FR64: 8463 case X86::CMOV_V4F32: 8464 case X86::CMOV_V2F64: 8465 case X86::CMOV_V2I64: 8466 case X86::CMOV_GR16: 8467 case X86::CMOV_GR32: 8468 case X86::CMOV_RFP32: 8469 case X86::CMOV_RFP64: 8470 case X86::CMOV_RFP80: 8471 return EmitLoweredSelect(MI, BB, EM); 8472 8473 case X86::FP32_TO_INT16_IN_MEM: 8474 case X86::FP32_TO_INT32_IN_MEM: 8475 case X86::FP32_TO_INT64_IN_MEM: 8476 case X86::FP64_TO_INT16_IN_MEM: 8477 case X86::FP64_TO_INT32_IN_MEM: 8478 case X86::FP64_TO_INT64_IN_MEM: 8479 case X86::FP80_TO_INT16_IN_MEM: 8480 case X86::FP80_TO_INT32_IN_MEM: 8481 case X86::FP80_TO_INT64_IN_MEM: { 8482 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8483 DebugLoc DL = MI->getDebugLoc(); 8484 8485 // Change the floating point control register to use "round towards zero" 8486 // mode when truncating to an integer value. 8487 MachineFunction *F = BB->getParent(); 8488 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 8489 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx); 8490 8491 // Load the old value of the high byte of the control word... 8492 unsigned OldCW = 8493 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 8494 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW), 8495 CWFrameIdx); 8496 8497 // Set the high part to be round to zero... 8498 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 8499 .addImm(0xC7F); 8500 8501 // Reload the modified control word now... 8502 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8503 8504 // Restore the memory image of control word to original value 8505 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 8506 .addReg(OldCW); 8507 8508 // Get the X86 opcode to use. 8509 unsigned Opc; 8510 switch (MI->getOpcode()) { 8511 default: llvm_unreachable("illegal opcode!"); 8512 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 8513 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 8514 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 8515 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 8516 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 8517 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 8518 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 8519 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 8520 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 8521 } 8522 8523 X86AddressMode AM; 8524 MachineOperand &Op = MI->getOperand(0); 8525 if (Op.isReg()) { 8526 AM.BaseType = X86AddressMode::RegBase; 8527 AM.Base.Reg = Op.getReg(); 8528 } else { 8529 AM.BaseType = X86AddressMode::FrameIndexBase; 8530 AM.Base.FrameIndex = Op.getIndex(); 8531 } 8532 Op = MI->getOperand(1); 8533 if (Op.isImm()) 8534 AM.Scale = Op.getImm(); 8535 Op = MI->getOperand(2); 8536 if (Op.isImm()) 8537 AM.IndexReg = Op.getImm(); 8538 Op = MI->getOperand(3); 8539 if (Op.isGlobal()) { 8540 AM.GV = Op.getGlobal(); 8541 } else { 8542 AM.Disp = Op.getImm(); 8543 } 8544 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM) 8545 .addReg(MI->getOperand(X86AddrNumOperands).getReg()); 8546 8547 // Reload the original control word now. 8548 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8549 8550 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8551 return BB; 8552 } 8553 // DBG_VALUE. Only the frame index case is done here. 8554 case X86::DBG_VALUE: { 8555 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8556 DebugLoc DL = MI->getDebugLoc(); 8557 X86AddressMode AM; 8558 MachineFunction *F = BB->getParent(); 8559 AM.BaseType = X86AddressMode::FrameIndexBase; 8560 AM.Base.FrameIndex = MI->getOperand(0).getImm(); 8561 addFullAddress(BuildMI(BB, DL, TII->get(X86::DBG_VALUE)), AM). 8562 addImm(MI->getOperand(1).getImm()). 8563 addMetadata(MI->getOperand(2).getMetadata()); 8564 F->DeleteMachineInstr(MI); // Remove pseudo. 8565 return BB; 8566 } 8567 8568 // String/text processing lowering. 8569 case X86::PCMPISTRM128REG: 8570 return EmitPCMP(MI, BB, 3, false /* in-mem */); 8571 case X86::PCMPISTRM128MEM: 8572 return EmitPCMP(MI, BB, 3, true /* in-mem */); 8573 case X86::PCMPESTRM128REG: 8574 return EmitPCMP(MI, BB, 5, false /* in mem */); 8575 case X86::PCMPESTRM128MEM: 8576 return EmitPCMP(MI, BB, 5, true /* in mem */); 8577 8578 // Atomic Lowering. 8579 case X86::ATOMAND32: 8580 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8581 X86::AND32ri, X86::MOV32rm, 8582 X86::LCMPXCHG32, X86::MOV32rr, 8583 X86::NOT32r, X86::EAX, 8584 X86::GR32RegisterClass); 8585 case X86::ATOMOR32: 8586 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 8587 X86::OR32ri, X86::MOV32rm, 8588 X86::LCMPXCHG32, X86::MOV32rr, 8589 X86::NOT32r, X86::EAX, 8590 X86::GR32RegisterClass); 8591 case X86::ATOMXOR32: 8592 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 8593 X86::XOR32ri, X86::MOV32rm, 8594 X86::LCMPXCHG32, X86::MOV32rr, 8595 X86::NOT32r, X86::EAX, 8596 X86::GR32RegisterClass); 8597 case X86::ATOMNAND32: 8598 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8599 X86::AND32ri, X86::MOV32rm, 8600 X86::LCMPXCHG32, X86::MOV32rr, 8601 X86::NOT32r, X86::EAX, 8602 X86::GR32RegisterClass, true); 8603 case X86::ATOMMIN32: 8604 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 8605 case X86::ATOMMAX32: 8606 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 8607 case X86::ATOMUMIN32: 8608 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 8609 case X86::ATOMUMAX32: 8610 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 8611 8612 case X86::ATOMAND16: 8613 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8614 X86::AND16ri, X86::MOV16rm, 8615 X86::LCMPXCHG16, X86::MOV16rr, 8616 X86::NOT16r, X86::AX, 8617 X86::GR16RegisterClass); 8618 case X86::ATOMOR16: 8619 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 8620 X86::OR16ri, X86::MOV16rm, 8621 X86::LCMPXCHG16, X86::MOV16rr, 8622 X86::NOT16r, X86::AX, 8623 X86::GR16RegisterClass); 8624 case X86::ATOMXOR16: 8625 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 8626 X86::XOR16ri, X86::MOV16rm, 8627 X86::LCMPXCHG16, X86::MOV16rr, 8628 X86::NOT16r, X86::AX, 8629 X86::GR16RegisterClass); 8630 case X86::ATOMNAND16: 8631 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8632 X86::AND16ri, X86::MOV16rm, 8633 X86::LCMPXCHG16, X86::MOV16rr, 8634 X86::NOT16r, X86::AX, 8635 X86::GR16RegisterClass, true); 8636 case X86::ATOMMIN16: 8637 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 8638 case X86::ATOMMAX16: 8639 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 8640 case X86::ATOMUMIN16: 8641 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 8642 case X86::ATOMUMAX16: 8643 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 8644 8645 case X86::ATOMAND8: 8646 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8647 X86::AND8ri, X86::MOV8rm, 8648 X86::LCMPXCHG8, X86::MOV8rr, 8649 X86::NOT8r, X86::AL, 8650 X86::GR8RegisterClass); 8651 case X86::ATOMOR8: 8652 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 8653 X86::OR8ri, X86::MOV8rm, 8654 X86::LCMPXCHG8, X86::MOV8rr, 8655 X86::NOT8r, X86::AL, 8656 X86::GR8RegisterClass); 8657 case X86::ATOMXOR8: 8658 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 8659 X86::XOR8ri, X86::MOV8rm, 8660 X86::LCMPXCHG8, X86::MOV8rr, 8661 X86::NOT8r, X86::AL, 8662 X86::GR8RegisterClass); 8663 case X86::ATOMNAND8: 8664 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8665 X86::AND8ri, X86::MOV8rm, 8666 X86::LCMPXCHG8, X86::MOV8rr, 8667 X86::NOT8r, X86::AL, 8668 X86::GR8RegisterClass, true); 8669 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 8670 // This group is for 64-bit host. 8671 case X86::ATOMAND64: 8672 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8673 X86::AND64ri32, X86::MOV64rm, 8674 X86::LCMPXCHG64, X86::MOV64rr, 8675 X86::NOT64r, X86::RAX, 8676 X86::GR64RegisterClass); 8677 case X86::ATOMOR64: 8678 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 8679 X86::OR64ri32, X86::MOV64rm, 8680 X86::LCMPXCHG64, X86::MOV64rr, 8681 X86::NOT64r, X86::RAX, 8682 X86::GR64RegisterClass); 8683 case X86::ATOMXOR64: 8684 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 8685 X86::XOR64ri32, X86::MOV64rm, 8686 X86::LCMPXCHG64, X86::MOV64rr, 8687 X86::NOT64r, X86::RAX, 8688 X86::GR64RegisterClass); 8689 case X86::ATOMNAND64: 8690 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8691 X86::AND64ri32, X86::MOV64rm, 8692 X86::LCMPXCHG64, X86::MOV64rr, 8693 X86::NOT64r, X86::RAX, 8694 X86::GR64RegisterClass, true); 8695 case X86::ATOMMIN64: 8696 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 8697 case X86::ATOMMAX64: 8698 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 8699 case X86::ATOMUMIN64: 8700 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 8701 case X86::ATOMUMAX64: 8702 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 8703 8704 // This group does 64-bit operations on a 32-bit host. 8705 case X86::ATOMAND6432: 8706 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8707 X86::AND32rr, X86::AND32rr, 8708 X86::AND32ri, X86::AND32ri, 8709 false); 8710 case X86::ATOMOR6432: 8711 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8712 X86::OR32rr, X86::OR32rr, 8713 X86::OR32ri, X86::OR32ri, 8714 false); 8715 case X86::ATOMXOR6432: 8716 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8717 X86::XOR32rr, X86::XOR32rr, 8718 X86::XOR32ri, X86::XOR32ri, 8719 false); 8720 case X86::ATOMNAND6432: 8721 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8722 X86::AND32rr, X86::AND32rr, 8723 X86::AND32ri, X86::AND32ri, 8724 true); 8725 case X86::ATOMADD6432: 8726 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8727 X86::ADD32rr, X86::ADC32rr, 8728 X86::ADD32ri, X86::ADC32ri, 8729 false); 8730 case X86::ATOMSUB6432: 8731 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8732 X86::SUB32rr, X86::SBB32rr, 8733 X86::SUB32ri, X86::SBB32ri, 8734 false); 8735 case X86::ATOMSWAP6432: 8736 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8737 X86::MOV32rr, X86::MOV32rr, 8738 X86::MOV32ri, X86::MOV32ri, 8739 false); 8740 case X86::VASTART_SAVE_XMM_REGS: 8741 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 8742 } 8743} 8744 8745//===----------------------------------------------------------------------===// 8746// X86 Optimization Hooks 8747//===----------------------------------------------------------------------===// 8748 8749void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8750 const APInt &Mask, 8751 APInt &KnownZero, 8752 APInt &KnownOne, 8753 const SelectionDAG &DAG, 8754 unsigned Depth) const { 8755 unsigned Opc = Op.getOpcode(); 8756 assert((Opc >= ISD::BUILTIN_OP_END || 8757 Opc == ISD::INTRINSIC_WO_CHAIN || 8758 Opc == ISD::INTRINSIC_W_CHAIN || 8759 Opc == ISD::INTRINSIC_VOID) && 8760 "Should use MaskedValueIsZero if you don't know whether Op" 8761 " is a target node!"); 8762 8763 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 8764 switch (Opc) { 8765 default: break; 8766 case X86ISD::ADD: 8767 case X86ISD::SUB: 8768 case X86ISD::SMUL: 8769 case X86ISD::UMUL: 8770 case X86ISD::INC: 8771 case X86ISD::DEC: 8772 case X86ISD::OR: 8773 case X86ISD::XOR: 8774 case X86ISD::AND: 8775 // These nodes' second result is a boolean. 8776 if (Op.getResNo() == 0) 8777 break; 8778 // Fallthrough 8779 case X86ISD::SETCC: 8780 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 8781 Mask.getBitWidth() - 1); 8782 break; 8783 } 8784} 8785 8786/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 8787/// node is a GlobalAddress + offset. 8788bool X86TargetLowering::isGAPlusOffset(SDNode *N, 8789 GlobalValue* &GA, int64_t &Offset) const{ 8790 if (N->getOpcode() == X86ISD::Wrapper) { 8791 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 8792 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 8793 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 8794 return true; 8795 } 8796 } 8797 return TargetLowering::isGAPlusOffset(N, GA, Offset); 8798} 8799 8800static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, 8801 EVT EltVT, LoadSDNode *&LDBase, 8802 unsigned &LastLoadedElt, 8803 SelectionDAG &DAG, MachineFrameInfo *MFI, 8804 const TargetLowering &TLI) { 8805 LDBase = NULL; 8806 LastLoadedElt = -1U; 8807 for (unsigned i = 0; i < NumElems; ++i) { 8808 if (N->getMaskElt(i) < 0) { 8809 if (!LDBase) 8810 return false; 8811 continue; 8812 } 8813 8814 SDValue Elt = DAG.getShuffleScalarElt(N, i); 8815 if (!Elt.getNode() || 8816 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 8817 return false; 8818 if (!LDBase) { 8819 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 8820 return false; 8821 LDBase = cast<LoadSDNode>(Elt.getNode()); 8822 LastLoadedElt = i; 8823 continue; 8824 } 8825 if (Elt.getOpcode() == ISD::UNDEF) 8826 continue; 8827 8828 LoadSDNode *LD = cast<LoadSDNode>(Elt); 8829 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 8830 return false; 8831 LastLoadedElt = i; 8832 } 8833 return true; 8834} 8835 8836/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 8837/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 8838/// if the load addresses are consecutive, non-overlapping, and in the right 8839/// order. In the case of v2i64, it will see if it can rewrite the 8840/// shuffle to be an appropriate build vector so it can take advantage of 8841// performBuildVectorCombine. 8842static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 8843 const TargetLowering &TLI) { 8844 DebugLoc dl = N->getDebugLoc(); 8845 EVT VT = N->getValueType(0); 8846 EVT EltVT = VT.getVectorElementType(); 8847 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8848 unsigned NumElems = VT.getVectorNumElements(); 8849 8850 if (VT.getSizeInBits() != 128) 8851 return SDValue(); 8852 8853 // Try to combine a vector_shuffle into a 128-bit load. 8854 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8855 LoadSDNode *LD = NULL; 8856 unsigned LastLoadedElt; 8857 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG, 8858 MFI, TLI)) 8859 return SDValue(); 8860 8861 if (LastLoadedElt == NumElems - 1) { 8862 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16) 8863 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8864 LD->getSrcValue(), LD->getSrcValueOffset(), 8865 LD->isVolatile(), LD->isNonTemporal(), 0); 8866 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8867 LD->getSrcValue(), LD->getSrcValueOffset(), 8868 LD->isVolatile(), LD->isNonTemporal(), 8869 LD->getAlignment()); 8870 } else if (NumElems == 4 && LastLoadedElt == 1) { 8871 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 8872 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 8873 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 8874 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 8875 } 8876 return SDValue(); 8877} 8878 8879/// PerformShuffleCombine - Detect vector gather/scatter index generation 8880/// and convert it from being a bunch of shuffles and extracts to a simple 8881/// store and scalar loads to extract the elements. 8882static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 8883 const TargetLowering &TLI) { 8884 SDValue InputVector = N->getOperand(0); 8885 8886 // Only operate on vectors of 4 elements, where the alternative shuffling 8887 // gets to be more expensive. 8888 if (InputVector.getValueType() != MVT::v4i32) 8889 return SDValue(); 8890 8891 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 8892 // single use which is a sign-extend or zero-extend, and all elements are 8893 // used. 8894 SmallVector<SDNode *, 4> Uses; 8895 unsigned ExtractedElements = 0; 8896 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 8897 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 8898 if (UI.getUse().getResNo() != InputVector.getResNo()) 8899 return SDValue(); 8900 8901 SDNode *Extract = *UI; 8902 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 8903 return SDValue(); 8904 8905 if (Extract->getValueType(0) != MVT::i32) 8906 return SDValue(); 8907 if (!Extract->hasOneUse()) 8908 return SDValue(); 8909 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 8910 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 8911 return SDValue(); 8912 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 8913 return SDValue(); 8914 8915 // Record which element was extracted. 8916 ExtractedElements |= 8917 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 8918 8919 Uses.push_back(Extract); 8920 } 8921 8922 // If not all the elements were used, this may not be worthwhile. 8923 if (ExtractedElements != 15) 8924 return SDValue(); 8925 8926 // Ok, we've now decided to do the transformation. 8927 DebugLoc dl = InputVector.getDebugLoc(); 8928 8929 // Store the value to a temporary stack slot. 8930 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 8931 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0, 8932 false, false, 0); 8933 8934 // Replace each use (extract) with a load of the appropriate element. 8935 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 8936 UE = Uses.end(); UI != UE; ++UI) { 8937 SDNode *Extract = *UI; 8938 8939 // Compute the element's address. 8940 SDValue Idx = Extract->getOperand(1); 8941 unsigned EltSize = 8942 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 8943 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 8944 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 8945 8946 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr); 8947 8948 // Load the scalar. 8949 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr, 8950 NULL, 0, false, false, 0); 8951 8952 // Replace the exact with the load. 8953 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 8954 } 8955 8956 // The replacement was made in place; don't return anything. 8957 return SDValue(); 8958} 8959 8960/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 8961static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 8962 const X86Subtarget *Subtarget) { 8963 DebugLoc DL = N->getDebugLoc(); 8964 SDValue Cond = N->getOperand(0); 8965 // Get the LHS/RHS of the select. 8966 SDValue LHS = N->getOperand(1); 8967 SDValue RHS = N->getOperand(2); 8968 8969 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 8970 // instructions match the semantics of the common C idiom x<y?x:y but not 8971 // x<=y?x:y, because of how they handle negative zero (which can be 8972 // ignored in unsafe-math mode). 8973 if (Subtarget->hasSSE2() && 8974 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 8975 Cond.getOpcode() == ISD::SETCC) { 8976 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 8977 8978 unsigned Opcode = 0; 8979 // Check for x CC y ? x : y. 8980 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 8981 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 8982 switch (CC) { 8983 default: break; 8984 case ISD::SETULT: 8985 // Converting this to a min would handle NaNs incorrectly, and swapping 8986 // the operands would cause it to handle comparisons between positive 8987 // and negative zero incorrectly. 8988 if (!FiniteOnlyFPMath() && 8989 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) { 8990 if (!UnsafeFPMath && 8991 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 8992 break; 8993 std::swap(LHS, RHS); 8994 } 8995 Opcode = X86ISD::FMIN; 8996 break; 8997 case ISD::SETOLE: 8998 // Converting this to a min would handle comparisons between positive 8999 // and negative zero incorrectly. 9000 if (!UnsafeFPMath && 9001 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 9002 break; 9003 Opcode = X86ISD::FMIN; 9004 break; 9005 case ISD::SETULE: 9006 // Converting this to a min would handle both negative zeros and NaNs 9007 // incorrectly, but we can swap the operands to fix both. 9008 std::swap(LHS, RHS); 9009 case ISD::SETOLT: 9010 case ISD::SETLT: 9011 case ISD::SETLE: 9012 Opcode = X86ISD::FMIN; 9013 break; 9014 9015 case ISD::SETOGE: 9016 // Converting this to a max would handle comparisons between positive 9017 // and negative zero incorrectly. 9018 if (!UnsafeFPMath && 9019 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS)) 9020 break; 9021 Opcode = X86ISD::FMAX; 9022 break; 9023 case ISD::SETUGT: 9024 // Converting this to a max would handle NaNs incorrectly, and swapping 9025 // the operands would cause it to handle comparisons between positive 9026 // and negative zero incorrectly. 9027 if (!FiniteOnlyFPMath() && 9028 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) { 9029 if (!UnsafeFPMath && 9030 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9031 break; 9032 std::swap(LHS, RHS); 9033 } 9034 Opcode = X86ISD::FMAX; 9035 break; 9036 case ISD::SETUGE: 9037 // Converting this to a max would handle both negative zeros and NaNs 9038 // incorrectly, but we can swap the operands to fix both. 9039 std::swap(LHS, RHS); 9040 case ISD::SETOGT: 9041 case ISD::SETGT: 9042 case ISD::SETGE: 9043 Opcode = X86ISD::FMAX; 9044 break; 9045 } 9046 // Check for x CC y ? y : x -- a min/max with reversed arms. 9047 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 9048 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 9049 switch (CC) { 9050 default: break; 9051 case ISD::SETOGE: 9052 // Converting this to a min would handle comparisons between positive 9053 // and negative zero incorrectly, and swapping the operands would 9054 // cause it to handle NaNs incorrectly. 9055 if (!UnsafeFPMath && 9056 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 9057 if (!FiniteOnlyFPMath() && 9058 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9059 break; 9060 std::swap(LHS, RHS); 9061 } 9062 Opcode = X86ISD::FMIN; 9063 break; 9064 case ISD::SETUGT: 9065 // Converting this to a min would handle NaNs incorrectly. 9066 if (!UnsafeFPMath && 9067 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9068 break; 9069 Opcode = X86ISD::FMIN; 9070 break; 9071 case ISD::SETUGE: 9072 // Converting this to a min would handle both negative zeros and NaNs 9073 // incorrectly, but we can swap the operands to fix both. 9074 std::swap(LHS, RHS); 9075 case ISD::SETOGT: 9076 case ISD::SETGT: 9077 case ISD::SETGE: 9078 Opcode = X86ISD::FMIN; 9079 break; 9080 9081 case ISD::SETULT: 9082 // Converting this to a max would handle NaNs incorrectly. 9083 if (!FiniteOnlyFPMath() && 9084 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9085 break; 9086 Opcode = X86ISD::FMAX; 9087 break; 9088 case ISD::SETOLE: 9089 // Converting this to a max would handle comparisons between positive 9090 // and negative zero incorrectly, and swapping the operands would 9091 // cause it to handle NaNs incorrectly. 9092 if (!UnsafeFPMath && 9093 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 9094 if (!FiniteOnlyFPMath() && 9095 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9096 break; 9097 std::swap(LHS, RHS); 9098 } 9099 Opcode = X86ISD::FMAX; 9100 break; 9101 case ISD::SETULE: 9102 // Converting this to a max would handle both negative zeros and NaNs 9103 // incorrectly, but we can swap the operands to fix both. 9104 std::swap(LHS, RHS); 9105 case ISD::SETOLT: 9106 case ISD::SETLT: 9107 case ISD::SETLE: 9108 Opcode = X86ISD::FMAX; 9109 break; 9110 } 9111 } 9112 9113 if (Opcode) 9114 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 9115 } 9116 9117 // If this is a select between two integer constants, try to do some 9118 // optimizations. 9119 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 9120 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 9121 // Don't do this for crazy integer types. 9122 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 9123 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 9124 // so that TrueC (the true value) is larger than FalseC. 9125 bool NeedsCondInvert = false; 9126 9127 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 9128 // Efficiently invertible. 9129 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 9130 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 9131 isa<ConstantSDNode>(Cond.getOperand(1))))) { 9132 NeedsCondInvert = true; 9133 std::swap(TrueC, FalseC); 9134 } 9135 9136 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 9137 if (FalseC->getAPIntValue() == 0 && 9138 TrueC->getAPIntValue().isPowerOf2()) { 9139 if (NeedsCondInvert) // Invert the condition if needed. 9140 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9141 DAG.getConstant(1, Cond.getValueType())); 9142 9143 // Zero extend the condition if needed. 9144 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 9145 9146 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9147 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 9148 DAG.getConstant(ShAmt, MVT::i8)); 9149 } 9150 9151 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 9152 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9153 if (NeedsCondInvert) // Invert the condition if needed. 9154 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9155 DAG.getConstant(1, Cond.getValueType())); 9156 9157 // Zero extend the condition if needed. 9158 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9159 FalseC->getValueType(0), Cond); 9160 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9161 SDValue(FalseC, 0)); 9162 } 9163 9164 // Optimize cases that will turn into an LEA instruction. This requires 9165 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9166 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9167 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9168 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9169 9170 bool isFastMultiplier = false; 9171 if (Diff < 10) { 9172 switch ((unsigned char)Diff) { 9173 default: break; 9174 case 1: // result = add base, cond 9175 case 2: // result = lea base( , cond*2) 9176 case 3: // result = lea base(cond, cond*2) 9177 case 4: // result = lea base( , cond*4) 9178 case 5: // result = lea base(cond, cond*4) 9179 case 8: // result = lea base( , cond*8) 9180 case 9: // result = lea base(cond, cond*8) 9181 isFastMultiplier = true; 9182 break; 9183 } 9184 } 9185 9186 if (isFastMultiplier) { 9187 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9188 if (NeedsCondInvert) // Invert the condition if needed. 9189 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9190 DAG.getConstant(1, Cond.getValueType())); 9191 9192 // Zero extend the condition if needed. 9193 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9194 Cond); 9195 // Scale the condition by the difference. 9196 if (Diff != 1) 9197 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9198 DAG.getConstant(Diff, Cond.getValueType())); 9199 9200 // Add the base if non-zero. 9201 if (FalseC->getAPIntValue() != 0) 9202 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9203 SDValue(FalseC, 0)); 9204 return Cond; 9205 } 9206 } 9207 } 9208 } 9209 9210 return SDValue(); 9211} 9212 9213/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 9214static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 9215 TargetLowering::DAGCombinerInfo &DCI) { 9216 DebugLoc DL = N->getDebugLoc(); 9217 9218 // If the flag operand isn't dead, don't touch this CMOV. 9219 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 9220 return SDValue(); 9221 9222 // If this is a select between two integer constants, try to do some 9223 // optimizations. Note that the operands are ordered the opposite of SELECT 9224 // operands. 9225 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 9226 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 9227 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 9228 // larger than FalseC (the false value). 9229 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 9230 9231 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 9232 CC = X86::GetOppositeBranchCondition(CC); 9233 std::swap(TrueC, FalseC); 9234 } 9235 9236 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 9237 // This is efficient for any integer data type (including i8/i16) and 9238 // shift amount. 9239 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 9240 SDValue Cond = N->getOperand(3); 9241 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9242 DAG.getConstant(CC, MVT::i8), Cond); 9243 9244 // Zero extend the condition if needed. 9245 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 9246 9247 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9248 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 9249 DAG.getConstant(ShAmt, MVT::i8)); 9250 if (N->getNumValues() == 2) // Dead flag value? 9251 return DCI.CombineTo(N, Cond, SDValue()); 9252 return Cond; 9253 } 9254 9255 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 9256 // for any integer data type, including i8/i16. 9257 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9258 SDValue Cond = N->getOperand(3); 9259 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9260 DAG.getConstant(CC, MVT::i8), Cond); 9261 9262 // Zero extend the condition if needed. 9263 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9264 FalseC->getValueType(0), Cond); 9265 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9266 SDValue(FalseC, 0)); 9267 9268 if (N->getNumValues() == 2) // Dead flag value? 9269 return DCI.CombineTo(N, Cond, SDValue()); 9270 return Cond; 9271 } 9272 9273 // Optimize cases that will turn into an LEA instruction. This requires 9274 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9275 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9276 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9277 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9278 9279 bool isFastMultiplier = false; 9280 if (Diff < 10) { 9281 switch ((unsigned char)Diff) { 9282 default: break; 9283 case 1: // result = add base, cond 9284 case 2: // result = lea base( , cond*2) 9285 case 3: // result = lea base(cond, cond*2) 9286 case 4: // result = lea base( , cond*4) 9287 case 5: // result = lea base(cond, cond*4) 9288 case 8: // result = lea base( , cond*8) 9289 case 9: // result = lea base(cond, cond*8) 9290 isFastMultiplier = true; 9291 break; 9292 } 9293 } 9294 9295 if (isFastMultiplier) { 9296 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9297 SDValue Cond = N->getOperand(3); 9298 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9299 DAG.getConstant(CC, MVT::i8), Cond); 9300 // Zero extend the condition if needed. 9301 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9302 Cond); 9303 // Scale the condition by the difference. 9304 if (Diff != 1) 9305 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9306 DAG.getConstant(Diff, Cond.getValueType())); 9307 9308 // Add the base if non-zero. 9309 if (FalseC->getAPIntValue() != 0) 9310 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9311 SDValue(FalseC, 0)); 9312 if (N->getNumValues() == 2) // Dead flag value? 9313 return DCI.CombineTo(N, Cond, SDValue()); 9314 return Cond; 9315 } 9316 } 9317 } 9318 } 9319 return SDValue(); 9320} 9321 9322 9323/// PerformMulCombine - Optimize a single multiply with constant into two 9324/// in order to implement it with two cheaper instructions, e.g. 9325/// LEA + SHL, LEA + LEA. 9326static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 9327 TargetLowering::DAGCombinerInfo &DCI) { 9328 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 9329 return SDValue(); 9330 9331 EVT VT = N->getValueType(0); 9332 if (VT != MVT::i64) 9333 return SDValue(); 9334 9335 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9336 if (!C) 9337 return SDValue(); 9338 uint64_t MulAmt = C->getZExtValue(); 9339 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 9340 return SDValue(); 9341 9342 uint64_t MulAmt1 = 0; 9343 uint64_t MulAmt2 = 0; 9344 if ((MulAmt % 9) == 0) { 9345 MulAmt1 = 9; 9346 MulAmt2 = MulAmt / 9; 9347 } else if ((MulAmt % 5) == 0) { 9348 MulAmt1 = 5; 9349 MulAmt2 = MulAmt / 5; 9350 } else if ((MulAmt % 3) == 0) { 9351 MulAmt1 = 3; 9352 MulAmt2 = MulAmt / 3; 9353 } 9354 if (MulAmt2 && 9355 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 9356 DebugLoc DL = N->getDebugLoc(); 9357 9358 if (isPowerOf2_64(MulAmt2) && 9359 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 9360 // If second multiplifer is pow2, issue it first. We want the multiply by 9361 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 9362 // is an add. 9363 std::swap(MulAmt1, MulAmt2); 9364 9365 SDValue NewMul; 9366 if (isPowerOf2_64(MulAmt1)) 9367 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 9368 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 9369 else 9370 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 9371 DAG.getConstant(MulAmt1, VT)); 9372 9373 if (isPowerOf2_64(MulAmt2)) 9374 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 9375 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 9376 else 9377 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 9378 DAG.getConstant(MulAmt2, VT)); 9379 9380 // Do not add new nodes to DAG combiner worklist. 9381 DCI.CombineTo(N, NewMul, false); 9382 } 9383 return SDValue(); 9384} 9385 9386static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 9387 SDValue N0 = N->getOperand(0); 9388 SDValue N1 = N->getOperand(1); 9389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 9390 EVT VT = N0.getValueType(); 9391 9392 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 9393 // since the result of setcc_c is all zero's or all ones. 9394 if (N1C && N0.getOpcode() == ISD::AND && 9395 N0.getOperand(1).getOpcode() == ISD::Constant) { 9396 SDValue N00 = N0.getOperand(0); 9397 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 9398 ((N00.getOpcode() == ISD::ANY_EXTEND || 9399 N00.getOpcode() == ISD::ZERO_EXTEND) && 9400 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 9401 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 9402 APInt ShAmt = N1C->getAPIntValue(); 9403 Mask = Mask.shl(ShAmt); 9404 if (Mask != 0) 9405 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 9406 N00, DAG.getConstant(Mask, VT)); 9407 } 9408 } 9409 9410 return SDValue(); 9411} 9412 9413/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 9414/// when possible. 9415static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 9416 const X86Subtarget *Subtarget) { 9417 EVT VT = N->getValueType(0); 9418 if (!VT.isVector() && VT.isInteger() && 9419 N->getOpcode() == ISD::SHL) 9420 return PerformSHLCombine(N, DAG); 9421 9422 // On X86 with SSE2 support, we can transform this to a vector shift if 9423 // all elements are shifted by the same amount. We can't do this in legalize 9424 // because the a constant vector is typically transformed to a constant pool 9425 // so we have no knowledge of the shift amount. 9426 if (!Subtarget->hasSSE2()) 9427 return SDValue(); 9428 9429 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 9430 return SDValue(); 9431 9432 SDValue ShAmtOp = N->getOperand(1); 9433 EVT EltVT = VT.getVectorElementType(); 9434 DebugLoc DL = N->getDebugLoc(); 9435 SDValue BaseShAmt = SDValue(); 9436 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 9437 unsigned NumElts = VT.getVectorNumElements(); 9438 unsigned i = 0; 9439 for (; i != NumElts; ++i) { 9440 SDValue Arg = ShAmtOp.getOperand(i); 9441 if (Arg.getOpcode() == ISD::UNDEF) continue; 9442 BaseShAmt = Arg; 9443 break; 9444 } 9445 for (; i != NumElts; ++i) { 9446 SDValue Arg = ShAmtOp.getOperand(i); 9447 if (Arg.getOpcode() == ISD::UNDEF) continue; 9448 if (Arg != BaseShAmt) { 9449 return SDValue(); 9450 } 9451 } 9452 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 9453 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 9454 SDValue InVec = ShAmtOp.getOperand(0); 9455 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 9456 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 9457 unsigned i = 0; 9458 for (; i != NumElts; ++i) { 9459 SDValue Arg = InVec.getOperand(i); 9460 if (Arg.getOpcode() == ISD::UNDEF) continue; 9461 BaseShAmt = Arg; 9462 break; 9463 } 9464 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 9465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 9466 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 9467 if (C->getZExtValue() == SplatIdx) 9468 BaseShAmt = InVec.getOperand(1); 9469 } 9470 } 9471 if (BaseShAmt.getNode() == 0) 9472 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 9473 DAG.getIntPtrConstant(0)); 9474 } else 9475 return SDValue(); 9476 9477 // The shift amount is an i32. 9478 if (EltVT.bitsGT(MVT::i32)) 9479 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 9480 else if (EltVT.bitsLT(MVT::i32)) 9481 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 9482 9483 // The shift amount is identical so we can do a vector shift. 9484 SDValue ValOp = N->getOperand(0); 9485 switch (N->getOpcode()) { 9486 default: 9487 llvm_unreachable("Unknown shift opcode!"); 9488 break; 9489 case ISD::SHL: 9490 if (VT == MVT::v2i64) 9491 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9492 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9493 ValOp, BaseShAmt); 9494 if (VT == MVT::v4i32) 9495 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9496 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9497 ValOp, BaseShAmt); 9498 if (VT == MVT::v8i16) 9499 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9500 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9501 ValOp, BaseShAmt); 9502 break; 9503 case ISD::SRA: 9504 if (VT == MVT::v4i32) 9505 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9506 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9507 ValOp, BaseShAmt); 9508 if (VT == MVT::v8i16) 9509 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9510 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9511 ValOp, BaseShAmt); 9512 break; 9513 case ISD::SRL: 9514 if (VT == MVT::v2i64) 9515 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9516 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9517 ValOp, BaseShAmt); 9518 if (VT == MVT::v4i32) 9519 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9520 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9521 ValOp, BaseShAmt); 9522 if (VT == MVT::v8i16) 9523 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9524 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9525 ValOp, BaseShAmt); 9526 break; 9527 } 9528 return SDValue(); 9529} 9530 9531static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 9532 const X86Subtarget *Subtarget) { 9533 EVT VT = N->getValueType(0); 9534 if (VT != MVT::i64 || !Subtarget->is64Bit()) 9535 return SDValue(); 9536 9537 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 9538 SDValue N0 = N->getOperand(0); 9539 SDValue N1 = N->getOperand(1); 9540 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 9541 std::swap(N0, N1); 9542 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 9543 return SDValue(); 9544 9545 SDValue ShAmt0 = N0.getOperand(1); 9546 if (ShAmt0.getValueType() != MVT::i8) 9547 return SDValue(); 9548 SDValue ShAmt1 = N1.getOperand(1); 9549 if (ShAmt1.getValueType() != MVT::i8) 9550 return SDValue(); 9551 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 9552 ShAmt0 = ShAmt0.getOperand(0); 9553 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 9554 ShAmt1 = ShAmt1.getOperand(0); 9555 9556 DebugLoc DL = N->getDebugLoc(); 9557 unsigned Opc = X86ISD::SHLD; 9558 SDValue Op0 = N0.getOperand(0); 9559 SDValue Op1 = N1.getOperand(0); 9560 if (ShAmt0.getOpcode() == ISD::SUB) { 9561 Opc = X86ISD::SHRD; 9562 std::swap(Op0, Op1); 9563 std::swap(ShAmt0, ShAmt1); 9564 } 9565 9566 if (ShAmt1.getOpcode() == ISD::SUB) { 9567 SDValue Sum = ShAmt1.getOperand(0); 9568 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 9569 if (SumC->getSExtValue() == 64 && 9570 ShAmt1.getOperand(1) == ShAmt0) 9571 return DAG.getNode(Opc, DL, VT, 9572 Op0, Op1, 9573 DAG.getNode(ISD::TRUNCATE, DL, 9574 MVT::i8, ShAmt0)); 9575 } 9576 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 9577 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 9578 if (ShAmt0C && 9579 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64) 9580 return DAG.getNode(Opc, DL, VT, 9581 N0.getOperand(0), N1.getOperand(0), 9582 DAG.getNode(ISD::TRUNCATE, DL, 9583 MVT::i8, ShAmt0)); 9584 } 9585 9586 return SDValue(); 9587} 9588 9589/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 9590static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 9591 const X86Subtarget *Subtarget) { 9592 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 9593 // the FP state in cases where an emms may be missing. 9594 // A preferable solution to the general problem is to figure out the right 9595 // places to insert EMMS. This qualifies as a quick hack. 9596 9597 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 9598 StoreSDNode *St = cast<StoreSDNode>(N); 9599 EVT VT = St->getValue().getValueType(); 9600 if (VT.getSizeInBits() != 64) 9601 return SDValue(); 9602 9603 const Function *F = DAG.getMachineFunction().getFunction(); 9604 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 9605 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 9606 && Subtarget->hasSSE2(); 9607 if ((VT.isVector() || 9608 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 9609 isa<LoadSDNode>(St->getValue()) && 9610 !cast<LoadSDNode>(St->getValue())->isVolatile() && 9611 St->getChain().hasOneUse() && !St->isVolatile()) { 9612 SDNode* LdVal = St->getValue().getNode(); 9613 LoadSDNode *Ld = 0; 9614 int TokenFactorIndex = -1; 9615 SmallVector<SDValue, 8> Ops; 9616 SDNode* ChainVal = St->getChain().getNode(); 9617 // Must be a store of a load. We currently handle two cases: the load 9618 // is a direct child, and it's under an intervening TokenFactor. It is 9619 // possible to dig deeper under nested TokenFactors. 9620 if (ChainVal == LdVal) 9621 Ld = cast<LoadSDNode>(St->getChain()); 9622 else if (St->getValue().hasOneUse() && 9623 ChainVal->getOpcode() == ISD::TokenFactor) { 9624 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 9625 if (ChainVal->getOperand(i).getNode() == LdVal) { 9626 TokenFactorIndex = i; 9627 Ld = cast<LoadSDNode>(St->getValue()); 9628 } else 9629 Ops.push_back(ChainVal->getOperand(i)); 9630 } 9631 } 9632 9633 if (!Ld || !ISD::isNormalLoad(Ld)) 9634 return SDValue(); 9635 9636 // If this is not the MMX case, i.e. we are just turning i64 load/store 9637 // into f64 load/store, avoid the transformation if there are multiple 9638 // uses of the loaded value. 9639 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 9640 return SDValue(); 9641 9642 DebugLoc LdDL = Ld->getDebugLoc(); 9643 DebugLoc StDL = N->getDebugLoc(); 9644 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 9645 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 9646 // pair instead. 9647 if (Subtarget->is64Bit() || F64IsLegal) { 9648 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 9649 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 9650 Ld->getBasePtr(), Ld->getSrcValue(), 9651 Ld->getSrcValueOffset(), Ld->isVolatile(), 9652 Ld->isNonTemporal(), Ld->getAlignment()); 9653 SDValue NewChain = NewLd.getValue(1); 9654 if (TokenFactorIndex != -1) { 9655 Ops.push_back(NewChain); 9656 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9657 Ops.size()); 9658 } 9659 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 9660 St->getSrcValue(), St->getSrcValueOffset(), 9661 St->isVolatile(), St->isNonTemporal(), 9662 St->getAlignment()); 9663 } 9664 9665 // Otherwise, lower to two pairs of 32-bit loads / stores. 9666 SDValue LoAddr = Ld->getBasePtr(); 9667 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 9668 DAG.getConstant(4, MVT::i32)); 9669 9670 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 9671 Ld->getSrcValue(), Ld->getSrcValueOffset(), 9672 Ld->isVolatile(), Ld->isNonTemporal(), 9673 Ld->getAlignment()); 9674 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 9675 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 9676 Ld->isVolatile(), Ld->isNonTemporal(), 9677 MinAlign(Ld->getAlignment(), 4)); 9678 9679 SDValue NewChain = LoLd.getValue(1); 9680 if (TokenFactorIndex != -1) { 9681 Ops.push_back(LoLd); 9682 Ops.push_back(HiLd); 9683 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9684 Ops.size()); 9685 } 9686 9687 LoAddr = St->getBasePtr(); 9688 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 9689 DAG.getConstant(4, MVT::i32)); 9690 9691 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 9692 St->getSrcValue(), St->getSrcValueOffset(), 9693 St->isVolatile(), St->isNonTemporal(), 9694 St->getAlignment()); 9695 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 9696 St->getSrcValue(), 9697 St->getSrcValueOffset() + 4, 9698 St->isVolatile(), 9699 St->isNonTemporal(), 9700 MinAlign(St->getAlignment(), 4)); 9701 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 9702 } 9703 return SDValue(); 9704} 9705 9706/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 9707/// X86ISD::FXOR nodes. 9708static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 9709 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 9710 // F[X]OR(0.0, x) -> x 9711 // F[X]OR(x, 0.0) -> x 9712 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9713 if (C->getValueAPF().isPosZero()) 9714 return N->getOperand(1); 9715 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9716 if (C->getValueAPF().isPosZero()) 9717 return N->getOperand(0); 9718 return SDValue(); 9719} 9720 9721/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 9722static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 9723 // FAND(0.0, x) -> 0.0 9724 // FAND(x, 0.0) -> 0.0 9725 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9726 if (C->getValueAPF().isPosZero()) 9727 return N->getOperand(0); 9728 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9729 if (C->getValueAPF().isPosZero()) 9730 return N->getOperand(1); 9731 return SDValue(); 9732} 9733 9734static SDValue PerformBTCombine(SDNode *N, 9735 SelectionDAG &DAG, 9736 TargetLowering::DAGCombinerInfo &DCI) { 9737 // BT ignores high bits in the bit index operand. 9738 SDValue Op1 = N->getOperand(1); 9739 if (Op1.hasOneUse()) { 9740 unsigned BitWidth = Op1.getValueSizeInBits(); 9741 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 9742 APInt KnownZero, KnownOne; 9743 TargetLowering::TargetLoweringOpt TLO(DAG); 9744 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9745 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 9746 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 9747 DCI.CommitTargetLoweringOpt(TLO); 9748 } 9749 return SDValue(); 9750} 9751 9752static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 9753 SDValue Op = N->getOperand(0); 9754 if (Op.getOpcode() == ISD::BIT_CONVERT) 9755 Op = Op.getOperand(0); 9756 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 9757 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 9758 VT.getVectorElementType().getSizeInBits() == 9759 OpVT.getVectorElementType().getSizeInBits()) { 9760 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 9761 } 9762 return SDValue(); 9763} 9764 9765// On X86 and X86-64, atomic operations are lowered to locked instructions. 9766// Locked instructions, in turn, have implicit fence semantics (all memory 9767// operations are flushed before issuing the locked instruction, and the 9768// are not buffered), so we can fold away the common pattern of 9769// fence-atomic-fence. 9770static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) { 9771 SDValue atomic = N->getOperand(0); 9772 switch (atomic.getOpcode()) { 9773 case ISD::ATOMIC_CMP_SWAP: 9774 case ISD::ATOMIC_SWAP: 9775 case ISD::ATOMIC_LOAD_ADD: 9776 case ISD::ATOMIC_LOAD_SUB: 9777 case ISD::ATOMIC_LOAD_AND: 9778 case ISD::ATOMIC_LOAD_OR: 9779 case ISD::ATOMIC_LOAD_XOR: 9780 case ISD::ATOMIC_LOAD_NAND: 9781 case ISD::ATOMIC_LOAD_MIN: 9782 case ISD::ATOMIC_LOAD_MAX: 9783 case ISD::ATOMIC_LOAD_UMIN: 9784 case ISD::ATOMIC_LOAD_UMAX: 9785 break; 9786 default: 9787 return SDValue(); 9788 } 9789 9790 SDValue fence = atomic.getOperand(0); 9791 if (fence.getOpcode() != ISD::MEMBARRIER) 9792 return SDValue(); 9793 9794 switch (atomic.getOpcode()) { 9795 case ISD::ATOMIC_CMP_SWAP: 9796 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9797 atomic.getOperand(1), atomic.getOperand(2), 9798 atomic.getOperand(3)); 9799 case ISD::ATOMIC_SWAP: 9800 case ISD::ATOMIC_LOAD_ADD: 9801 case ISD::ATOMIC_LOAD_SUB: 9802 case ISD::ATOMIC_LOAD_AND: 9803 case ISD::ATOMIC_LOAD_OR: 9804 case ISD::ATOMIC_LOAD_XOR: 9805 case ISD::ATOMIC_LOAD_NAND: 9806 case ISD::ATOMIC_LOAD_MIN: 9807 case ISD::ATOMIC_LOAD_MAX: 9808 case ISD::ATOMIC_LOAD_UMIN: 9809 case ISD::ATOMIC_LOAD_UMAX: 9810 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9811 atomic.getOperand(1), atomic.getOperand(2)); 9812 default: 9813 return SDValue(); 9814 } 9815} 9816 9817static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 9818 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 9819 // (and (i32 x86isd::setcc_carry), 1) 9820 // This eliminates the zext. This transformation is necessary because 9821 // ISD::SETCC is always legalized to i8. 9822 DebugLoc dl = N->getDebugLoc(); 9823 SDValue N0 = N->getOperand(0); 9824 EVT VT = N->getValueType(0); 9825 if (N0.getOpcode() == ISD::AND && 9826 N0.hasOneUse() && 9827 N0.getOperand(0).hasOneUse()) { 9828 SDValue N00 = N0.getOperand(0); 9829 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 9830 return SDValue(); 9831 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 9832 if (!C || C->getZExtValue() != 1) 9833 return SDValue(); 9834 return DAG.getNode(ISD::AND, dl, VT, 9835 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 9836 N00.getOperand(0), N00.getOperand(1)), 9837 DAG.getConstant(1, VT)); 9838 } 9839 9840 return SDValue(); 9841} 9842 9843SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 9844 DAGCombinerInfo &DCI) const { 9845 SelectionDAG &DAG = DCI.DAG; 9846 switch (N->getOpcode()) { 9847 default: break; 9848 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 9849 case ISD::EXTRACT_VECTOR_ELT: 9850 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 9851 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 9852 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 9853 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 9854 case ISD::SHL: 9855 case ISD::SRA: 9856 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 9857 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget); 9858 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 9859 case X86ISD::FXOR: 9860 case X86ISD::FOR: return PerformFORCombine(N, DAG); 9861 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 9862 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 9863 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 9864 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG); 9865 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 9866 } 9867 9868 return SDValue(); 9869} 9870 9871//===----------------------------------------------------------------------===// 9872// X86 Inline Assembly Support 9873//===----------------------------------------------------------------------===// 9874 9875static bool LowerToBSwap(CallInst *CI) { 9876 // FIXME: this should verify that we are targetting a 486 or better. If not, 9877 // we will turn this bswap into something that will be lowered to logical ops 9878 // instead of emitting the bswap asm. For now, we don't support 486 or lower 9879 // so don't worry about this. 9880 9881 // Verify this is a simple bswap. 9882 if (CI->getNumOperands() != 2 || 9883 CI->getType() != CI->getOperand(1)->getType() || 9884 !CI->getType()->isIntegerTy()) 9885 return false; 9886 9887 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 9888 if (!Ty || Ty->getBitWidth() % 16 != 0) 9889 return false; 9890 9891 // Okay, we can do this xform, do so now. 9892 const Type *Tys[] = { Ty }; 9893 Module *M = CI->getParent()->getParent()->getParent(); 9894 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 9895 9896 Value *Op = CI->getOperand(1); 9897 Op = CallInst::Create(Int, Op, CI->getName(), CI); 9898 9899 CI->replaceAllUsesWith(Op); 9900 CI->eraseFromParent(); 9901 return true; 9902} 9903 9904bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 9905 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 9906 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 9907 9908 std::string AsmStr = IA->getAsmString(); 9909 9910 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 9911 SmallVector<StringRef, 4> AsmPieces; 9912 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 9913 9914 switch (AsmPieces.size()) { 9915 default: return false; 9916 case 1: 9917 AsmStr = AsmPieces[0]; 9918 AsmPieces.clear(); 9919 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 9920 9921 // bswap $0 9922 if (AsmPieces.size() == 2 && 9923 (AsmPieces[0] == "bswap" || 9924 AsmPieces[0] == "bswapq" || 9925 AsmPieces[0] == "bswapl") && 9926 (AsmPieces[1] == "$0" || 9927 AsmPieces[1] == "${0:q}")) { 9928 // No need to check constraints, nothing other than the equivalent of 9929 // "=r,0" would be valid here. 9930 return LowerToBSwap(CI); 9931 } 9932 // rorw $$8, ${0:w} --> llvm.bswap.i16 9933 if (CI->getType()->isIntegerTy(16) && 9934 AsmPieces.size() == 3 && 9935 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 9936 AsmPieces[1] == "$$8," && 9937 AsmPieces[2] == "${0:w}" && 9938 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 9939 AsmPieces.clear(); 9940 const std::string &Constraints = IA->getConstraintString(); 9941 SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); 9942 std::sort(AsmPieces.begin(), AsmPieces.end()); 9943 if (AsmPieces.size() == 4 && 9944 AsmPieces[0] == "~{cc}" && 9945 AsmPieces[1] == "~{dirflag}" && 9946 AsmPieces[2] == "~{flags}" && 9947 AsmPieces[3] == "~{fpsr}") { 9948 return LowerToBSwap(CI); 9949 } 9950 } 9951 break; 9952 case 3: 9953 if (CI->getType()->isIntegerTy(64) && 9954 Constraints.size() >= 2 && 9955 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 9956 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 9957 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 9958 SmallVector<StringRef, 4> Words; 9959 SplitString(AsmPieces[0], Words, " \t"); 9960 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 9961 Words.clear(); 9962 SplitString(AsmPieces[1], Words, " \t"); 9963 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 9964 Words.clear(); 9965 SplitString(AsmPieces[2], Words, " \t,"); 9966 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 9967 Words[2] == "%edx") { 9968 return LowerToBSwap(CI); 9969 } 9970 } 9971 } 9972 } 9973 break; 9974 } 9975 return false; 9976} 9977 9978 9979 9980/// getConstraintType - Given a constraint letter, return the type of 9981/// constraint it is for this target. 9982X86TargetLowering::ConstraintType 9983X86TargetLowering::getConstraintType(const std::string &Constraint) const { 9984 if (Constraint.size() == 1) { 9985 switch (Constraint[0]) { 9986 case 'A': 9987 return C_Register; 9988 case 'f': 9989 case 'r': 9990 case 'R': 9991 case 'l': 9992 case 'q': 9993 case 'Q': 9994 case 'x': 9995 case 'y': 9996 case 'Y': 9997 return C_RegisterClass; 9998 case 'e': 9999 case 'Z': 10000 return C_Other; 10001 default: 10002 break; 10003 } 10004 } 10005 return TargetLowering::getConstraintType(Constraint); 10006} 10007 10008/// LowerXConstraint - try to replace an X constraint, which matches anything, 10009/// with another that has more specific requirements based on the type of the 10010/// corresponding operand. 10011const char *X86TargetLowering:: 10012LowerXConstraint(EVT ConstraintVT) const { 10013 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 10014 // 'f' like normal targets. 10015 if (ConstraintVT.isFloatingPoint()) { 10016 if (Subtarget->hasSSE2()) 10017 return "Y"; 10018 if (Subtarget->hasSSE1()) 10019 return "x"; 10020 } 10021 10022 return TargetLowering::LowerXConstraint(ConstraintVT); 10023} 10024 10025/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 10026/// vector. If it is invalid, don't add anything to Ops. 10027void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 10028 char Constraint, 10029 bool hasMemory, 10030 std::vector<SDValue>&Ops, 10031 SelectionDAG &DAG) const { 10032 SDValue Result(0, 0); 10033 10034 switch (Constraint) { 10035 default: break; 10036 case 'I': 10037 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10038 if (C->getZExtValue() <= 31) { 10039 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10040 break; 10041 } 10042 } 10043 return; 10044 case 'J': 10045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10046 if (C->getZExtValue() <= 63) { 10047 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10048 break; 10049 } 10050 } 10051 return; 10052 case 'K': 10053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10054 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 10055 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10056 break; 10057 } 10058 } 10059 return; 10060 case 'N': 10061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10062 if (C->getZExtValue() <= 255) { 10063 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10064 break; 10065 } 10066 } 10067 return; 10068 case 'e': { 10069 // 32-bit signed value 10070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10071 const ConstantInt *CI = C->getConstantIntValue(); 10072 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10073 C->getSExtValue())) { 10074 // Widen to 64 bits here to get it sign extended. 10075 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 10076 break; 10077 } 10078 // FIXME gcc accepts some relocatable values here too, but only in certain 10079 // memory models; it's complicated. 10080 } 10081 return; 10082 } 10083 case 'Z': { 10084 // 32-bit unsigned value 10085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10086 const ConstantInt *CI = C->getConstantIntValue(); 10087 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10088 C->getZExtValue())) { 10089 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10090 break; 10091 } 10092 } 10093 // FIXME gcc accepts some relocatable values here too, but only in certain 10094 // memory models; it's complicated. 10095 return; 10096 } 10097 case 'i': { 10098 // Literal immediates are always ok. 10099 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 10100 // Widen to 64 bits here to get it sign extended. 10101 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 10102 break; 10103 } 10104 10105 // If we are in non-pic codegen mode, we allow the address of a global (with 10106 // an optional displacement) to be used with 'i'. 10107 GlobalAddressSDNode *GA = 0; 10108 int64_t Offset = 0; 10109 10110 // Match either (GA), (GA+C), (GA+C1+C2), etc. 10111 while (1) { 10112 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 10113 Offset += GA->getOffset(); 10114 break; 10115 } else if (Op.getOpcode() == ISD::ADD) { 10116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10117 Offset += C->getZExtValue(); 10118 Op = Op.getOperand(0); 10119 continue; 10120 } 10121 } else if (Op.getOpcode() == ISD::SUB) { 10122 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10123 Offset += -C->getZExtValue(); 10124 Op = Op.getOperand(0); 10125 continue; 10126 } 10127 } 10128 10129 // Otherwise, this isn't something we can handle, reject it. 10130 return; 10131 } 10132 10133 GlobalValue *GV = GA->getGlobal(); 10134 // If we require an extra load to get this address, as in PIC mode, we 10135 // can't accept it. 10136 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 10137 getTargetMachine()))) 10138 return; 10139 10140 if (hasMemory) 10141 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 10142 else 10143 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset); 10144 Result = Op; 10145 break; 10146 } 10147 } 10148 10149 if (Result.getNode()) { 10150 Ops.push_back(Result); 10151 return; 10152 } 10153 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 10154 Ops, DAG); 10155} 10156 10157std::vector<unsigned> X86TargetLowering:: 10158getRegClassForInlineAsmConstraint(const std::string &Constraint, 10159 EVT VT) const { 10160 if (Constraint.size() == 1) { 10161 // FIXME: not handling fp-stack yet! 10162 switch (Constraint[0]) { // GCC X86 Constraint Letters 10163 default: break; // Unknown constraint letter 10164 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 10165 if (Subtarget->is64Bit()) { 10166 if (VT == MVT::i32) 10167 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 10168 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 10169 X86::R10D,X86::R11D,X86::R12D, 10170 X86::R13D,X86::R14D,X86::R15D, 10171 X86::EBP, X86::ESP, 0); 10172 else if (VT == MVT::i16) 10173 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 10174 X86::SI, X86::DI, X86::R8W,X86::R9W, 10175 X86::R10W,X86::R11W,X86::R12W, 10176 X86::R13W,X86::R14W,X86::R15W, 10177 X86::BP, X86::SP, 0); 10178 else if (VT == MVT::i8) 10179 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 10180 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 10181 X86::R10B,X86::R11B,X86::R12B, 10182 X86::R13B,X86::R14B,X86::R15B, 10183 X86::BPL, X86::SPL, 0); 10184 10185 else if (VT == MVT::i64) 10186 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 10187 X86::RSI, X86::RDI, X86::R8, X86::R9, 10188 X86::R10, X86::R11, X86::R12, 10189 X86::R13, X86::R14, X86::R15, 10190 X86::RBP, X86::RSP, 0); 10191 10192 break; 10193 } 10194 // 32-bit fallthrough 10195 case 'Q': // Q_REGS 10196 if (VT == MVT::i32) 10197 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 10198 else if (VT == MVT::i16) 10199 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 10200 else if (VT == MVT::i8) 10201 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 10202 else if (VT == MVT::i64) 10203 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 10204 break; 10205 } 10206 } 10207 10208 return std::vector<unsigned>(); 10209} 10210 10211std::pair<unsigned, const TargetRegisterClass*> 10212X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 10213 EVT VT) const { 10214 // First, see if this is a constraint that directly corresponds to an LLVM 10215 // register class. 10216 if (Constraint.size() == 1) { 10217 // GCC Constraint Letters 10218 switch (Constraint[0]) { 10219 default: break; 10220 case 'r': // GENERAL_REGS 10221 case 'l': // INDEX_REGS 10222 if (VT == MVT::i8) 10223 return std::make_pair(0U, X86::GR8RegisterClass); 10224 if (VT == MVT::i16) 10225 return std::make_pair(0U, X86::GR16RegisterClass); 10226 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10227 return std::make_pair(0U, X86::GR32RegisterClass); 10228 return std::make_pair(0U, X86::GR64RegisterClass); 10229 case 'R': // LEGACY_REGS 10230 if (VT == MVT::i8) 10231 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 10232 if (VT == MVT::i16) 10233 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 10234 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10235 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 10236 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 10237 case 'f': // FP Stack registers. 10238 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 10239 // value to the correct fpstack register class. 10240 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 10241 return std::make_pair(0U, X86::RFP32RegisterClass); 10242 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 10243 return std::make_pair(0U, X86::RFP64RegisterClass); 10244 return std::make_pair(0U, X86::RFP80RegisterClass); 10245 case 'y': // MMX_REGS if MMX allowed. 10246 if (!Subtarget->hasMMX()) break; 10247 return std::make_pair(0U, X86::VR64RegisterClass); 10248 case 'Y': // SSE_REGS if SSE2 allowed 10249 if (!Subtarget->hasSSE2()) break; 10250 // FALL THROUGH. 10251 case 'x': // SSE_REGS if SSE1 allowed 10252 if (!Subtarget->hasSSE1()) break; 10253 10254 switch (VT.getSimpleVT().SimpleTy) { 10255 default: break; 10256 // Scalar SSE types. 10257 case MVT::f32: 10258 case MVT::i32: 10259 return std::make_pair(0U, X86::FR32RegisterClass); 10260 case MVT::f64: 10261 case MVT::i64: 10262 return std::make_pair(0U, X86::FR64RegisterClass); 10263 // Vector types. 10264 case MVT::v16i8: 10265 case MVT::v8i16: 10266 case MVT::v4i32: 10267 case MVT::v2i64: 10268 case MVT::v4f32: 10269 case MVT::v2f64: 10270 return std::make_pair(0U, X86::VR128RegisterClass); 10271 } 10272 break; 10273 } 10274 } 10275 10276 // Use the default implementation in TargetLowering to convert the register 10277 // constraint into a member of a register class. 10278 std::pair<unsigned, const TargetRegisterClass*> Res; 10279 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 10280 10281 // Not found as a standard register? 10282 if (Res.second == 0) { 10283 // Map st(0) -> st(7) -> ST0 10284 if (Constraint.size() == 7 && Constraint[0] == '{' && 10285 tolower(Constraint[1]) == 's' && 10286 tolower(Constraint[2]) == 't' && 10287 Constraint[3] == '(' && 10288 (Constraint[4] >= '0' && Constraint[4] <= '7') && 10289 Constraint[5] == ')' && 10290 Constraint[6] == '}') { 10291 10292 Res.first = X86::ST0+Constraint[4]-'0'; 10293 Res.second = X86::RFP80RegisterClass; 10294 return Res; 10295 } 10296 10297 // GCC allows "st(0)" to be called just plain "st". 10298 if (StringRef("{st}").equals_lower(Constraint)) { 10299 Res.first = X86::ST0; 10300 Res.second = X86::RFP80RegisterClass; 10301 return Res; 10302 } 10303 10304 // flags -> EFLAGS 10305 if (StringRef("{flags}").equals_lower(Constraint)) { 10306 Res.first = X86::EFLAGS; 10307 Res.second = X86::CCRRegisterClass; 10308 return Res; 10309 } 10310 10311 // 'A' means EAX + EDX. 10312 if (Constraint == "A") { 10313 Res.first = X86::EAX; 10314 Res.second = X86::GR32_ADRegisterClass; 10315 return Res; 10316 } 10317 return Res; 10318 } 10319 10320 // Otherwise, check to see if this is a register class of the wrong value 10321 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 10322 // turn into {ax},{dx}. 10323 if (Res.second->hasType(VT)) 10324 return Res; // Correct type already, nothing to do. 10325 10326 // All of the single-register GCC register classes map their values onto 10327 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 10328 // really want an 8-bit or 32-bit register, map to the appropriate register 10329 // class and return the appropriate register. 10330 if (Res.second == X86::GR16RegisterClass) { 10331 if (VT == MVT::i8) { 10332 unsigned DestReg = 0; 10333 switch (Res.first) { 10334 default: break; 10335 case X86::AX: DestReg = X86::AL; break; 10336 case X86::DX: DestReg = X86::DL; break; 10337 case X86::CX: DestReg = X86::CL; break; 10338 case X86::BX: DestReg = X86::BL; break; 10339 } 10340 if (DestReg) { 10341 Res.first = DestReg; 10342 Res.second = X86::GR8RegisterClass; 10343 } 10344 } else if (VT == MVT::i32) { 10345 unsigned DestReg = 0; 10346 switch (Res.first) { 10347 default: break; 10348 case X86::AX: DestReg = X86::EAX; break; 10349 case X86::DX: DestReg = X86::EDX; break; 10350 case X86::CX: DestReg = X86::ECX; break; 10351 case X86::BX: DestReg = X86::EBX; break; 10352 case X86::SI: DestReg = X86::ESI; break; 10353 case X86::DI: DestReg = X86::EDI; break; 10354 case X86::BP: DestReg = X86::EBP; break; 10355 case X86::SP: DestReg = X86::ESP; break; 10356 } 10357 if (DestReg) { 10358 Res.first = DestReg; 10359 Res.second = X86::GR32RegisterClass; 10360 } 10361 } else if (VT == MVT::i64) { 10362 unsigned DestReg = 0; 10363 switch (Res.first) { 10364 default: break; 10365 case X86::AX: DestReg = X86::RAX; break; 10366 case X86::DX: DestReg = X86::RDX; break; 10367 case X86::CX: DestReg = X86::RCX; break; 10368 case X86::BX: DestReg = X86::RBX; break; 10369 case X86::SI: DestReg = X86::RSI; break; 10370 case X86::DI: DestReg = X86::RDI; break; 10371 case X86::BP: DestReg = X86::RBP; break; 10372 case X86::SP: DestReg = X86::RSP; break; 10373 } 10374 if (DestReg) { 10375 Res.first = DestReg; 10376 Res.second = X86::GR64RegisterClass; 10377 } 10378 } 10379 } else if (Res.second == X86::FR32RegisterClass || 10380 Res.second == X86::FR64RegisterClass || 10381 Res.second == X86::VR128RegisterClass) { 10382 // Handle references to XMM physical registers that got mapped into the 10383 // wrong class. This can happen with constraints like {xmm0} where the 10384 // target independent register mapper will just pick the first match it can 10385 // find, ignoring the required type. 10386 if (VT == MVT::f32) 10387 Res.second = X86::FR32RegisterClass; 10388 else if (VT == MVT::f64) 10389 Res.second = X86::FR64RegisterClass; 10390 else if (X86::VR128RegisterClass->hasType(VT)) 10391 Res.second = X86::VR128RegisterClass; 10392 } 10393 10394 return Res; 10395} 10396