X86ISelLowering.cpp revision f5d280a0a649a879f6571fe7c3a7cf5dc5d50cc1
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86TargetMachine.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/ADT/VectorExtras.h" 26#include "llvm/Analysis/ScalarEvolutionExpressions.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/SelectionDAG.h" 32#include "llvm/CodeGen/SSARegMap.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/ADT/StringExtras.h" 37using namespace llvm; 38 39// FIXME: temporary. 40static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, 41 cl::desc("Enable fastcc on X86")); 42X86TargetLowering::X86TargetLowering(TargetMachine &TM) 43 : TargetLowering(TM) { 44 Subtarget = &TM.getSubtarget<X86Subtarget>(); 45 X86ScalarSSE = Subtarget->hasSSE2(); 46 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 47 48 // Set up the TargetLowering object. 49 50 // X86 is weird, it always uses i8 for shift amounts and setcc results. 51 setShiftAmountType(MVT::i8); 52 setSetCCResultType(MVT::i8); 53 setSetCCResultContents(ZeroOrOneSetCCResult); 54 setSchedulingPreference(SchedulingForRegPressure); 55 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 56 setStackPointerRegisterToSaveRestore(X86StackPtr); 57 58 if (Subtarget->isTargetDarwin()) { 59 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 60 setUseUnderscoreSetJmp(false); 61 setUseUnderscoreLongJmp(false); 62 } else if (Subtarget->isTargetMingw()) { 63 // MS runtime is weird: it exports _setjmp, but longjmp! 64 setUseUnderscoreSetJmp(true); 65 setUseUnderscoreLongJmp(false); 66 } else { 67 setUseUnderscoreSetJmp(true); 68 setUseUnderscoreLongJmp(true); 69 } 70 71 // Add legal addressing mode scale values. 72 addLegalAddressScale(8); 73 addLegalAddressScale(4); 74 addLegalAddressScale(2); 75 // Enter the ones which require both scale + index last. These are more 76 // expensive. 77 addLegalAddressScale(9); 78 addLegalAddressScale(5); 79 addLegalAddressScale(3); 80 81 // Set up the register classes. 82 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 83 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 84 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 85 if (Subtarget->is64Bit()) 86 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 87 88 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 89 90 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 91 // operation. 92 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 93 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 94 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 95 96 if (Subtarget->is64Bit()) { 97 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 98 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 99 } else { 100 if (X86ScalarSSE) 101 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP. 102 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); 103 else 104 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 105 } 106 107 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 108 // this operation. 109 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 110 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 111 // SSE has no i16 to fp conversion, only i32 112 if (X86ScalarSSE) 113 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 114 else { 115 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 116 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 117 } 118 119 if (!Subtarget->is64Bit()) { 120 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode. 121 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 122 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 123 } 124 125 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 126 // this operation. 127 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 128 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 129 130 if (X86ScalarSSE) { 131 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 132 } else { 133 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 134 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 135 } 136 137 // Handle FP_TO_UINT by promoting the destination to a larger signed 138 // conversion. 139 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 140 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 141 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 142 143 if (Subtarget->is64Bit()) { 144 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 145 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 146 } else { 147 if (X86ScalarSSE && !Subtarget->hasSSE3()) 148 // Expand FP_TO_UINT into a select. 149 // FIXME: We would like to use a Custom expander here eventually to do 150 // the optimal thing for SSE vs. the default expansion in the legalizer. 151 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 152 else 153 // With SSE3 we can use fisttpll to convert to a signed i64. 154 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 155 } 156 157 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 158 if (!X86ScalarSSE) { 159 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 160 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 161 } 162 163 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 164 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 165 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 166 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 167 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 168 if (Subtarget->is64Bit()) 169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); 171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 172 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 173 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 174 setOperationAction(ISD::FREM , MVT::f64 , Expand); 175 176 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 177 setOperationAction(ISD::CTTZ , MVT::i8 , Expand); 178 setOperationAction(ISD::CTLZ , MVT::i8 , Expand); 179 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 180 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 181 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 182 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 183 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 184 setOperationAction(ISD::CTLZ , MVT::i32 , Expand); 185 if (Subtarget->is64Bit()) { 186 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 187 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 188 setOperationAction(ISD::CTLZ , MVT::i64 , Expand); 189 } 190 191 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 192 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 193 194 // These should be promoted to a larger select which is supported. 195 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 196 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 197 // X86 wants to expand cmov itself. 198 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 199 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 200 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 201 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 202 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 203 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 204 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 205 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 206 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 207 if (Subtarget->is64Bit()) { 208 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 209 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 210 } 211 // X86 ret instruction may pop stack. 212 setOperationAction(ISD::RET , MVT::Other, Custom); 213 // Darwin ABI issue. 214 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 215 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 216 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 217 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 218 if (Subtarget->is64Bit()) { 219 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 220 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 221 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 222 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 223 } 224 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 225 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 226 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 227 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 228 // X86 wants to expand memset / memcpy itself. 229 setOperationAction(ISD::MEMSET , MVT::Other, Custom); 230 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 231 232 // We don't have line number support yet. 233 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 234 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 235 // FIXME - use subtarget debug flags 236 if (!Subtarget->isTargetDarwin() && 237 !Subtarget->isTargetELF() && 238 !Subtarget->isTargetCygMing()) 239 setOperationAction(ISD::LABEL, MVT::Other, Expand); 240 241 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 242 setOperationAction(ISD::VASTART , MVT::Other, Custom); 243 244 // Use the default implementation. 245 setOperationAction(ISD::VAARG , MVT::Other, Expand); 246 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 247 setOperationAction(ISD::VAEND , MVT::Other, Expand); 248 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 249 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 250 if (Subtarget->is64Bit()) 251 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 252 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 253 254 if (X86ScalarSSE) { 255 // Set up the FP register classes. 256 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 257 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 258 259 // Use ANDPD to simulate FABS. 260 setOperationAction(ISD::FABS , MVT::f64, Custom); 261 setOperationAction(ISD::FABS , MVT::f32, Custom); 262 263 // Use XORP to simulate FNEG. 264 setOperationAction(ISD::FNEG , MVT::f64, Custom); 265 setOperationAction(ISD::FNEG , MVT::f32, Custom); 266 267 // Use ANDPD and ORPD to simulate FCOPYSIGN. 268 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 269 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 270 271 // We don't support sin/cos/fmod 272 setOperationAction(ISD::FSIN , MVT::f64, Expand); 273 setOperationAction(ISD::FCOS , MVT::f64, Expand); 274 setOperationAction(ISD::FREM , MVT::f64, Expand); 275 setOperationAction(ISD::FSIN , MVT::f32, Expand); 276 setOperationAction(ISD::FCOS , MVT::f32, Expand); 277 setOperationAction(ISD::FREM , MVT::f32, Expand); 278 279 // Expand FP immediates into loads from the stack, except for the special 280 // cases we handle. 281 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 282 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 283 addLegalFPImmediate(+0.0); // xorps / xorpd 284 } else { 285 // Set up the FP register classes. 286 addRegisterClass(MVT::f64, X86::RFPRegisterClass); 287 288 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 289 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 290 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 291 292 if (!UnsafeFPMath) { 293 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 294 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 295 } 296 297 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 298 addLegalFPImmediate(+0.0); // FLD0 299 addLegalFPImmediate(+1.0); // FLD1 300 addLegalFPImmediate(-0.0); // FLD0/FCHS 301 addLegalFPImmediate(-1.0); // FLD1/FCHS 302 } 303 304 // First set operation action for all vector types to expand. Then we 305 // will selectively turn on ones that can be effectively codegen'd. 306 for (unsigned VT = (unsigned)MVT::Vector + 1; 307 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) { 308 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); 309 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); 310 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand); 311 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand); 312 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 313 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand); 314 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 315 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 316 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 317 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 318 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 319 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); 320 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); 321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 322 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 323 } 324 325 if (Subtarget->hasMMX()) { 326 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 327 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 328 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 329 330 // FIXME: add MMX packed arithmetics 331 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); 332 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); 333 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); 334 } 335 336 if (Subtarget->hasSSE1()) { 337 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 338 339 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 340 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 341 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 342 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 343 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 344 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 345 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 346 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 347 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 348 } 349 350 if (Subtarget->hasSSE2()) { 351 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 352 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 353 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 354 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 355 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 356 357 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 358 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 359 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 360 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 361 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 362 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 363 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 364 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 365 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 366 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 367 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 368 369 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 370 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 371 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 372 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 373 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones. 374 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 375 376 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 377 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 378 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom); 379 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); 380 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom); 381 } 382 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 383 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 384 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 385 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 387 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 388 389 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 390 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 391 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); 392 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64); 393 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote); 394 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64); 395 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote); 396 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64); 397 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote); 398 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64); 399 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 400 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); 401 } 402 403 // Custom lower v2i64 and v2f64 selects. 404 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 405 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 406 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 407 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 408 } 409 410 // We want to custom lower some of our intrinsics. 411 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 412 413 // We have target-specific dag combine patterns for the following nodes: 414 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 415 setTargetDAGCombine(ISD::SELECT); 416 417 computeRegisterProperties(); 418 419 // FIXME: These should be based on subtarget info. Plus, the values should 420 // be smaller when we are in optimizing for size mode. 421 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores 422 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores 423 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores 424 allowUnalignedMemoryAccesses = true; // x86 supports it! 425} 426 427 428//===----------------------------------------------------------------------===// 429// Return Value Calling Convention Implementation 430//===----------------------------------------------------------------------===// 431 432#include "X86GenCallingConv.inc" 433 434/// LowerRET - Lower an ISD::RET node. 435SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { 436 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); 437 438 SmallVector<CCValAssign, 16> RVLocs; 439 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 440 CCState CCInfo(CC, getTargetMachine(), RVLocs); 441 442 // Determine which register each value should be copied into. 443 for (unsigned i = 0; i != Op.getNumOperands() / 2; ++i) { 444 MVT::ValueType VT = Op.getOperand(i*2+1).getValueType(); 445 if (RetCC_X86(i, VT, VT, CCValAssign::Full, 446 cast<ConstantSDNode>(Op.getOperand(i*2+2))->getValue(), 447 CCInfo)) 448 assert(0 && "Unhandled result type!"); 449 } 450 451 // If this is the first return lowered for this function, add the regs to the 452 // liveout set for the function. 453 if (DAG.getMachineFunction().liveout_empty()) { 454 for (unsigned i = 0; i != RVLocs.size(); ++i) 455 if (RVLocs[i].isRegLoc()) 456 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); 457 } 458 459 SDOperand Chain = Op.getOperand(0); 460 SDOperand Flag; 461 462 // Copy the result values into the output registers. 463 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() || 464 RVLocs[0].getLocReg() != X86::ST0) { 465 for (unsigned i = 0; i != RVLocs.size(); ++i) { 466 CCValAssign &VA = RVLocs[i]; 467 assert(VA.isRegLoc() && "Can only return in registers!"); 468 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), 469 Flag); 470 Flag = Chain.getValue(1); 471 } 472 } else { 473 // We need to handle a destination of ST0 specially, because it isn't really 474 // a register. 475 SDOperand Value = Op.getOperand(1); 476 477 // If this is an FP return with ScalarSSE, we need to move the value from 478 // an XMM register onto the fp-stack. 479 if (X86ScalarSSE) { 480 SDOperand MemLoc; 481 482 // If this is a load into a scalarsse value, don't store the loaded value 483 // back to the stack, only to reload it: just replace the scalar-sse load. 484 if (ISD::isNON_EXTLoad(Value.Val) && 485 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) { 486 Chain = Value.getOperand(0); 487 MemLoc = Value.getOperand(1); 488 } else { 489 // Spill the value to memory and reload it into top of stack. 490 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8; 491 MachineFunction &MF = DAG.getMachineFunction(); 492 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 493 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy()); 494 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0); 495 } 496 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other); 497 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())}; 498 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); 499 Chain = Value.getValue(1); 500 } 501 502 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 503 SDOperand Ops[] = { Chain, Value }; 504 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2); 505 Flag = Chain.getValue(1); 506 } 507 508 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16); 509 if (Flag.Val) 510 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag); 511 else 512 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop); 513} 514 515 516/// LowerCallResult - Lower the result values of an ISD::CALL into the 517/// appropriate copies out of appropriate physical registers. This assumes that 518/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 519/// being lowered. The returns a SDNode with the same number of values as the 520/// ISD::CALL. 521SDNode *X86TargetLowering:: 522LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, 523 unsigned CallingConv, SelectionDAG &DAG) { 524 SmallVector<SDOperand, 8> ResultVals; 525 526 SmallVector<CCValAssign, 16> RVLocs; 527 CCState CCInfo(CallingConv, getTargetMachine(), RVLocs); 528 529 for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) { 530 MVT::ValueType VT = TheCall->getValueType(i); 531 if (RetCC_X86(i, VT, VT, CCValAssign::Full, 0, CCInfo)) 532 assert(0 && "Unhandled result type!"); 533 } 534 535 // Copy all of the result registers out of their specified physreg. 536 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) { 537 for (unsigned i = 0; i != RVLocs.size(); ++i) { 538 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 539 RVLocs[i].getValVT(), InFlag).getValue(1); 540 InFlag = Chain.getValue(2); 541 ResultVals.push_back(Chain.getValue(0)); 542 } 543 } else { 544 // Copies from the FP stack are special, as ST0 isn't a valid register 545 // before the fp stackifier runs. 546 547 // Copy ST0 into an RFP register with FP_GET_RESULT. 548 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 549 SDOperand GROps[] = { Chain, InFlag }; 550 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2); 551 Chain = RetVal.getValue(1); 552 InFlag = RetVal.getValue(2); 553 554 // If we are using ScalarSSE, store ST(0) to the stack and reload it into 555 // an XMM register. 556 if (X86ScalarSSE) { 557 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This 558 // shouldn't be necessary except that RFP cannot be live across 559 // multiple blocks. When stackifier is fixed, they can be uncoupled. 560 MachineFunction &MF = DAG.getMachineFunction(); 561 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 562 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 563 SDOperand Ops[] = { 564 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag 565 }; 566 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5); 567 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0); 568 Chain = RetVal.getValue(1); 569 } 570 571 if (RVLocs[0].getValVT() == MVT::f32 && !X86ScalarSSE) 572 // FIXME: we would really like to remember that this FP_ROUND 573 // operation is okay to eliminate if we allow excess FP precision. 574 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 575 ResultVals.push_back(RetVal); 576 } 577 578 // Merge everything together with a MERGE_VALUES node. 579 ResultVals.push_back(Chain); 580 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), 581 &ResultVals[0], ResultVals.size()).Val; 582} 583 584 585//===----------------------------------------------------------------------===// 586// C & StdCall Calling Convention implementation 587//===----------------------------------------------------------------------===// 588// StdCall calling convention seems to be standard for many Windows' API 589// routines and around. It differs from C calling convention just a little: 590// callee should clean up the stack, not caller. Symbols should be also 591// decorated in some fancy way :) It doesn't support any vector arguments. 592 593/// AddLiveIn - This helper function adds the specified physical register to the 594/// MachineFunction as a live in value. It also creates a corresponding virtual 595/// register for it. 596static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 597 const TargetRegisterClass *RC) { 598 assert(RC->contains(PReg) && "Not the correct regclass!"); 599 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 600 MF.addLiveIn(PReg, VReg); 601 return VReg; 602} 603 604SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG, 605 bool isStdCall) { 606 unsigned NumArgs = Op.Val->getNumValues() - 1; 607 MachineFunction &MF = DAG.getMachineFunction(); 608 MachineFrameInfo *MFI = MF.getFrameInfo(); 609 SDOperand Root = Op.getOperand(0); 610 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 611 612 SmallVector<CCValAssign, 16> ArgLocs; 613 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(), 614 ArgLocs); 615 616 for (unsigned i = 0; i != NumArgs; ++i) { 617 MVT::ValueType ArgVT = Op.getValue(i).getValueType(); 618 unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue(); 619 if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 620 assert(0 && "Unhandled argument type!"); 621 } 622 623 SmallVector<SDOperand, 8> ArgValues; 624 unsigned LastVal = ~0U; 625 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 626 CCValAssign &VA = ArgLocs[i]; 627 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 628 // places. 629 assert(VA.getValNo() != LastVal && 630 "Don't support value assigned to multiple locs yet"); 631 LastVal = VA.getValNo(); 632 633 if (VA.isRegLoc()) { 634 MVT::ValueType RegVT = VA.getLocVT(); 635 TargetRegisterClass *RC; 636 if (RegVT == MVT::i32) 637 RC = X86::GR32RegisterClass; 638 else { 639 assert(MVT::isVector(RegVT)); 640 RC = X86::VR128RegisterClass; 641 } 642 643 SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); 644 AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 645 646 // If this is an 8 or 16-bit value, it is really passed promoted to 32 647 // bits. Insert an assert[sz]ext to capture this, then truncate to the 648 // right size. 649 if (VA.getLocInfo() == CCValAssign::SExt) 650 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 651 DAG.getValueType(VA.getValVT())); 652 else if (VA.getLocInfo() == CCValAssign::ZExt) 653 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 654 DAG.getValueType(VA.getValVT())); 655 656 if (VA.getLocInfo() != CCValAssign::Full) 657 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 658 659 ArgValues.push_back(ArgValue); 660 } else { 661 assert(VA.isMemLoc()); 662 663 // Create the nodes corresponding to a load from this parameter slot. 664 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, 665 VA.getLocMemOffset()); 666 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 667 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); 668 } 669 } 670 671 unsigned StackSize = CCInfo.getNextStackOffset(); 672 673 ArgValues.push_back(Root); 674 675 // If the function takes variable number of arguments, make a frame index for 676 // the start of the first vararg value... for expansion of llvm.va_start. 677 if (isVarArg) 678 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 679 680 if (isStdCall && !isVarArg) { 681 BytesToPopOnReturn = StackSize; // Callee pops everything.. 682 BytesCallerReserves = 0; 683 } else { 684 BytesToPopOnReturn = 0; // Callee pops hidden struct pointer. 685 686 // If this is an sret function, the return should pop the hidden pointer. 687 if (NumArgs && (cast<ConstantSDNode>(Op.getOperand(3))->getValue() & 4)) 688 BytesToPopOnReturn = 4; 689 690 BytesCallerReserves = StackSize; 691 } 692 693 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only. 694 ReturnAddrIndex = 0; // No return address slot generated yet. 695 696 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn); 697 698 // Return the new list of results. 699 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), 700 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); 701} 702 703SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, 704 unsigned CC) { 705 SDOperand Chain = Op.getOperand(0); 706 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 707 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 708 SDOperand Callee = Op.getOperand(4); 709 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 710 711 SmallVector<CCValAssign, 16> ArgLocs; 712 CCState CCInfo(CC, getTargetMachine(), ArgLocs); 713 714 for (unsigned i = 0; i != NumOps; ++i) { 715 MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType(); 716 unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 717 if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 718 assert(0 && "Unhandled argument type!"); 719 } 720 721 // Get a count of how many bytes are to be pushed on the stack. 722 unsigned NumBytes = CCInfo.getNextStackOffset(); 723 724 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 725 726 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; 727 SmallVector<SDOperand, 8> MemOpChains; 728 729 SDOperand StackPtr; 730 731 // Walk the register/memloc assignments, inserting copies/loads. 732 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 733 CCValAssign &VA = ArgLocs[i]; 734 SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); 735 736 // Promote the value if needed. 737 switch (VA.getLocInfo()) { 738 default: assert(0 && "Unknown loc info!"); 739 case CCValAssign::Full: break; 740 case CCValAssign::SExt: 741 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 742 break; 743 case CCValAssign::ZExt: 744 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 745 break; 746 case CCValAssign::AExt: 747 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 748 break; 749 } 750 751 if (VA.isRegLoc()) { 752 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 753 } else { 754 assert(VA.isMemLoc()); 755 if (StackPtr.Val == 0) 756 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy()); 757 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy()); 758 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 759 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 760 } 761 } 762 763 // If the first argument is an sret pointer, remember it. 764 bool isSRet = NumOps &&(cast<ConstantSDNode>(Op.getOperand(6))->getValue()&4); 765 766 if (!MemOpChains.empty()) 767 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 768 &MemOpChains[0], MemOpChains.size()); 769 770 // Build a sequence of copy-to-reg nodes chained together with token chain 771 // and flag operands which copy the outgoing args into registers. 772 SDOperand InFlag; 773 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 774 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 775 InFlag); 776 InFlag = Chain.getValue(1); 777 } 778 779 // ELF / PIC requires GOT in the EBX register before function calls via PLT 780 // GOT pointer. 781 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 782 Subtarget->isPICStyleGOT()) { 783 Chain = DAG.getCopyToReg(Chain, X86::EBX, 784 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 785 InFlag); 786 InFlag = Chain.getValue(1); 787 } 788 789 // If the callee is a GlobalAddress node (quite common, every direct call is) 790 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 791 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 792 // We should use extra load for direct calls to dllimported functions in 793 // non-JIT mode. 794 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 795 getTargetMachine(), true)) 796 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 797 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 798 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 799 800 // Returns a chain & a flag for retval copy to use. 801 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 802 SmallVector<SDOperand, 8> Ops; 803 Ops.push_back(Chain); 804 Ops.push_back(Callee); 805 806 // Add argument registers to the end of the list so that they are known live 807 // into the call. 808 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 809 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 810 RegsToPass[i].second.getValueType())); 811 812 // Add an implicit use GOT pointer in EBX. 813 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 814 Subtarget->isPICStyleGOT()) 815 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 816 817 if (InFlag.Val) 818 Ops.push_back(InFlag); 819 820 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 821 NodeTys, &Ops[0], Ops.size()); 822 InFlag = Chain.getValue(1); 823 824 // Create the CALLSEQ_END node. 825 unsigned NumBytesForCalleeToPush = 0; 826 827 if (CC == CallingConv::X86_StdCall) { 828 if (isVarArg) 829 NumBytesForCalleeToPush = isSRet ? 4 : 0; 830 else 831 NumBytesForCalleeToPush = NumBytes; 832 } else { 833 // If this is is a call to a struct-return function, the callee 834 // pops the hidden struct pointer, so we have to push it back. 835 // This is common for Darwin/X86, Linux & Mingw32 targets. 836 NumBytesForCalleeToPush = isSRet ? 4 : 0; 837 } 838 839 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 840 Ops.clear(); 841 Ops.push_back(Chain); 842 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 843 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy())); 844 Ops.push_back(InFlag); 845 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 846 InFlag = Chain.getValue(1); 847 848 // Handle result values, copying them out of physregs into vregs that we 849 // return. 850 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 851} 852 853 854//===----------------------------------------------------------------------===// 855// FastCall Calling Convention implementation 856//===----------------------------------------------------------------------===// 857// 858// The X86 'fastcall' calling convention passes up to two integer arguments in 859// registers (an appropriate portion of ECX/EDX), passes arguments in C order, 860// and requires that the callee pop its arguments off the stack (allowing proper 861// tail calls), and has the same return value conventions as C calling convs. 862// 863// This calling convention always arranges for the callee pop value to be 8n+4 864// bytes, which is needed for tail recursion elimination and stack alignment 865// reasons. 866SDOperand 867X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) { 868 unsigned NumArgs = Op.Val->getNumValues()-1; 869 MachineFunction &MF = DAG.getMachineFunction(); 870 MachineFrameInfo *MFI = MF.getFrameInfo(); 871 SDOperand Root = Op.getOperand(0); 872 873 SmallVector<CCValAssign, 16> ArgLocs; 874 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(), 875 ArgLocs); 876 877 for (unsigned i = 0; i != NumArgs; ++i) { 878 MVT::ValueType ArgVT = Op.getValue(i).getValueType(); 879 unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue(); 880 if (CC_X86_32_FastCall(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,CCInfo)) 881 assert(0 && "Unhandled argument type!"); 882 } 883 884 SmallVector<SDOperand, 8> ArgValues; 885 unsigned LastVal = ~0U; 886 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 887 CCValAssign &VA = ArgLocs[i]; 888 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 889 // places. 890 assert(VA.getValNo() != LastVal && 891 "Don't support value assigned to multiple locs yet"); 892 LastVal = VA.getValNo(); 893 894 if (VA.isRegLoc()) { 895 MVT::ValueType RegVT = VA.getLocVT(); 896 TargetRegisterClass *RC; 897 if (RegVT == MVT::i32) 898 RC = X86::GR32RegisterClass; 899 else { 900 assert(MVT::isVector(RegVT)); 901 RC = X86::VR128RegisterClass; 902 } 903 904 SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); 905 AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 906 907 // If this is an 8 or 16-bit value, it is really passed promoted to 32 908 // bits. Insert an assert[sz]ext to capture this, then truncate to the 909 // right size. 910 if (VA.getLocInfo() == CCValAssign::SExt) 911 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 912 DAG.getValueType(VA.getValVT())); 913 else if (VA.getLocInfo() == CCValAssign::ZExt) 914 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 915 DAG.getValueType(VA.getValVT())); 916 917 if (VA.getLocInfo() != CCValAssign::Full) 918 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 919 920 ArgValues.push_back(ArgValue); 921 } else { 922 assert(VA.isMemLoc()); 923 924 // Create the nodes corresponding to a load from this parameter slot. 925 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, 926 VA.getLocMemOffset()); 927 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 928 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); 929 } 930 } 931 932 ArgValues.push_back(Root); 933 934 unsigned StackSize = CCInfo.getNextStackOffset(); 935 936 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 937 // arguments and the arguments after the retaddr has been pushed are aligned. 938 if ((StackSize & 7) == 0) 939 StackSize += 4; 940 941 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 942 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only. 943 ReturnAddrIndex = 0; // No return address slot generated yet. 944 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments. 945 BytesCallerReserves = 0; 946 947 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn); 948 949 // Return the new list of results. 950 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), 951 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); 952} 953 954SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, 955 unsigned CC) { 956 SDOperand Chain = Op.getOperand(0); 957 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 958 SDOperand Callee = Op.getOperand(4); 959 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 960 961 962 SmallVector<CCValAssign, 16> ArgLocs; 963 CCState CCInfo(CC, getTargetMachine(), ArgLocs); 964 965 for (unsigned i = 0; i != NumOps; ++i) { 966 MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType(); 967 unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 968 if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 969 assert(0 && "Unhandled argument type!"); 970 } 971 972 // Get a count of how many bytes are to be pushed on the stack. 973 unsigned NumBytes = CCInfo.getNextStackOffset(); 974 975 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 976 // arguments and the arguments after the retaddr has been pushed are aligned. 977 if ((NumBytes & 7) == 0) 978 NumBytes += 4; 979 980 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 981 982 983 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; 984 SmallVector<SDOperand, 8> MemOpChains; 985 986 SDOperand StackPtr; 987 988 // Walk the register/memloc assignments, inserting copies/loads. 989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 990 CCValAssign &VA = ArgLocs[i]; 991 SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); 992 993 // Promote the value if needed. 994 switch (VA.getLocInfo()) { 995 default: assert(0 && "Unknown loc info!"); 996 case CCValAssign::Full: break; 997 case CCValAssign::SExt: 998 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 999 break; 1000 case CCValAssign::ZExt: 1001 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 1002 break; 1003 case CCValAssign::AExt: 1004 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 1005 break; 1006 } 1007 1008 if (VA.isRegLoc()) { 1009 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1010 } else { 1011 assert(VA.isMemLoc()); 1012 if (StackPtr.Val == 0) 1013 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy()); 1014 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy()); 1015 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1016 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1017 } 1018 } 1019 1020 if (!MemOpChains.empty()) 1021 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1022 &MemOpChains[0], MemOpChains.size()); 1023 1024 // Build a sequence of copy-to-reg nodes chained together with token chain 1025 // and flag operands which copy the outgoing args into registers. 1026 SDOperand InFlag; 1027 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1028 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1029 InFlag); 1030 InFlag = Chain.getValue(1); 1031 } 1032 1033 // If the callee is a GlobalAddress node (quite common, every direct call is) 1034 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1035 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1036 // We should use extra load for direct calls to dllimported functions in 1037 // non-JIT mode. 1038 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1039 getTargetMachine(), true)) 1040 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1041 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1042 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1043 1044 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1045 // GOT pointer. 1046 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1047 Subtarget->isPICStyleGOT()) { 1048 Chain = DAG.getCopyToReg(Chain, X86::EBX, 1049 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 1050 InFlag); 1051 InFlag = Chain.getValue(1); 1052 } 1053 1054 // Returns a chain & a flag for retval copy to use. 1055 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1056 SmallVector<SDOperand, 8> Ops; 1057 Ops.push_back(Chain); 1058 Ops.push_back(Callee); 1059 1060 // Add argument registers to the end of the list so that they are known live 1061 // into the call. 1062 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1063 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1064 RegsToPass[i].second.getValueType())); 1065 1066 // Add an implicit use GOT pointer in EBX. 1067 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1068 Subtarget->isPICStyleGOT()) 1069 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1070 1071 if (InFlag.Val) 1072 Ops.push_back(InFlag); 1073 1074 // FIXME: Do not generate X86ISD::TAILCALL for now. 1075 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 1076 NodeTys, &Ops[0], Ops.size()); 1077 InFlag = Chain.getValue(1); 1078 1079 // Returns a flag for retval copy to use. 1080 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1081 Ops.clear(); 1082 Ops.push_back(Chain); 1083 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1084 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1085 Ops.push_back(InFlag); 1086 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1087 InFlag = Chain.getValue(1); 1088 1089 // Handle result values, copying them out of physregs into vregs that we 1090 // return. 1091 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 1092} 1093 1094 1095//===----------------------------------------------------------------------===// 1096// X86-64 C Calling Convention implementation 1097//===----------------------------------------------------------------------===// 1098 1099SDOperand 1100X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) { 1101 unsigned NumArgs = Op.Val->getNumValues() - 1; 1102 MachineFunction &MF = DAG.getMachineFunction(); 1103 MachineFrameInfo *MFI = MF.getFrameInfo(); 1104 SDOperand Root = Op.getOperand(0); 1105 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1106 1107 static const unsigned GPR64ArgRegs[] = { 1108 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1109 }; 1110 static const unsigned XMMArgRegs[] = { 1111 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1112 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1113 }; 1114 1115 SmallVector<CCValAssign, 16> ArgLocs; 1116 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(), 1117 ArgLocs); 1118 1119 for (unsigned i = 0; i != NumArgs; ++i) { 1120 MVT::ValueType ArgVT = Op.getValue(i).getValueType(); 1121 unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue(); 1122 if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 1123 assert(0 && "Unhandled argument type!"); 1124 } 1125 1126 SmallVector<SDOperand, 8> ArgValues; 1127 unsigned LastVal = ~0U; 1128 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1129 CCValAssign &VA = ArgLocs[i]; 1130 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1131 // places. 1132 assert(VA.getValNo() != LastVal && 1133 "Don't support value assigned to multiple locs yet"); 1134 LastVal = VA.getValNo(); 1135 1136 if (VA.isRegLoc()) { 1137 MVT::ValueType RegVT = VA.getLocVT(); 1138 TargetRegisterClass *RC; 1139 if (RegVT == MVT::i32) 1140 RC = X86::GR32RegisterClass; 1141 else if (RegVT == MVT::i64) 1142 RC = X86::GR64RegisterClass; 1143 else if (RegVT == MVT::f32) 1144 RC = X86::FR32RegisterClass; 1145 else if (RegVT == MVT::f64) 1146 RC = X86::FR64RegisterClass; 1147 else { 1148 assert(MVT::isVector(RegVT)); 1149 RC = X86::VR128RegisterClass; 1150 } 1151 1152 SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); 1153 AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 1154 1155 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1156 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1157 // right size. 1158 if (VA.getLocInfo() == CCValAssign::SExt) 1159 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 1160 DAG.getValueType(VA.getValVT())); 1161 else if (VA.getLocInfo() == CCValAssign::ZExt) 1162 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 1163 DAG.getValueType(VA.getValVT())); 1164 1165 if (VA.getLocInfo() != CCValAssign::Full) 1166 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 1167 1168 ArgValues.push_back(ArgValue); 1169 } else { 1170 assert(VA.isMemLoc()); 1171 1172 // Create the nodes corresponding to a load from this parameter slot. 1173 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, 1174 VA.getLocMemOffset()); 1175 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 1176 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); 1177 } 1178 } 1179 1180 unsigned StackSize = CCInfo.getNextStackOffset(); 1181 1182 // If the function takes variable number of arguments, make a frame index for 1183 // the start of the first vararg value... for expansion of llvm.va_start. 1184 if (isVarArg) { 1185 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6); 1186 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1187 1188 // For X86-64, if there are vararg parameters that are passed via 1189 // registers, then we must store them to their spots on the stack so they 1190 // may be loaded by deferencing the result of va_next. 1191 VarArgsGPOffset = NumIntRegs * 8; 1192 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16; 1193 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1194 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16); 1195 1196 // Store the integer parameter registers. 1197 SmallVector<SDOperand, 8> MemOps; 1198 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1199 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1200 DAG.getConstant(VarArgsGPOffset, getPointerTy())); 1201 for (; NumIntRegs != 6; ++NumIntRegs) { 1202 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], 1203 X86::GR64RegisterClass); 1204 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1205 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1206 MemOps.push_back(Store); 1207 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1208 DAG.getConstant(8, getPointerTy())); 1209 } 1210 1211 // Now store the XMM (fp + vector) parameter registers. 1212 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1213 DAG.getConstant(VarArgsFPOffset, getPointerTy())); 1214 for (; NumXMMRegs != 8; ++NumXMMRegs) { 1215 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 1216 X86::VR128RegisterClass); 1217 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); 1218 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1219 MemOps.push_back(Store); 1220 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1221 DAG.getConstant(16, getPointerTy())); 1222 } 1223 if (!MemOps.empty()) 1224 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1225 &MemOps[0], MemOps.size()); 1226 } 1227 1228 ArgValues.push_back(Root); 1229 1230 ReturnAddrIndex = 0; // No return address slot generated yet. 1231 BytesToPopOnReturn = 0; // Callee pops nothing. 1232 BytesCallerReserves = StackSize; 1233 1234 // Return the new list of results. 1235 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), 1236 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); 1237} 1238 1239SDOperand 1240X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG, 1241 unsigned CC) { 1242 SDOperand Chain = Op.getOperand(0); 1243 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1244 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0; 1245 SDOperand Callee = Op.getOperand(4); 1246 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1247 1248 SmallVector<CCValAssign, 16> ArgLocs; 1249 CCState CCInfo(CC, getTargetMachine(), ArgLocs); 1250 1251 for (unsigned i = 0; i != NumOps; ++i) { 1252 MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType(); 1253 unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1254 if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 1255 assert(0 && "Unhandled argument type!"); 1256 } 1257 1258 // Get a count of how many bytes are to be pushed on the stack. 1259 unsigned NumBytes = CCInfo.getNextStackOffset(); 1260 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 1261 1262 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; 1263 SmallVector<SDOperand, 8> MemOpChains; 1264 1265 SDOperand StackPtr; 1266 1267 // Walk the register/memloc assignments, inserting copies/loads. 1268 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1269 CCValAssign &VA = ArgLocs[i]; 1270 SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); 1271 1272 // Promote the value if needed. 1273 switch (VA.getLocInfo()) { 1274 default: assert(0 && "Unknown loc info!"); 1275 case CCValAssign::Full: break; 1276 case CCValAssign::SExt: 1277 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 1278 break; 1279 case CCValAssign::ZExt: 1280 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 1281 break; 1282 case CCValAssign::AExt: 1283 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 1284 break; 1285 } 1286 1287 if (VA.isRegLoc()) { 1288 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1289 } else { 1290 assert(VA.isMemLoc()); 1291 if (StackPtr.Val == 0) 1292 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy()); 1293 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy()); 1294 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1295 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1296 } 1297 } 1298 1299 if (!MemOpChains.empty()) 1300 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1301 &MemOpChains[0], MemOpChains.size()); 1302 1303 // Build a sequence of copy-to-reg nodes chained together with token chain 1304 // and flag operands which copy the outgoing args into registers. 1305 SDOperand InFlag; 1306 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1307 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1308 InFlag); 1309 InFlag = Chain.getValue(1); 1310 } 1311 1312 if (isVarArg) { 1313 // From AMD64 ABI document: 1314 // For calls that may call functions that use varargs or stdargs 1315 // (prototype-less calls or calls to functions containing ellipsis (...) in 1316 // the declaration) %al is used as hidden argument to specify the number 1317 // of SSE registers used. The contents of %al do not need to match exactly 1318 // the number of registers, but must be an ubound on the number of SSE 1319 // registers used and is in the range 0 - 8 inclusive. 1320 1321 // Count the number of XMM registers allocated. 1322 static const unsigned XMMArgRegs[] = { 1323 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1324 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1325 }; 1326 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1327 1328 Chain = DAG.getCopyToReg(Chain, X86::AL, 1329 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1330 InFlag = Chain.getValue(1); 1331 } 1332 1333 // If the callee is a GlobalAddress node (quite common, every direct call is) 1334 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1335 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1336 // We should use extra load for direct calls to dllimported functions in 1337 // non-JIT mode. 1338 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1339 getTargetMachine(), true)) 1340 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1341 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1342 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1343 1344 // Returns a chain & a flag for retval copy to use. 1345 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1346 SmallVector<SDOperand, 8> Ops; 1347 Ops.push_back(Chain); 1348 Ops.push_back(Callee); 1349 1350 // Add argument registers to the end of the list so that they are known live 1351 // into the call. 1352 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1353 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1354 RegsToPass[i].second.getValueType())); 1355 1356 if (InFlag.Val) 1357 Ops.push_back(InFlag); 1358 1359 // FIXME: Do not generate X86ISD::TAILCALL for now. 1360 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 1361 NodeTys, &Ops[0], Ops.size()); 1362 InFlag = Chain.getValue(1); 1363 1364 // Returns a flag for retval copy to use. 1365 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1366 Ops.clear(); 1367 Ops.push_back(Chain); 1368 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 1369 Ops.push_back(DAG.getConstant(0, getPointerTy())); 1370 Ops.push_back(InFlag); 1371 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1372 InFlag = Chain.getValue(1); 1373 1374 // Handle result values, copying them out of physregs into vregs that we 1375 // return. 1376 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 1377} 1378 1379 1380//===----------------------------------------------------------------------===// 1381// Other Lowering Hooks 1382//===----------------------------------------------------------------------===// 1383 1384 1385SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 1386 if (ReturnAddrIndex == 0) { 1387 // Set up a frame object for the return address. 1388 MachineFunction &MF = DAG.getMachineFunction(); 1389 if (Subtarget->is64Bit()) 1390 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8); 1391 else 1392 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); 1393 } 1394 1395 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 1396} 1397 1398 1399 1400/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 1401/// specific condition code. It returns a false if it cannot do a direct 1402/// translation. X86CC is the translated CondCode. LHS/RHS are modified as 1403/// needed. 1404static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 1405 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS, 1406 SelectionDAG &DAG) { 1407 X86CC = X86::COND_INVALID; 1408 if (!isFP) { 1409 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 1410 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 1411 // X > -1 -> X == 0, jump !sign. 1412 RHS = DAG.getConstant(0, RHS.getValueType()); 1413 X86CC = X86::COND_NS; 1414 return true; 1415 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 1416 // X < 0 -> X == 0, jump on sign. 1417 X86CC = X86::COND_S; 1418 return true; 1419 } 1420 } 1421 1422 switch (SetCCOpcode) { 1423 default: break; 1424 case ISD::SETEQ: X86CC = X86::COND_E; break; 1425 case ISD::SETGT: X86CC = X86::COND_G; break; 1426 case ISD::SETGE: X86CC = X86::COND_GE; break; 1427 case ISD::SETLT: X86CC = X86::COND_L; break; 1428 case ISD::SETLE: X86CC = X86::COND_LE; break; 1429 case ISD::SETNE: X86CC = X86::COND_NE; break; 1430 case ISD::SETULT: X86CC = X86::COND_B; break; 1431 case ISD::SETUGT: X86CC = X86::COND_A; break; 1432 case ISD::SETULE: X86CC = X86::COND_BE; break; 1433 case ISD::SETUGE: X86CC = X86::COND_AE; break; 1434 } 1435 } else { 1436 // On a floating point condition, the flags are set as follows: 1437 // ZF PF CF op 1438 // 0 | 0 | 0 | X > Y 1439 // 0 | 0 | 1 | X < Y 1440 // 1 | 0 | 0 | X == Y 1441 // 1 | 1 | 1 | unordered 1442 bool Flip = false; 1443 switch (SetCCOpcode) { 1444 default: break; 1445 case ISD::SETUEQ: 1446 case ISD::SETEQ: X86CC = X86::COND_E; break; 1447 case ISD::SETOLT: Flip = true; // Fallthrough 1448 case ISD::SETOGT: 1449 case ISD::SETGT: X86CC = X86::COND_A; break; 1450 case ISD::SETOLE: Flip = true; // Fallthrough 1451 case ISD::SETOGE: 1452 case ISD::SETGE: X86CC = X86::COND_AE; break; 1453 case ISD::SETUGT: Flip = true; // Fallthrough 1454 case ISD::SETULT: 1455 case ISD::SETLT: X86CC = X86::COND_B; break; 1456 case ISD::SETUGE: Flip = true; // Fallthrough 1457 case ISD::SETULE: 1458 case ISD::SETLE: X86CC = X86::COND_BE; break; 1459 case ISD::SETONE: 1460 case ISD::SETNE: X86CC = X86::COND_NE; break; 1461 case ISD::SETUO: X86CC = X86::COND_P; break; 1462 case ISD::SETO: X86CC = X86::COND_NP; break; 1463 } 1464 if (Flip) 1465 std::swap(LHS, RHS); 1466 } 1467 1468 return X86CC != X86::COND_INVALID; 1469} 1470 1471/// hasFPCMov - is there a floating point cmov for the specific X86 condition 1472/// code. Current x86 isa includes the following FP cmov instructions: 1473/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 1474static bool hasFPCMov(unsigned X86CC) { 1475 switch (X86CC) { 1476 default: 1477 return false; 1478 case X86::COND_B: 1479 case X86::COND_BE: 1480 case X86::COND_E: 1481 case X86::COND_P: 1482 case X86::COND_A: 1483 case X86::COND_AE: 1484 case X86::COND_NE: 1485 case X86::COND_NP: 1486 return true; 1487 } 1488} 1489 1490/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return 1491/// true if Op is undef or if its value falls within the specified range (L, H]. 1492static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { 1493 if (Op.getOpcode() == ISD::UNDEF) 1494 return true; 1495 1496 unsigned Val = cast<ConstantSDNode>(Op)->getValue(); 1497 return (Val >= Low && Val < Hi); 1498} 1499 1500/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return 1501/// true if Op is undef or if its value equal to the specified value. 1502static bool isUndefOrEqual(SDOperand Op, unsigned Val) { 1503 if (Op.getOpcode() == ISD::UNDEF) 1504 return true; 1505 return cast<ConstantSDNode>(Op)->getValue() == Val; 1506} 1507 1508/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 1509/// specifies a shuffle of elements that is suitable for input to PSHUFD. 1510bool X86::isPSHUFDMask(SDNode *N) { 1511 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1512 1513 if (N->getNumOperands() != 4) 1514 return false; 1515 1516 // Check if the value doesn't reference the second vector. 1517 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 1518 SDOperand Arg = N->getOperand(i); 1519 if (Arg.getOpcode() == ISD::UNDEF) continue; 1520 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1521 if (cast<ConstantSDNode>(Arg)->getValue() >= 4) 1522 return false; 1523 } 1524 1525 return true; 1526} 1527 1528/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 1529/// specifies a shuffle of elements that is suitable for input to PSHUFHW. 1530bool X86::isPSHUFHWMask(SDNode *N) { 1531 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1532 1533 if (N->getNumOperands() != 8) 1534 return false; 1535 1536 // Lower quadword copied in order. 1537 for (unsigned i = 0; i != 4; ++i) { 1538 SDOperand Arg = N->getOperand(i); 1539 if (Arg.getOpcode() == ISD::UNDEF) continue; 1540 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1541 if (cast<ConstantSDNode>(Arg)->getValue() != i) 1542 return false; 1543 } 1544 1545 // Upper quadword shuffled. 1546 for (unsigned i = 4; i != 8; ++i) { 1547 SDOperand Arg = N->getOperand(i); 1548 if (Arg.getOpcode() == ISD::UNDEF) continue; 1549 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1550 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 1551 if (Val < 4 || Val > 7) 1552 return false; 1553 } 1554 1555 return true; 1556} 1557 1558/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 1559/// specifies a shuffle of elements that is suitable for input to PSHUFLW. 1560bool X86::isPSHUFLWMask(SDNode *N) { 1561 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1562 1563 if (N->getNumOperands() != 8) 1564 return false; 1565 1566 // Upper quadword copied in order. 1567 for (unsigned i = 4; i != 8; ++i) 1568 if (!isUndefOrEqual(N->getOperand(i), i)) 1569 return false; 1570 1571 // Lower quadword shuffled. 1572 for (unsigned i = 0; i != 4; ++i) 1573 if (!isUndefOrInRange(N->getOperand(i), 0, 4)) 1574 return false; 1575 1576 return true; 1577} 1578 1579/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 1580/// specifies a shuffle of elements that is suitable for input to SHUFP*. 1581static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) { 1582 if (NumElems != 2 && NumElems != 4) return false; 1583 1584 unsigned Half = NumElems / 2; 1585 for (unsigned i = 0; i < Half; ++i) 1586 if (!isUndefOrInRange(Elems[i], 0, NumElems)) 1587 return false; 1588 for (unsigned i = Half; i < NumElems; ++i) 1589 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2)) 1590 return false; 1591 1592 return true; 1593} 1594 1595bool X86::isSHUFPMask(SDNode *N) { 1596 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1597 return ::isSHUFPMask(N->op_begin(), N->getNumOperands()); 1598} 1599 1600/// isCommutedSHUFP - Returns true if the shuffle mask is except 1601/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 1602/// half elements to come from vector 1 (which would equal the dest.) and 1603/// the upper half to come from vector 2. 1604static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) { 1605 if (NumOps != 2 && NumOps != 4) return false; 1606 1607 unsigned Half = NumOps / 2; 1608 for (unsigned i = 0; i < Half; ++i) 1609 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2)) 1610 return false; 1611 for (unsigned i = Half; i < NumOps; ++i) 1612 if (!isUndefOrInRange(Ops[i], 0, NumOps)) 1613 return false; 1614 return true; 1615} 1616 1617static bool isCommutedSHUFP(SDNode *N) { 1618 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1619 return isCommutedSHUFP(N->op_begin(), N->getNumOperands()); 1620} 1621 1622/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 1623/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 1624bool X86::isMOVHLPSMask(SDNode *N) { 1625 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1626 1627 if (N->getNumOperands() != 4) 1628 return false; 1629 1630 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 1631 return isUndefOrEqual(N->getOperand(0), 6) && 1632 isUndefOrEqual(N->getOperand(1), 7) && 1633 isUndefOrEqual(N->getOperand(2), 2) && 1634 isUndefOrEqual(N->getOperand(3), 3); 1635} 1636 1637/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 1638/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 1639/// <2, 3, 2, 3> 1640bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) { 1641 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1642 1643 if (N->getNumOperands() != 4) 1644 return false; 1645 1646 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3 1647 return isUndefOrEqual(N->getOperand(0), 2) && 1648 isUndefOrEqual(N->getOperand(1), 3) && 1649 isUndefOrEqual(N->getOperand(2), 2) && 1650 isUndefOrEqual(N->getOperand(3), 3); 1651} 1652 1653/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 1654/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 1655bool X86::isMOVLPMask(SDNode *N) { 1656 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1657 1658 unsigned NumElems = N->getNumOperands(); 1659 if (NumElems != 2 && NumElems != 4) 1660 return false; 1661 1662 for (unsigned i = 0; i < NumElems/2; ++i) 1663 if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) 1664 return false; 1665 1666 for (unsigned i = NumElems/2; i < NumElems; ++i) 1667 if (!isUndefOrEqual(N->getOperand(i), i)) 1668 return false; 1669 1670 return true; 1671} 1672 1673/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 1674/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 1675/// and MOVLHPS. 1676bool X86::isMOVHPMask(SDNode *N) { 1677 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1678 1679 unsigned NumElems = N->getNumOperands(); 1680 if (NumElems != 2 && NumElems != 4) 1681 return false; 1682 1683 for (unsigned i = 0; i < NumElems/2; ++i) 1684 if (!isUndefOrEqual(N->getOperand(i), i)) 1685 return false; 1686 1687 for (unsigned i = 0; i < NumElems/2; ++i) { 1688 SDOperand Arg = N->getOperand(i + NumElems/2); 1689 if (!isUndefOrEqual(Arg, i + NumElems)) 1690 return false; 1691 } 1692 1693 return true; 1694} 1695 1696/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 1697/// specifies a shuffle of elements that is suitable for input to UNPCKL. 1698bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts, 1699 bool V2IsSplat = false) { 1700 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 1701 return false; 1702 1703 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 1704 SDOperand BitI = Elts[i]; 1705 SDOperand BitI1 = Elts[i+1]; 1706 if (!isUndefOrEqual(BitI, j)) 1707 return false; 1708 if (V2IsSplat) { 1709 if (isUndefOrEqual(BitI1, NumElts)) 1710 return false; 1711 } else { 1712 if (!isUndefOrEqual(BitI1, j + NumElts)) 1713 return false; 1714 } 1715 } 1716 1717 return true; 1718} 1719 1720bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { 1721 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1722 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 1723} 1724 1725/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 1726/// specifies a shuffle of elements that is suitable for input to UNPCKH. 1727bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts, 1728 bool V2IsSplat = false) { 1729 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 1730 return false; 1731 1732 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 1733 SDOperand BitI = Elts[i]; 1734 SDOperand BitI1 = Elts[i+1]; 1735 if (!isUndefOrEqual(BitI, j + NumElts/2)) 1736 return false; 1737 if (V2IsSplat) { 1738 if (isUndefOrEqual(BitI1, NumElts)) 1739 return false; 1740 } else { 1741 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 1742 return false; 1743 } 1744 } 1745 1746 return true; 1747} 1748 1749bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { 1750 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1751 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 1752} 1753 1754/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 1755/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 1756/// <0, 0, 1, 1> 1757bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { 1758 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1759 1760 unsigned NumElems = N->getNumOperands(); 1761 if (NumElems != 4 && NumElems != 8 && NumElems != 16) 1762 return false; 1763 1764 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 1765 SDOperand BitI = N->getOperand(i); 1766 SDOperand BitI1 = N->getOperand(i+1); 1767 1768 if (!isUndefOrEqual(BitI, j)) 1769 return false; 1770 if (!isUndefOrEqual(BitI1, j)) 1771 return false; 1772 } 1773 1774 return true; 1775} 1776 1777/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 1778/// specifies a shuffle of elements that is suitable for input to MOVSS, 1779/// MOVSD, and MOVD, i.e. setting the lowest element. 1780static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) { 1781 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 1782 return false; 1783 1784 if (!isUndefOrEqual(Elts[0], NumElts)) 1785 return false; 1786 1787 for (unsigned i = 1; i < NumElts; ++i) { 1788 if (!isUndefOrEqual(Elts[i], i)) 1789 return false; 1790 } 1791 1792 return true; 1793} 1794 1795bool X86::isMOVLMask(SDNode *N) { 1796 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1797 return ::isMOVLMask(N->op_begin(), N->getNumOperands()); 1798} 1799 1800/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 1801/// of what x86 movss want. X86 movs requires the lowest element to be lowest 1802/// element of vector 2 and the other elements to come from vector 1 in order. 1803static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps, 1804 bool V2IsSplat = false, 1805 bool V2IsUndef = false) { 1806 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 1807 return false; 1808 1809 if (!isUndefOrEqual(Ops[0], 0)) 1810 return false; 1811 1812 for (unsigned i = 1; i < NumOps; ++i) { 1813 SDOperand Arg = Ops[i]; 1814 if (!(isUndefOrEqual(Arg, i+NumOps) || 1815 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) || 1816 (V2IsSplat && isUndefOrEqual(Arg, NumOps)))) 1817 return false; 1818 } 1819 1820 return true; 1821} 1822 1823static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, 1824 bool V2IsUndef = false) { 1825 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1826 return isCommutedMOVL(N->op_begin(), N->getNumOperands(), 1827 V2IsSplat, V2IsUndef); 1828} 1829 1830/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 1831/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 1832bool X86::isMOVSHDUPMask(SDNode *N) { 1833 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1834 1835 if (N->getNumOperands() != 4) 1836 return false; 1837 1838 // Expect 1, 1, 3, 3 1839 for (unsigned i = 0; i < 2; ++i) { 1840 SDOperand Arg = N->getOperand(i); 1841 if (Arg.getOpcode() == ISD::UNDEF) continue; 1842 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1843 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 1844 if (Val != 1) return false; 1845 } 1846 1847 bool HasHi = false; 1848 for (unsigned i = 2; i < 4; ++i) { 1849 SDOperand Arg = N->getOperand(i); 1850 if (Arg.getOpcode() == ISD::UNDEF) continue; 1851 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1852 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 1853 if (Val != 3) return false; 1854 HasHi = true; 1855 } 1856 1857 // Don't use movshdup if it can be done with a shufps. 1858 return HasHi; 1859} 1860 1861/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 1862/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 1863bool X86::isMOVSLDUPMask(SDNode *N) { 1864 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1865 1866 if (N->getNumOperands() != 4) 1867 return false; 1868 1869 // Expect 0, 0, 2, 2 1870 for (unsigned i = 0; i < 2; ++i) { 1871 SDOperand Arg = N->getOperand(i); 1872 if (Arg.getOpcode() == ISD::UNDEF) continue; 1873 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1874 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 1875 if (Val != 0) return false; 1876 } 1877 1878 bool HasHi = false; 1879 for (unsigned i = 2; i < 4; ++i) { 1880 SDOperand Arg = N->getOperand(i); 1881 if (Arg.getOpcode() == ISD::UNDEF) continue; 1882 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1883 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 1884 if (Val != 2) return false; 1885 HasHi = true; 1886 } 1887 1888 // Don't use movshdup if it can be done with a shufps. 1889 return HasHi; 1890} 1891 1892/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 1893/// a splat of a single element. 1894static bool isSplatMask(SDNode *N) { 1895 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1896 1897 // This is a splat operation if each element of the permute is the same, and 1898 // if the value doesn't reference the second vector. 1899 unsigned NumElems = N->getNumOperands(); 1900 SDOperand ElementBase; 1901 unsigned i = 0; 1902 for (; i != NumElems; ++i) { 1903 SDOperand Elt = N->getOperand(i); 1904 if (isa<ConstantSDNode>(Elt)) { 1905 ElementBase = Elt; 1906 break; 1907 } 1908 } 1909 1910 if (!ElementBase.Val) 1911 return false; 1912 1913 for (; i != NumElems; ++i) { 1914 SDOperand Arg = N->getOperand(i); 1915 if (Arg.getOpcode() == ISD::UNDEF) continue; 1916 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1917 if (Arg != ElementBase) return false; 1918 } 1919 1920 // Make sure it is a splat of the first vector operand. 1921 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems; 1922} 1923 1924/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 1925/// a splat of a single element and it's a 2 or 4 element mask. 1926bool X86::isSplatMask(SDNode *N) { 1927 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1928 1929 // We can only splat 64-bit, and 32-bit quantities with a single instruction. 1930 if (N->getNumOperands() != 4 && N->getNumOperands() != 2) 1931 return false; 1932 return ::isSplatMask(N); 1933} 1934 1935/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand 1936/// specifies a splat of zero element. 1937bool X86::isSplatLoMask(SDNode *N) { 1938 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1939 1940 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 1941 if (!isUndefOrEqual(N->getOperand(i), 0)) 1942 return false; 1943 return true; 1944} 1945 1946/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 1947/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 1948/// instructions. 1949unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 1950 unsigned NumOperands = N->getNumOperands(); 1951 unsigned Shift = (NumOperands == 4) ? 2 : 1; 1952 unsigned Mask = 0; 1953 for (unsigned i = 0; i < NumOperands; ++i) { 1954 unsigned Val = 0; 1955 SDOperand Arg = N->getOperand(NumOperands-i-1); 1956 if (Arg.getOpcode() != ISD::UNDEF) 1957 Val = cast<ConstantSDNode>(Arg)->getValue(); 1958 if (Val >= NumOperands) Val -= NumOperands; 1959 Mask |= Val; 1960 if (i != NumOperands - 1) 1961 Mask <<= Shift; 1962 } 1963 1964 return Mask; 1965} 1966 1967/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 1968/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 1969/// instructions. 1970unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 1971 unsigned Mask = 0; 1972 // 8 nodes, but we only care about the last 4. 1973 for (unsigned i = 7; i >= 4; --i) { 1974 unsigned Val = 0; 1975 SDOperand Arg = N->getOperand(i); 1976 if (Arg.getOpcode() != ISD::UNDEF) 1977 Val = cast<ConstantSDNode>(Arg)->getValue(); 1978 Mask |= (Val - 4); 1979 if (i != 4) 1980 Mask <<= 2; 1981 } 1982 1983 return Mask; 1984} 1985 1986/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 1987/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 1988/// instructions. 1989unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 1990 unsigned Mask = 0; 1991 // 8 nodes, but we only care about the first 4. 1992 for (int i = 3; i >= 0; --i) { 1993 unsigned Val = 0; 1994 SDOperand Arg = N->getOperand(i); 1995 if (Arg.getOpcode() != ISD::UNDEF) 1996 Val = cast<ConstantSDNode>(Arg)->getValue(); 1997 Mask |= Val; 1998 if (i != 0) 1999 Mask <<= 2; 2000 } 2001 2002 return Mask; 2003} 2004 2005/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand 2006/// specifies a 8 element shuffle that can be broken into a pair of 2007/// PSHUFHW and PSHUFLW. 2008static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { 2009 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2010 2011 if (N->getNumOperands() != 8) 2012 return false; 2013 2014 // Lower quadword shuffled. 2015 for (unsigned i = 0; i != 4; ++i) { 2016 SDOperand Arg = N->getOperand(i); 2017 if (Arg.getOpcode() == ISD::UNDEF) continue; 2018 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2019 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2020 if (Val > 4) 2021 return false; 2022 } 2023 2024 // Upper quadword shuffled. 2025 for (unsigned i = 4; i != 8; ++i) { 2026 SDOperand Arg = N->getOperand(i); 2027 if (Arg.getOpcode() == ISD::UNDEF) continue; 2028 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2029 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2030 if (Val < 4 || Val > 7) 2031 return false; 2032 } 2033 2034 return true; 2035} 2036 2037/// CommuteVectorShuffle - Swap vector_shuffle operandsas well as 2038/// values in ther permute mask. 2039static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1, 2040 SDOperand &V2, SDOperand &Mask, 2041 SelectionDAG &DAG) { 2042 MVT::ValueType VT = Op.getValueType(); 2043 MVT::ValueType MaskVT = Mask.getValueType(); 2044 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT); 2045 unsigned NumElems = Mask.getNumOperands(); 2046 SmallVector<SDOperand, 8> MaskVec; 2047 2048 for (unsigned i = 0; i != NumElems; ++i) { 2049 SDOperand Arg = Mask.getOperand(i); 2050 if (Arg.getOpcode() == ISD::UNDEF) { 2051 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2052 continue; 2053 } 2054 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2055 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2056 if (Val < NumElems) 2057 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2058 else 2059 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2060 } 2061 2062 std::swap(V1, V2); 2063 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2064 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2065} 2066 2067/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2068/// match movhlps. The lower half elements should come from upper half of 2069/// V1 (and in order), and the upper half elements should come from the upper 2070/// half of V2 (and in order). 2071static bool ShouldXformToMOVHLPS(SDNode *Mask) { 2072 unsigned NumElems = Mask->getNumOperands(); 2073 if (NumElems != 4) 2074 return false; 2075 for (unsigned i = 0, e = 2; i != e; ++i) 2076 if (!isUndefOrEqual(Mask->getOperand(i), i+2)) 2077 return false; 2078 for (unsigned i = 2; i != 4; ++i) 2079 if (!isUndefOrEqual(Mask->getOperand(i), i+4)) 2080 return false; 2081 return true; 2082} 2083 2084/// isScalarLoadToVector - Returns true if the node is a scalar load that 2085/// is promoted to a vector. 2086static inline bool isScalarLoadToVector(SDNode *N) { 2087 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { 2088 N = N->getOperand(0).Val; 2089 return ISD::isNON_EXTLoad(N); 2090 } 2091 return false; 2092} 2093 2094/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2095/// match movlp{s|d}. The lower half elements should come from lower half of 2096/// V1 (and in order), and the upper half elements should come from the upper 2097/// half of V2 (and in order). And since V1 will become the source of the 2098/// MOVLP, it must be either a vector load or a scalar load to vector. 2099static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) { 2100 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2101 return false; 2102 // Is V2 is a vector load, don't do this transformation. We will try to use 2103 // load folding shufps op. 2104 if (ISD::isNON_EXTLoad(V2)) 2105 return false; 2106 2107 unsigned NumElems = Mask->getNumOperands(); 2108 if (NumElems != 2 && NumElems != 4) 2109 return false; 2110 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2111 if (!isUndefOrEqual(Mask->getOperand(i), i)) 2112 return false; 2113 for (unsigned i = NumElems/2; i != NumElems; ++i) 2114 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) 2115 return false; 2116 return true; 2117} 2118 2119/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2120/// all the same. 2121static bool isSplatVector(SDNode *N) { 2122 if (N->getOpcode() != ISD::BUILD_VECTOR) 2123 return false; 2124 2125 SDOperand SplatValue = N->getOperand(0); 2126 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2127 if (N->getOperand(i) != SplatValue) 2128 return false; 2129 return true; 2130} 2131 2132/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2133/// to an undef. 2134static bool isUndefShuffle(SDNode *N) { 2135 if (N->getOpcode() != ISD::BUILD_VECTOR) 2136 return false; 2137 2138 SDOperand V1 = N->getOperand(0); 2139 SDOperand V2 = N->getOperand(1); 2140 SDOperand Mask = N->getOperand(2); 2141 unsigned NumElems = Mask.getNumOperands(); 2142 for (unsigned i = 0; i != NumElems; ++i) { 2143 SDOperand Arg = Mask.getOperand(i); 2144 if (Arg.getOpcode() != ISD::UNDEF) { 2145 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2146 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) 2147 return false; 2148 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) 2149 return false; 2150 } 2151 } 2152 return true; 2153} 2154 2155/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2156/// that point to V2 points to its first element. 2157static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) { 2158 assert(Mask.getOpcode() == ISD::BUILD_VECTOR); 2159 2160 bool Changed = false; 2161 SmallVector<SDOperand, 8> MaskVec; 2162 unsigned NumElems = Mask.getNumOperands(); 2163 for (unsigned i = 0; i != NumElems; ++i) { 2164 SDOperand Arg = Mask.getOperand(i); 2165 if (Arg.getOpcode() != ISD::UNDEF) { 2166 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2167 if (Val > NumElems) { 2168 Arg = DAG.getConstant(NumElems, Arg.getValueType()); 2169 Changed = true; 2170 } 2171 } 2172 MaskVec.push_back(Arg); 2173 } 2174 2175 if (Changed) 2176 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), 2177 &MaskVec[0], MaskVec.size()); 2178 return Mask; 2179} 2180 2181/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2182/// operation of specified width. 2183static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { 2184 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2185 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 2186 2187 SmallVector<SDOperand, 8> MaskVec; 2188 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); 2189 for (unsigned i = 1; i != NumElems; ++i) 2190 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2191 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2192} 2193 2194/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation 2195/// of specified width. 2196static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { 2197 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2198 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 2199 SmallVector<SDOperand, 8> MaskVec; 2200 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 2201 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2202 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); 2203 } 2204 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2205} 2206 2207/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation 2208/// of specified width. 2209static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { 2210 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2211 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 2212 unsigned Half = NumElems/2; 2213 SmallVector<SDOperand, 8> MaskVec; 2214 for (unsigned i = 0; i != Half; ++i) { 2215 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); 2216 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); 2217 } 2218 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2219} 2220 2221/// getZeroVector - Returns a vector of specified type with all zero elements. 2222/// 2223static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) { 2224 assert(MVT::isVector(VT) && "Expected a vector type"); 2225 unsigned NumElems = getVectorNumElements(VT); 2226 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 2227 bool isFP = MVT::isFloatingPoint(EVT); 2228 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT); 2229 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero); 2230 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size()); 2231} 2232 2233/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32. 2234/// 2235static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) { 2236 SDOperand V1 = Op.getOperand(0); 2237 SDOperand Mask = Op.getOperand(2); 2238 MVT::ValueType VT = Op.getValueType(); 2239 unsigned NumElems = Mask.getNumOperands(); 2240 Mask = getUnpacklMask(NumElems, DAG); 2241 while (NumElems != 4) { 2242 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); 2243 NumElems >>= 1; 2244 } 2245 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1); 2246 2247 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 2248 Mask = getZeroVector(MaskVT, DAG); 2249 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1, 2250 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask); 2251 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 2252} 2253 2254/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2255/// constant +0.0. 2256static inline bool isZeroNode(SDOperand Elt) { 2257 return ((isa<ConstantSDNode>(Elt) && 2258 cast<ConstantSDNode>(Elt)->getValue() == 0) || 2259 (isa<ConstantFPSDNode>(Elt) && 2260 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0))); 2261} 2262 2263/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 2264/// vector and zero or undef vector. 2265static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT, 2266 unsigned NumElems, unsigned Idx, 2267 bool isZero, SelectionDAG &DAG) { 2268 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT); 2269 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2270 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT); 2271 SDOperand Zero = DAG.getConstant(0, EVT); 2272 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero); 2273 MaskVec[Idx] = DAG.getConstant(NumElems, EVT); 2274 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2275 &MaskVec[0], MaskVec.size()); 2276 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2277} 2278 2279/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 2280/// 2281static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros, 2282 unsigned NumNonZero, unsigned NumZero, 2283 SelectionDAG &DAG, TargetLowering &TLI) { 2284 if (NumNonZero > 8) 2285 return SDOperand(); 2286 2287 SDOperand V(0, 0); 2288 bool First = true; 2289 for (unsigned i = 0; i < 16; ++i) { 2290 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 2291 if (ThisIsNonZero && First) { 2292 if (NumZero) 2293 V = getZeroVector(MVT::v8i16, DAG); 2294 else 2295 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 2296 First = false; 2297 } 2298 2299 if ((i & 1) != 0) { 2300 SDOperand ThisElt(0, 0), LastElt(0, 0); 2301 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 2302 if (LastIsNonZero) { 2303 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); 2304 } 2305 if (ThisIsNonZero) { 2306 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); 2307 ThisElt = DAG.getNode(ISD::SHL, MVT::i16, 2308 ThisElt, DAG.getConstant(8, MVT::i8)); 2309 if (LastIsNonZero) 2310 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); 2311 } else 2312 ThisElt = LastElt; 2313 2314 if (ThisElt.Val) 2315 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, 2316 DAG.getConstant(i/2, TLI.getPointerTy())); 2317 } 2318 } 2319 2320 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); 2321} 2322 2323/// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16. 2324/// 2325static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros, 2326 unsigned NumNonZero, unsigned NumZero, 2327 SelectionDAG &DAG, TargetLowering &TLI) { 2328 if (NumNonZero > 4) 2329 return SDOperand(); 2330 2331 SDOperand V(0, 0); 2332 bool First = true; 2333 for (unsigned i = 0; i < 8; ++i) { 2334 bool isNonZero = (NonZeros & (1 << i)) != 0; 2335 if (isNonZero) { 2336 if (First) { 2337 if (NumZero) 2338 V = getZeroVector(MVT::v8i16, DAG); 2339 else 2340 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 2341 First = false; 2342 } 2343 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), 2344 DAG.getConstant(i, TLI.getPointerTy())); 2345 } 2346 } 2347 2348 return V; 2349} 2350 2351SDOperand 2352X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2353 // All zero's are handled with pxor. 2354 if (ISD::isBuildVectorAllZeros(Op.Val)) 2355 return Op; 2356 2357 // All one's are handled with pcmpeqd. 2358 if (ISD::isBuildVectorAllOnes(Op.Val)) 2359 return Op; 2360 2361 MVT::ValueType VT = Op.getValueType(); 2362 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 2363 unsigned EVTBits = MVT::getSizeInBits(EVT); 2364 2365 unsigned NumElems = Op.getNumOperands(); 2366 unsigned NumZero = 0; 2367 unsigned NumNonZero = 0; 2368 unsigned NonZeros = 0; 2369 std::set<SDOperand> Values; 2370 for (unsigned i = 0; i < NumElems; ++i) { 2371 SDOperand Elt = Op.getOperand(i); 2372 if (Elt.getOpcode() != ISD::UNDEF) { 2373 Values.insert(Elt); 2374 if (isZeroNode(Elt)) 2375 NumZero++; 2376 else { 2377 NonZeros |= (1 << i); 2378 NumNonZero++; 2379 } 2380 } 2381 } 2382 2383 if (NumNonZero == 0) 2384 // Must be a mix of zero and undef. Return a zero vector. 2385 return getZeroVector(VT, DAG); 2386 2387 // Splat is obviously ok. Let legalizer expand it to a shuffle. 2388 if (Values.size() == 1) 2389 return SDOperand(); 2390 2391 // Special case for single non-zero element. 2392 if (NumNonZero == 1) { 2393 unsigned Idx = CountTrailingZeros_32(NonZeros); 2394 SDOperand Item = Op.getOperand(Idx); 2395 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 2396 if (Idx == 0) 2397 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 2398 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx, 2399 NumZero > 0, DAG); 2400 2401 if (EVTBits == 32) { 2402 // Turn it into a shuffle of zero and zero-extended scalar to vector. 2403 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0, 2404 DAG); 2405 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2406 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT); 2407 SmallVector<SDOperand, 8> MaskVec; 2408 for (unsigned i = 0; i < NumElems; i++) 2409 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); 2410 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2411 &MaskVec[0], MaskVec.size()); 2412 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, 2413 DAG.getNode(ISD::UNDEF, VT), Mask); 2414 } 2415 } 2416 2417 // Let legalizer expand 2-wide build_vector's. 2418 if (EVTBits == 64) 2419 return SDOperand(); 2420 2421 // If element VT is < 32 bits, convert it to inserts into a zero vector. 2422 if (EVTBits == 8) { 2423 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 2424 *this); 2425 if (V.Val) return V; 2426 } 2427 2428 if (EVTBits == 16) { 2429 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 2430 *this); 2431 if (V.Val) return V; 2432 } 2433 2434 // If element VT is == 32 bits, turn it into a number of shuffles. 2435 SmallVector<SDOperand, 8> V; 2436 V.resize(NumElems); 2437 if (NumElems == 4 && NumZero > 0) { 2438 for (unsigned i = 0; i < 4; ++i) { 2439 bool isZero = !(NonZeros & (1 << i)); 2440 if (isZero) 2441 V[i] = getZeroVector(VT, DAG); 2442 else 2443 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 2444 } 2445 2446 for (unsigned i = 0; i < 2; ++i) { 2447 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 2448 default: break; 2449 case 0: 2450 V[i] = V[i*2]; // Must be a zero vector. 2451 break; 2452 case 1: 2453 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], 2454 getMOVLMask(NumElems, DAG)); 2455 break; 2456 case 2: 2457 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 2458 getMOVLMask(NumElems, DAG)); 2459 break; 2460 case 3: 2461 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 2462 getUnpacklMask(NumElems, DAG)); 2463 break; 2464 } 2465 } 2466 2467 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd) 2468 // clears the upper bits. 2469 // FIXME: we can do the same for v4f32 case when we know both parts of 2470 // the lower half come from scalar_to_vector (loadf32). We should do 2471 // that in post legalizer dag combiner with target specific hooks. 2472 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0) 2473 return V[0]; 2474 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2475 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT); 2476 SmallVector<SDOperand, 8> MaskVec; 2477 bool Reverse = (NonZeros & 0x3) == 2; 2478 for (unsigned i = 0; i < 2; ++i) 2479 if (Reverse) 2480 MaskVec.push_back(DAG.getConstant(1-i, EVT)); 2481 else 2482 MaskVec.push_back(DAG.getConstant(i, EVT)); 2483 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 2484 for (unsigned i = 0; i < 2; ++i) 2485 if (Reverse) 2486 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); 2487 else 2488 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); 2489 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2490 &MaskVec[0], MaskVec.size()); 2491 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); 2492 } 2493 2494 if (Values.size() > 2) { 2495 // Expand into a number of unpckl*. 2496 // e.g. for v4f32 2497 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 2498 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 2499 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 2500 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG); 2501 for (unsigned i = 0; i < NumElems; ++i) 2502 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 2503 NumElems >>= 1; 2504 while (NumElems != 0) { 2505 for (unsigned i = 0; i < NumElems; ++i) 2506 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], 2507 UnpckMask); 2508 NumElems >>= 1; 2509 } 2510 return V[0]; 2511 } 2512 2513 return SDOperand(); 2514} 2515 2516SDOperand 2517X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2518 SDOperand V1 = Op.getOperand(0); 2519 SDOperand V2 = Op.getOperand(1); 2520 SDOperand PermMask = Op.getOperand(2); 2521 MVT::ValueType VT = Op.getValueType(); 2522 unsigned NumElems = PermMask.getNumOperands(); 2523 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 2524 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 2525 bool V1IsSplat = false; 2526 bool V2IsSplat = false; 2527 2528 if (isUndefShuffle(Op.Val)) 2529 return DAG.getNode(ISD::UNDEF, VT); 2530 2531 if (isSplatMask(PermMask.Val)) { 2532 if (NumElems <= 4) return Op; 2533 // Promote it to a v4i32 splat. 2534 return PromoteSplat(Op, DAG); 2535 } 2536 2537 if (X86::isMOVLMask(PermMask.Val)) 2538 return (V1IsUndef) ? V2 : Op; 2539 2540 if (X86::isMOVSHDUPMask(PermMask.Val) || 2541 X86::isMOVSLDUPMask(PermMask.Val) || 2542 X86::isMOVHLPSMask(PermMask.Val) || 2543 X86::isMOVHPMask(PermMask.Val) || 2544 X86::isMOVLPMask(PermMask.Val)) 2545 return Op; 2546 2547 if (ShouldXformToMOVHLPS(PermMask.Val) || 2548 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val)) 2549 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 2550 2551 bool Commuted = false; 2552 V1IsSplat = isSplatVector(V1.Val); 2553 V2IsSplat = isSplatVector(V2.Val); 2554 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 2555 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 2556 std::swap(V1IsSplat, V2IsSplat); 2557 std::swap(V1IsUndef, V2IsUndef); 2558 Commuted = true; 2559 } 2560 2561 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) { 2562 if (V2IsUndef) return V1; 2563 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 2564 if (V2IsSplat) { 2565 // V2 is a splat, so the mask may be malformed. That is, it may point 2566 // to any V2 element. The instruction selectior won't like this. Get 2567 // a corrected mask and commute to form a proper MOVS{S|D}. 2568 SDOperand NewMask = getMOVLMask(NumElems, DAG); 2569 if (NewMask.Val != PermMask.Val) 2570 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 2571 } 2572 return Op; 2573 } 2574 2575 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 2576 X86::isUNPCKLMask(PermMask.Val) || 2577 X86::isUNPCKHMask(PermMask.Val)) 2578 return Op; 2579 2580 if (V2IsSplat) { 2581 // Normalize mask so all entries that point to V2 points to its first 2582 // element then try to match unpck{h|l} again. If match, return a 2583 // new vector_shuffle with the corrected mask. 2584 SDOperand NewMask = NormalizeMask(PermMask, DAG); 2585 if (NewMask.Val != PermMask.Val) { 2586 if (X86::isUNPCKLMask(PermMask.Val, true)) { 2587 SDOperand NewMask = getUnpacklMask(NumElems, DAG); 2588 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 2589 } else if (X86::isUNPCKHMask(PermMask.Val, true)) { 2590 SDOperand NewMask = getUnpackhMask(NumElems, DAG); 2591 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 2592 } 2593 } 2594 } 2595 2596 // Normalize the node to match x86 shuffle ops if needed 2597 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val)) 2598 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 2599 2600 if (Commuted) { 2601 // Commute is back and try unpck* again. 2602 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 2603 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 2604 X86::isUNPCKLMask(PermMask.Val) || 2605 X86::isUNPCKHMask(PermMask.Val)) 2606 return Op; 2607 } 2608 2609 // If VT is integer, try PSHUF* first, then SHUFP*. 2610 if (MVT::isInteger(VT)) { 2611 if (X86::isPSHUFDMask(PermMask.Val) || 2612 X86::isPSHUFHWMask(PermMask.Val) || 2613 X86::isPSHUFLWMask(PermMask.Val)) { 2614 if (V2.getOpcode() != ISD::UNDEF) 2615 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 2616 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); 2617 return Op; 2618 } 2619 2620 if (X86::isSHUFPMask(PermMask.Val)) 2621 return Op; 2622 2623 // Handle v8i16 shuffle high / low shuffle node pair. 2624 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) { 2625 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2626 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 2627 SmallVector<SDOperand, 8> MaskVec; 2628 for (unsigned i = 0; i != 4; ++i) 2629 MaskVec.push_back(PermMask.getOperand(i)); 2630 for (unsigned i = 4; i != 8; ++i) 2631 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2632 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2633 &MaskVec[0], MaskVec.size()); 2634 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2635 MaskVec.clear(); 2636 for (unsigned i = 0; i != 4; ++i) 2637 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2638 for (unsigned i = 4; i != 8; ++i) 2639 MaskVec.push_back(PermMask.getOperand(i)); 2640 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size()); 2641 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2642 } 2643 } else { 2644 // Floating point cases in the other order. 2645 if (X86::isSHUFPMask(PermMask.Val)) 2646 return Op; 2647 if (X86::isPSHUFDMask(PermMask.Val) || 2648 X86::isPSHUFHWMask(PermMask.Val) || 2649 X86::isPSHUFLWMask(PermMask.Val)) { 2650 if (V2.getOpcode() != ISD::UNDEF) 2651 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 2652 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); 2653 return Op; 2654 } 2655 } 2656 2657 if (NumElems == 4) { 2658 MVT::ValueType MaskVT = PermMask.getValueType(); 2659 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT); 2660 SmallVector<std::pair<int, int>, 8> Locs; 2661 Locs.reserve(NumElems); 2662 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 2663 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 2664 unsigned NumHi = 0; 2665 unsigned NumLo = 0; 2666 // If no more than two elements come from either vector. This can be 2667 // implemented with two shuffles. First shuffle gather the elements. 2668 // The second shuffle, which takes the first shuffle as both of its 2669 // vector operands, put the elements into the right order. 2670 for (unsigned i = 0; i != NumElems; ++i) { 2671 SDOperand Elt = PermMask.getOperand(i); 2672 if (Elt.getOpcode() == ISD::UNDEF) { 2673 Locs[i] = std::make_pair(-1, -1); 2674 } else { 2675 unsigned Val = cast<ConstantSDNode>(Elt)->getValue(); 2676 if (Val < NumElems) { 2677 Locs[i] = std::make_pair(0, NumLo); 2678 Mask1[NumLo] = Elt; 2679 NumLo++; 2680 } else { 2681 Locs[i] = std::make_pair(1, NumHi); 2682 if (2+NumHi < NumElems) 2683 Mask1[2+NumHi] = Elt; 2684 NumHi++; 2685 } 2686 } 2687 } 2688 if (NumLo <= 2 && NumHi <= 2) { 2689 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 2690 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2691 &Mask1[0], Mask1.size())); 2692 for (unsigned i = 0; i != NumElems; ++i) { 2693 if (Locs[i].first == -1) 2694 continue; 2695 else { 2696 unsigned Idx = (i < NumElems/2) ? 0 : NumElems; 2697 Idx += Locs[i].first * (NumElems/2) + Locs[i].second; 2698 Mask2[i] = DAG.getConstant(Idx, MaskEVT); 2699 } 2700 } 2701 2702 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, 2703 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2704 &Mask2[0], Mask2.size())); 2705 } 2706 2707 // Break it into (shuffle shuffle_hi, shuffle_lo). 2708 Locs.clear(); 2709 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 2710 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 2711 SmallVector<SDOperand,8> *MaskPtr = &LoMask; 2712 unsigned MaskIdx = 0; 2713 unsigned LoIdx = 0; 2714 unsigned HiIdx = NumElems/2; 2715 for (unsigned i = 0; i != NumElems; ++i) { 2716 if (i == NumElems/2) { 2717 MaskPtr = &HiMask; 2718 MaskIdx = 1; 2719 LoIdx = 0; 2720 HiIdx = NumElems/2; 2721 } 2722 SDOperand Elt = PermMask.getOperand(i); 2723 if (Elt.getOpcode() == ISD::UNDEF) { 2724 Locs[i] = std::make_pair(-1, -1); 2725 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) { 2726 Locs[i] = std::make_pair(MaskIdx, LoIdx); 2727 (*MaskPtr)[LoIdx] = Elt; 2728 LoIdx++; 2729 } else { 2730 Locs[i] = std::make_pair(MaskIdx, HiIdx); 2731 (*MaskPtr)[HiIdx] = Elt; 2732 HiIdx++; 2733 } 2734 } 2735 2736 SDOperand LoShuffle = 2737 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 2738 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2739 &LoMask[0], LoMask.size())); 2740 SDOperand HiShuffle = 2741 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 2742 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2743 &HiMask[0], HiMask.size())); 2744 SmallVector<SDOperand, 8> MaskOps; 2745 for (unsigned i = 0; i != NumElems; ++i) { 2746 if (Locs[i].first == -1) { 2747 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 2748 } else { 2749 unsigned Idx = Locs[i].first * NumElems + Locs[i].second; 2750 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); 2751 } 2752 } 2753 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, 2754 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2755 &MaskOps[0], MaskOps.size())); 2756 } 2757 2758 return SDOperand(); 2759} 2760 2761SDOperand 2762X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { 2763 if (!isa<ConstantSDNode>(Op.getOperand(1))) 2764 return SDOperand(); 2765 2766 MVT::ValueType VT = Op.getValueType(); 2767 // TODO: handle v16i8. 2768 if (MVT::getSizeInBits(VT) == 16) { 2769 // Transform it so it match pextrw which produces a 32-bit result. 2770 MVT::ValueType EVT = (MVT::ValueType)(VT+1); 2771 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT, 2772 Op.getOperand(0), Op.getOperand(1)); 2773 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, 2774 DAG.getValueType(VT)); 2775 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 2776 } else if (MVT::getSizeInBits(VT) == 32) { 2777 SDOperand Vec = Op.getOperand(0); 2778 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 2779 if (Idx == 0) 2780 return Op; 2781 // SHUFPS the element to the lowest double word, then movss. 2782 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 2783 SmallVector<SDOperand, 8> IdxVec; 2784 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT))); 2785 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 2786 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 2787 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 2788 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2789 &IdxVec[0], IdxVec.size()); 2790 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 2791 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 2792 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 2793 DAG.getConstant(0, getPointerTy())); 2794 } else if (MVT::getSizeInBits(VT) == 64) { 2795 SDOperand Vec = Op.getOperand(0); 2796 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 2797 if (Idx == 0) 2798 return Op; 2799 2800 // UNPCKHPD the element to the lowest double word, then movsd. 2801 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 2802 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 2803 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 2804 SmallVector<SDOperand, 8> IdxVec; 2805 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT))); 2806 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); 2807 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2808 &IdxVec[0], IdxVec.size()); 2809 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 2810 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 2811 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 2812 DAG.getConstant(0, getPointerTy())); 2813 } 2814 2815 return SDOperand(); 2816} 2817 2818SDOperand 2819X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { 2820 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 2821 // as its second argument. 2822 MVT::ValueType VT = Op.getValueType(); 2823 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT); 2824 SDOperand N0 = Op.getOperand(0); 2825 SDOperand N1 = Op.getOperand(1); 2826 SDOperand N2 = Op.getOperand(2); 2827 if (MVT::getSizeInBits(BaseVT) == 16) { 2828 if (N1.getValueType() != MVT::i32) 2829 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 2830 if (N2.getValueType() != MVT::i32) 2831 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32); 2832 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); 2833 } else if (MVT::getSizeInBits(BaseVT) == 32) { 2834 unsigned Idx = cast<ConstantSDNode>(N2)->getValue(); 2835 if (Idx == 0) { 2836 // Use a movss. 2837 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1); 2838 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 2839 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT); 2840 SmallVector<SDOperand, 8> MaskVec; 2841 MaskVec.push_back(DAG.getConstant(4, BaseVT)); 2842 for (unsigned i = 1; i <= 3; ++i) 2843 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2844 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1, 2845 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2846 &MaskVec[0], MaskVec.size())); 2847 } else { 2848 // Use two pinsrw instructions to insert a 32 bit value. 2849 Idx <<= 1; 2850 if (MVT::isFloatingPoint(N1.getValueType())) { 2851 if (ISD::isNON_EXTLoad(N1.Val)) { 2852 // Just load directly from f32mem to GR32. 2853 LoadSDNode *LD = cast<LoadSDNode>(N1); 2854 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(), 2855 LD->getSrcValue(), LD->getSrcValueOffset()); 2856 } else { 2857 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1); 2858 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1); 2859 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1, 2860 DAG.getConstant(0, getPointerTy())); 2861 } 2862 } 2863 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0); 2864 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1, 2865 DAG.getConstant(Idx, getPointerTy())); 2866 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8)); 2867 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1, 2868 DAG.getConstant(Idx+1, getPointerTy())); 2869 return DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2870 } 2871 } 2872 2873 return SDOperand(); 2874} 2875 2876SDOperand 2877X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2878 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); 2879 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt); 2880} 2881 2882// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 2883// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 2884// one of the above mentioned nodes. It has to be wrapped because otherwise 2885// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 2886// be used to form addressing mode. These wrapped nodes will be selected 2887// into MOV32ri. 2888SDOperand 2889X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 2890 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 2891 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(), 2892 getPointerTy(), 2893 CP->getAlignment()); 2894 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 2895 // With PIC, the address is actually $g + Offset. 2896 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2897 !Subtarget->isPICStyleRIPRel()) { 2898 Result = DAG.getNode(ISD::ADD, getPointerTy(), 2899 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 2900 Result); 2901 } 2902 2903 return Result; 2904} 2905 2906SDOperand 2907X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 2908 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2909 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy()); 2910 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 2911 // With PIC, the address is actually $g + Offset. 2912 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2913 !Subtarget->isPICStyleRIPRel()) { 2914 Result = DAG.getNode(ISD::ADD, getPointerTy(), 2915 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 2916 Result); 2917 } 2918 2919 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to 2920 // load the value at address GV, not the value of GV itself. This means that 2921 // the GlobalAddress must be in the base or index register of the address, not 2922 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call 2923 // The same applies for external symbols during PIC codegen 2924 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) 2925 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0); 2926 2927 return Result; 2928} 2929 2930SDOperand 2931X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) { 2932 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 2933 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 2934 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 2935 // With PIC, the address is actually $g + Offset. 2936 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2937 !Subtarget->isPICStyleRIPRel()) { 2938 Result = DAG.getNode(ISD::ADD, getPointerTy(), 2939 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 2940 Result); 2941 } 2942 2943 return Result; 2944} 2945 2946SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 2947 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 2948 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 2949 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 2950 // With PIC, the address is actually $g + Offset. 2951 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2952 !Subtarget->isPICStyleRIPRel()) { 2953 Result = DAG.getNode(ISD::ADD, getPointerTy(), 2954 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 2955 Result); 2956 } 2957 2958 return Result; 2959} 2960 2961SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { 2962 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2963 "Not an i64 shift!"); 2964 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 2965 SDOperand ShOpLo = Op.getOperand(0); 2966 SDOperand ShOpHi = Op.getOperand(1); 2967 SDOperand ShAmt = Op.getOperand(2); 2968 SDOperand Tmp1 = isSRA ? 2969 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) : 2970 DAG.getConstant(0, MVT::i32); 2971 2972 SDOperand Tmp2, Tmp3; 2973 if (Op.getOpcode() == ISD::SHL_PARTS) { 2974 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt); 2975 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt); 2976 } else { 2977 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt); 2978 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt); 2979 } 2980 2981 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 2982 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, 2983 DAG.getConstant(32, MVT::i8)); 2984 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)}; 2985 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1); 2986 2987 SDOperand Hi, Lo; 2988 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8); 2989 2990 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag); 2991 SmallVector<SDOperand, 4> Ops; 2992 if (Op.getOpcode() == ISD::SHL_PARTS) { 2993 Ops.push_back(Tmp2); 2994 Ops.push_back(Tmp3); 2995 Ops.push_back(CC); 2996 Ops.push_back(InFlag); 2997 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 2998 InFlag = Hi.getValue(1); 2999 3000 Ops.clear(); 3001 Ops.push_back(Tmp3); 3002 Ops.push_back(Tmp1); 3003 Ops.push_back(CC); 3004 Ops.push_back(InFlag); 3005 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3006 } else { 3007 Ops.push_back(Tmp2); 3008 Ops.push_back(Tmp3); 3009 Ops.push_back(CC); 3010 Ops.push_back(InFlag); 3011 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3012 InFlag = Lo.getValue(1); 3013 3014 Ops.clear(); 3015 Ops.push_back(Tmp3); 3016 Ops.push_back(Tmp1); 3017 Ops.push_back(CC); 3018 Ops.push_back(InFlag); 3019 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3020 } 3021 3022 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32); 3023 Ops.clear(); 3024 Ops.push_back(Lo); 3025 Ops.push_back(Hi); 3026 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size()); 3027} 3028 3029SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 3030 assert(Op.getOperand(0).getValueType() <= MVT::i64 && 3031 Op.getOperand(0).getValueType() >= MVT::i16 && 3032 "Unknown SINT_TO_FP to lower!"); 3033 3034 SDOperand Result; 3035 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3036 unsigned Size = MVT::getSizeInBits(SrcVT)/8; 3037 MachineFunction &MF = DAG.getMachineFunction(); 3038 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 3039 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3040 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), 3041 StackSlot, NULL, 0); 3042 3043 // Build the FILD 3044 SDVTList Tys; 3045 if (X86ScalarSSE) 3046 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 3047 else 3048 Tys = DAG.getVTList(MVT::f64, MVT::Other); 3049 SmallVector<SDOperand, 8> Ops; 3050 Ops.push_back(Chain); 3051 Ops.push_back(StackSlot); 3052 Ops.push_back(DAG.getValueType(SrcVT)); 3053 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD, 3054 Tys, &Ops[0], Ops.size()); 3055 3056 if (X86ScalarSSE) { 3057 Chain = Result.getValue(1); 3058 SDOperand InFlag = Result.getValue(2); 3059 3060 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 3061 // shouldn't be necessary except that RFP cannot be live across 3062 // multiple blocks. When stackifier is fixed, they can be uncoupled. 3063 MachineFunction &MF = DAG.getMachineFunction(); 3064 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3065 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3066 Tys = DAG.getVTList(MVT::Other); 3067 SmallVector<SDOperand, 8> Ops; 3068 Ops.push_back(Chain); 3069 Ops.push_back(Result); 3070 Ops.push_back(StackSlot); 3071 Ops.push_back(DAG.getValueType(Op.getValueType())); 3072 Ops.push_back(InFlag); 3073 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 3074 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0); 3075 } 3076 3077 return Result; 3078} 3079 3080SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 3081 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && 3082 "Unknown FP_TO_SINT to lower!"); 3083 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 3084 // stack slot. 3085 MachineFunction &MF = DAG.getMachineFunction(); 3086 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; 3087 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 3088 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3089 3090 unsigned Opc; 3091 switch (Op.getValueType()) { 3092 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 3093 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 3094 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 3095 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 3096 } 3097 3098 SDOperand Chain = DAG.getEntryNode(); 3099 SDOperand Value = Op.getOperand(0); 3100 if (X86ScalarSSE) { 3101 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 3102 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0); 3103 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other); 3104 SDOperand Ops[] = { 3105 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 3106 }; 3107 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); 3108 Chain = Value.getValue(1); 3109 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 3110 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 3111 } 3112 3113 // Build the FP_TO_INT*_IN_MEM 3114 SDOperand Ops[] = { Chain, Value, StackSlot }; 3115 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); 3116 3117 // Load the result. 3118 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); 3119} 3120 3121SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { 3122 MVT::ValueType VT = Op.getValueType(); 3123 const Type *OpNTy = MVT::getTypeForValueType(VT); 3124 std::vector<Constant*> CV; 3125 if (VT == MVT::f64) { 3126 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63)))); 3127 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3128 } else { 3129 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31)))); 3130 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3131 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3132 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3133 } 3134 Constant *CS = ConstantStruct::get(CV); 3135 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 3136 SDVTList Tys = DAG.getVTList(VT, MVT::Other); 3137 SmallVector<SDOperand, 3> Ops; 3138 Ops.push_back(DAG.getEntryNode()); 3139 Ops.push_back(CPIdx); 3140 Ops.push_back(DAG.getSrcValue(NULL)); 3141 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 3142 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); 3143} 3144 3145SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { 3146 MVT::ValueType VT = Op.getValueType(); 3147 const Type *OpNTy = MVT::getTypeForValueType(VT); 3148 std::vector<Constant*> CV; 3149 if (VT == MVT::f64) { 3150 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63))); 3151 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3152 } else { 3153 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31))); 3154 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3155 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3156 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 3157 } 3158 Constant *CS = ConstantStruct::get(CV); 3159 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 3160 SDVTList Tys = DAG.getVTList(VT, MVT::Other); 3161 SmallVector<SDOperand, 3> Ops; 3162 Ops.push_back(DAG.getEntryNode()); 3163 Ops.push_back(CPIdx); 3164 Ops.push_back(DAG.getSrcValue(NULL)); 3165 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 3166 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); 3167} 3168 3169SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { 3170 SDOperand Op0 = Op.getOperand(0); 3171 SDOperand Op1 = Op.getOperand(1); 3172 MVT::ValueType VT = Op.getValueType(); 3173 MVT::ValueType SrcVT = Op1.getValueType(); 3174 const Type *SrcTy = MVT::getTypeForValueType(SrcVT); 3175 3176 // If second operand is smaller, extend it first. 3177 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) { 3178 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); 3179 SrcVT = VT; 3180 } 3181 3182 // First get the sign bit of second operand. 3183 std::vector<Constant*> CV; 3184 if (SrcVT == MVT::f64) { 3185 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63))); 3186 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3187 } else { 3188 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31))); 3189 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3190 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3191 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3192 } 3193 Constant *CS = ConstantStruct::get(CV); 3194 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 3195 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other); 3196 SmallVector<SDOperand, 3> Ops; 3197 Ops.push_back(DAG.getEntryNode()); 3198 Ops.push_back(CPIdx); 3199 Ops.push_back(DAG.getSrcValue(NULL)); 3200 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 3201 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); 3202 3203 // Shift sign bit right or left if the two operands have different types. 3204 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) { 3205 // Op0 is MVT::f32, Op1 is MVT::f64. 3206 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); 3207 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, 3208 DAG.getConstant(32, MVT::i32)); 3209 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit); 3210 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit, 3211 DAG.getConstant(0, getPointerTy())); 3212 } 3213 3214 // Clear first operand sign bit. 3215 CV.clear(); 3216 if (VT == MVT::f64) { 3217 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63)))); 3218 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3219 } else { 3220 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31)))); 3221 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3222 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3223 CV.push_back(ConstantFP::get(SrcTy, 0.0)); 3224 } 3225 CS = ConstantStruct::get(CV); 3226 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 3227 Tys = DAG.getVTList(VT, MVT::Other); 3228 Ops.clear(); 3229 Ops.push_back(DAG.getEntryNode()); 3230 Ops.push_back(CPIdx); 3231 Ops.push_back(DAG.getSrcValue(NULL)); 3232 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size()); 3233 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); 3234 3235 // Or the value with the sign bit. 3236 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); 3237} 3238 3239SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG, 3240 SDOperand Chain) { 3241 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 3242 SDOperand Cond; 3243 SDOperand Op0 = Op.getOperand(0); 3244 SDOperand Op1 = Op.getOperand(1); 3245 SDOperand CC = Op.getOperand(2); 3246 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3247 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3248 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag); 3249 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); 3250 unsigned X86CC; 3251 3252 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, 3253 Op0, Op1, DAG)) { 3254 SDOperand Ops1[] = { Chain, Op0, Op1 }; 3255 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1); 3256 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond }; 3257 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2); 3258 } 3259 3260 assert(isFP && "Illegal integer SetCC!"); 3261 3262 SDOperand COps[] = { Chain, Op0, Op1 }; 3263 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1); 3264 3265 switch (SetCCOpcode) { 3266 default: assert(false && "Illegal floating point SetCC!"); 3267 case ISD::SETOEQ: { // !PF & ZF 3268 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond }; 3269 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2); 3270 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8), 3271 Tmp1.getValue(1) }; 3272 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2); 3273 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 3274 } 3275 case ISD::SETUNE: { // PF | !ZF 3276 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond }; 3277 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2); 3278 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8), 3279 Tmp1.getValue(1) }; 3280 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2); 3281 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 3282 } 3283 } 3284} 3285 3286SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { 3287 bool addTest = true; 3288 SDOperand Chain = DAG.getEntryNode(); 3289 SDOperand Cond = Op.getOperand(0); 3290 SDOperand CC; 3291 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3292 3293 if (Cond.getOpcode() == ISD::SETCC) 3294 Cond = LowerSETCC(Cond, DAG, Chain); 3295 3296 if (Cond.getOpcode() == X86ISD::SETCC) { 3297 CC = Cond.getOperand(0); 3298 3299 // If condition flag is set by a X86ISD::CMP, then make a copy of it 3300 // (since flag operand cannot be shared). Use it as the condition setting 3301 // operand in place of the X86ISD::SETCC. 3302 // If the X86ISD::SETCC has more than one use, then perhaps it's better 3303 // to use a test instead of duplicating the X86ISD::CMP (for register 3304 // pressure reason)? 3305 SDOperand Cmp = Cond.getOperand(1); 3306 unsigned Opc = Cmp.getOpcode(); 3307 bool IllegalFPCMov = !X86ScalarSSE && 3308 MVT::isFloatingPoint(Op.getValueType()) && 3309 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); 3310 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) && 3311 !IllegalFPCMov) { 3312 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) }; 3313 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3); 3314 addTest = false; 3315 } 3316 } 3317 3318 if (addTest) { 3319 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 3320 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) }; 3321 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3); 3322 } 3323 3324 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag); 3325 SmallVector<SDOperand, 4> Ops; 3326 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 3327 // condition is true. 3328 Ops.push_back(Op.getOperand(2)); 3329 Ops.push_back(Op.getOperand(1)); 3330 Ops.push_back(CC); 3331 Ops.push_back(Cond.getValue(1)); 3332 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 3333} 3334 3335SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { 3336 bool addTest = true; 3337 SDOperand Chain = Op.getOperand(0); 3338 SDOperand Cond = Op.getOperand(1); 3339 SDOperand Dest = Op.getOperand(2); 3340 SDOperand CC; 3341 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3342 3343 if (Cond.getOpcode() == ISD::SETCC) 3344 Cond = LowerSETCC(Cond, DAG, Chain); 3345 3346 if (Cond.getOpcode() == X86ISD::SETCC) { 3347 CC = Cond.getOperand(0); 3348 3349 // If condition flag is set by a X86ISD::CMP, then make a copy of it 3350 // (since flag operand cannot be shared). Use it as the condition setting 3351 // operand in place of the X86ISD::SETCC. 3352 // If the X86ISD::SETCC has more than one use, then perhaps it's better 3353 // to use a test instead of duplicating the X86ISD::CMP (for register 3354 // pressure reason)? 3355 SDOperand Cmp = Cond.getOperand(1); 3356 unsigned Opc = Cmp.getOpcode(); 3357 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) { 3358 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) }; 3359 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3); 3360 addTest = false; 3361 } 3362 } 3363 3364 if (addTest) { 3365 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 3366 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) }; 3367 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3); 3368 } 3369 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 3370 Cond, Op.getOperand(2), CC, Cond.getValue(1)); 3371} 3372 3373SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 3374 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3375 3376 if (Subtarget->is64Bit()) 3377 return LowerX86_64CCCCallTo(Op, DAG, CallingConv); 3378 else 3379 switch (CallingConv) { 3380 default: 3381 assert(0 && "Unsupported calling convention"); 3382 case CallingConv::Fast: 3383 // TODO: Implement fastcc 3384 // Falls through 3385 case CallingConv::C: 3386 case CallingConv::X86_StdCall: 3387 return LowerCCCCallTo(Op, DAG, CallingConv); 3388 case CallingConv::X86_FastCall: 3389 return LowerFastCCCallTo(Op, DAG, CallingConv); 3390 } 3391} 3392 3393SDOperand 3394X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 3395 MachineFunction &MF = DAG.getMachineFunction(); 3396 const Function* Fn = MF.getFunction(); 3397 if (Fn->hasExternalLinkage() && 3398 Subtarget->isTargetCygMing() && 3399 Fn->getName() == "main") 3400 MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true); 3401 3402 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3403 if (Subtarget->is64Bit()) 3404 return LowerX86_64CCCArguments(Op, DAG); 3405 else 3406 switch(CC) { 3407 default: 3408 assert(0 && "Unsupported calling convention"); 3409 case CallingConv::Fast: 3410 // TODO: implement fastcc. 3411 3412 // Falls through 3413 case CallingConv::C: 3414 return LowerCCCArguments(Op, DAG); 3415 case CallingConv::X86_StdCall: 3416 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(StdCall); 3417 return LowerCCCArguments(Op, DAG, true); 3418 case CallingConv::X86_FastCall: 3419 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall); 3420 return LowerFastCCArguments(Op, DAG); 3421 } 3422} 3423 3424SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) { 3425 SDOperand InFlag(0, 0); 3426 SDOperand Chain = Op.getOperand(0); 3427 unsigned Align = 3428 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 3429 if (Align == 0) Align = 1; 3430 3431 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); 3432 // If not DWORD aligned, call memset if size is less than the threshold. 3433 // It knows how to align to the right boundary first. 3434 if ((Align & 3) != 0 || 3435 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) { 3436 MVT::ValueType IntPtr = getPointerTy(); 3437 const Type *IntPtrTy = getTargetData()->getIntPtrType(); 3438 TargetLowering::ArgListTy Args; 3439 TargetLowering::ArgListEntry Entry; 3440 Entry.Node = Op.getOperand(1); 3441 Entry.Ty = IntPtrTy; 3442 Entry.isSigned = false; 3443 Entry.isInReg = false; 3444 Entry.isSRet = false; 3445 Args.push_back(Entry); 3446 // Extend the unsigned i8 argument to be an int value for the call. 3447 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2)); 3448 Entry.Ty = IntPtrTy; 3449 Entry.isSigned = false; 3450 Entry.isInReg = false; 3451 Entry.isSRet = false; 3452 Args.push_back(Entry); 3453 Entry.Node = Op.getOperand(3); 3454 Args.push_back(Entry); 3455 std::pair<SDOperand,SDOperand> CallResult = 3456 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 3457 DAG.getExternalSymbol("memset", IntPtr), Args, DAG); 3458 return CallResult.second; 3459 } 3460 3461 MVT::ValueType AVT; 3462 SDOperand Count; 3463 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2)); 3464 unsigned BytesLeft = 0; 3465 bool TwoRepStos = false; 3466 if (ValC) { 3467 unsigned ValReg; 3468 uint64_t Val = ValC->getValue() & 255; 3469 3470 // If the value is a constant, then we can potentially use larger sets. 3471 switch (Align & 3) { 3472 case 2: // WORD aligned 3473 AVT = MVT::i16; 3474 ValReg = X86::AX; 3475 Val = (Val << 8) | Val; 3476 break; 3477 case 0: // DWORD aligned 3478 AVT = MVT::i32; 3479 ValReg = X86::EAX; 3480 Val = (Val << 8) | Val; 3481 Val = (Val << 16) | Val; 3482 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned 3483 AVT = MVT::i64; 3484 ValReg = X86::RAX; 3485 Val = (Val << 32) | Val; 3486 } 3487 break; 3488 default: // Byte aligned 3489 AVT = MVT::i8; 3490 ValReg = X86::AL; 3491 Count = Op.getOperand(3); 3492 break; 3493 } 3494 3495 if (AVT > MVT::i8) { 3496 if (I) { 3497 unsigned UBytes = MVT::getSizeInBits(AVT) / 8; 3498 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy()); 3499 BytesLeft = I->getValue() % UBytes; 3500 } else { 3501 assert(AVT >= MVT::i32 && 3502 "Do not use rep;stos if not at least DWORD aligned"); 3503 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(), 3504 Op.getOperand(3), DAG.getConstant(2, MVT::i8)); 3505 TwoRepStos = true; 3506 } 3507 } 3508 3509 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), 3510 InFlag); 3511 InFlag = Chain.getValue(1); 3512 } else { 3513 AVT = MVT::i8; 3514 Count = Op.getOperand(3); 3515 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag); 3516 InFlag = Chain.getValue(1); 3517 } 3518 3519 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 3520 Count, InFlag); 3521 InFlag = Chain.getValue(1); 3522 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 3523 Op.getOperand(1), InFlag); 3524 InFlag = Chain.getValue(1); 3525 3526 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 3527 SmallVector<SDOperand, 8> Ops; 3528 Ops.push_back(Chain); 3529 Ops.push_back(DAG.getValueType(AVT)); 3530 Ops.push_back(InFlag); 3531 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 3532 3533 if (TwoRepStos) { 3534 InFlag = Chain.getValue(1); 3535 Count = Op.getOperand(3); 3536 MVT::ValueType CVT = Count.getValueType(); 3537 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, 3538 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 3539 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 3540 Left, InFlag); 3541 InFlag = Chain.getValue(1); 3542 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 3543 Ops.clear(); 3544 Ops.push_back(Chain); 3545 Ops.push_back(DAG.getValueType(MVT::i8)); 3546 Ops.push_back(InFlag); 3547 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 3548 } else if (BytesLeft) { 3549 // Issue stores for the last 1 - 7 bytes. 3550 SDOperand Value; 3551 unsigned Val = ValC->getValue() & 255; 3552 unsigned Offset = I->getValue() - BytesLeft; 3553 SDOperand DstAddr = Op.getOperand(1); 3554 MVT::ValueType AddrVT = DstAddr.getValueType(); 3555 if (BytesLeft >= 4) { 3556 Val = (Val << 8) | Val; 3557 Val = (Val << 16) | Val; 3558 Value = DAG.getConstant(Val, MVT::i32); 3559 Chain = DAG.getStore(Chain, Value, 3560 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 3561 DAG.getConstant(Offset, AddrVT)), 3562 NULL, 0); 3563 BytesLeft -= 4; 3564 Offset += 4; 3565 } 3566 if (BytesLeft >= 2) { 3567 Value = DAG.getConstant((Val << 8) | Val, MVT::i16); 3568 Chain = DAG.getStore(Chain, Value, 3569 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 3570 DAG.getConstant(Offset, AddrVT)), 3571 NULL, 0); 3572 BytesLeft -= 2; 3573 Offset += 2; 3574 } 3575 if (BytesLeft == 1) { 3576 Value = DAG.getConstant(Val, MVT::i8); 3577 Chain = DAG.getStore(Chain, Value, 3578 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 3579 DAG.getConstant(Offset, AddrVT)), 3580 NULL, 0); 3581 } 3582 } 3583 3584 return Chain; 3585} 3586 3587SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 3588 SDOperand Chain = Op.getOperand(0); 3589 unsigned Align = 3590 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 3591 if (Align == 0) Align = 1; 3592 3593 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); 3594 // If not DWORD aligned, call memcpy if size is less than the threshold. 3595 // It knows how to align to the right boundary first. 3596 if ((Align & 3) != 0 || 3597 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) { 3598 MVT::ValueType IntPtr = getPointerTy(); 3599 TargetLowering::ArgListTy Args; 3600 TargetLowering::ArgListEntry Entry; 3601 Entry.Ty = getTargetData()->getIntPtrType(); 3602 Entry.isSigned = false; 3603 Entry.isInReg = false; 3604 Entry.isSRet = false; 3605 Entry.Node = Op.getOperand(1); Args.push_back(Entry); 3606 Entry.Node = Op.getOperand(2); Args.push_back(Entry); 3607 Entry.Node = Op.getOperand(3); Args.push_back(Entry); 3608 std::pair<SDOperand,SDOperand> CallResult = 3609 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 3610 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 3611 return CallResult.second; 3612 } 3613 3614 MVT::ValueType AVT; 3615 SDOperand Count; 3616 unsigned BytesLeft = 0; 3617 bool TwoRepMovs = false; 3618 switch (Align & 3) { 3619 case 2: // WORD aligned 3620 AVT = MVT::i16; 3621 break; 3622 case 0: // DWORD aligned 3623 AVT = MVT::i32; 3624 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned 3625 AVT = MVT::i64; 3626 break; 3627 default: // Byte aligned 3628 AVT = MVT::i8; 3629 Count = Op.getOperand(3); 3630 break; 3631 } 3632 3633 if (AVT > MVT::i8) { 3634 if (I) { 3635 unsigned UBytes = MVT::getSizeInBits(AVT) / 8; 3636 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy()); 3637 BytesLeft = I->getValue() % UBytes; 3638 } else { 3639 assert(AVT >= MVT::i32 && 3640 "Do not use rep;movs if not at least DWORD aligned"); 3641 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(), 3642 Op.getOperand(3), DAG.getConstant(2, MVT::i8)); 3643 TwoRepMovs = true; 3644 } 3645 } 3646 3647 SDOperand InFlag(0, 0); 3648 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 3649 Count, InFlag); 3650 InFlag = Chain.getValue(1); 3651 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 3652 Op.getOperand(1), InFlag); 3653 InFlag = Chain.getValue(1); 3654 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, 3655 Op.getOperand(2), InFlag); 3656 InFlag = Chain.getValue(1); 3657 3658 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 3659 SmallVector<SDOperand, 8> Ops; 3660 Ops.push_back(Chain); 3661 Ops.push_back(DAG.getValueType(AVT)); 3662 Ops.push_back(InFlag); 3663 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 3664 3665 if (TwoRepMovs) { 3666 InFlag = Chain.getValue(1); 3667 Count = Op.getOperand(3); 3668 MVT::ValueType CVT = Count.getValueType(); 3669 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, 3670 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 3671 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 3672 Left, InFlag); 3673 InFlag = Chain.getValue(1); 3674 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 3675 Ops.clear(); 3676 Ops.push_back(Chain); 3677 Ops.push_back(DAG.getValueType(MVT::i8)); 3678 Ops.push_back(InFlag); 3679 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 3680 } else if (BytesLeft) { 3681 // Issue loads and stores for the last 1 - 7 bytes. 3682 unsigned Offset = I->getValue() - BytesLeft; 3683 SDOperand DstAddr = Op.getOperand(1); 3684 MVT::ValueType DstVT = DstAddr.getValueType(); 3685 SDOperand SrcAddr = Op.getOperand(2); 3686 MVT::ValueType SrcVT = SrcAddr.getValueType(); 3687 SDOperand Value; 3688 if (BytesLeft >= 4) { 3689 Value = DAG.getLoad(MVT::i32, Chain, 3690 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 3691 DAG.getConstant(Offset, SrcVT)), 3692 NULL, 0); 3693 Chain = Value.getValue(1); 3694 Chain = DAG.getStore(Chain, Value, 3695 DAG.getNode(ISD::ADD, DstVT, DstAddr, 3696 DAG.getConstant(Offset, DstVT)), 3697 NULL, 0); 3698 BytesLeft -= 4; 3699 Offset += 4; 3700 } 3701 if (BytesLeft >= 2) { 3702 Value = DAG.getLoad(MVT::i16, Chain, 3703 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 3704 DAG.getConstant(Offset, SrcVT)), 3705 NULL, 0); 3706 Chain = Value.getValue(1); 3707 Chain = DAG.getStore(Chain, Value, 3708 DAG.getNode(ISD::ADD, DstVT, DstAddr, 3709 DAG.getConstant(Offset, DstVT)), 3710 NULL, 0); 3711 BytesLeft -= 2; 3712 Offset += 2; 3713 } 3714 3715 if (BytesLeft == 1) { 3716 Value = DAG.getLoad(MVT::i8, Chain, 3717 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 3718 DAG.getConstant(Offset, SrcVT)), 3719 NULL, 0); 3720 Chain = Value.getValue(1); 3721 Chain = DAG.getStore(Chain, Value, 3722 DAG.getNode(ISD::ADD, DstVT, DstAddr, 3723 DAG.getConstant(Offset, DstVT)), 3724 NULL, 0); 3725 } 3726 } 3727 3728 return Chain; 3729} 3730 3731SDOperand 3732X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) { 3733 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 3734 SDOperand TheOp = Op.getOperand(0); 3735 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1); 3736 if (Subtarget->is64Bit()) { 3737 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); 3738 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX, 3739 MVT::i64, Copy1.getValue(2)); 3740 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2, 3741 DAG.getConstant(32, MVT::i8)); 3742 SDOperand Ops[] = { 3743 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1) 3744 }; 3745 3746 Tys = DAG.getVTList(MVT::i64, MVT::Other); 3747 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 3748 } 3749 3750 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); 3751 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX, 3752 MVT::i32, Copy1.getValue(2)); 3753 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) }; 3754 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 3755 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3); 3756} 3757 3758SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { 3759 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 3760 3761 if (!Subtarget->is64Bit()) { 3762 // vastart just stores the address of the VarArgsFrameIndex slot into the 3763 // memory location argument. 3764 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 3765 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(), 3766 SV->getOffset()); 3767 } 3768 3769 // __va_list_tag: 3770 // gp_offset (0 - 6 * 8) 3771 // fp_offset (48 - 48 + 8 * 16) 3772 // overflow_arg_area (point to parameters coming in memory). 3773 // reg_save_area 3774 SmallVector<SDOperand, 8> MemOps; 3775 SDOperand FIN = Op.getOperand(1); 3776 // Store gp_offset 3777 SDOperand Store = DAG.getStore(Op.getOperand(0), 3778 DAG.getConstant(VarArgsGPOffset, MVT::i32), 3779 FIN, SV->getValue(), SV->getOffset()); 3780 MemOps.push_back(Store); 3781 3782 // Store fp_offset 3783 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 3784 DAG.getConstant(4, getPointerTy())); 3785 Store = DAG.getStore(Op.getOperand(0), 3786 DAG.getConstant(VarArgsFPOffset, MVT::i32), 3787 FIN, SV->getValue(), SV->getOffset()); 3788 MemOps.push_back(Store); 3789 3790 // Store ptr to overflow_arg_area 3791 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 3792 DAG.getConstant(4, getPointerTy())); 3793 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 3794 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(), 3795 SV->getOffset()); 3796 MemOps.push_back(Store); 3797 3798 // Store ptr to reg_save_area. 3799 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 3800 DAG.getConstant(8, getPointerTy())); 3801 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 3802 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(), 3803 SV->getOffset()); 3804 MemOps.push_back(Store); 3805 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); 3806} 3807 3808SDOperand 3809X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 3810 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 3811 switch (IntNo) { 3812 default: return SDOperand(); // Don't custom lower most intrinsics. 3813 // Comparison intrinsics. 3814 case Intrinsic::x86_sse_comieq_ss: 3815 case Intrinsic::x86_sse_comilt_ss: 3816 case Intrinsic::x86_sse_comile_ss: 3817 case Intrinsic::x86_sse_comigt_ss: 3818 case Intrinsic::x86_sse_comige_ss: 3819 case Intrinsic::x86_sse_comineq_ss: 3820 case Intrinsic::x86_sse_ucomieq_ss: 3821 case Intrinsic::x86_sse_ucomilt_ss: 3822 case Intrinsic::x86_sse_ucomile_ss: 3823 case Intrinsic::x86_sse_ucomigt_ss: 3824 case Intrinsic::x86_sse_ucomige_ss: 3825 case Intrinsic::x86_sse_ucomineq_ss: 3826 case Intrinsic::x86_sse2_comieq_sd: 3827 case Intrinsic::x86_sse2_comilt_sd: 3828 case Intrinsic::x86_sse2_comile_sd: 3829 case Intrinsic::x86_sse2_comigt_sd: 3830 case Intrinsic::x86_sse2_comige_sd: 3831 case Intrinsic::x86_sse2_comineq_sd: 3832 case Intrinsic::x86_sse2_ucomieq_sd: 3833 case Intrinsic::x86_sse2_ucomilt_sd: 3834 case Intrinsic::x86_sse2_ucomile_sd: 3835 case Intrinsic::x86_sse2_ucomigt_sd: 3836 case Intrinsic::x86_sse2_ucomige_sd: 3837 case Intrinsic::x86_sse2_ucomineq_sd: { 3838 unsigned Opc = 0; 3839 ISD::CondCode CC = ISD::SETCC_INVALID; 3840 switch (IntNo) { 3841 default: break; 3842 case Intrinsic::x86_sse_comieq_ss: 3843 case Intrinsic::x86_sse2_comieq_sd: 3844 Opc = X86ISD::COMI; 3845 CC = ISD::SETEQ; 3846 break; 3847 case Intrinsic::x86_sse_comilt_ss: 3848 case Intrinsic::x86_sse2_comilt_sd: 3849 Opc = X86ISD::COMI; 3850 CC = ISD::SETLT; 3851 break; 3852 case Intrinsic::x86_sse_comile_ss: 3853 case Intrinsic::x86_sse2_comile_sd: 3854 Opc = X86ISD::COMI; 3855 CC = ISD::SETLE; 3856 break; 3857 case Intrinsic::x86_sse_comigt_ss: 3858 case Intrinsic::x86_sse2_comigt_sd: 3859 Opc = X86ISD::COMI; 3860 CC = ISD::SETGT; 3861 break; 3862 case Intrinsic::x86_sse_comige_ss: 3863 case Intrinsic::x86_sse2_comige_sd: 3864 Opc = X86ISD::COMI; 3865 CC = ISD::SETGE; 3866 break; 3867 case Intrinsic::x86_sse_comineq_ss: 3868 case Intrinsic::x86_sse2_comineq_sd: 3869 Opc = X86ISD::COMI; 3870 CC = ISD::SETNE; 3871 break; 3872 case Intrinsic::x86_sse_ucomieq_ss: 3873 case Intrinsic::x86_sse2_ucomieq_sd: 3874 Opc = X86ISD::UCOMI; 3875 CC = ISD::SETEQ; 3876 break; 3877 case Intrinsic::x86_sse_ucomilt_ss: 3878 case Intrinsic::x86_sse2_ucomilt_sd: 3879 Opc = X86ISD::UCOMI; 3880 CC = ISD::SETLT; 3881 break; 3882 case Intrinsic::x86_sse_ucomile_ss: 3883 case Intrinsic::x86_sse2_ucomile_sd: 3884 Opc = X86ISD::UCOMI; 3885 CC = ISD::SETLE; 3886 break; 3887 case Intrinsic::x86_sse_ucomigt_ss: 3888 case Intrinsic::x86_sse2_ucomigt_sd: 3889 Opc = X86ISD::UCOMI; 3890 CC = ISD::SETGT; 3891 break; 3892 case Intrinsic::x86_sse_ucomige_ss: 3893 case Intrinsic::x86_sse2_ucomige_sd: 3894 Opc = X86ISD::UCOMI; 3895 CC = ISD::SETGE; 3896 break; 3897 case Intrinsic::x86_sse_ucomineq_ss: 3898 case Intrinsic::x86_sse2_ucomineq_sd: 3899 Opc = X86ISD::UCOMI; 3900 CC = ISD::SETNE; 3901 break; 3902 } 3903 3904 unsigned X86CC; 3905 SDOperand LHS = Op.getOperand(1); 3906 SDOperand RHS = Op.getOperand(2); 3907 translateX86CC(CC, true, X86CC, LHS, RHS, DAG); 3908 3909 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 3910 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS }; 3911 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3); 3912 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag); 3913 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond }; 3914 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2); 3915 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC); 3916 } 3917 } 3918} 3919 3920SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { 3921 // Depths > 0 not supported yet! 3922 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3923 return SDOperand(); 3924 3925 // Just load the return address 3926 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 3927 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 3928} 3929 3930SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { 3931 // Depths > 0 not supported yet! 3932 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3933 return SDOperand(); 3934 3935 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 3936 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, 3937 DAG.getConstant(4, getPointerTy())); 3938} 3939 3940/// LowerOperation - Provide custom lowering hooks for some operations. 3941/// 3942SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 3943 switch (Op.getOpcode()) { 3944 default: assert(0 && "Should not custom lower this!"); 3945 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3946 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3947 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 3948 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 3949 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3950 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3951 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 3952 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 3953 case ISD::SHL_PARTS: 3954 case ISD::SRA_PARTS: 3955 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 3956 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 3957 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 3958 case ISD::FABS: return LowerFABS(Op, DAG); 3959 case ISD::FNEG: return LowerFNEG(Op, DAG); 3960 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 3961 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode()); 3962 case ISD::SELECT: return LowerSELECT(Op, DAG); 3963 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 3964 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 3965 case ISD::CALL: return LowerCALL(Op, DAG); 3966 case ISD::RET: return LowerRET(Op, DAG); 3967 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 3968 case ISD::MEMSET: return LowerMEMSET(Op, DAG); 3969 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); 3970 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG); 3971 case ISD::VASTART: return LowerVASTART(Op, DAG); 3972 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3973 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3974 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3975 } 3976 return SDOperand(); 3977} 3978 3979const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 3980 switch (Opcode) { 3981 default: return NULL; 3982 case X86ISD::SHLD: return "X86ISD::SHLD"; 3983 case X86ISD::SHRD: return "X86ISD::SHRD"; 3984 case X86ISD::FAND: return "X86ISD::FAND"; 3985 case X86ISD::FOR: return "X86ISD::FOR"; 3986 case X86ISD::FXOR: return "X86ISD::FXOR"; 3987 case X86ISD::FSRL: return "X86ISD::FSRL"; 3988 case X86ISD::FILD: return "X86ISD::FILD"; 3989 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 3990 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 3991 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 3992 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 3993 case X86ISD::FLD: return "X86ISD::FLD"; 3994 case X86ISD::FST: return "X86ISD::FST"; 3995 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT"; 3996 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT"; 3997 case X86ISD::CALL: return "X86ISD::CALL"; 3998 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 3999 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 4000 case X86ISD::CMP: return "X86ISD::CMP"; 4001 case X86ISD::COMI: return "X86ISD::COMI"; 4002 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 4003 case X86ISD::SETCC: return "X86ISD::SETCC"; 4004 case X86ISD::CMOV: return "X86ISD::CMOV"; 4005 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 4006 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 4007 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 4008 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 4009 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK"; 4010 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA"; 4011 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 4012 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 4013 case X86ISD::S2VEC: return "X86ISD::S2VEC"; 4014 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 4015 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 4016 case X86ISD::FMAX: return "X86ISD::FMAX"; 4017 case X86ISD::FMIN: return "X86ISD::FMIN"; 4018 } 4019} 4020 4021/// isLegalAddressImmediate - Return true if the integer value or 4022/// GlobalValue can be used as the offset of the target addressing mode. 4023bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const { 4024 // X86 allows a sign-extended 32-bit immediate field. 4025 return (V > -(1LL << 32) && V < (1LL << 32)-1); 4026} 4027 4028bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { 4029 // In 64-bit mode, GV is 64-bit so it won't fit in the 32-bit displacement 4030 // field unless we are in small code model. 4031 if (Subtarget->is64Bit() && 4032 getTargetMachine().getCodeModel() != CodeModel::Small) 4033 return false; 4034 4035 return (!Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)); 4036} 4037 4038/// isShuffleMaskLegal - Targets can use this to indicate that they only 4039/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4040/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4041/// are assumed to be legal. 4042bool 4043X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 4044 // Only do shuffles on 128-bit vector types for now. 4045 if (MVT::getSizeInBits(VT) == 64) return false; 4046 return (Mask.Val->getNumOperands() <= 4 || 4047 isSplatMask(Mask.Val) || 4048 isPSHUFHW_PSHUFLWMask(Mask.Val) || 4049 X86::isUNPCKLMask(Mask.Val) || 4050 X86::isUNPCKL_v_undef_Mask(Mask.Val) || 4051 X86::isUNPCKHMask(Mask.Val)); 4052} 4053 4054bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 4055 MVT::ValueType EVT, 4056 SelectionDAG &DAG) const { 4057 unsigned NumElts = BVOps.size(); 4058 // Only do shuffles on 128-bit vector types for now. 4059 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false; 4060 if (NumElts == 2) return true; 4061 if (NumElts == 4) { 4062 return (isMOVLMask(&BVOps[0], 4) || 4063 isCommutedMOVL(&BVOps[0], 4, true) || 4064 isSHUFPMask(&BVOps[0], 4) || 4065 isCommutedSHUFP(&BVOps[0], 4)); 4066 } 4067 return false; 4068} 4069 4070//===----------------------------------------------------------------------===// 4071// X86 Scheduler Hooks 4072//===----------------------------------------------------------------------===// 4073 4074MachineBasicBlock * 4075X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 4076 MachineBasicBlock *BB) { 4077 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4078 switch (MI->getOpcode()) { 4079 default: assert(false && "Unexpected instr type to insert"); 4080 case X86::CMOV_FR32: 4081 case X86::CMOV_FR64: 4082 case X86::CMOV_V4F32: 4083 case X86::CMOV_V2F64: 4084 case X86::CMOV_V2I64: { 4085 // To "insert" a SELECT_CC instruction, we actually have to insert the 4086 // diamond control-flow pattern. The incoming instruction knows the 4087 // destination vreg to set, the condition code register to branch on, the 4088 // true/false values to select between, and a branch opcode to use. 4089 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4090 ilist<MachineBasicBlock>::iterator It = BB; 4091 ++It; 4092 4093 // thisMBB: 4094 // ... 4095 // TrueVal = ... 4096 // cmpTY ccX, r1, r2 4097 // bCC copy1MBB 4098 // fallthrough --> copy0MBB 4099 MachineBasicBlock *thisMBB = BB; 4100 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 4101 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 4102 unsigned Opc = 4103 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 4104 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); 4105 MachineFunction *F = BB->getParent(); 4106 F->getBasicBlockList().insert(It, copy0MBB); 4107 F->getBasicBlockList().insert(It, sinkMBB); 4108 // Update machine-CFG edges by first adding all successors of the current 4109 // block to the new block which will contain the Phi node for the select. 4110 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 4111 e = BB->succ_end(); i != e; ++i) 4112 sinkMBB->addSuccessor(*i); 4113 // Next, remove all successors of the current block, and add the true 4114 // and fallthrough blocks as its successors. 4115 while(!BB->succ_empty()) 4116 BB->removeSuccessor(BB->succ_begin()); 4117 BB->addSuccessor(copy0MBB); 4118 BB->addSuccessor(sinkMBB); 4119 4120 // copy0MBB: 4121 // %FalseValue = ... 4122 // # fallthrough to sinkMBB 4123 BB = copy0MBB; 4124 4125 // Update machine-CFG edges 4126 BB->addSuccessor(sinkMBB); 4127 4128 // sinkMBB: 4129 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4130 // ... 4131 BB = sinkMBB; 4132 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) 4133 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 4134 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4135 4136 delete MI; // The pseudo instruction is gone now. 4137 return BB; 4138 } 4139 4140 case X86::FP_TO_INT16_IN_MEM: 4141 case X86::FP_TO_INT32_IN_MEM: 4142 case X86::FP_TO_INT64_IN_MEM: { 4143 // Change the floating point control register to use "round towards zero" 4144 // mode when truncating to an integer value. 4145 MachineFunction *F = BB->getParent(); 4146 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 4147 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); 4148 4149 // Load the old value of the high byte of the control word... 4150 unsigned OldCW = 4151 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass); 4152 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); 4153 4154 // Set the high part to be round to zero... 4155 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) 4156 .addImm(0xC7F); 4157 4158 // Reload the modified control word now... 4159 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 4160 4161 // Restore the memory image of control word to original value 4162 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) 4163 .addReg(OldCW); 4164 4165 // Get the X86 opcode to use. 4166 unsigned Opc; 4167 switch (MI->getOpcode()) { 4168 default: assert(0 && "illegal opcode!"); 4169 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break; 4170 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break; 4171 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break; 4172 } 4173 4174 X86AddressMode AM; 4175 MachineOperand &Op = MI->getOperand(0); 4176 if (Op.isRegister()) { 4177 AM.BaseType = X86AddressMode::RegBase; 4178 AM.Base.Reg = Op.getReg(); 4179 } else { 4180 AM.BaseType = X86AddressMode::FrameIndexBase; 4181 AM.Base.FrameIndex = Op.getFrameIndex(); 4182 } 4183 Op = MI->getOperand(1); 4184 if (Op.isImmediate()) 4185 AM.Scale = Op.getImm(); 4186 Op = MI->getOperand(2); 4187 if (Op.isImmediate()) 4188 AM.IndexReg = Op.getImm(); 4189 Op = MI->getOperand(3); 4190 if (Op.isGlobalAddress()) { 4191 AM.GV = Op.getGlobal(); 4192 } else { 4193 AM.Disp = Op.getImm(); 4194 } 4195 addFullAddress(BuildMI(BB, TII->get(Opc)), AM) 4196 .addReg(MI->getOperand(4).getReg()); 4197 4198 // Reload the original control word now. 4199 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 4200 4201 delete MI; // The pseudo instruction is gone now. 4202 return BB; 4203 } 4204 } 4205} 4206 4207//===----------------------------------------------------------------------===// 4208// X86 Optimization Hooks 4209//===----------------------------------------------------------------------===// 4210 4211void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 4212 uint64_t Mask, 4213 uint64_t &KnownZero, 4214 uint64_t &KnownOne, 4215 unsigned Depth) const { 4216 unsigned Opc = Op.getOpcode(); 4217 assert((Opc >= ISD::BUILTIN_OP_END || 4218 Opc == ISD::INTRINSIC_WO_CHAIN || 4219 Opc == ISD::INTRINSIC_W_CHAIN || 4220 Opc == ISD::INTRINSIC_VOID) && 4221 "Should use MaskedValueIsZero if you don't know whether Op" 4222 " is a target node!"); 4223 4224 KnownZero = KnownOne = 0; // Don't know anything. 4225 switch (Opc) { 4226 default: break; 4227 case X86ISD::SETCC: 4228 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 4229 break; 4230 } 4231} 4232 4233/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4234/// element of the result of the vector shuffle. 4235static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) { 4236 MVT::ValueType VT = N->getValueType(0); 4237 SDOperand PermMask = N->getOperand(2); 4238 unsigned NumElems = PermMask.getNumOperands(); 4239 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1); 4240 i %= NumElems; 4241 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4242 return (i == 0) 4243 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT)); 4244 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) { 4245 SDOperand Idx = PermMask.getOperand(i); 4246 if (Idx.getOpcode() == ISD::UNDEF) 4247 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT)); 4248 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG); 4249 } 4250 return SDOperand(); 4251} 4252 4253/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 4254/// node is a GlobalAddress + an offset. 4255static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) { 4256 unsigned Opc = N->getOpcode(); 4257 if (Opc == X86ISD::Wrapper) { 4258 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) { 4259 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 4260 return true; 4261 } 4262 } else if (Opc == ISD::ADD) { 4263 SDOperand N1 = N->getOperand(0); 4264 SDOperand N2 = N->getOperand(1); 4265 if (isGAPlusOffset(N1.Val, GA, Offset)) { 4266 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 4267 if (V) { 4268 Offset += V->getSignExtended(); 4269 return true; 4270 } 4271 } else if (isGAPlusOffset(N2.Val, GA, Offset)) { 4272 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 4273 if (V) { 4274 Offset += V->getSignExtended(); 4275 return true; 4276 } 4277 } 4278 } 4279 return false; 4280} 4281 4282/// isConsecutiveLoad - Returns true if N is loading from an address of Base 4283/// + Dist * Size. 4284static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size, 4285 MachineFrameInfo *MFI) { 4286 if (N->getOperand(0).Val != Base->getOperand(0).Val) 4287 return false; 4288 4289 SDOperand Loc = N->getOperand(1); 4290 SDOperand BaseLoc = Base->getOperand(1); 4291 if (Loc.getOpcode() == ISD::FrameIndex) { 4292 if (BaseLoc.getOpcode() != ISD::FrameIndex) 4293 return false; 4294 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex(); 4295 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 4296 int FS = MFI->getObjectSize(FI); 4297 int BFS = MFI->getObjectSize(BFI); 4298 if (FS != BFS || FS != Size) return false; 4299 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size); 4300 } else { 4301 GlobalValue *GV1 = NULL; 4302 GlobalValue *GV2 = NULL; 4303 int64_t Offset1 = 0; 4304 int64_t Offset2 = 0; 4305 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1); 4306 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2); 4307 if (isGA1 && isGA2 && GV1 == GV2) 4308 return Offset1 == (Offset2 + Dist*Size); 4309 } 4310 4311 return false; 4312} 4313 4314static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI, 4315 const X86Subtarget *Subtarget) { 4316 GlobalValue *GV; 4317 int64_t Offset; 4318 if (isGAPlusOffset(Base, GV, Offset)) 4319 return (GV->getAlignment() >= 16 && (Offset % 16) == 0); 4320 else { 4321 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!"); 4322 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex(); 4323 if (BFI < 0) 4324 // Fixed objects do not specify alignment, however the offsets are known. 4325 return ((Subtarget->getStackAlignment() % 16) == 0 && 4326 (MFI->getObjectOffset(BFI) % 16) == 0); 4327 else 4328 return MFI->getObjectAlignment(BFI) >= 16; 4329 } 4330 return false; 4331} 4332 4333 4334/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 4335/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 4336/// if the load addresses are consecutive, non-overlapping, and in the right 4337/// order. 4338static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 4339 const X86Subtarget *Subtarget) { 4340 MachineFunction &MF = DAG.getMachineFunction(); 4341 MachineFrameInfo *MFI = MF.getFrameInfo(); 4342 MVT::ValueType VT = N->getValueType(0); 4343 MVT::ValueType EVT = MVT::getVectorBaseType(VT); 4344 SDOperand PermMask = N->getOperand(2); 4345 int NumElems = (int)PermMask.getNumOperands(); 4346 SDNode *Base = NULL; 4347 for (int i = 0; i < NumElems; ++i) { 4348 SDOperand Idx = PermMask.getOperand(i); 4349 if (Idx.getOpcode() == ISD::UNDEF) { 4350 if (!Base) return SDOperand(); 4351 } else { 4352 SDOperand Arg = 4353 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG); 4354 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val)) 4355 return SDOperand(); 4356 if (!Base) 4357 Base = Arg.Val; 4358 else if (!isConsecutiveLoad(Arg.Val, Base, 4359 i, MVT::getSizeInBits(EVT)/8,MFI)) 4360 return SDOperand(); 4361 } 4362 } 4363 4364 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget); 4365 if (isAlign16) { 4366 LoadSDNode *LD = cast<LoadSDNode>(Base); 4367 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 4368 LD->getSrcValueOffset()); 4369 } else { 4370 // Just use movups, it's shorter. 4371 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other); 4372 SmallVector<SDOperand, 3> Ops; 4373 Ops.push_back(Base->getOperand(0)); 4374 Ops.push_back(Base->getOperand(1)); 4375 Ops.push_back(Base->getOperand(2)); 4376 return DAG.getNode(ISD::BIT_CONVERT, VT, 4377 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size())); 4378 } 4379} 4380 4381/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 4382static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 4383 const X86Subtarget *Subtarget) { 4384 SDOperand Cond = N->getOperand(0); 4385 4386 // If we have SSE[12] support, try to form min/max nodes. 4387 if (Subtarget->hasSSE2() && 4388 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { 4389 if (Cond.getOpcode() == ISD::SETCC) { 4390 // Get the LHS/RHS of the select. 4391 SDOperand LHS = N->getOperand(1); 4392 SDOperand RHS = N->getOperand(2); 4393 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 4394 4395 unsigned Opcode = 0; 4396 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 4397 switch (CC) { 4398 default: break; 4399 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 4400 case ISD::SETULE: 4401 case ISD::SETLE: 4402 if (!UnsafeFPMath) break; 4403 // FALL THROUGH. 4404 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 4405 case ISD::SETLT: 4406 Opcode = X86ISD::FMIN; 4407 break; 4408 4409 case ISD::SETOGT: // (X > Y) ? X : Y -> max 4410 case ISD::SETUGT: 4411 case ISD::SETGT: 4412 if (!UnsafeFPMath) break; 4413 // FALL THROUGH. 4414 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 4415 case ISD::SETGE: 4416 Opcode = X86ISD::FMAX; 4417 break; 4418 } 4419 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 4420 switch (CC) { 4421 default: break; 4422 case ISD::SETOGT: // (X > Y) ? Y : X -> min 4423 case ISD::SETUGT: 4424 case ISD::SETGT: 4425 if (!UnsafeFPMath) break; 4426 // FALL THROUGH. 4427 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 4428 case ISD::SETGE: 4429 Opcode = X86ISD::FMIN; 4430 break; 4431 4432 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 4433 case ISD::SETULE: 4434 case ISD::SETLE: 4435 if (!UnsafeFPMath) break; 4436 // FALL THROUGH. 4437 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 4438 case ISD::SETLT: 4439 Opcode = X86ISD::FMAX; 4440 break; 4441 } 4442 } 4443 4444 if (Opcode) 4445 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS); 4446 } 4447 4448 } 4449 4450 return SDOperand(); 4451} 4452 4453 4454SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N, 4455 DAGCombinerInfo &DCI) const { 4456 SelectionDAG &DAG = DCI.DAG; 4457 switch (N->getOpcode()) { 4458 default: break; 4459 case ISD::VECTOR_SHUFFLE: 4460 return PerformShuffleCombine(N, DAG, Subtarget); 4461 case ISD::SELECT: 4462 return PerformSELECTCombine(N, DAG, Subtarget); 4463 } 4464 4465 return SDOperand(); 4466} 4467 4468//===----------------------------------------------------------------------===// 4469// X86 Inline Assembly Support 4470//===----------------------------------------------------------------------===// 4471 4472/// getConstraintType - Given a constraint letter, return the type of 4473/// constraint it is for this target. 4474X86TargetLowering::ConstraintType 4475X86TargetLowering::getConstraintType(char ConstraintLetter) const { 4476 switch (ConstraintLetter) { 4477 case 'A': 4478 case 'r': 4479 case 'R': 4480 case 'l': 4481 case 'q': 4482 case 'Q': 4483 case 'x': 4484 case 'Y': 4485 return C_RegisterClass; 4486 default: return TargetLowering::getConstraintType(ConstraintLetter); 4487 } 4488} 4489 4490/// isOperandValidForConstraint - Return the specified operand (possibly 4491/// modified) if the specified SDOperand is valid for the specified target 4492/// constraint letter, otherwise return null. 4493SDOperand X86TargetLowering:: 4494isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) { 4495 switch (Constraint) { 4496 default: break; 4497 case 'i': 4498 // Literal immediates are always ok. 4499 if (isa<ConstantSDNode>(Op)) return Op; 4500 4501 // If we are in non-pic codegen mode, we allow the address of a global to 4502 // be used with 'i'. 4503 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) { 4504 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 4505 return SDOperand(0, 0); 4506 4507 if (GA->getOpcode() != ISD::TargetGlobalAddress) 4508 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 4509 GA->getOffset()); 4510 return Op; 4511 } 4512 4513 // Otherwise, not valid for this mode. 4514 return SDOperand(0, 0); 4515 } 4516 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG); 4517} 4518 4519 4520std::vector<unsigned> X86TargetLowering:: 4521getRegClassForInlineAsmConstraint(const std::string &Constraint, 4522 MVT::ValueType VT) const { 4523 if (Constraint.size() == 1) { 4524 // FIXME: not handling fp-stack yet! 4525 // FIXME: not handling MMX registers yet ('y' constraint). 4526 switch (Constraint[0]) { // GCC X86 Constraint Letters 4527 default: break; // Unknown constraint letter 4528 case 'A': // EAX/EDX 4529 if (VT == MVT::i32 || VT == MVT::i64) 4530 return make_vector<unsigned>(X86::EAX, X86::EDX, 0); 4531 break; 4532 case 'r': // GENERAL_REGS 4533 case 'R': // LEGACY_REGS 4534 if (VT == MVT::i64 && Subtarget->is64Bit()) 4535 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 4536 X86::RSI, X86::RDI, X86::RBP, X86::RSP, 4537 X86::R8, X86::R9, X86::R10, X86::R11, 4538 X86::R12, X86::R13, X86::R14, X86::R15, 0); 4539 if (VT == MVT::i32) 4540 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 4541 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); 4542 else if (VT == MVT::i16) 4543 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 4544 X86::SI, X86::DI, X86::BP, X86::SP, 0); 4545 else if (VT == MVT::i8) 4546 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 4547 break; 4548 case 'l': // INDEX_REGS 4549 if (VT == MVT::i32) 4550 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 4551 X86::ESI, X86::EDI, X86::EBP, 0); 4552 else if (VT == MVT::i16) 4553 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 4554 X86::SI, X86::DI, X86::BP, 0); 4555 else if (VT == MVT::i8) 4556 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); 4557 break; 4558 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 4559 case 'Q': // Q_REGS 4560 if (VT == MVT::i32) 4561 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 4562 else if (VT == MVT::i16) 4563 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 4564 else if (VT == MVT::i8) 4565 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); 4566 break; 4567 case 'x': // SSE_REGS if SSE1 allowed 4568 if (Subtarget->hasSSE1()) 4569 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 4570 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 4571 0); 4572 return std::vector<unsigned>(); 4573 case 'Y': // SSE_REGS if SSE2 allowed 4574 if (Subtarget->hasSSE2()) 4575 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 4576 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 4577 0); 4578 return std::vector<unsigned>(); 4579 } 4580 } 4581 4582 return std::vector<unsigned>(); 4583} 4584 4585std::pair<unsigned, const TargetRegisterClass*> 4586X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 4587 MVT::ValueType VT) const { 4588 // Use the default implementation in TargetLowering to convert the register 4589 // constraint into a member of a register class. 4590 std::pair<unsigned, const TargetRegisterClass*> Res; 4591 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 4592 4593 // Not found as a standard register? 4594 if (Res.second == 0) { 4595 // GCC calls "st(0)" just plain "st". 4596 if (StringsEqualNoCase("{st}", Constraint)) { 4597 Res.first = X86::ST0; 4598 Res.second = X86::RSTRegisterClass; 4599 } 4600 4601 return Res; 4602 } 4603 4604 // Otherwise, check to see if this is a register class of the wrong value 4605 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 4606 // turn into {ax},{dx}. 4607 if (Res.second->hasType(VT)) 4608 return Res; // Correct type already, nothing to do. 4609 4610 // All of the single-register GCC register classes map their values onto 4611 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 4612 // really want an 8-bit or 32-bit register, map to the appropriate register 4613 // class and return the appropriate register. 4614 if (Res.second != X86::GR16RegisterClass) 4615 return Res; 4616 4617 if (VT == MVT::i8) { 4618 unsigned DestReg = 0; 4619 switch (Res.first) { 4620 default: break; 4621 case X86::AX: DestReg = X86::AL; break; 4622 case X86::DX: DestReg = X86::DL; break; 4623 case X86::CX: DestReg = X86::CL; break; 4624 case X86::BX: DestReg = X86::BL; break; 4625 } 4626 if (DestReg) { 4627 Res.first = DestReg; 4628 Res.second = Res.second = X86::GR8RegisterClass; 4629 } 4630 } else if (VT == MVT::i32) { 4631 unsigned DestReg = 0; 4632 switch (Res.first) { 4633 default: break; 4634 case X86::AX: DestReg = X86::EAX; break; 4635 case X86::DX: DestReg = X86::EDX; break; 4636 case X86::CX: DestReg = X86::ECX; break; 4637 case X86::BX: DestReg = X86::EBX; break; 4638 case X86::SI: DestReg = X86::ESI; break; 4639 case X86::DI: DestReg = X86::EDI; break; 4640 case X86::BP: DestReg = X86::EBP; break; 4641 case X86::SP: DestReg = X86::ESP; break; 4642 } 4643 if (DestReg) { 4644 Res.first = DestReg; 4645 Res.second = Res.second = X86::GR32RegisterClass; 4646 } 4647 } else if (VT == MVT::i64) { 4648 unsigned DestReg = 0; 4649 switch (Res.first) { 4650 default: break; 4651 case X86::AX: DestReg = X86::RAX; break; 4652 case X86::DX: DestReg = X86::RDX; break; 4653 case X86::CX: DestReg = X86::RCX; break; 4654 case X86::BX: DestReg = X86::RBX; break; 4655 case X86::SI: DestReg = X86::RSI; break; 4656 case X86::DI: DestReg = X86::RDI; break; 4657 case X86::BP: DestReg = X86::RBP; break; 4658 case X86::SP: DestReg = X86::RSP; break; 4659 } 4660 if (DestReg) { 4661 Res.first = DestReg; 4662 Res.second = Res.second = X86::GR64RegisterClass; 4663 } 4664 } 4665 4666 return Res; 4667} 4668