X86InstrInfo.h revision 19a2011194399849ecdf1499c7615e8276a8e68c
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22 23namespace llvm { 24 class X86RegisterInfo; 25 class X86TargetMachine; 26 27namespace X86 { 28 // X86 specific condition code. These correspond to X86_*_COND in 29 // X86InstrInfo.td. They must be kept in synch. 30 enum CondCode { 31 COND_A = 0, 32 COND_AE = 1, 33 COND_B = 2, 34 COND_BE = 3, 35 COND_E = 4, 36 COND_G = 5, 37 COND_GE = 6, 38 COND_L = 7, 39 COND_LE = 8, 40 COND_NE = 9, 41 COND_NO = 10, 42 COND_NP = 11, 43 COND_NS = 12, 44 COND_O = 13, 45 COND_P = 14, 46 COND_S = 15, 47 48 // Artificial condition codes. These are used by AnalyzeBranch 49 // to indicate a block terminated with two conditional branches to 50 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 51 // which can't be represented on x86 with a single condition. These 52 // are never used in MachineInstrs. 53 COND_NE_OR_P, 54 COND_NP_OR_E, 55 56 COND_INVALID 57 }; 58 59 // Turn condition code into conditional branch opcode. 60 unsigned GetCondBranchFromCond(CondCode CC); 61 62 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63 /// e.g. turning COND_E to COND_NE. 64 CondCode GetOppositeBranchCondition(X86::CondCode CC); 65 66} 67 68/// X86II - This namespace holds all of the target specific flags that 69/// instruction info tracks. 70/// 71namespace X86II { 72 /// Target Operand Flag enum. 73 enum TOF { 74 //===------------------------------------------------------------------===// 75 // X86 Specific MachineOperand flags. 76 77 MO_NO_FLAG = 0, 78 79 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 80 /// relocation of: 81 /// SYMBOL_LABEL + [. - PICBASELABEL] 82 MO_GOT_ABSOLUTE_ADDRESS = 1, 83 84 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 85 /// immediate should get the value of the symbol minus the PIC base label: 86 /// SYMBOL_LABEL - PICBASELABEL 87 MO_PIC_BASE_OFFSET = 2, 88 89 /// MO_GOT - On a symbol operand this indicates that the immediate is the 90 /// offset to the GOT entry for the symbol name from the base of the GOT. 91 /// 92 /// See the X86-64 ELF ABI supplement for more details. 93 /// SYMBOL_LABEL @GOT 94 MO_GOT = 3, 95 96 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 97 /// the offset to the location of the symbol name from the base of the GOT. 98 /// 99 /// See the X86-64 ELF ABI supplement for more details. 100 /// SYMBOL_LABEL @GOTOFF 101 MO_GOTOFF = 4, 102 103 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 104 /// offset to the GOT entry for the symbol name from the current code 105 /// location. 106 /// 107 /// See the X86-64 ELF ABI supplement for more details. 108 /// SYMBOL_LABEL @GOTPCREL 109 MO_GOTPCREL = 5, 110 111 /// MO_PLT - On a symbol operand this indicates that the immediate is 112 /// offset to the PLT entry of symbol name from the current code location. 113 /// 114 /// See the X86-64 ELF ABI supplement for more details. 115 /// SYMBOL_LABEL @PLT 116 MO_PLT = 6, 117 118 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 119 /// some TLS offset. 120 /// 121 /// See 'ELF Handling for Thread-Local Storage' for more details. 122 /// SYMBOL_LABEL @TLSGD 123 MO_TLSGD = 7, 124 125 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 126 /// some TLS offset. 127 /// 128 /// See 'ELF Handling for Thread-Local Storage' for more details. 129 /// SYMBOL_LABEL @GOTTPOFF 130 MO_GOTTPOFF = 8, 131 132 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 133 /// some TLS offset. 134 /// 135 /// See 'ELF Handling for Thread-Local Storage' for more details. 136 /// SYMBOL_LABEL @INDNTPOFF 137 MO_INDNTPOFF = 9, 138 139 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 140 /// some TLS offset. 141 /// 142 /// See 'ELF Handling for Thread-Local Storage' for more details. 143 /// SYMBOL_LABEL @TPOFF 144 MO_TPOFF = 10, 145 146 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 147 /// some TLS offset. 148 /// 149 /// See 'ELF Handling for Thread-Local Storage' for more details. 150 /// SYMBOL_LABEL @NTPOFF 151 MO_NTPOFF = 11, 152 153 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 154 /// reference is actually to the "__imp_FOO" symbol. This is used for 155 /// dllimport linkage on windows. 156 MO_DLLIMPORT = 12, 157 158 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 159 /// reference is actually to the "FOO$stub" symbol. This is used for calls 160 /// and jumps to external functions on Tiger and before. 161 MO_DARWIN_STUB = 13, 162 163 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 164 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 165 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 166 MO_DARWIN_NONLAZY = 14, 167 168 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 169 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 170 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 171 MO_DARWIN_NONLAZY_PIC_BASE = 15, 172 173 /// MO_DARWIN_HIDDEN_NONLAZY - On a symbol operand "FOO", this indicates 174 /// that the reference is actually to the "FOO$non_lazy_ptr" symbol, which 175 /// is a non-PIC-base-relative reference to a hidden dyld lazy pointer stub. 176 MO_DARWIN_HIDDEN_NONLAZY = 16, 177 178 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 179 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 180 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 181 /// stub. 182 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE = 17 183 }; 184} 185 186/// isGlobalStubReference - Return true if the specified TargetFlag operand is 187/// a reference to a stub for a global, not the global itself. 188inline static bool isGlobalStubReference(unsigned char TargetFlag) { 189 switch (TargetFlag) { 190 case X86II::MO_DLLIMPORT: // dllimport stub. 191 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 192 case X86II::MO_GOT: // normal GOT reference. 193 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 194 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 195 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 196 case X86II::MO_DARWIN_HIDDEN_NONLAZY: // Hidden $non_lazy_ptr ref. 197 return true; 198 default: 199 return false; 200 } 201} 202 203/// isGlobalRelativeToPICBase - Return true if the specified global value 204/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 205/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 206inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 207 switch (TargetFlag) { 208 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 209 case X86II::MO_GOT: // isPICStyleGOT: other global. 210 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 211 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 212 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 213 return true; 214 default: 215 return false; 216 } 217} 218 219/// X86II - This namespace holds all of the target specific flags that 220/// instruction info tracks. 221/// 222namespace X86II { 223 enum { 224 //===------------------------------------------------------------------===// 225 // Instruction encodings. These are the standard/most common forms for X86 226 // instructions. 227 // 228 229 // PseudoFrm - This represents an instruction that is a pseudo instruction 230 // or one that has not been implemented yet. It is illegal to code generate 231 // it, but tolerated for intermediate implementation stages. 232 Pseudo = 0, 233 234 /// Raw - This form is for instructions that don't have any operands, so 235 /// they are just a fixed opcode value, like 'leave'. 236 RawFrm = 1, 237 238 /// AddRegFrm - This form is used for instructions like 'push r32' that have 239 /// their one register operand added to their opcode. 240 AddRegFrm = 2, 241 242 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 243 /// to specify a destination, which in this case is a register. 244 /// 245 MRMDestReg = 3, 246 247 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 248 /// to specify a destination, which in this case is memory. 249 /// 250 MRMDestMem = 4, 251 252 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 253 /// to specify a source, which in this case is a register. 254 /// 255 MRMSrcReg = 5, 256 257 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 258 /// to specify a source, which in this case is memory. 259 /// 260 MRMSrcMem = 6, 261 262 /// MRM[0-7][rm] - These forms are used to represent instructions that use 263 /// a Mod/RM byte, and use the middle field to hold extended opcode 264 /// information. In the intel manual these are represented as /0, /1, ... 265 /// 266 267 // First, instructions that operate on a register r/m operand... 268 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 269 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 270 271 // Next, instructions that operate on a memory r/m operand... 272 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 273 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 274 275 // MRMInitReg - This form is used for instructions whose source and 276 // destinations are the same register. 277 MRMInitReg = 32, 278 279 FormMask = 63, 280 281 //===------------------------------------------------------------------===// 282 // Actual flags... 283 284 // OpSize - Set if this instruction requires an operand size prefix (0x66), 285 // which most often indicates that the instruction operates on 16 bit data 286 // instead of 32 bit data. 287 OpSize = 1 << 6, 288 289 // AsSize - Set if this instruction requires an operand size prefix (0x67), 290 // which most often indicates that the instruction address 16 bit address 291 // instead of 32 bit address (or 32 bit address in 64 bit mode). 292 AdSize = 1 << 7, 293 294 //===------------------------------------------------------------------===// 295 // Op0Mask - There are several prefix bytes that are used to form two byte 296 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 297 // used to obtain the setting of this field. If no bits in this field is 298 // set, there is no prefix byte for obtaining a multibyte opcode. 299 // 300 Op0Shift = 8, 301 Op0Mask = 0xF << Op0Shift, 302 303 // TB - TwoByte - Set if this instruction has a two byte opcode, which 304 // starts with a 0x0F byte before the real opcode. 305 TB = 1 << Op0Shift, 306 307 // REP - The 0xF3 prefix byte indicating repetition of the following 308 // instruction. 309 REP = 2 << Op0Shift, 310 311 // D8-DF - These escape opcodes are used by the floating point unit. These 312 // values must remain sequential. 313 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 314 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 315 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 316 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 317 318 // XS, XD - These prefix codes are for single and double precision scalar 319 // floating point operations performed in the SSE registers. 320 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 321 322 // T8, TA - Prefix after the 0x0F prefix. 323 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 324 325 //===------------------------------------------------------------------===// 326 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 327 // They are used to specify GPRs and SSE registers, 64-bit operand size, 328 // etc. We only cares about REX.W and REX.R bits and only the former is 329 // statically determined. 330 // 331 REXShift = 12, 332 REX_W = 1 << REXShift, 333 334 //===------------------------------------------------------------------===// 335 // This three-bit field describes the size of an immediate operand. Zero is 336 // unused so that we can tell if we forgot to set a value. 337 ImmShift = 13, 338 ImmMask = 7 << ImmShift, 339 Imm8 = 1 << ImmShift, 340 Imm16 = 2 << ImmShift, 341 Imm32 = 3 << ImmShift, 342 Imm64 = 4 << ImmShift, 343 344 //===------------------------------------------------------------------===// 345 // FP Instruction Classification... Zero is non-fp instruction. 346 347 // FPTypeMask - Mask for all of the FP types... 348 FPTypeShift = 16, 349 FPTypeMask = 7 << FPTypeShift, 350 351 // NotFP - The default, set for instructions that do not use FP registers. 352 NotFP = 0 << FPTypeShift, 353 354 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 355 ZeroArgFP = 1 << FPTypeShift, 356 357 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 358 OneArgFP = 2 << FPTypeShift, 359 360 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 361 // result back to ST(0). For example, fcos, fsqrt, etc. 362 // 363 OneArgFPRW = 3 << FPTypeShift, 364 365 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 366 // explicit argument, storing the result to either ST(0) or the implicit 367 // argument. For example: fadd, fsub, fmul, etc... 368 TwoArgFP = 4 << FPTypeShift, 369 370 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 371 // explicit argument, but have no destination. Example: fucom, fucomi, ... 372 CompareFP = 5 << FPTypeShift, 373 374 // CondMovFP - "2 operand" floating point conditional move instructions. 375 CondMovFP = 6 << FPTypeShift, 376 377 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 378 SpecialFP = 7 << FPTypeShift, 379 380 // Lock prefix 381 LOCKShift = 19, 382 LOCK = 1 << LOCKShift, 383 384 // Segment override prefixes. Currently we just need ability to address 385 // stuff in gs and fs segments. 386 SegOvrShift = 20, 387 SegOvrMask = 3 << SegOvrShift, 388 FS = 1 << SegOvrShift, 389 GS = 2 << SegOvrShift, 390 391 // Bits 22 -> 23 are unused 392 OpcodeShift = 24, 393 OpcodeMask = 0xFF << OpcodeShift 394 }; 395} 396 397const int X86AddrNumOperands = 5; 398 399inline static bool isScale(const MachineOperand &MO) { 400 return MO.isImm() && 401 (MO.getImm() == 1 || MO.getImm() == 2 || 402 MO.getImm() == 4 || MO.getImm() == 8); 403} 404 405inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 406 if (MI->getOperand(Op).isFI()) return true; 407 return Op+4 <= MI->getNumOperands() && 408 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 409 MI->getOperand(Op+2).isReg() && 410 (MI->getOperand(Op+3).isImm() || 411 MI->getOperand(Op+3).isGlobal() || 412 MI->getOperand(Op+3).isCPI() || 413 MI->getOperand(Op+3).isJTI()); 414} 415 416inline static bool isMem(const MachineInstr *MI, unsigned Op) { 417 if (MI->getOperand(Op).isFI()) return true; 418 return Op+5 <= MI->getNumOperands() && 419 MI->getOperand(Op+4).isReg() && 420 isLeaMem(MI, Op); 421} 422 423class X86InstrInfo : public TargetInstrInfoImpl { 424 X86TargetMachine &TM; 425 const X86RegisterInfo RI; 426 427 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 428 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 429 /// 430 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 431 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 432 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 433 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 434 435 /// MemOp2RegOpTable - Load / store unfolding opcode map. 436 /// 437 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 438 439public: 440 explicit X86InstrInfo(X86TargetMachine &tm); 441 442 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 443 /// such, whenever a client has an instance of instruction info, it should 444 /// always be able to get register info as well (through this method). 445 /// 446 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 447 448 /// Return true if the instruction is a register to register move and return 449 /// the source and dest operands and their sub-register indices by reference. 450 virtual bool isMoveInstr(const MachineInstr &MI, 451 unsigned &SrcReg, unsigned &DstReg, 452 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 453 454 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 455 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 456 457 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 458 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 459 unsigned DestReg, const MachineInstr *Orig) const; 460 461 bool isInvariantLoad(const MachineInstr *MI) const; 462 463 /// convertToThreeAddress - This method must be implemented by targets that 464 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 465 /// may be able to convert a two-address instruction into a true 466 /// three-address instruction on demand. This allows the X86 target (for 467 /// example) to convert ADD and SHL instructions into LEA instructions if they 468 /// would require register copies due to two-addressness. 469 /// 470 /// This method returns a null pointer if the transformation cannot be 471 /// performed, otherwise it returns the new instruction. 472 /// 473 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 474 MachineBasicBlock::iterator &MBBI, 475 LiveVariables *LV) const; 476 477 /// commuteInstruction - We have a few instructions that must be hacked on to 478 /// commute them. 479 /// 480 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 481 482 // Branch analysis. 483 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 484 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 485 MachineBasicBlock *&FBB, 486 SmallVectorImpl<MachineOperand> &Cond, 487 bool AllowModify) const; 488 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 489 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 490 MachineBasicBlock *FBB, 491 const SmallVectorImpl<MachineOperand> &Cond) const; 492 virtual bool copyRegToReg(MachineBasicBlock &MBB, 493 MachineBasicBlock::iterator MI, 494 unsigned DestReg, unsigned SrcReg, 495 const TargetRegisterClass *DestRC, 496 const TargetRegisterClass *SrcRC) const; 497 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 498 MachineBasicBlock::iterator MI, 499 unsigned SrcReg, bool isKill, int FrameIndex, 500 const TargetRegisterClass *RC) const; 501 502 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 503 SmallVectorImpl<MachineOperand> &Addr, 504 const TargetRegisterClass *RC, 505 SmallVectorImpl<MachineInstr*> &NewMIs) const; 506 507 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 508 MachineBasicBlock::iterator MI, 509 unsigned DestReg, int FrameIndex, 510 const TargetRegisterClass *RC) const; 511 512 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 513 SmallVectorImpl<MachineOperand> &Addr, 514 const TargetRegisterClass *RC, 515 SmallVectorImpl<MachineInstr*> &NewMIs) const; 516 517 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 518 MachineBasicBlock::iterator MI, 519 const std::vector<CalleeSavedInfo> &CSI) const; 520 521 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 522 MachineBasicBlock::iterator MI, 523 const std::vector<CalleeSavedInfo> &CSI) const; 524 525 /// foldMemoryOperand - If this target supports it, fold a load or store of 526 /// the specified stack slot into the specified machine instruction for the 527 /// specified operand(s). If this is possible, the target should perform the 528 /// folding and return true, otherwise it should return false. If it folds 529 /// the instruction, it is likely that the MachineInstruction the iterator 530 /// references has been changed. 531 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 532 MachineInstr* MI, 533 const SmallVectorImpl<unsigned> &Ops, 534 int FrameIndex) const; 535 536 /// foldMemoryOperand - Same as the previous version except it allows folding 537 /// of any load and store from / to any address, not just from a specific 538 /// stack slot. 539 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 540 MachineInstr* MI, 541 const SmallVectorImpl<unsigned> &Ops, 542 MachineInstr* LoadMI) const; 543 544 /// canFoldMemoryOperand - Returns true if the specified load / store is 545 /// folding is possible. 546 virtual bool canFoldMemoryOperand(const MachineInstr*, 547 const SmallVectorImpl<unsigned> &) const; 548 549 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 550 /// a store or a load and a store into two or more instruction. If this is 551 /// possible, returns true as well as the new instructions by reference. 552 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 553 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 554 SmallVectorImpl<MachineInstr*> &NewMIs) const; 555 556 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 557 SmallVectorImpl<SDNode*> &NewNodes) const; 558 559 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 560 /// instruction after load / store are unfolded from an instruction of the 561 /// specified opcode. It returns zero if the specified unfolding is not 562 /// possible. 563 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 564 bool UnfoldLoad, bool UnfoldStore) const; 565 566 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 567 virtual 568 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 569 570 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 571 /// instruction that defines the specified register class. 572 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 573 574 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 575 // specified machine instruction. 576 // 577 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 578 return TID->TSFlags >> X86II::OpcodeShift; 579 } 580 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 581 return getBaseOpcodeFor(&get(Opcode)); 582 } 583 584 static bool isX86_64NonExtLowByteReg(unsigned reg) { 585 return (reg == X86::SPL || reg == X86::BPL || 586 reg == X86::SIL || reg == X86::DIL); 587 } 588 589 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 590 static bool isX86_64ExtendedReg(const MachineOperand &MO); 591 static unsigned determineREX(const MachineInstr &MI); 592 593 /// GetInstSize - Returns the size of the specified MachineInstr. 594 /// 595 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 596 597 /// getGlobalBaseReg - Return a virtual register initialized with the 598 /// the global base register value. Output instructions required to 599 /// initialize the register in the function entry block, if necessary. 600 /// 601 unsigned getGlobalBaseReg(MachineFunction *MF) const; 602 603private: 604 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 605 MachineInstr* MI, 606 unsigned OpNum, 607 const SmallVectorImpl<MachineOperand> &MOs) const; 608}; 609 610} // End llvm namespace 611 612#endif 613