X86InstrInfo.h revision 408396014742a05cad1c91949d2226169e3f9d80
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86RegisterInfo.h" 19 20namespace llvm { 21 22/// X86II - This namespace holds all of the target specific flags that 23/// instruction info tracks. 24/// 25namespace X86II { 26 enum { 27 //===------------------------------------------------------------------===// 28 // Instruction types. These are the standard/most common forms for X86 29 // instructions. 30 // 31 32 // PseudoFrm - This represents an instruction that is a pseudo instruction 33 // or one that has not been implemented yet. It is illegal to code generate 34 // it, but tolerated for intermediate implementation stages. 35 Pseudo = 0, 36 37 /// Raw - This form is for instructions that don't have any operands, so 38 /// they are just a fixed opcode value, like 'leave'. 39 RawFrm = 1, 40 41 /// AddRegFrm - This form is used for instructions like 'push r32' that have 42 /// their one register operand added to their opcode. 43 AddRegFrm = 2, 44 45 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 46 /// to specify a destination, which in this case is a register. 47 /// 48 MRMDestReg = 3, 49 50 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 51 /// to specify a destination, which in this case is memory. 52 /// 53 MRMDestMem = 4, 54 55 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 56 /// to specify a source, which in this case is a register. 57 /// 58 MRMSrcReg = 5, 59 60 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 61 /// to specify a source, which in this case is memory. 62 /// 63 MRMSrcMem = 6, 64 65 /// MRM[0-7][rm] - These forms are used to represent instructions that use 66 /// a Mod/RM byte, and use the middle field to hold extended opcode 67 /// information. In the intel manual these are represented as /0, /1, ... 68 /// 69 70 // First, instructions that operate on a register r/m operand... 71 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 72 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 73 74 // Next, instructions that operate on a memory r/m operand... 75 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 76 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 77 78 // MRMInitReg - This form is used for instructions whose source and 79 // destinations are the same register. 80 MRMInitReg = 32, 81 82 FormMask = 63, 83 84 //===------------------------------------------------------------------===// 85 // Actual flags... 86 87 // OpSize - Set if this instruction requires an operand size prefix (0x66), 88 // which most often indicates that the instruction operates on 16 bit data 89 // instead of 32 bit data. 90 OpSize = 1 << 6, 91 92 // Op0Mask - There are several prefix bytes that are used to form two byte 93 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 94 // used to obtain the setting of this field. If no bits in this field is 95 // set, there is no prefix byte for obtaining a multibyte opcode. 96 // 97 Op0Shift = 7, 98 Op0Mask = 0xF << Op0Shift, 99 100 // TB - TwoByte - Set if this instruction has a two byte opcode, which 101 // starts with a 0x0F byte before the real opcode. 102 TB = 1 << Op0Shift, 103 104 // REP - The 0xF3 prefix byte indicating repetition of the following 105 // instruction. 106 REP = 2 << Op0Shift, 107 108 // D8-DF - These escape opcodes are used by the floating point unit. These 109 // values must remain sequential. 110 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 111 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 112 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 113 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 114 115 // XS, XD - These prefix codes are for single and double precision scalar 116 // floating point operations performed in the SSE registers. 117 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 118 119 //===------------------------------------------------------------------===// 120 // This two-bit field describes the size of an immediate operand. Zero is 121 // unused so that we can tell if we forgot to set a value. 122 ImmShift = 11, 123 ImmMask = 7 << ImmShift, 124 Imm8 = 1 << ImmShift, 125 Imm16 = 2 << ImmShift, 126 Imm32 = 3 << ImmShift, 127 128 //===------------------------------------------------------------------===// 129 // FP Instruction Classification... Zero is non-fp instruction. 130 131 // FPTypeMask - Mask for all of the FP types... 132 FPTypeShift = 13, 133 FPTypeMask = 7 << FPTypeShift, 134 135 // NotFP - The default, set for instructions that do not use FP registers. 136 NotFP = 0 << FPTypeShift, 137 138 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 139 ZeroArgFP = 1 << FPTypeShift, 140 141 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 142 OneArgFP = 2 << FPTypeShift, 143 144 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 145 // result back to ST(0). For example, fcos, fsqrt, etc. 146 // 147 OneArgFPRW = 3 << FPTypeShift, 148 149 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 150 // explicit argument, storing the result to either ST(0) or the implicit 151 // argument. For example: fadd, fsub, fmul, etc... 152 TwoArgFP = 4 << FPTypeShift, 153 154 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 155 // explicit argument, but have no destination. Example: fucom, fucomi, ... 156 CompareFP = 5 << FPTypeShift, 157 158 // CondMovFP - "2 operand" floating point conditional move instructions. 159 CondMovFP = 6 << FPTypeShift, 160 161 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 162 SpecialFP = 7 << FPTypeShift, 163 164 // Bit 15 is unused. 165 OpcodeShift = 17, 166 OpcodeMask = 0xFF << OpcodeShift, 167 // Bits 25 -> 31 are unused 168 }; 169} 170 171class X86InstrInfo : public TargetInstrInfo { 172 const X86RegisterInfo RI; 173public: 174 X86InstrInfo(); 175 176 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 177 /// such, whenever a client has an instance of instruction info, it should 178 /// always be able to get register info as well (through this method). 179 /// 180 virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 181 182 // Return true if the instruction is a register to register move and 183 // leave the source and dest operands in the passed parameters. 184 // 185 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 186 unsigned& destReg) const; 187 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 188 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 189 190 /// convertToThreeAddress - This method must be implemented by targets that 191 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 192 /// may be able to convert a two-address instruction into a true 193 /// three-address instruction on demand. This allows the X86 target (for 194 /// example) to convert ADD and SHL instructions into LEA instructions if they 195 /// would require register copies due to two-addressness. 196 /// 197 /// This method returns a null pointer if the transformation cannot be 198 /// performed, otherwise it returns the new instruction. 199 /// 200 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const; 201 202 /// commuteInstruction - We have a few instructions that must be hacked on to 203 /// commute them. 204 /// 205 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 206 207 208 /// Insert a goto (unconditional branch) sequence to TMBB, at the 209 /// end of MBB 210 virtual void insertGoto(MachineBasicBlock& MBB, 211 MachineBasicBlock& TMBB) const; 212 213 /// Reverses the branch condition of the MachineInstr pointed by 214 /// MI. The instruction is replaced and the new MI is returned. 215 virtual MachineBasicBlock::iterator 216 reverseBranchCondition(MachineBasicBlock::iterator MI) const; 217 218 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 219 // specified opcode number. 220 // 221 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 222 return get(Opcode).TSFlags >> X86II::OpcodeShift; 223 } 224}; 225 226} // End llvm namespace 227 228#endif 229