X86InstrInfo.h revision 58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/IndexedMap.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22 23namespace llvm { 24 class X86RegisterInfo; 25 class X86TargetMachine; 26 27namespace X86 { 28 // X86 specific condition code. These correspond to X86_*_COND in 29 // X86InstrInfo.td. They must be kept in synch. 30 enum CondCode { 31 COND_A = 0, 32 COND_AE = 1, 33 COND_B = 2, 34 COND_BE = 3, 35 COND_E = 4, 36 COND_G = 5, 37 COND_GE = 6, 38 COND_L = 7, 39 COND_LE = 8, 40 COND_NE = 9, 41 COND_NO = 10, 42 COND_NP = 11, 43 COND_NS = 12, 44 COND_O = 13, 45 COND_P = 14, 46 COND_S = 15, 47 COND_INVALID 48 }; 49 50 // Turn condition code into conditional branch opcode. 51 unsigned GetCondBranchFromCond(CondCode CC); 52 53 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 54 /// e.g. turning COND_E to COND_NE. 55 CondCode GetOppositeBranchCondition(X86::CondCode CC); 56 57} 58 59/// X86II - This namespace holds all of the target specific flags that 60/// instruction info tracks. 61/// 62namespace X86II { 63 enum { 64 //===------------------------------------------------------------------===// 65 // Instruction types. These are the standard/most common forms for X86 66 // instructions. 67 // 68 69 // PseudoFrm - This represents an instruction that is a pseudo instruction 70 // or one that has not been implemented yet. It is illegal to code generate 71 // it, but tolerated for intermediate implementation stages. 72 Pseudo = 0, 73 74 /// Raw - This form is for instructions that don't have any operands, so 75 /// they are just a fixed opcode value, like 'leave'. 76 RawFrm = 1, 77 78 /// AddRegFrm - This form is used for instructions like 'push r32' that have 79 /// their one register operand added to their opcode. 80 AddRegFrm = 2, 81 82 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 83 /// to specify a destination, which in this case is a register. 84 /// 85 MRMDestReg = 3, 86 87 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 88 /// to specify a destination, which in this case is memory. 89 /// 90 MRMDestMem = 4, 91 92 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 93 /// to specify a source, which in this case is a register. 94 /// 95 MRMSrcReg = 5, 96 97 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 98 /// to specify a source, which in this case is memory. 99 /// 100 MRMSrcMem = 6, 101 102 /// MRM[0-7][rm] - These forms are used to represent instructions that use 103 /// a Mod/RM byte, and use the middle field to hold extended opcode 104 /// information. In the intel manual these are represented as /0, /1, ... 105 /// 106 107 // First, instructions that operate on a register r/m operand... 108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 110 111 // Next, instructions that operate on a memory r/m operand... 112 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 113 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 114 115 // MRMInitReg - This form is used for instructions whose source and 116 // destinations are the same register. 117 MRMInitReg = 32, 118 119 FormMask = 63, 120 121 //===------------------------------------------------------------------===// 122 // Actual flags... 123 124 // OpSize - Set if this instruction requires an operand size prefix (0x66), 125 // which most often indicates that the instruction operates on 16 bit data 126 // instead of 32 bit data. 127 OpSize = 1 << 6, 128 129 // AsSize - Set if this instruction requires an operand size prefix (0x67), 130 // which most often indicates that the instruction address 16 bit address 131 // instead of 32 bit address (or 32 bit address in 64 bit mode). 132 AdSize = 1 << 7, 133 134 //===------------------------------------------------------------------===// 135 // Op0Mask - There are several prefix bytes that are used to form two byte 136 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 137 // used to obtain the setting of this field. If no bits in this field is 138 // set, there is no prefix byte for obtaining a multibyte opcode. 139 // 140 Op0Shift = 8, 141 Op0Mask = 0xF << Op0Shift, 142 143 // TB - TwoByte - Set if this instruction has a two byte opcode, which 144 // starts with a 0x0F byte before the real opcode. 145 TB = 1 << Op0Shift, 146 147 // REP - The 0xF3 prefix byte indicating repetition of the following 148 // instruction. 149 REP = 2 << Op0Shift, 150 151 // D8-DF - These escape opcodes are used by the floating point unit. These 152 // values must remain sequential. 153 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 154 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 155 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 156 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 157 158 // XS, XD - These prefix codes are for single and double precision scalar 159 // floating point operations performed in the SSE registers. 160 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 161 162 // T8, TA - Prefix after the 0x0F prefix. 163 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 164 165 //===------------------------------------------------------------------===// 166 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 167 // They are used to specify GPRs and SSE registers, 64-bit operand size, 168 // etc. We only cares about REX.W and REX.R bits and only the former is 169 // statically determined. 170 // 171 REXShift = 12, 172 REX_W = 1 << REXShift, 173 174 //===------------------------------------------------------------------===// 175 // This three-bit field describes the size of an immediate operand. Zero is 176 // unused so that we can tell if we forgot to set a value. 177 ImmShift = 13, 178 ImmMask = 7 << ImmShift, 179 Imm8 = 1 << ImmShift, 180 Imm16 = 2 << ImmShift, 181 Imm32 = 3 << ImmShift, 182 Imm64 = 4 << ImmShift, 183 184 //===------------------------------------------------------------------===// 185 // FP Instruction Classification... Zero is non-fp instruction. 186 187 // FPTypeMask - Mask for all of the FP types... 188 FPTypeShift = 16, 189 FPTypeMask = 7 << FPTypeShift, 190 191 // NotFP - The default, set for instructions that do not use FP registers. 192 NotFP = 0 << FPTypeShift, 193 194 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 195 ZeroArgFP = 1 << FPTypeShift, 196 197 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 198 OneArgFP = 2 << FPTypeShift, 199 200 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 201 // result back to ST(0). For example, fcos, fsqrt, etc. 202 // 203 OneArgFPRW = 3 << FPTypeShift, 204 205 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 206 // explicit argument, storing the result to either ST(0) or the implicit 207 // argument. For example: fadd, fsub, fmul, etc... 208 TwoArgFP = 4 << FPTypeShift, 209 210 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 211 // explicit argument, but have no destination. Example: fucom, fucomi, ... 212 CompareFP = 5 << FPTypeShift, 213 214 // CondMovFP - "2 operand" floating point conditional move instructions. 215 CondMovFP = 6 << FPTypeShift, 216 217 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 218 SpecialFP = 7 << FPTypeShift, 219 220 // Lock prefix 221 LOCKShift = 19, 222 LOCK = 1 << LOCKShift, 223 224 // Bits 20 -> 23 are unused 225 OpcodeShift = 24, 226 OpcodeMask = 0xFF << OpcodeShift 227 }; 228} 229 230class X86InstrInfo : public TargetInstrInfoImpl { 231 X86TargetMachine &TM; 232 const X86RegisterInfo RI; 233 234 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 235 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 236 /// 237 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 238 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 239 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 240 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 241 242 /// MemOp2RegOpTable - Load / store unfolding opcode map. 243 /// 244 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 245 246public: 247 explicit X86InstrInfo(X86TargetMachine &tm); 248 249 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 250 /// such, whenever a client has an instance of instruction info, it should 251 /// always be able to get register info as well (through this method). 252 /// 253 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 254 255 // Return true if the instruction is a register to register move and 256 // leave the source and dest operands in the passed parameters. 257 // 258 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 259 unsigned& destReg) const; 260 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 261 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 262 263 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 264 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 265 unsigned DestReg, const MachineInstr *Orig) const; 266 267 bool isInvariantLoad(MachineInstr *MI) const; 268 269 /// convertToThreeAddress - This method must be implemented by targets that 270 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 271 /// may be able to convert a two-address instruction into a true 272 /// three-address instruction on demand. This allows the X86 target (for 273 /// example) to convert ADD and SHL instructions into LEA instructions if they 274 /// would require register copies due to two-addressness. 275 /// 276 /// This method returns a null pointer if the transformation cannot be 277 /// performed, otherwise it returns the new instruction. 278 /// 279 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 280 MachineBasicBlock::iterator &MBBI, 281 LiveVariables &LV) const; 282 283 /// commuteInstruction - We have a few instructions that must be hacked on to 284 /// commute them. 285 /// 286 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 287 288 // Branch analysis. 289 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 290 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 291 MachineBasicBlock *&FBB, 292 std::vector<MachineOperand> &Cond) const; 293 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 294 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 295 MachineBasicBlock *FBB, 296 const std::vector<MachineOperand> &Cond) const; 297 virtual void copyRegToReg(MachineBasicBlock &MBB, 298 MachineBasicBlock::iterator MI, 299 unsigned DestReg, unsigned SrcReg, 300 const TargetRegisterClass *DestRC, 301 const TargetRegisterClass *SrcRC) const; 302 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 303 MachineBasicBlock::iterator MI, 304 unsigned SrcReg, bool isKill, int FrameIndex, 305 const TargetRegisterClass *RC) const; 306 307 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 308 SmallVectorImpl<MachineOperand> &Addr, 309 const TargetRegisterClass *RC, 310 SmallVectorImpl<MachineInstr*> &NewMIs) const; 311 312 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 313 MachineBasicBlock::iterator MI, 314 unsigned DestReg, int FrameIndex, 315 const TargetRegisterClass *RC) const; 316 317 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 318 SmallVectorImpl<MachineOperand> &Addr, 319 const TargetRegisterClass *RC, 320 SmallVectorImpl<MachineInstr*> &NewMIs) const; 321 322 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 323 MachineBasicBlock::iterator MI, 324 const std::vector<CalleeSavedInfo> &CSI) const; 325 326 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 327 MachineBasicBlock::iterator MI, 328 const std::vector<CalleeSavedInfo> &CSI) const; 329 330 /// foldMemoryOperand - If this target supports it, fold a load or store of 331 /// the specified stack slot into the specified machine instruction for the 332 /// specified operand(s). If this is possible, the target should perform the 333 /// folding and return true, otherwise it should return false. If it folds 334 /// the instruction, it is likely that the MachineInstruction the iterator 335 /// references has been changed. 336 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 337 MachineInstr* MI, 338 SmallVectorImpl<unsigned> &Ops, 339 int FrameIndex) const; 340 341 /// foldMemoryOperand - Same as the previous version except it allows folding 342 /// of any load and store from / to any address, not just from a specific 343 /// stack slot. 344 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 345 MachineInstr* MI, 346 SmallVectorImpl<unsigned> &Ops, 347 MachineInstr* LoadMI) const; 348 349 /// canFoldMemoryOperand - Returns true if the specified load / store is 350 /// folding is possible. 351 virtual bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl<unsigned> &) const; 352 353 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 354 /// a store or a load and a store into two or more instruction. If this is 355 /// possible, returns true as well as the new instructions by reference. 356 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 357 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 358 SmallVectorImpl<MachineInstr*> &NewMIs) const; 359 360 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 361 SmallVectorImpl<SDNode*> &NewNodes) const; 362 363 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 364 /// instruction after load / store are unfolded from an instruction of the 365 /// specified opcode. It returns zero if the specified unfolding is not 366 /// possible. 367 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 368 bool UnfoldLoad, bool UnfoldStore) const; 369 370 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; 371 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; 372 373 const TargetRegisterClass *getPointerRegClass() const; 374 375 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 376 // specified machine instruction. 377 // 378 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 379 return TID->TSFlags >> X86II::OpcodeShift; 380 } 381 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 382 return getBaseOpcodeFor(&get(Opcode)); 383 } 384 385 static bool isX86_64NonExtLowByteReg(unsigned reg) { 386 return (reg == X86::SPL || reg == X86::BPL || 387 reg == X86::SIL || reg == X86::DIL); 388 } 389 390 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 391 static unsigned getX86RegNum(unsigned RegNo); 392 static bool isX86_64ExtendedReg(const MachineOperand &MO); 393 static unsigned determineREX(const MachineInstr &MI); 394 395 /// GetInstSize - Returns the size of the specified MachineInstr. 396 /// 397 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 398 399private: 400 MachineInstr* foldMemoryOperand(MachineInstr* MI, 401 unsigned OpNum, 402 SmallVector<MachineOperand,4> &MOs) const; 403}; 404 405} // End llvm namespace 406 407#endif 408