X86InstrInfo.h revision 627c00b663f881600b4af1ae135af6ee2cb19c1a
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86RegisterInfo.h" 19 20namespace llvm { 21 class X86RegisterInfo; 22 class X86TargetMachine; 23 24namespace X86 { 25 // X86 specific condition code. These correspond to X86_*_COND in 26 // X86InstrInfo.td. They must be kept in synch. 27 enum CondCode { 28 COND_A = 0, 29 COND_AE = 1, 30 COND_B = 2, 31 COND_BE = 3, 32 COND_E = 4, 33 COND_G = 5, 34 COND_GE = 6, 35 COND_L = 7, 36 COND_LE = 8, 37 COND_NE = 9, 38 COND_NO = 10, 39 COND_NP = 11, 40 COND_NS = 12, 41 COND_O = 13, 42 COND_P = 14, 43 COND_S = 15, 44 COND_INVALID 45 }; 46 47 // Turn condition code into conditional branch opcode. 48 unsigned GetCondBranchFromCond(CondCode CC); 49 50 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 51 /// e.g. turning COND_E to COND_NE. 52 CondCode GetOppositeBranchCondition(X86::CondCode CC); 53 54} 55 56/// X86II - This namespace holds all of the target specific flags that 57/// instruction info tracks. 58/// 59namespace X86II { 60 enum { 61 //===------------------------------------------------------------------===// 62 // Instruction types. These are the standard/most common forms for X86 63 // instructions. 64 // 65 66 // PseudoFrm - This represents an instruction that is a pseudo instruction 67 // or one that has not been implemented yet. It is illegal to code generate 68 // it, but tolerated for intermediate implementation stages. 69 Pseudo = 0, 70 71 /// Raw - This form is for instructions that don't have any operands, so 72 /// they are just a fixed opcode value, like 'leave'. 73 RawFrm = 1, 74 75 /// AddRegFrm - This form is used for instructions like 'push r32' that have 76 /// their one register operand added to their opcode. 77 AddRegFrm = 2, 78 79 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 80 /// to specify a destination, which in this case is a register. 81 /// 82 MRMDestReg = 3, 83 84 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 85 /// to specify a destination, which in this case is memory. 86 /// 87 MRMDestMem = 4, 88 89 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 90 /// to specify a source, which in this case is a register. 91 /// 92 MRMSrcReg = 5, 93 94 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 95 /// to specify a source, which in this case is memory. 96 /// 97 MRMSrcMem = 6, 98 99 /// MRM[0-7][rm] - These forms are used to represent instructions that use 100 /// a Mod/RM byte, and use the middle field to hold extended opcode 101 /// information. In the intel manual these are represented as /0, /1, ... 102 /// 103 104 // First, instructions that operate on a register r/m operand... 105 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 106 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 107 108 // Next, instructions that operate on a memory r/m operand... 109 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 110 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 111 112 // MRMInitReg - This form is used for instructions whose source and 113 // destinations are the same register. 114 MRMInitReg = 32, 115 116 FormMask = 63, 117 118 //===------------------------------------------------------------------===// 119 // Actual flags... 120 121 // OpSize - Set if this instruction requires an operand size prefix (0x66), 122 // which most often indicates that the instruction operates on 16 bit data 123 // instead of 32 bit data. 124 OpSize = 1 << 6, 125 126 // AsSize - Set if this instruction requires an operand size prefix (0x67), 127 // which most often indicates that the instruction address 16 bit address 128 // instead of 32 bit address (or 32 bit address in 64 bit mode). 129 AdSize = 1 << 7, 130 131 //===------------------------------------------------------------------===// 132 // Op0Mask - There are several prefix bytes that are used to form two byte 133 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 134 // used to obtain the setting of this field. If no bits in this field is 135 // set, there is no prefix byte for obtaining a multibyte opcode. 136 // 137 Op0Shift = 8, 138 Op0Mask = 0xF << Op0Shift, 139 140 // TB - TwoByte - Set if this instruction has a two byte opcode, which 141 // starts with a 0x0F byte before the real opcode. 142 TB = 1 << Op0Shift, 143 144 // REP - The 0xF3 prefix byte indicating repetition of the following 145 // instruction. 146 REP = 2 << Op0Shift, 147 148 // D8-DF - These escape opcodes are used by the floating point unit. These 149 // values must remain sequential. 150 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 151 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 152 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 153 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 154 155 // XS, XD - These prefix codes are for single and double precision scalar 156 // floating point operations performed in the SSE registers. 157 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 158 159 // T8, TA - Prefix after the 0x0F prefix. 160 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 161 162 //===------------------------------------------------------------------===// 163 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 164 // They are used to specify GPRs and SSE registers, 64-bit operand size, 165 // etc. We only cares about REX.W and REX.R bits and only the former is 166 // statically determined. 167 // 168 REXShift = 12, 169 REX_W = 1 << REXShift, 170 171 //===------------------------------------------------------------------===// 172 // This three-bit field describes the size of an immediate operand. Zero is 173 // unused so that we can tell if we forgot to set a value. 174 ImmShift = 13, 175 ImmMask = 7 << ImmShift, 176 Imm8 = 1 << ImmShift, 177 Imm16 = 2 << ImmShift, 178 Imm32 = 3 << ImmShift, 179 Imm64 = 4 << ImmShift, 180 181 //===------------------------------------------------------------------===// 182 // FP Instruction Classification... Zero is non-fp instruction. 183 184 // FPTypeMask - Mask for all of the FP types... 185 FPTypeShift = 16, 186 FPTypeMask = 7 << FPTypeShift, 187 188 // NotFP - The default, set for instructions that do not use FP registers. 189 NotFP = 0 << FPTypeShift, 190 191 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 192 ZeroArgFP = 1 << FPTypeShift, 193 194 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 195 OneArgFP = 2 << FPTypeShift, 196 197 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 198 // result back to ST(0). For example, fcos, fsqrt, etc. 199 // 200 OneArgFPRW = 3 << FPTypeShift, 201 202 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 203 // explicit argument, storing the result to either ST(0) or the implicit 204 // argument. For example: fadd, fsub, fmul, etc... 205 TwoArgFP = 4 << FPTypeShift, 206 207 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 208 // explicit argument, but have no destination. Example: fucom, fucomi, ... 209 CompareFP = 5 << FPTypeShift, 210 211 // CondMovFP - "2 operand" floating point conditional move instructions. 212 CondMovFP = 6 << FPTypeShift, 213 214 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 215 SpecialFP = 7 << FPTypeShift, 216 217 // Bits 19 -> 23 are unused 218 OpcodeShift = 24, 219 OpcodeMask = 0xFF << OpcodeShift 220 }; 221} 222 223class X86InstrInfo : public TargetInstrInfo { 224 X86TargetMachine &TM; 225 const X86RegisterInfo RI; 226public: 227 X86InstrInfo(X86TargetMachine &tm); 228 229 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 230 /// such, whenever a client has an instance of instruction info, it should 231 /// always be able to get register info as well (through this method). 232 /// 233 virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 234 235 // Return true if the instruction is a register to register move and 236 // leave the source and dest operands in the passed parameters. 237 // 238 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 239 unsigned& destReg) const; 240 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 241 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 242 bool isReallyTriviallyReMaterializable(MachineInstr *MI) const; 243 bool isReallySideEffectFree(MachineInstr *MI) const; 244 245 /// convertToThreeAddress - This method must be implemented by targets that 246 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 247 /// may be able to convert a two-address instruction into a true 248 /// three-address instruction on demand. This allows the X86 target (for 249 /// example) to convert ADD and SHL instructions into LEA instructions if they 250 /// would require register copies due to two-addressness. 251 /// 252 /// This method returns a null pointer if the transformation cannot be 253 /// performed, otherwise it returns the new instruction. 254 /// 255 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 256 MachineBasicBlock::iterator &MBBI, 257 LiveVariables &LV) const; 258 259 /// commuteInstruction - We have a few instructions that must be hacked on to 260 /// commute them. 261 /// 262 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 263 264 // Branch analysis. 265 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 266 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 267 MachineBasicBlock *&FBB, 268 std::vector<MachineOperand> &Cond) const; 269 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 270 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 271 MachineBasicBlock *FBB, 272 const std::vector<MachineOperand> &Cond) const; 273 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; 274 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; 275 276 const TargetRegisterClass *getPointerRegClass() const; 277 278 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 279 // specified machine instruction. 280 // 281 unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const { 282 return TID->TSFlags >> X86II::OpcodeShift; 283 } 284 unsigned char getBaseOpcodeFor(MachineOpCode Opcode) const { 285 return getBaseOpcodeFor(&get(Opcode)); 286 } 287}; 288 289} // End llvm namespace 290 291#endif 292