X86InstrInfo.h revision 75cdf27f48f0b81f778b6aa50efcefa0497a9dae
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22 23namespace llvm { 24 class X86RegisterInfo; 25 class X86TargetMachine; 26 27namespace X86 { 28 // X86 specific condition code. These correspond to X86_*_COND in 29 // X86InstrInfo.td. They must be kept in synch. 30 enum CondCode { 31 COND_A = 0, 32 COND_AE = 1, 33 COND_B = 2, 34 COND_BE = 3, 35 COND_E = 4, 36 COND_G = 5, 37 COND_GE = 6, 38 COND_L = 7, 39 COND_LE = 8, 40 COND_NE = 9, 41 COND_NO = 10, 42 COND_NP = 11, 43 COND_NS = 12, 44 COND_O = 13, 45 COND_P = 14, 46 COND_S = 15, 47 48 // Artificial condition codes. These are used by AnalyzeBranch 49 // to indicate a block terminated with two conditional branches to 50 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 51 // which can't be represented on x86 with a single condition. These 52 // are never used in MachineInstrs. 53 COND_NE_OR_P, 54 COND_NP_OR_E, 55 56 COND_INVALID 57 }; 58 59 // Turn condition code into conditional branch opcode. 60 unsigned GetCondBranchFromCond(CondCode CC); 61 62 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63 /// e.g. turning COND_E to COND_NE. 64 CondCode GetOppositeBranchCondition(X86::CondCode CC); 65 66} 67 68/// X86II - This namespace holds all of the target specific flags that 69/// instruction info tracks. 70/// 71namespace X86II { 72 enum { 73 //===------------------------------------------------------------------===// 74 // X86 Specific MachineOperand flags. 75 76 MO_NO_FLAG = 0, 77 78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 79 /// relocation of: 80 /// SYMBOL_LABEL + [. - PICBASELABEL] 81 MO_GOT_ABSOLUTE_ADDRESS = 1, 82 83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 84 /// immediate should get the value of the symbol minus the PIC base label: 85 /// SYMBOL_LABEL - PICBASELABEL 86 MO_PIC_BASE_OFFSET = 2, 87 88 /// MO_GOT - On a symbol operand this indicates that the immediate is the 89 /// offset to the GOT entry for the symbol name from the base of the GOT. 90 /// 91 /// See the X86-64 ELF ABI supplement for more details. 92 /// SYMBOL_LABEL @GOT 93 MO_GOT = 3, 94 95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 96 /// the offset to the location of the symbol name from the base of the GOT. 97 /// 98 /// See the X86-64 ELF ABI supplement for more details. 99 /// SYMBOL_LABEL @GOTOFF 100 MO_GOTOFF = 4, 101 102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 103 /// offset to the GOT entry for the symbol name from the current code 104 /// location. 105 /// 106 /// See the X86-64 ELF ABI supplement for more details. 107 /// SYMBOL_LABEL @GOTPCREL 108 MO_GOTPCREL = 5, 109 110 /// MO_PLT - On a symbol operand this indicates that the immediate is 111 /// offset to the PLT entry of symbol name from the current code location. 112 /// 113 /// See the X86-64 ELF ABI supplement for more details. 114 /// SYMBOL_LABEL @PLT 115 MO_PLT = 6, 116 117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 118 /// some TLS offset. 119 /// 120 /// See 'ELF Handling for Thread-Local Storage' for more details. 121 /// SYMBOL_LABEL @TLSGD 122 MO_TLSGD = 7, 123 124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 125 /// some TLS offset. 126 /// 127 /// See 'ELF Handling for Thread-Local Storage' for more details. 128 /// SYMBOL_LABEL @GOTTPOFF 129 MO_GOTTPOFF = 8, 130 131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 132 /// some TLS offset. 133 /// 134 /// See 'ELF Handling for Thread-Local Storage' for more details. 135 /// SYMBOL_LABEL @INDNTPOFF 136 MO_INDNTPOFF = 9, 137 138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 139 /// some TLS offset. 140 /// 141 /// See 'ELF Handling for Thread-Local Storage' for more details. 142 /// SYMBOL_LABEL @TPOFF 143 MO_TPOFF = 10, 144 145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 146 /// some TLS offset. 147 /// 148 /// See 'ELF Handling for Thread-Local Storage' for more details. 149 /// SYMBOL_LABEL @NTPOFF 150 MO_NTPOFF = 11, 151 152 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 153 /// reference is actually to the "__imp_FOO" symbol. This is used for 154 /// dllimport linkage on windows. 155 MO_DLLIMPORT = 12, 156 157 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 158 /// reference is actually to the "FOO$stub" symbol. This is used for calls 159 /// and jumps to external functions on Tiger and before. 160 MO_DARWIN_STUB = 13, 161 162 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 163 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 164 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 165 MO_DARWIN_NONLAZY = 14, 166 167 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 168 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 169 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 170 MO_DARWIN_NONLAZY_PIC_BASE = 15, 171 172 /// MO_DARWIN_HIDDEN_NONLAZY - On a symbol operand "FOO", this indicates 173 /// that the reference is actually to the "FOO$non_lazy_ptr" symbol, which 174 /// is a non-PIC-base-relative reference to a hidden dyld lazy pointer stub. 175 MO_DARWIN_HIDDEN_NONLAZY = 16, 176 177 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 178 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 179 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 180 /// stub. 181 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE = 17, 182 183 //===------------------------------------------------------------------===// 184 // Instruction encodings. These are the standard/most common forms for X86 185 // instructions. 186 // 187 188 // PseudoFrm - This represents an instruction that is a pseudo instruction 189 // or one that has not been implemented yet. It is illegal to code generate 190 // it, but tolerated for intermediate implementation stages. 191 Pseudo = 0, 192 193 /// Raw - This form is for instructions that don't have any operands, so 194 /// they are just a fixed opcode value, like 'leave'. 195 RawFrm = 1, 196 197 /// AddRegFrm - This form is used for instructions like 'push r32' that have 198 /// their one register operand added to their opcode. 199 AddRegFrm = 2, 200 201 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 202 /// to specify a destination, which in this case is a register. 203 /// 204 MRMDestReg = 3, 205 206 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 207 /// to specify a destination, which in this case is memory. 208 /// 209 MRMDestMem = 4, 210 211 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 212 /// to specify a source, which in this case is a register. 213 /// 214 MRMSrcReg = 5, 215 216 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 217 /// to specify a source, which in this case is memory. 218 /// 219 MRMSrcMem = 6, 220 221 /// MRM[0-7][rm] - These forms are used to represent instructions that use 222 /// a Mod/RM byte, and use the middle field to hold extended opcode 223 /// information. In the intel manual these are represented as /0, /1, ... 224 /// 225 226 // First, instructions that operate on a register r/m operand... 227 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 228 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 229 230 // Next, instructions that operate on a memory r/m operand... 231 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 232 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 233 234 // MRMInitReg - This form is used for instructions whose source and 235 // destinations are the same register. 236 MRMInitReg = 32, 237 238 FormMask = 63, 239 240 //===------------------------------------------------------------------===// 241 // Actual flags... 242 243 // OpSize - Set if this instruction requires an operand size prefix (0x66), 244 // which most often indicates that the instruction operates on 16 bit data 245 // instead of 32 bit data. 246 OpSize = 1 << 6, 247 248 // AsSize - Set if this instruction requires an operand size prefix (0x67), 249 // which most often indicates that the instruction address 16 bit address 250 // instead of 32 bit address (or 32 bit address in 64 bit mode). 251 AdSize = 1 << 7, 252 253 //===------------------------------------------------------------------===// 254 // Op0Mask - There are several prefix bytes that are used to form two byte 255 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 256 // used to obtain the setting of this field. If no bits in this field is 257 // set, there is no prefix byte for obtaining a multibyte opcode. 258 // 259 Op0Shift = 8, 260 Op0Mask = 0xF << Op0Shift, 261 262 // TB - TwoByte - Set if this instruction has a two byte opcode, which 263 // starts with a 0x0F byte before the real opcode. 264 TB = 1 << Op0Shift, 265 266 // REP - The 0xF3 prefix byte indicating repetition of the following 267 // instruction. 268 REP = 2 << Op0Shift, 269 270 // D8-DF - These escape opcodes are used by the floating point unit. These 271 // values must remain sequential. 272 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 273 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 274 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 275 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 276 277 // XS, XD - These prefix codes are for single and double precision scalar 278 // floating point operations performed in the SSE registers. 279 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 280 281 // T8, TA - Prefix after the 0x0F prefix. 282 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 283 284 //===------------------------------------------------------------------===// 285 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 286 // They are used to specify GPRs and SSE registers, 64-bit operand size, 287 // etc. We only cares about REX.W and REX.R bits and only the former is 288 // statically determined. 289 // 290 REXShift = 12, 291 REX_W = 1 << REXShift, 292 293 //===------------------------------------------------------------------===// 294 // This three-bit field describes the size of an immediate operand. Zero is 295 // unused so that we can tell if we forgot to set a value. 296 ImmShift = 13, 297 ImmMask = 7 << ImmShift, 298 Imm8 = 1 << ImmShift, 299 Imm16 = 2 << ImmShift, 300 Imm32 = 3 << ImmShift, 301 Imm64 = 4 << ImmShift, 302 303 //===------------------------------------------------------------------===// 304 // FP Instruction Classification... Zero is non-fp instruction. 305 306 // FPTypeMask - Mask for all of the FP types... 307 FPTypeShift = 16, 308 FPTypeMask = 7 << FPTypeShift, 309 310 // NotFP - The default, set for instructions that do not use FP registers. 311 NotFP = 0 << FPTypeShift, 312 313 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 314 ZeroArgFP = 1 << FPTypeShift, 315 316 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 317 OneArgFP = 2 << FPTypeShift, 318 319 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 320 // result back to ST(0). For example, fcos, fsqrt, etc. 321 // 322 OneArgFPRW = 3 << FPTypeShift, 323 324 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 325 // explicit argument, storing the result to either ST(0) or the implicit 326 // argument. For example: fadd, fsub, fmul, etc... 327 TwoArgFP = 4 << FPTypeShift, 328 329 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 330 // explicit argument, but have no destination. Example: fucom, fucomi, ... 331 CompareFP = 5 << FPTypeShift, 332 333 // CondMovFP - "2 operand" floating point conditional move instructions. 334 CondMovFP = 6 << FPTypeShift, 335 336 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 337 SpecialFP = 7 << FPTypeShift, 338 339 // Lock prefix 340 LOCKShift = 19, 341 LOCK = 1 << LOCKShift, 342 343 // Segment override prefixes. Currently we just need ability to address 344 // stuff in gs and fs segments. 345 SegOvrShift = 20, 346 SegOvrMask = 3 << SegOvrShift, 347 FS = 1 << SegOvrShift, 348 GS = 2 << SegOvrShift, 349 350 // Bits 22 -> 23 are unused 351 OpcodeShift = 24, 352 OpcodeMask = 0xFF << OpcodeShift 353 }; 354} 355 356const int X86AddrNumOperands = 5; 357 358inline static bool isScale(const MachineOperand &MO) { 359 return MO.isImm() && 360 (MO.getImm() == 1 || MO.getImm() == 2 || 361 MO.getImm() == 4 || MO.getImm() == 8); 362} 363 364inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 365 if (MI->getOperand(Op).isFI()) return true; 366 return Op+4 <= MI->getNumOperands() && 367 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 368 MI->getOperand(Op+2).isReg() && 369 (MI->getOperand(Op+3).isImm() || 370 MI->getOperand(Op+3).isGlobal() || 371 MI->getOperand(Op+3).isCPI() || 372 MI->getOperand(Op+3).isJTI()); 373} 374 375inline static bool isMem(const MachineInstr *MI, unsigned Op) { 376 if (MI->getOperand(Op).isFI()) return true; 377 return Op+5 <= MI->getNumOperands() && 378 MI->getOperand(Op+4).isReg() && 379 isLeaMem(MI, Op); 380} 381 382class X86InstrInfo : public TargetInstrInfoImpl { 383 X86TargetMachine &TM; 384 const X86RegisterInfo RI; 385 386 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 387 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 388 /// 389 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 390 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 391 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 392 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 393 394 /// MemOp2RegOpTable - Load / store unfolding opcode map. 395 /// 396 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 397 398public: 399 explicit X86InstrInfo(X86TargetMachine &tm); 400 401 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 402 /// such, whenever a client has an instance of instruction info, it should 403 /// always be able to get register info as well (through this method). 404 /// 405 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 406 407 /// Return true if the instruction is a register to register move and return 408 /// the source and dest operands and their sub-register indices by reference. 409 virtual bool isMoveInstr(const MachineInstr &MI, 410 unsigned &SrcReg, unsigned &DstReg, 411 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 412 413 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 414 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 415 416 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 417 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 418 unsigned DestReg, const MachineInstr *Orig) const; 419 420 bool isInvariantLoad(const MachineInstr *MI) const; 421 422 /// convertToThreeAddress - This method must be implemented by targets that 423 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 424 /// may be able to convert a two-address instruction into a true 425 /// three-address instruction on demand. This allows the X86 target (for 426 /// example) to convert ADD and SHL instructions into LEA instructions if they 427 /// would require register copies due to two-addressness. 428 /// 429 /// This method returns a null pointer if the transformation cannot be 430 /// performed, otherwise it returns the new instruction. 431 /// 432 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 433 MachineBasicBlock::iterator &MBBI, 434 LiveVariables *LV) const; 435 436 /// commuteInstruction - We have a few instructions that must be hacked on to 437 /// commute them. 438 /// 439 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 440 441 // Branch analysis. 442 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 443 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 444 MachineBasicBlock *&FBB, 445 SmallVectorImpl<MachineOperand> &Cond, 446 bool AllowModify) const; 447 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 448 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 449 MachineBasicBlock *FBB, 450 const SmallVectorImpl<MachineOperand> &Cond) const; 451 virtual bool copyRegToReg(MachineBasicBlock &MBB, 452 MachineBasicBlock::iterator MI, 453 unsigned DestReg, unsigned SrcReg, 454 const TargetRegisterClass *DestRC, 455 const TargetRegisterClass *SrcRC) const; 456 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 457 MachineBasicBlock::iterator MI, 458 unsigned SrcReg, bool isKill, int FrameIndex, 459 const TargetRegisterClass *RC) const; 460 461 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 462 SmallVectorImpl<MachineOperand> &Addr, 463 const TargetRegisterClass *RC, 464 SmallVectorImpl<MachineInstr*> &NewMIs) const; 465 466 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 467 MachineBasicBlock::iterator MI, 468 unsigned DestReg, int FrameIndex, 469 const TargetRegisterClass *RC) const; 470 471 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 472 SmallVectorImpl<MachineOperand> &Addr, 473 const TargetRegisterClass *RC, 474 SmallVectorImpl<MachineInstr*> &NewMIs) const; 475 476 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 477 MachineBasicBlock::iterator MI, 478 const std::vector<CalleeSavedInfo> &CSI) const; 479 480 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 481 MachineBasicBlock::iterator MI, 482 const std::vector<CalleeSavedInfo> &CSI) const; 483 484 /// foldMemoryOperand - If this target supports it, fold a load or store of 485 /// the specified stack slot into the specified machine instruction for the 486 /// specified operand(s). If this is possible, the target should perform the 487 /// folding and return true, otherwise it should return false. If it folds 488 /// the instruction, it is likely that the MachineInstruction the iterator 489 /// references has been changed. 490 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 491 MachineInstr* MI, 492 const SmallVectorImpl<unsigned> &Ops, 493 int FrameIndex) const; 494 495 /// foldMemoryOperand - Same as the previous version except it allows folding 496 /// of any load and store from / to any address, not just from a specific 497 /// stack slot. 498 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 499 MachineInstr* MI, 500 const SmallVectorImpl<unsigned> &Ops, 501 MachineInstr* LoadMI) const; 502 503 /// canFoldMemoryOperand - Returns true if the specified load / store is 504 /// folding is possible. 505 virtual bool canFoldMemoryOperand(const MachineInstr*, 506 const SmallVectorImpl<unsigned> &) const; 507 508 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 509 /// a store or a load and a store into two or more instruction. If this is 510 /// possible, returns true as well as the new instructions by reference. 511 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 512 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 513 SmallVectorImpl<MachineInstr*> &NewMIs) const; 514 515 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 516 SmallVectorImpl<SDNode*> &NewNodes) const; 517 518 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 519 /// instruction after load / store are unfolded from an instruction of the 520 /// specified opcode. It returns zero if the specified unfolding is not 521 /// possible. 522 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 523 bool UnfoldLoad, bool UnfoldStore) const; 524 525 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 526 virtual 527 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 528 529 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 530 /// instruction that defines the specified register class. 531 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 532 533 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 534 // specified machine instruction. 535 // 536 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 537 return TID->TSFlags >> X86II::OpcodeShift; 538 } 539 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 540 return getBaseOpcodeFor(&get(Opcode)); 541 } 542 543 static bool isX86_64NonExtLowByteReg(unsigned reg) { 544 return (reg == X86::SPL || reg == X86::BPL || 545 reg == X86::SIL || reg == X86::DIL); 546 } 547 548 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 549 static bool isX86_64ExtendedReg(const MachineOperand &MO); 550 static unsigned determineREX(const MachineInstr &MI); 551 552 /// GetInstSize - Returns the size of the specified MachineInstr. 553 /// 554 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 555 556 /// getGlobalBaseReg - Return a virtual register initialized with the 557 /// the global base register value. Output instructions required to 558 /// initialize the register in the function entry block, if necessary. 559 /// 560 unsigned getGlobalBaseReg(MachineFunction *MF) const; 561 562private: 563 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 564 MachineInstr* MI, 565 unsigned OpNum, 566 const SmallVectorImpl<MachineOperand> &MOs) const; 567}; 568 569} // End llvm namespace 570 571#endif 572