X86InstrInfo.h revision 770bcc7b15adbc978800db70dbb1c3c22913b52c
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22 23namespace llvm { 24 class X86RegisterInfo; 25 class X86TargetMachine; 26 27namespace X86 { 28 // X86 specific condition code. These correspond to X86_*_COND in 29 // X86InstrInfo.td. They must be kept in synch. 30 enum CondCode { 31 COND_A = 0, 32 COND_AE = 1, 33 COND_B = 2, 34 COND_BE = 3, 35 COND_E = 4, 36 COND_G = 5, 37 COND_GE = 6, 38 COND_L = 7, 39 COND_LE = 8, 40 COND_NE = 9, 41 COND_NO = 10, 42 COND_NP = 11, 43 COND_NS = 12, 44 COND_O = 13, 45 COND_P = 14, 46 COND_S = 15, 47 48 // Artificial condition codes. These are used by AnalyzeBranch 49 // to indicate a block terminated with two conditional branches to 50 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 51 // which can't be represented on x86 with a single condition. These 52 // are never used in MachineInstrs. 53 COND_NE_OR_P, 54 COND_NP_OR_E, 55 56 COND_INVALID 57 }; 58 59 // Turn condition code into conditional branch opcode. 60 unsigned GetCondBranchFromCond(CondCode CC); 61 62 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63 /// e.g. turning COND_E to COND_NE. 64 CondCode GetOppositeBranchCondition(X86::CondCode CC); 65 66} 67 68/// X86II - This namespace holds all of the target specific flags that 69/// instruction info tracks. 70/// 71namespace X86II { 72 enum { 73 //===------------------------------------------------------------------===// 74 // Instruction types. These are the standard/most common forms for X86 75 // instructions. 76 // 77 78 // PseudoFrm - This represents an instruction that is a pseudo instruction 79 // or one that has not been implemented yet. It is illegal to code generate 80 // it, but tolerated for intermediate implementation stages. 81 Pseudo = 0, 82 83 /// Raw - This form is for instructions that don't have any operands, so 84 /// they are just a fixed opcode value, like 'leave'. 85 RawFrm = 1, 86 87 /// AddRegFrm - This form is used for instructions like 'push r32' that have 88 /// their one register operand added to their opcode. 89 AddRegFrm = 2, 90 91 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 92 /// to specify a destination, which in this case is a register. 93 /// 94 MRMDestReg = 3, 95 96 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 97 /// to specify a destination, which in this case is memory. 98 /// 99 MRMDestMem = 4, 100 101 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 102 /// to specify a source, which in this case is a register. 103 /// 104 MRMSrcReg = 5, 105 106 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 107 /// to specify a source, which in this case is memory. 108 /// 109 MRMSrcMem = 6, 110 111 /// MRM[0-7][rm] - These forms are used to represent instructions that use 112 /// a Mod/RM byte, and use the middle field to hold extended opcode 113 /// information. In the intel manual these are represented as /0, /1, ... 114 /// 115 116 // First, instructions that operate on a register r/m operand... 117 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 118 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 119 120 // Next, instructions that operate on a memory r/m operand... 121 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 122 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 123 124 // MRMInitReg - This form is used for instructions whose source and 125 // destinations are the same register. 126 MRMInitReg = 32, 127 128 FormMask = 63, 129 130 //===------------------------------------------------------------------===// 131 // Actual flags... 132 133 // OpSize - Set if this instruction requires an operand size prefix (0x66), 134 // which most often indicates that the instruction operates on 16 bit data 135 // instead of 32 bit data. 136 OpSize = 1 << 6, 137 138 // AsSize - Set if this instruction requires an operand size prefix (0x67), 139 // which most often indicates that the instruction address 16 bit address 140 // instead of 32 bit address (or 32 bit address in 64 bit mode). 141 AdSize = 1 << 7, 142 143 //===------------------------------------------------------------------===// 144 // Op0Mask - There are several prefix bytes that are used to form two byte 145 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 146 // used to obtain the setting of this field. If no bits in this field is 147 // set, there is no prefix byte for obtaining a multibyte opcode. 148 // 149 Op0Shift = 8, 150 Op0Mask = 0xF << Op0Shift, 151 152 // TB - TwoByte - Set if this instruction has a two byte opcode, which 153 // starts with a 0x0F byte before the real opcode. 154 TB = 1 << Op0Shift, 155 156 // REP - The 0xF3 prefix byte indicating repetition of the following 157 // instruction. 158 REP = 2 << Op0Shift, 159 160 // D8-DF - These escape opcodes are used by the floating point unit. These 161 // values must remain sequential. 162 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 163 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 164 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 165 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 166 167 // XS, XD - These prefix codes are for single and double precision scalar 168 // floating point operations performed in the SSE registers. 169 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 170 171 // T8, TA - Prefix after the 0x0F prefix. 172 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 173 174 //===------------------------------------------------------------------===// 175 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 176 // They are used to specify GPRs and SSE registers, 64-bit operand size, 177 // etc. We only cares about REX.W and REX.R bits and only the former is 178 // statically determined. 179 // 180 REXShift = 12, 181 REX_W = 1 << REXShift, 182 183 //===------------------------------------------------------------------===// 184 // This three-bit field describes the size of an immediate operand. Zero is 185 // unused so that we can tell if we forgot to set a value. 186 ImmShift = 13, 187 ImmMask = 7 << ImmShift, 188 Imm8 = 1 << ImmShift, 189 Imm16 = 2 << ImmShift, 190 Imm32 = 3 << ImmShift, 191 Imm64 = 4 << ImmShift, 192 193 //===------------------------------------------------------------------===// 194 // FP Instruction Classification... Zero is non-fp instruction. 195 196 // FPTypeMask - Mask for all of the FP types... 197 FPTypeShift = 16, 198 FPTypeMask = 7 << FPTypeShift, 199 200 // NotFP - The default, set for instructions that do not use FP registers. 201 NotFP = 0 << FPTypeShift, 202 203 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 204 ZeroArgFP = 1 << FPTypeShift, 205 206 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 207 OneArgFP = 2 << FPTypeShift, 208 209 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 210 // result back to ST(0). For example, fcos, fsqrt, etc. 211 // 212 OneArgFPRW = 3 << FPTypeShift, 213 214 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 215 // explicit argument, storing the result to either ST(0) or the implicit 216 // argument. For example: fadd, fsub, fmul, etc... 217 TwoArgFP = 4 << FPTypeShift, 218 219 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 220 // explicit argument, but have no destination. Example: fucom, fucomi, ... 221 CompareFP = 5 << FPTypeShift, 222 223 // CondMovFP - "2 operand" floating point conditional move instructions. 224 CondMovFP = 6 << FPTypeShift, 225 226 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 227 SpecialFP = 7 << FPTypeShift, 228 229 // Lock prefix 230 LOCKShift = 19, 231 LOCK = 1 << LOCKShift, 232 233 // Segment override prefixes. Currently we just need ability to address 234 // stuff in gs and fs segments. 235 SegOvrShift = 20, 236 SegOvrMask = 3 << SegOvrShift, 237 FS = 1 << SegOvrShift, 238 GS = 2 << SegOvrShift, 239 240 // Bits 22 -> 23 are unused 241 OpcodeShift = 24, 242 OpcodeMask = 0xFF << OpcodeShift 243 }; 244} 245 246inline static bool isScale(const MachineOperand &MO) { 247 return MO.isImm() && 248 (MO.getImm() == 1 || MO.getImm() == 2 || 249 MO.getImm() == 4 || MO.getImm() == 8); 250} 251 252inline static bool isMem(const MachineInstr *MI, unsigned Op) { 253 if (MI->getOperand(Op).isFI()) return true; 254 return Op+4 <= MI->getNumOperands() && 255 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 256 MI->getOperand(Op+2).isReg() && 257 (MI->getOperand(Op+3).isImm() || 258 MI->getOperand(Op+3).isGlobal() || 259 MI->getOperand(Op+3).isCPI() || 260 MI->getOperand(Op+3).isJTI()); 261} 262 263class X86InstrInfo : public TargetInstrInfoImpl { 264 X86TargetMachine &TM; 265 const X86RegisterInfo RI; 266 267 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 268 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 269 /// 270 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 271 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 272 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 273 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 274 275 /// MemOp2RegOpTable - Load / store unfolding opcode map. 276 /// 277 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 278 279public: 280 explicit X86InstrInfo(X86TargetMachine &tm); 281 282 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 283 /// such, whenever a client has an instance of instruction info, it should 284 /// always be able to get register info as well (through this method). 285 /// 286 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 287 288 /// Return true if the instruction is a register to register move and return 289 /// the source and dest operands and their sub-register indices by reference. 290 virtual bool isMoveInstr(const MachineInstr &MI, 291 unsigned &SrcReg, unsigned &DstReg, 292 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 293 294 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 295 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 296 297 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; 298 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 299 unsigned DestReg, const MachineInstr *Orig) const; 300 301 bool isInvariantLoad(const MachineInstr *MI) const; 302 303 /// convertToThreeAddress - This method must be implemented by targets that 304 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 305 /// may be able to convert a two-address instruction into a true 306 /// three-address instruction on demand. This allows the X86 target (for 307 /// example) to convert ADD and SHL instructions into LEA instructions if they 308 /// would require register copies due to two-addressness. 309 /// 310 /// This method returns a null pointer if the transformation cannot be 311 /// performed, otherwise it returns the new instruction. 312 /// 313 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 314 MachineBasicBlock::iterator &MBBI, 315 LiveVariables *LV) const; 316 317 /// commuteInstruction - We have a few instructions that must be hacked on to 318 /// commute them. 319 /// 320 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 321 322 // Branch analysis. 323 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 324 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 325 MachineBasicBlock *&FBB, 326 SmallVectorImpl<MachineOperand> &Cond) const; 327 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 328 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 329 MachineBasicBlock *FBB, 330 const SmallVectorImpl<MachineOperand> &Cond) const; 331 virtual bool copyRegToReg(MachineBasicBlock &MBB, 332 MachineBasicBlock::iterator MI, 333 unsigned DestReg, unsigned SrcReg, 334 const TargetRegisterClass *DestRC, 335 const TargetRegisterClass *SrcRC) const; 336 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 337 MachineBasicBlock::iterator MI, 338 unsigned SrcReg, bool isKill, int FrameIndex, 339 const TargetRegisterClass *RC) const; 340 341 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 342 SmallVectorImpl<MachineOperand> &Addr, 343 const TargetRegisterClass *RC, 344 SmallVectorImpl<MachineInstr*> &NewMIs) const; 345 346 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 347 MachineBasicBlock::iterator MI, 348 unsigned DestReg, int FrameIndex, 349 const TargetRegisterClass *RC) const; 350 351 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 352 SmallVectorImpl<MachineOperand> &Addr, 353 const TargetRegisterClass *RC, 354 SmallVectorImpl<MachineInstr*> &NewMIs) const; 355 356 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 357 MachineBasicBlock::iterator MI, 358 const std::vector<CalleeSavedInfo> &CSI) const; 359 360 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 361 MachineBasicBlock::iterator MI, 362 const std::vector<CalleeSavedInfo> &CSI) const; 363 364 /// foldMemoryOperand - If this target supports it, fold a load or store of 365 /// the specified stack slot into the specified machine instruction for the 366 /// specified operand(s). If this is possible, the target should perform the 367 /// folding and return true, otherwise it should return false. If it folds 368 /// the instruction, it is likely that the MachineInstruction the iterator 369 /// references has been changed. 370 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 371 MachineInstr* MI, 372 const SmallVectorImpl<unsigned> &Ops, 373 int FrameIndex) const; 374 375 /// foldMemoryOperand - Same as the previous version except it allows folding 376 /// of any load and store from / to any address, not just from a specific 377 /// stack slot. 378 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 379 MachineInstr* MI, 380 const SmallVectorImpl<unsigned> &Ops, 381 MachineInstr* LoadMI) const; 382 383 /// canFoldMemoryOperand - Returns true if the specified load / store is 384 /// folding is possible. 385 virtual bool canFoldMemoryOperand(const MachineInstr*, 386 const SmallVectorImpl<unsigned> &) const; 387 388 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 389 /// a store or a load and a store into two or more instruction. If this is 390 /// possible, returns true as well as the new instructions by reference. 391 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 392 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 393 SmallVectorImpl<MachineInstr*> &NewMIs) const; 394 395 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 396 SmallVectorImpl<SDNode*> &NewNodes) const; 397 398 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 399 /// instruction after load / store are unfolded from an instruction of the 400 /// specified opcode. It returns zero if the specified unfolding is not 401 /// possible. 402 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 403 bool UnfoldLoad, bool UnfoldStore) const; 404 405 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 406 virtual 407 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 408 409 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 410 /// instruction that defines the specified register class. 411 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 412 413 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 414 // specified machine instruction. 415 // 416 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { 417 return TID->TSFlags >> X86II::OpcodeShift; 418 } 419 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 420 return getBaseOpcodeFor(&get(Opcode)); 421 } 422 423 static bool isX86_64NonExtLowByteReg(unsigned reg) { 424 return (reg == X86::SPL || reg == X86::BPL || 425 reg == X86::SIL || reg == X86::DIL); 426 } 427 428 static unsigned sizeOfImm(const TargetInstrDesc *Desc); 429 static bool isX86_64ExtendedReg(const MachineOperand &MO); 430 static unsigned determineREX(const MachineInstr &MI); 431 432 /// GetInstSize - Returns the size of the specified MachineInstr. 433 /// 434 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 435 436 /// getGlobalBaseReg - Return a virtual register initialized with the 437 /// the global base register value. Output instructions required to 438 /// initialize the register in the function entry block, if necessary. 439 /// 440 unsigned getGlobalBaseReg(MachineFunction *MF) const; 441 442private: 443 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 444 MachineInstr* MI, 445 unsigned OpNum, 446 const SmallVectorImpl<MachineOperand> &MOs) const; 447}; 448 449} // End llvm namespace 450 451#endif 452