X86InstrInfo.h revision 835acabce13993e210b7cef0020a585125f9cb1e
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21 22namespace llvm { 23 class X86RegisterInfo; 24 class X86TargetMachine; 25 26namespace X86 { 27 // X86 specific condition code. These correspond to X86_*_COND in 28 // X86InstrInfo.td. They must be kept in synch. 29 enum CondCode { 30 COND_A = 0, 31 COND_AE = 1, 32 COND_B = 2, 33 COND_BE = 3, 34 COND_E = 4, 35 COND_G = 5, 36 COND_GE = 6, 37 COND_L = 7, 38 COND_LE = 8, 39 COND_NE = 9, 40 COND_NO = 10, 41 COND_NP = 11, 42 COND_NS = 12, 43 COND_O = 13, 44 COND_P = 14, 45 COND_S = 15, 46 47 // Artificial condition codes. These are used by AnalyzeBranch 48 // to indicate a block terminated with two conditional branches to 49 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 50 // which can't be represented on x86 with a single condition. These 51 // are never used in MachineInstrs. 52 COND_NE_OR_P, 53 COND_NP_OR_E, 54 55 COND_INVALID 56 }; 57 58 // Turn condition code into conditional branch opcode. 59 unsigned GetCondBranchFromCond(CondCode CC); 60 61 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 62 /// e.g. turning COND_E to COND_NE. 63 CondCode GetOppositeBranchCondition(X86::CondCode CC); 64 65} 66 67/// X86II - This namespace holds all of the target specific flags that 68/// instruction info tracks. 69/// 70namespace X86II { 71 /// Target Operand Flag enum. 72 enum TOF { 73 //===------------------------------------------------------------------===// 74 // X86 Specific MachineOperand flags. 75 76 MO_NO_FLAG, 77 78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 79 /// relocation of: 80 /// SYMBOL_LABEL + [. - PICBASELABEL] 81 MO_GOT_ABSOLUTE_ADDRESS, 82 83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 84 /// immediate should get the value of the symbol minus the PIC base label: 85 /// SYMBOL_LABEL - PICBASELABEL 86 MO_PIC_BASE_OFFSET, 87 88 /// MO_GOT - On a symbol operand this indicates that the immediate is the 89 /// offset to the GOT entry for the symbol name from the base of the GOT. 90 /// 91 /// See the X86-64 ELF ABI supplement for more details. 92 /// SYMBOL_LABEL @GOT 93 MO_GOT, 94 95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 96 /// the offset to the location of the symbol name from the base of the GOT. 97 /// 98 /// See the X86-64 ELF ABI supplement for more details. 99 /// SYMBOL_LABEL @GOTOFF 100 MO_GOTOFF, 101 102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 103 /// offset to the GOT entry for the symbol name from the current code 104 /// location. 105 /// 106 /// See the X86-64 ELF ABI supplement for more details. 107 /// SYMBOL_LABEL @GOTPCREL 108 MO_GOTPCREL, 109 110 /// MO_PLT - On a symbol operand this indicates that the immediate is 111 /// offset to the PLT entry of symbol name from the current code location. 112 /// 113 /// See the X86-64 ELF ABI supplement for more details. 114 /// SYMBOL_LABEL @PLT 115 MO_PLT, 116 117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 118 /// some TLS offset. 119 /// 120 /// See 'ELF Handling for Thread-Local Storage' for more details. 121 /// SYMBOL_LABEL @TLSGD 122 MO_TLSGD, 123 124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 125 /// some TLS offset. 126 /// 127 /// See 'ELF Handling for Thread-Local Storage' for more details. 128 /// SYMBOL_LABEL @GOTTPOFF 129 MO_GOTTPOFF, 130 131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 132 /// some TLS offset. 133 /// 134 /// See 'ELF Handling for Thread-Local Storage' for more details. 135 /// SYMBOL_LABEL @INDNTPOFF 136 MO_INDNTPOFF, 137 138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 139 /// some TLS offset. 140 /// 141 /// See 'ELF Handling for Thread-Local Storage' for more details. 142 /// SYMBOL_LABEL @TPOFF 143 MO_TPOFF, 144 145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 146 /// some TLS offset. 147 /// 148 /// See 'ELF Handling for Thread-Local Storage' for more details. 149 /// SYMBOL_LABEL @NTPOFF 150 MO_NTPOFF, 151 152 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 153 /// reference is actually to the "__imp_FOO" symbol. This is used for 154 /// dllimport linkage on windows. 155 MO_DLLIMPORT, 156 157 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 158 /// reference is actually to the "FOO$stub" symbol. This is used for calls 159 /// and jumps to external functions on Tiger and before. 160 MO_DARWIN_STUB, 161 162 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 163 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 164 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 165 MO_DARWIN_NONLAZY, 166 167 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 168 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 169 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 170 MO_DARWIN_NONLAZY_PIC_BASE, 171 172 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 173 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 174 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 175 /// stub. 176 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE 177 }; 178} 179 180/// isGlobalStubReference - Return true if the specified TargetFlag operand is 181/// a reference to a stub for a global, not the global itself. 182inline static bool isGlobalStubReference(unsigned char TargetFlag) { 183 switch (TargetFlag) { 184 case X86II::MO_DLLIMPORT: // dllimport stub. 185 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 186 case X86II::MO_GOT: // normal GOT reference. 187 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 188 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 189 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 190 return true; 191 default: 192 return false; 193 } 194} 195 196/// isGlobalRelativeToPICBase - Return true if the specified global value 197/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 198/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 199inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 200 switch (TargetFlag) { 201 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 202 case X86II::MO_GOT: // isPICStyleGOT: other global. 203 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 204 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 205 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 206 return true; 207 default: 208 return false; 209 } 210} 211 212/// X86II - This namespace holds all of the target specific flags that 213/// instruction info tracks. 214/// 215namespace X86II { 216 enum { 217 //===------------------------------------------------------------------===// 218 // Instruction encodings. These are the standard/most common forms for X86 219 // instructions. 220 // 221 222 // PseudoFrm - This represents an instruction that is a pseudo instruction 223 // or one that has not been implemented yet. It is illegal to code generate 224 // it, but tolerated for intermediate implementation stages. 225 Pseudo = 0, 226 227 /// Raw - This form is for instructions that don't have any operands, so 228 /// they are just a fixed opcode value, like 'leave'. 229 RawFrm = 1, 230 231 /// AddRegFrm - This form is used for instructions like 'push r32' that have 232 /// their one register operand added to their opcode. 233 AddRegFrm = 2, 234 235 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 236 /// to specify a destination, which in this case is a register. 237 /// 238 MRMDestReg = 3, 239 240 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 241 /// to specify a destination, which in this case is memory. 242 /// 243 MRMDestMem = 4, 244 245 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 246 /// to specify a source, which in this case is a register. 247 /// 248 MRMSrcReg = 5, 249 250 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 251 /// to specify a source, which in this case is memory. 252 /// 253 MRMSrcMem = 6, 254 255 /// MRM[0-7][rm] - These forms are used to represent instructions that use 256 /// a Mod/RM byte, and use the middle field to hold extended opcode 257 /// information. In the intel manual these are represented as /0, /1, ... 258 /// 259 260 // First, instructions that operate on a register r/m operand... 261 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 262 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 263 264 // Next, instructions that operate on a memory r/m operand... 265 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 266 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 267 268 // MRMInitReg - This form is used for instructions whose source and 269 // destinations are the same register. 270 MRMInitReg = 32, 271 272 //// MRM_C1 - A mod/rm byte of exactly 0xC1. 273 MRM_C1 = 33, 274 MRM_C8 = 34, 275 MRM_C9 = 35, 276 MRM_E8 = 36, 277 MRM_F0 = 37, 278 279 FormMask = 63, 280 281 //===------------------------------------------------------------------===// 282 // Actual flags... 283 284 // OpSize - Set if this instruction requires an operand size prefix (0x66), 285 // which most often indicates that the instruction operates on 16 bit data 286 // instead of 32 bit data. 287 OpSize = 1 << 6, 288 289 // AsSize - Set if this instruction requires an operand size prefix (0x67), 290 // which most often indicates that the instruction address 16 bit address 291 // instead of 32 bit address (or 32 bit address in 64 bit mode). 292 AdSize = 1 << 7, 293 294 //===------------------------------------------------------------------===// 295 // Op0Mask - There are several prefix bytes that are used to form two byte 296 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 297 // used to obtain the setting of this field. If no bits in this field is 298 // set, there is no prefix byte for obtaining a multibyte opcode. 299 // 300 Op0Shift = 8, 301 Op0Mask = 0xF << Op0Shift, 302 303 // TB - TwoByte - Set if this instruction has a two byte opcode, which 304 // starts with a 0x0F byte before the real opcode. 305 TB = 1 << Op0Shift, 306 307 // REP - The 0xF3 prefix byte indicating repetition of the following 308 // instruction. 309 REP = 2 << Op0Shift, 310 311 // D8-DF - These escape opcodes are used by the floating point unit. These 312 // values must remain sequential. 313 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 314 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 315 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 316 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 317 318 // XS, XD - These prefix codes are for single and double precision scalar 319 // floating point operations performed in the SSE registers. 320 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 321 322 // T8, TA - Prefix after the 0x0F prefix. 323 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 324 325 // TF - Prefix before and after 0x0F 326 TF = 15 << Op0Shift, 327 328 //===------------------------------------------------------------------===// 329 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 330 // They are used to specify GPRs and SSE registers, 64-bit operand size, 331 // etc. We only cares about REX.W and REX.R bits and only the former is 332 // statically determined. 333 // 334 REXShift = 12, 335 REX_W = 1 << REXShift, 336 337 //===------------------------------------------------------------------===// 338 // This three-bit field describes the size of an immediate operand. Zero is 339 // unused so that we can tell if we forgot to set a value. 340 ImmShift = 13, 341 ImmMask = 7 << ImmShift, 342 Imm8 = 1 << ImmShift, 343 Imm8PCRel = 2 << ImmShift, 344 Imm16 = 3 << ImmShift, 345 Imm32 = 4 << ImmShift, 346 Imm32PCRel = 5 << ImmShift, 347 Imm64 = 6 << ImmShift, 348 349 //===------------------------------------------------------------------===// 350 // FP Instruction Classification... Zero is non-fp instruction. 351 352 // FPTypeMask - Mask for all of the FP types... 353 FPTypeShift = 16, 354 FPTypeMask = 7 << FPTypeShift, 355 356 // NotFP - The default, set for instructions that do not use FP registers. 357 NotFP = 0 << FPTypeShift, 358 359 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 360 ZeroArgFP = 1 << FPTypeShift, 361 362 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 363 OneArgFP = 2 << FPTypeShift, 364 365 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 366 // result back to ST(0). For example, fcos, fsqrt, etc. 367 // 368 OneArgFPRW = 3 << FPTypeShift, 369 370 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 371 // explicit argument, storing the result to either ST(0) or the implicit 372 // argument. For example: fadd, fsub, fmul, etc... 373 TwoArgFP = 4 << FPTypeShift, 374 375 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 376 // explicit argument, but have no destination. Example: fucom, fucomi, ... 377 CompareFP = 5 << FPTypeShift, 378 379 // CondMovFP - "2 operand" floating point conditional move instructions. 380 CondMovFP = 6 << FPTypeShift, 381 382 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 383 SpecialFP = 7 << FPTypeShift, 384 385 // Lock prefix 386 LOCKShift = 19, 387 LOCK = 1 << LOCKShift, 388 389 // Segment override prefixes. Currently we just need ability to address 390 // stuff in gs and fs segments. 391 SegOvrShift = 20, 392 SegOvrMask = 3 << SegOvrShift, 393 FS = 1 << SegOvrShift, 394 GS = 2 << SegOvrShift, 395 396 // Bits 22 -> 23 are unused 397 OpcodeShift = 24, 398 OpcodeMask = 0xFF << OpcodeShift 399 }; 400 401 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 402 // specified machine instruction. 403 // 404 static inline unsigned char getBaseOpcodeFor(unsigned TSFlags) { 405 return TSFlags >> X86II::OpcodeShift; 406 } 407 408 static inline bool hasImm(unsigned TSFlags) { 409 return (TSFlags & X86II::ImmMask) != 0; 410 } 411 412 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 413 /// of the specified instruction. 414 static inline unsigned getSizeOfImm(unsigned TSFlags) { 415 switch (TSFlags & X86II::ImmMask) { 416 default: assert(0 && "Unknown immediate size"); 417 case X86II::Imm8: 418 case X86II::Imm8PCRel: return 1; 419 case X86II::Imm16: return 2; 420 case X86II::Imm32: 421 case X86II::Imm32PCRel: return 4; 422 case X86II::Imm64: return 8; 423 } 424 } 425 426 /// isImmPCRel - Return true if the immediate of the specified instruction's 427 /// TSFlags indicates that it is pc relative. 428 static inline unsigned isImmPCRel(unsigned TSFlags) { 429 switch (TSFlags & X86II::ImmMask) { 430 default: assert(0 && "Unknown immediate size"); 431 case X86II::Imm8PCRel: 432 case X86II::Imm32PCRel: 433 return true; 434 case X86II::Imm8: 435 case X86II::Imm16: 436 case X86II::Imm32: 437 case X86II::Imm64: 438 return false; 439 } 440 } 441} 442 443const int X86AddrNumOperands = 5; 444 445inline static bool isScale(const MachineOperand &MO) { 446 return MO.isImm() && 447 (MO.getImm() == 1 || MO.getImm() == 2 || 448 MO.getImm() == 4 || MO.getImm() == 8); 449} 450 451inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 452 if (MI->getOperand(Op).isFI()) return true; 453 return Op+4 <= MI->getNumOperands() && 454 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 455 MI->getOperand(Op+2).isReg() && 456 (MI->getOperand(Op+3).isImm() || 457 MI->getOperand(Op+3).isGlobal() || 458 MI->getOperand(Op+3).isCPI() || 459 MI->getOperand(Op+3).isJTI()); 460} 461 462inline static bool isMem(const MachineInstr *MI, unsigned Op) { 463 if (MI->getOperand(Op).isFI()) return true; 464 return Op+5 <= MI->getNumOperands() && 465 MI->getOperand(Op+4).isReg() && 466 isLeaMem(MI, Op); 467} 468 469class X86InstrInfo : public TargetInstrInfoImpl { 470 X86TargetMachine &TM; 471 const X86RegisterInfo RI; 472 473 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 474 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 475 /// 476 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 477 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 478 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 479 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 480 481 /// MemOp2RegOpTable - Load / store unfolding opcode map. 482 /// 483 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 484 485public: 486 explicit X86InstrInfo(X86TargetMachine &tm); 487 488 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 489 /// such, whenever a client has an instance of instruction info, it should 490 /// always be able to get register info as well (through this method). 491 /// 492 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 493 494 /// Return true if the instruction is a register to register move and return 495 /// the source and dest operands and their sub-register indices by reference. 496 virtual bool isMoveInstr(const MachineInstr &MI, 497 unsigned &SrcReg, unsigned &DstReg, 498 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 499 500 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 501 /// extension instruction. That is, it's like a copy where it's legal for the 502 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 503 /// true, then it's expected the pre-extension value is available as a subreg 504 /// of the result register. This also returns the sub-register index in 505 /// SubIdx. 506 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 507 unsigned &SrcReg, unsigned &DstReg, 508 unsigned &SubIdx) const; 509 510 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 511 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 512 /// stack locations as well. This uses a heuristic so it isn't 513 /// reliable for correctness. 514 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 515 int &FrameIndex) const; 516 517 /// hasLoadFromStackSlot - If the specified machine instruction has 518 /// a load from a stack slot, return true along with the FrameIndex 519 /// of the loaded stack slot and the machine mem operand containing 520 /// the reference. If not, return false. Unlike 521 /// isLoadFromStackSlot, this returns true for any instructions that 522 /// loads from the stack. This is a hint only and may not catch all 523 /// cases. 524 bool hasLoadFromStackSlot(const MachineInstr *MI, 525 const MachineMemOperand *&MMO, 526 int &FrameIndex) const; 527 528 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 529 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 530 /// stack locations as well. This uses a heuristic so it isn't 531 /// reliable for correctness. 532 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 533 int &FrameIndex) const; 534 535 /// hasStoreToStackSlot - If the specified machine instruction has a 536 /// store to a stack slot, return true along with the FrameIndex of 537 /// the loaded stack slot and the machine mem operand containing the 538 /// reference. If not, return false. Unlike isStoreToStackSlot, 539 /// this returns true for any instructions that loads from the 540 /// stack. This is a hint only and may not catch all cases. 541 bool hasStoreToStackSlot(const MachineInstr *MI, 542 const MachineMemOperand *&MMO, 543 int &FrameIndex) const; 544 545 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 546 AliasAnalysis *AA) const; 547 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 548 unsigned DestReg, unsigned SubIdx, 549 const MachineInstr *Orig, 550 const TargetRegisterInfo *TRI) const; 551 552 /// convertToThreeAddress - This method must be implemented by targets that 553 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 554 /// may be able to convert a two-address instruction into a true 555 /// three-address instruction on demand. This allows the X86 target (for 556 /// example) to convert ADD and SHL instructions into LEA instructions if they 557 /// would require register copies due to two-addressness. 558 /// 559 /// This method returns a null pointer if the transformation cannot be 560 /// performed, otherwise it returns the new instruction. 561 /// 562 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 563 MachineBasicBlock::iterator &MBBI, 564 LiveVariables *LV) const; 565 566 /// commuteInstruction - We have a few instructions that must be hacked on to 567 /// commute them. 568 /// 569 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 570 571 // Branch analysis. 572 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 573 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 574 MachineBasicBlock *&FBB, 575 SmallVectorImpl<MachineOperand> &Cond, 576 bool AllowModify) const; 577 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 578 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 579 MachineBasicBlock *FBB, 580 const SmallVectorImpl<MachineOperand> &Cond) const; 581 virtual bool copyRegToReg(MachineBasicBlock &MBB, 582 MachineBasicBlock::iterator MI, 583 unsigned DestReg, unsigned SrcReg, 584 const TargetRegisterClass *DestRC, 585 const TargetRegisterClass *SrcRC) const; 586 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 587 MachineBasicBlock::iterator MI, 588 unsigned SrcReg, bool isKill, int FrameIndex, 589 const TargetRegisterClass *RC) const; 590 591 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 592 SmallVectorImpl<MachineOperand> &Addr, 593 const TargetRegisterClass *RC, 594 MachineInstr::mmo_iterator MMOBegin, 595 MachineInstr::mmo_iterator MMOEnd, 596 SmallVectorImpl<MachineInstr*> &NewMIs) const; 597 598 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 599 MachineBasicBlock::iterator MI, 600 unsigned DestReg, int FrameIndex, 601 const TargetRegisterClass *RC) const; 602 603 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 604 SmallVectorImpl<MachineOperand> &Addr, 605 const TargetRegisterClass *RC, 606 MachineInstr::mmo_iterator MMOBegin, 607 MachineInstr::mmo_iterator MMOEnd, 608 SmallVectorImpl<MachineInstr*> &NewMIs) const; 609 610 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 611 MachineBasicBlock::iterator MI, 612 const std::vector<CalleeSavedInfo> &CSI) const; 613 614 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 615 MachineBasicBlock::iterator MI, 616 const std::vector<CalleeSavedInfo> &CSI) const; 617 618 /// foldMemoryOperand - If this target supports it, fold a load or store of 619 /// the specified stack slot into the specified machine instruction for the 620 /// specified operand(s). If this is possible, the target should perform the 621 /// folding and return true, otherwise it should return false. If it folds 622 /// the instruction, it is likely that the MachineInstruction the iterator 623 /// references has been changed. 624 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 625 MachineInstr* MI, 626 const SmallVectorImpl<unsigned> &Ops, 627 int FrameIndex) const; 628 629 /// foldMemoryOperand - Same as the previous version except it allows folding 630 /// of any load and store from / to any address, not just from a specific 631 /// stack slot. 632 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 633 MachineInstr* MI, 634 const SmallVectorImpl<unsigned> &Ops, 635 MachineInstr* LoadMI) const; 636 637 /// canFoldMemoryOperand - Returns true if the specified load / store is 638 /// folding is possible. 639 virtual bool canFoldMemoryOperand(const MachineInstr*, 640 const SmallVectorImpl<unsigned> &) const; 641 642 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 643 /// a store or a load and a store into two or more instruction. If this is 644 /// possible, returns true as well as the new instructions by reference. 645 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 646 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 647 SmallVectorImpl<MachineInstr*> &NewMIs) const; 648 649 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 650 SmallVectorImpl<SDNode*> &NewNodes) const; 651 652 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 653 /// instruction after load / store are unfolded from an instruction of the 654 /// specified opcode. It returns zero if the specified unfolding is not 655 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 656 /// index of the operand which will hold the register holding the loaded 657 /// value. 658 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 659 bool UnfoldLoad, bool UnfoldStore, 660 unsigned *LoadRegIndex = 0) const; 661 662 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 663 /// to determine if two loads are loading from the same base address. It 664 /// should only return true if the base pointers are the same and the 665 /// only differences between the two addresses are the offset. It also returns 666 /// the offsets by reference. 667 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 668 int64_t &Offset1, int64_t &Offset2) const; 669 670 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 671 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 672 /// be scheduled togther. On some targets if two loads are loading from 673 /// addresses in the same cache line, it's better if they are scheduled 674 /// together. This function takes two integers that represent the load offsets 675 /// from the common base address. It returns true if it decides it's desirable 676 /// to schedule the two loads together. "NumLoads" is the number of loads that 677 /// have already been scheduled after Load1. 678 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 679 int64_t Offset1, int64_t Offset2, 680 unsigned NumLoads) const; 681 682 virtual 683 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 684 685 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 686 /// instruction that defines the specified register class. 687 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 688 689 static bool isX86_64NonExtLowByteReg(unsigned reg) { 690 return (reg == X86::SPL || reg == X86::BPL || 691 reg == X86::SIL || reg == X86::DIL); 692 } 693 694 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 695 if (!MO.isReg()) return false; 696 return isX86_64ExtendedReg(MO.getReg()); 697 } 698 static unsigned determineREX(const MachineInstr &MI); 699 700 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 701 /// higher) register? e.g. r8, xmm8, xmm13, etc. 702 static bool isX86_64ExtendedReg(unsigned RegNo); 703 704 /// GetInstSize - Returns the size of the specified MachineInstr. 705 /// 706 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 707 708 /// getGlobalBaseReg - Return a virtual register initialized with the 709 /// the global base register value. Output instructions required to 710 /// initialize the register in the function entry block, if necessary. 711 /// 712 unsigned getGlobalBaseReg(MachineFunction *MF) const; 713 714private: 715 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 716 MachineFunction::iterator &MFI, 717 MachineBasicBlock::iterator &MBBI, 718 LiveVariables *LV) const; 719 720 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 721 MachineInstr* MI, 722 unsigned OpNum, 723 const SmallVectorImpl<MachineOperand> &MOs, 724 unsigned Size, unsigned Alignment) const; 725 726 /// isFrameOperand - Return true and the FrameIndex if the specified 727 /// operand and follow operands form a reference to the stack frame. 728 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 729 int &FrameIndex) const; 730}; 731 732} // End llvm namespace 733 734#endif 735