X86InstrInfo.h revision 962021bc7f6721c20c7dfe8ca809e2d98b1c554a
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21 22namespace llvm { 23 class X86RegisterInfo; 24 class X86TargetMachine; 25 26namespace X86 { 27 // X86 specific condition code. These correspond to X86_*_COND in 28 // X86InstrInfo.td. They must be kept in synch. 29 enum CondCode { 30 COND_A = 0, 31 COND_AE = 1, 32 COND_B = 2, 33 COND_BE = 3, 34 COND_E = 4, 35 COND_G = 5, 36 COND_GE = 6, 37 COND_L = 7, 38 COND_LE = 8, 39 COND_NE = 9, 40 COND_NO = 10, 41 COND_NP = 11, 42 COND_NS = 12, 43 COND_O = 13, 44 COND_P = 14, 45 COND_S = 15, 46 47 // Artificial condition codes. These are used by AnalyzeBranch 48 // to indicate a block terminated with two conditional branches to 49 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 50 // which can't be represented on x86 with a single condition. These 51 // are never used in MachineInstrs. 52 COND_NE_OR_P, 53 COND_NP_OR_E, 54 55 COND_INVALID 56 }; 57 58 // Turn condition code into conditional branch opcode. 59 unsigned GetCondBranchFromCond(CondCode CC); 60 61 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 62 /// e.g. turning COND_E to COND_NE. 63 CondCode GetOppositeBranchCondition(X86::CondCode CC); 64 65} 66 67/// X86II - This namespace holds all of the target specific flags that 68/// instruction info tracks. 69/// 70namespace X86II { 71 /// Target Operand Flag enum. 72 enum TOF { 73 //===------------------------------------------------------------------===// 74 // X86 Specific MachineOperand flags. 75 76 MO_NO_FLAG, 77 78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 79 /// relocation of: 80 /// SYMBOL_LABEL + [. - PICBASELABEL] 81 MO_GOT_ABSOLUTE_ADDRESS, 82 83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 84 /// immediate should get the value of the symbol minus the PIC base label: 85 /// SYMBOL_LABEL - PICBASELABEL 86 MO_PIC_BASE_OFFSET, 87 88 /// MO_GOT - On a symbol operand this indicates that the immediate is the 89 /// offset to the GOT entry for the symbol name from the base of the GOT. 90 /// 91 /// See the X86-64 ELF ABI supplement for more details. 92 /// SYMBOL_LABEL @GOT 93 MO_GOT, 94 95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 96 /// the offset to the location of the symbol name from the base of the GOT. 97 /// 98 /// See the X86-64 ELF ABI supplement for more details. 99 /// SYMBOL_LABEL @GOTOFF 100 MO_GOTOFF, 101 102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 103 /// offset to the GOT entry for the symbol name from the current code 104 /// location. 105 /// 106 /// See the X86-64 ELF ABI supplement for more details. 107 /// SYMBOL_LABEL @GOTPCREL 108 MO_GOTPCREL, 109 110 /// MO_PLT - On a symbol operand this indicates that the immediate is 111 /// offset to the PLT entry of symbol name from the current code location. 112 /// 113 /// See the X86-64 ELF ABI supplement for more details. 114 /// SYMBOL_LABEL @PLT 115 MO_PLT, 116 117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 118 /// some TLS offset. 119 /// 120 /// See 'ELF Handling for Thread-Local Storage' for more details. 121 /// SYMBOL_LABEL @TLSGD 122 MO_TLSGD, 123 124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 125 /// some TLS offset. 126 /// 127 /// See 'ELF Handling for Thread-Local Storage' for more details. 128 /// SYMBOL_LABEL @GOTTPOFF 129 MO_GOTTPOFF, 130 131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 132 /// some TLS offset. 133 /// 134 /// See 'ELF Handling for Thread-Local Storage' for more details. 135 /// SYMBOL_LABEL @INDNTPOFF 136 MO_INDNTPOFF, 137 138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 139 /// some TLS offset. 140 /// 141 /// See 'ELF Handling for Thread-Local Storage' for more details. 142 /// SYMBOL_LABEL @TPOFF 143 MO_TPOFF, 144 145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 146 /// some TLS offset. 147 /// 148 /// See 'ELF Handling for Thread-Local Storage' for more details. 149 /// SYMBOL_LABEL @NTPOFF 150 MO_NTPOFF, 151 152 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 153 /// reference is actually to the "__imp_FOO" symbol. This is used for 154 /// dllimport linkage on windows. 155 MO_DLLIMPORT, 156 157 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 158 /// reference is actually to the "FOO$stub" symbol. This is used for calls 159 /// and jumps to external functions on Tiger and before. 160 MO_DARWIN_STUB, 161 162 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 163 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 164 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 165 MO_DARWIN_NONLAZY, 166 167 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 168 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 169 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 170 MO_DARWIN_NONLAZY_PIC_BASE, 171 172 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 173 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 174 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 175 /// stub. 176 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE 177 }; 178} 179 180/// isGlobalStubReference - Return true if the specified TargetFlag operand is 181/// a reference to a stub for a global, not the global itself. 182inline static bool isGlobalStubReference(unsigned char TargetFlag) { 183 switch (TargetFlag) { 184 case X86II::MO_DLLIMPORT: // dllimport stub. 185 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 186 case X86II::MO_GOT: // normal GOT reference. 187 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 188 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 189 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 190 return true; 191 default: 192 return false; 193 } 194} 195 196/// isGlobalRelativeToPICBase - Return true if the specified global value 197/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 198/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 199inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 200 switch (TargetFlag) { 201 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 202 case X86II::MO_GOT: // isPICStyleGOT: other global. 203 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 204 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 205 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 206 return true; 207 default: 208 return false; 209 } 210} 211 212/// X86II - This namespace holds all of the target specific flags that 213/// instruction info tracks. 214/// 215namespace X86II { 216 enum { 217 //===------------------------------------------------------------------===// 218 // Instruction encodings. These are the standard/most common forms for X86 219 // instructions. 220 // 221 222 // PseudoFrm - This represents an instruction that is a pseudo instruction 223 // or one that has not been implemented yet. It is illegal to code generate 224 // it, but tolerated for intermediate implementation stages. 225 Pseudo = 0, 226 227 /// Raw - This form is for instructions that don't have any operands, so 228 /// they are just a fixed opcode value, like 'leave'. 229 RawFrm = 1, 230 231 /// AddRegFrm - This form is used for instructions like 'push r32' that have 232 /// their one register operand added to their opcode. 233 AddRegFrm = 2, 234 235 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 236 /// to specify a destination, which in this case is a register. 237 /// 238 MRMDestReg = 3, 239 240 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 241 /// to specify a destination, which in this case is memory. 242 /// 243 MRMDestMem = 4, 244 245 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 246 /// to specify a source, which in this case is a register. 247 /// 248 MRMSrcReg = 5, 249 250 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 251 /// to specify a source, which in this case is memory. 252 /// 253 MRMSrcMem = 6, 254 255 /// MRM[0-7][rm] - These forms are used to represent instructions that use 256 /// a Mod/RM byte, and use the middle field to hold extended opcode 257 /// information. In the intel manual these are represented as /0, /1, ... 258 /// 259 260 // First, instructions that operate on a register r/m operand... 261 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 262 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 263 264 // Next, instructions that operate on a memory r/m operand... 265 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 266 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 267 268 // MRMInitReg - This form is used for instructions whose source and 269 // destinations are the same register. 270 MRMInitReg = 32, 271 272 //// MRM_C1 - A mod/rm byte of exactly 0xC1. 273 MRM_C1 = 33, 274 MRM_C2 = 34, 275 MRM_C3 = 35, 276 MRM_C4 = 36, 277 MRM_C8 = 37, 278 MRM_C9 = 38, 279 MRM_E8 = 39, 280 MRM_F0 = 40, 281 MRM_F8 = 41, 282 MRM_F9 = 42, 283 284 FormMask = 63, 285 286 //===------------------------------------------------------------------===// 287 // Actual flags... 288 289 // OpSize - Set if this instruction requires an operand size prefix (0x66), 290 // which most often indicates that the instruction operates on 16 bit data 291 // instead of 32 bit data. 292 OpSize = 1 << 6, 293 294 // AsSize - Set if this instruction requires an operand size prefix (0x67), 295 // which most often indicates that the instruction address 16 bit address 296 // instead of 32 bit address (or 32 bit address in 64 bit mode). 297 AdSize = 1 << 7, 298 299 //===------------------------------------------------------------------===// 300 // Op0Mask - There are several prefix bytes that are used to form two byte 301 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 302 // used to obtain the setting of this field. If no bits in this field is 303 // set, there is no prefix byte for obtaining a multibyte opcode. 304 // 305 Op0Shift = 8, 306 Op0Mask = 0xF << Op0Shift, 307 308 // TB - TwoByte - Set if this instruction has a two byte opcode, which 309 // starts with a 0x0F byte before the real opcode. 310 TB = 1 << Op0Shift, 311 312 // REP - The 0xF3 prefix byte indicating repetition of the following 313 // instruction. 314 REP = 2 << Op0Shift, 315 316 // D8-DF - These escape opcodes are used by the floating point unit. These 317 // values must remain sequential. 318 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 319 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 320 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 321 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 322 323 // XS, XD - These prefix codes are for single and double precision scalar 324 // floating point operations performed in the SSE registers. 325 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 326 327 // T8, TA - Prefix after the 0x0F prefix. 328 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 329 330 // TF - Prefix before and after 0x0F 331 TF = 15 << Op0Shift, 332 333 //===------------------------------------------------------------------===// 334 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 335 // They are used to specify GPRs and SSE registers, 64-bit operand size, 336 // etc. We only cares about REX.W and REX.R bits and only the former is 337 // statically determined. 338 // 339 REXShift = 12, 340 REX_W = 1 << REXShift, 341 342 //===------------------------------------------------------------------===// 343 // This three-bit field describes the size of an immediate operand. Zero is 344 // unused so that we can tell if we forgot to set a value. 345 ImmShift = 13, 346 ImmMask = 7 << ImmShift, 347 Imm8 = 1 << ImmShift, 348 Imm8PCRel = 2 << ImmShift, 349 Imm16 = 3 << ImmShift, 350 Imm32 = 4 << ImmShift, 351 Imm32PCRel = 5 << ImmShift, 352 Imm64 = 6 << ImmShift, 353 354 //===------------------------------------------------------------------===// 355 // FP Instruction Classification... Zero is non-fp instruction. 356 357 // FPTypeMask - Mask for all of the FP types... 358 FPTypeShift = 16, 359 FPTypeMask = 7 << FPTypeShift, 360 361 // NotFP - The default, set for instructions that do not use FP registers. 362 NotFP = 0 << FPTypeShift, 363 364 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 365 ZeroArgFP = 1 << FPTypeShift, 366 367 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 368 OneArgFP = 2 << FPTypeShift, 369 370 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 371 // result back to ST(0). For example, fcos, fsqrt, etc. 372 // 373 OneArgFPRW = 3 << FPTypeShift, 374 375 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 376 // explicit argument, storing the result to either ST(0) or the implicit 377 // argument. For example: fadd, fsub, fmul, etc... 378 TwoArgFP = 4 << FPTypeShift, 379 380 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 381 // explicit argument, but have no destination. Example: fucom, fucomi, ... 382 CompareFP = 5 << FPTypeShift, 383 384 // CondMovFP - "2 operand" floating point conditional move instructions. 385 CondMovFP = 6 << FPTypeShift, 386 387 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 388 SpecialFP = 7 << FPTypeShift, 389 390 // Lock prefix 391 LOCKShift = 19, 392 LOCK = 1 << LOCKShift, 393 394 // Segment override prefixes. Currently we just need ability to address 395 // stuff in gs and fs segments. 396 SegOvrShift = 20, 397 SegOvrMask = 3 << SegOvrShift, 398 FS = 1 << SegOvrShift, 399 GS = 2 << SegOvrShift, 400 401 // Execution domain for SSE instructions in bits 22, 23. 402 // 0 in bits 22-23 means normal, non-SSE instruction. 403 SSEDomainShift = 22, 404 405 OpcodeShift = 24, 406 OpcodeMask = 0xFF << OpcodeShift 407 }; 408 409 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 410 // specified machine instruction. 411 // 412 static inline unsigned char getBaseOpcodeFor(unsigned TSFlags) { 413 return TSFlags >> X86II::OpcodeShift; 414 } 415 416 static inline bool hasImm(unsigned TSFlags) { 417 return (TSFlags & X86II::ImmMask) != 0; 418 } 419 420 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 421 /// of the specified instruction. 422 static inline unsigned getSizeOfImm(unsigned TSFlags) { 423 switch (TSFlags & X86II::ImmMask) { 424 default: assert(0 && "Unknown immediate size"); 425 case X86II::Imm8: 426 case X86II::Imm8PCRel: return 1; 427 case X86II::Imm16: return 2; 428 case X86II::Imm32: 429 case X86II::Imm32PCRel: return 4; 430 case X86II::Imm64: return 8; 431 } 432 } 433 434 /// isImmPCRel - Return true if the immediate of the specified instruction's 435 /// TSFlags indicates that it is pc relative. 436 static inline unsigned isImmPCRel(unsigned TSFlags) { 437 switch (TSFlags & X86II::ImmMask) { 438 default: assert(0 && "Unknown immediate size"); 439 case X86II::Imm8PCRel: 440 case X86II::Imm32PCRel: 441 return true; 442 case X86II::Imm8: 443 case X86II::Imm16: 444 case X86II::Imm32: 445 case X86II::Imm64: 446 return false; 447 } 448 } 449} 450 451const int X86AddrNumOperands = 5; 452 453inline static bool isScale(const MachineOperand &MO) { 454 return MO.isImm() && 455 (MO.getImm() == 1 || MO.getImm() == 2 || 456 MO.getImm() == 4 || MO.getImm() == 8); 457} 458 459inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 460 if (MI->getOperand(Op).isFI()) return true; 461 return Op+4 <= MI->getNumOperands() && 462 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 463 MI->getOperand(Op+2).isReg() && 464 (MI->getOperand(Op+3).isImm() || 465 MI->getOperand(Op+3).isGlobal() || 466 MI->getOperand(Op+3).isCPI() || 467 MI->getOperand(Op+3).isJTI()); 468} 469 470inline static bool isMem(const MachineInstr *MI, unsigned Op) { 471 if (MI->getOperand(Op).isFI()) return true; 472 return Op+5 <= MI->getNumOperands() && 473 MI->getOperand(Op+4).isReg() && 474 isLeaMem(MI, Op); 475} 476 477class X86InstrInfo : public TargetInstrInfoImpl { 478 X86TargetMachine &TM; 479 const X86RegisterInfo RI; 480 481 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 482 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 483 /// 484 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 485 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 486 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 487 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 488 489 /// MemOp2RegOpTable - Load / store unfolding opcode map. 490 /// 491 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 492 493public: 494 explicit X86InstrInfo(X86TargetMachine &tm); 495 496 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 497 /// such, whenever a client has an instance of instruction info, it should 498 /// always be able to get register info as well (through this method). 499 /// 500 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 501 502 /// Return true if the instruction is a register to register move and return 503 /// the source and dest operands and their sub-register indices by reference. 504 virtual bool isMoveInstr(const MachineInstr &MI, 505 unsigned &SrcReg, unsigned &DstReg, 506 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 507 508 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 509 /// extension instruction. That is, it's like a copy where it's legal for the 510 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 511 /// true, then it's expected the pre-extension value is available as a subreg 512 /// of the result register. This also returns the sub-register index in 513 /// SubIdx. 514 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 515 unsigned &SrcReg, unsigned &DstReg, 516 unsigned &SubIdx) const; 517 518 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 519 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 520 /// stack locations as well. This uses a heuristic so it isn't 521 /// reliable for correctness. 522 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 523 int &FrameIndex) const; 524 525 /// hasLoadFromStackSlot - If the specified machine instruction has 526 /// a load from a stack slot, return true along with the FrameIndex 527 /// of the loaded stack slot and the machine mem operand containing 528 /// the reference. If not, return false. Unlike 529 /// isLoadFromStackSlot, this returns true for any instructions that 530 /// loads from the stack. This is a hint only and may not catch all 531 /// cases. 532 bool hasLoadFromStackSlot(const MachineInstr *MI, 533 const MachineMemOperand *&MMO, 534 int &FrameIndex) const; 535 536 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 537 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 538 /// stack locations as well. This uses a heuristic so it isn't 539 /// reliable for correctness. 540 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 541 int &FrameIndex) const; 542 543 /// hasStoreToStackSlot - If the specified machine instruction has a 544 /// store to a stack slot, return true along with the FrameIndex of 545 /// the loaded stack slot and the machine mem operand containing the 546 /// reference. If not, return false. Unlike isStoreToStackSlot, 547 /// this returns true for any instructions that loads from the 548 /// stack. This is a hint only and may not catch all cases. 549 bool hasStoreToStackSlot(const MachineInstr *MI, 550 const MachineMemOperand *&MMO, 551 int &FrameIndex) const; 552 553 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 554 AliasAnalysis *AA) const; 555 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 556 unsigned DestReg, unsigned SubIdx, 557 const MachineInstr *Orig, 558 const TargetRegisterInfo *TRI) const; 559 560 /// convertToThreeAddress - This method must be implemented by targets that 561 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 562 /// may be able to convert a two-address instruction into a true 563 /// three-address instruction on demand. This allows the X86 target (for 564 /// example) to convert ADD and SHL instructions into LEA instructions if they 565 /// would require register copies due to two-addressness. 566 /// 567 /// This method returns a null pointer if the transformation cannot be 568 /// performed, otherwise it returns the new instruction. 569 /// 570 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 571 MachineBasicBlock::iterator &MBBI, 572 LiveVariables *LV) const; 573 574 /// commuteInstruction - We have a few instructions that must be hacked on to 575 /// commute them. 576 /// 577 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 578 579 // Branch analysis. 580 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 581 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 582 MachineBasicBlock *&FBB, 583 SmallVectorImpl<MachineOperand> &Cond, 584 bool AllowModify) const; 585 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 586 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 587 MachineBasicBlock *FBB, 588 const SmallVectorImpl<MachineOperand> &Cond) const; 589 virtual bool copyRegToReg(MachineBasicBlock &MBB, 590 MachineBasicBlock::iterator MI, 591 unsigned DestReg, unsigned SrcReg, 592 const TargetRegisterClass *DestRC, 593 const TargetRegisterClass *SrcRC) const; 594 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 595 MachineBasicBlock::iterator MI, 596 unsigned SrcReg, bool isKill, int FrameIndex, 597 const TargetRegisterClass *RC) const; 598 599 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 600 SmallVectorImpl<MachineOperand> &Addr, 601 const TargetRegisterClass *RC, 602 MachineInstr::mmo_iterator MMOBegin, 603 MachineInstr::mmo_iterator MMOEnd, 604 SmallVectorImpl<MachineInstr*> &NewMIs) const; 605 606 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 607 MachineBasicBlock::iterator MI, 608 unsigned DestReg, int FrameIndex, 609 const TargetRegisterClass *RC) const; 610 611 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 612 SmallVectorImpl<MachineOperand> &Addr, 613 const TargetRegisterClass *RC, 614 MachineInstr::mmo_iterator MMOBegin, 615 MachineInstr::mmo_iterator MMOEnd, 616 SmallVectorImpl<MachineInstr*> &NewMIs) const; 617 618 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 619 MachineBasicBlock::iterator MI, 620 const std::vector<CalleeSavedInfo> &CSI) const; 621 622 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 623 MachineBasicBlock::iterator MI, 624 const std::vector<CalleeSavedInfo> &CSI) const; 625 626 virtual 627 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 628 unsigned FrameIx, uint64_t Offset, 629 const MDNode *MDPtr, 630 DebugLoc DL) const; 631 632 /// foldMemoryOperand - If this target supports it, fold a load or store of 633 /// the specified stack slot into the specified machine instruction for the 634 /// specified operand(s). If this is possible, the target should perform the 635 /// folding and return true, otherwise it should return false. If it folds 636 /// the instruction, it is likely that the MachineInstruction the iterator 637 /// references has been changed. 638 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 639 MachineInstr* MI, 640 const SmallVectorImpl<unsigned> &Ops, 641 int FrameIndex) const; 642 643 /// foldMemoryOperand - Same as the previous version except it allows folding 644 /// of any load and store from / to any address, not just from a specific 645 /// stack slot. 646 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 647 MachineInstr* MI, 648 const SmallVectorImpl<unsigned> &Ops, 649 MachineInstr* LoadMI) const; 650 651 /// canFoldMemoryOperand - Returns true if the specified load / store is 652 /// folding is possible. 653 virtual bool canFoldMemoryOperand(const MachineInstr*, 654 const SmallVectorImpl<unsigned> &) const; 655 656 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 657 /// a store or a load and a store into two or more instruction. If this is 658 /// possible, returns true as well as the new instructions by reference. 659 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 660 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 661 SmallVectorImpl<MachineInstr*> &NewMIs) const; 662 663 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 664 SmallVectorImpl<SDNode*> &NewNodes) const; 665 666 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 667 /// instruction after load / store are unfolded from an instruction of the 668 /// specified opcode. It returns zero if the specified unfolding is not 669 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 670 /// index of the operand which will hold the register holding the loaded 671 /// value. 672 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 673 bool UnfoldLoad, bool UnfoldStore, 674 unsigned *LoadRegIndex = 0) const; 675 676 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 677 /// to determine if two loads are loading from the same base address. It 678 /// should only return true if the base pointers are the same and the 679 /// only differences between the two addresses are the offset. It also returns 680 /// the offsets by reference. 681 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 682 int64_t &Offset1, int64_t &Offset2) const; 683 684 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 685 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 686 /// be scheduled togther. On some targets if two loads are loading from 687 /// addresses in the same cache line, it's better if they are scheduled 688 /// together. This function takes two integers that represent the load offsets 689 /// from the common base address. It returns true if it decides it's desirable 690 /// to schedule the two loads together. "NumLoads" is the number of loads that 691 /// have already been scheduled after Load1. 692 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 693 int64_t Offset1, int64_t Offset2, 694 unsigned NumLoads) const; 695 696 virtual 697 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 698 699 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 700 /// instruction that defines the specified register class. 701 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 702 703 static bool isX86_64NonExtLowByteReg(unsigned reg) { 704 return (reg == X86::SPL || reg == X86::BPL || 705 reg == X86::SIL || reg == X86::DIL); 706 } 707 708 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 709 if (!MO.isReg()) return false; 710 return isX86_64ExtendedReg(MO.getReg()); 711 } 712 static unsigned determineREX(const MachineInstr &MI); 713 714 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 715 /// higher) register? e.g. r8, xmm8, xmm13, etc. 716 static bool isX86_64ExtendedReg(unsigned RegNo); 717 718 /// GetInstSize - Returns the size of the specified MachineInstr. 719 /// 720 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 721 722 /// getGlobalBaseReg - Return a virtual register initialized with the 723 /// the global base register value. Output instructions required to 724 /// initialize the register in the function entry block, if necessary. 725 /// 726 unsigned getGlobalBaseReg(MachineFunction *MF) const; 727 728 /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 729 /// and a bitmask of possible arguments to SetSSEDomain ase the second. 730 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const; 731 732 /// SetSSEDomain - Set the SSEDomain of MI. 733 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; 734 735private: 736 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 737 MachineFunction::iterator &MFI, 738 MachineBasicBlock::iterator &MBBI, 739 LiveVariables *LV) const; 740 741 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 742 MachineInstr* MI, 743 unsigned OpNum, 744 const SmallVectorImpl<MachineOperand> &MOs, 745 unsigned Size, unsigned Alignment) const; 746 747 /// isFrameOperand - Return true and the FrameIndex if the specified 748 /// operand and follow operands form a reference to the stack frame. 749 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 750 int &FrameIndex) const; 751}; 752 753} // End llvm namespace 754 755#endif 756