X86InstrInfo.h revision be95c15903c80b5bc340a9308d1fa334235e23e7
1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86INSTRUCTIONINFO_H 15#define X86INSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "X86.h" 19#include "X86RegisterInfo.h" 20#include "llvm/ADT/DenseMap.h" 21 22namespace llvm { 23 class X86RegisterInfo; 24 class X86TargetMachine; 25 26namespace X86 { 27 // Enums for memory operand decoding. Each memory operand is represented with 28 // a 5 operand sequence in the form: 29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 30 // These enums help decode this. 31 enum { 32 AddrBaseReg = 0, 33 AddrScaleAmt = 1, 34 AddrIndexReg = 2, 35 AddrDisp = 3, 36 37 /// AddrSegmentReg - The operand # of the segment in the memory operand. 38 AddrSegmentReg = 4, 39 40 /// AddrNumOperands - Total number of operands in a memory reference. 41 AddrNumOperands = 5 42 }; 43 44 45 // X86 specific condition code. These correspond to X86_*_COND in 46 // X86InstrInfo.td. They must be kept in synch. 47 enum CondCode { 48 COND_A = 0, 49 COND_AE = 1, 50 COND_B = 2, 51 COND_BE = 3, 52 COND_E = 4, 53 COND_G = 5, 54 COND_GE = 6, 55 COND_L = 7, 56 COND_LE = 8, 57 COND_NE = 9, 58 COND_NO = 10, 59 COND_NP = 11, 60 COND_NS = 12, 61 COND_O = 13, 62 COND_P = 14, 63 COND_S = 15, 64 65 // Artificial condition codes. These are used by AnalyzeBranch 66 // to indicate a block terminated with two conditional branches to 67 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 68 // which can't be represented on x86 with a single condition. These 69 // are never used in MachineInstrs. 70 COND_NE_OR_P, 71 COND_NP_OR_E, 72 73 COND_INVALID 74 }; 75 76 // Turn condition code into conditional branch opcode. 77 unsigned GetCondBranchFromCond(CondCode CC); 78 79 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 80 /// e.g. turning COND_E to COND_NE. 81 CondCode GetOppositeBranchCondition(X86::CondCode CC); 82 83} 84 85/// X86II - This namespace holds all of the target specific flags that 86/// instruction info tracks. 87/// 88namespace X86II { 89 /// Target Operand Flag enum. 90 enum TOF { 91 //===------------------------------------------------------------------===// 92 // X86 Specific MachineOperand flags. 93 94 MO_NO_FLAG, 95 96 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 97 /// relocation of: 98 /// SYMBOL_LABEL + [. - PICBASELABEL] 99 MO_GOT_ABSOLUTE_ADDRESS, 100 101 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 102 /// immediate should get the value of the symbol minus the PIC base label: 103 /// SYMBOL_LABEL - PICBASELABEL 104 MO_PIC_BASE_OFFSET, 105 106 /// MO_GOT - On a symbol operand this indicates that the immediate is the 107 /// offset to the GOT entry for the symbol name from the base of the GOT. 108 /// 109 /// See the X86-64 ELF ABI supplement for more details. 110 /// SYMBOL_LABEL @GOT 111 MO_GOT, 112 113 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 114 /// the offset to the location of the symbol name from the base of the GOT. 115 /// 116 /// See the X86-64 ELF ABI supplement for more details. 117 /// SYMBOL_LABEL @GOTOFF 118 MO_GOTOFF, 119 120 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 121 /// offset to the GOT entry for the symbol name from the current code 122 /// location. 123 /// 124 /// See the X86-64 ELF ABI supplement for more details. 125 /// SYMBOL_LABEL @GOTPCREL 126 MO_GOTPCREL, 127 128 /// MO_PLT - On a symbol operand this indicates that the immediate is 129 /// offset to the PLT entry of symbol name from the current code location. 130 /// 131 /// See the X86-64 ELF ABI supplement for more details. 132 /// SYMBOL_LABEL @PLT 133 MO_PLT, 134 135 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 136 /// some TLS offset. 137 /// 138 /// See 'ELF Handling for Thread-Local Storage' for more details. 139 /// SYMBOL_LABEL @TLSGD 140 MO_TLSGD, 141 142 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 143 /// some TLS offset. 144 /// 145 /// See 'ELF Handling for Thread-Local Storage' for more details. 146 /// SYMBOL_LABEL @GOTTPOFF 147 MO_GOTTPOFF, 148 149 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 150 /// some TLS offset. 151 /// 152 /// See 'ELF Handling for Thread-Local Storage' for more details. 153 /// SYMBOL_LABEL @INDNTPOFF 154 MO_INDNTPOFF, 155 156 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 157 /// some TLS offset. 158 /// 159 /// See 'ELF Handling for Thread-Local Storage' for more details. 160 /// SYMBOL_LABEL @TPOFF 161 MO_TPOFF, 162 163 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 164 /// some TLS offset. 165 /// 166 /// See 'ELF Handling for Thread-Local Storage' for more details. 167 /// SYMBOL_LABEL @NTPOFF 168 MO_NTPOFF, 169 170 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 171 /// reference is actually to the "__imp_FOO" symbol. This is used for 172 /// dllimport linkage on windows. 173 MO_DLLIMPORT, 174 175 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 176 /// reference is actually to the "FOO$stub" symbol. This is used for calls 177 /// and jumps to external functions on Tiger and before. 178 MO_DARWIN_STUB, 179 180 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 181 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 182 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 183 MO_DARWIN_NONLAZY, 184 185 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 186 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 187 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 188 MO_DARWIN_NONLAZY_PIC_BASE, 189 190 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 191 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 192 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 193 /// stub. 194 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 195 196 /// MO_TLVP - On a symbol operand this indicates that the immediate is 197 /// some TLS offset. 198 /// 199 /// This is the TLS offset for the Darwin TLS mechanism. 200 MO_TLVP, 201 202 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 203 /// is some TLS offset from the picbase. 204 /// 205 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 206 MO_TLVP_PIC_BASE 207 }; 208} 209 210/// isGlobalStubReference - Return true if the specified TargetFlag operand is 211/// a reference to a stub for a global, not the global itself. 212inline static bool isGlobalStubReference(unsigned char TargetFlag) { 213 switch (TargetFlag) { 214 case X86II::MO_DLLIMPORT: // dllimport stub. 215 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 216 case X86II::MO_GOT: // normal GOT reference. 217 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 218 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 219 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 220 return true; 221 default: 222 return false; 223 } 224} 225 226/// isGlobalRelativeToPICBase - Return true if the specified global value 227/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 228/// is true, the addressing mode has the PIC base register added in (e.g. EBX). 229inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 230 switch (TargetFlag) { 231 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 232 case X86II::MO_GOT: // isPICStyleGOT: other global. 233 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 234 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 235 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 236 case X86II::MO_TLVP: // ??? Pretty sure.. 237 return true; 238 default: 239 return false; 240 } 241} 242 243/// X86II - This namespace holds all of the target specific flags that 244/// instruction info tracks. 245/// 246namespace X86II { 247 enum { 248 //===------------------------------------------------------------------===// 249 // Instruction encodings. These are the standard/most common forms for X86 250 // instructions. 251 // 252 253 // PseudoFrm - This represents an instruction that is a pseudo instruction 254 // or one that has not been implemented yet. It is illegal to code generate 255 // it, but tolerated for intermediate implementation stages. 256 Pseudo = 0, 257 258 /// Raw - This form is for instructions that don't have any operands, so 259 /// they are just a fixed opcode value, like 'leave'. 260 RawFrm = 1, 261 262 /// AddRegFrm - This form is used for instructions like 'push r32' that have 263 /// their one register operand added to their opcode. 264 AddRegFrm = 2, 265 266 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 267 /// to specify a destination, which in this case is a register. 268 /// 269 MRMDestReg = 3, 270 271 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 272 /// to specify a destination, which in this case is memory. 273 /// 274 MRMDestMem = 4, 275 276 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 277 /// to specify a source, which in this case is a register. 278 /// 279 MRMSrcReg = 5, 280 281 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 282 /// to specify a source, which in this case is memory. 283 /// 284 MRMSrcMem = 6, 285 286 /// MRM[0-7][rm] - These forms are used to represent instructions that use 287 /// a Mod/RM byte, and use the middle field to hold extended opcode 288 /// information. In the intel manual these are represented as /0, /1, ... 289 /// 290 291 // First, instructions that operate on a register r/m operand... 292 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 293 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 294 295 // Next, instructions that operate on a memory r/m operand... 296 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 297 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 298 299 // MRMInitReg - This form is used for instructions whose source and 300 // destinations are the same register. 301 MRMInitReg = 32, 302 303 //// MRM_C1 - A mod/rm byte of exactly 0xC1. 304 MRM_C1 = 33, 305 MRM_C2 = 34, 306 MRM_C3 = 35, 307 MRM_C4 = 36, 308 MRM_C8 = 37, 309 MRM_C9 = 38, 310 MRM_E8 = 39, 311 MRM_F0 = 40, 312 MRM_F8 = 41, 313 MRM_F9 = 42, 314 315 FormMask = 63, 316 317 //===------------------------------------------------------------------===// 318 // Actual flags... 319 320 // OpSize - Set if this instruction requires an operand size prefix (0x66), 321 // which most often indicates that the instruction operates on 16 bit data 322 // instead of 32 bit data. 323 OpSize = 1 << 6, 324 325 // AsSize - Set if this instruction requires an operand size prefix (0x67), 326 // which most often indicates that the instruction address 16 bit address 327 // instead of 32 bit address (or 32 bit address in 64 bit mode). 328 AdSize = 1 << 7, 329 330 //===------------------------------------------------------------------===// 331 // Op0Mask - There are several prefix bytes that are used to form two byte 332 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 333 // used to obtain the setting of this field. If no bits in this field is 334 // set, there is no prefix byte for obtaining a multibyte opcode. 335 // 336 Op0Shift = 8, 337 Op0Mask = 0xF << Op0Shift, 338 339 // TB - TwoByte - Set if this instruction has a two byte opcode, which 340 // starts with a 0x0F byte before the real opcode. 341 TB = 1 << Op0Shift, 342 343 // REP - The 0xF3 prefix byte indicating repetition of the following 344 // instruction. 345 REP = 2 << Op0Shift, 346 347 // D8-DF - These escape opcodes are used by the floating point unit. These 348 // values must remain sequential. 349 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 350 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 351 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 352 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 353 354 // XS, XD - These prefix codes are for single and double precision scalar 355 // floating point operations performed in the SSE registers. 356 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 357 358 // T8, TA - Prefix after the 0x0F prefix. 359 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 360 361 // TF - Prefix before and after 0x0F 362 TF = 15 << Op0Shift, 363 364 //===------------------------------------------------------------------===// 365 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 366 // They are used to specify GPRs and SSE registers, 64-bit operand size, 367 // etc. We only cares about REX.W and REX.R bits and only the former is 368 // statically determined. 369 // 370 REXShift = 12, 371 REX_W = 1 << REXShift, 372 373 //===------------------------------------------------------------------===// 374 // This three-bit field describes the size of an immediate operand. Zero is 375 // unused so that we can tell if we forgot to set a value. 376 ImmShift = 13, 377 ImmMask = 7 << ImmShift, 378 Imm8 = 1 << ImmShift, 379 Imm8PCRel = 2 << ImmShift, 380 Imm16 = 3 << ImmShift, 381 Imm16PCRel = 4 << ImmShift, 382 Imm32 = 5 << ImmShift, 383 Imm32PCRel = 6 << ImmShift, 384 Imm64 = 7 << ImmShift, 385 386 //===------------------------------------------------------------------===// 387 // FP Instruction Classification... Zero is non-fp instruction. 388 389 // FPTypeMask - Mask for all of the FP types... 390 FPTypeShift = 16, 391 FPTypeMask = 7 << FPTypeShift, 392 393 // NotFP - The default, set for instructions that do not use FP registers. 394 NotFP = 0 << FPTypeShift, 395 396 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 397 ZeroArgFP = 1 << FPTypeShift, 398 399 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 400 OneArgFP = 2 << FPTypeShift, 401 402 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 403 // result back to ST(0). For example, fcos, fsqrt, etc. 404 // 405 OneArgFPRW = 3 << FPTypeShift, 406 407 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 408 // explicit argument, storing the result to either ST(0) or the implicit 409 // argument. For example: fadd, fsub, fmul, etc... 410 TwoArgFP = 4 << FPTypeShift, 411 412 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 413 // explicit argument, but have no destination. Example: fucom, fucomi, ... 414 CompareFP = 5 << FPTypeShift, 415 416 // CondMovFP - "2 operand" floating point conditional move instructions. 417 CondMovFP = 6 << FPTypeShift, 418 419 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 420 SpecialFP = 7 << FPTypeShift, 421 422 // Lock prefix 423 LOCKShift = 19, 424 LOCK = 1 << LOCKShift, 425 426 // Segment override prefixes. Currently we just need ability to address 427 // stuff in gs and fs segments. 428 SegOvrShift = 20, 429 SegOvrMask = 3 << SegOvrShift, 430 FS = 1 << SegOvrShift, 431 GS = 2 << SegOvrShift, 432 433 // Execution domain for SSE instructions in bits 22, 23. 434 // 0 in bits 22-23 means normal, non-SSE instruction. 435 SSEDomainShift = 22, 436 437 OpcodeShift = 24, 438 OpcodeMask = 0xFF << OpcodeShift, 439 440 //===------------------------------------------------------------------===// 441 // VEX - The opcode prefix used by AVX instructions 442 VEX = 1ULL << 32, 443 444 // VEX_W - Has a opcode specific functionality, but is used in the same 445 // way as REX_W is for regular SSE instructions. 446 VEX_W = 1ULL << 33, 447 448 // VEX_4V - Used to specify an additional AVX/SSE register. Several 2 449 // address instructions in SSE are represented as 3 address ones in AVX 450 // and the additional register is encoded in VEX_VVVV prefix. 451 VEX_4V = 1ULL << 34, 452 453 // VEX_I8IMM - Specifies that the last register used in a AVX instruction, 454 // must be encoded in the i8 immediate field. This usually happens in 455 // instructions with 4 operands. 456 VEX_I8IMM = 1ULL << 35 457 }; 458 459 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 460 // specified machine instruction. 461 // 462 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 463 return TSFlags >> X86II::OpcodeShift; 464 } 465 466 static inline bool hasImm(uint64_t TSFlags) { 467 return (TSFlags & X86II::ImmMask) != 0; 468 } 469 470 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 471 /// of the specified instruction. 472 static inline unsigned getSizeOfImm(uint64_t TSFlags) { 473 switch (TSFlags & X86II::ImmMask) { 474 default: assert(0 && "Unknown immediate size"); 475 case X86II::Imm8: 476 case X86II::Imm8PCRel: return 1; 477 case X86II::Imm16: 478 case X86II::Imm16PCRel: return 2; 479 case X86II::Imm32: 480 case X86II::Imm32PCRel: return 4; 481 case X86II::Imm64: return 8; 482 } 483 } 484 485 /// isImmPCRel - Return true if the immediate of the specified instruction's 486 /// TSFlags indicates that it is pc relative. 487 static inline unsigned isImmPCRel(uint64_t TSFlags) { 488 switch (TSFlags & X86II::ImmMask) { 489 default: assert(0 && "Unknown immediate size"); 490 case X86II::Imm8PCRel: 491 case X86II::Imm16PCRel: 492 case X86II::Imm32PCRel: 493 return true; 494 case X86II::Imm8: 495 case X86II::Imm16: 496 case X86II::Imm32: 497 case X86II::Imm64: 498 return false; 499 } 500 } 501 502 /// getMemoryOperandNo - The function returns the MCInst operand # for the 503 /// first field of the memory operand. If the instruction doesn't have a 504 /// memory operand, this returns -1. 505 /// 506 /// Note that this ignores tied operands. If there is a tied register which 507 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 508 /// counted as one operand. 509 /// 510 static inline int getMemoryOperandNo(uint64_t TSFlags) { 511 switch (TSFlags & X86II::FormMask) { 512 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); 513 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); 514 case X86II::Pseudo: 515 case X86II::RawFrm: 516 case X86II::AddRegFrm: 517 case X86II::MRMDestReg: 518 case X86II::MRMSrcReg: 519 return -1; 520 case X86II::MRMDestMem: 521 return 0; 522 case X86II::MRMSrcMem: { 523 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 524 unsigned FirstMemOp = 1; 525 if (HasVEX_4V) 526 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). 527 528 // FIXME: Maybe lea should have its own form? This is a horrible hack. 529 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 530 // Opcode == X86::LEA16r || Opcode == X86::LEA32r) 531 return FirstMemOp; 532 } 533 case X86II::MRM0r: case X86II::MRM1r: 534 case X86II::MRM2r: case X86II::MRM3r: 535 case X86II::MRM4r: case X86II::MRM5r: 536 case X86II::MRM6r: case X86II::MRM7r: 537 return -1; 538 case X86II::MRM0m: case X86II::MRM1m: 539 case X86II::MRM2m: case X86II::MRM3m: 540 case X86II::MRM4m: case X86II::MRM5m: 541 case X86II::MRM6m: case X86II::MRM7m: 542 return 0; 543 case X86II::MRM_C1: 544 case X86II::MRM_C2: 545 case X86II::MRM_C3: 546 case X86II::MRM_C4: 547 case X86II::MRM_C8: 548 case X86II::MRM_C9: 549 case X86II::MRM_E8: 550 case X86II::MRM_F0: 551 case X86II::MRM_F8: 552 case X86II::MRM_F9: 553 return -1; 554 } 555 } 556} 557 558inline static bool isScale(const MachineOperand &MO) { 559 return MO.isImm() && 560 (MO.getImm() == 1 || MO.getImm() == 2 || 561 MO.getImm() == 4 || MO.getImm() == 8); 562} 563 564inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 565 if (MI->getOperand(Op).isFI()) return true; 566 return Op+4 <= MI->getNumOperands() && 567 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 568 MI->getOperand(Op+2).isReg() && 569 (MI->getOperand(Op+3).isImm() || 570 MI->getOperand(Op+3).isGlobal() || 571 MI->getOperand(Op+3).isCPI() || 572 MI->getOperand(Op+3).isJTI()); 573} 574 575inline static bool isMem(const MachineInstr *MI, unsigned Op) { 576 if (MI->getOperand(Op).isFI()) return true; 577 return Op+5 <= MI->getNumOperands() && 578 MI->getOperand(Op+4).isReg() && 579 isLeaMem(MI, Op); 580} 581 582class X86InstrInfo : public TargetInstrInfoImpl { 583 X86TargetMachine &TM; 584 const X86RegisterInfo RI; 585 586 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 587 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 588 /// 589 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 590 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 591 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 592 DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 593 594 /// MemOp2RegOpTable - Load / store unfolding opcode map. 595 /// 596 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 597 598public: 599 explicit X86InstrInfo(X86TargetMachine &tm); 600 601 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 602 /// such, whenever a client has an instance of instruction info, it should 603 /// always be able to get register info as well (through this method). 604 /// 605 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 606 607 /// Return true if the instruction is a register to register move and return 608 /// the source and dest operands and their sub-register indices by reference. 609 virtual bool isMoveInstr(const MachineInstr &MI, 610 unsigned &SrcReg, unsigned &DstReg, 611 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 612 613 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 614 /// extension instruction. That is, it's like a copy where it's legal for the 615 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 616 /// true, then it's expected the pre-extension value is available as a subreg 617 /// of the result register. This also returns the sub-register index in 618 /// SubIdx. 619 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 620 unsigned &SrcReg, unsigned &DstReg, 621 unsigned &SubIdx) const; 622 623 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 624 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 625 /// stack locations as well. This uses a heuristic so it isn't 626 /// reliable for correctness. 627 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 628 int &FrameIndex) const; 629 630 /// hasLoadFromStackSlot - If the specified machine instruction has 631 /// a load from a stack slot, return true along with the FrameIndex 632 /// of the loaded stack slot and the machine mem operand containing 633 /// the reference. If not, return false. Unlike 634 /// isLoadFromStackSlot, this returns true for any instructions that 635 /// loads from the stack. This is a hint only and may not catch all 636 /// cases. 637 bool hasLoadFromStackSlot(const MachineInstr *MI, 638 const MachineMemOperand *&MMO, 639 int &FrameIndex) const; 640 641 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 642 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 643 /// stack locations as well. This uses a heuristic so it isn't 644 /// reliable for correctness. 645 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 646 int &FrameIndex) const; 647 648 /// hasStoreToStackSlot - If the specified machine instruction has a 649 /// store to a stack slot, return true along with the FrameIndex of 650 /// the loaded stack slot and the machine mem operand containing the 651 /// reference. If not, return false. Unlike isStoreToStackSlot, 652 /// this returns true for any instructions that loads from the 653 /// stack. This is a hint only and may not catch all cases. 654 bool hasStoreToStackSlot(const MachineInstr *MI, 655 const MachineMemOperand *&MMO, 656 int &FrameIndex) const; 657 658 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 659 AliasAnalysis *AA) const; 660 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 661 unsigned DestReg, unsigned SubIdx, 662 const MachineInstr *Orig, 663 const TargetRegisterInfo &TRI) const; 664 665 /// convertToThreeAddress - This method must be implemented by targets that 666 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 667 /// may be able to convert a two-address instruction into a true 668 /// three-address instruction on demand. This allows the X86 target (for 669 /// example) to convert ADD and SHL instructions into LEA instructions if they 670 /// would require register copies due to two-addressness. 671 /// 672 /// This method returns a null pointer if the transformation cannot be 673 /// performed, otherwise it returns the new instruction. 674 /// 675 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 676 MachineBasicBlock::iterator &MBBI, 677 LiveVariables *LV) const; 678 679 /// commuteInstruction - We have a few instructions that must be hacked on to 680 /// commute them. 681 /// 682 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 683 684 // Branch analysis. 685 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 686 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 687 MachineBasicBlock *&FBB, 688 SmallVectorImpl<MachineOperand> &Cond, 689 bool AllowModify) const; 690 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 691 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 692 MachineBasicBlock *FBB, 693 const SmallVectorImpl<MachineOperand> &Cond, 694 DebugLoc DL) const; 695 virtual bool copyRegToReg(MachineBasicBlock &MBB, 696 MachineBasicBlock::iterator MI, 697 unsigned DestReg, unsigned SrcReg, 698 const TargetRegisterClass *DestRC, 699 const TargetRegisterClass *SrcRC, 700 DebugLoc DL) const; 701 virtual void copyPhysReg(MachineBasicBlock &MBB, 702 MachineBasicBlock::iterator MI, DebugLoc DL, 703 unsigned DestReg, unsigned SrcReg, 704 bool KillSrc) const; 705 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 706 MachineBasicBlock::iterator MI, 707 unsigned SrcReg, bool isKill, int FrameIndex, 708 const TargetRegisterClass *RC, 709 const TargetRegisterInfo *TRI) const; 710 711 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 712 SmallVectorImpl<MachineOperand> &Addr, 713 const TargetRegisterClass *RC, 714 MachineInstr::mmo_iterator MMOBegin, 715 MachineInstr::mmo_iterator MMOEnd, 716 SmallVectorImpl<MachineInstr*> &NewMIs) const; 717 718 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 719 MachineBasicBlock::iterator MI, 720 unsigned DestReg, int FrameIndex, 721 const TargetRegisterClass *RC, 722 const TargetRegisterInfo *TRI) const; 723 724 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 725 SmallVectorImpl<MachineOperand> &Addr, 726 const TargetRegisterClass *RC, 727 MachineInstr::mmo_iterator MMOBegin, 728 MachineInstr::mmo_iterator MMOEnd, 729 SmallVectorImpl<MachineInstr*> &NewMIs) const; 730 731 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 732 MachineBasicBlock::iterator MI, 733 const std::vector<CalleeSavedInfo> &CSI, 734 const TargetRegisterInfo *TRI) const; 735 736 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 737 MachineBasicBlock::iterator MI, 738 const std::vector<CalleeSavedInfo> &CSI, 739 const TargetRegisterInfo *TRI) const; 740 741 virtual 742 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 743 int FrameIx, uint64_t Offset, 744 const MDNode *MDPtr, 745 DebugLoc DL) const; 746 747 /// foldMemoryOperand - If this target supports it, fold a load or store of 748 /// the specified stack slot into the specified machine instruction for the 749 /// specified operand(s). If this is possible, the target should perform the 750 /// folding and return true, otherwise it should return false. If it folds 751 /// the instruction, it is likely that the MachineInstruction the iterator 752 /// references has been changed. 753 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 754 MachineInstr* MI, 755 const SmallVectorImpl<unsigned> &Ops, 756 int FrameIndex) const; 757 758 /// foldMemoryOperand - Same as the previous version except it allows folding 759 /// of any load and store from / to any address, not just from a specific 760 /// stack slot. 761 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 762 MachineInstr* MI, 763 const SmallVectorImpl<unsigned> &Ops, 764 MachineInstr* LoadMI) const; 765 766 /// canFoldMemoryOperand - Returns true if the specified load / store is 767 /// folding is possible. 768 virtual bool canFoldMemoryOperand(const MachineInstr*, 769 const SmallVectorImpl<unsigned> &) const; 770 771 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 772 /// a store or a load and a store into two or more instruction. If this is 773 /// possible, returns true as well as the new instructions by reference. 774 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 775 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 776 SmallVectorImpl<MachineInstr*> &NewMIs) const; 777 778 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 779 SmallVectorImpl<SDNode*> &NewNodes) const; 780 781 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 782 /// instruction after load / store are unfolded from an instruction of the 783 /// specified opcode. It returns zero if the specified unfolding is not 784 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 785 /// index of the operand which will hold the register holding the loaded 786 /// value. 787 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 788 bool UnfoldLoad, bool UnfoldStore, 789 unsigned *LoadRegIndex = 0) const; 790 791 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 792 /// to determine if two loads are loading from the same base address. It 793 /// should only return true if the base pointers are the same and the 794 /// only differences between the two addresses are the offset. It also returns 795 /// the offsets by reference. 796 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 797 int64_t &Offset1, int64_t &Offset2) const; 798 799 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 800 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 801 /// be scheduled togther. On some targets if two loads are loading from 802 /// addresses in the same cache line, it's better if they are scheduled 803 /// together. This function takes two integers that represent the load offsets 804 /// from the common base address. It returns true if it decides it's desirable 805 /// to schedule the two loads together. "NumLoads" is the number of loads that 806 /// have already been scheduled after Load1. 807 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 808 int64_t Offset1, int64_t Offset2, 809 unsigned NumLoads) const; 810 811 virtual void getNoopForMachoTarget(MCInst &NopInst) const; 812 813 virtual 814 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 815 816 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 817 /// instruction that defines the specified register class. 818 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 819 820 static bool isX86_64NonExtLowByteReg(unsigned reg) { 821 return (reg == X86::SPL || reg == X86::BPL || 822 reg == X86::SIL || reg == X86::DIL); 823 } 824 825 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 826 if (!MO.isReg()) return false; 827 return isX86_64ExtendedReg(MO.getReg()); 828 } 829 static unsigned determineREX(const MachineInstr &MI); 830 831 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 832 /// higher) register? e.g. r8, xmm8, xmm13, etc. 833 static bool isX86_64ExtendedReg(unsigned RegNo); 834 835 /// GetInstSize - Returns the size of the specified MachineInstr. 836 /// 837 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 838 839 /// getGlobalBaseReg - Return a virtual register initialized with the 840 /// the global base register value. Output instructions required to 841 /// initialize the register in the function entry block, if necessary. 842 /// 843 unsigned getGlobalBaseReg(MachineFunction *MF) const; 844 845 /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 846 /// and a bitmask of possible arguments to SetSSEDomain ase the second. 847 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const; 848 849 /// SetSSEDomain - Set the SSEDomain of MI. 850 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; 851 852private: 853 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 854 MachineFunction::iterator &MFI, 855 MachineBasicBlock::iterator &MBBI, 856 LiveVariables *LV) const; 857 858 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 859 MachineInstr* MI, 860 unsigned OpNum, 861 const SmallVectorImpl<MachineOperand> &MOs, 862 unsigned Size, unsigned Alignment) const; 863 864 /// isFrameOperand - Return true and the FrameIndex if the specified 865 /// operand and follow operands form a reference to the stack frame. 866 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 867 int &FrameIndex) const; 868}; 869 870} // End llvm namespace 871 872#endif 873