1a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu/* 2a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Mesa 3-D graphics library 3a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 4a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Copyright (C) 2012-2015 LunarG, Inc. 5a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 6a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Permission is hereby granted, free of charge, to any person obtaining a 7a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * copy of this software and associated documentation files (the "Software"), 8a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * to deal in the Software without restriction, including without limitation 9a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * and/or sell copies of the Software, and to permit persons to whom the 11a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Software is furnished to do so, subject to the following conditions: 12a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 13a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * The above copyright notice and this permission notice shall be included 14a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * in all copies or substantial portions of the Software. 15a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 16a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * DEALINGS IN THE SOFTWARE. 23a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 24a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Authors: 25a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Chia-I Wu <olv@lunarg.com> 26a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu */ 27a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 28a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu#include "ilo_debug.h" 29a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu#include "ilo_state_sbe.h" 30a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 31a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wustatic bool 32a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wusbe_validate_gen8(const struct ilo_dev *dev, 33a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_info *info) 34a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu{ 35a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu ILO_DEV_ASSERT(dev, 6, 8); 36a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 37a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(info->attr_count <= ILO_STATE_SBE_MAX_ATTR_COUNT); 38a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 39a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(info->vue_read_base + info->vue_read_count <= 40a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu info->cv_vue_attr_count); 41a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 42a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu /* 43a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * From the Sandy Bridge PRM, volume 2 part 1, page 248: 44a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 45a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * "(Vertex URB Entry Read Length) 46a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Format: U5 47a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Range [1,16] 48a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 49a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Specifies the amount of URB data read for each Vertex URB entry, in 50a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 256-bit register increments. 51a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 52a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Programming Notes 53a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * It is UNDEFINED to set this field to 0 indicating no Vertex URB 54a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * data to be read." 55a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 56a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * "(Vertex URB Entry Read Offset) 57a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Format: U6 58a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Range [0,63] 59a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 60a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Specifies the offset (in 256-bit units) at which Vertex URB data is 61a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * to be read from the URB." 62a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu */ 63a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(info->vue_read_base % 2 == 0 && info->vue_read_base <= 126); 64a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(info->vue_read_count <= 32); 65a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 66a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu /* 67a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * From the Ivy Bridge PRM, volume 2 part 1, page 268: 68a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 69a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * "This field (Point Sprite Texture Coordinate Enable) must be 70a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * programmed to 0 when non-point primitives are rendered." 71a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu */ 72a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (ilo_dev_gen(dev) < ILO_GEN(7.5) && info->point_sprite_enables) 73a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(info->cv_is_point); 74a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 75a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu /* 76a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * From the Sandy Bridge PRM, volume 2 part 1, page 246: 77a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 78a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * "(Number of SF Output Attributes) 33-48: Specifies 17-32 attributes 79a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * (# attributes = field value - 16). Swizzling performed on 80a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attributes 16-31 (as required) only. Attributes 0-15 passed through 81a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * unmodified. 82a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 83a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Note : 84a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 85a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attribute n Component Override and Constant Source states apply to 86a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attributes 16-31 (as required) instead of Attributes 0-15. E.g., 87a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * this allows an Attribute 16-31 component to be overridden with the 88a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * PrimitiveID value. 89a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 90a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attribute n WrapShortest Enables still apply to Attributes 0-15. 91a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 92a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attribute n Swizzle Select and Attribute n Source Attribute states 93a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * are ignored and none of the swizzling functions available through 94a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * these controls are performed." 95a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 96a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * From the Sandy Bridge PRM, volume 2 part 1, page 247: 97a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 98a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * "This bit (Attribute Swizzle Enable) controls the use of the 99a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attribute n Swizzle Select and Attribute n Source Attribute fields 100a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * only. If ENABLED, those fields are used as described below. If 101a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * DISABLED, attributes are copied from their corresponding source 102a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * attributes, for the purposes of Swizzle Select only. 103a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 104a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Note that the following fields are unaffected by this bit, and are 105a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * therefore always used to control their respective fields: 106a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attribute n Component Override X/Y/Z/W 107a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attribute n Constant Source 108a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attribute n WrapShortest Enables" 109a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 110a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * From the Ivy Bridge PRM, volume 2 part 1, page 264: 111a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 112a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * "When Attribute Swizzle Enable is ENABLED, this bit (Attribute 113a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Swizzle Control Mode) controls whether attributes 0-15 or 16-31 are 114a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * subject to the following swizzle controls: 115a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 116a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * - Attribute n Component Override X/Y/Z/W 117a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * - Attribute n Constant Source 118a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * - Attribute n Swizzle Select 119a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * - Attribute n Source Attribute 120a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * - Attribute n Wrap Shortest Enables" 121a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 122a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * "SWIZ_16_31... Only valid when 16 or more attributes are output." 123a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu */ 124a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(info->swizzle_count <= ILO_STATE_SBE_MAX_SWIZZLE_COUNT); 125a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (info->swizzle_16_31) { 126a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(ilo_dev_gen(dev) >= ILO_GEN(7) && 127a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu info->swizzle_enable && 128a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu info->attr_count > 16); 129a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 130a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 131a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return true; 132a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu} 133a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 134a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wustatic uint8_t 135a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wusbe_get_gen8_min_read_count(const struct ilo_dev *dev, 136a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_info *info) 137a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu{ 138a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint8_t min_count = 0; 139a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 140a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu ILO_DEV_ASSERT(dev, 6, 8); 141a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 142a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu /* minimum read count for non-swizzled attributes */ 143a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (!info->swizzle_enable || info->swizzle_count < info->attr_count) { 144a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (info->swizzle_16_31 && info->swizzle_count + 16 == info->attr_count) 145a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu min_count = 16; 146a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu else 147a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu min_count = info->attr_count; 148a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 149a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 150a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (info->swizzle_enable) { 151a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint8_t i; 152a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 153a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu for (i = 0; i < info->swizzle_count; i++) { 154a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_swizzle_info *swizzle = 155a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu &info->swizzles[i]; 156a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu bool inputattr_facing; 157a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 158a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu switch (swizzle->attr_select) { 159a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu case GEN6_INPUTATTR_FACING: 160a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu case GEN6_INPUTATTR_FACING_W: 161a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu inputattr_facing = true; 162a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu break; 163a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu default: 164a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu inputattr_facing = false; 165a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu break; 166a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 167a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 168a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (min_count < swizzle->attr + inputattr_facing + 1) 169a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu min_count = swizzle->attr + inputattr_facing + 1; 170a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 171a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 172a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 173a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return min_count; 174a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu} 175a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 176a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wustatic uint8_t 177a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wusbe_get_gen8_read_length(const struct ilo_dev *dev, 178a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_info *info) 179a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu{ 180a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint8_t read_len; 181a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 182a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu ILO_DEV_ASSERT(dev, 6, 8); 183a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 184a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu /* 185a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * From the Sandy Bridge PRM, volume 2 part 1, page 248: 186a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 187a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * "(Vertex URB Entry Read Length) 188a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * This field should be set to the minimum length required to read the 189a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * maximum source attribute. The maximum source attribute is indicated 190a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * by the maximum value of the enabled Attribute # Source Attribute if 191a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * Attribute Swizzle Enable is set, Number of Output Attributes -1 if 192a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * enable is not set. 193a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * read_length = ceiling((max_source_attr+1)/2) 194a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * 195a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * [errata] Corruption/Hang possible if length programmed larger than 196a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * recommended" 197a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu */ 198a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (info->has_min_read_count) { 199a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu read_len = info->vue_read_count; 200a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(read_len == sbe_get_gen8_min_read_count(dev, info)); 201a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } else { 202a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu read_len = sbe_get_gen8_min_read_count(dev, info); 203a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(read_len <= info->vue_read_count); 204a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 205a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 206a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu /* 207a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * In pairs. URB entries are aligned to 1024-bits or 512-bits. There is 208a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu * no need to worry about reading past entries. 209a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu */ 210a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu read_len = (read_len + 1) / 2; 211a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (!read_len) 212a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu read_len = 1; 213a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 214a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return read_len; 215a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu} 216a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 217a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wustatic bool 218a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wusbe_set_gen8_3DSTATE_SBE(struct ilo_state_sbe *sbe, 219a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_dev *dev, 220a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_info *info) 221a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu{ 222a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint8_t vue_read_offset, vue_read_len; 223a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint8_t attr_count; 224a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint32_t dw1, dw2, dw3; 225a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 226a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu ILO_DEV_ASSERT(dev, 6, 8); 227a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 228a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (!sbe_validate_gen8(dev, info)) 229a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return false; 230a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 231a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu vue_read_offset = info->vue_read_base / 2; 232a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu vue_read_len = sbe_get_gen8_read_length(dev, info); 233a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 234a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu attr_count = info->attr_count; 235a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (ilo_dev_gen(dev) == ILO_GEN(6) && info->swizzle_16_31) 236a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu attr_count += 16; 237a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 238a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu dw1 = attr_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT | 239a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu vue_read_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT; 240a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 241a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (ilo_dev_gen(dev) >= ILO_GEN(8)) { 242c8083b1adc79073c0d6fc3bb87d6a18e41c779c4Chia-I Wu dw1 |= GEN8_SBE_DW1_FORCE_URB_READ_LEN | 243c8083b1adc79073c0d6fc3bb87d6a18e41c779c4Chia-I Wu GEN8_SBE_DW1_FORCE_URB_READ_OFFSET | 244a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu vue_read_offset << GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT; 245a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } else { 246a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu dw1 |= vue_read_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT; 247a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 248a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 249a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (ilo_dev_gen(dev) >= ILO_GEN(7) && info->swizzle_16_31) 250a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu dw1 |= GEN7_SBE_DW1_ATTR_SWIZZLE_16_31; 251a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 252a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (info->swizzle_enable) 253a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu dw1 |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE; 254a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 255a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu dw1 |= (info->point_sprite_origin_lower_left) ? 256a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT : 257a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT; 258a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 259a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu dw2 = info->point_sprite_enables; 260a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu dw3 = info->const_interp_enables; 261a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 262a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu STATIC_ASSERT(ARRAY_SIZE(sbe->sbe) >= 3); 263a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu sbe->sbe[0] = dw1; 264a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu sbe->sbe[1] = dw2; 265a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu sbe->sbe[2] = dw3; 266a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 267a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return true; 268a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu} 269a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 270a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wustatic bool 271a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wusbe_set_gen8_3DSTATE_SBE_SWIZ(struct ilo_state_sbe *sbe, 272a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_dev *dev, 273a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_info *info) 274a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu{ 275a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint16_t swiz[ILO_STATE_SBE_MAX_SWIZZLE_COUNT]; 276a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint8_t i; 277a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 278a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu ILO_DEV_ASSERT(dev, 6, 8); 279a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 280a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu for (i = 0; i < info->swizzle_count; i++) { 281a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_swizzle_info *swizzle = &info->swizzles[i]; 282a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 283a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu /* U5 */ 284a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(swizzle->attr < 32); 285a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu swiz[i] = swizzle->attr_select << GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT | 286a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu swizzle->attr << GEN8_SBE_SWIZ_SRC_ATTR__SHIFT; 287a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 288a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu if (swizzle->force_zeros) { 289c8083b1adc79073c0d6fc3bb87d6a18e41c779c4Chia-I Wu swiz[i] |= GEN8_SBE_SWIZ_CONST_OVERRIDE_W | 290c8083b1adc79073c0d6fc3bb87d6a18e41c779c4Chia-I Wu GEN8_SBE_SWIZ_CONST_OVERRIDE_Z | 291c8083b1adc79073c0d6fc3bb87d6a18e41c779c4Chia-I Wu GEN8_SBE_SWIZ_CONST_OVERRIDE_Y | 292c8083b1adc79073c0d6fc3bb87d6a18e41c779c4Chia-I Wu GEN8_SBE_SWIZ_CONST_OVERRIDE_X | 293a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu GEN8_SBE_SWIZ_CONST_0000; 294a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 295a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 296a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 297a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu for (; i < ARRAY_SIZE(swiz); i++) { 298a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu swiz[i] = GEN6_INPUTATTR_NORMAL << GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT | 299a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu i << GEN8_SBE_SWIZ_SRC_ATTR__SHIFT; 300a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu } 301a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 302a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu STATIC_ASSERT(sizeof(sbe->swiz) == sizeof(swiz)); 303a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu memcpy(sbe->swiz, swiz, sizeof(swiz)); 304a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 305a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return true; 306a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu} 307a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 308a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wubool 309a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wuilo_state_sbe_init(struct ilo_state_sbe *sbe, 310a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_dev *dev, 311a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_info *info) 312a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu{ 313a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(ilo_is_zeroed(sbe, sizeof(*sbe))); 314a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return ilo_state_sbe_set_info(sbe, dev, info); 315a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu} 316a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 317a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wubool 318a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wuilo_state_sbe_init_for_rectlist(struct ilo_state_sbe *sbe, 319a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_dev *dev, 320a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint8_t read_base, 321a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu uint8_t read_count) 322a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu{ 323a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu struct ilo_state_sbe_info info; 324a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 325a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu memset(&info, 0, sizeof(info)); 326a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu info.attr_count = read_count; 327a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu info.cv_vue_attr_count = read_base + read_count; 328a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu info.vue_read_base = read_base; 329a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu info.vue_read_count = read_count; 330a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu info.has_min_read_count = true; 331a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 332a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return ilo_state_sbe_set_info(sbe, dev, &info); 333a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu} 334a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 335a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wubool 336a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wuilo_state_sbe_set_info(struct ilo_state_sbe *sbe, 337a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_dev *dev, 338a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu const struct ilo_state_sbe_info *info) 339a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu{ 340a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu bool ret = true; 341a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 342a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu ILO_DEV_ASSERT(dev, 6, 8); 343a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 344a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu ret &= sbe_set_gen8_3DSTATE_SBE(sbe, dev, info); 345a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu ret &= sbe_set_gen8_3DSTATE_SBE_SWIZ(sbe, dev, info); 346a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 347a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu assert(ret); 348a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu 349a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu return true; 350a0bb1c2d1787cf2bd14620bf81d6d59cebfa766aChia-I Wu} 351