1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24
25#ifndef GEN_DEVICE_INFO_H
26#define GEN_DEVICE_INFO_H
27
28#include <stdbool.h>
29
30/**
31 * Intel hardware information and quirks
32 */
33struct gen_device_info
34{
35   int gen; /**< Generation number: 4, 5, 6, 7, ... */
36   int gt;
37
38   bool is_g4x;
39   bool is_ivybridge;
40   bool is_baytrail;
41   bool is_haswell;
42   bool is_cherryview;
43   bool is_broxton;
44   bool is_kabylake;
45
46   bool has_hiz_and_separate_stencil;
47   bool must_use_separate_stencil;
48
49   bool has_llc;
50
51   bool has_pln;
52   bool has_compr4;
53   bool has_surface_tile_offset;
54   bool supports_simd16_3src;
55   bool has_resource_streamer;
56
57   /**
58    * \name Intel hardware quirks
59    *  @{
60    */
61   bool has_negative_rhw_bug;
62
63   /**
64    * Some versions of Gen hardware don't do centroid interpolation correctly
65    * on unlit pixels, causing incorrect values for derivatives near triangle
66    * edges.  Enabling this flag causes the fragment shader to use
67    * non-centroid interpolation for unlit pixels, at the expense of two extra
68    * fragment shader instructions.
69    */
70   bool needs_unlit_centroid_workaround;
71   /** @} */
72
73   /**
74    * \name GPU hardware limits
75    *
76    * In general, you can find shader thread maximums by looking at the "Maximum
77    * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
78    * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
79    * limits come from the "Number of URB Entries" field in the
80    * 3DSTATE_URB_VS command and friends.
81    *
82    * These fields are used to calculate the scratch space to allocate.  The
83    * amount of scratch space can be larger without being harmful on modern
84    * GPUs, however, prior to Haswell, programming the maximum number of threads
85    * to greater than the hardware maximum would cause GPU performance to tank.
86    *
87    *  @{
88    */
89   /**
90    * Total number of slices present on the device whether or not they've been
91    * fused off.
92    *
93    * XXX: CS thread counts are limited by the inability to do cross subslice
94    * communication. It is the effectively the number of logical threads which
95    * can be executed in a subslice. Fuse configurations may cause this number
96    * to change, so we program @max_cs_threads as the lower maximum.
97    */
98   unsigned num_slices;
99   unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
100   unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
101   unsigned max_tes_threads;  /**< Maximum Domain Shader threads */
102   unsigned max_gs_threads;   /**< Maximum Geometry Shader threads. */
103   /**
104    * Theoretical maximum number of Pixel Shader threads.
105    *
106    * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
107    * automatically scale pixel shader thread count, based on a single value
108    * programmed into 3DSTATE_PS.
109    *
110    * To calculate the maximum number of threads for Gen8 beyond (which have
111    * multiple Pixel Shader Dispatchers):
112    *
113    * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
114    * - Usually there's only one PSD per subslice, so use the number of
115    *   subslices for number of PSDs.
116    * - For max_wm_threads, the total should be PSD threads * #PSDs.
117    */
118   unsigned max_wm_threads;
119
120   /**
121    * Maximum Compute Shader threads.
122    *
123    * Thread count * number of EUs per subslice
124    */
125   unsigned max_cs_threads;
126
127   struct {
128      /**
129       * Hardware default URB size.
130       *
131       * The units this is expressed in are somewhat inconsistent: 512b units
132       * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
133       *
134       * Look up "URB Size" in the "Device Attributes" page, and take the
135       * maximum.  Look up the slice count for each GT SKU on the same page.
136       * urb.size = URB Size (kbytes) / slice count
137       */
138      unsigned size;
139
140      /**
141       * The minimum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
142       */
143      unsigned min_entries[4];
144
145      /**
146       * The maximum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
147       */
148      unsigned max_entries[4];
149   } urb;
150   /** @} */
151};
152
153bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
154const char *gen_get_device_name(int devid);
155
156#endif /* GEN_DEVICE_INFO_H */
157