brw_clip_state.c revision 9b22427911ad27efc1f36faee9462c6082d0417c
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32#include "brw_context.h" 33#include "brw_state.h" 34#include "brw_defines.h" 35 36struct brw_clip_unit_key { 37 unsigned int total_grf; 38 unsigned int urb_entry_read_length; 39 unsigned int curb_entry_read_length; 40 unsigned int clip_mode; 41 42 unsigned int curbe_offset; 43 44 unsigned int nr_urb_entries, urb_size; 45 46 GLboolean depth_clamp; 47}; 48 49static void 50clip_unit_populate_key(struct brw_context *brw, struct brw_clip_unit_key *key) 51{ 52 GLcontext *ctx = &brw->intel.ctx; 53 memset(key, 0, sizeof(*key)); 54 55 /* CACHE_NEW_CLIP_PROG */ 56 key->total_grf = brw->clip.prog_data->total_grf; 57 key->urb_entry_read_length = brw->clip.prog_data->urb_read_length; 58 key->curb_entry_read_length = brw->clip.prog_data->curb_read_length; 59 key->clip_mode = brw->clip.prog_data->clip_mode; 60 61 /* BRW_NEW_CURBE_OFFSETS */ 62 key->curbe_offset = brw->curbe.clip_start; 63 64 /* BRW_NEW_URB_FENCE */ 65 key->nr_urb_entries = brw->urb.nr_clip_entries; 66 key->urb_size = brw->urb.vsize; 67 68 /* _NEW_TRANSOFORM */ 69 key->depth_clamp = ctx->Transform.DepthClamp; 70} 71 72static dri_bo * 73clip_unit_create_from_key(struct brw_context *brw, 74 struct brw_clip_unit_key *key) 75{ 76 struct intel_context *intel = &brw->intel; 77 struct brw_clip_unit_state clip; 78 dri_bo *bo; 79 80 memset(&clip, 0, sizeof(clip)); 81 82 clip.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1; 83 /* reloc */ 84 clip.thread0.kernel_start_pointer = brw->clip.prog_bo->offset >> 6; 85 86 clip.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; 87 clip.thread1.single_program_flow = 1; 88 89 clip.thread3.urb_entry_read_length = key->urb_entry_read_length; 90 clip.thread3.const_urb_entry_read_length = key->curb_entry_read_length; 91 clip.thread3.const_urb_entry_read_offset = key->curbe_offset * 2; 92 clip.thread3.dispatch_grf_start_reg = 1; 93 clip.thread3.urb_entry_read_offset = 0; 94 95 clip.thread4.nr_urb_entries = key->nr_urb_entries; 96 clip.thread4.urb_entry_allocation_size = key->urb_size - 1; 97 /* If we have enough clip URB entries to run two threads, do so. 98 */ 99 if (key->nr_urb_entries >= 10) { 100 /* Half of the URB entries go to each thread, and it has to be an 101 * even number. 102 */ 103 assert(key->nr_urb_entries % 2 == 0); 104 105 /* Although up to 16 concurrent Clip threads are allowed on IGDNG, 106 * only 2 threads can output VUEs at a time. 107 */ 108 if (intel->is_ironlake) 109 clip.thread4.max_threads = 16 - 1; 110 else 111 clip.thread4.max_threads = 2 - 1; 112 } else { 113 assert(key->nr_urb_entries >= 5); 114 clip.thread4.max_threads = 1 - 1; 115 } 116 117 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) 118 clip.thread4.max_threads = 0; 119 120 if (INTEL_DEBUG & DEBUG_STATS) 121 clip.thread4.stats_enable = 1; 122 123 clip.clip5.userclip_enable_flags = 0x7f; 124 clip.clip5.userclip_must_clip = 1; 125 clip.clip5.guard_band_enable = 0; 126 if (!key->depth_clamp) 127 clip.clip5.viewport_z_clip_enable = 1; 128 clip.clip5.viewport_xy_clip_enable = 1; 129 clip.clip5.vertex_position_space = BRW_CLIP_NDCSPACE; 130 clip.clip5.api_mode = BRW_CLIP_API_OGL; 131 clip.clip5.clip_mode = key->clip_mode; 132 133 if (intel->is_g4x) 134 clip.clip5.negative_w_clip_test = 1; 135 136 clip.clip6.clipper_viewport_state_ptr = 0; 137 clip.viewport_xmin = -1; 138 clip.viewport_xmax = 1; 139 clip.viewport_ymin = -1; 140 clip.viewport_ymax = 1; 141 142 bo = brw_upload_cache(&brw->cache, BRW_CLIP_UNIT, 143 key, sizeof(*key), 144 &brw->clip.prog_bo, 1, 145 &clip, sizeof(clip)); 146 147 /* Emit clip program relocation */ 148 assert(brw->clip.prog_bo); 149 dri_bo_emit_reloc(bo, 150 I915_GEM_DOMAIN_INSTRUCTION, 151 0, 152 clip.thread0.grf_reg_count << 1, 153 offsetof(struct brw_clip_unit_state, thread0), 154 brw->clip.prog_bo); 155 156 return bo; 157} 158 159static void upload_clip_unit( struct brw_context *brw ) 160{ 161 struct brw_clip_unit_key key; 162 163 clip_unit_populate_key(brw, &key); 164 165 dri_bo_unreference(brw->clip.state_bo); 166 brw->clip.state_bo = brw_search_cache(&brw->cache, BRW_CLIP_UNIT, 167 &key, sizeof(key), 168 &brw->clip.prog_bo, 1, 169 NULL); 170 if (brw->clip.state_bo == NULL) { 171 brw->clip.state_bo = clip_unit_create_from_key(brw, &key); 172 } 173} 174 175const struct brw_tracked_state brw_clip_unit = { 176 .dirty = { 177 .mesa = _NEW_TRANSFORM, 178 .brw = (BRW_NEW_CURBE_OFFSETS | 179 BRW_NEW_URB_FENCE), 180 .cache = CACHE_NEW_CLIP_PROG 181 }, 182 .prepare = upload_clip_unit, 183}; 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