radeon_cmdbuf.h revision 2d5fd2069031de9324a135b51a369617667223e4 
1#ifndef COMMON_CMDBUF_H
2#define COMMON_CMDBUF_H
3
4GLboolean rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller);
5int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller);
6int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller);
7void rcommonInitCmdBuf(radeonContextPtr rmesa);
8void rcommonDestroyCmdBuf(radeonContextPtr rmesa);
9
10void rcommonBeginBatch(radeonContextPtr rmesa,
11		       int n,
12		       const char *file,
13		       const char *function,
14		       int line);
15
16/* +r6/r7 : code here moved */
17
18#define CP_PACKET2  (2 << 30)
19#define CP_PACKET0(reg, n)	(RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
20#define CP_PACKET0_ONE(reg, n)	(RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
21#define CP_PACKET3(pkt, n)	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
22
23/**
24 * Every function writing to the command buffer needs to declare this
25 * to get the necessary local variables.
26 */
27#define BATCH_LOCALS(rmesa) \
28	const radeonContextPtr b_l_rmesa = rmesa
29
30/**
31 * Prepare writing n dwords to the command buffer,
32 * including producing any necessary state emits on buffer wraparound.
33 */
34#define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, __FILE__, __FUNCTION__, __LINE__)
35
36/**
37 * Same as BEGIN_BATCH, but do not cause automatic state emits.
38 */
39#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, __FILE__, __FUNCTION__, __LINE__)
40
41/**
42 * Write one dword to the command buffer.
43 */
44#define OUT_BATCH(data) \
45	do { \
46        radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\
47	} while(0)
48
49/**
50 * Write a relocated dword to the command buffer.
51 */
52#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) 	\
53	do { 							\
54	int  __offset = (offset);				\
55        if (0 && __offset) {					\
56            fprintf(stderr, "(%s:%s:%d) offset : %d\n",		\
57            __FILE__, __FUNCTION__, __LINE__, __offset);	\
58        }							\
59        radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, __offset);	\
60        radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, 		\
61                              bo, rd, wd, flags);		\
62	} while(0)
63
64
65/**
66 * Write n dwords from ptr to the command buffer.
67 */
68#define OUT_BATCH_TABLE(ptr,n) \
69	do { \
70		radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, (ptr), (n));\
71	} while(0)
72
73/**
74 * Finish writing dwords to the command buffer.
75 * The number of (direct or indirect) OUT_BATCH calls between the previous
76 * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time.
77 */
78#define END_BATCH() \
79	do { \
80        radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\
81	} while(0)
82
83/**
84 * After the last END_BATCH() of rendering, this indicates that flushing
85 * the command buffer now is okay.
86 */
87#define COMMIT_BATCH() \
88	do { \
89	} while(0)
90
91
92/** Single register write to command buffer; requires 2 dwords. */
93#define OUT_BATCH_REGVAL(reg, val) \
94	OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
95	OUT_BATCH((val))
96
97/** Continuous register range write to command buffer; requires 1 dword,
98 * expects count dwords afterwards for register contents. */
99#define OUT_BATCH_REGSEQ(reg, count) \
100	OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
101
102/* +r6/r7 : code here moved */
103
104/* Fire the buffered vertices no matter what.
105 */
106static INLINE void radeon_firevertices(radeonContextPtr radeon)
107{
108   if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
109      radeon->glCtx.Driver.Flush(&radeon->glCtx); /* +r6/r7 */
110}
111
112#endif
113