1//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SystemZTargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "systemz-lower" 15 16#include "SystemZISelLowering.h" 17#include "SystemZ.h" 18#include "SystemZTargetMachine.h" 19#include "SystemZSubtarget.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Function.h" 22#include "llvm/Intrinsics.h" 23#include "llvm/CallingConv.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/CodeGen/CallingConvLower.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/PseudoSourceValue.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 34#include "llvm/CodeGen/ValueTypes.h" 35#include "llvm/Target/TargetOptions.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/raw_ostream.h" 39#include "llvm/ADT/VectorExtras.h" 40using namespace llvm; 41 42SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : 43 TargetLowering(tm, new TargetLoweringObjectFileELF()), 44 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 45 46 RegInfo = TM.getRegisterInfo(); 47 48 // Set up the register classes. 49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); 50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); 51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); 52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); 53 54 if (!UseSoftFloat) { 55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); 56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); 57 } 58 59 // Compute derived properties from the register classes 60 computeRegisterProperties(); 61 62 // Provide all sorts of operation actions 63 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 66 67 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand); 68 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); 69 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 70 71 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand); 72 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); 73 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 74 75 setStackPointerRegisterToSaveRestore(SystemZ::R15D); 76 77 // TODO: It may be better to default to latency-oriented scheduling, however 78 // LLVM's current latency-oriented scheduler can't handle physreg definitions 79 // such as SystemZ has with PSW, so set this to the register-pressure 80 // scheduler, because it can. 81 setSchedulingPreference(Sched::RegPressure); 82 83 setBooleanContents(ZeroOrOneBooleanContent); 84 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 85 86 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 87 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 88 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 89 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 90 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 91 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 92 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 93 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 94 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 95 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 96 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 97 98 setOperationAction(ISD::SDIV, MVT::i32, Expand); 99 setOperationAction(ISD::UDIV, MVT::i32, Expand); 100 setOperationAction(ISD::SDIV, MVT::i64, Expand); 101 setOperationAction(ISD::UDIV, MVT::i64, Expand); 102 setOperationAction(ISD::SREM, MVT::i32, Expand); 103 setOperationAction(ISD::UREM, MVT::i32, Expand); 104 setOperationAction(ISD::SREM, MVT::i64, Expand); 105 setOperationAction(ISD::UREM, MVT::i64, Expand); 106 107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 108 109 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 110 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 111 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 112 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 113 setOperationAction(ISD::CTLZ, MVT::i32, Promote); 114 setOperationAction(ISD::CTLZ, MVT::i64, Legal); 115 116 // FIXME: Can we lower these 2 efficiently? 117 setOperationAction(ISD::SETCC, MVT::i32, Expand); 118 setOperationAction(ISD::SETCC, MVT::i64, Expand); 119 setOperationAction(ISD::SETCC, MVT::f32, Expand); 120 setOperationAction(ISD::SETCC, MVT::f64, Expand); 121 setOperationAction(ISD::SELECT, MVT::i32, Expand); 122 setOperationAction(ISD::SELECT, MVT::i64, Expand); 123 setOperationAction(ISD::SELECT, MVT::f32, Expand); 124 setOperationAction(ISD::SELECT, MVT::f64, Expand); 125 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 126 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 127 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 128 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 129 130 setOperationAction(ISD::MULHS, MVT::i64, Expand); 131 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 132 133 // FIXME: Can we support these natively? 134 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 135 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 136 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 137 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 138 139 // Lower some FP stuff 140 setOperationAction(ISD::FSIN, MVT::f32, Expand); 141 setOperationAction(ISD::FSIN, MVT::f64, Expand); 142 setOperationAction(ISD::FCOS, MVT::f32, Expand); 143 setOperationAction(ISD::FCOS, MVT::f64, Expand); 144 setOperationAction(ISD::FREM, MVT::f32, Expand); 145 setOperationAction(ISD::FREM, MVT::f64, Expand); 146 setOperationAction(ISD::FMA, MVT::f32, Expand); 147 setOperationAction(ISD::FMA, MVT::f64, Expand); 148 149 // We have only 64-bit bitconverts 150 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 151 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 152 153 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 154 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 155 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 156 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 157 158 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 159 160 setMinFunctionAlignment(1); 161} 162 163SDValue SystemZTargetLowering::LowerOperation(SDValue Op, 164 SelectionDAG &DAG) const { 165 switch (Op.getOpcode()) { 166 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 167 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 168 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 169 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 171 default: 172 llvm_unreachable("Should not custom lower this!"); 173 return SDValue(); 174 } 175} 176 177bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 178 if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64)) 179 return false; 180 181 // +0.0 lzer 182 // +0.0f lzdr 183 // -0.0 lzer + lner 184 // -0.0f lzdr + lndr 185 return Imm.isZero() || Imm.isNegZero(); 186} 187 188//===----------------------------------------------------------------------===// 189// SystemZ Inline Assembly Support 190//===----------------------------------------------------------------------===// 191 192/// getConstraintType - Given a constraint letter, return the type of 193/// constraint it is for this target. 194TargetLowering::ConstraintType 195SystemZTargetLowering::getConstraintType(const std::string &Constraint) const { 196 if (Constraint.size() == 1) { 197 switch (Constraint[0]) { 198 case 'r': 199 return C_RegisterClass; 200 default: 201 break; 202 } 203 } 204 return TargetLowering::getConstraintType(Constraint); 205} 206 207std::pair<unsigned, const TargetRegisterClass*> 208SystemZTargetLowering:: 209getRegForInlineAsmConstraint(const std::string &Constraint, 210 EVT VT) const { 211 if (Constraint.size() == 1) { 212 // GCC Constraint Letters 213 switch (Constraint[0]) { 214 default: break; 215 case 'r': // GENERAL_REGS 216 if (VT == MVT::i32) 217 return std::make_pair(0U, SystemZ::GR32RegisterClass); 218 else if (VT == MVT::i128) 219 return std::make_pair(0U, SystemZ::GR128RegisterClass); 220 221 return std::make_pair(0U, SystemZ::GR64RegisterClass); 222 } 223 } 224 225 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 226} 227 228//===----------------------------------------------------------------------===// 229// Calling Convention Implementation 230//===----------------------------------------------------------------------===// 231 232#include "SystemZGenCallingConv.inc" 233 234SDValue 235SystemZTargetLowering::LowerFormalArguments(SDValue Chain, 236 CallingConv::ID CallConv, 237 bool isVarArg, 238 const SmallVectorImpl<ISD::InputArg> 239 &Ins, 240 DebugLoc dl, 241 SelectionDAG &DAG, 242 SmallVectorImpl<SDValue> &InVals) 243 const { 244 245 switch (CallConv) { 246 default: 247 llvm_unreachable("Unsupported calling convention"); 248 case CallingConv::C: 249 case CallingConv::Fast: 250 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 251 } 252} 253 254SDValue 255SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 256 CallingConv::ID CallConv, bool isVarArg, 257 bool &isTailCall, 258 const SmallVectorImpl<ISD::OutputArg> &Outs, 259 const SmallVectorImpl<SDValue> &OutVals, 260 const SmallVectorImpl<ISD::InputArg> &Ins, 261 DebugLoc dl, SelectionDAG &DAG, 262 SmallVectorImpl<SDValue> &InVals) const { 263 // SystemZ target does not yet support tail call optimization. 264 isTailCall = false; 265 266 switch (CallConv) { 267 default: 268 llvm_unreachable("Unsupported calling convention"); 269 case CallingConv::Fast: 270 case CallingConv::C: 271 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 272 Outs, OutVals, Ins, dl, DAG, InVals); 273 } 274} 275 276/// LowerCCCArguments - transform physical registers into virtual registers and 277/// generate load operations for arguments places on the stack. 278// FIXME: struct return stuff 279// FIXME: varargs 280SDValue 281SystemZTargetLowering::LowerCCCArguments(SDValue Chain, 282 CallingConv::ID CallConv, 283 bool isVarArg, 284 const SmallVectorImpl<ISD::InputArg> 285 &Ins, 286 DebugLoc dl, 287 SelectionDAG &DAG, 288 SmallVectorImpl<SDValue> &InVals) 289 const { 290 291 MachineFunction &MF = DAG.getMachineFunction(); 292 MachineFrameInfo *MFI = MF.getFrameInfo(); 293 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 294 295 // Assign locations to all of the incoming arguments. 296 SmallVector<CCValAssign, 16> ArgLocs; 297 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 298 getTargetMachine(), ArgLocs, *DAG.getContext()); 299 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ); 300 301 if (isVarArg) 302 report_fatal_error("Varargs not supported yet"); 303 304 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 305 SDValue ArgValue; 306 CCValAssign &VA = ArgLocs[i]; 307 EVT LocVT = VA.getLocVT(); 308 if (VA.isRegLoc()) { 309 // Arguments passed in registers 310 TargetRegisterClass *RC; 311 switch (LocVT.getSimpleVT().SimpleTy) { 312 default: 313#ifndef NDEBUG 314 errs() << "LowerFormalArguments Unhandled argument type: " 315 << LocVT.getSimpleVT().SimpleTy 316 << "\n"; 317#endif 318 llvm_unreachable(0); 319 case MVT::i64: 320 RC = SystemZ::GR64RegisterClass; 321 break; 322 case MVT::f32: 323 RC = SystemZ::FP32RegisterClass; 324 break; 325 case MVT::f64: 326 RC = SystemZ::FP64RegisterClass; 327 break; 328 } 329 330 unsigned VReg = RegInfo.createVirtualRegister(RC); 331 RegInfo.addLiveIn(VA.getLocReg(), VReg); 332 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT); 333 } else { 334 // Sanity check 335 assert(VA.isMemLoc()); 336 337 // Create the nodes corresponding to a load from this parameter slot. 338 // Create the frame index object for this incoming parameter... 339 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8, 340 VA.getLocMemOffset(), true); 341 342 // Create the SelectionDAG nodes corresponding to a load 343 // from this parameter 344 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 345 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN, 346 MachinePointerInfo::getFixedStack(FI), 347 false, false, 0); 348 } 349 350 // If this is an 8/16/32-bit value, it is really passed promoted to 64 351 // bits. Insert an assert[sz]ext to capture this, then truncate to the 352 // right size. 353 if (VA.getLocInfo() == CCValAssign::SExt) 354 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, 355 DAG.getValueType(VA.getValVT())); 356 else if (VA.getLocInfo() == CCValAssign::ZExt) 357 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, 358 DAG.getValueType(VA.getValVT())); 359 360 if (VA.getLocInfo() != CCValAssign::Full) 361 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 362 363 InVals.push_back(ArgValue); 364 } 365 366 return Chain; 367} 368 369/// LowerCCCCallTo - functions arguments are copied from virtual regs to 370/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 371/// TODO: sret. 372SDValue 373SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 374 CallingConv::ID CallConv, bool isVarArg, 375 bool isTailCall, 376 const SmallVectorImpl<ISD::OutputArg> 377 &Outs, 378 const SmallVectorImpl<SDValue> &OutVals, 379 const SmallVectorImpl<ISD::InputArg> &Ins, 380 DebugLoc dl, SelectionDAG &DAG, 381 SmallVectorImpl<SDValue> &InVals) const { 382 MachineFunction &MF = DAG.getMachineFunction(); 383 const TargetFrameLowering *TFI = TM.getFrameLowering(); 384 385 // Offset to first argument stack slot. 386 const unsigned FirstArgOffset = 160; 387 388 // Analyze operands of the call, assigning locations to each operand. 389 SmallVector<CCValAssign, 16> ArgLocs; 390 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 391 getTargetMachine(), ArgLocs, *DAG.getContext()); 392 393 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); 394 395 // Get a count of how many bytes are to be pushed on the stack. 396 unsigned NumBytes = CCInfo.getNextStackOffset(); 397 398 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 399 getPointerTy(), true)); 400 401 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 402 SmallVector<SDValue, 12> MemOpChains; 403 SDValue StackPtr; 404 405 // Walk the register/memloc assignments, inserting copies/loads. 406 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 407 CCValAssign &VA = ArgLocs[i]; 408 409 SDValue Arg = OutVals[i]; 410 411 // Promote the value if needed. 412 switch (VA.getLocInfo()) { 413 default: assert(0 && "Unknown loc info!"); 414 case CCValAssign::Full: break; 415 case CCValAssign::SExt: 416 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 417 break; 418 case CCValAssign::ZExt: 419 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 420 break; 421 case CCValAssign::AExt: 422 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 423 break; 424 } 425 426 // Arguments that can be passed on register must be kept at RegsToPass 427 // vector 428 if (VA.isRegLoc()) { 429 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 430 } else { 431 assert(VA.isMemLoc()); 432 433 if (StackPtr.getNode() == 0) 434 StackPtr = 435 DAG.getCopyFromReg(Chain, dl, 436 (TFI->hasFP(MF) ? 437 SystemZ::R11D : SystemZ::R15D), 438 getPointerTy()); 439 440 unsigned Offset = FirstArgOffset + VA.getLocMemOffset(); 441 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 442 StackPtr, 443 DAG.getIntPtrConstant(Offset)); 444 445 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 446 MachinePointerInfo(), 447 false, false, 0)); 448 } 449 } 450 451 // Transform all store nodes into one single node because all store nodes are 452 // independent of each other. 453 if (!MemOpChains.empty()) 454 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 455 &MemOpChains[0], MemOpChains.size()); 456 457 // Build a sequence of copy-to-reg nodes chained together with token chain and 458 // flag operands which copy the outgoing args into registers. The InFlag in 459 // necessary since all emitted instructions must be stuck together. 460 SDValue InFlag; 461 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 462 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 463 RegsToPass[i].second, InFlag); 464 InFlag = Chain.getValue(1); 465 } 466 467 // If the callee is a GlobalAddress node (quite common, every direct call is) 468 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 469 // Likewise ExternalSymbol -> TargetExternalSymbol. 470 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 471 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); 472 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 473 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 474 475 // Returns a chain & a flag for retval copy to use. 476 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 477 SmallVector<SDValue, 8> Ops; 478 Ops.push_back(Chain); 479 Ops.push_back(Callee); 480 481 // Add argument registers to the end of the list so that they are 482 // known live into the call. 483 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 484 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 485 RegsToPass[i].second.getValueType())); 486 487 if (InFlag.getNode()) 488 Ops.push_back(InFlag); 489 490 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 491 InFlag = Chain.getValue(1); 492 493 // Create the CALLSEQ_END node. 494 Chain = DAG.getCALLSEQ_END(Chain, 495 DAG.getConstant(NumBytes, getPointerTy(), true), 496 DAG.getConstant(0, getPointerTy(), true), 497 InFlag); 498 InFlag = Chain.getValue(1); 499 500 // Handle result values, copying them out of physregs into vregs that we 501 // return. 502 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 503 DAG, InVals); 504} 505 506/// LowerCallResult - Lower the result values of a call into the 507/// appropriate copies out of appropriate physical registers. 508/// 509SDValue 510SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 511 CallingConv::ID CallConv, bool isVarArg, 512 const SmallVectorImpl<ISD::InputArg> 513 &Ins, 514 DebugLoc dl, SelectionDAG &DAG, 515 SmallVectorImpl<SDValue> &InVals) const { 516 517 // Assign locations to each value returned by this call. 518 SmallVector<CCValAssign, 16> RVLocs; 519 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 520 getTargetMachine(), RVLocs, *DAG.getContext()); 521 522 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); 523 524 // Copy all of the result registers out of their specified physreg. 525 for (unsigned i = 0; i != RVLocs.size(); ++i) { 526 CCValAssign &VA = RVLocs[i]; 527 528 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 529 VA.getLocVT(), InFlag).getValue(1); 530 SDValue RetValue = Chain.getValue(0); 531 InFlag = Chain.getValue(2); 532 533 // If this is an 8/16/32-bit value, it is really passed promoted to 64 534 // bits. Insert an assert[sz]ext to capture this, then truncate to the 535 // right size. 536 if (VA.getLocInfo() == CCValAssign::SExt) 537 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, 538 DAG.getValueType(VA.getValVT())); 539 else if (VA.getLocInfo() == CCValAssign::ZExt) 540 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, 541 DAG.getValueType(VA.getValVT())); 542 543 if (VA.getLocInfo() != CCValAssign::Full) 544 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue); 545 546 InVals.push_back(RetValue); 547 } 548 549 return Chain; 550} 551 552 553SDValue 554SystemZTargetLowering::LowerReturn(SDValue Chain, 555 CallingConv::ID CallConv, bool isVarArg, 556 const SmallVectorImpl<ISD::OutputArg> &Outs, 557 const SmallVectorImpl<SDValue> &OutVals, 558 DebugLoc dl, SelectionDAG &DAG) const { 559 560 // CCValAssign - represent the assignment of the return value to a location 561 SmallVector<CCValAssign, 16> RVLocs; 562 563 // CCState - Info about the registers and stack slot. 564 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 565 getTargetMachine(), RVLocs, *DAG.getContext()); 566 567 // Analize return values. 568 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); 569 570 // If this is the first return lowered for this function, add the regs to the 571 // liveout set for the function. 572 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 573 for (unsigned i = 0; i != RVLocs.size(); ++i) 574 if (RVLocs[i].isRegLoc()) 575 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 576 } 577 578 SDValue Flag; 579 580 // Copy the result values into the output registers. 581 for (unsigned i = 0; i != RVLocs.size(); ++i) { 582 CCValAssign &VA = RVLocs[i]; 583 SDValue ResValue = OutVals[i]; 584 assert(VA.isRegLoc() && "Can only return in registers!"); 585 586 // If this is an 8/16/32-bit value, it is really should be passed promoted 587 // to 64 bits. 588 if (VA.getLocInfo() == CCValAssign::SExt) 589 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); 590 else if (VA.getLocInfo() == CCValAssign::ZExt) 591 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); 592 else if (VA.getLocInfo() == CCValAssign::AExt) 593 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); 594 595 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); 596 597 // Guarantee that all emitted copies are stuck together, 598 // avoiding something bad. 599 Flag = Chain.getValue(1); 600 } 601 602 if (Flag.getNode()) 603 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 604 605 // Return Void 606 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain); 607} 608 609SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, 610 ISD::CondCode CC, SDValue &SystemZCC, 611 SelectionDAG &DAG) const { 612 // FIXME: Emit a test if RHS is zero 613 614 bool isUnsigned = false; 615 SystemZCC::CondCodes TCC; 616 switch (CC) { 617 default: 618 llvm_unreachable("Invalid integer condition!"); 619 case ISD::SETEQ: 620 case ISD::SETOEQ: 621 TCC = SystemZCC::E; 622 break; 623 case ISD::SETUEQ: 624 TCC = SystemZCC::NLH; 625 break; 626 case ISD::SETNE: 627 case ISD::SETONE: 628 TCC = SystemZCC::NE; 629 break; 630 case ISD::SETUNE: 631 TCC = SystemZCC::LH; 632 break; 633 case ISD::SETO: 634 TCC = SystemZCC::O; 635 break; 636 case ISD::SETUO: 637 TCC = SystemZCC::NO; 638 break; 639 case ISD::SETULE: 640 if (LHS.getValueType().isFloatingPoint()) { 641 TCC = SystemZCC::NH; 642 break; 643 } 644 isUnsigned = true; // FALLTHROUGH 645 case ISD::SETLE: 646 case ISD::SETOLE: 647 TCC = SystemZCC::LE; 648 break; 649 case ISD::SETUGE: 650 if (LHS.getValueType().isFloatingPoint()) { 651 TCC = SystemZCC::NL; 652 break; 653 } 654 isUnsigned = true; // FALLTHROUGH 655 case ISD::SETGE: 656 case ISD::SETOGE: 657 TCC = SystemZCC::HE; 658 break; 659 case ISD::SETUGT: 660 if (LHS.getValueType().isFloatingPoint()) { 661 TCC = SystemZCC::NLE; 662 break; 663 } 664 isUnsigned = true; // FALLTHROUGH 665 case ISD::SETGT: 666 case ISD::SETOGT: 667 TCC = SystemZCC::H; 668 break; 669 case ISD::SETULT: 670 if (LHS.getValueType().isFloatingPoint()) { 671 TCC = SystemZCC::NHE; 672 break; 673 } 674 isUnsigned = true; // FALLTHROUGH 675 case ISD::SETLT: 676 case ISD::SETOLT: 677 TCC = SystemZCC::L; 678 break; 679 } 680 681 SystemZCC = DAG.getConstant(TCC, MVT::i32); 682 683 DebugLoc dl = LHS.getDebugLoc(); 684 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), 685 dl, MVT::i64, LHS, RHS); 686} 687 688 689SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 690 SDValue Chain = Op.getOperand(0); 691 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 692 SDValue LHS = Op.getOperand(2); 693 SDValue RHS = Op.getOperand(3); 694 SDValue Dest = Op.getOperand(4); 695 DebugLoc dl = Op.getDebugLoc(); 696 697 SDValue SystemZCC; 698 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 699 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(), 700 Chain, Dest, SystemZCC, Flag); 701} 702 703SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, 704 SelectionDAG &DAG) const { 705 SDValue LHS = Op.getOperand(0); 706 SDValue RHS = Op.getOperand(1); 707 SDValue TrueV = Op.getOperand(2); 708 SDValue FalseV = Op.getOperand(3); 709 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 710 DebugLoc dl = Op.getDebugLoc(); 711 712 SDValue SystemZCC; 713 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 714 715 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 716 SmallVector<SDValue, 4> Ops; 717 Ops.push_back(TrueV); 718 Ops.push_back(FalseV); 719 Ops.push_back(SystemZCC); 720 Ops.push_back(Flag); 721 722 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size()); 723} 724 725SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, 726 SelectionDAG &DAG) const { 727 DebugLoc dl = Op.getDebugLoc(); 728 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 729 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 730 731 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 732 bool ExtraLoadRequired = 733 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false); 734 735 SDValue Result; 736 if (!IsPic && !ExtraLoadRequired) { 737 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 738 Offset = 0; 739 } else { 740 unsigned char OpFlags = 0; 741 if (ExtraLoadRequired) 742 OpFlags = SystemZII::MO_GOTENT; 743 744 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 745 } 746 747 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl, 748 getPointerTy(), Result); 749 750 if (ExtraLoadRequired) 751 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 752 MachinePointerInfo::getGOT(), false, false, 0); 753 754 // If there was a non-zero offset that we didn't fold, create an explicit 755 // addition for it. 756 if (Offset != 0) 757 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 758 DAG.getConstant(Offset, getPointerTy())); 759 760 return Result; 761} 762 763// FIXME: PIC here 764SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op, 765 SelectionDAG &DAG) const { 766 DebugLoc dl = Op.getDebugLoc(); 767 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 768 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 769 770 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 771} 772 773 774// FIXME: PIC here 775// FIXME: This is just dirty hack. We need to lower cpool properly 776SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op, 777 SelectionDAG &DAG) const { 778 DebugLoc dl = Op.getDebugLoc(); 779 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 780 781 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 782 CP->getAlignment(), 783 CP->getOffset()); 784 785 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 786} 787 788const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { 789 switch (Opcode) { 790 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG"; 791 case SystemZISD::CALL: return "SystemZISD::CALL"; 792 case SystemZISD::BRCOND: return "SystemZISD::BRCOND"; 793 case SystemZISD::CMP: return "SystemZISD::CMP"; 794 case SystemZISD::UCMP: return "SystemZISD::UCMP"; 795 case SystemZISD::SELECT: return "SystemZISD::SELECT"; 796 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper"; 797 default: return NULL; 798 } 799} 800 801//===----------------------------------------------------------------------===// 802// Other Lowering Code 803//===----------------------------------------------------------------------===// 804 805MachineBasicBlock* 806SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 807 MachineBasicBlock *BB) const { 808 const SystemZInstrInfo &TII = *TM.getInstrInfo(); 809 DebugLoc dl = MI->getDebugLoc(); 810 assert((MI->getOpcode() == SystemZ::Select32 || 811 MI->getOpcode() == SystemZ::SelectF32 || 812 MI->getOpcode() == SystemZ::Select64 || 813 MI->getOpcode() == SystemZ::SelectF64) && 814 "Unexpected instr type to insert"); 815 816 // To "insert" a SELECT instruction, we actually have to insert the diamond 817 // control-flow pattern. The incoming instruction knows the destination vreg 818 // to set, the condition code register to branch on, the true/false values to 819 // select between, and a branch opcode to use. 820 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 821 MachineFunction::iterator I = BB; 822 ++I; 823 824 // thisMBB: 825 // ... 826 // TrueVal = ... 827 // cmpTY ccX, r1, r2 828 // jCC copy1MBB 829 // fallthrough --> copy0MBB 830 MachineBasicBlock *thisMBB = BB; 831 MachineFunction *F = BB->getParent(); 832 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 833 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 834 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm(); 835 F->insert(I, copy0MBB); 836 F->insert(I, copy1MBB); 837 // Update machine-CFG edges by transferring all successors of the current 838 // block to the new block which will contain the Phi node for the select. 839 copy1MBB->splice(copy1MBB->begin(), BB, 840 llvm::next(MachineBasicBlock::iterator(MI)), 841 BB->end()); 842 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 843 // Next, add the true and fallthrough blocks as its successors. 844 BB->addSuccessor(copy0MBB); 845 BB->addSuccessor(copy1MBB); 846 847 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); 848 849 // copy0MBB: 850 // %FalseValue = ... 851 // # fallthrough to copy1MBB 852 BB = copy0MBB; 853 854 // Update machine-CFG edges 855 BB->addSuccessor(copy1MBB); 856 857 // copy1MBB: 858 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 859 // ... 860 BB = copy1MBB; 861 BuildMI(*BB, BB->begin(), dl, TII.get(SystemZ::PHI), 862 MI->getOperand(0).getReg()) 863 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 864 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 865 866 MI->eraseFromParent(); // The pseudo instruction is gone now. 867 return BB; 868} 869