IceTargetLoweringX8664Traits.h revision d1bd1d330c8eb8116811ad4dc01fe636b80b86cb
1//===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// 2// 3// The Subzero Code Generator 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// 10/// \file 11/// \brief Declares the X8664 Target Lowering Traits. 12/// 13//===----------------------------------------------------------------------===// 14 15#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H 16#define SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H 17 18#include "IceAssembler.h" 19#include "IceConditionCodesX8664.h" 20#include "IceDefs.h" 21#include "IceInst.h" 22#include "IceInstX8664.def" 23#include "IceOperand.h" 24#include "IceRegistersX8664.h" 25#include "IceTargetLowering.h" 26#include "IceTargetLoweringX8664.def" 27#include "IceTargetLoweringX86RegClass.h" 28 29#include <array> 30#include <initializer_list> 31 32namespace Ice { 33 34namespace X8664 { 35using namespace ::Ice::X86; 36 37template <class TraitsType> class AssemblerX86Base; 38template <class TraitsType> struct Insts; 39template <class TraitsType> class TargetX86Base; 40 41class TargetX8664; 42 43struct TargetX8664Traits { 44 //---------------------------------------------------------------------------- 45 // ______ ______ __ __ 46 // /\ __ \/\ ___\/\ "-./ \ 47 // \ \ __ \ \___ \ \ \-./\ \ 48 // \ \_\ \_\/\_____\ \_\ \ \_\ 49 // \/_/\/_/\/_____/\/_/ \/_/ 50 // 51 //---------------------------------------------------------------------------- 52 static constexpr ::Ice::Assembler::AssemblerKind AsmKind = 53 ::Ice::Assembler::Asm_X8632; 54 55 static constexpr bool Is64Bit = true; 56 static constexpr bool HasPopa = false; 57 static constexpr bool HasPusha = false; 58 static constexpr bool UsesX87 = false; 59 static constexpr ::Ice::RegX8664::GPRRegister Last8BitGPR = 60 ::Ice::RegX8664::GPRRegister::Encoded_Reg_r15d; 61 62 enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 }; 63 64 using GPRRegister = ::Ice::RegX8664::GPRRegister; 65 using ByteRegister = ::Ice::RegX8664::ByteRegister; 66 using XmmRegister = ::Ice::RegX8664::XmmRegister; 67 68 using Cond = ::Ice::CondX8664; 69 70 using RegisterSet = ::Ice::RegX8664; 71 static constexpr SizeT StackPtr = RegX8664::Reg_rsp; 72 static constexpr SizeT FramePtr = RegX8664::Reg_rbp; 73 static constexpr GPRRegister Encoded_Reg_Accumulator = 74 RegX8664::Encoded_Reg_eax; 75 static constexpr GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx; 76 static constexpr FixupKind FK_PcRel = llvm::ELF::R_X86_64_PC32; 77 static constexpr FixupKind FK_Abs = llvm::ELF::R_X86_64_32; 78 static constexpr FixupKind FK_Gotoff = llvm::ELF::R_X86_64_GOTOFF64; 79 static constexpr FixupKind FK_GotPC = llvm::ELF::R_X86_64_GOTPC32; 80 81 class Operand { 82 public: 83 enum RexBits { 84 RexNone = 0x00, 85 RexBase = 0x40, 86 RexW = RexBase | (1 << 3), 87 RexR = RexBase | (1 << 2), 88 RexX = RexBase | (1 << 1), 89 RexB = RexBase | (1 << 0), 90 }; 91 92 protected: 93 // Needed by subclass Address. 94 Operand() = default; 95 96 public: 97 Operand(const Operand &) = default; 98 Operand(Operand &&) = default; 99 Operand &operator=(const Operand &) = default; 100 Operand &operator=(Operand &&) = default; 101 102 uint8_t mod() const { return (encoding_at(0) >> 6) & 3; } 103 104 uint8_t rexX() const { return (rex_ & RexX) != RexX ? RexNone : RexX; } 105 uint8_t rexB() const { return (rex_ & RexB) != RexB ? RexNone : RexB; } 106 107 GPRRegister rm() const { 108 return static_cast<GPRRegister>((rexB() != 0 ? 0x08 : 0) | 109 (encoding_at(0) & 7)); 110 } 111 112 ScaleFactor scale() const { 113 return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3); 114 } 115 116 GPRRegister index() const { 117 return static_cast<GPRRegister>((rexX() != 0 ? 0x08 : 0) | 118 ((encoding_at(1) >> 3) & 7)); 119 } 120 121 GPRRegister base() const { 122 return static_cast<GPRRegister>((rexB() != 0 ? 0x08 : 0) | 123 (encoding_at(1) & 7)); 124 } 125 126 int8_t disp8() const { 127 assert(length_ >= 2); 128 return static_cast<int8_t>(encoding_[length_ - 1]); 129 } 130 131 AssemblerFixup *fixup() const { return fixup_; } 132 133 protected: 134 void SetModRM(int mod, GPRRegister rm) { 135 assert((mod & ~3) == 0); 136 encoding_[0] = (mod << 6) | (rm & 0x07); 137 rex_ = (rm & 0x08) ? RexB : RexNone; 138 length_ = 1; 139 } 140 141 void SetSIB(ScaleFactor scale, GPRRegister index, GPRRegister base) { 142 assert(length_ == 1); 143 assert((scale & ~3) == 0); 144 encoding_[1] = (scale << 6) | ((index & 0x07) << 3) | (base & 0x07); 145 rex_ = 146 ((base & 0x08) ? RexB : RexNone) | ((index & 0x08) ? RexX : RexNone); 147 length_ = 2; 148 } 149 150 void SetDisp8(int8_t disp) { 151 assert(length_ == 1 || length_ == 2); 152 encoding_[length_++] = static_cast<uint8_t>(disp); 153 } 154 155 void SetDisp32(int32_t disp) { 156 assert(length_ == 1 || length_ == 2); 157 intptr_t disp_size = sizeof(disp); 158 memmove(&encoding_[length_], &disp, disp_size); 159 length_ += disp_size; 160 } 161 162 void SetFixup(AssemblerFixup *fixup) { fixup_ = fixup; } 163 164 private: 165 AssemblerFixup *fixup_ = nullptr; 166 uint8_t rex_ = 0; 167 uint8_t encoding_[6]; 168 uint8_t length_ = 0; 169 170 explicit Operand(GPRRegister reg) : fixup_(nullptr) { SetModRM(3, reg); } 171 172 /// Get the operand encoding byte at the given index. 173 uint8_t encoding_at(intptr_t index) const { 174 assert(index >= 0 && index < length_); 175 return encoding_[index]; 176 } 177 178 /// Returns whether or not this operand is really the given register in 179 /// disguise. Used from the assembler to generate better encodings. 180 bool IsRegister(GPRRegister reg) const { 181 return ((encoding_[0] & 0xF8) == 182 0xC0) // Addressing mode is register only. 183 && 184 (rm() == reg); // Register codes match. 185 } 186 187 friend class AssemblerX86Base<TargetX8664Traits>; 188 }; 189 190 class Address : public Operand { 191 Address() = default; 192 193 public: 194 Address(const Address &) = default; 195 Address(Address &&) = default; 196 Address &operator=(const Address &) = default; 197 Address &operator=(Address &&) = default; 198 199 Address(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) { 200 if (Fixup == nullptr && Disp == 0 && 201 (Base & 7) != RegX8664::Encoded_Reg_rbp) { 202 SetModRM(0, Base); 203 if ((Base & 7) == RegX8664::Encoded_Reg_rsp) 204 SetSIB(TIMES_1, RegX8664::Encoded_Reg_rsp, Base); 205 } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { 206 SetModRM(1, Base); 207 if ((Base & 7) == RegX8664::Encoded_Reg_rsp) 208 SetSIB(TIMES_1, RegX8664::Encoded_Reg_rsp, Base); 209 SetDisp8(Disp); 210 } else { 211 SetModRM(2, Base); 212 if ((Base & 7) == RegX8664::Encoded_Reg_rsp) 213 SetSIB(TIMES_1, RegX8664::Encoded_Reg_rsp, Base); 214 SetDisp32(Disp); 215 if (Fixup) 216 SetFixup(Fixup); 217 } 218 } 219 220 Address(GPRRegister Index, ScaleFactor Scale, int32_t Disp, 221 AssemblerFixup *Fixup) { 222 assert(Index != RegX8664::Encoded_Reg_rsp); // Illegal addressing mode. 223 SetModRM(0, RegX8664::Encoded_Reg_rsp); 224 SetSIB(Scale, Index, RegX8664::Encoded_Reg_rbp); 225 SetDisp32(Disp); 226 if (Fixup) 227 SetFixup(Fixup); 228 } 229 230 Address(GPRRegister Base, GPRRegister Index, ScaleFactor Scale, 231 int32_t Disp, AssemblerFixup *Fixup) { 232 assert(Index != RegX8664::Encoded_Reg_rsp); // Illegal addressing mode. 233 if (Fixup == nullptr && Disp == 0 && 234 (Base & 7) != RegX8664::Encoded_Reg_rbp) { 235 SetModRM(0, RegX8664::Encoded_Reg_rsp); 236 SetSIB(Scale, Index, Base); 237 } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { 238 SetModRM(1, RegX8664::Encoded_Reg_rsp); 239 SetSIB(Scale, Index, Base); 240 SetDisp8(Disp); 241 } else { 242 SetModRM(2, RegX8664::Encoded_Reg_rsp); 243 SetSIB(Scale, Index, Base); 244 SetDisp32(Disp); 245 if (Fixup) 246 SetFixup(Fixup); 247 } 248 } 249 250 /// Generate a RIP-relative address expression on x86-64. 251 static Address RipRelative(RelocOffsetT Offset, AssemblerFixup *Fixup) { 252 assert(Fixup != nullptr); 253 assert(Fixup->kind() == FK_PcRel); 254 Address NewAddress; 255 NewAddress.SetModRM(0x0, RegX8664::Encoded_Reg_rbp); 256 257 // Use the Offset in the displacement for now. If we decide to process 258 // fixups later, we'll need to patch up the emitted displacement. 259 NewAddress.SetDisp32(Offset); 260 if (Fixup) 261 NewAddress.SetFixup(Fixup); 262 263 return NewAddress; 264 } 265 266 /// Generate an absolute address. 267 static Address Absolute(RelocOffsetT Addr) { 268 Address NewAddress; 269 NewAddress.SetModRM(0x0, RegX8664::Encoded_Reg_rsp); 270 static constexpr ScaleFactor NoScale = TIMES_1; 271 NewAddress.SetSIB(NoScale, RegX8664::Encoded_Reg_rsp, 272 RegX8664::Encoded_Reg_rbp); 273 NewAddress.SetDisp32(Addr); 274 return NewAddress; 275 } 276 277 static Address ofConstPool(Assembler *Asm, const Constant *Imm) { 278 // TODO(jpp): ??? 279 AssemblerFixup *Fixup = Asm->createFixup(FK_Abs, Imm); 280 const RelocOffsetT Offset = 4; 281 return Address::RipRelative(Offset, Fixup); 282 } 283 }; 284 285 //---------------------------------------------------------------------------- 286 // __ ______ __ __ ______ ______ __ __ __ ______ 287 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ 288 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ 289 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ 290 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ 291 // 292 //---------------------------------------------------------------------------- 293 enum InstructionSet { 294 Begin, 295 // SSE2 is the PNaCl baseline instruction set. 296 SSE2 = Begin, 297 SSE4_1, 298 End 299 }; 300 301 static const char *TargetName; 302 static constexpr Type WordType = IceType_i64; 303 304 static IceString getRegName(int32_t RegNum) { 305 static const char *const RegNames[RegisterSet::Reg_NUM] = { 306#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 307 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 308 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 309 name, 310 REGX8664_TABLE 311#undef X 312 }; 313 assert(RegNum >= 0); 314 assert(RegNum < RegisterSet::Reg_NUM); 315 return RegNames[RegNum]; 316 } 317 318 static GPRRegister getEncodedGPR(int32_t RegNum) { 319 static const GPRRegister GPRRegs[RegisterSet::Reg_NUM] = { 320#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 321 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 322 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 323 GPRRegister(isGPR ? encode : GPRRegister::Encoded_Not_GPR), 324 REGX8664_TABLE 325#undef X 326 }; 327 assert(RegNum >= 0); 328 assert(RegNum < RegisterSet::Reg_NUM); 329 assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR); 330 return GPRRegs[RegNum]; 331 } 332 333 static ByteRegister getEncodedByteReg(int32_t RegNum) { 334 static const ByteRegister ByteRegs[RegisterSet::Reg_NUM] = { 335#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 336 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 337 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 338 ByteRegister(is8 ? encode : ByteRegister::Encoded_Not_ByteReg), 339 REGX8664_TABLE 340#undef X 341 }; 342 assert(RegNum >= 0); 343 assert(RegNum < RegisterSet::Reg_NUM); 344 assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg); 345 return ByteRegs[RegNum]; 346 } 347 348 static XmmRegister getEncodedXmm(int32_t RegNum) { 349 static const XmmRegister XmmRegs[RegisterSet::Reg_NUM] = { 350#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 351 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 352 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 353 XmmRegister(isXmm ? encode : XmmRegister::Encoded_Not_Xmm), 354 REGX8664_TABLE 355#undef X 356 }; 357 assert(RegNum >= 0); 358 assert(RegNum < RegisterSet::Reg_NUM); 359 assert(XmmRegs[RegNum] != XmmRegister::Encoded_Not_Xmm); 360 return XmmRegs[RegNum]; 361 } 362 363 static uint32_t getEncoding(int32_t RegNum) { 364 static const uint32_t Encoding[RegisterSet::Reg_NUM] = { 365#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 366 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 367 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 368 encode, 369 REGX8664_TABLE 370#undef X 371 }; 372 assert(RegNum >= 0); 373 assert(RegNum < RegisterSet::Reg_NUM); 374 return Encoding[RegNum]; 375 } 376 377 static inline int32_t getBaseReg(int32_t RegNum) { 378 static const int32_t BaseRegs[RegisterSet::Reg_NUM] = { 379#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 380 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 381 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 382 encode, 383 REGX8664_TABLE 384#undef X 385 }; 386 assert(RegNum >= 0); 387 assert(RegNum < RegisterSet::Reg_NUM); 388 return BaseRegs[RegNum]; 389 } 390 391private: 392 static int32_t getFirstGprForType(Type Ty) { 393 switch (Ty) { 394 default: 395 llvm_unreachable("Invalid type for GPR."); 396 case IceType_i1: 397 case IceType_i8: 398 return RegisterSet::Reg_al; 399 case IceType_i16: 400 return RegisterSet::Reg_ax; 401 case IceType_i32: 402 return RegisterSet::Reg_eax; 403 case IceType_i64: 404 return RegisterSet::Reg_rax; 405 } 406 } 407 408public: 409 static int32_t getGprForType(Type Ty, int32_t RegNum) { 410 assert(RegNum != Variable::NoRegister); 411 412 if (!isScalarIntegerType(Ty)) { 413 return RegNum; 414 } 415 416 assert(Ty == IceType_i1 || Ty == IceType_i8 || Ty == IceType_i16 || 417 Ty == IceType_i32 || Ty == IceType_i64); 418 419 if (RegNum == RegisterSet::Reg_ah) { 420 assert(Ty == IceType_i8); 421 return RegNum; 422 } 423 424 assert(RegNum != RegisterSet::Reg_bh); 425 assert(RegNum != RegisterSet::Reg_ch); 426 assert(RegNum != RegisterSet::Reg_dh); 427 428 const int32_t FirstGprForType = getFirstGprForType(Ty); 429 430 switch (RegNum) { 431 default: 432 llvm::report_fatal_error("Unknown register."); 433#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 434 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 435 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 436 case RegisterSet::val: { \ 437 if (!isGPR) \ 438 return RegisterSet::val; \ 439 assert((is64) || (is32) || (is16) || (is8) || \ 440 getBaseReg(RegisterSet::val) == RegisterSet::Reg_rsp || \ 441 getBaseReg(RegisterSet::val) == RegisterSet::Reg_rbp); \ 442 constexpr int32_t FirstGprWithRegNumSize = \ 443 ((is64) || RegisterSet::val == RegisterSet::Reg_rsp || \ 444 RegisterSet::val == RegisterSet::Reg_rbp) \ 445 ? RegisterSet::Reg_rax \ 446 : (((is32) || RegisterSet::val == RegisterSet::Reg_esp || \ 447 RegisterSet::val == RegisterSet::Reg_ebp) \ 448 ? RegisterSet::Reg_eax \ 449 : (((is16) || RegisterSet::val == RegisterSet::Reg_sp || \ 450 RegisterSet::val == RegisterSet::Reg_bp) \ 451 ? RegisterSet::Reg_ax \ 452 : RegisterSet::Reg_al)); \ 453 const int32_t NewRegNum = \ 454 RegNum - FirstGprWithRegNumSize + FirstGprForType; \ 455 assert(getBaseReg(RegNum) == getBaseReg(NewRegNum) && \ 456 "Error involving " #val); \ 457 return NewRegNum; \ 458 } 459 REGX8664_TABLE 460#undef X 461 } 462 } 463 464private: 465 /// SizeOf is used to obtain the size of an initializer list as a constexpr 466 /// expression. This is only needed until our C++ library is updated to 467 /// C++ 14 -- which defines constexpr members to std::initializer_list. 468 class SizeOf { 469 SizeOf(const SizeOf &) = delete; 470 SizeOf &operator=(const SizeOf &) = delete; 471 472 public: 473 constexpr SizeOf() : Size(0) {} 474 template <typename... T> 475 explicit constexpr SizeOf(T...) 476 : Size(length<T...>::value) {} 477 constexpr SizeT size() const { return Size; } 478 479 private: 480 template <typename T, typename... U> struct length { 481 static constexpr std::size_t value = 1 + length<U...>::value; 482 }; 483 484 template <typename T> struct length<T> { 485 static constexpr std::size_t value = 1; 486 }; 487 488 const std::size_t Size; 489 }; 490 491public: 492 static void initRegisterSet( 493 const ::Ice::ClFlags &Flags, 494 std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet, 495 std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases) { 496 llvm::SmallBitVector IntegerRegistersI64(RegisterSet::Reg_NUM); 497 llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); 498 llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM); 499 llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); 500 llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); 501 llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); 502 llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); 503 llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); 504 llvm::SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM); 505 llvm::SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM); 506 llvm::SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM); 507 llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM); 508 509 static constexpr struct { 510 uint16_t Val; 511 unsigned IsReservedWhenSandboxing : 1; 512 unsigned Is64 : 1; 513 unsigned Is32 : 1; 514 unsigned Is16 : 1; 515 unsigned Is8 : 1; 516 unsigned IsXmm : 1; 517 unsigned Is64To8 : 1; 518 unsigned Is32To8 : 1; 519 unsigned Is16To8 : 1; 520 unsigned IsTrunc8Rcvr : 1; 521 unsigned IsAhRcvr : 1; 522#define NUM_ALIASES_BITS 2 523 SizeT NumAliases : (NUM_ALIASES_BITS + 1); 524 uint16_t Aliases[1 << NUM_ALIASES_BITS]; 525#undef NUM_ALIASES_BITS 526 } X8664RegTable[RegisterSet::Reg_NUM] = { 527#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 528 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 529 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 530 { \ 531 RegisterSet::val, sboxres, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 532 is16To8, isTrunc8Rcvr, isAhRcvr, (SizeOf aliases).size(), aliases, \ 533 } \ 534 , 535 REGX8664_TABLE 536#undef X 537 }; 538 539 const bool NeedSandboxing = Flags.getUseSandboxing(); 540 for (SizeT ii = 0; ii < llvm::array_lengthof(X8664RegTable); ++ii) { 541 const auto &Entry = X8664RegTable[ii]; 542 // Even though the register is disabled for register allocation, it might 543 // still be used by the Target Lowering (e.g., base pointer), so the 544 // register alias table still needs to be defined. 545 (*RegisterAliases)[Entry.Val].resize(RegisterSet::Reg_NUM); 546 for (int J = 0; J < Entry.NumAliases; ++J) { 547 SizeT Alias = Entry.Aliases[J]; 548 assert(!(*RegisterAliases)[Entry.Val][Alias] && "Duplicate alias"); 549 (*RegisterAliases)[Entry.Val].set(Alias); 550 } 551 552 (*RegisterAliases)[Entry.Val].set(Entry.Val); 553 const bool DisabledRegister = 554 NeedSandboxing && Entry.IsReservedWhenSandboxing; 555 if (DisabledRegister) { 556 continue; 557 } 558 (IntegerRegistersI64)[Entry.Val] = Entry.Is64; 559 (IntegerRegistersI32)[Entry.Val] = Entry.Is32; 560 (IntegerRegistersI16)[Entry.Val] = Entry.Is16; 561 (IntegerRegistersI8)[Entry.Val] = Entry.Is8; 562 (FloatRegisters)[Entry.Val] = Entry.IsXmm; 563 (VectorRegisters)[Entry.Val] = Entry.IsXmm; 564 (Trunc64To8Registers)[Entry.Val] = Entry.Is64To8; 565 (Trunc32To8Registers)[Entry.Val] = Entry.Is32To8; 566 (Trunc16To8Registers)[Entry.Val] = Entry.Is16To8; 567 (Trunc8RcvrRegisters)[Entry.Val] = Entry.IsTrunc8Rcvr; 568 (AhRcvrRegisters)[Entry.Val] = Entry.IsAhRcvr; 569 } 570 571 (*TypeToRegisterSet)[RC_void] = InvalidRegisters; 572 (*TypeToRegisterSet)[RC_i1] = IntegerRegistersI8; 573 (*TypeToRegisterSet)[RC_i8] = IntegerRegistersI8; 574 (*TypeToRegisterSet)[RC_i16] = IntegerRegistersI16; 575 (*TypeToRegisterSet)[RC_i32] = IntegerRegistersI32; 576 (*TypeToRegisterSet)[RC_i64] = IntegerRegistersI64; 577 (*TypeToRegisterSet)[RC_f32] = FloatRegisters; 578 (*TypeToRegisterSet)[RC_f64] = FloatRegisters; 579 (*TypeToRegisterSet)[RC_v4i1] = VectorRegisters; 580 (*TypeToRegisterSet)[RC_v8i1] = VectorRegisters; 581 (*TypeToRegisterSet)[RC_v16i1] = VectorRegisters; 582 (*TypeToRegisterSet)[RC_v16i8] = VectorRegisters; 583 (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; 584 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; 585 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; 586 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; 587 (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; 588 (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; 589 (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; 590 (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; 591 } 592 593 static llvm::SmallBitVector 594 getRegisterSet(const ::Ice::ClFlags &Flags, 595 TargetLowering::RegSetMask Include, 596 TargetLowering::RegSetMask Exclude) { 597 llvm::SmallBitVector Registers(RegisterSet::Reg_NUM); 598 599 const bool NeedSandboxing = Flags.getUseSandboxing(); 600#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 601 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 602 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 603 if (!NeedSandboxing || !(sboxres)) { \ 604 if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave)) \ 605 Registers[RegisterSet::val] = true; \ 606 if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave)) \ 607 Registers[RegisterSet::val] = true; \ 608 if (stackptr && (Include & ::Ice::TargetLowering::RegSet_StackPointer)) \ 609 Registers[RegisterSet::val] = true; \ 610 if (frameptr && (Include & ::Ice::TargetLowering::RegSet_FramePointer)) \ 611 Registers[RegisterSet::val] = true; \ 612 if (scratch && (Exclude & ::Ice::TargetLowering::RegSet_CallerSave)) \ 613 Registers[RegisterSet::val] = false; \ 614 if (preserved && (Exclude & ::Ice::TargetLowering::RegSet_CalleeSave)) \ 615 Registers[RegisterSet::val] = false; \ 616 if (stackptr && (Exclude & ::Ice::TargetLowering::RegSet_StackPointer)) \ 617 Registers[RegisterSet::val] = false; \ 618 if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer)) \ 619 Registers[RegisterSet::val] = false; \ 620 } 621 622 REGX8664_TABLE 623 624#undef X 625 626 return Registers; 627 } 628 629 static void 630 makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func, 631 llvm::SmallVectorImpl<int32_t> &Permutation, 632 const llvm::SmallBitVector &ExcludeRegisters, 633 uint64_t Salt) { 634 // TODO(stichnot): Declaring Permutation this way loses type/size 635 // information. Fix this in conjunction with the caller-side TODO. 636 assert(Permutation.size() >= RegisterSet::Reg_NUM); 637 // Expected upper bound on the number of registers in a single equivalence 638 // class. For x86-64, this would comprise the 16 XMM registers. This is 639 // for performance, not correctness. 640 static const unsigned MaxEquivalenceClassSize = 8; 641 using RegisterList = llvm::SmallVector<int32_t, MaxEquivalenceClassSize>; 642 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; 643 EquivalenceClassMap EquivalenceClasses; 644 SizeT NumShuffled = 0, NumPreserved = 0; 645 646// Build up the equivalence classes of registers by looking at the register 647// properties as well as whether the registers should be explicitly excluded 648// from shuffling. 649#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ 650 sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \ 651 is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \ 652 if (ExcludeRegisters[RegisterSet::val]) { \ 653 /* val stays the same in the resulting permutation. */ \ 654 Permutation[RegisterSet::val] = RegisterSet::val; \ 655 ++NumPreserved; \ 656 } else { \ 657 uint32_t AttrKey = 0; \ 658 uint32_t Index = 0; \ 659 /* Combine relevant attributes into an equivalence class key. */ \ 660 Index |= (scratch << (AttrKey++)); \ 661 Index |= (preserved << (AttrKey++)); \ 662 Index |= (is8 << (AttrKey++)); \ 663 Index |= (is16 << (AttrKey++)); \ 664 Index |= (is32 << (AttrKey++)); \ 665 Index |= (is64 << (AttrKey++)); \ 666 Index |= (isXmm << (AttrKey++)); \ 667 Index |= (is16To8 << (AttrKey++)); \ 668 Index |= (is32To8 << (AttrKey++)); \ 669 Index |= (is64To8 << (AttrKey++)); \ 670 Index |= (isTrunc8Rcvr << (AttrKey++)); \ 671 /* val is assigned to an equivalence class based on its properties. */ \ 672 EquivalenceClasses[Index].push_back(RegisterSet::val); \ 673 } 674 REGX8664_TABLE 675#undef X 676 677 // Create a random number generator for regalloc randomization. 678 RandomNumberGenerator RNG(Ctx->getFlags().getRandomSeed(), 679 RPE_RegAllocRandomization, Salt); 680 RandomNumberGeneratorWrapper RNGW(RNG); 681 682 // Shuffle the resulting equivalence classes. 683 for (auto I : EquivalenceClasses) { 684 const RegisterList &List = I.second; 685 RegisterList Shuffled(List); 686 RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW); 687 for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) { 688 Permutation[List[SI]] = Shuffled[SI]; 689 ++NumShuffled; 690 } 691 } 692 693 assert(NumShuffled + NumPreserved == RegisterSet::Reg_NUM); 694 695 if (Func->isVerbose(IceV_Random)) { 696 OstreamLocker L(Func->getContext()); 697 Ostream &Str = Func->getContext()->getStrDump(); 698 Str << "Register equivalence classes:\n"; 699 for (auto I : EquivalenceClasses) { 700 Str << "{"; 701 const RegisterList &List = I.second; 702 bool First = true; 703 for (int32_t Register : List) { 704 if (!First) 705 Str << " "; 706 First = false; 707 Str << getRegName(Register); 708 } 709 Str << "}\n"; 710 } 711 } 712 } 713 714 static int32_t getRaxOrDie() { return RegisterSet::Reg_rax; } 715 716 static int32_t getRdxOrDie() { return RegisterSet::Reg_rdx; } 717 718 // x86-64 calling convention: 719 // 720 // * The first eight arguments of vector/fp type, regardless of their 721 // position relative to the other arguments in the argument list, are placed 722 // in registers %xmm0 - %xmm7. 723 // 724 // * The first six arguments of integer types, regardless of their position 725 // relative to the other arguments in the argument list, are placed in 726 // registers %rdi, %rsi, %rdx, %rcx, %r8, and %r9. 727 // 728 // This intends to match the section "Function Calling Sequence" of the 729 // document "System V Application Binary Interface." 730 731 /// The maximum number of arguments to pass in XMM registers 732 static constexpr uint32_t X86_MAX_XMM_ARGS = 8; 733 /// The maximum number of arguments to pass in GPR registers 734 static constexpr uint32_t X86_MAX_GPR_ARGS = 6; 735 /// Whether scalar floating point arguments are passed in XMM registers 736 static constexpr bool X86_PASS_SCALAR_FP_IN_XMM = true; 737 /// Get the register for a given argument slot in the XMM registers. 738 static int32_t getRegisterForXmmArgNum(uint32_t ArgNum) { 739 // TODO(sehr): Change to use the CCArg technique used in ARM32. 740 static_assert(RegisterSet::Reg_xmm0 + 1 == RegisterSet::Reg_xmm1, 741 "Inconsistency between XMM register numbers and ordinals"); 742 if (ArgNum >= X86_MAX_XMM_ARGS) { 743 return Variable::NoRegister; 744 } 745 return static_cast<int32_t>(RegisterSet::Reg_xmm0 + ArgNum); 746 } 747 /// Get the register for a given argument slot in the GPRs. 748 static int32_t getRegisterForGprArgNum(Type Ty, uint32_t ArgNum) { 749 if (ArgNum >= X86_MAX_GPR_ARGS) { 750 return Variable::NoRegister; 751 } 752 static const RegisterSet::AllRegisters GprForArgNum[] = { 753 RegisterSet::Reg_rdi, RegisterSet::Reg_rsi, RegisterSet::Reg_rdx, 754 RegisterSet::Reg_rcx, RegisterSet::Reg_r8, RegisterSet::Reg_r9, 755 }; 756 static_assert(llvm::array_lengthof(GprForArgNum) == X86_MAX_GPR_ARGS, 757 "Mismatch between MAX_GPR_ARGS and GprForArgNum."); 758 assert(Ty == IceType_i64 || Ty == IceType_i32); 759 return static_cast<int32_t>(getGprForType(Ty, GprForArgNum[ArgNum])); 760 } 761 762 /// The number of bits in a byte 763 static constexpr uint32_t X86_CHAR_BIT = 8; 764 /// Stack alignment. This is defined in IceTargetLoweringX8664.cpp because it 765 /// is used as an argument to std::max(), and the default std::less<T> has an 766 /// operator(T const&, T const&) which requires this member to have an 767 /// address. 768 static const uint32_t X86_STACK_ALIGNMENT_BYTES; 769 /// Size of the return address on the stack 770 static constexpr uint32_t X86_RET_IP_SIZE_BYTES = 8; 771 /// The number of different NOP instructions 772 static constexpr uint32_t X86_NUM_NOP_VARIANTS = 5; 773 774 /// \name Limits for unrolling memory intrinsics. 775 /// @{ 776 static constexpr uint32_t MEMCPY_UNROLL_LIMIT = 8; 777 static constexpr uint32_t MEMMOVE_UNROLL_LIMIT = 8; 778 static constexpr uint32_t MEMSET_UNROLL_LIMIT = 16; 779 /// @} 780 781 /// Value is in bytes. Return Value adjusted to the next highest multiple of 782 /// the stack alignment. 783 static uint32_t applyStackAlignment(uint32_t Value) { 784 return Utils::applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES); 785 } 786 787 /// Return the type which the elements of the vector have in the X86 788 /// representation of the vector. 789 static Type getInVectorElementType(Type Ty) { 790 assert(isVectorType(Ty)); 791 size_t Index = static_cast<size_t>(Ty); 792 (void)Index; 793 assert(Index < TableTypeX8664AttributesSize); 794 return TableTypeX8664Attributes[Ty].InVectorElementType; 795 } 796 797 // Note: The following data structures are defined in 798 // IceTargetLoweringX8664.cpp. 799 800 /// The following table summarizes the logic for lowering the fcmp 801 /// instruction. There is one table entry for each of the 16 conditions. 802 /// 803 /// The first four columns describe the case when the operands are floating 804 /// point scalar values. A comment in lowerFcmp() describes the lowering 805 /// template. In the most general case, there is a compare followed by two 806 /// conditional branches, because some fcmp conditions don't map to a single 807 /// x86 conditional branch. However, in many cases it is possible to swap the 808 /// operands in the comparison and have a single conditional branch. Since 809 /// it's quite tedious to validate the table by hand, good execution tests are 810 /// helpful. 811 /// 812 /// The last two columns describe the case when the operands are vectors of 813 /// floating point values. For most fcmp conditions, there is a clear mapping 814 /// to a single x86 cmpps instruction variant. Some fcmp conditions require 815 /// special code to handle and these are marked in the table with a 816 /// Cmpps_Invalid predicate. 817 /// {@ 818 static const struct TableFcmpType { 819 uint32_t Default; 820 bool SwapScalarOperands; 821 Cond::BrCond C1, C2; 822 bool SwapVectorOperands; 823 Cond::CmppsCond Predicate; 824 } TableFcmp[]; 825 static const size_t TableFcmpSize; 826 /// @} 827 828 /// The following table summarizes the logic for lowering the icmp instruction 829 /// for i32 and narrower types. Each icmp condition has a clear mapping to an 830 /// x86 conditional branch instruction. 831 /// {@ 832 static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[]; 833 static const size_t TableIcmp32Size; 834 /// @} 835 836 /// The following table summarizes the logic for lowering the icmp instruction 837 /// for the i64 type. For Eq and Ne, two separate 32-bit comparisons and 838 /// conditional branches are needed. For the other conditions, three separate 839 /// conditional branches are needed. 840 /// {@ 841 static const struct TableIcmp64Type { 842 Cond::BrCond C1, C2, C3; 843 } TableIcmp64[]; 844 static const size_t TableIcmp64Size; 845 /// @} 846 847 static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) { 848 size_t Index = static_cast<size_t>(Cond); 849 assert(Index < TableIcmp32Size); 850 return TableIcmp32[Index].Mapping; 851 } 852 853 static const struct TableTypeX8664AttributesType { 854 Type InVectorElementType; 855 } TableTypeX8664Attributes[]; 856 static const size_t TableTypeX8664AttributesSize; 857 858 //---------------------------------------------------------------------------- 859 // __ __ __ ______ ______ 860 // /\ \/\ "-.\ \/\ ___\/\__ _\ 861 // \ \ \ \ \-. \ \___ \/_/\ \/ 862 // \ \_\ \_\\"\_\/\_____\ \ \_\ 863 // \/_/\/_/ \/_/\/_____/ \/_/ 864 // 865 //---------------------------------------------------------------------------- 866 using Traits = TargetX8664Traits; 867 using Insts = ::Ice::X8664::Insts<Traits>; 868 869 using TargetLowering = ::Ice::X8664::TargetX86Base<Traits>; 870 using ConcreteTarget = ::Ice::X8664::TargetX8664; 871 using Assembler = ::Ice::X8664::AssemblerX86Base<Traits>; 872 873 /// X86Operand extends the Operand hierarchy. Its subclasses are X86OperandMem 874 /// and VariableSplit. 875 class X86Operand : public ::Ice::Operand { 876 X86Operand() = delete; 877 X86Operand(const X86Operand &) = delete; 878 X86Operand &operator=(const X86Operand &) = delete; 879 880 public: 881 enum OperandKindX8664 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit }; 882 using ::Ice::Operand::dump; 883 884 void dump(const Cfg *, Ostream &Str) const override; 885 886 protected: 887 X86Operand(OperandKindX8664 Kind, Type Ty) 888 : Operand(static_cast<::Ice::Operand::OperandKind>(Kind), Ty) {} 889 }; 890 891 /// X86OperandMem represents the m64 addressing mode, with optional base and 892 /// index registers, a constant offset, and a fixed shift value for the index 893 /// register. 894 class X86OperandMem : public X86Operand { 895 X86OperandMem() = delete; 896 X86OperandMem(const X86OperandMem &) = delete; 897 X86OperandMem &operator=(const X86OperandMem &) = delete; 898 899 public: 900 enum SegmentRegisters { DefaultSegment = -1, SegReg_NUM }; 901 static X86OperandMem * 902 create(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, 903 Variable *Index = nullptr, uint16_t Shift = 0, 904 SegmentRegisters SegmentRegister = DefaultSegment, 905 bool IsRebased = false) { 906 assert(SegmentRegister == DefaultSegment); 907 (void)SegmentRegister; 908 return new (Func->allocate<X86OperandMem>()) 909 X86OperandMem(Func, Ty, Base, Offset, Index, Shift, IsRebased); 910 } 911 static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base, 912 Constant *Offset, bool IsRebased) { 913 constexpr Variable *NoIndex = nullptr; 914 constexpr uint16_t NoShift = 0; 915 return new (Func->allocate<X86OperandMem>()) 916 X86OperandMem(Func, Ty, Base, Offset, NoIndex, NoShift, IsRebased); 917 } 918 Variable *getBase() const { return Base; } 919 Constant *getOffset() const { return Offset; } 920 Variable *getIndex() const { return Index; } 921 uint16_t getShift() const { return Shift; } 922 SegmentRegisters getSegmentRegister() const { return DefaultSegment; } 923 void emitSegmentOverride(Assembler *) const {} 924 bool getIsRebased() const { return IsRebased; } 925 Address toAsmAddress(Assembler *Asm, const Ice::TargetLowering *Target, 926 bool IsLeaAddr = false) const; 927 928 void emit(const Cfg *Func) const override; 929 using X86Operand::dump; 930 void dump(const Cfg *Func, Ostream &Str) const override; 931 932 static bool classof(const Operand *Operand) { 933 return Operand->getKind() == static_cast<OperandKind>(kMem); 934 } 935 936 void setRandomized(bool R) { Randomized = R; } 937 938 bool getRandomized() const { return Randomized; } 939 940 private: 941 X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, 942 Variable *Index, uint16_t Shift, bool IsRebased); 943 944 Variable *const Base; 945 Constant *const Offset; 946 Variable *const Index; 947 const uint16_t Shift; 948 const bool IsRebased; 949 /// A flag to show if this memory operand is a randomized one. Randomized 950 /// memory operands are generated in 951 /// TargetX86Base::randomizeOrPoolImmediate() 952 bool Randomized = false; 953 }; 954 955 /// VariableSplit is a way to treat an f64 memory location as a pair of i32 956 /// locations (Low and High). This is needed for some cases of the Bitcast 957 /// instruction. Since it's not possible for integer registers to access the 958 /// XMM registers and vice versa, the lowering forces the f64 to be spilled to 959 /// the stack and then accesses through the VariableSplit. 960 // TODO(jpp): remove references to VariableSplit from IceInstX86Base as 64bit 961 // targets can natively handle these. 962 class VariableSplit : public X86Operand { 963 VariableSplit() = delete; 964 VariableSplit(const VariableSplit &) = delete; 965 VariableSplit &operator=(const VariableSplit &) = delete; 966 967 public: 968 enum Portion { Low, High }; 969 static VariableSplit *create(Cfg *Func, Variable *Var, Portion Part) { 970 return new (Func->allocate<VariableSplit>()) 971 VariableSplit(Func, Var, Part); 972 } 973 int32_t getOffset() const { return Part == High ? 4 : 0; } 974 975 Address toAsmAddress(const Cfg *Func) const; 976 void emit(const Cfg *Func) const override; 977 using X86Operand::dump; 978 void dump(const Cfg *Func, Ostream &Str) const override; 979 980 static bool classof(const Operand *Operand) { 981 return Operand->getKind() == static_cast<OperandKind>(kSplit); 982 } 983 984 private: 985 VariableSplit(Cfg *Func, Variable *Var, Portion Part) 986 : X86Operand(kSplit, IceType_i32), Var(Var), Part(Part) { 987 assert(Var->getType() == IceType_f64); 988 Vars = Func->allocateArrayOf<Variable *>(1); 989 Vars[0] = Var; 990 NumVars = 1; 991 } 992 993 Variable *Var; 994 Portion Part; 995 }; 996 997 /// SpillVariable decorates a Variable by linking it to another Variable. When 998 /// stack frame offsets are computed, the SpillVariable is given a distinct 999 /// stack slot only if its linked Variable has a register. If the linked 1000 /// Variable has a stack slot, then the Variable and SpillVariable share that 1001 /// slot. 1002 class SpillVariable : public Variable { 1003 SpillVariable() = delete; 1004 SpillVariable(const SpillVariable &) = delete; 1005 SpillVariable &operator=(const SpillVariable &) = delete; 1006 1007 public: 1008 static SpillVariable *create(Cfg *Func, Type Ty, SizeT Index) { 1009 return new (Func->allocate<SpillVariable>()) SpillVariable(Ty, Index); 1010 } 1011 const static OperandKind SpillVariableKind = 1012 static_cast<OperandKind>(kVariable_Target); 1013 static bool classof(const Operand *Operand) { 1014 return Operand->getKind() == SpillVariableKind; 1015 } 1016 void setLinkedTo(Variable *Var) { LinkedTo = Var; } 1017 Variable *getLinkedTo() const { return LinkedTo; } 1018 // Inherit dump() and emit() from Variable. 1019 1020 private: 1021 SpillVariable(Type Ty, SizeT Index) 1022 : Variable(SpillVariableKind, Ty, Index), LinkedTo(nullptr) {} 1023 Variable *LinkedTo; 1024 }; 1025 1026 // Note: The following data structures are defined in IceInstX8664.cpp. 1027 1028 static const struct InstBrAttributesType { 1029 Cond::BrCond Opposite; 1030 const char *DisplayString; 1031 const char *EmitString; 1032 } InstBrAttributes[]; 1033 1034 static const struct InstCmppsAttributesType { 1035 const char *EmitString; 1036 } InstCmppsAttributes[]; 1037 1038 static const struct TypeAttributesType { 1039 const char *CvtString; // i (integer), s (single FP), d (double FP) 1040 const char *SdSsString; // ss, sd, or <blank> 1041 const char *PdPsString; // ps, pd, or <blank> 1042 const char *SpSdString; // ss, sd, ps, pd, or <blank> 1043 const char *PackString; // b, w, d, or <blank> 1044 const char *WidthString; // b, w, l, q, or <blank> 1045 const char *FldString; // s, l, or <blank> 1046 } TypeAttributes[]; 1047}; 1048 1049using Traits = ::Ice::X8664::TargetX8664Traits; 1050} // end of namespace X8664 1051 1052} // end of namespace Ice 1053 1054#endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H 1055