176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This software is available to you under a choice of one of two 376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman licenses. You may choose to be licensed under the terms of the GNU 476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman General Public License (GPL) Version 2, available at 576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD 676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman license, available in the LICENSE.TXT file accompanying this 776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman software. These details are also available at 876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman <http://openib.org/license.html>. 976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 1176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 1376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 1476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 1576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 1776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman SOFTWARE. 1876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. 2076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman*/ 2176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2276d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanFILE_LICENCE ( GPL2_ONLY ); 2376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*** 2576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman *** This file was generated at "Tue Nov 22 15:21:23 2005" 2676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman *** by: 2776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix arbelprm_ -bits -fixnames MT25218_PRM.csp 2876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ***/ 2976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#ifndef H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H 3176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H 3276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* UD Address Vector */ 3476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_ud_address_vector_st { /* Little Endian */ 3676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* Protection Domain */ 3776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_number[0x00002]; /* Port number 3876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Port 1 3976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2 - Port 2 4076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved */ 4176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00006]; 4276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 4376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 4476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 4576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 4676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 4776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 4876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 4976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control. 5076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - 4X injection rate 5176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - 1X injection rate 5276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved 5376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 5476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00001]; 5576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg[0x00002]; /* Max Message size, size is 256*2^MSG bytes */ 5676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00002]; 5776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table 5876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman mgid_index = (port_number-1) * 2^log_max_gid + gid_index 5976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Where: 6076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1. log_max_gid is taken from QUERY_DEV_LIM command 6176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2. gid_index is the index to the GID table */ 6276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x0000a]; 6376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 6476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 6576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 6676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ 6776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 6876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 6976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 7076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 7176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 7276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 7376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 7476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */ 7576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 7676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 7776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send doorbell */ 7976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_send_doorbell_st { /* Little Endian */ 8176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */ 8276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */ 8376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00002]; 8476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */ 8576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */ 8676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 8776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */ 8876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 8976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 9076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 9176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 9276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* ACCESS_LAM_inject_errors_input_modifier */ 9476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_access_lam_inject_errors_input_modifier_st { /* Little Endian */ 9676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t index3[0x00007]; 9776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q3[0x00001]; 9876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t index2[0x00007]; 9976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q2[0x00001]; 10076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t index1[0x00007]; 10176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q1[0x00001]; 10276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t index0[0x00007]; 10376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q0[0x00001]; 10476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 10576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 10676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* ACCESS_LAM_inject_errors_input_parameter */ 10876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_access_lam_inject_errors_input_parameter_st { /* Little Endian */ 11076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ba[0x00002]; /* Bank Address */ 11176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t da[0x00002]; /* Dimm Address */ 11276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0001c]; 11376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 11476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ra[0x00010]; /* Row Address */ 11576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ca[0x00010]; /* Column Address */ 11676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 11776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 11876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 12076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_recv_wqe_segment_next_st { /* Little Endian */ 12276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00006]; 12376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */ 12476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 12576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes). 12676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Zero value in NDS field signals end of WQEs? chain. 12776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 12876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0001a]; 12976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 13076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 13176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment data inline */ 13376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_data_inline_st { /* Little Endian */ 13576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */ 13676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00015]; 13776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t always1[0x00001]; 13876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 13976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */ 14076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 14176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 14276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 14376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 14476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 14576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment data ptr */ 14776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_data_ptr_st { /* Little Endian */ 14976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t byte_count[0x0001f]; 15076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t always0[0x00001]; 15176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 15276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t l_key[0x00020]; 15376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 15476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t local_address_h[0x00020]; 15576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 15676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t local_address_l[0x00020]; 15776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 15876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 15976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment rd */ 16176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_local_invalidate_segment_st { /* Little Endian */ 16376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 16476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 16576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_key[0x00018]; 16676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 16776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 16876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x000a0]; 16976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 17076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 17176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Fast_Registration_Segment */ 17376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_fast_registration_segment_st { /* Little Endian */ 17576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0001b]; 17676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */ 17776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */ 17876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */ 17976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */ 18076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */ 18176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 18276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list */ 18376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 18476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. */ 18576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 18676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. 18776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman page_size should be less than 20. */ 18876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 18976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t zb[0x00001]; /* Zero Based Region */ 19076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list */ 19176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 19276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */ 19376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 19476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */ 19576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 19676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */ 19776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 19876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */ 19976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 20076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 20176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment atomic */ 20376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_atomic_st { /* Little Endian */ 20576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t swap_add_h[0x00020]; 20676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 20776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t swap_add_l[0x00020]; 20876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 20976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t compare_h[0x00020]; 21076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 21176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t compare_l[0x00020]; 21276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 21376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 21476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment remote address */ 21676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_remote_address_st { /* Little Endian */ 21876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t remote_virt_addr_h[0x00020]; 21976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 22076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t remote_virt_addr_l[0x00020]; 22176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 22276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rkey[0x00020]; 22376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 22476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 22576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 22676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 22776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* end wqe segment bind */ 22976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 23076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_bind_st { /* Little Endian */ 23176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0001d]; 23276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */ 23376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window. 23476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 23576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */ 23676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 23776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0001e]; 23876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */ 23976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t type[0x00001]; /* Window type. 24076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Type one window 24176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Type two window 24276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 24376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 24476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */ 24576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 24676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */ 24776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 24876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_h[0x00020]; 24976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 25076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_l[0x00020]; 25176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 25276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t length_h[0x00020]; 25376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 25476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t length_l[0x00020]; 25576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 25676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 25776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment ud */ 25976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 26076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_ud_st { /* Little Endian */ 26176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 26276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 26376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t destination_qp[0x00018]; 26476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 26576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 26676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q_key[0x00020]; 26776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 26876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 26976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 27076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 27176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment rd */ 27376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_rd_st { /* Little Endian */ 27576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t destination_qp[0x00018]; 27676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 27776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 27876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q_key[0x00020]; 27976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 28076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 28176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 28276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 28376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 28476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment ctrl */ 28576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 28676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_ctrl_send_st { /* Little Endian */ 28776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t always1[0x00001]; 28876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t s[0x00001]; /* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */ 28976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e[0x00001]; /* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */ 29076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t c[0x00001]; /* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */ 29176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */ 29276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */ 29376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00001]; 29476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */ 29576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00018]; 29676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 29776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */ 29876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 29976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 30076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 30176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment next */ 30276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 30376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_next_st { /* Little Endian */ 30476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nopcode[0x00005]; /* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP: 30576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?00000? - NOP. WQE with this opcode creates a completion, but does nothing else 30676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?01000? - RDMA-write 30776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?01001? - RDMA-Write with Immediate 30876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?10000? - RDMA-read 30976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?10001? - Atomic Compare & swap 31076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?10010? - Atomic Fetch & Add 31176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?11000? - Bind memory window 31276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 31376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The encoding for the following operations depends on the QP type: 31476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For RC, UC and RD QP: 31576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?01010? - SEND 31676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?01011? - SEND with Immediate 31776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 31876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For UD QP: 31976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of 32076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman both the current WQE and the next WQE, as follows: 32176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 32276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set : 32376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?01000? - SEND 32476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?01001? - SEND with Immediate 32576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 32676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set): 32776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?01010? - SEND 32876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ?01011? - SEND with Immediate 32976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 33076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman All other opcode values are RESERVED, and will result in invalid operation execution. */ 33176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00001]; 33276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */ 33376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 33476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes). 33576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Zero value in NDS field signals end of WQEs? chain. 33676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 33776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f[0x00001]; /* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */ 33876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t always1[0x00001]; 33976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00018]; 34076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 34176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 34276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 34376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Address Path */ 34476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 34576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_address_path_st { /* Little Endian */ 34676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pkey_index[0x00007]; /* PKey table index */ 34776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00011]; 34876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_number[0x00002]; /* Specific port associated with this QP/EE. 34976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Port 1 35076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2 - Port 2 35176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved */ 35276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00006]; 35376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 35476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 35576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 35676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 35776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00005]; 35876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rnr_retry[0x00003]; /* RNR retry count (see C9-132 in IB spec Vol 1) 35976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0-6 - number of retries 36076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7 - infinite */ 36176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 36276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 36376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control. 36476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - 100% injection rate 36576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - 25% injection rate 36676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2 - 12.5% injection rate 36776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - 50% injection rate 36876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved */ 36976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00005]; 37076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table */ 37176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00005]; 37276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details. 37376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */ 37476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 37576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 37676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 37776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ 37876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 37976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 38076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 38176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 38276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 38376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 38476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 38576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */ 38676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 38776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 38876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 38976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* HCA Command Register (HCR) */ 39076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 39176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_hca_command_register_st { /* Little Endian */ 39276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */ 39376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 39476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */ 39576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 39676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */ 39776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 39876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */ 39976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 40076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */ 40176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 40276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 40376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */ 40476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 40576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[0x0000c]; /* Command opcode */ 40676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */ 40776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00006]; 40876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e[0x00001]; /* Event Request 40976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Don't report event (software will poll the GO bit) 41076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Report event to EQ when the command completes */ 41176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR) 41276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Software can write to the HCR only if Go bit is cleared. 41376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */ 41476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared) 41576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */ 41676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 41776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 41876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 41976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* CQ Doorbell */ 42076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 42176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_cq_cmd_doorbell_st { /* Little Endian */ 42276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn[0x00018]; /* CQ number accessed */ 42376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ 42476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x0 - Reserved 42576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter. 42676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter. 42776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated 42876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Other - Reserved */ 42976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00001]; 43076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ. 43176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited 43276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman completion or Request notification for multiple completions doorbells after receiving completion notification. 43376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is initialized to Zero */ 43476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 43576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 43676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */ 43776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 43876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 43976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 44076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* RD-send doorbell */ 44176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 44276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_rd_send_doorbell_st { /* Little Endian */ 44376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 44476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram) 44576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be zero for Nop and Bind operations */ 44676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 44776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 44876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 44976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 45076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_send_doorbell_st send_doorbell;/* Send Parameters */ 45176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 45276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 45376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 45476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Multicast Group Member QP */ 45576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 45676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_mgmqp_st { /* Little Endian */ 45776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */ 45876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00007]; 45976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */ 46076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 46176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 46276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 46376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* vsd */ 46476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 46576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_vsd_st { /* Little Endian */ 46676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw0[0x00020]; 46776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 46876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw1[0x00020]; 46976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw2[0x00020]; 47176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw3[0x00020]; 47376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw4[0x00020]; 47576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw5[0x00020]; 47776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw6[0x00020]; 47976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw7[0x00020]; 48176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw8[0x00020]; 48376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw9[0x00020]; 48576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw10[0x00020]; 48776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw11[0x00020]; 48976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw12[0x00020]; 49176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw13[0x00020]; 49376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw14[0x00020]; 49576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw15[0x00020]; 49776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw16[0x00020]; 49976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw17[0x00020]; 50176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw18[0x00020]; 50376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw19[0x00020]; 50576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw20[0x00020]; 50776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw21[0x00020]; 50976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw22[0x00020]; 51176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw23[0x00020]; 51376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw24[0x00020]; 51576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw25[0x00020]; 51776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw26[0x00020]; 51976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 52076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw27[0x00020]; 52176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 52276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw28[0x00020]; 52376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 52476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw29[0x00020]; 52576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 52676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw30[0x00020]; 52776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 52876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw31[0x00020]; 52976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 53076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw32[0x00020]; 53176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 53276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw33[0x00020]; 53376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 53476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw34[0x00020]; 53576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 53676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw35[0x00020]; 53776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 53876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw36[0x00020]; 53976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 54076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw37[0x00020]; 54176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 54276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw38[0x00020]; 54376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 54476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw39[0x00020]; 54576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 54676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw40[0x00020]; 54776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 54876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw41[0x00020]; 54976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 55076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw42[0x00020]; 55176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 55276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw43[0x00020]; 55376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 55476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw44[0x00020]; 55576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 55676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw45[0x00020]; 55776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 55876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw46[0x00020]; 55976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 56076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw47[0x00020]; 56176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 56276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw48[0x00020]; 56376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 56476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw49[0x00020]; 56576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 56676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw50[0x00020]; 56776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 56876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw51[0x00020]; 56976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 57076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw52[0x00020]; 57176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 57276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw53[0x00020]; 57376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 57476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw54[0x00020]; 57576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 57676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw55[0x00020]; 57776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 57876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 57976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 58076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* ACCESS_LAM_inject_errors */ 58176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 58276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_access_lam_inject_errors_st { /* Little Endian */ 58376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_access_lam_inject_errors_input_parameter_st access_lam_inject_errors_input_parameter; 58476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 58576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_access_lam_inject_errors_input_modifier_st access_lam_inject_errors_input_modifier; 58676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 58776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 58876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 58976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 59076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 59176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Logical DIMM Information */ 59276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 59376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_dimminfo_st { /* Little Endian */ 59476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dimmsize[0x00010]; /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */ 59576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 59676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dimmstatus[0x00001]; /* DIMM Status 59776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Enabled 59876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Disabled 59976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 60076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dh[0x00001]; /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */ 60176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wo[0x00001]; /* When set, the DIMM is write only. 60276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If data integrity is configured (other than none), the DIMM must be 60376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman only targeted by write transactions where the address and size are multiples of 16 bytes. */ 60476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00005]; 60576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 60676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM 60776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - DIMM SPD was read from InfiniHost-III-EX NVMEM */ 60876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits. 60976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid only if spd bit is 0. */ 61076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */ 61176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t syn[0x00004]; /* Error syndrome (valid regardless of status value) 61276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - DIMM has no error 61376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - SPD error (e.g. checksum error, no response, error while reading) 61476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2) 61576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict) 61676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5 - DIMM size trimmed due to configuration (size exceeds) 61776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - Error, reserved 61876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 61976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00016]; 62076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00040]; 62276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */ 62476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */ 62676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00040]; 62876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 63076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 63176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* UAR Parameters */ 63276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 63376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_uar_params_st { /* Little Endian */ 63476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_base_addr_h[0x00020];/* UAR Base (pyhsical) Address [63:32] (QUERY_HCA only) */ 63576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 63676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00014]; 63776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_base_addr_l[0x0000c];/* UAR Base (pyhsical) Address [31:20] (QUERY_HCA only) */ 63876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 63976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page. 64076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Size of UAR Page is 4KB*2^UAR_Page_Size */ 64176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */ 64276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00004]; 64376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_uar_entry_sz[0x00006];/* Size of UAR Context entry is 2^log_uar_sz in 4KByte pages */ 64476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x0000a]; 64576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 64676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 64776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 64876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32]. 64976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Number of entries in table is 2^log_max_uars. 65076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size */ 65176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 65276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0]. 65376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Number of entries in table is 2^log_max_uars. 65476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. */ 65576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 65676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_context_base_addr_h[0x00020];/* Base address of UAR Context [63:32]. 65776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Number of entries in table is 2^log_max_uars. 65876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. */ 65976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 66076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_context_base_addr_l[0x00020];/* Base address of UAR Context [31:0]. 66176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Number of entries in table is 2^log_max_uars. 66276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. */ 66376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 66476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 66576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 66676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Translation and Protection Tables Parameters */ 66776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 66876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_tptparams_st { /* Little Endian */ 66976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32]. 67076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Entry size is 64 bytes. 67176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. 67276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 67376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 67476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0]. 67576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Entry size is 64 bytes. 67676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. 67776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 67876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 67976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_mpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the MPT table. */ 68076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00002]; 68176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - 68276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The field returned in RNR Naks generated when a page fault is detected. 68376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman It has no effect when on-demand-paging is not used. */ 68476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00013]; 68576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 68676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00020]; 68776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 68876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32]. 68976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. 69076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 69176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 69276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0]. 69376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. 69476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 69576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 69676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00040]; 69776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 69876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 69976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 70076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Multicast Support Parameters */ 70176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 70276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_multicastparam_st { /* Little Endian */ 70376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32]. 70476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The base address must be aligned to the entry size. 70576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if multicast is not supported. */ 70676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 70776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. 70876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The base address must be aligned to the entry size. 70976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if multicast is not supported. */ 71076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 71176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 71276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 71376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry. 71476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be greater than 5 (to allow CTRL and GID sections). 71576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman That implies the number of QPs per MC table entry. */ 71676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00010]; 71776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 71876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2) 71976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman INIT_HCA - the required number of entries 72076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */ 72176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x0000f]; 72276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 72376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */ 72476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00013]; 72576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function 72676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Default hash function 72776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved */ 72876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00005]; 72976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 73076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 73176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 73276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 73376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 73476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QPC/EEC/CQC/EQC/RDB Parameters */ 73576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 73676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_qpcbaseaddr_st { /* Little Endian */ 73776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 73876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 73976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32] 74076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size */ 74176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 74276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */ 74376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 74476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpc_base_addr_l[0x00019];/* QPC Base Address [31:7] 74576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size */ 74676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 74776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 74876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 74976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eec_base_addr_h[0x00020];/* EEC Base Address [63:32] 75076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size. 75176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if RD is not supported. */ 75276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 75376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */ 75476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00002]; 75576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eec_base_addr_l[0x00019];/* EEC Base Address [31:7] 75676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size 75776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if RD is not supported. */ 75876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 75976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32] 76076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size 76176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 76276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 76376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */ 76476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5] 76576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size 76676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 76776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 76876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32] 76976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size */ 77076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 77176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */ 77276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00001]; 77376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6] 77476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size */ 77576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 77676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00040]; 77776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 77876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32] 77976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table has same number of entries as QPC table. 78076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. */ 78176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 78276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0] 78376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table has same number of entries as QPC table. 78476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. */ 78576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 78676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00040]; 78776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 78876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32] 78976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table has same number of entries as EEC table. 79076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. 79176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if RD is not supported. */ 79276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 79376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0] 79476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table has same number of entries as EEC table. 79576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. 79676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if RD is not supported. */ 79776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 79876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00040]; 79976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 80076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32] 80176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if EQs are not supported. 80276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. */ 80376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 80476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs. 80576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 6 or less in InfiniHost-III-EX. */ 80676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00002]; 80776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6] 80876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if EQs are not supported. 80976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. */ 81076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 81176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00040]; 81276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 81376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32]. 81476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if remote RDMA reads are not supported. 81576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Please refer to QP and EE chapter for further explanation on RDB allocation. */ 81676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 81776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0]. 81876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to RDB entry size (32 bytes). 81976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to zero if remote RDMA reads are not supported. 82076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Please refer to QP and EE chapter for further explanation on RDB allocation. */ 82176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 82276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00040]; 82376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 82476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 82576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 82676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Header_Log_Register */ 82776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 82876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_header_log_register_st { /* Little Endian */ 82976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t place_holder[0x00020]; 83076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 83176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00060]; 83276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 83376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 83476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 83576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Performance Monitors */ 83676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 83776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_performance_monitors_st { /* Little Endian */ 83876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */ 83976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */ 84076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */ 84176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00001]; 84276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 84376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 84476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 84576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00001]; 84676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 84776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 84876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 84976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00001]; 85076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 85176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 85276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 85376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00001]; 85476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */ 85576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00003]; 85676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */ 85776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00003]; 85876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 85976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clock_counter[0x00020]; 86076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 86176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_counter1[0x00020]; 86276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 86376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */ 86476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 86576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 86676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 86776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Receive segment format */ 86876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 86976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_ctrl_recv_st { /* Little Endian */ 87076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_recv_wqe_segment_next_st wqe_segment_next; 87176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 87276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00002]; 87376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00001]; 87476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00001]; 87576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x0001c]; 87676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 87776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00020]; 87876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 87976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 88076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 88176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* MLX WQE segment format */ 88276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 88376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_ctrl_mlx_st { /* Little Endian */ 88476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00002]; 88576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e[0x00001]; /* WQE event */ 88676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */ 88776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t icrc[0x00002]; /* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved. 3 - Leave last dword as is. Last dword must not be 0x0. */ 88876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 88976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; 89076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_statrate[0x00004]; 89176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */ 89276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */ 89376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x0000e]; 89476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 89576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */ 89676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */ 89776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 89876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00040]; 89976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 90076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 90176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 90276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send WQE segment format */ 90376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 90476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_send_wqe_segment_st { /* Little Endian */ 90576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_next_st wqe_segment_next;/* Send wqe segment next */ 90676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 90776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */ 90876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 90976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */ 91076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 91176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */ 91276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 91376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */ 91476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 91576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00180]; 91676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 91776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */ 91876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 91976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */ 92076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 92176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 92276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 92376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */ 92476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 92576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */ 92676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 92776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */ 92876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 92976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00200]; 93076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 93176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 93276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 93376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QP and EE Context Entry */ 93476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 93576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_queue_pair_ee_context_entry_st { /* Little Endian */ 93676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 93776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t de[0x00001]; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */ 93876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 93976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm) 94076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11-Migrated 94176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00-Armed 94276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 01-Rearm 94376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10-Reserved 94476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Should be set to 11 for UD QPs and for QPs which do not support APM */ 94576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00003]; 94676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t st[0x00003]; /* Service type (invalid in EE context): 94776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 000-Reliable Connection 94876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 001-Unreliable Connection 94976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 010-Reliable Datagram 95076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 011-Unreliable Datagram 95176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 111-MLX transport (raw bits injection). Used for management QPs and RAW */ 95276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00009]; 95376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t state[0x00004]; /* QP/EE state: 95476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - RST 95576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - INIT 95676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2 - RTR 95776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - RTS 95876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4 - SQEr 95976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5 - SQD (Send Queue Drained) 96076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6 - ERR 96176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7 - Send Queue Draining 96276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8 - Reserved 96376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9 - Suspended 96476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman A- F - Reserved 96576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */ 96676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 96776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00020]; 96876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 96976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sched_queue[0x00004]; /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */ 97076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */ 97176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00003]; 97276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes. 97376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 97476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */ 97576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00001]; 97676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. 97776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 97876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */ 97976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00001]; 98076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max. 98176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be equal to MTU for UD and MLX QPs. */ 98276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative): 98376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - 256 bytes 98476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - 512 98576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - 1024 98676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x4 - 2048 98776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved 98876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 98976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Should be configured to 0x4 for UD and MLX QPs. */ 99076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 99176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t usr_page[0x00018]; /* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */ 99276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00008]; 99376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 99476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained 99576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is valid for QUERY and ERR2RST commands only. */ 99676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00008]; 99776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 99876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */ 99976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00008]; 100076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 100176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00040]; 100276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 100376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */ 100476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 100576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */ 100676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 100776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rdd[0x00018]; /* Reliable Datagram Domain */ 100876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00008]; 100976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 101076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* QP protection domain. Not valid (reserved) in EE context. */ 101176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x00008]; 101276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 101376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_base_adr_h[0x00020];/* Bits 63:32 of WQE address for both SQ and RQ. 101476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Reserved for EE context. */ 101576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 101676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_lkey[0x00020]; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */ 101776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 101876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x00003]; 101976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ssc[0x00001]; /* Send Signaled Completion 102076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - all send WQEs generate CQEs. 102176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - only send WQEs with C bit set generate completion. 102276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid (reserved) in EE context. */ 102376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sic[0x00001]; /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */ 102476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only). 102576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */ 102676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only). 102776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */ 102876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */ 102976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x00001]; 103076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sae[0x00001]; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */ 103176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t swe[0x00001]; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */ 103276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sre[0x00001]; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */ 103376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */ 103476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x00002]; 103576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */ 103676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t flight_lim[0x00004]; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue. 103776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Number of outstanding messages is 2^Flight_Lim. 103876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use 0xF for unlimited number of outstanding messages. */ 103976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */ 104076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x00020]; 104276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */ 104476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved18[0x00008]; 104576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */ 104776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved19[0x00008]; 104876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved20[0x00006]; 105076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t snd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */ 105176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 105276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t snd_db_record_index[0x00020];/* Index in the UAR Context Table Entry. 105376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record. 105476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The entry is obtained via the usr_page field. 105576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid for EE. */ 105676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 105776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */ 105876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved21[0x00008]; 105976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 106076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */ 106176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved22[0x00008]; 106276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 106376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved23[0x00003]; 106476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rsc[0x00001]; /* 1 - all receive WQEs generate CQEs. 106576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - only receive WQEs with C bit set generate completion. 106676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid (reserved) in EE context. 106776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 106876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ric[0x00001]; /* Invalid Credits. 106976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - place "Invalid Credits" to ACKs sent from this queue. 107076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - ACKs report the actual number of end to end credits on the connection. 107176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid (reserved) in EE context. 107276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be set to 1 on QPs which are attached to SRQ. */ 107376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved24[0x00008]; 107476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */ 107576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */ 107676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */ 107776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved25[0x00005]; 107876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. 107976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0 for EE context. */ 108076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved26[0x00008]; 108176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 108276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */ 108376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). 108476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid (reserved) in EE context. */ 108576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved27[0x00003]; 108676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 108776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved28[0x00005]; 108876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer. 108976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */ 109076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 109176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */ 109276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved29[0x00008]; 109376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 109476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved30[0x00006]; 109576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */ 109676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 109776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue. 109876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record. 109976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The entry is obtained via the usr_page field. 110076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid for EE. */ 110176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 110276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams. 110376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message. 110476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid (reserved) in EE context. */ 110576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 110676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. 110776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */ 110876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */ 110976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved31[0x00007]; 111076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 111176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */ 111276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved32[0x00008]; 111376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 111476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. 111576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in SQ initialization. 111676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (QUERY_QPEE only). */ 111776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ. 111876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in RQ initialization. 111976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (QUERY_QPEE only). */ 112076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 112176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved33[0x00040]; 112276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 112376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 112476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 112576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Clear Interrupt [63:0] */ 112676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 112776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_clr_int_st { /* Little Endian */ 112876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32] 112976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 113076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This register is write-only. Reading from this register will cause undefined result 113176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 113276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 113376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0] 113476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 113576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This register is write-only. Reading from this register will cause undefined result */ 113676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 113776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 113876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 113976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* EQ_Arm_DB_Region */ 114076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 114176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_eq_arm_db_region_st { /* Little Endian */ 114276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq_x_arm_h[0x00020]; /* EQ[63:32] X state. 114376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This register is used to Arm EQs when setting the appropriate bits. */ 114476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 114576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq_x_arm_l[0x00020]; /* EQ[31:0] X state. 114676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This register is used to Arm EQs when setting the appropriate bits. */ 114776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 114876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 114976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 115076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* EQ Set CI DBs Table */ 115176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 115276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_eq_set_ci_table_st { /* Little Endian */ 115376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */ 115476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 115576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 115676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 115776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */ 115876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 115976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 116076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */ 116276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00020]; 116476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */ 116676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 116876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */ 117076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00020]; 117276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */ 117476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 117676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */ 117876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00020]; 118076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */ 118276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00020]; 118476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */ 118676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00020]; 118876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */ 119076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00020]; 119276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */ 119476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00020]; 119676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */ 119876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00020]; 120076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */ 120276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00020]; 120476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */ 120676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x00020]; 120876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */ 121076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x00020]; 121276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */ 121476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x00020]; 121676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */ 121876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x00020]; 122076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */ 122276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x00020]; 122476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */ 122676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved18[0x00020]; 122876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */ 123076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved19[0x00020]; 123276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */ 123476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved20[0x00020]; 123676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */ 123876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved21[0x00020]; 124076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */ 124276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved22[0x00020]; 124476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */ 124676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved23[0x00020]; 124876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */ 125076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved24[0x00020]; 125276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */ 125476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved25[0x00020]; 125676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */ 125876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved26[0x00020]; 126076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */ 126276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved27[0x00020]; 126476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */ 126676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved28[0x00020]; 126876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */ 127076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 127176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved29[0x00020]; 127276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 127376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */ 127476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 127576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved30[0x00020]; 127676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 127776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */ 127876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 127976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved31[0x00020]; 128076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 128176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */ 128276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 128376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved32[0x00020]; 128476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 128576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */ 128676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 128776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved33[0x00020]; 128876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 128976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */ 129076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 129176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved34[0x00020]; 129276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 129376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */ 129476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 129576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved35[0x00020]; 129676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 129776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */ 129876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 129976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved36[0x00020]; 130076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 130176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */ 130276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 130376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved37[0x00020]; 130476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 130576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */ 130676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 130776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved38[0x00020]; 130876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 130976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */ 131076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 131176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved39[0x00020]; 131276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 131376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */ 131476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 131576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved40[0x00020]; 131676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 131776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */ 131876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 131976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved41[0x00020]; 132076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 132176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */ 132276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 132376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved42[0x00020]; 132476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 132576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */ 132676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 132776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved43[0x00020]; 132876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 132976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */ 133076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 133176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved44[0x00020]; 133276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 133376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */ 133476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 133576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved45[0x00020]; 133676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 133776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */ 133876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 133976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved46[0x00020]; 134076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 134176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */ 134276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 134376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved47[0x00020]; 134476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 134576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */ 134676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 134776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved48[0x00020]; 134876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 134976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */ 135076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 135176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved49[0x00020]; 135276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 135376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */ 135476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 135576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved50[0x00020]; 135676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 135776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */ 135876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 135976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved51[0x00020]; 136076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 136176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */ 136276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 136376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved52[0x00020]; 136476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 136576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */ 136676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 136776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved53[0x00020]; 136876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 136976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */ 137076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved54[0x00020]; 137276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */ 137476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved55[0x00020]; 137676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */ 137876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved56[0x00020]; 138076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 138176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */ 138276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 138376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved57[0x00020]; 138476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 138576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */ 138676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 138776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved58[0x00020]; 138876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 138976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */ 139076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 139176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved59[0x00020]; 139276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 139376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */ 139476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 139576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved60[0x00020]; 139676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 139776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */ 139876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 139976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved61[0x00020]; 140076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 140176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */ 140276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 140376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved62[0x00020]; 140476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 140576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */ 140676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 140776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved63[0x00020]; 140876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 140976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 141076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 141176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* InfiniHost-III-EX Configuration Registers */ 141276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 141376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_configuration_registers_st { /* Little Endian */ 141476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x403400]; 141576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 141676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */ 141776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 141876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x3fcb20]; 141976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 142076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 142176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 142276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QP_DB_Record */ 142376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 142476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_qp_db_record_st { /* Little Endian */ 142576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */ 142676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 142776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 142876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00005]; 142976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t res[0x00003]; /* 0x3 for SQ 143076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x4 for RQ 143176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x5 for SRQ */ 143276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qp_number[0x00018]; /* QP number */ 143376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 143476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 143576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* CQ_ARM_DB_Record */ 143776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_cq_arm_db_record_st { /* Little Endian */ 143976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */ 144076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 144176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd[0x00003]; /* 0x0 - No command 144276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter. 144376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter. 144476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated 144576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Other - Reserved */ 144676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */ 144776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t res[0x00003]; /* Must be 0x2 */ 144876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_number[0x00018]; /* CQ number */ 144976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 145076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 145176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* CQ_CI_DB_Record */ 145376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_cq_ci_db_record_st { /* Little Endian */ 145576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[0x00020]; /* CQ counter */ 145676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 145776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00005]; 145876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t res[0x00003]; /* Must be 0x1 */ 145976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_number[0x00018]; /* CQ number */ 146076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 146176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 146276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 146376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Virtual_Physical_Mapping */ 146476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 146576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_virtual_physical_mapping_st { /* Little Endian */ 146676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */ 146776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 146876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0000c]; 146976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */ 147076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 147176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */ 147276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 147376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */ 147476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00006]; 147576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */ 147676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 147776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 147876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* MOD_STAT_CFG */ 148076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 148176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_mod_stat_cfg_st { /* Little Endian */ 148276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */ 148376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00001]; 148476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq[0x00001]; /* When set SRQs are supported */ 148576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq_m[0x00001]; /* Modify SRQ parameters */ 148676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00018]; 148776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 148876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x007e0]; 148976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 149076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 149176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 149276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* SRQ Context */ 149376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 149476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_srq_context_st { /* Little Endian */ 149576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srqn[0x00018]; /* SRQ number */ 149676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. 149776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maximum value is 0x10, i.e. 16M WQEs. */ 149876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t state[0x00004]; /* SRQ State: 149976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1111 - SW Ownership 150076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0000 - HW Ownership 150176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0001 - Error 150276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ 150376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 150476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t l_key[0x00020]; /* memory key (L-Key) to be used to access WQEs. */ 150576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 150676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue. 150776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record. 150876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The entry is obtained via the usr_page field. */ 150976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 151076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t usr_page[0x00018]; /* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */ 151176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00005]; 151276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */ 151376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 151476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_addr_h[0x00020]; /* Bits 63:32 of WQE address (WQE base address) */ 151576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 151676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00006]; 151776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */ 151876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 151976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* SRQ protection domain. */ 152076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00008]; 152176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 152276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. 152376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ 152476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */ 152576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 152676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. 152776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in SRQ initialization. 152876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (QUERY_SRQ only). */ 152976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00010]; 153076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 153176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00060]; 153276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 153376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 153476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 153576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* PBL */ 153676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 153776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_pbl_st { /* Little Endian */ 153876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */ 153976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 154076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */ 154176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 154276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */ 154376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 154476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */ 154576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 154676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */ 154776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 154876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */ 154976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 155076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */ 155176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 155276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */ 155376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 155476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 155576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 155676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Performance Counters */ 155776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 155876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_performance_counters_st { /* Little Endian */ 155976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sqpc_access_cnt[0x00020];/* SQPC cache access count */ 156076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */ 156276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 156476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rqpc_access_cnt[0x00020];/* RQPC cache access count */ 156676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */ 156876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 157076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqc_access_cnt[0x00020];/* CQC cache access count */ 157276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */ 157476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 157676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tpt_access_cnt[0x00020];/* TPT cache access count */ 157876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */ 158076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 158176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */ 158276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 158376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00620]; 158476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 158576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 158676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 158776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Transport and CI Error Counters */ 158876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 158976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_transport_and_ci_error_counters_st { /* Little Endian */ 159076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */ 159176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */ 159376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */ 159576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */ 159776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */ 159976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */ 160176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */ 160376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */ 160576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error. 160776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Incremented each time a CQE with error is generated */ 160876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error. 161076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Incremented each time a CQE with error is generated */ 161176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 161276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 161376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 161476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */ 161576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 161676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 161776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 161876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */ 161976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 162076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */ 162176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 162276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 162376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 162476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors 162576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK-Invalid Request on: 162676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1. Unsupported OpCode: Responder detected an unsupported OpCode. 162776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such 162876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman as a missing "Last" packet. 162976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Note: there is no PSN error, thus this does not indicate a dropped packet. */ 163076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 163176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors. 163276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK may or may not be sent. 163376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only): 163476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Inbound request OpCode was either reserved, or was for a function not supported by this 163576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman QP. (E.g. RDMA or ATOMIC on QP not set up for this). 163676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion. 163776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3. Too many RDMA READ or ATOMIC Requests: There were more requests received 163876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman and not ACKed than allowed for the connection. 163976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder 164076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman detected an error in the sequence of OpCodes; a missing "Last" packet 164176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder 164276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman detected an error in the sequence of OpCodes; a missing "First" packet 164376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able 164476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman buffer space. 164576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7. Length error: RDMA WRITE request message contained too much or too little pay-load 164676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman data compared to the DMA length advertised in the first or only packet. 164776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8. Length error: Payload length was not consistent with the opcode: 164876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman a: 0 byte <= "only" <= PMTU bytes 164976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman b: ("first" or "middle") == PMTU bytes 165076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman c: 1byte <= "last" <= PMTU bytes 165176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9. Length error: Inbound message exceeded the size supported by the CA port. */ 165276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 165376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors. 165476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK-Remote Access Error on: 165576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman R_Key Violation: Responder detected an invalid R_Key while executing an RDMA 165676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Request. */ 165776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 165876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors. 165976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman R_Key Violation Responder detected an R_Key violation while executing an RDMA 166076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman request. 166176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK may or may not be sent. */ 166276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 166376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors. 166476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK-Remote Operation Error on: 166576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Remote Operation Error: Responder encountered an error, (local to the responder), 166676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman which prevented it from completing the request. */ 166776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 166876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors. 166976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK-Remote Operation Error on: 167076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing 167176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman the packet. 167276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2. Remote Operation Error: Responder encountered an error, (local to the responder), 167376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman which prevented it from completing the request. */ 167476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 167576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */ 167676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 167776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 167876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 167976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */ 168076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 168176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00020]; 168276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 168376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */ 168476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 168576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */ 168676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 168776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00040]; 168876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 168976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */ 169076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 169176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00020]; 169276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 169376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */ 169476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 169576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00020]; 169676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 169776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */ 169876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 169976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00380]; 170076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 170176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */ 170276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 170376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */ 170476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 170576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */ 170676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 170776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00020]; 170876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 170976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */ 171076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 171176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */ 171276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 171376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */ 171476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 171576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00020]; 171676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 171776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */ 171876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 171976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x003e0]; 172076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 172176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */ 172276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 172376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */ 172476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 172576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */ 172676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 172776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x002a0]; 172876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 172976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 173076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 173176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - HCR Completion Event */ 173276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 173376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_hcr_completion_event_st { /* Little Endian */ 173476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t token[0x00010]; /* HCR Token */ 173576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 173676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 173776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 173876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 173976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00008]; /* HCR Status */ 174076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00018]; 174176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 174276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */ 174376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 174476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */ 174576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 174676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 174776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 174876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 174976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 175076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Completion with Error CQE */ 175176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 175276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_completion_with_error_st { /* Little Endian */ 175376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t myqpn[0x00018]; /* Indicates the QP for which completion is being reported */ 175476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 175576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 175676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00060]; 175776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 175876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00010]; 175976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vendor_code[0x00008]; 176076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome: 176176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x01 - Local Length Error 176276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x02 - Local QP Operation Error 176376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x03 - Local EE Context Operation Error 176476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x04 - Local Protection Error 176576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x05 - Work Request Flushed Error 176676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x06 - Memory Window Bind Error 176776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x10 - Bad Response Error 176876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x11 - Local Access Error 176976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x12 - Remote Invalid Request Error 177076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x13 - Remote Access Error 177176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x14 - Remote Operation Error 177276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x15 - Transport Retry Counter Exceeded 177376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x16 - RNR Retry Counter Exceeded 177476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x20 - Local RDD Violation Error 177576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x21 - Remote Invalid RD Request 177676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x22 - Remote Aborted Error 177776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x23 - Invalid EE Context Number 177876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x24 - Invalid EE Context State 177976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - Reserved 178076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */ 178176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 178276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 178376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 178476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00006]; 178576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_addr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */ 178676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 178776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00007]; 178876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */ 178976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00010]; 179076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for. 179176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 179276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The following values are reported in case of completion with error: 179376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xFE - For completion with error on Receive Queues 179476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xFF - For completion with error on Send Queues */ 179576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 179676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 179776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 179876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Resize CQ Input Mailbox */ 179976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 180076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_resize_cq_st { /* Little Endian */ 180176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 180276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 180376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_addr_h[0x00020]; /* Start address of CQ[63:32]. 180476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be aligned on CQE size (32 bytes) */ 180576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 180676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_addr_l[0x00020]; /* Start address of CQ[31:0]. 180776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be aligned on CQE size (32 bytes) */ 180876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 180976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00018]; 181076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */ 181176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00003]; 181276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 181376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00060]; 181476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 181576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */ 181676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 181776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00100]; 181876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 181976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 182076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 182176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* MAD_IFC Input Modifier */ 182276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 182376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_mad_ifc_input_modifier_st { /* Little Endian */ 182476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */ 182576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set. 182676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Required for trap generation when BKey check is enabled and for global routed packets. */ 182776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00007]; 182876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. 182976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is required for trap generation upon MKey/BKey validation. */ 183076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 183176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 183276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 183376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* MAD_IFC Input Mailbox */ 183476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 183576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_mad_ifc_st { /* Little Endian */ 183676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */ 183776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 183876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD. 183976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 184076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 184176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 184276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD. 184376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 184476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 184576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 184676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. 184776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 184876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD. 184976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 185076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid. 185176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 185276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00004]; 185376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD. 185476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 185576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 185676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD. 185776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 185876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00010]; 185976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 186076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00180]; 186176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 186276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. 186376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid if Mad_extended_info bit (in the input modifier) and g bit are set. 186476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise this field is reserved. */ 186576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 186676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x004c0]; 186776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 186876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 186976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 187076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Query Debug Message */ 187176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 187276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_query_debug_msg_st { /* Little Endian */ 187376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */ 187476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 187576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t v[0x00001]; /* Physical translation is valid */ 187676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0000b]; 187776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */ 187876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 187976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */ 188076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 188176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */ 188276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 188376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */ 188476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 188576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */ 188676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 188776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x000c0]; 188876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 188976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */ 189076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */ 189276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 189476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */ 189676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */ 189876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */ 190076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 190176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */ 190276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 190376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */ 190476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 190576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */ 190676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 190776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */ 190876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 190976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */ 191076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 191176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */ 191276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 191376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */ 191476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 191576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */ 191676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 191776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */ 191876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 191976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff6_addr[0x00020]; /* Address in firmware area of Trace Buffer 6 */ 192076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 192176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff6_size[0x00020]; /* Size of Trace Buffer 6 */ 192276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 192376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff7_addr[0x00020]; /* Address in firmware area of Trace Buffer 7 */ 192476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 192576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff7_size[0x00020]; /* Size of Trace Buffer 7 */ 192676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 192776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00400]; 192876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 192976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 193076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 193176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* User Access Region */ 193276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 193376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_uar_st { /* Little Endian */ 193476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */ 193576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 193676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */ 193776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 193876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 193976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 194076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */ 194176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 194276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x03ec0]; 194376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 194476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 194576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 194676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Receive doorbell */ 194776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 194876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_receive_doorbell_st { /* Little Endian */ 194976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 195076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */ 195176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 195276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 195376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00005]; 195476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */ 195576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00002]; 195676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */ 195776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 195876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 195976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 196076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* SET_IB Parameters */ 196176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 196276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_set_ib_st { /* Little Endian */ 196376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */ 196476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00011]; 196576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 196676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman system_image_guid and sig must be the same for all ports. */ 196776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0000d]; 196876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 196976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */ 197076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 197176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 197276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 197376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 197476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 197576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 197676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 197776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00180]; 197876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 197976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 198076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 198176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Multicast Group Member */ 198276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 198376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_mgm_entry_st { /* Little Endian */ 198476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00006]; 198576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number. 198676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables. 198776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman next_gid_index=0 means end of the chain. */ 198876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 198976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00060]; 199076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 199176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format. 199276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 199376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 199476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format. 199576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 199676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 199776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format. 199876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 199976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 200076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format. 200176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 200276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 200376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */ 200476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 200576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */ 200676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 200776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */ 200876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 200976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */ 201076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 201176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */ 201276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 201376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */ 201476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 201576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */ 201676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 201776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */ 201876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 201976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 202076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 202176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* INIT_IB Parameters */ 202276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 202376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_init_ib_st { /* Little Endian */ 202476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00004]; 202576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15. 202676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Legal values are 1,2,4 and 8. */ 202776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_width_cap[0x00004];/* IB Port Width 202876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - 1x 202976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - 1x, 4x 203076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208) 203176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else - Reserved */ 203276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtu_cap[0x00004]; /* Maximum MTU Supported 203376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x0 - Reserved 203476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - 256 203576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - 512 203676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - 1024 203776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x4 - 2048 203876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x5 - 0xF Reserved */ 203976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */ 204076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified. 204176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman node_guid and ng must be the same for all ports. */ 204276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 204376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman system_image_guid and sig must be the same for all ports. */ 204476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0000d]; 204576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 204676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */ 204776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00010]; 204876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 204976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port. 205076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 205176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00010]; 205276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 205376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00020]; 205476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 205576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */ 205676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 205776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */ 205876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 205976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set 206076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 206176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 206276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set 206376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 206476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 206576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 206676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 206776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 206876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 206976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 207076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 207176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x006c0]; 207276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 207376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 207476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 207576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Query Device Limitations */ 207676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 207776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_query_dev_lim_st { /* Little Endian */ 207876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 207976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 208076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */ 208176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00003]; 208276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use 208376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */ 208476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00004]; 208576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */ 208676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */ 208776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 208876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_ee[0x00005]; /* Log2 of the Maximum number of EE contexts supported */ 208976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00003]; 209076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use 209176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */ 209276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00004]; 209376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set. 209476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 209576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00007]; 209676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use 209776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1 209876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This parameter is valid only if the SRQ bit is set. */ 209976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 210076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */ 210176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00003]; 210276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use 210376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */ 210476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00004]; 210576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */ 210676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00008]; 210776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 210876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_eq[0x00003]; /* Log2 of the Maximum number of EQs */ 210976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00005]; 211076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use 211176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_rsvd_eqs-1 211276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If 0 - no resources are reserved. */ 211376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00004]; 211476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */ 211576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00002]; 211676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */ 211776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 211876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */ 211976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00002]; 212076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use 212176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */ 212276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x00004]; 212376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */ 212476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x00004]; 212576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use 212676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1 212776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 212876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 212976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x00020]; 213076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 213176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */ 213276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x0000a]; 213376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */ 213476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x0000a]; 213576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 213676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */ 213776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved18[0x00016]; 213876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use 213976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */ 214076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 214176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */ 214276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved19[0x0001f]; 214376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 214476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */ 214576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_vl[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */ 214676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_port_width[0x00004];/* IB Port Width 214776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - 1x 214876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - 1x, 4x 214976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - 1x, 4x or 12x 215076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else - Reserved */ 215176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_mtu[0x00004]; /* Maximum MTU Supported 215276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x0 - Reserved 215376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - 256 215476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - 512 215576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - 1024 215676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x4 - 2048 215776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x5 - 0xF Reserved */ 215876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb. 215976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */ 216076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved20[0x0000b]; 216176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 216276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */ 216376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved21[0x0001c]; 216476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 216576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */ 216676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved22[0x0000c]; 216776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported 216876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bit 0 - full bw 216976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bit 1 - 1/4 bw 217076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bit 2 - 1/8 bw 217176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bit 3 - 1/2 bw; */ 217276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 217376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved23[0x00020]; 217476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 217576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rc[0x00001]; /* RC Transport supported */ 217676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uc[0x00001]; /* UC Transport Supported */ 217776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ud[0x00001]; /* UD Transport Supported */ 217876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rd[0x00001]; /* RD Transport Supported */ 217976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t raw_ipv6[0x00001]; /* Raw IPv6 Transport Supported */ 218076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t raw_ether[0x00001]; /* Raw Ethertype Transport Supported */ 218176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq[0x00001]; /* SRQ is supported 218276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 218376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ipo_ib_checksum[0x00001];/* IP over IB checksum is supported */ 218476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */ 218576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */ 218676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved24[0x00006]; 218776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mw[0x00001]; /* Memory windows supported */ 218876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */ 218976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */ 219076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */ 219176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */ 219276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */ 219376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved25[0x00002]; 219476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pg[0x00001]; /* Paging on demand supported */ 219576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r[0x00001]; /* Router mode supported */ 219676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved26[0x00006]; 219776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 219876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2). 219976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */ 220076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved27[0x00008]; 220176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */ 220276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved28[0x00006]; 220376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use 220476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_reserved_uars-1 220576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Note that UAR number num_reserved_uars is always for the kernel. */ 220676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 220776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved29[0x00020]; 220876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 220976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */ 221076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */ 221176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved30[0x00008]; 221276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 221376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */ 221476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */ 221576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved31[0x00008]; 221676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 221776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved32[0x00040]; 221876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 221976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */ 222076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT. 222176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_reserved_mcgs-1 222276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If 0 - no resources are reserved. */ 222376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved33[0x00004]; 222476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */ 222576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved34[0x00008]; 222676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 222776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */ 222876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved35[0x00006]; 222976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use 223076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_reserved_rdds-1. 223176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If 0 - no resources are reserved. */ 223276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_pd[0x00006]; /* Log2 of the maximum number of PDs */ 223376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved36[0x00006]; 223476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use 223576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_reserved_pds-1 223676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If 0 - no resources are reserved. */ 223776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 223876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved37[0x000c0]; 223976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 224076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device 224176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 224276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eec_entry_sz[0x00010]; /* EEC Entry Size for the device 224376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 224476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 224576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device 224676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 224776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eeec_entry_sz[0x00010];/* Extended EEC entry size for the device 224876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 224976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 225076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device 225176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 225276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device 225376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 225476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 225576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size 225676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 225776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device 225876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 225976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 226076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mpt_entry_sz[0x00010]; /* MPT entry size in Bytes for the device. 226176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 226276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device. 226376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 8 bytes */ 226476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 226576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */ 226676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism: 226776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Type 2A - QP Number Association; or 226876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Type 2B - QP Number and PD Association. */ 226976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */ 227076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. (The device does not supports Block List) */ 227176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */ 227276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */ 227376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved38[0x00002]; 227476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_pbl_sz[0x00006]; /* Log2 of the Maximum Physical Buffer List size in Bytes supported by this HCA when invoking the Allocate L_Key verb. 227576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 227676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved39[0x00012]; 227776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 227876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */ 227976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 228076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lamr[0x00001]; /* When set the device requires local attached memory in order to operate. 228176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman When set, ICM pages, Firmware Area and ICM auxiliary pages must be allocated in the local attached memory. */ 228276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved40[0x0001f]; 228376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 228476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */ 228576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 228676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */ 228776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 228876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved41[0x002c0]; 228976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 229076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 229176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 229276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QUERY_ADAPTER Parameters Block */ 229376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 229476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_query_adapter_st { /* Little Endian */ 229576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 229676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 229776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00018]; 229876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */ 229976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 230076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00060]; 230176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 230276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_vsd_st vsd; 230376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 230476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 230576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 230676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QUERY_FW Parameters Block */ 230776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 230876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_query_fw_st { /* Little Endian */ 230976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */ 231076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */ 231176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 231276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */ 231376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */ 231476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 231576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */ 231676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0000e]; 231776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_h_mode[0x00001]; /* Hermon mode. If '1', then WQE and AV format is the advanced format */ 231876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t zb_wq_cq[0x00001]; /* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */ 231976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 232076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */ 232176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00017]; 232276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dt[0x00001]; /* Debug Trace Support 232376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Debug trace is not supported 232476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Debug trace is supported */ 232576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 232676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */ 232776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x0001f]; 232876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 232976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00060]; 233076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 233176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address. 233276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Points to 64 bit register. */ 233376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 233476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address. 233576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Points to 64 bit register. */ 233676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 233776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00040]; 233876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 233976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t error_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */ 234076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 234176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t error_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */ 234276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 234376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t error_buf_size[0x00020];/* Size in words */ 234476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 234576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 234676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 234776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address. 234876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Points to 64 bit register. 234976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Setting bit x in the offset, arms EQ number x. 235076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 235176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 235276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address. 235376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Points to 64 bit register. 235476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Setting bit x in the offset, arms EQ number x. */ 235576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 235676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address. 235776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Points to a the EQ Set CI DBs Table base address. */ 235876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 235976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address. 236076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Points to a the EQ Set CI DBs Table base address. */ 236176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 236276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_dw1[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 236376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_dw0[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 236476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 236576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_dw3[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 236676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_dw2[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 236776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 236876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_dw5[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 236976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_dw4[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 237076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 237176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_dw7[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 237276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_dw6[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 237376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 237476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */ 237576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 237676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_db_addr_base_l[0x00020];/* Low bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */ 237776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 237876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x004c0]; 237976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 238076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 238176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 238276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* ACCESS_LAM */ 238376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 238476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_access_lam_st { /* Little Endian */ 238576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_access_lam_inject_errors_st access_lam_inject_errors; 238676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 238776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 238876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 238976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 239076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 239176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* ENABLE_LAM Parameters Block */ 239276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 239376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_enable_lam_st { /* Little Endian */ 239476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lam_start_adr_h[0x00020];/* LAM start address [63:32] */ 239576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 239676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lam_start_adr_l[0x00020];/* LAM start address [31:0] */ 239776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 239876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lam_end_adr_h[0x00020];/* LAM end address [63:32] */ 239976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 240076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lam_end_adr_l[0x00020];/* LAM end address [31:0] */ 240176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 240276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t di[0x00002]; /* Data Integrity Configuration: 240376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00 - none 240476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 01 - Parity 240576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10 - ECC Detection Only 240676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - ECC With Correction */ 240776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ap[0x00002]; /* Auto Precharge Mode 240876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00 - No auto precharge 240976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 01 - Auto precharge per transaction 241076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10 - Auto precharge per 64 bytes 241176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - reserved */ 241276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dh[0x00001]; /* When set, LAM is Hidden and can not be accessed directly from the PCI bus. */ 241376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0001b]; 241476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 241576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00160]; 241676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 241776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_dimminfo_st dimm0; /* Logical DIMM 0 Parameters */ 241876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 241976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_dimminfo_st dimm1; /* Logical DIMM 1 Parameters */ 242076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 242176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00400]; 242276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 242376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 242476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 242576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Memory Access Parameters for UD Address Vector Table */ 242676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 242776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_udavtable_memory_parameters_st { /* Little Endian */ 242876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */ 242976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 243076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */ 243176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00005]; 243276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */ 243376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 243476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 243576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 243676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 243776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* INIT_HCA & QUERY_HCA Parameters Block */ 243876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 243976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_init_hca_st { /* Little Endian */ 244076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00060]; 244176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 244276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00010]; 244376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t time_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented. 244476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond) 244576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman When sets to Zero, timestamp reporting in the CQE is disabled. 244676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This feature is currently not supported. 244776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 244876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */ 244976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 245076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00008]; 245176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t router_qp[0x00010]; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet. 245276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid only if RE bit is set */ 245376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00007]; 245476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t re[0x00001]; /* Router Mode Enable 245576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */ 245676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 245776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t udp[0x00001]; /* UD Port Check Enable 245876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Port field in Address Vector is ignored 245976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */ 246076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations 246176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Host is Little Endian 246276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Host is Big endian 246376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 246476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00001]; 246576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */ 246676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sph[0x00001]; /* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet 246776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet 246876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 246976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rph[0x00001]; /* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet 247076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet 247176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 247276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00002]; 247376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t responder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester . 247476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman responder_exu/16 = (number of responder exu engines)/(total number of engines) 247576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Legal values are 0x0-0xF. 0 is "auto". 247676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 247776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 247876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00004]; 247976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_quota[0x0000f]; /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */ 248076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */ 248176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 248276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00040]; 248376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 248476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters; 248576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 248676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00100]; 248776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 248876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_multicastparam_st multicast_parameters; 248976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 249076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00080]; 249176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 249276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_tptparams_st tpt_parameters; 249376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 249476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00080]; 249576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 249676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_uar_params_st uar_parameters;/* UAR Parameters */ 249776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 249876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00600]; 249976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 250076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 250176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 250276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event Queue Context Table Entry */ 250376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 250476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_eqc_st { /* Little Endian */ 250576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 250676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t st[0x00004]; /* Event delivery state machine 250776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x9 - Armed 250876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xA - Fired 250976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xB - Always_Armed (auto-rearm) 251076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved */ 251176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00005]; 251276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t oi[0x00001]; /* Oerrun ignore. 251376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If set, HW will not check EQ full condition when writing new EQEs. */ 251476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tr[0x00001]; /* Translation Required. If set - EQ access undergo address translation. */ 251576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00005]; 251676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00004]; /* 0 - SW ownership 251776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - HW ownership 251876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_EQ and HW2SW_EQ commands only */ 251976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00004]; /* EQ status: 252076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0000 - OK 252176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1010 - EQ write failure 252276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_EQ and HW2SW_EQ commands only */ 252376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 252476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_h[0x00020];/* Start Address of Event Queue[63:32]. */ 252576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 252676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_l[0x00020];/* Start Address of Event Queue[31:0]. 252776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be aligned on 32-byte boundary */ 252876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 252976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00018]; 253076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_eq_size[0x00005]; /* Amount of entries in this EQ is 2^log_eq_size. 253176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Log_eq_size must be bigger than 1. 253276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */ 253376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00003]; 253476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 253576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 253676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 253776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t intr[0x00008]; /* Interrupt (message) to be generated to report event to INT layer. 253876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express. 253976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported). 254076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman All other values are reserved and should not be used. 254176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 254276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */ 254376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00018]; 254476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 254576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* PD to be used to access EQ */ 254676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00008]; 254776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 254876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lkey[0x00020]; /* Memory key (L-Key) to be used to access EQ */ 254976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 255076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00040]; 255176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 255276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue. 255376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be initalized to zero while opening EQ */ 255476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 255576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA. 255676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be initalized to zero while opening EQ. */ 255776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 255876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00080]; 255976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 256076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 256176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 256276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Memory Translation Table (MTT) Entry */ 256376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 256476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_mtt_st { /* Little Endian */ 256576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 256676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 256776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */ 256876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0000b]; 256976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 257076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 257176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 257276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 257376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Memory Protection Table (MPT) Entry */ 257476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 257576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_mpt_st { /* Little Endian */ 257676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 257776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */ 257876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */ 257976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lr[0x00001]; /* If set - local read access enabled */ 258076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lw[0x00001]; /* If set - local write access enabled */ 258176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rr[0x00001]; /* If set - remote read access enabled. */ 258276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rw[0x00001]; /* If set - remote write access enabled */ 258376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t a[0x00001]; /* If set - remote Atomic access is enabled */ 258476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eb[0x00001]; /* If set - Bind is enabled. Valid for region entry only. */ 258576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0000c]; 258676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00004]; /* Region/Window Status 258776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xF - not valid (SW ownership) 258876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - FREE state 258976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else - HW ownership 259076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Unbound Type I windows are doneted reg_wnd_len field equals zero. 259176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Unbound Type II windows are donated by Status=FREE. */ 259276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 259376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. 259476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman page_size should be less than 20. */ 259576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 259676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t type[0x00001]; /* Applicable for windows only, must be zero for regions 259776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Type one window 259876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Type two window */ 259976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */ 260076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 260176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. 260276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 260376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 260476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* Protection Domain */ 260576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00001]; 260676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. 260776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be set for type2 windows and non-shared physical memory regions. 260876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */ 260976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t zb[0x00001]; /* When set, this region is Zero Based Region */ 261076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */ 261176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. 261276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. 261376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail. 261476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 261576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00003]; 261676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 261776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */ 261876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 261976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */ 262076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 262176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */ 262276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 262376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */ 262476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 262576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. 262676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to. 262776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */ 262876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 262976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t win_cnt[0x00020]; /* Number of windows bound to this region. Valid for regions only. 263076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */ 263176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 263276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 263376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 263476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_adr_h[0x00006]; /* Base (first) address of the MTT relative to MTT base in the ICM */ 263576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x0001a]; 263676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 263776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00003]; 263876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_adr_l[0x0001d]; /* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */ 263976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 264076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_sz[0x00020]; /* Number of MTT entries allocated for this MR. 264176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved. 264276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */ 264376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 264476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00040]; 264576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 264676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 264776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 264876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Completion Queue Context Table Entry */ 264976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 265076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_completion_queue_context_st { /* Little Endian */ 265176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 265276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t st[0x00004]; /* Event delivery state machine 265376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x0 - reserved 265476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x9 - ARMED (Request for Notification) 265576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x6 - ARMED SOLICITED (Request Solicited Notification) 265676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xA - FIRED 265776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved 265876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 265976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in CQ initialization. 266076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_CQ and HW2SW_CQ commands only. */ 266176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00005]; 266276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled. 266376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */ 266476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x0000a]; 266576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00004]; /* CQ status 266676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0000 - OK 266776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1001 - CQ overflow 266876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1010 - CQ write failure 266976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_CQ and HW2SW_CQ commands only */ 267076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 267176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_h[0x00020];/* Start address of CQ[63:32]. 267276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be aligned on CQE size (32 bytes) */ 267376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 267476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_l[0x00020];/* Start address of CQ[31:0]. 267576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be aligned on CQE size (32 bytes) */ 267676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 267776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */ 267876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries). 267976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */ 268076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00003]; 268176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 268276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00020]; 268376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 268476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t c_eqn[0x00008]; /* Event Queue this CQ reports completion events to. 268576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid values are 0 to 63 268676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If configured to value other than 0-63, completion events will not be reported on the CQ. */ 268776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00018]; 268876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 268976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* Protection Domain to be used to access CQ. 269076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same PD of the CQ L_Key. */ 269176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00008]; 269276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 269376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */ 269476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 269576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t last_notified_indx[0x00020];/* Maintained by HW. 269676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for QUERY_CQ and HW2SW_CQ commands only. */ 269776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 269876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t solicit_producer_indx[0x00020];/* Maintained by HW. 269976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for QUERY_CQ and HW2SW_CQ commands only. 270076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 270176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 270276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t consumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ. 270376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in CQ initialization. 270476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_CQ and HW2SW_CQ commands only. */ 270576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 270676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t producer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ. 270776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added.. 270876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */ 270976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 271076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn[0x00018]; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table 271176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_CQ and HW2SW_CQ commands only */ 271276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00008]; 271376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 271476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry. 271576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record. 271676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This value can be retrieved from the HW in the QUERY_CQ command. */ 271776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 271876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_state_db_record[0x00020];/* Index in the UAR Context Table Entry. 271976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record. 272076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This value can be retrieved from the HW in the QUERY_CQ command. */ 272176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 272276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00020]; 272376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 272476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 272576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 272676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* GPIO_event_data */ 272776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 272876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_gpio_event_data_st { /* Little Endian */ 272976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00060]; 273076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 273176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 273276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 273376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 273476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 273576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 273676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 273776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 273876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 273976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - QP/EE Events */ 274076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 274176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_qp_ee_event_st { /* Little Endian */ 274276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for */ 274376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 274476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 274576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 274676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 274776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x0001c]; 274876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field 274976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid on SRQ events */ 275076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00003]; 275176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 275276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00060]; 275376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 275476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 275576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 275676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* InfiniHost-III-EX Type0 Configuration Header */ 275776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 275876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_mt25208_type0_st { /* Little Endian */ 275976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */ 276076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode 276176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25218 (decimal) - InfiniHost-III EX mode (the mode described in this manual) 276276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode 276376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 276476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 276576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t command[0x00010]; /* PCI Command Register */ 276676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00010]; /* PCI Status Register */ 276776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 276876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t revision_id[0x00008]; 276976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t class_code_hca_class_code[0x00018]; 277076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 277176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */ 277276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t latency_timer[0x00008]; 277376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t header_type[0x00008]; /* hardwired to zero */ 277476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bist[0x00008]; 277576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 277676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */ 277776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 277876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */ 277976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 278076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */ 278176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 278276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */ 278376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00010]; 278476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */ 278576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 278676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */ 278776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 278876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */ 278976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00010]; 279076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 279176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 279276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 279376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 279476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cardbus_cis_pointer[0x00020]; 279576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 279676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */ 279776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */ 279876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 279976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 280076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x0000a]; 280176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 280276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 280376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */ 280476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00018]; 280576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 280676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 280776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 280876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t interrupt_line[0x00008]; 280976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t interrupt_pin[0x00008]; 281076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t min_gnt[0x00008]; 281176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_latency[0x00008]; 281276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 281376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00100]; 281476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 281576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msi_cap_id[0x00008]; 281676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msi_next_cap_ptr[0x00008]; 281776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msi_en[0x00001]; 281876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t multiple_msg_cap[0x00003]; 281976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t multiple_msg_en[0x00003]; 282076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cap_64_bit_addr[0x00001]; 282176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00008]; 282276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 282376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg_addr_l[0x00020]; 282476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 282576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg_addr_h[0x00020]; 282676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 282776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg_data[0x00010]; 282876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00010]; 282976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 283076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00080]; 283176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 283276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */ 283376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_next_cap_ptr[0x00008]; 283476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h 283576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [3] PME clock - 0h 283676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [4] RsvP 283776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [5] Device specific initialization - 0h 283876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [8:6] AUX current - 0h 283976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [9] D1 support - 0h 284076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [10] D2 support - 0h 284176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [15:11] PME support - 0h */ 284276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 284376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */ 284476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_control_status_brdg_ext[0x00008]; 284576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t data[0x00008]; 284676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 284776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00040]; 284876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 284976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */ 285076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vpd_next_cap_id[0x00008]; 285176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vpd_address[0x0000f]; 285276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f[0x00001]; 285376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 285476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vpd_data[0x00020]; 285576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 285676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00040]; 285776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 285876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */ 285976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pciex_next_cap_ptr[0x00008]; 286076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h 286176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [7:4] Device/Port Type - 0h 286276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [8] Slot implemented - 0h 286376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [13:9] Interrupt message number 286476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 286576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 286676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h 286776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [4:3] Phantom Function supported - 0h 286876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [5] Extended Tag Filed supported - 0h 286976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [8:6] Endpoint L0s Acceptable Latency - TBD 287076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [11:9] Endpoint L1 Acceptable Latency - TBD 287176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [12] Attention Button Present - configured through InfiniBurn 287276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [13] Attention Indicator Present - configured through InfiniBurn 287376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [14] Power Indicator Present - configured through InfiniBurn 287476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [25:18] Captured Slot Power Limit Value 287576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [27:26] Captured Slot Power Limit Scale */ 287676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 287776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t device_control[0x00010]; 287876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t device_status[0x00010]; 287976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 288076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h 288176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [9:4] Maximum Link Width - 8h 288276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [11:10] Active State Power Management Support - 3h 288376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [14:12] L0s Exit Latency - TBD 288476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [17:15] L1 Exit Latency - TBD 288576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [31:24] Port Number - 0h */ 288676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 288776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t link_control[0x00010]; 288876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h 288976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [9:4] Negotiated Link Width 289076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [12] Slot clock configuration - 1h */ 289176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 289276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00260]; 289376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 289476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */ 289576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t capability_version[0x00004];/* 1h */ 289676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_capability_offset[0x0000c];/* 0h */ 289776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 289876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status 289976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4 Data Link Protocol Error Status 290076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Poisoned TLP Status 290176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13 Flow Control Protocol Error Status 290276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14 Completion Timeout Status 290376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15 Completer Abort Status 290476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16 Unexpected Completion Status 290576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17 Receiver Overflow Status 290676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 18 Malformed TLP Status 290776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19 ECRC Error Status 290876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20 Unsupported Request Error Status */ 290976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 291076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask 291176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4 Data Link Protocol Error Mask 291276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Poisoned TLP Mask 291376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13 Flow Control Protocol Error Mask 291476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14 Completion Timeout Mask 291576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15 Completer Abort Mask 291676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16 Unexpected Completion Mask 291776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17 Receiver Overflow Mask 291876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 18 Malformed TLP Mask 291976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19 ECRC Error Mask 292076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20 Unsupported Request Error Mask */ 292176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 292276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity 292376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4 Data Link Protocol Error Severity 292476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Poisoned TLP Severity 292576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13 Flow Control Protocol Error Severity 292676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14 Completion Timeout Severity 292776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15 Completer Abort Severity 292876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16 Unexpected Completion Severity 292976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17 Receiver Overflow Severity 293076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 18 Malformed TLP Severity 293176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19 ECRC Error Severity 293276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20 Unsupported Request Error Severity */ 293376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 293476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status 293576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6 Bad TLP Status 293676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7 Bad DLLP Status 293776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8 REPLAY_NUM Rollover Status 293876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Replay Timer Timeout Status */ 293976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 294076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask 294176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6 Bad TLP Mask 294276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7 Bad DLLP Mask 294376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8 REPLAY_NUM Rollover Mask 294476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Replay Timer Timeout Mask */ 294576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 294676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]; 294776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 294876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_header_log_register_st header_log_register; 294976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 295076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x006a0]; 295176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 295276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 295376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 295476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event Data Field - Performance Monitor */ 295576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 295676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_performance_monitor_event_st { /* Little Endian */ 295776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */ 295876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 295976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC 296076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x02 - RQPC 296176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x03 - CQC 296276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x04 - Rkey 296376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x05 - TLB 296476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x06 - port0 296576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x07 - port1 */ 296676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00018]; 296776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 296876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 296976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 297076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 297176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 297276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - Page Faults */ 297376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 297476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_page_fault_event_data_st { /* Little Endian */ 297576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 297676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 297776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 297876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 297976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */ 298076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 298176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */ 298276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00003]; 298376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */ 298476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */ 298576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */ 298676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */ 298776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */ 298876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 298976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */ 299076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 299176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 299276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */ 299376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 299476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 299576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 299676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* WQE segments format */ 299776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 299876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_wqe_segment_st { /* Little Endian */ 299976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */ 300076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 300176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00280]; 300276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 300376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */ 300476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 300576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00100]; 300676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 300776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_ctrl_recv_st recv_wqe_segment_ctrl;/* Receive segment format */ 300876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 300976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00080]; 301076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 301176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 301276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 301376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - Port State Change */ 301476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 301576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_port_state_change_st { /* Little Endian */ 301676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 301776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 301876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0001c]; 301976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */ 302076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 302176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 302276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00060]; 302376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 302476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 302576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 302676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - Completion Queue Error */ 302776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 302876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_completion_queue_error_st { /* Little Endian */ 302976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 303076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 303176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 303276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 303376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 303476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t syndrome[0x00008]; /* Error syndrome 303576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x01 - CQ overrun 303676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x02 - CQ access violation error */ 303776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00018]; 303876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 303976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00060]; 304076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 304176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 304276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 304376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - Completion Event */ 304476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 304576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_completion_event_st { /* Little Endian */ 304676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 304776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 304876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 304976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x000a0]; 305076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 305176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 305276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 305376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event Queue Entry */ 305476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 305576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_event_queue_entry_st { /* Little Endian */ 305676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. 305776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Defined for events which have sub types, zero elsewhere. */ 305876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 305976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_type[0x00008]; /* Event Type */ 306076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 306176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 306276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */ 306376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 306476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00007]; 306576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00001]; /* Owner of the entry 306676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 SW 306776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 HW */ 306876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00018]; 306976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 307076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 307176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 307276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QP/EE State Transitions Command Parameters */ 307376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 307476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_qp_ee_state_transitions_st { /* Little Endian */ 307576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */ 307676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 307776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 307876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 307976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data */ 308076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 308176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x009c0]; 308276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 308376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 308476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 308576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Completion Queue Entry Format */ 308676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 308776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_completion_queue_entry_st { /* Little Endian */ 308876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 308976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00004]; 309076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ver[0x00004]; /* CQE version. 309176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 for InfiniHost-III-EX */ 309276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 309376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_ee[0x00018]; /* EE context (for RD only). 309476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Invalid for Bind and Nop operation on RD. 309576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For non RD services this filed reports the CQE timestamp. The Timestamp is a free running counter that is incremented every TimeStampGranularity tick. The counter rolls-over when it reaches saturation. TimeStampGranularity is configured in the INIT_HCA command. This feature is currently not supported. 309676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 309776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t checksum_15_8[0x00008];/* Checksum[15:8] - See IPoverIB checksum offloading chapter */ 309876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 309976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */ 310076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t checksum_7_0[0x00008]; /* Checksum[7:0] - See IPoverIB checksum offloading chapter */ 310176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 310276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */ 310376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. 310476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid in responder of UD QP CQE only. 310576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */ 310676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g[0x00001]; /* GRH present indicator. Valid in Responder of UD QP CQE only. */ 310776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ipok[0x00001]; /* IP OK - See IPoverIB checksum offloading chapter */ 310876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00003]; 310976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; /* Service Level of the message. Valid in Responder of UD QP CQE only. */ 311076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 311176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only. 311276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet. 311376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet. 311476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived. 311576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If Opcode field indicates that this was send and invalidate, this field contains the key that was invalidated. 311676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For CQE of send queue of the reliable connection service (but send and invalide), bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message. */ 311776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 311876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data actually transferred (valid for receive queue completions only) */ 311976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 312076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00006]; 312176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_adr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */ 312276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 312376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00007]; 312476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */ 312576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x0000f]; 312676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t s[0x00001]; /* If set, completion is reported for Send queue, if cleared - receive queue. */ 312776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for. 312876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field. 312976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field. 313076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only) 313176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 313276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The following values are reported in case of completion with error: 313376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xFE - For completion with error on Receive Queues 313476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xFF - For completion with error on Send Queues */ 313576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 313676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 313776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 313876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 313976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 314076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_ecc_detect_event_data_st { /* Little Endian */ 314176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 314276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 314376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cause_lsb[0x00001]; 314476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 314576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cause_msb[0x00001]; 314676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 314776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_rmw[0x00001]; 314876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_src_id[0x00003]; 314976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_da[0x00002]; 315076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ba[0x00002]; 315176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00011]; 315276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t overflow[0x00001]; 315376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 315476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ra[0x00010]; 315576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ca[0x00010]; 315676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 315776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 315876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 315976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - ECC Detection Event */ 316076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 316176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_scrubbing_event_st { /* Little Endian */ 316276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 316376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 316476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause: 316576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman single ECC error in the 64bit lsb data, on the rise edge of the clock */ 316676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 316776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause: 316876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman single ECC error in the 64bit msb data, on the fall edge of the clock */ 316976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 317076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_rmw[0x00001]; /* transaction type: 317176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - read 317276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - read/modify/write */ 317376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */ 317476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_da[0x00002]; /* Error DIMM address */ 317576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ba[0x00002]; /* Error bank address */ 317676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00011]; 317776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */ 317876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 317976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ra[0x00010]; /* Error row address */ 318076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ca[0x00010]; /* Error column address */ 318176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 318276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 318376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 318476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Miscellaneous Counters */ 318576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 318676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_misc_counters_st { /* Little Endian */ 318776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ddr_scan_cnt[0x00020]; /* Number of times whole of LAM was scanned */ 318876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 318976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x007e0]; 319076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 319176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 319276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 319376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* LAM_EN Output Parameter */ 319476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 319576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_lam_en_out_param_st { /* Little Endian */ 319676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 319776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 319876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 319976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 320076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Extended_Completion_Queue_Entry */ 320176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 320276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_extended_completion_queue_entry_st { /* Little Endian */ 320376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 320476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 320576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 320676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 320776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 320876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 320976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_eq_cmd_doorbell_st { /* Little Endian */ 321076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 321176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 321276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 321376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 321476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 0 */ 321576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 321676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct arbelprm_arbel_prm_st { /* Little Endian */ 321776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */ 321876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 321976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x7ff00]; 322076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */ 322276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x7f000]; 322476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */ 322676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x7ff00]; 322876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_completion_event_st completion_event;/* Event_data Field - Completion Event */ 323076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x7ff40]; 323276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */ 323476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x7ff40]; 323676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */ 323876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x7ff40]; 324076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_wqe_segment_st wqe_segment;/* WQE segments format */ 324276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x7f000]; 324476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */ 324676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x7ff40]; 324876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */ 325076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0xfff20]; 325276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */ 325476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x7f000]; 325676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */ 325876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00040]; 326076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_gpio_event_data_st gpio_event_data; 326276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x7fe40]; 326476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 326676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x7ff00]; 326876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */ 327076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x7fa00]; 327276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_address_path_st address_path;/* Address Path */ 327476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x7ff00]; 327676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */ 327876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x7fe00]; 328076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */ 328276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x7fe00]; 328476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */ 328676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x7ffc0]; 328876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_eqc_st eqc; /* Event Queue Context Table Entry */ 329076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved18[0x7fe00]; 329276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_performance_monitors_st performance_monitors;/* Performance Monitors */ 329476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved19[0x7ff80]; 329676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */ 329876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved20[0xfff20]; 330076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */ 330276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved21[0x7f000]; 330476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */ 330676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved22[0x7fc00]; 330876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */ 331076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved23[0x7ffc0]; 331276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_multicastparam_st multicastparam;/* Multicast Support Parameters */ 331476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved24[0x7ff00]; 331676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */ 331876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved25[0x7ff00]; 332076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 332176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_enable_lam_st enable_lam;/* ENABLE_LAM Parameters Block */ 332276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 332376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_access_lam_st access_lam; 332476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 332576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved26[0x7f700]; 332676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 332776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_dimminfo_st dimminfo;/* Logical DIMM Information */ 332876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 332976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved27[0x7ff00]; 333076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 333176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */ 333276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 333376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved28[0x7f800]; 333476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 333576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */ 333676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 333776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved29[0x7f800]; 333876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 333976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_query_dev_lim_st query_dev_lim;/* Query Device Limitations */ 334076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 334176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved30[0x7f800]; 334276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 334376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_uar_params_st uar_params;/* UAR Parameters */ 334476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 334576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved31[0x7ff00]; 334676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 334776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_init_ib_st init_ib; /* INIT_IB Parameters */ 334876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 334976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved32[0x7f800]; 335076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 335176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgm_entry_st mgm_entry;/* Multicast Group Member */ 335276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 335376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved33[0x7fe00]; 335476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 335576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_set_ib_st set_ib; /* SET_IB Parameters */ 335676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 335776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved34[0x7fe00]; 335876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 335976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */ 336076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 336176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved35[0x7ff80]; 336276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 336376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */ 336476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 336576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved36[0x7ffc0]; 336676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 336776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */ 336876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 336976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved37[0x7ffc0]; 337076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 337176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */ 337276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 337376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved38[0xfffc0]; 337476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 337576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_uar_st uar; /* User Access Region */ 337676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 337776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved39[0x7c000]; 337876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 337976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mgmqp_st mgmqp; /* Multicast Group Member QP */ 338076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 338176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved40[0x7ffe0]; 338276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 338376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */ 338476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 338576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved41[0x7f800]; 338676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 338776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */ 338876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 338976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved42[0x00900]; 339076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 339176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */ 339276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 339376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved43[0x7e6e0]; 339476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 339576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */ 339676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 339776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved44[0x7fe00]; 339876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 339976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */ 340076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 340176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved45[0x7ff00]; 340276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 340376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */ 340476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 340576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved46[0x7ff40]; 340676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 340776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */ 340876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 340976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved47[0x7f000]; 341076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 341176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_performance_counters_st performance_counters;/* Performance Counters */ 341276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 341376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved48[0x9ff800]; 341476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 341576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 341676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 341776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved49[0x7ff00]; 341876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 341976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_pbl_st pbl; /* Physical Buffer List */ 342076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 342176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved50[0x7ff00]; 342276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 342376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_srq_context_st srq_context;/* SRQ Context */ 342476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 342576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved51[0x7fe80]; 342676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 342776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */ 342876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 342976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved52[0x7f800]; 343076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 343176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */ 343276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 343376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved53[0x7ff80]; 343476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 343576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */ 343676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 343776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved54[0x7ffc0]; 343876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 343976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */ 344076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 344176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved55[0x7ffc0]; 344276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 344376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_qp_db_record_st qp_db_record;/* QP_DB_Record */ 344476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 344576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved56[0x1fffc0]; 344676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 344776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */ 344876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 344976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */ 345076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 345176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved57[0x01000]; 345276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 345376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_eq_arm_db_region_st eq_arm_db_region;/* EQ Arm Doorbell Region */ 345476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 345576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved58[0x00fc0]; 345676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 345776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct arbelprm_clr_int_st clr_int; /* Clear Interrupt Register */ 345876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 345976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved59[0xffcfc0]; 346076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 346176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 346276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif /* H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H */ 3463