176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This software is available to you under a choice of one of two 376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman licenses. You may choose to be licensed under the terms of the GNU 476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman General Public License (GPL) Version 2, available at 576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD 676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman license, available in the LICENSE.TXT file accompanying this 776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman software. These details are also available at 876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman <http://openib.org/license.html>. 976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 1176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 1376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 1476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 1576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 1776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman SOFTWARE. 1876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. 2076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman*/ 2176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2276d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanFILE_LICENCE ( GPL2_ONLY ); 2376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/*** 2576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman *** This file was generated at "Mon Apr 16 23:22:02 2007" 2676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman *** by: 2776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix hermonprm_ -bits -fixnames MT25408_PRM.csp 2876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman ***/ 2976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#ifndef H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H 3176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H 3276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* UD Address Vector */ 3476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_ud_address_vector_st { /* Little Endian */ 3676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* Protection Domain */ 3776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_number[0x00002]; /* Port number 3876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Port 1 3976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2 - Port 2 4076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved */ 4176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00005]; 4276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fl[0x00001]; /* force loopback */ 4376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 4476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 4576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 4676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 4776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 4876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 4976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 5076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. 5176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - 4X injection rate 5276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - 1X injection rate 5376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved 5476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 5576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00004]; 5676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table 5776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman mgid_index = (port_number-1) * 2^log_max_gid + gid_index 5876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Where: 5976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1. log_max_gid is taken from QUERY_DEV_CAP command 6076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2. gid_index is the index to the GID table */ 6176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00009]; 6276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 6376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 6476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 6576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ 6676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 6776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 6876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 6976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 7076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 7176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 7276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 7376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */ 7476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 7576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 7676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send doorbell */ 7876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_send_doorbell_st { /* Little Endian */ 8076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */ 8176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */ 8276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00002]; 8376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */ 8476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */ 8576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 8676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */ 8776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 8876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 8976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 9076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 9176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment data inline */ 9376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_data_inline_st { /* Little Endian */ 9576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */ 9676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00015]; 9776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t always1[0x00001]; 9876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 9976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */ 10076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 10176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 10276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 10376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 10476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 10576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment data ptr */ 10776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_data_ptr_st { /* Little Endian */ 10976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t byte_count[0x0001f]; 11076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t always0[0x00001]; 11176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 11276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t l_key[0x00020]; 11376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 11476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t local_address_h[0x00020]; 11576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 11676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t local_address_l[0x00020]; 11776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 11876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 11976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment rd */ 12176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_local_invalidate_segment_st { /* Little Endian */ 12376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 12476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 12576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_key[0x00018]; 12676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 12776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 12876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x000a0]; 12976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 13076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 13176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Fast_Registration_Segment ####michal - doesn't match PRM (fields were added, see below) new table size in bytes - 0x30 */ 13376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_fast_registration_segment_st { /* Little Endian */ 13576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0001b]; 13676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */ 13776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */ 13876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */ 13976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */ 14076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */ 14176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 14276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list ### michal - this field is replaced with mem_key .32 */ 14376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 14476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. ###michal-this field is replaced with pbl_ptr_63_32 */ 14576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 14676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. 14776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman page_size should be less than 20. ###michal - field doesn't exsist (see replacement above) */ 14876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 14976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t zb[0x00001]; /* Zero Based Region ###michal - field doesn't exsist (see replacement above) */ 15076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list ###michal - field doesn't exsist (see replacement above) */ 15176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 15276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */ 15376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 15476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */ 15576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 15676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */ 15776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 15876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */ 15976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 16076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 16176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment atomic */ 16376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_atomic_st { /* Little Endian */ 16576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t swap_add_h[0x00020]; 16676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 16776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t swap_add_l[0x00020]; 16876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 16976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t compare_h[0x00020]; 17076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 17176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t compare_l[0x00020]; 17276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 17376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 17476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment remote address */ 17676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_remote_address_st { /* Little Endian */ 17876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t remote_virt_addr_h[0x00020]; 17976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 18076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t remote_virt_addr_l[0x00020]; 18176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 18276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rkey[0x00020]; 18376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 18476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 18576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 18676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 18776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 18876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* end wqe segment bind */ 18976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_bind_st { /* Little Endian */ 19176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0001d]; 19276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */ 19376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window. 19476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 19576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */ 19676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 19776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0001e]; 19876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */ 19976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t type[0x00001]; /* Window type. 20076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Type one window 20176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Type two window 20276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 20376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 20476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */ 20576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 20676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */ 20776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 20876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_h[0x00020]; 20976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 21076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_address_l[0x00020]; 21176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 21276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t length_h[0x00020]; 21376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 21476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t length_l[0x00020]; 21576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 21676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 21776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment ud */ 21976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_ud_st { /* Little Endian */ 22176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 22276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 22376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t destination_qp[0x00018]; 22476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 22576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 22676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q_key[0x00020]; 22776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 22876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 22976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 23076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 23176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 23276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment rd */ 23376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 23476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_rd_st { /* Little Endian */ 23576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t destination_qp[0x00018]; 23676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 23776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 23876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q_key[0x00020]; 23976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 24076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 24176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 24276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 24376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 24476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send wqe segment ctrl */ 24576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 24676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_ctrl_send_st { /* Little Endian */ 24776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[0x00005]; 24876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0001a]; 24976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00001]; 25076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 25176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ds[0x00006]; /* descriptor (wqe) size in 16bytes chunk */ 25276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f[0x00001]; /* fence */ 25376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00019]; 25476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 25576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 25676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t s[0x00001]; /* Remote Solicited Event */ 25776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t c[0x00002]; /* completion required: 0b00 - no 0b11 - yes */ 25876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */ 25976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */ 26076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00001]; 26176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */ 26276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t src_remote_buf[0x00018]; 26376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 26476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */ 26576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 26676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 26776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 26876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Address Path # ###michal - match to PRM */ 26976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_address_path_st { /* Little Endian */ 27176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pkey_index[0x00007]; /* PKey table index */ 27276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00016]; 27376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sv[0x00001]; /* Service VLAN on QP */ 27476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cv[0x00001]; /* Customer VLAN in QP */ 27576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 27676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 27776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 27876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_lid_smac_idx[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 27976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t grh_ip[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 28076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 28176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 28276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 28376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. 28476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - 100% injection rate 28576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - 25% injection rate 28676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2 - 12.5% injection rate 28776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - 50% injection rate 28876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7: 2.5 Gb/s. 28976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8: 10 Gb/s. 29076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9: 30 Gb/s. 29176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10: 5 Gb/s. 29276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11: 20 Gb/s. 29376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12: 40 Gb/s. 29476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13: 60 Gb/s. 29576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14: 80 Gb/s. 29676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15: 120 Gb/s. */ 29776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00004]; 29876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table */ 29976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00004]; 30076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details. 30176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */ 30276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 30376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 30476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 30576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00004]; 30676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 30776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 30876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 30976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 31076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 31176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 31276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 31376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */ 31476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 31576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00008]; 31676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sp[0x00001]; /* if set, spoofing protection is enforced on this QP and Ethertype headers are restricted */ 31776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00002]; 31876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fvl[0x00001]; /* force VLAN */ 31976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fsip[0x00001]; /* force source IP */ 32076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fsm[0x00001]; /* force source MAC */ 32176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x0000a]; 32276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sched_queue[0x00008]; 32376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 32476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dmac_47_32[0x00010]; 32576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vlan_index[0x00007]; 32676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00001]; 32776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter_index[0x00008];/* Index to a table of counters that counts egress packets and bytes, 0xFF not valid */ 32876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 32976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dmac_31_0[0x00020]; 33076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 33176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 33276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 33376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* HCA Command Register (HCR) #### michal - match PRM */ 33476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 33576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_hca_command_register_st { /* Little Endian */ 33676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */ 33776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 33876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */ 33976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 34076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */ 34176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 34276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */ 34376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 34476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */ 34576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 34676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 34776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */ 34876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 34976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[0x0000c]; /* Command opcode */ 35076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */ 35176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00005]; 35276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t t[0x00001]; /* Toggle */ 35376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e[0x00001]; /* Event Request 35476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Don't report event (software will poll the GO bit) 35576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Report event to EQ when the command completes */ 35676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR) 35776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Software can write to the HCR only if Go bit is cleared. 35876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */ 35976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared) 36076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */ 36176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 36276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 36376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 36476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* CQ Doorbell */ 36576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 36676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_cq_cmd_doorbell_st { /* Little Endian */ 36776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn[0x00018]; /* CQ number accessed */ 36876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ 36976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x0 - Reserved 37076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter. 37176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter. 37276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated 37376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Other - Reserved */ 37476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00001]; 37576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ. 37676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited 37776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman completion or Request notification for multiple completions doorbells after receiving completion notification. 37876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is initialized to Zero */ 37976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 38076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 38176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */ 38276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 38376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 38476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 38576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* RD-send doorbell */ 38676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 38776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_rd_send_doorbell_st { /* Little Endian */ 38876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 38976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram) 39076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be zero for Nop and Bind operations */ 39176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 39276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 39376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 39476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 39576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_send_doorbell_st send_doorbell;/* Send Parameters */ 39676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 39776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 39876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 39976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Multicast Group Member QP #### michal - match PRM */ 40076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 40176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mgmqp_st { /* Little Endian */ 40276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */ 40376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00006]; 40476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t blck_lb[0x00001]; /* Block self-loopback messages arriving to this qp */ 40576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */ 40676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 40776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 40876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 40976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* vsd */ 41076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 41176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_vsd_st { /* Little Endian */ 41276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw0[0x00020]; 41376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 41476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw1[0x00020]; 41576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 41676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw2[0x00020]; 41776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 41876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw3[0x00020]; 41976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 42076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw4[0x00020]; 42176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 42276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw5[0x00020]; 42376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 42476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw6[0x00020]; 42576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 42676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw7[0x00020]; 42776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 42876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw8[0x00020]; 42976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 43076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw9[0x00020]; 43176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 43276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw10[0x00020]; 43376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 43476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw11[0x00020]; 43576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 43676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw12[0x00020]; 43776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 43876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw13[0x00020]; 43976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 44076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw14[0x00020]; 44176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 44276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw15[0x00020]; 44376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 44476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw16[0x00020]; 44576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 44676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw17[0x00020]; 44776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 44876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw18[0x00020]; 44976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 45076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw19[0x00020]; 45176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 45276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw20[0x00020]; 45376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 45476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw21[0x00020]; 45576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 45676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw22[0x00020]; 45776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 45876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw23[0x00020]; 45976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 46076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw24[0x00020]; 46176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 46276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw25[0x00020]; 46376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 46476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw26[0x00020]; 46576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 46676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw27[0x00020]; 46776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 46876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw28[0x00020]; 46976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw29[0x00020]; 47176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw30[0x00020]; 47376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw31[0x00020]; 47576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw32[0x00020]; 47776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 47876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw33[0x00020]; 47976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw34[0x00020]; 48176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw35[0x00020]; 48376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw36[0x00020]; 48576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw37[0x00020]; 48776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 48876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw38[0x00020]; 48976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw39[0x00020]; 49176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw40[0x00020]; 49376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw41[0x00020]; 49576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw42[0x00020]; 49776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 49876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw43[0x00020]; 49976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw44[0x00020]; 50176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw45[0x00020]; 50376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw46[0x00020]; 50576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw47[0x00020]; 50776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 50876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw48[0x00020]; 50976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw49[0x00020]; 51176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw50[0x00020]; 51376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw51[0x00020]; 51576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw52[0x00020]; 51776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 51876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw53[0x00020]; 51976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 52076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw54[0x00020]; 52176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 52276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vsd_dw55[0x00020]; 52376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 52476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 52576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 52676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* UAR Parameters */ 52776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 52876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_uar_params_st { /* Little Endian */ 52976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 53076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 53176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page. 53276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Size of UAR Page is 4KB*2^UAR_Page_Size */ 53376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */ 53476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00014]; 53576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 53676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x000a0]; 53776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 53876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 53976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 54076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Translation and Protection Tables Parameters */ 54176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 54276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_tptparams_st { /* Little Endian */ 54376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dmpt_base_adr_h[0x00020];/* dMPT - Memory Protection Table base physical address [63:32]. 54476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Entry size is 64 bytes. 54576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. 54676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 54776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 54876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dmpt_base_adr_l[0x00020];/* dMPT - Memory Protection Table base physical address [31:0]. 54976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Entry size is 64 bytes. 55076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. 55176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 55276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 55376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_dmpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the dMPT table. */ 55476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00002]; 55576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - 55676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The field returned in RNR Naks generated when a page fault is detected. 55776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman It has no effect when on-demand-paging is not used. */ 55876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00013]; 55976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 56076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00020]; 56176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 56276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32]. 56376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. 56476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 56576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 56676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0]. 56776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. 56876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 56976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 57076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmpt_base_adr_h[0x00020];/* cMPT - Memory Protection Table base physical address [63:32]. 57176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Entry size is 64 bytes. 57276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. */ 57376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 57476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmpt_base_adr_l[0x00020];/* cMPT - Memory Protection Table base physical address [31:0]. 57576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Entry size is 64 bytes. 57676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to its size. */ 57776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 57876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 57976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 58076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Multicast Support Parameters #### michal - match PRM */ 58176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 58276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_multicastparam_st { /* Little Endian */ 58376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32]. 58476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The base address must be aligned to the entry size. 58576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if multicast is not supported. */ 58676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 58776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. 58876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The base address must be aligned to the entry size. 58976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if multicast is not supported. */ 59076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 59176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 59276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 59376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_mc_table_entry_sz[0x00005];/* Log2 of the Size of multicast group member (MGM) entry. 59476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be greater than 5 (to allow CTRL and GID sections). 59576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman That implies the number of QPs per MC table entry. */ 59676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0000b]; 59776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00010]; 59876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 59976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_mc_table_hash_sz[0x00005];/* Number of entries in multicast DGID hash table (must be power of 2) 60076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman INIT_HCA - the required number of entries 60176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */ 60276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x0001b]; 60376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 60476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */ 60576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00013]; 60676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function 60776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Default hash function 60876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved */ 60976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00005]; 61076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 61176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00020]; 61276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 61376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 61476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 61576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QPC/EEC/CQC/EQC/RDB Parameters #### michal - doesn't match PRM (field name are differs. see below) */ 61676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 61776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_qpcbaseaddr_st { /* Little Endian */ 61876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 61976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32] 62176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size */ 62276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */ 62476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpc_base_addr_l[0x0001b];/* QPC Base Address [31:7] 62576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size */ 62676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 62876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 62976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 63076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 63176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32] 63276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size 63376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 63476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 63576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */ 63676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5] 63776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size 63876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 63976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 64076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32] 64176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size */ 64276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 64376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */ 64476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqc_base_addr_l[0x0001b];/* CQC Base Address [31:6] 64576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned on its size */ 64676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 64776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00040]; 64876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 64976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t altc_base_addr_h[0x00020];/* AltC Base Address (altc_base_addr_h) [63:32] 65076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table has same number of entries as QPC table. 65176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. */ 65276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 65376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t altc_base_addr_l[0x00020];/* AltC Base Address (altc_base_addr_l) [31:0] 65476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table has same number of entries as QPC table. 65576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. */ 65676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 65776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00040]; 65876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 65976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t auxc_base_addr_h[0x00020]; 66076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 66176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t auxc_base_addr_l[0x00020]; 66276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 66376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00040]; 66476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 66576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32] 66676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if EQs are not supported. 66776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. */ 66876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 66976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_of_eq[0x00005];/* Log base 2 of number of supported EQs. 67076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 6 or less in InfiniHost-III-EX. */ 67176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqc_base_addr_l[0x0001b];/* EQC Base Address [31:6] 67276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Address may be set to 0xFFFFFFFF if EQs are not supported. 67376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to entry size. */ 67476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 67576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00040]; 67676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 67776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rdmardc_base_addr_h[0x00020];/* rdmardc_base_addr_h: Base address of table that holds remote read and remote atomic requests [63:32]. */ 67876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 67976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_num_rd[0x00003]; /* Log (base 2) of the maximum number of RdmaRdC entries per QP. This denotes the maximum number of outstanding reads/atomics as a responder. */ 68076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00002]; 68176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rdmardc_base_addr_l[0x0001b];/* rdmardc_base_addr_l: Base address of table that holds remote read and remote atomic requests [31:0]. 68276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Table must be aligned to RDB entry size (32 bytes). */ 68376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 68476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00040]; 68576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 68676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 68776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 68876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Header_Log_Register */ 68976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 69076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_header_log_register_st { /* Little Endian */ 69176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t place_holder[0x00020]; 69276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 69376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00060]; 69476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 69576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 69676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 69776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Performance Monitors */ 69876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 69976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_performance_monitors_st { /* Little Endian */ 70076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */ 70176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */ 70276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */ 70376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00001]; 70476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 70576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 70676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 70776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00001]; 70876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 70976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 71076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 71176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00001]; 71276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 71376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 71476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 71576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00001]; 71676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */ 71776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00003]; 71876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */ 71976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00003]; 72076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 72176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clock_counter[0x00020]; 72276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 72376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_counter1[0x00020]; 72476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 72576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */ 72676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 72776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 72876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 72976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* MLX WQE segment format */ 73076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 73176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_ctrl_mlx_st { /* Little Endian */ 73276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[0x00005]; /* must be 0xA = SEND */ 73376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0001a]; 73476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00001]; 73576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 73676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ds[0x00006]; /* Descriptor Size */ 73776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0001a]; 73876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 73976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 74076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00001]; 74176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t c[0x00002]; /* Create CQE (for "requested signalling" QP) */ 74276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t icrc[0x00001]; /* last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. 1 - Leave last dword as is. */ 74376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00003]; 74476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; 74576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_statrate[0x00004]; 74676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */ 74776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */ 74876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x0000e]; 74976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 75076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00010]; 75176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */ 75276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 75376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 75476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 75576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Send WQE segment format */ 75676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 75776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_send_wqe_segment_st { /* Little Endian */ 75876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */ 75976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 76076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */ 76176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 76276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */ 76376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 76476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */ 76576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 76676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00180]; 76776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 76876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */ 76976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 77076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */ 77176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 77276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 77376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 77476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */ 77576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 77676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */ 77776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 77876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */ 77976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 78076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00200]; 78176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 78276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 78376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 78476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QP and EE Context Entry */ 78576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 78676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_queue_pair_ee_context_entry_st { /* Little Endian */ 78776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 78876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00001]; 78976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 79076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm) 79176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11-Migrated 79276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00-Armed 79376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 01-Rearm 79476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10-Reserved 79576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Should be set to 11 for UD QPs and for QPs which do not support APM */ 79676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00003]; 79776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t st[0x00004]; /* Transport Service Type: RC: 0, UC: 1, RD: 2, UD: 3, FCMND:4, FEXCH:5, SRC:6, MLX 7, Raw Eth 11 */ 79876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00008]; 79976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t state[0x00004]; /* QP/EE state: 80076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - RST 80176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - INIT 80276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2 - RTR 80376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - RTS 80476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4 - SQEr 80576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5 - SQD (Send Queue Drained) 80676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6 - ERR 80776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7 - Send Queue Draining 80876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8 - Reserved 80976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9 - Suspended 81076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman A- F - Reserved 81176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */ 81276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 81376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; 81476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00008]; 81576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 81676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00004]; 81776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */ 81876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00003]; 81976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes. 82076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 82176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */ 82276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00001]; 82376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. 82476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 82576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */ 82676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00001]; 82776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max. 82876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be equal to MTU for UD and MLX QPs. */ 82976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative): 83076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - 256 bytes 83176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - 512 83276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - 1024 83376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x4 - 2048 83476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved 83576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 83676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Should be configured to 0x4 for UD and MLX QPs. */ 83776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 83876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t usr_page[0x00018]; /* UAR number to ring doorbells for this QP (aliased to doorbell and Blue Flame pages) */ 83976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00008]; 84076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 84176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained 84276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is valid for QUERY and ERR2RST commands only. */ 84376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00008]; 84476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 84576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */ 84676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00008]; 84776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 84876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */ 84976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 85076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */ 85176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 85276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x00003]; 85376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x00001]; 85476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x00001]; 85576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only). 85676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */ 85776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only). 85876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */ 85976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */ 86076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x00001]; 86176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rnr_retry[0x00003]; 86276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */ 86376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x00002]; 86476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */ 86576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved18[0x00004]; 86676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */ 86776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 86876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved19[0x00020]; 86976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 87076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */ 87176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved20[0x00008]; 87276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 87376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */ 87476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved21[0x00008]; 87576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 87676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved22[0x00040]; 87776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 87876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */ 87976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved23[0x00008]; 88076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 88176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */ 88276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved24[0x00008]; 88376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 88476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved25[0x00004]; 88576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ric[0x00001]; /* Invalid Credits. 88676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - place "Invalid Credits" to ACKs sent from this queue. 88776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - ACKs report the actual number of end to end credits on the connection. 88876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid (reserved) in EE context. 88976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be set to 1 on QPs which are attached to SRQ. */ 89076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved26[0x00001]; 89176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t page_offset[0x00006]; /* start address of wqes in first page (11:6), bits [5:0] reserved */ 89276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved27[0x00001]; 89376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */ 89476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */ 89576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */ 89676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved28[0x00005]; 89776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. 89876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0 for EE context. */ 89976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved29[0x00008]; 90076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 90176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */ 90276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). 90376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid (reserved) in EE context. */ 90476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved30[0x00003]; 90576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 90676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srcd[0x00010]; /* Scalable Reliable Connection Domain. Valid for SRC transport service */ 90776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved31[0x00010]; 90876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 90976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */ 91076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved32[0x00008]; 91176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 91276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t db_record_addr_h[0x00020];/* QP DB Record physical address */ 91376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 91476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved33[0x00002]; 91576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t db_record_addr_l[0x0001e];/* QP DB Record physical address */ 91676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 91776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams. 91876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message. 91976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid (reserved) in EE context. */ 92076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 92176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. 92276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */ 92376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */ 92476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved34[0x00007]; 92576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 92676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */ 92776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved35[0x00008]; 92876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 92976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. 93076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in SQ initialization. 93176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (QUERY_QPEE only). */ 93276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ. 93376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in RQ initialization. 93476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman (QUERY_QPEE only). */ 93576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 93676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved36[0x00040]; 93776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 93876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rmc_parent_qpn[0x00018];/* reliable multicast parent queue number */ 93976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hs[0x00001]; /* Header Separation. If set, the byte count of the first scatter entry will be ignored. The buffer specified by the first scatter entry will contain packet headers (up to TCP). CQE will report number of bytes scattered to the first scatter entry. Intended for use on IPoverIB on UD QP or Raw Ethernet QP. */ 94076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t is[0x00001]; /* when set - inline scatter is enabled for this RQ */ 94176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved37[0x00001]; 94276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rme[0x00002]; /* Reliable Multicast 94376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00 - disabled 94476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 01 - parent QP (requester) 94576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10 - child QP (requester) 94676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - responder QP 94776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Note that Reliable Multicast is a preliminary definition which can be subject to change. */ 94876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved38[0x00002]; 94976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mkey_rmp[0x00001]; /* If set, MKey used to access TPT for incoming RDMA-write request is calculated by adding MKey from the packet to base_MKey field in the QPC. Can be set only for QPs that are not target for RDMA-read request. */ 95076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 95176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t base_mkey[0x00018]; /* Base Mkey bits [31:8]. Lower 8 bits must be zero. */ 95276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rmc_peers[0x00008];/* Number of remote peers in Reliable Multicast group */ 95376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 95476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 95576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved39[0x00010]; 95676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 95776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved40[0x00002]; 95876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 95976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved41[0x00003]; 96076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 96176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 96276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vft_lan[0x0000c]; 96376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vft_prio[0x00003]; /* The Priority filed in the VFT header for FCP */ 96476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved42[0x00001]; 96576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cs_ctl[0x00009]; /* The Priority filed in the VFT header for FCP */ 96676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved43[0x00006]; 96776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ve[0x00001]; /* Should we add/check the VFT header */ 96876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 96976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t exch_base[0x00010]; /* For init QP only - The base exchanges */ 97076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved44[0x00008]; 97176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t exch_size[0x00004]; /* For CMMD QP only - The size (from base) exchanges is 2exchanges_size */ 97276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved45[0x00003]; 97376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fc[0x00001]; /* When set it mean that this QP is used for FIBRE CHANNEL. */ 97476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 97576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t remote_id[0x00018]; /* Peer NX port ID */ 97676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved46[0x00008]; 97776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 97876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fcp_mtu[0x0000a]; /* In 4*Bytes units. The MTU Size */ 97976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved47[0x00006]; 98076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_id_indx[0x00008]; /* Index to My NX port ID table */ 98176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vft_hop_count[0x00008];/* HopCnt value for the VFT header */ 98276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 98376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved48[0x000c0]; 98476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 98576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 98676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 98776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 98876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 98976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mcg_qp_dw_st { /* Little Endian */ 99076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; 99176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00006]; 99276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t blck_lb[0x00001]; 99376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00001]; 99476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 99576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 99676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 99776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Clear Interrupt [63:0] #### michal - match to PRM */ 99876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 99976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_clr_int_st { /* Little Endian */ 100076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32] 100176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 100276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This register is write-only. Reading from this register will cause undefined result 100376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 100476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 100576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0] 100676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 100776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This register is write-only. Reading from this register will cause undefined result */ 100876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 100976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 101076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 101176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* EQ Set CI DBs Table */ 101276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 101376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_eq_set_ci_table_st { /* Little Endian */ 101476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */ 101576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 101676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 101776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 101876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */ 101976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 102076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 102176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 102276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */ 102376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 102476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00020]; 102576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 102676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */ 102776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 102876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 102976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 103076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */ 103176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 103276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00020]; 103376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 103476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */ 103576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 103676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 103776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 103876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */ 103976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00020]; 104176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */ 104376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00020]; 104576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */ 104776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 104876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00020]; 104976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 105076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */ 105176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 105276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00020]; 105376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 105476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */ 105576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 105676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00020]; 105776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 105876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */ 105976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 106076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00020]; 106176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 106276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */ 106376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 106476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00020]; 106576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 106676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */ 106776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 106876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x00020]; 106976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 107076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */ 107176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 107276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x00020]; 107376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 107476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */ 107576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 107676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x00020]; 107776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 107876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */ 107976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 108076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x00020]; 108176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 108276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */ 108376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 108476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x00020]; 108576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 108676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */ 108776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 108876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved18[0x00020]; 108976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 109076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */ 109176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 109276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved19[0x00020]; 109376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 109476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */ 109576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 109676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved20[0x00020]; 109776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 109876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */ 109976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 110076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved21[0x00020]; 110176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 110276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */ 110376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 110476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved22[0x00020]; 110576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 110676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */ 110776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 110876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved23[0x00020]; 110976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 111076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */ 111176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 111276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved24[0x00020]; 111376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 111476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */ 111576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 111676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved25[0x00020]; 111776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 111876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */ 111976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 112076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved26[0x00020]; 112176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 112276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */ 112376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 112476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved27[0x00020]; 112576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 112676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */ 112776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 112876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved28[0x00020]; 112976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 113076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */ 113176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 113276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved29[0x00020]; 113376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 113476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */ 113576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 113676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved30[0x00020]; 113776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 113876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */ 113976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 114076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved31[0x00020]; 114176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 114276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */ 114376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 114476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved32[0x00020]; 114576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 114676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */ 114776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 114876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved33[0x00020]; 114976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 115076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */ 115176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 115276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved34[0x00020]; 115376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 115476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */ 115576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 115676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved35[0x00020]; 115776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 115876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */ 115976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved36[0x00020]; 116176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */ 116376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved37[0x00020]; 116576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */ 116776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 116876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved38[0x00020]; 116976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */ 117176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved39[0x00020]; 117376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */ 117576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved40[0x00020]; 117776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 117876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */ 117976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved41[0x00020]; 118176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */ 118376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved42[0x00020]; 118576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */ 118776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 118876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved43[0x00020]; 118976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */ 119176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved44[0x00020]; 119376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */ 119576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved45[0x00020]; 119776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 119876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */ 119976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved46[0x00020]; 120176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */ 120376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved47[0x00020]; 120576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */ 120776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 120876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved48[0x00020]; 120976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */ 121176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved49[0x00020]; 121376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */ 121576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved50[0x00020]; 121776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 121876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */ 121976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved51[0x00020]; 122176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */ 122376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved52[0x00020]; 122576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */ 122776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 122876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved53[0x00020]; 122976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */ 123176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved54[0x00020]; 123376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */ 123576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved55[0x00020]; 123776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 123876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */ 123976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved56[0x00020]; 124176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */ 124376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved57[0x00020]; 124576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */ 124776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 124876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved58[0x00020]; 124976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */ 125176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved59[0x00020]; 125376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */ 125576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved60[0x00020]; 125776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 125876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */ 125976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved61[0x00020]; 126176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */ 126376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved62[0x00020]; 126576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */ 126776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 126876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved63[0x00020]; 126976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 127076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 127176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 127276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* InfiniHost-III-EX Configuration Registers #### michal - match to PRM */ 127376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 127476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_configuration_registers_st { /* Little Endian */ 127576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x403400]; 127676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 127776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */ 127876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 127976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x3fcb20]; 128076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 128176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 128276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 128376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QP_DB_Record ### michal = gdror fixed */ 128476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 128576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_qp_db_record_st { /* Little Endian */ 128676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t receive_wqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */ 128776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 128876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 128976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 129076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* CQ_ARM_DB_Record */ 129276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_cq_arm_db_record_st { /* Little Endian */ 129476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */ 129576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 129676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd[0x00003]; /* 0x0 - No command 129776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter. 129876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter. 129976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated 130076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Other - Reserved */ 130176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */ 130276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t res[0x00003]; /* Must be 0x2 */ 130376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_number[0x00018]; /* CQ number */ 130476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 130576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 130676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 130776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* CQ_CI_DB_Record */ 130876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 130976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_cq_ci_db_record_st { /* Little Endian */ 131076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[0x00020]; /* CQ counter */ 131176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 131276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00005]; 131376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t res[0x00003]; /* Must be 0x1 */ 131476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_number[0x00018]; /* CQ number */ 131576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 131676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 131776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 131876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Virtual_Physical_Mapping */ 131976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 132076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_virtual_physical_mapping_st { /* Little Endian */ 132176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */ 132276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 132376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0000c]; 132476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */ 132576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 132676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */ 132776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 132876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */ 132976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00006]; 133076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */ 133176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 133276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 133376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 133476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* MOD_STAT_CFG #### michal - gdror fix */ 133576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 133676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mod_stat_cfg_st { /* Little Endian */ 133776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 133876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rx_options[0x00004]; /* number of RX options to sweep when doing SerDes parameters AutoNegotiation. */ 133976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00003]; 134076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rx_options_m[0x00001]; /* Modify rx_options */ 134176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tx_options[0x00004]; /* number of TX options to sweep when doing SerDes parameters AutoNegotiation. */ 134276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00003]; 134376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tx_options_m[0x00001]; /* Modify tx_options */ 134476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 134576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 134676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 134776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pre_amp[0x00004]; /* Pre Amplitude */ 134876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pre_emp_pre_amp[0x00004]; 134976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pre_emp_out[0x00004]; /* Pre Emphasis Out */ 135076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t voltage[0x00004]; 135176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t equ[0x00004]; /* Equalization */ 135276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x0000b]; 135376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t serdes_m[0x00001]; /* Modify serdes parameters */ 135476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 135576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lid[0x00010]; /* default LID */ 135676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lid_m[0x00001]; /* Modify default LID */ 135776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00003]; 135876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_en[0x00001]; /* enable port (E_Key) */ 135976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_en_m[0x00001]; /* Modify port_en */ 136076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x0000a]; 136176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 136276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x0001f]; 136376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t guid_hi_m[0x00001]; /* Modify guid_hi */ 136476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 136576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t guid_hi[0x00020]; 136676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 136776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x0001f]; 136876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t guid_lo_m[0x00001]; /* Modify guid_lo */ 136976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t guid_lo[0x00020]; 137176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x0001f]; 137376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nodeguid_hi_m[0x00001]; 137476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nodeguid_hi[0x00020]; 137676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 137776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x0001f]; 137876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nodeguid_lo_m[0x00001]; 137976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 138076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nodeguid_lo[0x00020]; 138176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 138276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00680]; 138376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 138476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 138576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* SRQ Context */ 138776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_srq_context_st { /* Little Endian */ 138976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srqn[0x00018]; /* SRQ number */ 139076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. 139176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maximum value is 0x10, i.e. 16M WQEs. */ 139276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t state[0x00004]; /* SRQ State: 139376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1111 - SW Ownership 139476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0000 - HW Ownership 139576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0001 - Error 139676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ 139776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 139876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t src_domain[0x00010]; /* The Scalable RC Domain. Messages coming to receive ports specifying this SRQ as receive queue will be served only if SRC_Domain of the SRQ matches SRC_Domain of the transport QP of this message. */ 139976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 140076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_srq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */ 140176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00005]; 140276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 140376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn[0x00018]; /* Completion Queue to report SRC messages directed to this SRQ. */ 140476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t page_offset[0x00006]; /* The offset of the first WQE from the beginning of 4Kbyte page (Figure 52,�Work Queue Buffer Structure�) */ 140576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 140676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 140776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 140876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 140976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 141076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00010]; 141176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 141276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00002]; 141376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 141476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00003]; 141576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 141676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 141776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* SRQ protection domain */ 141876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00008]; 141976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 142076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ 142176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then an SRQ limit event is fired and the LWM is set to zero. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ 142276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 142376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq_wqe_counter[0x00010];/* A 16-bit counter incremented for each WQE posted to the SRQ. Must be 0x0 in SRQ initialization. Valid only upon the QUERY_SRQ command. */ 142476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00010]; 142576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 142676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00020]; 142776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 142876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t db_record_addr_h[0x00020];/* SRQ DB Record physical address [63:32] */ 142976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 143076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00002]; 143176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t db_record_addr_l[0x0001e];/* SRQ DB Record physical address [31:2] */ 143276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 143376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 143476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* PBL */ 143676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_pbl_st { /* Little Endian */ 143876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */ 143976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 144076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */ 144176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 144276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */ 144376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 144476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */ 144576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 144676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */ 144776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 144876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */ 144976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 145076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */ 145176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 145276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */ 145376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 145476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 145576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Performance Counters #### michal - gdror fixed */ 145776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_performance_counters_st { /* Little Endian */ 145976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 146076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 146176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00080]; 146276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 146376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00080]; 146476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 146576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00060]; 146676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 146776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00620]; 146876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 146976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 147076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Transport and CI Error Counters */ 147276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_transport_and_ci_error_counters_st { /* Little Endian */ 147476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */ 147576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 147676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */ 147776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 147876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */ 147976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 148076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */ 148176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 148276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */ 148376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 148476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */ 148576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 148676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */ 148776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 148876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */ 148976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 149076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error. 149176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Incremented each time a CQE with error is generated */ 149276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 149376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error. 149476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Incremented each time a CQE with error is generated */ 149576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 149676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 149776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 149876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */ 149976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 150076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 150176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 150276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */ 150376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 150476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */ 150576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 150676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 150776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 150876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors 150976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK-Invalid Request on: 151076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1. Unsupported OpCode: Responder detected an unsupported OpCode. 151176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such 151276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman as a missing "Last" packet. 151376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Note: there is no PSN error, thus this does not indicate a dropped packet. */ 151476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 151576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors. 151676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK may or may not be sent. 151776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only): 151876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Inbound request OpCode was either reserved, or was for a function not supported by this 151976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman QP. (E.g. RDMA or ATOMIC on QP not set up for this). 152076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion. 152176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3. Too many RDMA READ or ATOMIC Requests: There were more requests received 152276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman and not ACKed than allowed for the connection. 152376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder 152476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman detected an error in the sequence of OpCodes; a missing "Last" packet 152576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder 152676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman detected an error in the sequence of OpCodes; a missing "First" packet 152776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able 152876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman buffer space. 152976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7. Length error: RDMA WRITE request message contained too much or too little pay-load 153076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman data compared to the DMA length advertised in the first or only packet. 153176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8. Length error: Payload length was not consistent with the opcode: 153276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman a: 0 byte <= "only" <= PMTU bytes 153376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman b: ("first" or "middle") == PMTU bytes 153476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman c: 1byte <= "last" <= PMTU bytes 153576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9. Length error: Inbound message exceeded the size supported by the CA port. */ 153676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 153776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors. 153876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK-Remote Access Error on: 153976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman R_Key Violation: Responder detected an invalid R_Key while executing an RDMA 154076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Request. */ 154176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 154276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors. 154376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman R_Key Violation Responder detected an R_Key violation while executing an RDMA 154476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman request. 154576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK may or may not be sent. */ 154676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 154776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors. 154876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK-Remote Operation Error on: 154976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Remote Operation Error: Responder encountered an error, (local to the responder), 155076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman which prevented it from completing the request. */ 155176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 155276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors. 155376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman NAK-Remote Operation Error on: 155476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing 155576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman the packet. 155676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2. Remote Operation Error: Responder encountered an error, (local to the responder), 155776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman which prevented it from completing the request. */ 155876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 155976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */ 156076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 156276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */ 156476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_rnr[0x00020]; /* Responder - the number of RNR Naks sent */ 156676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rnr[0x00020]; /* Requester - the number of RNR Naks received */ 156876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 156976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00040]; 157076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 157276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */ 157476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00020]; 157676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */ 157876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 157976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00020]; 158076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 158176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */ 158276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 158376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00380]; 158476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 158576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */ 158676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 158776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */ 158876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 158976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */ 159076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00020]; 159276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */ 159476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */ 159676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */ 159876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 159976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00020]; 160076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */ 160276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x003e0]; 160476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */ 160676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */ 160876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 160976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */ 161076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 161176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x002a0]; 161276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 161376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 161476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 161576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - HCR Completion Event #### michal - match PRM */ 161676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 161776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_hcr_completion_event_st { /* Little Endian */ 161876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t token[0x00010]; /* HCR Token */ 161976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 162076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 162176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 162276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 162376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00008]; /* HCR Status */ 162476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00018]; 162576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 162676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */ 162776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 162876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */ 162976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 163076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 163176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 163276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 163376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 163476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Completion with Error CQE #### michal - gdror fixed */ 163576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 163676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_completion_with_error_st { /* Little Endian */ 163776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 163876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 163976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 164076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x000a0]; 164176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 164276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome: 164376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x01 - Local Length Error 164476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x02 - Local QP Operation Error 164576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x03 - Local EE Context Operation Error 164676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x04 - Local Protection Error 164776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x05 - Work Request Flushed Error 164876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x06 - Memory Window Bind Error 164976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x10 - Bad Response Error 165076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x11 - Local Access Error 165176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x12 - Remote Invalid Request Error 165276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x13 - Remote Access Error 165376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x14 - Remote Operation Error 165476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x15 - Transport Retry Counter Exceeded 165576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x16 - RNR Retry Counter Exceeded 165676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x20 - Local RDD Violation Error 165776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x21 - Remote Invalid RD Request 165876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x22 - Remote Aborted Error 165976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x23 - Invalid EE Context Number 166076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x24 - Invalid EE Context State 166176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - Reserved 166276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */ 166376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vendor_error_syndrome[0x00008]; 166476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_counter[0x00010]; 166576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 166676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[0x00005]; /* The opcode of WQE completion is reported for. 166776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 166876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The following values are reported in case of completion with error: 166976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xFE - For completion with error on Receive Queues 167076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xFF - For completion with error on Send Queues */ 167176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00001]; 167276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ 167376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ 167476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00018]; 167576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 167676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 167776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 167876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Resize CQ Input Mailbox */ 167976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 168076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_resize_cq_st { /* Little Endian */ 168176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 168276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 168376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00006]; 168476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t page_offset[0x00006]; 168576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00014]; 168676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 168776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00018]; 168876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */ 168976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00003]; 169076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 169176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 169276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 169376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_h[0x00008]; 169476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00010]; 169576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_page_size[0x00006]; 169676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00002]; 169776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 169876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00003]; 169976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_l[0x0001d]; 170076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 170176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00020]; 170276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 170376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00100]; 170476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 170576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 170676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 170776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* MAD_IFC Input Modifier */ 170876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 170976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mad_ifc_input_modifier_st { /* Little Endian */ 171076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */ 171176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set. 171276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Required for trap generation when BKey check is enabled and for global routed packets. */ 171376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00007]; 171476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. 171576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is required for trap generation upon MKey/BKey validation. */ 171676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 171776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 171876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 171976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* MAD_IFC Input Mailbox ###michal -gdror fixed */ 172076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 172176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mad_ifc_st { /* Little Endian */ 172276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */ 172376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 172476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD. 172576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 172676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 172776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 172876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 172976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 173076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD. 173176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 173276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00008]; 173376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 173476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00010]; 173576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD. 173676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 173776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid. 173876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 173976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00004]; 174076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD. 174176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 174276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 174376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD. 174476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 174576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00010]; 174676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 174776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00160]; 174876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 174976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. 175076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid if Mad_extended_info bit (in the input modifier) and g bit are set. 175176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise this field is reserved. */ 175276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 175376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x004c0]; 175476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 175576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 175676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 175776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Query Debug Message #### michal - gdror fixed */ 175876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 175976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_query_debug_msg_st { /* Little Endian */ 176076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */ 176176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 176276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t v[0x00001]; /* Physical translation is valid */ 176376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x0000b]; 176476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */ 176576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 176676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */ 176776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 176876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */ 176976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 177076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */ 177176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 177276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */ 177376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 177476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x000c0]; 177576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 177676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */ 177776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 177876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */ 177976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 178076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00040]; 178176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 178276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */ 178376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 178476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */ 178576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 178676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */ 178776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 178876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */ 178976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 179076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */ 179176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 179276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */ 179376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 179476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */ 179576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 179676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */ 179776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 179876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */ 179976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 180076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */ 180176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 180276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */ 180376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 180476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */ 180576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 180676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00080]; 180776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 180876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hw_buff_addr[0x00020]; /* Dror Mux Bohrer tracer */ 180976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 181076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hw_buff_size[0x00020]; 181176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 181276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x003c0]; 181376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 181476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 181576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 181676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* User Access Region */ 181776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 181876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_uar_st { /* Little Endian */ 181976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */ 182076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 182176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ 182276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 182376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 182476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 182576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */ 182676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 182776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x03ec0]; 182876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 182976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 183076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 183176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Receive doorbell */ 183276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 183376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_receive_doorbell_st { /* Little Endian */ 183476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 183576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */ 183676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 183776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 183876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00005]; 183976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */ 184076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00002]; 184176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */ 184276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 184376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 184476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 184576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* SET_IB Parameters */ 184676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 184776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_set_ib_st { /* Little Endian */ 184876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */ 184976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00011]; 185076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 185176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman system_image_guid and sig must be the same for all ports. */ 185276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0000d]; 185376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 185476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */ 185576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 185676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 185776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 185876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 185976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 186076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 186176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 186276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00180]; 186376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 186476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 186576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 186676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Multicast Group Member #### michal - gdror fixed */ 186776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 186876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mgm_entry_st { /* Little Endian */ 186976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00006]; 187076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number. 187176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables. 187276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman next_gid_index=0 means end of the chain. */ 187376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 187476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00060]; 187576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 187676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format. 187776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 187876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 187976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format. 188076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 188176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 188276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format. 188376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 188476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 188576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format. 188676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 188776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 188876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */ 188976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */ 189176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */ 189376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */ 189576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */ 189776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 189876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */ 189976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 190076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */ 190176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 190276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */ 190376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 190476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 190576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 190676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* INIT_PORT Parameters #### michal - match PRM */ 190776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 190876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_init_port_st { /* Little Endian */ 190976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00004]; 191076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15. 191176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Legal values are 1,2,4 and 8. */ 191276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_width_cap[0x00004];/* IB Port Width 191376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - 1x 191476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - 1x, 4x 191576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208) 191676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else - Reserved */ 191776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00004]; 191876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */ 191976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified. 192076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman node_guid and ng must be the same for all ports. */ 192176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 192276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman system_image_guid and sig must be the same for all ports. */ 192376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x0000d]; 192476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 192576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */ 192676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtu[0x00010]; /* Maximum MTU Supported in bytes 192776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman must be: 256, 512, 1024, 2048 or 4096 192876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For Eth port, can be any 192976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Field must not cross device capabilities as reported 193076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 193176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 193276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port. 193376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 193476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00010]; 193576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 193676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00020]; 193776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 193876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */ 193976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 194076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */ 194176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 194276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set 194376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 194476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 194576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set 194676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 194776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 194876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 194976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 195076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 195176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 195276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be the same for both ports. */ 195376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 195476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x006c0]; 195576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 195676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 195776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 195876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Query Device Capablities #### michal - gdror fixed */ 195976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 196076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_query_dev_cap_st { /* Little Endian */ 196176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 196276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 196376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */ 196476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00003]; 196576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use 196676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */ 196776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00004]; 196876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */ 196976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */ 197076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 197176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_scqs[0x00004]; /* log base 2 of number of supported schedule queues */ 197276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00004]; 197376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_scqs[0x00006]; 197476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00002]; 197576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_srqs[0x00005]; 197676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00007]; 197776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_srqs[0x00004]; 197876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 197976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */ 198076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00003]; 198176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use 198276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */ 198376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00004]; 198476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */ 198576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00008]; 198676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 198776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_eq[0x00004]; /* Log2 of the Maximum number of EQs */ 198876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00004]; 198976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use 199076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_rsvd_eqs-1 199176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If 0 - no resources are reserved. */ 199276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00004]; 199376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_d_mpts[0x00006];/* Log (base 2) of the maximum number of data MPT entries (the number of Regions/Windows) */ 199476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00002]; 199576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */ 199676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 199776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */ 199876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00002]; 199976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use 200076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */ 200176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x00004]; 200276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_mrw_sz[0x00007];/* Log2 of the Maximum Size of Memory Region/Window. is it in PRM layout? */ 200376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x00005]; 200476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use 200576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1 200676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 200776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 200876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x00020]; 200976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 201076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */ 201176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x0000a]; 201276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */ 201376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x0000a]; 201476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 201576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */ 201676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved18[0x0001a]; 201776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 201876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */ 201976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved19[0x0001f]; 202076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 202176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */ 202276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_vl_ib[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */ 202376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ib_port_width[0x00004];/* IB Port Width 202476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - 1x 202576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3 - 1x, 4x 202676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - 1x, 4x or 12x 202776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman else - Reserved */ 202876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ib_mtu[0x00004]; /* Maximum MTU Supported 202976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x0 - Reserved 203076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - 256 203176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - 512 203276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - 1024 203376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x4 - 2048 203476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x5 - 4096 203576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x6-0xF Reserved */ 203676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb. 203776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */ 203876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port_type[0x00004]; /* Hermon New. bit per port. bit0 is first port. value '1' is ehternet. '0' is IB */ 203976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved20[0x00004]; 204076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t w[0x00001]; /* Hermon New. 10GB eth support */ 204176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t j[0x00001]; /* Hermon New. Jumbo frame support */ 204276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved21[0x00001]; 204376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 204476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */ 204576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved22[0x00004]; 204676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_ethtype[0x00004]; /* Hermon New. log2 eth type table size */ 204776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved23[0x00004]; 204876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_drain_size[0x00008];/* Log (base 2) of minimum size of the NoDropVLDrain buffer, specified in 4Kpages units */ 204976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_msg[0x00005]; /* Log (base 2) of the maximum message size supported by the device */ 205076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved24[0x00003]; 205176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 205276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */ 205376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved25[0x0000c]; 205476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported 205576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bit 0 - full bw 205676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bit 1 - 1/4 bw 205776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bit 2 - 1/8 bw 205876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman bit 3 - 1/2 bw; */ 205976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 206076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved26[0x00020]; 206176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 206276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rc[0x00001]; /* RC Transport supported */ 206376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uc[0x00001]; /* UC Transport Supported */ 206476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ud[0x00001]; /* UD Transport Supported */ 206576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t src[0x00001]; /* SRC Transport Supported. Hermon New instead of RD. */ 206676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rcm[0x00001]; /* Reliable Multicast support. Hermon New instead of IPv6 Transport Supported */ 206776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fcoib[0x00001]; /* Hermon New */ 206876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq[0x00001]; /* SRQ is supported 206976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 207076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t checksum[0x00001]; /* IP over IB checksum is supported */ 207176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */ 207276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */ 207376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vmm[0x00001]; /* Hermon New */ 207476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fcoe[0x00001]; 207576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dpdp[0x00001]; /* Dual Port Different Protocols */ 207676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t raw_ethertype[0x00001]; 207776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t raw_ipv6[0x00001]; 207876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t blh[0x00001]; 207976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mw[0x00001]; /* Memory windows supported */ 208076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */ 208176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */ 208276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */ 208376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */ 208476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */ 208576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved28[0x00002]; 208676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pg[0x00001]; /* Paging on demand supported */ 208776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r[0x00001]; /* Router mode supported */ 208876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved29[0x00006]; 208976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 209076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2). 209176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */ 209276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved30[0x00008]; 209376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */ 209476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved31[0x00006]; 209576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use 209676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_reserved_uars-1 209776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Note that UAR number num_reserved_uars is always for the kernel. */ 209876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 209976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_bf_pages[0x00006];/* Maximum number of BlueFlame pages is 2^log_max_bf_pages */ 210076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved32[0x00002]; 210176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_bf_regs_per_page[0x00006];/* Maximum number of BlueFlame registers per page is 2^log_max_bf_regs_per_page. It may be that only the beginning of a page contains BlueFlame registers. */ 210276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved33[0x00002]; 210376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_bf_reg_size[0x00005];/* BlueFlame register size in bytes is 2^log_bf_reg_size */ 210476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved34[0x0000a]; 210576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bf[0x00001]; /* If set to "1" then BlueFlame may be used. */ 210676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 210776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */ 210876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */ 210976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved35[0x00008]; 211076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 211176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */ 211276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */ 211376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved36[0x00008]; 211476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 211576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved37[0x00001]; 211676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fexch_base_mpt_31_25[0x00007];/* Hermon New. FC mpt base mpt number */ 211776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fcp_ud_base_23_8[0x00010];/* Hermon New. FC ud QP base QPN */ 211876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fexch_base_qp_23_16[0x00008];/* Hermon New. FC Exchange QP base QPN */ 211976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 212076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved38[0x00020]; 212176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 212276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */ 212376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT. 212476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_reserved_mcgs-1 212576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If 0 - no resources are reserved. */ 212676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved39[0x00004]; 212776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */ 212876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved40[0x00008]; 212976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 213076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_srcds[0x00004];/* Log2 of the maximum number of SRC Domains */ 213176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved41[0x00008]; 213276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_scrds[0x00004];/* The number of SRCDs reserved for firmware use 213376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_reserved_rdds-1. 213476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If 0 - no resources are reserved. */ 213576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_pd[0x00005]; /* Log2 of the maximum number of PDs */ 213676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved42[0x00007]; 213776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use 213876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The reserved resources are numbered from 0 to num_reserved_pds-1 213976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If 0 - no resources are reserved. */ 214076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 214176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved43[0x000c0]; 214276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 214376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device 214476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 214576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rdmardc_entry_sz[0x00010];/* RdmaRdC Entry Size for the device 214676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 214776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 214876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t altc_entry_sz[0x00010];/* Extended QPC entry size for the device 214976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 215076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t aux_entry_sz[0x00010]; /* Auxilary context entry size */ 215176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 215276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device 215376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 215476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device 215576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 215676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 215776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t c_mpt_entry_sz[0x00010];/* cMPT entry size in Bytes for the device. 215876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 215976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device 216076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 216176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 216276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t d_mpt_entry_sz[0x00010];/* dMPT entry size in Bytes for the device. 216376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 216476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device. 216576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For the InfiniHost-III-EX MT25208 entry size is 8 bytes */ 216676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 216776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */ 216876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism: 216976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Type 2A - QP Number Association; or 217076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Type 2B - QP Number and PD Association. */ 217176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */ 217276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. */ 217376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */ 217476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */ 217576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved44[0x0001a]; 217676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 217776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */ 217876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 217976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved45[0x00020]; 218076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 218176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */ 218276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 218376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */ 218476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 218576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved46[0x002c0]; 218676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 218776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 218876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 218976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QUERY_ADAPTER Parameters Block #### michal - gdror fixed */ 219076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 219176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_query_adapter_st { /* Little Endian */ 219276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 219376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 219476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00018]; 219576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */ 219676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 219776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00060]; 219876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 219976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_vsd_st vsd; /* ###michal- this field was replaced by 2 fields : vsd .1664; vsd(continued/psid .128; */ 220076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 220176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 220276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 220376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QUERY_FW Parameters Block #### michal - doesn't match PRM */ 220476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 220576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_query_fw_st { /* Little Endian */ 220676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */ 220776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */ 220876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 220976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */ 221076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */ 221176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 221276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */ 221376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 221476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 221576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */ 221676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00017]; 221776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dt[0x00001]; /* Debug Trace Support 221876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Debug trace is not supported 221976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Debug trace is supported */ 222076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 222176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00001]; 222276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ccq[0x00001]; /* CCQ support */ 222376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00006]; 222476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_seconds[0x00008]; /* FW timestamp - seconds. Dispalyed as Hexadecimal number */ 222576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_minutes[0x00008]; /* FW timestamp - minutes. Dispalyed as Hexadecimal number */ 222676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_hour[0x00008]; /* FW timestamp - hour. Dispalyed as Hexadecimal number */ 222776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 222876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_day[0x00008]; /* FW timestamp - day. Dispalyed as Hexadecimal number */ 222976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_month[0x00008]; /* FW timestamp - month. Dispalyed as Hexadecimal number */ 223076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fw_year[0x00010]; /* FW timestamp - year. Dispalyed as Hexadecimal number (e.g. 0x2005) */ 223176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 223276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00040]; 223376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 223476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_base_offset_h[0x00020];/* Bits [63:32] of the Clear Interrupt registers offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ 223576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 223676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_base_offset_l[0x00020];/* Bits [31:0] of the Clear Interrupt registers offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ 223776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 223876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x0001e]; 223976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clr_int_bar[0x00002]; /* PCI base address register (BAR) where clr_int register is located. 224076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00 - BAR 0-1 224176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 01 - BAR 2-3 224276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10 - BAR 4-5 224376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - Reserved 224476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The PCI BARs of ConnectX are 64 bit BARs. 224576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman In ConnectX, clr_int register is located on BAR 0-1. */ 224676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 224776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00020]; 224876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 224976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t error_buf_offset_h[0x00020];/* Read Only buffer for catastrophic error reports (bits [63:32] of offset from error_buf_bar register in PCI address space.) */ 225076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 225176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t error_buf_offset_l[0x00020];/* Read Only buffer for catastrophic error reports (bits [31:0] of offset from error_buf_bar register in PCI address space.) */ 225276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 225376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t error_buf_size[0x00020];/* Size in words */ 225476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 225576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x0001e]; 225676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t error_buf_bar[0x00002];/* PCI base address register (BAR) where error_buf register is located. 225776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00 - BAR 0-1 225876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 01 - BAR 2-3 225976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10 - BAR 4-5 226076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11 - Reserved 226176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman The PCI BARs of ConnectX are 64 bit BARs. 226276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman In ConnectX, error_buf register is located on BAR 0-1. */ 226376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 226476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00600]; 226576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 226676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 226776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 226876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Memory Access Parameters for UD Address Vector Table */ 226976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 227076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_udavtable_memory_parameters_st { /* Little Endian */ 227176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */ 227276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 227376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */ 227476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00005]; 227576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */ 227676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 227776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 227876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 227976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 228076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* INIT_HCA & QUERY_HCA Parameters Block ####michal-doesn't match PRM (see differs below) new size in bytes:0x300 */ 228176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 228276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_init_hca_st { /* Little Endian */ 228376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00018]; 228476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t version[0x00008]; 228576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 228676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 228776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 228876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00010]; 228976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t hca_core_clock[0x00010];/* Internal Clock freq in MHz */ 229076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 229176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t router_qp[0x00018]; /* QP number for router mode (8 LSBits should be 0). Low order 8 bits are taken from the TClass field of the incoming packet. 229276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid only if RE bit is set */ 229376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00005]; 229476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ipr2[0x00001]; /* Hermon New. IP router on port 2 */ 229576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ipr1[0x00001]; /* Hermon New. IP router on port 1 */ 229676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ibr[0x00001]; /* InfiniBand Router Mode */ 229776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 229876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t udp[0x00001]; /* UD Port Check Enable 229976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Port field in Address Vector is ignored 230076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */ 230176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations 230276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - Host is Little Endian 230376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - Host is Big endian 230476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 230576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00001]; 230676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */ 230776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x0001c]; 230876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 230976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00040]; 231076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 231176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;/* ## michal - this field has chenged to - "qpc_cqc_eqc_parameters" - gdror, this is ok for now */ 231276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 231376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00100]; 231476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 231576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_multicastparam_st multicast_parameters;/* ##michal- this field has chenged to - "IBUD/IPv6_multicast_parameters" - gdror - this is OK for now */ 231676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 231776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00080]; 231876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 231976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_tptparams_st tpt_parameters; 232076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 232176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00080]; 232276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 232376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_uar_params_st uar_parameters;/* UAR Parameters */ 232476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 232576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00600]; 232676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 232776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 232876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 232976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event Queue Context Table Entry #### michal - gdror fixed */ 233076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 233176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_eqc_st { /* Little Endian */ 233276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 233376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t st[0x00004]; /* Event delivery state machine 233476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x9 - Armed 233576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xA - Fired 233676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xB - Always_Armed (auto-rearm) 233776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved */ 233876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00005]; 233976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t oi[0x00001]; /* Oerrun ignore. 234076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If set, HW will not check EQ full condition when writing new EQEs. */ 234176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ec[0x00001]; /* is set, all EQEs are written (coalesced) to first EQ entry */ 234276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00009]; 234376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00004]; /* EQ status: 234476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0000 - OK 234576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1010 - EQ write failure 234676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_EQ and HW2SW_EQ commands only */ 234776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 234876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 234976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 235076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00005]; 235176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t page_offset[0x00007]; /* offset bits[11:5] of first EQE in the EQ relative to the first page in memory region mapping this EQ */ 235276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00014]; 235376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 235476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00018]; 235576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_eq_size[0x00005]; /* Log (base 2) of the EQ size (in entries). Maximum EQ size is 2^22 EQEs (max log_eq_size is 22) */ 235676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00003]; 235776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 235876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq_max_count[0x00010]; /* Event Generation Moderation counter */ 235976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eq_period[0x00010]; /* Event Generation moderation timed, microseconds */ 236076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 236176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t intr[0x0000a]; /* MSI-X table entry index to be used to signal interrupts on this EQ. Reserved if MSI-X are not enabled in the PCI configuration header. */ 236276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00016]; 236376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 236476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] relative to INIT_HCA.mtt_base_addr */ 236576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00010]; 236676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 236776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00002]; 236876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 236976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00003]; 237076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] relative to INIT_HCA.mtt_base_addr */ 237176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 237276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00040]; 237376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 237476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t consumer_counter[0x00018];/* Consumer counter. The counter is incremented for each EQE polled from the EQ. 237576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in EQ initialization. 237676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maintained by HW (valid for the QUERY_EQ command only). */ 237776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x00008]; 237876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 237976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t producer_counter[0x00018];/* Producer Coutner. The counter is incremented for each EQE that is written by the HW to the EQ. 238076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman EQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a EQE needs to be added. 238176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maintained by HW (valid for the QUERY_EQ command only) */ 238276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x00008]; 238376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 238476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x00080]; 238576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 238676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 238776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 238876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Memory Translation Table (MTT) Entry #### michal - match to PRM */ 238976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 239076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mtt_st { /* Little Endian */ 239176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 239276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 239376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */ 239476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00002]; 239576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ptag_l[0x0001d]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 239676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 239776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 239876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 239976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Memory Protection Table (MPT) Entry ### doesn't match PRM (new fields were added). new size in bytes : 0x54 */ 240076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 240176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mpt_st { /* Little Endian */ 240276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 240376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */ 240476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation is performed for this region */ 240576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lr[0x00001]; /* If set - local read access is enabled. Must be set for all MPT Entries. */ 240676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lw[0x00001]; /* If set - local write access is enabled */ 240776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rr[0x00001]; /* If set - remote read access is enabled. */ 240876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rw[0x00001]; /* If set - remote write access is enabled */ 240976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t atomic[0x00001]; /* If set - remote Atomic access is allowed. */ 241076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t eb[0x00001]; /* If set - bind is enabled. Valid only for regions. */ 241176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t atc_req[0x00001]; /* If set, second hop of address translation (PA to MA) to be performed in the device prior to issuing the uplink request. */ 241276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t atc_xlated[0x00001]; /* If set, uplink cycle to be issues with ATC_translated indicator to force bypass of the chipset IOMMU. */ 241376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00001]; 241476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t no_snoop[0x00001]; /* If set, issue PCIe cycle with ûno Snoopÿ attribute - cycle not to be snooped in CPU caches */ 241576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00008]; 241676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00004]; /* 0xF - Not Valid 0x3 - Free. else - HW ownership.Unbound Type1 windows are denoted by reg_wnd_len=0. Unbound Type II windows are denoted by Status = Free. */ 241776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 241876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00007]; 241976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bqp[0x00001]; /* 0 - not bound to qp (type 1 window, MR)1 - bound to qp (type 2 window) */ 242076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */ 242176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 242276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. */ 242376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 242476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* Protection Domain. If VMM support is enabled PD[17:23] specify Guest VM Identifier */ 242576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t en_rinv[0x00001]; /* Enable remote invalidation */ 242676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. Must be set for type2 windows and non-shared physical memory regions. Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */ 242776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t nce[0x00001]; /* Data can be cached in Network Cache (see ûNetwork Cacheÿ on page 81) */ 242876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */ 242976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail */ 243076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t w_dif[0x00001]; /* Wire space contains dif */ 243176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t m_dif[0x00001]; /* Memory space contains dif */ 243276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00001]; 243376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 243476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_addr_h[0x00020]; /* Start Address - Virtual Address where this region/window starts */ 243576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 243676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_addr_l[0x00020]; /* Start Address - Virtual Address where this region/window starts */ 243776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 243876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t len_h[0x00020]; /* Region/Window Length */ 243976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 244076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t len_l[0x00020]; /* Region/Window Length */ 244176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 244276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */ 244376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 244476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t win_cnt[0x00018]; /* Number of windows bound to this region. Valid for regions only.The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */ 244576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00008]; 244676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 244776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_rep[0x00004]; /* Log (base 2) of the number of time an MTT is replicated.E.g. for 64KB virtual blocks from 512B blocks, a replication factor of 2^7 is needed (MTT_REPLICATION_FACTOR=7).Up to 1MB of replicated block works */ 244876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00011]; 244976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t block_mode[0x00001]; /* If set, the page size is not power of two, and entity_size is in bytes. */ 245076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t len64[0x00001]; /* Region/Window Length[64]. This bit added to enable registering 2^64 bytes per region */ 245176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fbo_en[0x00001]; /* If set, mtt_fbo field is valid, otherwise it is calculated from least significant bytes of the address. Must be set when mtt_rep is used or MPT is block-mode region */ 245276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00008]; 245376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 245476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_adr_h[0x00008]; /* Offset to MTT list for this region. Must be aligned on 8 bytes. */ 245576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00018]; 245676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 245776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_adr_l[0x00020]; /* Offset to MTT list for this region. Must be aligned on 8 bytes.###michal-relpaced with: RESERVED .3;mtt_adr_l .29; gdror - this is OK to leave it this way. */ 245876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 245976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_size[0x00020]; /* Number of MTT entries allocated for this MR.When Fast Registration Operations cannot be executed on this region (FRE bit is zero) this field is reserved.When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value cannot be zero. */ 246076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 246176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t entity_size[0x00015]; /* Page/block size. If MPT maps pages, the page size is 2entiry_size. If MPT maps blocks, the entity_size field specifies block size in bytes. The minimum amount of memory that can be mapped with single MTT is 512 bytes. */ 246276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x0000b]; 246376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 246476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_fbo[0x00015]; /* First byte offset in the zero-based region - the first byte within the first block/page start address refers to. When mtt_rep is being used, fbo points within the replicated block (i.e. block-size x 2^mtt_rep) */ 246576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x0000b]; 246676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 246776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 246876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 246976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Completion Queue Context Table Entry #### michal - match PRM */ 247076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 247176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_completion_queue_context_st { /* Little Endian */ 247276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 247376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t st[0x00004]; /* Event delivery state machine 247476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x0 - reserved 247576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x9 - ARMED (Request for Notification) 247676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x6 - ARMED SOLICITED (Request Solicited Notification) 247776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0xA - FIRED 247876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman other - reserved 247976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 248076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Must be 0x0 in CQ initialization. 248176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_CQ and HW2SW_CQ commands only. */ 248276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00005]; 248376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled. 248476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */ 248576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cc[0x00001]; /* is set, all CQEs are written (coalesced) to first CQ entry */ 248676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00009]; 248776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00004]; /* CQ status 248876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0000 - OK 248976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1001 - CQ overflow 249076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1010 - CQ write failure 249176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for the QUERY_CQ and HW2SW_CQ commands only */ 249276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 249376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 249476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 249576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00005]; 249676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t page_offset[0x00007]; /* offset of first CQE in the CQ relative to the first page in memory region mapping this CQ */ 249776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00014]; 249876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 249976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */ 250076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries). 250176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */ 250276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00003]; 250376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 250476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_max_count[0x00010]; /* Event Generation Moderation counter */ 250576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cq_period[0x00010]; /* Event Generation moderation timed, microseconds */ 250676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 250776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t c_eqn[0x00009]; /* Event Queue this CQ reports completion events to. 250876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid values are 0 to 63 250976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman If configured to value other than 0-63, completion events will not be reported on the CQ. */ 251076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00017]; 251176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 251276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 251376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00010]; 251476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t log2_page_size[0x00006]; 251576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00002]; 251676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 251776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00003]; 251876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 251976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 252076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t last_notified_indx[0x00018];/* Maintained by HW. 252176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for QUERY_CQ and HW2SW_CQ commands only. */ 252276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00008]; 252376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 252476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t solicit_producer_indx[0x00018];/* Maintained by HW. 252576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Valid for QUERY_CQ and HW2SW_CQ commands only. 252676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 252776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00008]; 252876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 252976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t consumer_counter[0x00018];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ. 253076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 253176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x00008]; 253276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 253376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t producer_counter[0x00018];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ. 253476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added.. 253576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */ 253676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x00008]; 253776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 253876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x00020]; 253976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 254076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x00020]; 254176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 254276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t db_record_addr_h[0x00020];/* CQ DB Record physical address [63:32] */ 254376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 254476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x00003]; 254576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t db_record_addr_l[0x0001d];/* CQ DB Record physical address [31:3] */ 254676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 254776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 254876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 254976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* GPIO_event_data #### michal - gdror fixed */ 255076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 255176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_gpio_event_data_st { /* Little Endian */ 255276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00060]; 255376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 255476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 255576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 255676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 255776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 255876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 255976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 256076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 256176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 256276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - QP/EE Events #### michal - doesn't match PRM */ 256376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 256476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_qp_ee_event_st { /* Little Endian */ 256576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for ###michal - field changed to QP number */ 256676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 256776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 256876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 256976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 257076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x0001c]; 257176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field 257276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Not valid on SRQ events ###michal - field replaced with RESERVED */ 257376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00003]; 257476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 257576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00060]; 257676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 257776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 257876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 257976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* InfiniHost-III-EX Type0 Configuration Header ####michal - doesn't match PRM (new fields added, see below) */ 258076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 258176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mt25208_type0_st { /* Little Endian */ 258276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */ 258376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode 258476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25408 (decimal) - InfiniHost-III EX mode (the mode described in this manual) 258576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode 258676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 258776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 258876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t command[0x00010]; /* PCI Command Register */ 258976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t status[0x00010]; /* PCI Status Register */ 259076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 259176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t revision_id[0x00008]; 259276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t class_code_hca_class_code[0x00018]; 259376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 259476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */ 259576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t latency_timer[0x00008]; 259676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t header_type[0x00008]; /* hardwired to zero */ 259776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bist[0x00008]; 259876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 259976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */ 260076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00010]; 260176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */ 260276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 260376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */ 260476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 260576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */ 260676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00010]; 260776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */ 260876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 260976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */ 261076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 261176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */ 261276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00010]; 261376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 261476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 261576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 261676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 261776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cardbus_cis_pointer[0x00020]; 261876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 261976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */ 262076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */ 262176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 262276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 262376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x0000a]; 262476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 262576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 262676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */ 262776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x00018]; 262876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 262976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x00020]; 263076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 263176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t interrupt_line[0x00008]; 263276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t interrupt_pin[0x00008]; 263376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t min_gnt[0x00008]; 263476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t max_latency[0x00008]; 263576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 263676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x00100]; 263776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 263876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msi_cap_id[0x00008]; 263976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msi_next_cap_ptr[0x00008]; 264076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msi_en[0x00001]; 264176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t multiple_msg_cap[0x00003]; 264276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t multiple_msg_en[0x00003]; 264376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cap_64_bit_addr[0x00001]; 264476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x00008]; 264576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 264676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg_addr_l[0x00020]; 264776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 264876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg_addr_h[0x00020]; 264976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 265076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t msg_data[0x00010]; 265176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0x00010]; 265276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 265376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x00080]; 265476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 265576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */ 265676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_next_cap_ptr[0x00008]; 265776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h 265876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [3] PME clock - 0h 265976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [4] RsvP 266076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [5] Device specific initialization - 0h 266176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [8:6] AUX current - 0h 266276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [9] D1 support - 0h 266376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [10] D2 support - 0h 266476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [15:11] PME support - 0h */ 266576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 266676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */ 266776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pm_control_status_brdg_ext[0x00008]; 266876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t data[0x00008]; 266976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 267076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00040]; 267176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 267276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */ 267376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vpd_next_cap_id[0x00008]; 267476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vpd_address[0x0000f]; 267576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t f[0x00001]; 267676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 267776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vpd_data[0x00020]; 267876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 267976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x00040]; 268076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 268176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */ 268276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pciex_next_cap_ptr[0x00008]; 268376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h 268476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [7:4] Device/Port Type - 0h 268576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [8] Slot implemented - 0h 268676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [13:9] Interrupt message number 268776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 268876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 268976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h 269076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [4:3] Phantom Function supported - 0h 269176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [5] Extended Tag Filed supported - 0h 269276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [8:6] Endpoint L0s Acceptable Latency - TBD 269376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [11:9] Endpoint L1 Acceptable Latency - TBD 269476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [12] Attention Button Present - configured through InfiniBurn 269576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [13] Attention Indicator Present - configured through InfiniBurn 269676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [14] Power Indicator Present - configured through InfiniBurn 269776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [25:18] Captured Slot Power Limit Value 269876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [27:26] Captured Slot Power Limit Scale */ 269976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 270076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t device_control[0x00010]; 270176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t device_status[0x00010]; 270276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 270376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h 270476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [9:4] Maximum Link Width - 8h 270576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [11:10] Active State Power Management Support - 3h 270676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [14:12] L0s Exit Latency - TBD 270776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [17:15] L1 Exit Latency - TBD 270876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [31:24] Port Number - 0h */ 270976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 271076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t link_control[0x00010]; 271176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h 271276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [9:4] Negotiated Link Width 271376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman [12] Slot clock configuration - 1h */ 271476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 271576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x00260]; 271676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 271776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */ 271876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t capability_version[0x00004];/* 1h */ 271976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_capability_offset[0x0000c];/* 0h */ 272076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 272176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status 272276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4 Data Link Protocol Error Status 272376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Poisoned TLP Status 272476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13 Flow Control Protocol Error Status 272576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14 Completion Timeout Status 272676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15 Completer Abort Status 272776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16 Unexpected Completion Status 272876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17 Receiver Overflow Status 272976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 18 Malformed TLP Status 273076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19 ECRC Error Status 273176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20 Unsupported Request Error Status */ 273276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 273376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask 273476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4 Data Link Protocol Error Mask 273576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Poisoned TLP Mask 273676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13 Flow Control Protocol Error Mask 273776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14 Completion Timeout Mask 273876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15 Completer Abort Mask 273976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16 Unexpected Completion Mask 274076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17 Receiver Overflow Mask 274176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 18 Malformed TLP Mask 274276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19 ECRC Error Mask 274376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20 Unsupported Request Error Mask */ 274476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 274576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity 274676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4 Data Link Protocol Error Severity 274776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Poisoned TLP Severity 274876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13 Flow Control Protocol Error Severity 274976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14 Completion Timeout Severity 275076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 15 Completer Abort Severity 275176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16 Unexpected Completion Severity 275276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17 Receiver Overflow Severity 275376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 18 Malformed TLP Severity 275476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19 ECRC Error Severity 275576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20 Unsupported Request Error Severity */ 275676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 275776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status 275876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6 Bad TLP Status 275976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7 Bad DLLP Status 276076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8 REPLAY_NUM Rollover Status 276176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Replay Timer Timeout Status */ 276276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 276376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask 276476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6 Bad TLP Mask 276576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7 Bad DLLP Mask 276676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8 REPLAY_NUM Rollover Mask 276776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12 Replay Timer Timeout Mask */ 276876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 276976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]; 277076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 277176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_header_log_register_st header_log_register; 277276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 277376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x006a0]; 277476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 277576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 277676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 277776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event Data Field - Performance Monitor */ 277876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 277976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_performance_monitor_event_st { /* Little Endian */ 278076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */ 278176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 278276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC 278376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x02 - RQPC 278476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x03 - CQC 278576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x04 - Rkey 278676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x05 - TLB 278776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x06 - port0 278876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x07 - port1 */ 278976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00018]; 279076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 279176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00040]; 279276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 279376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 279476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 279576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - Page Faults */ 279676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 279776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_page_fault_event_data_st { /* Little Endian */ 279876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 279976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 280076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 280176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 280276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */ 280376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 280476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */ 280576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00003]; 280676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */ 280776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */ 280876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */ 280976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */ 281076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */ 281176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 281276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */ 281376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 281476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 281576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */ 281676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 281776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 281876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 281976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* WQE segments format */ 282076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 282176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_wqe_segment_st { /* Little Endian */ 282276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */ 282376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 282476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00280]; 282576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 282676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */ 282776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 282876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00100]; 282976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 283076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t recv_wqe_segment_ctrl[4][0x00020];/* Receive segment format */ 283176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 283276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00080]; 283376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 283476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 283576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 283676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - Port State Change #### michal - match PRM */ 283776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 283876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_port_state_change_st { /* Little Endian */ 283976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00040]; 284076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 284176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x0001c]; 284276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */ 284376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 284476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 284576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00060]; 284676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 284776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 284876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 284976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - Completion Queue Error #### michal - match PRM */ 285076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 285176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_completion_queue_error_st { /* Little Endian */ 285276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 285376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 285476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 285576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00020]; 285676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 285776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t syndrome[0x00008]; /* Error syndrome 285876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x01 - CQ overrun 285976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x02 - CQ access violation error */ 286076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00018]; 286176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 286276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00060]; 286376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 286476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 286576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 286676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - Completion Event #### michal - match PRM */ 286776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 286876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_completion_event_st { /* Little Endian */ 286976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 287076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 287176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 287276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x000a0]; 287376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 287476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 287576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 287676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event Queue Entry #### michal - match to PRM */ 287776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 287876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_event_queue_entry_st { /* Little Endian */ 287976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. 288076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Defined for events which have sub types, zero elsewhere. */ 288176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00008]; 288276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_type[0x00008]; /* Event Type */ 288376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 288476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 288576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */ 288676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 288776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00007]; 288876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00001]; /* Owner of the entry 288976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 SW 289076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 HW */ 289176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00018]; 289276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 289376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 289476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 289576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* QP/EE State Transitions Command Parameters ###michal - doesn't match PRM (field name changed) */ 289676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 289776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_qp_ee_state_transitions_st { /* Little Endian */ 289876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */ 289976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 290076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 290176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 290276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data ###michal - field has replaced with "qpc_data" (size .1948) */ 290376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 290476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00800]; 290576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 290676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 290776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 290876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Completion Queue Entry Format #### michal - fixed by gdror */ 290976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 291076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_completion_queue_entry_st { /* Little Endian */ 291176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 291276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00002]; 291376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t d2s[0x00001]; /* Duplicate to Sniffer. This bit is set if both Send and Receive queues are subject for sniffer queue. The HW delivers 291476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman packet only to send-associated sniffer receive queue. */ 291576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fcrc_sd[0x00001]; /* FCRC: If set, FC CRC is correct in FC frame encapsulated in payload. Valid for Raw Frame FC receive queue only. 291676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman SD: CQ associated with Sniffer receive queue. If set, packets were skipped due to lack of receive buffers on the Sniffer receive queue */ 291776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t fl[0x00001]; /* Force Loopback Valid for responder RawEth and UD only. */ 291876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vlan[0x00002]; /* Valid for RawEth and UD over Ethernet only. Applicable for RawEth and UD over Ethernet Receive queue 291976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 00 - No VLAN header was present in the packet 292076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 01 - C-VLAN (802.1q) Header was present in the frame. 292176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10 - S-VLAN (802.1ad) Header was present in the frame. */ 292276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t dife[0x00001]; /* DIF Error */ 292376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 292476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t immediate_rssvalue_invalidatekey[0x00020];/* For a responder CQE, if completed WQE Opcode is Send With Immediate or Write With Immediate, this field contains immediate field of the received message. 292576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For a responder CQE, if completed WQE Opcode is Send With Invalidate, this field contains the R_key that was invalidated. 292676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For a responder CQE of a GSI packet this filed contains the Pkey Index of the packet. 292776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For IPoIB (UD) and RawEth CQEs this field contains the RSS hash function value. 292876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise, this field is reserved. */ 292976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 293076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t srq_rqpn[0x00018]; /* For Responder UD QPs, Remote (source) QP number. 293176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For Responder SRC QPs, SRQ number. 293276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise, this field is reserved. */ 293376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ml_path_mac_index[0x00007];/* For responder UD over IB CQE: These are the lower LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. Invalid if incoming message DLID is the permissive LID or incoming message is multicast. 293476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For responder UD over Ethernet and RawEth CQEs: Index of the MAC Table entry that the packet DMAC was matched against. 293576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise, this field is reserved. */ 293676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t g[0x00001]; /* For responder UD over IB CQE this bit indicates the presence of a GRH 293776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For responder UD over Ethernet CQE this bit is set if IPv6 L3 header was present in the packet, this bit is cleared if IPv4 L3 Header was present in the packet. 293876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise, this field is reserved. */ 293976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 294076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t slid_smac47_32[0x00010];/* For responder UD over IB CQE it is the source LID of the packet. 294176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For responder UD over Ethernet and RawEth CQEs it is the source-MAC[47:32] of the packet. 294276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise, this field is reserved. */ 294376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vid[0x0000c]; /* Frame VID, valid for Responder Raw Ethernet and UD over Ethernet QP. Otherwise, this field is reserved. */ 294476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; /* For responder UD over IB - the Service Level of the packet. 294576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For responder UD over Ethernet and RawEth - it is VLAN-header[15:12] 294676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise, this field is reserved. */ 294776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 294876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t smac31_0_rawether_ipoib_status[0x00020];/* For responder UD over Ethernet - source MAC[31:0] of the packet. 294976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For responder RawEth and UD over IB - RawEth-IPoIB status {3 reserved, ipok,udp,tcp,ipv4opt,ipv6,ipv4vf,ipv4,rht(6),ipv6extmask(6),reserved(2),l2am,reserved(2),bfcs,reserved(2),enc} 295076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Otherwise, this field is reserved. */ 295176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 295276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data transferred. Applicable for RDMA-read, Atomic and all receive operations. completions. 295376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman For Receive Queue that is subject for headers. separation, byte_cnt[31:24] specify number of bytes scattered to the first scatter entry (headers. length). Byte_cnt[23:0] specify total byte count received (including headers). */ 295476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 295576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t checksum[0x00010]; /* Valid for RawEth and IPoIB only. */ 295676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t wqe_counter[0x00010]; 295776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 295876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[0x00005]; /* Send completions - same encoding as WQE. 295976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Error coding is 0x1F 296076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman Receive: 296176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x0 - RDMA-Write with Immediate 296276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x1 - Send 296376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x2 - Send with Immediate 296476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0x3 - Send & Invalidate 296576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 296676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t is[0x00001]; /* inline scatter */ 296776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ 296876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ 296976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00010]; 297076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00008]; 297176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 297276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 297376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 297476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 297576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 297676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mcg_qps_st { /* Little Endian */ 297776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mcg_qp_dw_st dw[128]; 297876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 297976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 298076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 298176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 298276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 298376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_mcg_hdr_st { /* Little Endian */ 298476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00006]; 298576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t next_mcg[0x0001a]; 298676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 298776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t members_count[0x00018]; 298876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00008]; 298976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 299076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00020]; 299176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 299276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00020]; 299376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 299476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t gid3[0x00020]; 299576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 299676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t gid2[0x00020]; 299776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 299876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t gid1[0x00020]; 299976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 300076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t gid0[0x00020]; 300176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 300276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 300376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 300476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 300576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 300676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_sched_queue_context_st { /* Little Endian */ 300776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t policy[0x00003]; /* Schedule Queue Policy - 0 - LLSQ, 1 - GBSQ, 2 - BESQ */ 300876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t vl15[0x00001]; 300976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sl[0x00004]; /* SL this Schedule Queue is associated with (if vl15 bit is 0) */ 301076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t port[0x00002]; /* Port this Schedule Queue is associated with */ 301176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00006]; 301276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t weight[0x00010]; /* Weight of this SchQ */ 301376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 301476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 301576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 301676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 301776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 301876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_ecc_detect_event_data_st { /* Little Endian */ 301976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 302076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 302176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cause_lsb[0x00001]; 302276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 302376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cause_msb[0x00001]; 302476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 302576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_rmw[0x00001]; 302676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_src_id[0x00003]; 302776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_da[0x00002]; 302876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ba[0x00002]; 302976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00011]; 303076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t overflow[0x00001]; 303176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 303276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ra[0x00010]; 303376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ca[0x00010]; 303476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 303576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 303676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 303776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Event_data Field - ECC Detection Event */ 303876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 303976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_scrubbing_event_st { /* Little Endian */ 304076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00080]; 304176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 304276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause: 304376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman single ECC error in the 64bit lsb data, on the rise edge of the clock */ 304476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x00002]; 304576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause: 304676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman single ECC error in the 64bit msb data, on the fall edge of the clock */ 304776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x00002]; 304876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_rmw[0x00001]; /* transaction type: 304976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 0 - read 305076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1 - read/modify/write */ 305176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */ 305276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_da[0x00002]; /* Error DIMM address */ 305376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ba[0x00002]; /* Error bank address */ 305476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x00011]; 305576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */ 305676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 305776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ra[0x00010]; /* Error row address */ 305876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t err_ca[0x00010]; /* Error column address */ 305976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 306076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 306176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 306276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* */ 306376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 306476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_eq_cmd_doorbell_st { /* Little Endian */ 306576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x00020]; 306676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 306776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 306876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 306976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 0 */ 307076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 307176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct hermonprm_hermon_prm_st { /* Little Endian */ 307276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */ 307376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 307476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved0[0x7ff00]; 307576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 307676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */ 307776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 307876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved1[0x7f000]; 307976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 308076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */ 308176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 308276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved2[0x7ff00]; 308376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 308476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_completion_event_st completion_event;/* Event_data Field - Completion Event */ 308576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 308676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved3[0x7ff40]; 308776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 308876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */ 308976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 309076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved4[0x7ff40]; 309176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 309276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */ 309376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 309476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved5[0x7ff40]; 309576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 309676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_wqe_segment_st wqe_segment;/* WQE segments format */ 309776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 309876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved6[0x7f000]; 309976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 310076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */ 310176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 310276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved7[0x7ff40]; 310376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 310476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */ 310576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 310676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved8[0xfff20]; 310776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 310876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */ 310976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 311076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved9[0x7f000]; 311176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 311276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */ 311376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 311476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved10[0x00040]; 311576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 311676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_gpio_event_data_st gpio_event_data; 311776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 311876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved11[0x7fe40]; 311976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 312076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 312176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 312276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved12[0x7ff00]; 312376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 312476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */ 312576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 312676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved13[0x7f840]; 312776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 312876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_address_path_st address_path;/* Address Path */ 312976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 313076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved14[0x7fea0]; 313176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 313276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */ 313376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 313476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved15[0x7fe00]; 313576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 313676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */ 313776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 313876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved16[0x7fe00]; 313976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 314076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */ 314176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 314276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved17[0x7ffc0]; 314376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 314476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_eqc_st eqc; /* Event Queue Context Table Entry */ 314576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 314676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved18[0x7fe00]; 314776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 314876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_performance_monitors_st performance_monitors;/* Performance Monitors */ 314976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 315076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved19[0x7ff80]; 315176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 315276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */ 315376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 315476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved20[0xfff20]; 315576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 315676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */ 315776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 315876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved21[0x7f000]; 315976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 316076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */ 316176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 316276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved22[0x7fc00]; 316376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 316476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */ 316576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 316676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved23[0x7ffc0]; 316776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 316876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_multicastparam_st multicastparam;/* Multicast Support Parameters */ 316976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 317076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved24[0x7ff00]; 317176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 317276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */ 317376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 317476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved25[0x7ff00]; 317576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 317676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved26[0x00800]; 317776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 317876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved27[0x00100]; 317976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 318076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved28[0x7f700]; 318176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 318276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved29[0x00100]; 318376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 318476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved30[0x7ff00]; 318576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 318676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */ 318776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 318876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved31[0x7f800]; 318976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 319076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */ 319176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 319276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved32[0x7f800]; 319376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 319476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_query_dev_cap_st query_dev_cap;/* Query Device Limitations */ 319576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 319676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved33[0x7f800]; 319776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 319876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_uar_params_st uar_params;/* UAR Parameters */ 319976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 320076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved34[0x7ff00]; 320176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 320276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_init_port_st init_port;/* INIT_PORT Parameters */ 320376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 320476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved35[0x7f800]; 320576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 320676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgm_entry_st mgm_entry;/* Multicast Group Member */ 320776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 320876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved36[0x7fe00]; 320976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 321076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_set_ib_st set_ib; /* SET_IB Parameters */ 321176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 321276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved37[0x7fe00]; 321376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 321476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */ 321576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 321676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved38[0x7ff80]; 321776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 321876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ 321976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved39[0x7ffc0]; 322176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */ 322376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved40[0x7ffc0]; 322576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */ 322776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 322876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved41[0xfffc0]; 322976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_uar_st uar; /* User Access Region */ 323176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved42[0x7c000]; 323376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mgmqp_st mgmqp; /* Multicast Group Member QP */ 323576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved43[0x7ffe0]; 323776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 323876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */ 323976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved44[0x7f800]; 324176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */ 324376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved45[0x00900]; 324576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */ 324776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 324876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved46[0x7e6e0]; 324976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */ 325176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved47[0x7fe00]; 325376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */ 325576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved48[0x7ff00]; 325776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 325876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */ 325976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved49[0x7ff40]; 326176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */ 326376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved50[0x7f000]; 326576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_performance_counters_st performance_counters;/* Performance Counters */ 326776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 326876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved51[0x9ff800]; 326976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 327176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved52[0x7ff00]; 327376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_pbl_st pbl; /* Physical Buffer List */ 327576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved53[0x7ff00]; 327776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 327876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_srq_context_st srq_context;/* SRQ Context */ 327976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved54[0x7fe80]; 328176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */ 328376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved55[0x7f800]; 328576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */ 328776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 328876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved56[0x7ff80]; 328976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */ 329176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved57[0x7ffc0]; 329376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */ 329576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved58[0x7ffc0]; 329776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 329876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_qp_db_record_st qp_db_record;/* QP_DB_Record */ 329976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved59[0x00020]; 330176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved60[0x1fffc0]; 330376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */ 330576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */ 330776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 330876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved61[0x01000]; 330976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved62[0x00040]; 331176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved63[0x00fc0]; 331376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct hermonprm_clr_int_st clr_int; /* Clear Interrupt Register */ 331576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reserved64[0xffcfc0]; 331776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* -------------- */ 331876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 331976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif /* H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H */ 3320