176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. 376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * This software is available to you under a choice of one of two 676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * licenses. You may choose to be licensed under the terms of the GNU 776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * General Public License (GPL) Version 2, available from the file 876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * COPYING in the main directory of this source tree, or the 976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * OpenIB.org BSD license below: 1076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 1176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Redistribution and use in source and binary forms, with or 1276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * without modification, are permitted provided that the following 1376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * conditions are met: 1476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 1576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * - Redistributions of source code must retain the above 1676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * copyright notice, this list of conditions and the following 1776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * disclaimer. 1876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 1976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * - Redistributions in binary form must reproduce the above 2076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * copyright notice, this list of conditions and the following 2176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * disclaimer in the documentation and/or other materials 2276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * provided with the distribution. 2376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 2476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 2776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 2876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 2976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 3076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 3176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * SOFTWARE. 3276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 3376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 3476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* This file is mechanically generated from RTL. Any hand-edits will be lost! */ 3576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */ 3776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3876d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanFILE_LICENCE ( GPL2_ONLY ); 3976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_Revision_offset 0x00000000UL 4176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_Revision_pb { 4276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t R_ChipRevMinor[8]; 4376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t R_ChipRevMajor[8]; 4476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t R_Arch[8]; 4576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t R_SW[8]; 4676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t BoardID[8]; 4776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t R_Emulation_Revcode[22]; 4876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t R_Emulation[1]; 4976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t R_Simulator[1]; 5076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 5176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_Revision { 5276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_Revision_pb ); 5376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 5476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_Control_offset 0x00000008UL 5676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_Control_pb { 5776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SyncReset[1]; 5876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t FreezeMode[1]; 5976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkEn[1]; 6076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIERetryBufDiagEn[1]; 6176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TxLatency[1]; 6276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[1]; 6376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIECplQDiagEn[1]; 6476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SyncResetExceptPcieIRAMRST[1]; 6576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[56]; 6676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 6776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_Control { 6876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_Control_pb ); 6976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 7076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PageAlign_offset 0x00000010UL 7276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PortCnt_offset 0x00000018UL 7476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_DbgPortSel_offset 0x00000020UL 7676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_DbgPortSel_pb { 7776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NibbleSel0[4]; 7876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NibbleSel1[4]; 7976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NibbleSel2[4]; 8076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NibbleSel3[4]; 8176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NibbleSel4[4]; 8276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NibbleSel5[4]; 8376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NibbleSel6[4]; 8476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NibbleSel7[4]; 8576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SrcMuxSel[14]; 8676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t DbgClkPortSel[5]; 8776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t EnDbgPort[1]; 8876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t EnEnhancedDebugMode[1]; 8976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t EnhMode_SrcMuxSelIndex[10]; 9076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t EnhMode_SrcMuxSelWrEn[1]; 9176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 9276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_DbgPortSel { 9376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_DbgPortSel_pb ); 9476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 9576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_DebugSigsIntSel_offset 0x00000028UL 9776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_DebugSigsIntSel_pb { 9876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t debug_port_sel_pcs_pipe_lane07[3]; 9976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t debug_port_sel_pcs_pipe_lane815[3]; 10076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t debug_port_sel_pcs_sdout[1]; 10176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t debug_port_sel_pcs_symlock_elfifo_lane[4]; 10276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t debug_port_sel_pcs_rxdet_encdec_lane[4]; 10376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t debug_port_sel_pcie_rx_tx[1]; 10476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t debug_port_sel_xgxs[4]; 10576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t debug_port_sel_epb_pcie[1]; 10676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[43]; 10776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 10876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_DebugSigsIntSel { 10976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_DebugSigsIntSel_pb ); 11076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 11176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendRegBase_offset 0x00000030UL 11376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_UserRegBase_offset 0x00000038UL 11576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_CntrRegBase_offset 0x00000040UL 11776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 11876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_Scratch_offset 0x00000048UL 11976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_REG_000050_offset 0x00000050UL 12176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IntBlocked_offset 0x00000060UL 12376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IntBlocked_pb { 12476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail0IntBlocked[1]; 12576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail1IntBlocked[1]; 12676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail2IntBlocked[1]; 12776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail3IntBlocked[1]; 12876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail4IntBlocked[1]; 12976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail5IntBlocked[1]; 13076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail6IntBlocked[1]; 13176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail7IntBlocked[1]; 13276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail8IntBlocked[1]; 13376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail9IntBlocked[1]; 13476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail10IntBlocked[1]; 13576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail11IntBlocked[1]; 13676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail12IntBlocked[1]; 13776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail13IntBlocked[1]; 13876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail14IntBlocked[1]; 13976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail15IntBlocked[1]; 14076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail16IntBlocked[1]; 14176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[9]; 14276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t JIntBlocked[1]; 14376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBSerdesTrimDoneIntBlocked[1]; 14476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t assertGPIOIntBlocked[1]; 14576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PioBufAvailIntBlocked[1]; 14676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PioSetIntBlocked[1]; 14776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ErrorIntBlocked[1]; 14876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg0IntBlocked[1]; 14976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg1IntBlocked[1]; 15076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg2IntBlocked[1]; 15176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg3IntBlocked[1]; 15276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg4IntBlocked[1]; 15376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg5IntBlocked[1]; 15476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg6IntBlocked[1]; 15576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg7IntBlocked[1]; 15676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg8IntBlocked[1]; 15776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg9IntBlocked[1]; 15876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg10IntBlocked[1]; 15976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg11IntBlocked[1]; 16076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg12IntBlocked[1]; 16176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg13IntBlocked[1]; 16276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg14IntBlocked[1]; 16376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg15IntBlocked[1]; 16476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg16IntBlocked[1]; 16576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[13]; 16676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDisabledBlocked[1]; 16776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaIntBlocked[1]; 16876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 16976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IntBlocked { 17076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IntBlocked_pb ); 17176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 17276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IntMask_offset 0x00000068UL 17476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IntMask_pb { 17576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail0IntMask[1]; 17676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail1IntMask[1]; 17776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail2IntMask[1]; 17876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail3IntMask[1]; 17976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail4IntMask[1]; 18076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail5IntMask[1]; 18176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail6IntMask[1]; 18276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail7IntMask[1]; 18376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail8IntMask[1]; 18476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail9IntMask[1]; 18576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail10IntMask[1]; 18676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail11IntMask[1]; 18776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail12IntMask[1]; 18876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail13IntMask[1]; 18976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail14IntMask[1]; 19076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail15IntMask[1]; 19176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail16IntMask[1]; 19276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[9]; 19376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t JIntMask[1]; 19476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBSerdesTrimDoneIntMask[1]; 19576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t assertGPIOIntMask[1]; 19676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PioBufAvailIntMask[1]; 19776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PioSetIntMask[1]; 19876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ErrorIntMask[1]; 19976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg0IntMask[1]; 20076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg1IntMask[1]; 20176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg2IntMask[1]; 20276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg3IntMask[1]; 20376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg4IntMask[1]; 20476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg5IntMask[1]; 20576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg6IntMask[1]; 20676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg7IntMask[1]; 20776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg8IntMask[1]; 20876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg9IntMask[1]; 20976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg10IntMask[1]; 21076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg11IntMask[1]; 21176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg12IntMask[1]; 21276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg13IntMask[1]; 21376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg14IntMask[1]; 21476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg15IntMask[1]; 21576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg16IntMask[1]; 21676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[13]; 21776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDisabledMasked[1]; 21876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaIntMask[1]; 21976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 22076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IntMask { 22176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IntMask_pb ); 22276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 22376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IntStatus_offset 0x00000070UL 22576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IntStatus_pb { 22676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail0[1]; 22776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail1[1]; 22876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail2[1]; 22976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail3[1]; 23076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail4[1]; 23176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail5[1]; 23276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail6[1]; 23376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail7[1]; 23476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail8[1]; 23576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail9[1]; 23676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail10[1]; 23776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail11[1]; 23876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail12[1]; 23976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail13[1]; 24076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail14[1]; 24176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail15[1]; 24276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail16[1]; 24376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[9]; 24476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t JInt[1]; 24576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBSerdesTrimDone[1]; 24676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t assertGPIO[1]; 24776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PioBufAvail[1]; 24876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PioSent[1]; 24976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Error[1]; 25076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg0[1]; 25176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg1[1]; 25276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg2[1]; 25376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg3[1]; 25476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg4[1]; 25576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg5[1]; 25676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg6[1]; 25776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg7[1]; 25876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg8[1]; 25976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg9[1]; 26076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg10[1]; 26176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg11[1]; 26276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg12[1]; 26376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg13[1]; 26476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg14[1]; 26576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg15[1]; 26676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg16[1]; 26776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[13]; 26876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDisabled[1]; 26976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaInt[1]; 27076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 27176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IntStatus { 27276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IntStatus_pb ); 27376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 27476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IntClear_offset 0x00000078UL 27676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IntClear_pb { 27776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail0IntClear[1]; 27876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail1IntClear[1]; 27976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail2IntClear[1]; 28076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail3IntClear[1]; 28176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail4IntClear[1]; 28276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail5IntClear[1]; 28376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail6IntClear[1]; 28476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail7IntClear[1]; 28576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail8IntClear[1]; 28676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail9IntClear[1]; 28776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail10IntClear[1]; 28876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail11IntClear[1]; 28976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail12IntClear[1]; 29076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail13IntClear[1]; 29176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail14IntClear[1]; 29276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail15IntClear[1]; 29376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvAvail16IntClear[1]; 29476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[9]; 29576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t JIntClear[1]; 29676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBSerdesTrimDoneClear[1]; 29776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t assertGPIOIntClear[1]; 29876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PioBufAvailIntClear[1]; 29976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PioSetIntClear[1]; 30076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ErrorIntClear[1]; 30176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg0IntClear[1]; 30276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg1IntClear[1]; 30376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg2IntClear[1]; 30476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg3IntClear[1]; 30576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg4IntClear[1]; 30676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg5IntClear[1]; 30776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg6IntClear[1]; 30876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg7IntClear[1]; 30976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg8IntClear[1]; 31076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg9IntClear[1]; 31176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg10IntClear[1]; 31276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg11IntClear[1]; 31376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg12IntClear[1]; 31476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg13IntClear[1]; 31576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg14IntClear[1]; 31676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg15IntClear[1]; 31776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUrg16IntClear[1]; 31876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[13]; 31976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDisabledClear[1]; 32076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaIntClear[1]; 32176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 32276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IntClear { 32376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IntClear_pb ); 32476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 32576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 32676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_ErrMask_offset 0x00000080UL 32776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ErrMask_pb { 32876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvFormatErrMask[1]; 32976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvVCRCErrMask[1]; 33076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvICRCErrMask[1]; 33176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvMinPktLenErrMask[1]; 33276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvMaxPktLenErrMask[1]; 33376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvLongPktLenErrMask[1]; 33476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvShortPktLenErrMask[1]; 33576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUnexpectedCharErrMask[1]; 33676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUnsupportedVLErrMask[1]; 33776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvEBPErrMask[1]; 33876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvIBFlowErrMask[1]; 33976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvBadVersionErrMask[1]; 34076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvEgrFullErrMask[1]; 34176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrFullErrMask[1]; 34276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvBadTidErrMask[1]; 34376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrLenErrMask[1]; 34476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrErrMask[1]; 34576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvIBLostLinkErrMask[1]; 34676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[9]; 34776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendSpecialTriggerErrMask[1]; 34876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDisabledErrMask[1]; 34976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendMinPktLenErrMask[1]; 35076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendMaxPktLenErrMask[1]; 35176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnderRunErrMask[1]; 35276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendPktLenErrMask[1]; 35376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDroppedSmpPktErrMask[1]; 35476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDroppedDataPktErrMask[1]; 35576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendPioArmLaunchErrMask[1]; 35676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnexpectedPktNumErrMask[1]; 35776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnsupportedVLErrMask[1]; 35876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendBufMisuseErrMask[1]; 35976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaGenMismatchErrMask[1]; 36076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaOutOfBoundErrMask[1]; 36176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaTailOutOfBoundErrMask[1]; 36276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaBaseErrMask[1]; 36376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDma1stDescErrMask[1]; 36476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaRpyTagErrMask[1]; 36576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDwEnErrMask[1]; 36676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaMissingDwErrMask[1]; 36776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaUnexpDataErrMask[1]; 36876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBStatusChangedMask[1]; 36976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t InvalidAddrErrMask[1]; 37076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ResetNegatedMask[1]; 37176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t HardwareErrMask[1]; 37276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDescAddrMisalignErrMask[1]; 37376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t InvalidEEPCmdMask[1]; 37476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[10]; 37576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 37676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ErrMask { 37776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrMask_pb ); 37876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 37976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 38076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_ErrStatus_offset 0x00000088UL 38176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ErrStatus_pb { 38276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvFormatErr[1]; 38376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvVCRCErr[1]; 38476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvICRCErr[1]; 38576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvMinPktLenErr[1]; 38676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvMaxPktLenErr[1]; 38776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvLongPktLenErr[1]; 38876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvShortPktLenErr[1]; 38976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUnexpectedCharErr[1]; 39076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUnsupportedVLErr[1]; 39176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvEBPErr[1]; 39276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvIBFlowErr[1]; 39376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvBadVersionErr[1]; 39476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvEgrFullErr[1]; 39576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrFullErr[1]; 39676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvBadTidErr[1]; 39776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrLenErr[1]; 39876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrErr[1]; 39976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvIBLostLinkErr[1]; 40076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[9]; 40176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendSpecialTriggerErr[1]; 40276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDisabledErr[1]; 40376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendMinPktLenErr[1]; 40476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendMaxPktLenErr[1]; 40576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnderRunErr[1]; 40676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendPktLenErr[1]; 40776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDroppedSmpPktErr[1]; 40876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDroppedDataPktErr[1]; 40976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendPioArmLaunchErr[1]; 41076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnexpectedPktNumErr[1]; 41176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnsupportedVLErr[1]; 41276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendBufMisuseErr[1]; 41376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaGenMismatchErr[1]; 41476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaOutOfBoundErr[1]; 41576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaTailOutOfBoundErr[1]; 41676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaBaseErr[1]; 41776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDma1stDescErr[1]; 41876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaRpyTagErr[1]; 41976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDwEnErr[1]; 42076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaMissingDwErr[1]; 42176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaUnexpDataErr[1]; 42276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBStatusChanged[1]; 42376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t InvalidAddrErr[1]; 42476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ResetNegated[1]; 42576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t HardwareErr[1]; 42676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDescAddrMisalignErr[1]; 42776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t InvalidEEPCmdErr[1]; 42876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[10]; 42976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 43076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ErrStatus { 43176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrStatus_pb ); 43276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 43376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 43476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_ErrClear_offset 0x00000090UL 43576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ErrClear_pb { 43676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvFormatErrClear[1]; 43776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvVCRCErrClear[1]; 43876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvICRCErrClear[1]; 43976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvMinPktLenErrClear[1]; 44076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvMaxPktLenErrClear[1]; 44176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvLongPktLenErrClear[1]; 44276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvShortPktLenErrClear[1]; 44376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUnexpectedCharErrClear[1]; 44476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvUnsupportedVLErrClear[1]; 44576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvEBPErrClear[1]; 44676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvIBFlowErrClear[1]; 44776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvBadVersionErrClear[1]; 44876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvEgrFullErrClear[1]; 44976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrFullErrClear[1]; 45076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvBadTidErrClear[1]; 45176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrLenErrClear[1]; 45276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrErrClear[1]; 45376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvIBLostLinkErrClear[1]; 45476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[9]; 45576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendSpecialTriggerErrClear[1]; 45676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDisabledErrClear[1]; 45776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendMinPktLenErrClear[1]; 45876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendMaxPktLenErrClear[1]; 45976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnderRunErrClear[1]; 46076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendPktLenErrClear[1]; 46176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDroppedSmpPktErrClear[1]; 46276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDroppedDataPktErrClear[1]; 46376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendPioArmLaunchErrClear[1]; 46476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnexpectedPktNumErrClear[1]; 46576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendUnsupportedVLErrClear[1]; 46676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendBufMisuseErrClear[1]; 46776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaGenMismatchErrClear[1]; 46876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaOutOfBoundErrClear[1]; 46976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaTailOutOfBoundErrClear[1]; 47076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaBaseErrClear[1]; 47176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDma1stDescErrClear[1]; 47276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaRpyTagErrClear[1]; 47376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDwEnErrClear[1]; 47476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaMissingDwErrClear[1]; 47576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaUnexpDataErrClear[1]; 47676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBStatusChangedClear[1]; 47776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t InvalidAddrErrClear[1]; 47876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ResetNegatedClear[1]; 47976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t HardwareErrClear[1]; 48076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaDescAddrMisalignErrClear[1]; 48176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t InvalidEEPCmdErrClear[1]; 48276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[10]; 48376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 48476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ErrClear { 48576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrClear_pb ); 48676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 48776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 48876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_HwErrMask_offset 0x00000098UL 48976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_HwErrMask_pb { 49076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIeMemParityErrMask[8]; 49176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved3[20]; 49276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaMemReadErrMask[1]; 49376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PoisonedTLPMask[1]; 49476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PcieCplTimeoutMask[1]; 49576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIeBusParityErrMask[3]; 49676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[2]; 49776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIEOct0_uC_MemoryParityErrMask[1]; 49876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIEOct1_uC_MemoryParityErrMask[1]; 49976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_uC_MemoryParityErrMask[1]; 50076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t DDSRXEQMemoryParityErrMask[1]; 50176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TXEMemParityErrMask[4]; 50276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RXEMemParityErrMask[7]; 50376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[3]; 50476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PowerOnBISTFailedMask[1]; 50576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[1]; 50676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ0PClkNotDetectMask[1]; 50776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ1PClkNotDetectMask[1]; 50876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ2PClkNotDetectMask[1]; 50976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ3PClkNotDetectMask[1]; 51076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBSerdesPClkNotDetectMask[1]; 51176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Clk_uC_PLLNotLockedMask[1]; 51276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBCBusToSPCParityErrMask[1]; 51376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBCBusFromSPCParityErrMask[1]; 51476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 51576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_HwErrMask { 51676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrMask_pb ); 51776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 51876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 51976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_HwErrStatus_offset 0x000000a0UL 52076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_HwErrStatus_pb { 52176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIeMemParity[8]; 52276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved3[20]; 52376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaMemReadErr[1]; 52476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PoisenedTLP[1]; 52576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PcieCplTimeout[1]; 52676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIeBusParity[3]; 52776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[2]; 52876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIE_uC_Oct0MemoryParityErr[1]; 52976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIE_uC_Oct1MemoryParityErr[1]; 53076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_uC_MemoryParityErr[1]; 53176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t DDSRXEQMemoryParityErr[1]; 53276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TXEMemParity[4]; 53376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RXEMemParity[7]; 53476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[3]; 53576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PowerOnBISTFailed[1]; 53676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[1]; 53776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ0PClkNotDetect[1]; 53876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ1PClkNotDetect[1]; 53976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ2PClkNotDetect[1]; 54076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ3PClkNotDetect[1]; 54176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBSerdesPClkNotDetect[1]; 54276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Clk_uC_PLLNotLocked[1]; 54376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBCBusToSPCParityErr[1]; 54476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBCBusFromSPCParityErr[1]; 54576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 54676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_HwErrStatus { 54776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrStatus_pb ); 54876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 54976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 55076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_HwErrClear_offset 0x000000a8UL 55176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_HwErrClear_pb { 55276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIeMemParityClr[8]; 55376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved3[20]; 55476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaMemReadErrClear[1]; 55576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PoisonedTLPClear[1]; 55676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PcieCplTimeoutClear[1]; 55776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIeBusParityClr[3]; 55876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[2]; 55976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIE_uC_Oct0MemoryParityErrClear[1]; 56076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIE_uC_Oct1MemoryParityErrClear[1]; 56176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_uC_MemoryParityErrClear[1]; 56276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t DDSRXEQMemoryParityErrClear[1]; 56376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TXEMemParityClear[4]; 56476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RXEMemParityClear[7]; 56576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[3]; 56676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PowerOnBISTFailedClear[1]; 56776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[1]; 56876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ0PClkNotDetectClear[1]; 56976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ1PClkNotDetectClear[1]; 57076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ2PClkNotDetectClear[1]; 57176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PCIESerdesQ3PClkNotDetectClear[1]; 57276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBSerdesPClkNotDetectClear[1]; 57376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Clk_uC_PLLNotLockedClear[1]; 57476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBCBusToSPCparityErrClear[1]; 57576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBCBusFromSPCParityErrClear[1]; 57676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 57776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_HwErrClear { 57876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrClear_pb ); 57976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 58076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 58176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_HwDiagCtrl_offset 0x000000b0UL 58276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_HwDiagCtrl_pb { 58376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t forcePCIeMemParity[8]; 58476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[23]; 58576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t forcePCIeBusParity[4]; 58676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[1]; 58776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ForcePCIE_uC_Oct0MemoryParityErr[1]; 58876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ForcePCIE_uC_Oct1MemoryParityErr[1]; 58976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ForceIB_uC_MemoryParityErr[1]; 59076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ForceDDSRXEQMemoryParityErr[1]; 59176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ForceTxMemparityErr[4]; 59276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ForceRxMemParityErr[7]; 59376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[9]; 59476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t CounterDisable[1]; 59576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t CounterWrEnable[1]; 59676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ForceIBCBusToSPCParityErr[1]; 59776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ForceIBCBusFromSPCParityErr[1]; 59876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 59976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_HwDiagCtrl { 60076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_HwDiagCtrl_pb ); 60176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 60276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 60376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_REG_0000B8_offset 0x000000b8UL 60476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 60576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBCStatus_offset 0x000000c0UL 60676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCStatus_pb { 60776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkTrainingState[5]; 60876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkState[3]; 60976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkSpeedActive[1]; 61076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkWidthActive[1]; 61176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t DDS_RXEQ_FAIL[1]; 61276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_SERDES_TRIM_DONE[1]; 61376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBRxLaneReversed[1]; 61476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IBTxLaneReversed[1]; 61576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 61676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TxReady[1]; 61776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TxCreditOk[1]; 61876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 61976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 62076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCStatus { 62176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCStatus_pb ); 62276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 62376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 62476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBCCtrl_offset 0x000000c8UL 62576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCCtrl_pb { 62676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t FlowCtrlPeriod[8]; 62776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t FlowCtrlWaterMark[8]; 62876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkInitCmd[3]; 62976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkCmd[2]; 63076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t MaxPktLen[11]; 63176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PhyerrThreshold[4]; 63276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t OverrunThreshold[4]; 63376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t CreditScale[3]; 63476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[19]; 63576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkDownDefaultState[1]; 63676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Loopback[1]; 63776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 63876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCCtrl { 63976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCCtrl_pb ); 64076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 64176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 64276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_EXTStatus_offset 0x000000d0UL 64376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_EXTStatus_pb { 64476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[14]; 64576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t MemBISTEndTest[1]; 64676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t MemBISTDisabled[1]; 64776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[16]; 64876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 64976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t GPIOIn[16]; 65076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 65176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_EXTStatus { 65276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_EXTStatus_pb ); 65376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 65476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 65576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_EXTCtrl_offset 0x000000d8UL 65676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_EXTCtrl_pb { 65776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LEDGblErrRedOff[1]; 65876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LEDGblOkGreenOn[1]; 65976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LEDPriPortYellowOn[1]; 66076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LEDPriPortGreenOn[1]; 66176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[28]; 66276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t GPIOInvert[16]; 66376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t GPIOOe[16]; 66476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 66576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_EXTCtrl { 66676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_EXTCtrl_pb ); 66776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 66876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 66976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_GPIOOut_offset 0x000000e0UL 67076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 67176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_GPIOMask_offset 0x000000e8UL 67276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 67376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_GPIOStatus_offset 0x000000f0UL 67476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 67576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_GPIOClear_offset 0x000000f8UL 67676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 67776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvCtrl_offset 0x00000100UL 67876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvCtrl_pb { 67976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PortEnable[17]; 68076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IntrAvail[17]; 68176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvPartitionKeyDisable[1]; 68276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TailUpd[1]; 68376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PortCfg[2]; 68476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvQPMapEnable[1]; 68576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[25]; 68676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 68776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvCtrl { 68876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvCtrl_pb ); 68976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 69076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 69176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvBTHQP_offset 0x00000108UL 69276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvBTHQP_pb { 69376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvBTHQP[24]; 69476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[8]; 69576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 69676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 69776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvBTHQP { 69876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvBTHQP_pb ); 69976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 70076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 70176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrSize_offset 0x00000110UL 70276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 70376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrCnt_offset 0x00000118UL 70476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 70576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrEntSize_offset 0x00000120UL 70676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 70776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvTIDBase_offset 0x00000128UL 70876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 70976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvTIDCnt_offset 0x00000130UL 71076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 71176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrBase_offset 0x00000138UL 71276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 71376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrCnt_offset 0x00000140UL 71476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 71576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvBufBase_offset 0x00000148UL 71676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 71776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvBufSize_offset 0x00000150UL 71876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 71976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxIntMemBase_offset 0x00000158UL 72076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 72176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxIntMemSize_offset 0x00000160UL 72276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 72376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvPartitionKey_offset 0x00000168UL 72476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 72576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvQPMulticastPort_offset 0x00000170UL 72676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvQPMulticastPort_pb { 72776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvQpMcPort[5]; 72876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[59]; 72976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 73076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvQPMulticastPort { 73176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvQPMulticastPort_pb ); 73276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 73376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 73476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvPktLEDCnt_offset 0x00000178UL 73576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvPktLEDCnt_pb { 73676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t OFFperiod[32]; 73776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ONperiod[32]; 73876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 73976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvPktLEDCnt { 74076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvPktLEDCnt_pb ); 74176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 74276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 74376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBCDDRCtrl_offset 0x00000180UL 74476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCDDRCtrl_pb { 74576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_ENHANCED_MODE[1]; 74676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SD_SPEED[1]; 74776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SD_SPEED_SDR[1]; 74876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SD_SPEED_DDR[1]; 74976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SD_SPEED_QDR[1]; 75076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_NUM_CHANNELS[2]; 75176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_POLARITY_REV_SUPP[1]; 75276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_LANE_REV_SUPPORTED[1]; 75376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SD_RX_EQUAL_ENABLE[1]; 75476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SD_ADD_ENB[1]; 75576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SD_DDSV[1]; 75676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SD_DDS[4]; 75776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t HRTBT_ENB[1]; 75876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t HRTBT_AUTO[1]; 75976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t HRTBT_PORT[8]; 76076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t HRTBT_REQ[1]; 76176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[5]; 76276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_DLID[16]; 76376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_DLID_MASK[16]; 76476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 76576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCDDRCtrl { 76676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRCtrl_pb ); 76776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 76876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 76976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_HRTBT_GUID_offset 0x00000188UL 77076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 77176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IB_SDTEST_IF_TX_offset 0x00000190UL 77276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IB_SDTEST_IF_TX_pb { 77376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_T_TX_VALID[1]; 77476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_3_TX_VALID[1]; 77576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[9]; 77676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_TX_OPCODE[2]; 77776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_TX_SPEED[3]; 77876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 77976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_TX_TX_CFG[16]; 78076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_TX_RX_CFG[16]; 78176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 78276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IB_SDTEST_IF_TX { 78376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IB_SDTEST_IF_TX_pb ); 78476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 78576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 78676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IB_SDTEST_IF_RX_offset 0x00000198UL 78776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IB_SDTEST_IF_RX_pb { 78876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_T_RX_VALID[1]; 78976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_3_RX_VALID[1]; 79076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[14]; 79176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_RX_A[8]; 79276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_RX_B[8]; 79376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_RX_TX_CFG[16]; 79476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TS_RX_RX_CFG[16]; 79576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 79676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IB_SDTEST_IF_RX { 79776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IB_SDTEST_IF_RX_pb ); 79876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 79976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 80076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBCDDRCtrl2_offset 0x000001a0UL 80176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCDDRCtrl2_pb { 80276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_FRONT_PORCH[5]; 80376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t IB_BACK_PORCH[5]; 80476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[54]; 80576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 80676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCDDRCtrl2 { 80776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRCtrl2_pb ); 80876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 80976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 81076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBCDDRStatus_offset 0x000001a8UL 81176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCDDRStatus_pb { 81276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LinkRoundTripLatency[26]; 81376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ReqDDSLocalFromRmt[4]; 81476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RxEqLocalDevice[2]; 81576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t heartbeat_crosstalk[4]; 81676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t heartbeat_timed_out[1]; 81776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[27]; 81876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 81976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBCDDRStatus { 82076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRStatus_pb ); 82176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 82276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 82376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_JIntReload_offset 0x000001b0UL 82476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_JIntReload_pb { 82576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t J_reload[16]; 82676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t J_limit_reload[16]; 82776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 82876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 82976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_JIntReload { 83076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_JIntReload_pb ); 83176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 83276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 83376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBNCModeCtrl_offset 0x000001b8UL 83476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBNCModeCtrl_pb { 83576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TSMEnable_send_TS1[1]; 83676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TSMEnable_send_TS2[1]; 83776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1]; 83876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[5]; 83976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TSMCode_TS1[9]; 84076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TSMCode_TS2[9]; 84176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[38]; 84276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 84376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBNCModeCtrl { 84476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IBNCModeCtrl_pb ); 84576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 84676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 84776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendCtrl_offset 0x000001c0UL 84876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendCtrl_pb { 84976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Abort[1]; 85076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendIntBufAvail[1]; 85176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendBufAvailUpd[1]; 85276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SPioEnable[1]; 85376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SSpecialTriggerEn[1]; 85476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[4]; 85576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaIntEnable[1]; 85676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaSingleDescriptor[1]; 85776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaEnable[1]; 85876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SDmaHalt[1]; 85976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[3]; 86076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t DisarmPIOBuf[8]; 86176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t AvailUpdThld[5]; 86276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[2]; 86376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Disarm[1]; 86476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 86576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 86676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendCtrl { 86776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendCtrl_pb ); 86876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 86976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 87076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendBufBase_offset 0x000001c8UL 87176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufBase_pb { 87276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t BaseAddr_SmallPIO[21]; 87376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[11]; 87476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t BaseAddr_LargePIO[21]; 87576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[11]; 87676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 87776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufBase { 87876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufBase_pb ); 87976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 88076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 88176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendBufSize_offset 0x000001d0UL 88276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufSize_pb { 88376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Size_SmallPIO[12]; 88476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[20]; 88576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Size_LargePIO[13]; 88676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[19]; 88776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 88876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufSize { 88976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufSize_pb ); 89076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 89176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 89276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendBufCnt_offset 0x000001d8UL 89376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufCnt_pb { 89476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Num_SmallBuffers[9]; 89576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[23]; 89676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Num_LargeBuffers[4]; 89776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[28]; 89876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 89976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufCnt { 90076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufCnt_pb ); 90176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 90276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 90376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendBufAvailAddr_offset 0x000001e0UL 90476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufAvailAddr_pb { 90576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[6]; 90676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendBufAvailAddr[34]; 90776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[24]; 90876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 90976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufAvailAddr { 91076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvailAddr_pb ); 91176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 91276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 91376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxIntMemBase_offset 0x000001e8UL 91476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 91576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxIntMemSize_offset 0x000001f0UL 91676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 91776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaBase_offset 0x000001f8UL 91876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaBase_pb { 91976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDmaBase[48]; 92076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 92176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 92276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaBase { 92376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBase_pb ); 92476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 92576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 92676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaLenGen_offset 0x00000200UL 92776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaLenGen_pb { 92876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Length[16]; 92976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Generation[3]; 93076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[45]; 93176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 93276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaLenGen { 93376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaLenGen_pb ); 93476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 93576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 93676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaTail_offset 0x00000208UL 93776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaTail_pb { 93876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDmaTail[16]; 93976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[48]; 94076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 94176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaTail { 94276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaTail_pb ); 94376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 94476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 94576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaHead_offset 0x00000210UL 94676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaHead_pb { 94776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDmaHead[16]; 94876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[16]; 94976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t InternalSendDmaHead[16]; 95076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 95176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 95276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaHead { 95376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaHead_pb ); 95476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 95576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 95676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaHeadAddr_offset 0x00000218UL 95776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaHeadAddr_pb { 95876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendDmaHeadAddr[48]; 95976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 96076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 96176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaHeadAddr { 96276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaHeadAddr_pb ); 96376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 96476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 96576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaBufMask0_offset 0x00000220UL 96676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaBufMask0_pb { 96776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t BufMask_63_0[0]; 96876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[64]; 96976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 97076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaBufMask0 { 97176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBufMask0_pb ); 97276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 97376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 97476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaStatus_offset 0x00000238UL 97576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaStatus_pb { 97676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SplFifoDescIndex[16]; 97776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SplFifoBufNum[8]; 97876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SplFifoFull[1]; 97976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SplFifoEmpty[1]; 98076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SplFifoDisarmed[1]; 98176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SplFifoReadyToGo[1]; 98276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ScbFetchDescFlag[1]; 98376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ScbEntryValid[1]; 98476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ScbEmpty[1]; 98576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ScbFull[1]; 98676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RpyTag_7_0[8]; 98776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RpyLowAddr_6_0[7]; 98876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ScbDescIndex_13_0[14]; 98976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t InternalSDmaEnable[1]; 99076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t AbortInProg[1]; 99176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ScoreBoardDrainInProg[1]; 99276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 99376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaStatus { 99476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaStatus_pb ); 99576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 99676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 99776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendBufErr0_offset 0x00000240UL 99876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufErr0_pb { 99976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendBufErr_63_0[0]; 100076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[64]; 100176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 100276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufErr0 { 100376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufErr0_pb ); 100476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 100576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 100676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_REG_000258_offset 0x00000258UL 100776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 100876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_AvailUpdCount_offset 0x00000268UL 100976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_AvailUpdCount_pb { 101076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t AvailUpdCount[5]; 101176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[59]; 101276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 101376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_AvailUpdCount { 101476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_AvailUpdCount_pb ); 101576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 101676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 101776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrAddr0_offset 0x00000270UL 101876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrAddr0_pb { 101976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[2]; 102076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrAddr0[38]; 102176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[24]; 102276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 102376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrAddr0 { 102476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrAddr0_pb ); 102576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 102676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 102776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_REG_0002F8_offset 0x000002f8UL 102876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 102976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTailAddr0_offset 0x00000300UL 103076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrTailAddr0_pb { 103176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[2]; 103276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHdrTailAddr0[38]; 103376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[24]; 103476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 103576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrTailAddr0 { 103676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrTailAddr0_pb ); 103776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 103876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 103976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_REG_000388_offset 0x00000388UL 104076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 104176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_ibsd_epb_access_ctrl_offset 0x000003c0UL 104276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ibsd_epb_access_ctrl_pb { 104376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sw_ib_epb_req[1]; 104476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[7]; 104576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sw_ib_epb_req_granted[1]; 104676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[55]; 104776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 104876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ibsd_epb_access_ctrl { 104976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_ibsd_epb_access_ctrl_pb ); 105076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 105176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 105276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_ibsd_epb_transaction_reg_offset 0x000003c8UL 105376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ibsd_epb_transaction_reg_pb { 105476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ib_epb_data[8]; 105576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ib_epb_address[15]; 105676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[1]; 105776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ib_epb_read_write[1]; 105876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ib_epb_cs[2]; 105976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[1]; 106076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_data_parity[1]; 106176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[1]; 106276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ib_epb_req_error[1]; 106376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ib_epb_rdy[1]; 106476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 106576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 106676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_ibsd_epb_transaction_reg { 106776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_ibsd_epb_transaction_reg_pb ); 106876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 106976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 107076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_REG_0003D0_offset 0x000003d0UL 107176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 107276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_XGXSCfg_offset 0x000003d8UL 107376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_XGXSCfg_pb { 107476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tx_rx_reset[1]; 107576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[1]; 107676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t xcv_reset[1]; 107776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[6]; 107876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t link_sync_mask[10]; 107976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[44]; 108076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sel_link_down_for_fctrl_lane_sync_reset[1]; 108176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 108276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_XGXSCfg { 108376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_XGXSCfg_pb ); 108476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 108576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 108676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBSerDesCtrl_offset 0x000003e0UL 108776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBSerDesCtrl_pb { 108876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ResetIB_uC_Core[1]; 108976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved2[7]; 109076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NumSerDesRegsToWrForDDS[5]; 109176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t NumSerDesRegsToWrForRXEQ[5]; 109276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[14]; 109376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TXINV[1]; 109476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RXINV[1]; 109576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RXIDLE[1]; 109676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TWC[1]; 109776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t TXOBPD[1]; 109876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PLLM[3]; 109976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PLLN[2]; 110076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t CKSEL_uC[2]; 110176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t INT_uC[1]; 110276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[19]; 110376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 110476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_IBSerDesCtrl { 110576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_IBSerDesCtrl_pb ); 110676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 110776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 110876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_EEPCtlStat_offset 0x000003e8UL 110976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_EEPCtlStat_pb { 111076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t EPAccEn[2]; 111176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t EPReset[1]; 111276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ByteProg[1]; 111376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t PageMode[1]; 111476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t LstDatWr[1]; 111576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t CmdWrErr[1]; 111676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[24]; 111776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t CtlrStat[1]; 111876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 111976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 112076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_EEPCtlStat { 112176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_EEPCtlStat_pb ); 112276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 112376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 112476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_EEPAddrCmd_offset 0x000003f0UL 112576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_EEPAddrCmd_pb { 112676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t EPAddr[24]; 112776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t EPCmd[8]; 112876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 112976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 113076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_EEPAddrCmd { 113176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_EEPAddrCmd_pb ); 113276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 113376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 113476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_EEPData_offset 0x000003f8UL 113576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 113676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_pciesd_epb_access_ctrl_offset 0x00000400UL 113776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_pciesd_epb_access_ctrl_pb { 113876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sw_pcie_epb_req[1]; 113976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sw_pcieepb_star_en[2]; 114076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[5]; 114176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t sw_pcie_epb_req_granted[1]; 114276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[55]; 114376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 114476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_pciesd_epb_access_ctrl { 114576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_pciesd_epb_access_ctrl_pb ); 114676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 114776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 114876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_pciesd_epb_transaction_reg_offset 0x00000408UL 114976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_pciesd_epb_transaction_reg_pb { 115076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pcie_epb_data[8]; 115176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pcie_epb_address[15]; 115276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[1]; 115376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pcie_epb_read_write[1]; 115476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pcie_epb_cs[3]; 115576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t mem_data_parity[1]; 115676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[1]; 115776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pcie_epb_req_error[1]; 115876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t pcie_epb_rdy[1]; 115976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 116076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 116176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_pciesd_epb_transaction_reg { 116276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_pciesd_epb_transaction_reg_pb ); 116376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 116476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 116576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_efuse_control_reg_offset 0x00000410UL 116676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_efuse_control_reg_pb { 116776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_op[1]; 116876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t operation[1]; 116976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t read_valid[1]; 117076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t req_error[1]; 117176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[27]; 117276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rdy[1]; 117376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 117476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 117576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_efuse_control_reg { 117676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_efuse_control_reg_pb ); 117776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 117876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 117976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_efuse_rddata0_reg_offset 0x00000418UL 118076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 118176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_procmon_register_offset 0x00000438UL 118276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_procmon_register_pb { 118376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t interval_time[12]; 118476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved1[2]; 118576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t clear_counter[1]; 118676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t start_counter[1]; 118776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t procmon_count[9]; 118876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[6]; 118976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t procmon_count_valid[1]; 119076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 119176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 119276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_procmon_register { 119376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_procmon_register_pb ); 119476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 119576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 119676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PcieRbufTestReg0_offset 0x00000440UL 119776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 119876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PcieRBufTestReg1_offset 0x00000448UL 119976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 120076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SPC_JTAG_ACCESS_REG_offset 0x00000460UL 120176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SPC_JTAG_ACCESS_REG_pb { 120276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t rdy[1]; 120376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tdo[1]; 120476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t tdi[1]; 120576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t opcode[2]; 120676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t bist_en[5]; 120776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SPC_JTAG_ACCESS_EN[1]; 120876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[53]; 120976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 121076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SPC_JTAG_ACCESS_REG { 121176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SPC_JTAG_ACCESS_REG_pb ); 121276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 121376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 121476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_LAControlReg_offset 0x00000468UL 121576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_LAControlReg_pb { 121676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Finished[1]; 121776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Address[8]; 121876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Mode[2]; 121976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Delay[20]; 122076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[1]; 122176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 122276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 122376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_LAControlReg { 122476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_LAControlReg_pb ); 122576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 122676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 122776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_GPIODebugSelReg_offset 0x00000470UL 122876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_GPIODebugSelReg_pb { 122976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t GPIOSourceSelDebug[16]; 123076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SelPulse[16]; 123176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[32]; 123276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 123376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_GPIODebugSelReg { 123476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_GPIODebugSelReg_pb ); 123576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 123676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 123776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_DebugPortValueReg_offset 0x00000478UL 123876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 123976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaBufUsed0_offset 0x00000480UL 124076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaBufUsed0_pb { 124176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t BufUsed_63_0[0]; 124276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[64]; 124376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 124476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaBufUsed0 { 124576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBufUsed0_pb ); 124676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 124776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 124876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendDmaReqTagUsed_offset 0x00000498UL 124976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaReqTagUsed_pb { 125076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t ReqTagUsed_7_0[8]; 125176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[8]; 125276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[48]; 125376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 125476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendDmaReqTagUsed { 125576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaReqTagUsed_pb ); 125676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 125776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 125876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_efuse_pgm_data0_offset 0x000004a0UL 125976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 126076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_0004B0_offset 0x000004b0UL 126176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 126276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SerDes_DDSRXEQ0_offset 0x00000500UL 126376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SerDes_DDSRXEQ0_pb { 126476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t element_num[4]; 126576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t reg_addr[6]; 126676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[54]; 126776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 126876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SerDes_DDSRXEQ0 { 126976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SerDes_DDSRXEQ0_pb ); 127076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 127176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 127276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_0005F0_offset 0x000005f0UL 127376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 127476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_LAMemory_offset 0x00000600UL 127576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 127676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_0007F0_offset 0x000007f0UL 127776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 127876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendBufAvail0_offset 0x00001000UL 127976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufAvail0_pb { 128076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t SendBuf_31_0[0]; 128176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t _unused_0[64]; 128276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 128376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_SendBufAvail0 { 128476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvail0_pb ); 128576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 128676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 128776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_001028_offset 0x00001028UL 128876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 128976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_LBIntCnt_offset 0x00013000UL 129076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_LBFlowStallCnt_offset 0x00013008UL 129276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxSDmaDescCnt_offset 0x00013010UL 129476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxUnsupVLErrCnt_offset 0x00013018UL 129676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxDataPktCnt_offset 0x00013020UL 129876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 129976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxFlowPktCnt_offset 0x00013028UL 130076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 130176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxDwordCnt_offset 0x00013030UL 130276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 130376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxLenErrCnt_offset 0x00013038UL 130476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 130576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxMaxMinLenErrCnt_offset 0x00013040UL 130676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 130776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxUnderrunCnt_offset 0x00013048UL 130876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 130976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxFlowStallCnt_offset 0x00013050UL 131076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 131176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_TxDroppedPktCnt_offset 0x00013058UL 131276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 131376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxDroppedPktCnt_offset 0x00013060UL 131476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 131576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxDataPktCnt_offset 0x00013068UL 131676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 131776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxFlowPktCnt_offset 0x00013070UL 131876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 131976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxDwordCnt_offset 0x00013078UL 132076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 132176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxLenErrCnt_offset 0x00013080UL 132276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 132376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxMaxMinLenErrCnt_offset 0x00013088UL 132476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 132576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxICRCErrCnt_offset 0x00013090UL 132676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 132776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxVCRCErrCnt_offset 0x00013098UL 132876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 132976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxFlowCtrlViolCnt_offset 0x000130a0UL 133076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 133176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxVersionErrCnt_offset 0x000130a8UL 133276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 133376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxLinkMalformCnt_offset 0x000130b0UL 133476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 133576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxEBPCnt_offset 0x000130b8UL 133676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 133776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxLPCRCErrCnt_offset 0x000130c0UL 133876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 133976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxBufOvflCnt_offset 0x000130c8UL 134076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 134176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxTIDFullErrCnt_offset 0x000130d0UL 134276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 134376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxTIDValidErrCnt_offset 0x000130d8UL 134476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 134576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxPKeyMismatchCnt_offset 0x000130e0UL 134676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 134776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxP0HdrEgrOvflCnt_offset 0x000130e8UL 134876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 134976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBStatusChangeCnt_offset 0x00013170UL 135076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 135176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBLinkErrRecoveryCnt_offset 0x00013178UL 135276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 135376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBLinkDownedCnt_offset 0x00013180UL 135476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 135576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBSymbolErrCnt_offset 0x00013188UL 135676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 135776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxVL15DroppedPktCnt_offset 0x00013190UL 135876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 135976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxOtherLocalPhyErrCnt_offset 0x00013198UL 136076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 136176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PcieRetryBufDiagQwordCnt_offset 0x000131a0UL 136276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 136376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_ExcessBufferOvflCnt_offset 0x000131a8UL 136476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 136576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_LocalLinkIntegrityErrCnt_offset 0x000131b0UL 136676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 136776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxVlErrCnt_offset 0x000131b8UL 136876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 136976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RxDlidFltrCnt_offset 0x000131c0UL 137076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 137176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_CNT_0131C8_offset 0x000131c8UL 137276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 137376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PSStat_offset 0x00013200UL 137476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 137576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PSStart_offset 0x00013208UL 137676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 137776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PSInterval_offset 0x00013210UL 137876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 137976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PSRcvDataCount_offset 0x00013218UL 138076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PSRcvPktsCount_offset 0x00013220UL 138276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PSXmitDataCount_offset 0x00013228UL 138476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PSXmitPktsCount_offset 0x00013230UL 138676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PSXmitWaitCount_offset 0x00013238UL 138876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 138976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_CNT_013240_offset 0x00013240UL 139076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 139176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrArray_offset 0x00014000UL 139276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 139376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_038000_offset 0x00038000UL 139476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 139576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvTIDArray0_offset 0x00053000UL 139676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 139776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PIOLaunchFIFO_offset 0x00064000UL 139876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 139976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_064480_offset 0x00064480UL 140076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 140176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendPIOpbcCache_offset 0x00064800UL 140276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 140376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_064C80_offset 0x00064c80UL 140476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 140576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PreLaunchFIFO_offset 0x00065000UL 140676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 140776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_065080_offset 0x00065080UL 140876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 140976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_ScoreBoard_offset 0x00065400UL 141076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 141176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_065440_offset 0x00065440UL 141276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 141376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_DescriptorFIFO_offset 0x00065800UL 141476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 141576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_065880_offset 0x00065880UL 141676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 141776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvBuf1_offset 0x00072000UL 141876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 141976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_074800_offset 0x00074800UL 142076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 142176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvBuf2_offset 0x00075000UL 142276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 142376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_076400_offset 0x00076400UL 142476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 142576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvFlags_offset 0x00077000UL 142676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 142776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_078400_offset 0x00078400UL 142876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 142976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvLookupBuf1_offset 0x00079000UL 143076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_07A400_offset 0x0007a400UL 143276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvDMADatBuf_offset 0x0007b000UL 143476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvDMAHdrBuf_offset 0x0007b800UL 143676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MiscRXEIntMem_offset 0x0007c000UL 143876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 143976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_07D400_offset 0x0007d400UL 144076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 144176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PCIERcvBuf_offset 0x00080000UL 144276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 144376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PCIERetryBuf_offset 0x00084000UL 144476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 144576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PCIERcvBufRdToWrAddr_offset 0x00088000UL 144676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 144776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_PCIECplBuf_offset 0x00090000UL 144876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 144976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_IBSerDesMappTable_offset 0x00094000UL 145076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_095000_offset 0x00095000UL 145276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_SendBuf0_MA_offset 0x00100000UL 145476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_1A0000_offset 0x001a0000UL 145676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail0_offset 0x00200000UL 145876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 145976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead0_offset 0x00200008UL 146076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead0_pb { 146176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 146276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 146376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 146476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 146576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead0 { 146676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead0_pb ); 146776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 146876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 146976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail0_offset 0x00200010UL 147076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead0_offset 0x00200018UL 147276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_200020_offset 0x00200020UL 147476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail1_offset 0x00210000UL 147676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 147776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead1_offset 0x00210008UL 147876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead1_pb { 147976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 148076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 148176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 148276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 148376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead1 { 148476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead1_pb ); 148576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 148676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 148776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail1_offset 0x00210010UL 148876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 148976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead1_offset 0x00210018UL 149076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 149176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_210020_offset 0x00210020UL 149276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 149376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail2_offset 0x00220000UL 149476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 149576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead2_offset 0x00220008UL 149676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead2_pb { 149776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 149876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 149976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 150076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 150176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead2 { 150276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead2_pb ); 150376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 150476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 150576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail2_offset 0x00220010UL 150676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 150776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead2_offset 0x00220018UL 150876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 150976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_220020_offset 0x00220020UL 151076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 151176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail3_offset 0x00230000UL 151276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 151376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead3_offset 0x00230008UL 151476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead3_pb { 151576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 151676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 151776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 151876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 151976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead3 { 152076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead3_pb ); 152176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 152276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 152376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail3_offset 0x00230010UL 152476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 152576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead3_offset 0x00230018UL 152676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 152776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_230020_offset 0x00230020UL 152876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 152976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail4_offset 0x00240000UL 153076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 153176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead4_offset 0x00240008UL 153276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead4_pb { 153376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 153476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 153576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 153676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 153776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead4 { 153876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead4_pb ); 153976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 154076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 154176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail4_offset 0x00240010UL 154276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 154376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead4_offset 0x00240018UL 154476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 154576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_240020_offset 0x00240020UL 154676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 154776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail5_offset 0x00250000UL 154876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 154976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead5_offset 0x00250008UL 155076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead5_pb { 155176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 155276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 155376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 155476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 155576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead5 { 155676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead5_pb ); 155776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 155876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 155976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail5_offset 0x00250010UL 156076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 156176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead5_offset 0x00250018UL 156276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 156376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_250020_offset 0x00250020UL 156476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 156576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail6_offset 0x00260000UL 156676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 156776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead6_offset 0x00260008UL 156876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead6_pb { 156976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 157076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 157176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 157276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 157376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead6 { 157476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead6_pb ); 157576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 157676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 157776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail6_offset 0x00260010UL 157876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 157976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead6_offset 0x00260018UL 158076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 158176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_260020_offset 0x00260020UL 158276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 158376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail7_offset 0x00270000UL 158476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 158576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead7_offset 0x00270008UL 158676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead7_pb { 158776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 158876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 158976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 159076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 159176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead7 { 159276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead7_pb ); 159376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 159476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 159576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail7_offset 0x00270010UL 159676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 159776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead7_offset 0x00270018UL 159876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 159976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_270020_offset 0x00270020UL 160076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 160176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail8_offset 0x00280000UL 160276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 160376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead8_offset 0x00280008UL 160476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead8_pb { 160576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 160676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 160776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 160876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 160976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead8 { 161076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead8_pb ); 161176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 161276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 161376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail8_offset 0x00280010UL 161476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 161576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead8_offset 0x00280018UL 161676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 161776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_280020_offset 0x00280020UL 161876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 161976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail9_offset 0x00290000UL 162076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 162176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead9_offset 0x00290008UL 162276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead9_pb { 162376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 162476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 162576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 162676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 162776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead9 { 162876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead9_pb ); 162976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 163076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 163176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail9_offset 0x00290010UL 163276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 163376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead9_offset 0x00290018UL 163476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 163576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_290020_offset 0x00290020UL 163676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 163776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail10_offset 0x002a0000UL 163876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 163976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead10_offset 0x002a0008UL 164076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead10_pb { 164176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 164276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 164376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 164476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 164576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead10 { 164676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead10_pb ); 164776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 164876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 164976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail10_offset 0x002a0010UL 165076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 165176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead10_offset 0x002a0018UL 165276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 165376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_2A0020_offset 0x002a0020UL 165476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 165576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail11_offset 0x002b0000UL 165676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 165776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead11_offset 0x002b0008UL 165876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead11_pb { 165976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 166076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 166176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 166276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 166376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead11 { 166476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead11_pb ); 166576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 166676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 166776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail11_offset 0x002b0010UL 166876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 166976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead11_offset 0x002b0018UL 167076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 167176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_2B0020_offset 0x002b0020UL 167276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 167376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail12_offset 0x002c0000UL 167476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 167576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead12_offset 0x002c0008UL 167676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead12_pb { 167776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 167876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 167976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 168076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 168176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead12 { 168276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead12_pb ); 168376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 168476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 168576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail12_offset 0x002c0010UL 168676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 168776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead12_offset 0x002c0018UL 168876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 168976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_2C0020_offset 0x002c0020UL 169076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 169176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail13_offset 0x002d0000UL 169276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 169376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead13_offset 0x002d0008UL 169476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead13_pb { 169576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 169676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 169776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 169876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 169976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead13 { 170076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead13_pb ); 170176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 170276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 170376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail13_offset 0x002d0010UL 170476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 170576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead13_offset 0x002d0018UL 170676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 170776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_2D0020_offset 0x002d0020UL 170876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 170976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail14_offset 0x002e0000UL 171076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 171176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead14_offset 0x002e0008UL 171276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead14_pb { 171376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 171476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 171576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 171676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 171776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead14 { 171876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead14_pb ); 171976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 172076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 172176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail14_offset 0x002e0010UL 172276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 172376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead14_offset 0x002e0018UL 172476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 172576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_2E0020_offset 0x002e0020UL 172676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 172776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail15_offset 0x002f0000UL 172876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 172976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead15_offset 0x002f0008UL 173076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead15_pb { 173176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 173276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 173376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 173476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 173576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead15 { 173676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead15_pb ); 173776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 173876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 173976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail15_offset 0x002f0010UL 174076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 174176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead15_offset 0x002f0018UL 174276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 174376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_2F0020_offset 0x002f0020UL 174476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 174576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrTail16_offset 0x00300000UL 174676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 174776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvHdrHead16_offset 0x00300008UL 174876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead16_pb { 174976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t RcvHeadPointer[32]; 175076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t counter[16]; 175176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman pseudo_bit_t Reserved[16]; 175276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 175376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct QIB_7220_RcvHdrHead16 { 175476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead16_pb ); 175576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 175676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 175776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexTail16_offset 0x00300010UL 175876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 175976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_RcvEgrIndexHead16_offset 0x00300018UL 176076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 176176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define QIB_7220_MEM_300020_offset 0x00300020UL 176276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1763