1362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 2362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/*---------------------------------------------------------------*/ 3362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/*--- begin host_mips_defs.h ---*/ 4362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/*---------------------------------------------------------------*/ 5362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 6362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* 7362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj This file is part of Valgrind, a dynamic binary instrumentation 8362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj framework. 9362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 10ed39800a83baf5bffbe391f3974eb2af0f415f80Elliott Hughes Copyright (C) 2010-2017 RT-RK 11362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj mips-valgrind@rt-rk.com 12362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 13362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj This program is free software; you can redistribute it and/or 14362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj modify it under the terms of the GNU General Public License as 15362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj published by the Free Software Foundation; either version 2 of the 16362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj License, or (at your option) any later version. 17362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 18362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj This program is distributed in the hope that it will be useful, but 19362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj WITHOUT ANY WARRANTY; without even the implied warranty of 20362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj General Public License for more details. 22362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 23362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj You should have received a copy of the GNU General Public License 24362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj along with this program; if not, write to the Free Software 25362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 26362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 02111-1307, USA. 27362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 28362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj The GNU General Public License is contained in the file COPYING. 29362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj*/ 30362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 31362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj#ifndef __VEX_HOST_MIPS_DEFS_H 32362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj#define __VEX_HOST_MIPS_DEFS_H 33362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 3458a637b6675d4d68e13d18b75cea7eee2a2a91feflorian#include "libvex_basictypes.h" 35b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj#include "libvex.h" /* VexArch */ 36b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj#include "host_generic_regs.h" /* HReg */ 3758a637b6675d4d68e13d18b75cea7eee2a2a91feflorian 38362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 39a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj/* --------- Registers. --------- */ 40362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 41a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#define ST_IN static inline 42a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 43a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#define GPR(_mode64, _enc, _ix64, _ix32) \ 44a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj mkHReg(False, (_mode64) ? HRcInt64 : HRcInt32, \ 45a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj (_enc), (_mode64) ? (_ix64) : (_ix32)) 46a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 47a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#define FR(_mode64, _enc, _ix64, _ix32) \ 48a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj mkHReg(False, (_mode64) ? HRcFlt64 : HRcFlt32, \ 49a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj (_enc), (_mode64) ? (_ix64) : (_ix32)) 50a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 51a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#define DR(_mode64, _enc, _ix64, _ix32) \ 52a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj mkHReg(False, HRcFlt64, \ 53a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj (_enc), (_mode64) ? (_ix64) : (_ix32)) 54a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 55a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR16 ( Bool mode64 ) { return GPR(mode64, 16, 0, 0); } 56a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR17 ( Bool mode64 ) { return GPR(mode64, 17, 1, 1); } 57a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR18 ( Bool mode64 ) { return GPR(mode64, 18, 2, 2); } 58a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR19 ( Bool mode64 ) { return GPR(mode64, 19, 3, 3); } 59a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR20 ( Bool mode64 ) { return GPR(mode64, 20, 4, 4); } 60a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR21 ( Bool mode64 ) { return GPR(mode64, 21, 5, 5); } 61a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR22 ( Bool mode64 ) { return GPR(mode64, 22, 6, 6); } 62a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 63a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR12 ( Bool mode64 ) { return GPR(mode64, 12, 7, 7); } 64a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR13 ( Bool mode64 ) { return GPR(mode64, 13, 8, 8); } 65a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR14 ( Bool mode64 ) { return GPR(mode64, 14, 9, 9); } 66a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR15 ( Bool mode64 ) { return GPR(mode64, 15, 10, 10); } 67a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR24 ( Bool mode64 ) { return GPR(mode64, 24, 11, 11); } 68a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 69a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_F16 ( Bool mode64 ) { return FR (mode64, 16, 12, 12); } 70a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_F18 ( Bool mode64 ) { return FR (mode64, 18, 13, 13); } 71a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_F20 ( Bool mode64 ) { return FR (mode64, 20, 14, 14); } 72a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_F22 ( Bool mode64 ) { return FR (mode64, 22, 15, 15); } 73a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_F24 ( Bool mode64 ) { return FR (mode64, 24, 16, 16); } 74a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_F26 ( Bool mode64 ) { return FR (mode64, 26, 17, 17); } 75a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_F28 ( Bool mode64 ) { return FR (mode64, 28, 18, 18); } 76a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_F30 ( Bool mode64 ) { return FR (mode64, 30, 19, 19); } 77a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 78a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj// DRs are only allocatable in 32-bit mode, so the 64-bit index numbering 79a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj// doesn't advance here. 80a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_D0 ( Bool mode64 ) { vassert(!mode64); 81a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj return DR (mode64, 0, 0, 20); } 82a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_D1 ( Bool mode64 ) { vassert(!mode64); 83a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj return DR (mode64, 2, 0, 21); } 84a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_D2 ( Bool mode64 ) { vassert(!mode64); 85a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj return DR (mode64, 4, 0, 22); } 86a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_D3 ( Bool mode64 ) { vassert(!mode64); 87a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj return DR (mode64, 6, 0, 23); } 88a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_D4 ( Bool mode64 ) { vassert(!mode64); 89a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj return DR (mode64, 8, 0, 24); } 90a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_D5 ( Bool mode64 ) { vassert(!mode64); 91a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj return DR (mode64, 10, 0, 25); } 92a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_D6 ( Bool mode64 ) { vassert(!mode64); 93a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj return DR (mode64, 12, 0, 26); } 94a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_D7 ( Bool mode64 ) { vassert(!mode64); 95a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj return DR (mode64, 14, 0, 27); } 96a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 97a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_HI ( Bool mode64 ) { return FR (mode64, 33, 20, 28); } 98a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_LO ( Bool mode64 ) { return FR (mode64, 34, 21, 29); } 99a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 100a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR0 ( Bool mode64 ) { return GPR(mode64, 0, 22, 30); } 101a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR1 ( Bool mode64 ) { return GPR(mode64, 1, 23, 31); } 102a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR2 ( Bool mode64 ) { return GPR(mode64, 2, 24, 32); } 103a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR3 ( Bool mode64 ) { return GPR(mode64, 3, 25, 33); } 104a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR4 ( Bool mode64 ) { return GPR(mode64, 4, 26, 34); } 105a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR5 ( Bool mode64 ) { return GPR(mode64, 5, 27, 35); } 106a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR6 ( Bool mode64 ) { return GPR(mode64, 6, 28, 36); } 107a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR7 ( Bool mode64 ) { return GPR(mode64, 7, 29, 37); } 108a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR8 ( Bool mode64 ) { return GPR(mode64, 8, 30, 38); } 109a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR9 ( Bool mode64 ) { return GPR(mode64, 9, 31, 39); } 110a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR10 ( Bool mode64 ) { return GPR(mode64, 10, 32, 40); } 111a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR11 ( Bool mode64 ) { return GPR(mode64, 11, 33, 41); } 112a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR23 ( Bool mode64 ) { return GPR(mode64, 23, 34, 42); } 113a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR25 ( Bool mode64 ) { return GPR(mode64, 25, 35, 43); } 114a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR29 ( Bool mode64 ) { return GPR(mode64, 29, 36, 44); } 115a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregMIPS_GPR31 ( Bool mode64 ) { return GPR(mode64, 31, 37, 45); } 116a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 117a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#undef ST_IN 118a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#undef GPR 119a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#undef FR 120a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#undef DR 121362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 122b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj#define GuestStatePointer(_mode64) hregMIPS_GPR23(_mode64) 123362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj#define StackFramePointer(_mode64) hregMIPS_GPR30(_mode64) 124362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj#define StackPointer(_mode64) hregMIPS_GPR29(_mode64) 125a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 126ed39800a83baf5bffbe391f3974eb2af0f415f80Elliott Hughes/* guest_COND offset */ 127ed39800a83baf5bffbe391f3974eb2af0f415f80Elliott Hughes#define COND_OFFSET(_mode64) ((_mode64) ? 588 : 448) 128ed39800a83baf5bffbe391f3974eb2af0f415f80Elliott Hughes 129a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj/* Num registers used for function calls */ 130a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#if defined(VGP_mips32_linux) 131a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj /* a0, a1, a2, a3 */ 132a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj# define MIPS_N_REGPARMS 4 133a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#else 134a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj /* a0, a1, a2, a3, a4, a5, a6, a7 */ 135a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj# define MIPS_N_REGPARMS 8 136b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj#endif 137362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 138a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjextern void ppHRegMIPS ( HReg, Bool ); 139a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 140a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 141362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- Condition codes, Intel encoding. --------- */ 142362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 143b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_EQ = 0, /* equal */ 144b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_NE = 1, /* not equal */ 145362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 146b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_HS = 2, /* >=u (higher or same) */ 147b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_LO = 3, /* <u (lower) */ 148362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 149b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_MI = 4, /* minus (negative) */ 150b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_PL = 5, /* plus (zero or +ve) */ 151362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 152b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_VS = 6, /* overflow */ 153b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_VC = 7, /* no overflow */ 154362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 155b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_HI = 8, /* >u (higher) */ 156b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_LS = 9, /* <=u (lower or same) */ 157362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 158b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_GE = 10, /* >=s (signed greater or equal) */ 159b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_LT = 11, /* <s (signed less than) */ 160362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 161b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_GT = 12, /* >s (signed greater) */ 162b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_LE = 13, /* <=s (signed less or equal) */ 163362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 164b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_AL = 14, /* always (unconditional) */ 165b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPScc_NV = 15 /* never (unconditional): */ 166362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSCondCode; 167362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 16855085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar *showMIPSCondCode(MIPSCondCode); 169362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 170362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- Memory address expressions (amodes). --------- */ 171362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 172362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mam_IR, /* Immediate (signed 16-bit) + Reg */ 173362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mam_RR /* Reg1 + Reg2 */ 174362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSAModeTag; 175362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 176362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef struct { 177362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAModeTag tag; 178362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj union { 179362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 180362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg base; 181362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Int index; 182362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } IR; 183362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 184362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg base; 185362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg index; 186362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } RR; 187362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Mam; 188362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSAMode; 189362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 190362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSAMode *MIPSAMode_IR(Int, HReg); 191362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSAMode *MIPSAMode_RR(HReg, HReg); 192362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 193362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSAMode *dopyMIPSAMode(MIPSAMode *); 194362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSAMode *nextMIPSAModeFloat(MIPSAMode *); 195362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSAMode *nextMIPSAModeInt(MIPSAMode *); 196362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 197362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern void ppMIPSAMode(MIPSAMode *, Bool); 198362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 199362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- Operand, which can be a reg or a u16/s16. --------- */ 200362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* ("RH" == "Register or Halfword immediate") */ 201362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 202362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mrh_Imm, 203362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mrh_Reg 204362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSRHTag; 205362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 206362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef struct { 207362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSRHTag tag; 208362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj union { 209362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 210362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool syned; 211362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj UShort imm16; 212362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Imm; 213362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 214362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg reg; 215362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Reg; 216362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Mrh; 217362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSRH; 218362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 219362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern void ppMIPSRH(MIPSRH *, Bool); 220362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 221362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSRH *MIPSRH_Imm(Bool, UShort); 222362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSRH *MIPSRH_Reg(HReg); 223362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 224362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- Instructions. --------- */ 225362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 226362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/*Tags for operations*/ 227362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 228362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- */ 229362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 230362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mun_CLO, 231362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mun_CLZ, 232b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Mun_DCLO, 233b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Mun_DCLZ, 234362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mun_NOP, 235362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSUnaryOp; 236362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 23755085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar *showMIPSUnaryOp(MIPSUnaryOp); 238362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- */ 239362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 240362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- */ 241362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 242362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 243362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Malu_INVALID, 244362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Malu_ADD, Malu_SUB, 245362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Malu_AND, Malu_OR, Malu_NOR, Malu_XOR, 246b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Malu_DADD, Malu_DSUB, 247b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Malu_SLT 248362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSAluOp; 249362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 25055085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar *showMIPSAluOp(MIPSAluOp, 251362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool /* is the 2nd operand an immediate? */ ); 252362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 253362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- */ 254362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 255362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mshft_INVALID, 256362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mshft_SLL, Mshft_SRL, 257362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mshft_SRA 258362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSShftOp; 259362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 26055085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar *showMIPSShftOp(MIPSShftOp, 261362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool /* is the 2nd operand an immediate? */ , 262362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool /* is this a 32bit or 64bit op? */ ); 263362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 264362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- */ 265362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 266362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Macc_ADD, 267362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Macc_SUB 268362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSMaccOp; 269362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 27055085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar *showMIPSMaccOp(MIPSMaccOp, Bool); 271362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- */ 272362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 273362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* ----- Instruction tags ----- */ 274362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 275b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_LI, /* load word (32/64-bit) immediate (fake insn) */ 276b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Alu, /* word add/sub/and/or/xor/nor/others? */ 277b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Shft, /* word sll/srl/sra */ 278b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Unary, /* clo, clz, nop, neg */ 279362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 280b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Cmp, /* word compare (fake insn) */ 281362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 282b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Mul, /* widening/non-widening multiply */ 283b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Div, /* div */ 284362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 285b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Call, /* call to address in register */ 286362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 287362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* The following 5 insns are mandated by translation chaining */ 288b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_XDirect, /* direct transfer to GA */ 289b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_XIndir, /* indirect transfer to GA */ 290b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_XAssisted, /* assisted transfer to GA */ 291b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_EvCheck, /* Event check */ 292b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_ProfInc, /* 64-bit profile counter increment */ 293b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 294b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_RdWrLR, /* Read/Write Link Register */ 295b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Mthi, /* Move to HI from GP register */ 296b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Mtlo, /* Move to LO from GP register */ 297b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Mfhi, /* Move from HI to GP register */ 298b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Mflo, /* Move from LO to GP register */ 299b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Macc, /* Multiply and accumulate */ 300b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 301b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Load, /* zero-extending load a 8|16|32 bit value from mem */ 302b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_Store, /* store a 8|16|32 bit value to mem */ 3036ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj Min_Cas, /* compare and swap */ 304b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_LoadL, /* mips Load Linked Word - LL */ 305b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_StoreC, /* mips Store Conditional Word - SC */ 306b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 307b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpUnary, /* FP unary op */ 308b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpBinary, /* FP binary op */ 309b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpTernary, /* FP ternary op */ 310b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpConvert, /* FP conversion op */ 311b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpMulAcc, /* FP multipy-accumulate style op */ 312b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpLdSt, /* FP load/store */ 313b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpSTFIW, /* stfiwx */ 314b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpRSP, /* FP round IEEE754 double to IEEE754 single */ 315b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpCftI, /* fcfid/fctid/fctiw */ 316b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpCMov, /* FP floating point conditional move */ 317b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_MtFCSR, /* set FCSR register */ 318b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_MfFCSR, /* get FCSR register */ 319b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpCompare, /* FP compare, generating value into int reg */ 320b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 321b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_FpGpMove, /* Move from/to fpr to/from gpr */ 322b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Min_MoveCond /* Move Conditional */ 323362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSInstrTag; 324362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 325362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* --------- */ 326362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef enum { 327362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mfp_INVALID, 328362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 329362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Ternary */ 330362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mfp_MADDD, Mfp_MSUBD, 331362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mfp_MADDS, Mfp_MSUBS, 332362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 333362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Binary */ 334362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mfp_ADDD, Mfp_SUBD, Mfp_MULD, Mfp_DIVD, 335b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Mfp_ADDS, Mfp_SUBS, Mfp_MULS, Mfp_DIVS, 336362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 337362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Unary */ 338c3fee0debd7287a8c6a3b89ee6bc1ec58241938bdejanj Mfp_SQRTS, Mfp_SQRTD, 339362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Mfp_ABSS, Mfp_ABSD, Mfp_NEGS, Mfp_NEGD, Mfp_MOVS, Mfp_MOVD, 340b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 341b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj /* FP convert */ 342b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Mfp_CVTSD, Mfp_CVTSW, Mfp_CVTWD, 343b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Mfp_CVTWS, Mfp_CVTDL, Mfp_CVTSL, Mfp_CVTLS, Mfp_CVTLD, Mfp_TRULS, Mfp_TRULD, 344b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Mfp_TRUWS, Mfp_TRUWD, Mfp_FLOORWS, Mfp_FLOORWD, Mfp_ROUNDWS, Mfp_ROUNDWD, 345f37c086134874a2ba372f6750a45466473a813b1dejanj Mfp_CVTDW, Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD, Mfp_CVTDS, 346f37c086134874a2ba372f6750a45466473a813b1dejanj Mfp_ROUNDLD, Mfp_FLOORLD, 347f37c086134874a2ba372f6750a45466473a813b1dejanj 348f37c086134874a2ba372f6750a45466473a813b1dejanj /* FP compare */ 349f37c086134874a2ba372f6750a45466473a813b1dejanj Mfp_CMP_UN, Mfp_CMP_EQ, Mfp_CMP_LT, Mfp_CMP_NGT 350b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 351362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSFpOp; 352362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 35355085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar *showMIPSFpOp(MIPSFpOp); 354362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 355b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj/* Move from/to fpr to/from gpr */ 356b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjtypedef enum { 357b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MFpGpMove_mfc1, /* Move Word From Floating Point - MIPS32 */ 358b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MFpGpMove_dmfc1, /* Doubleword Move from Floating Point - MIPS64 */ 359b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MFpGpMove_mtc1, /* Move Word to Floating Point - MIPS32 */ 360b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MFpGpMove_dmtc1 /* Doubleword Move to Floating Point - MIPS64 */ 361b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj} MIPSFpGpMoveOp; 362b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 363b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjextern const HChar *showMIPSFpGpMoveOp ( MIPSFpGpMoveOp ); 364b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 365b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj/* Move Conditional */ 366b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjtypedef enum { 367b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MFpMoveCond_movns, /* FP Move Conditional on Not Zero - MIPS32 */ 368b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MFpMoveCond_movnd, 369b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MMoveCond_movn /* Move Conditional on Not Zero */ 370b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj} MIPSMoveCondOp; 371b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 372b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjextern const HChar *showMIPSMoveCondOp ( MIPSMoveCondOp ); 373b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 374362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/*--------- Structure for instructions ----------*/ 375362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* Destinations are on the LEFT (first operand) */ 376362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 377362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjtypedef struct { 378362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSInstrTag tag; 379362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj union { 380362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Get a 32/64-bit literal into a register. 381362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj May turn into a number of real insns. */ 382362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 383362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 384362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj ULong imm; 385362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } LI; 386362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Integer add/sub/and/or/xor. Limitations: 387362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj - For add, the immediate, if it exists, is a signed 16. 388362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj - For sub, the immediate, if it exists, is a signed 16 389362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj which may not be -32768, since no such instruction 390362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj exists, and so we have to emit addi with +32768, but 391362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj that is not possible. 392362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj - For and/or/xor, the immediate, if it exists, 393362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj is an unsigned 16. 394362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj */ 395362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 396362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAluOp op; 397362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 398362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcL; 399362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSRH *srcR; 400362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Alu; 401362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Integer shl/shr/sar. 402362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Limitations: the immediate, if it exists, 403362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj is a signed 5-bit value between 1 and 31 inclusive. 404362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj */ 405362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 406362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSShftOp op; 407362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool sz32; /* mode64 has both 32 and 64bit shft */ 408362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 409362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcL; 410362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSRH *srcR; 411362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Shft; 412362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Clz, Clo, nop */ 413362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 414362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSUnaryOp op; 415362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 416362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg src; 417362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Unary; 418362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Word compare. Fake instruction, used for basic block ending */ 419362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 420362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool syned; 421362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool sz32; 422362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 423362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcL; 424362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcR; 425362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 426362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSCondCode cond; 427362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Cmp; 428362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 429b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Bool widening; /* True => widening, False => non-widening */ 430b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Bool syned; /* signed/unsigned - meaningless if widenind = False */ 431362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool sz32; 432362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 433362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcL; 434362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcR; 435362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Mul; 436362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 437b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Bool syned; /* signed/unsigned - meaningless if widenind = False */ 438362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool sz32; 439362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcL; 440362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcR; 441362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Div; 442362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Pseudo-insn. Call target (an absolute address), on given 443362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj condition (which could be Mcc_ALWAYS). argiregs indicates 444b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj which of $4 .. $7 (mips32) or $4 .. $11 (mips64) 445362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj carries argument values for this call, 446b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj using a bit mask (1<<N is set if $N holds an arg, for N in 447b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj $4 .. $7 or $4 .. $11 inclusive). 448362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj If cond is != Mcc_ALWAYS, src is checked. 449362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Otherwise, unconditional call */ 450362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 451362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSCondCode cond; 452b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Addr64 target; 453362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj UInt argiregs; 454362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg src; 455cfe046e178666280b87da998b1b52ecda03ecd89sewardj RetLoc rloc; /* where the return value will be */ 456362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Call; 457362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Update the guest EIP value, then exit requesting to chain 458362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj to it. May be conditional. Urr, use of Addr32 implicitly 459362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj assumes that wordsize(guest) == wordsize(host). */ 460362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 461b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Addr64 dstGA; /* next guest address */ 462b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPSAMode* amPC; /* amode in guest state for PC */ 463b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPSCondCode cond; /* can be MIPScc_AL */ 464b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj Bool toFastEP; /* chain to the slow or fast point? */ 465362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } XDirect; 466362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Boring transfer to a guest address not known at JIT time. 467362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Not chainable. May be conditional. */ 468362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 469362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dstGA; 470362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode* amPC; 471362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSCondCode cond; /* can be MIPScc_AL */ 472362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } XIndir; 473362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Assisted transfer to a guest address, most general case. 474362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Not chainable. May be conditional. */ 475362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 476362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dstGA; 477362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode* amPC; 478362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSCondCode cond; /* can be MIPScc_AL */ 479362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj IRJumpKind jk; 480362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } XAssisted; 481362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Zero extending loads. Dst size is host word size */ 482362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 483362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj UChar sz; /* 1|2|4|8 */ 484362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 485362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode *src; 486362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Load; 487362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* 64/32/16/8 bit stores */ 488362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 489362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj UChar sz; /* 1|2|4|8 */ 490362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode *dst; 491362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg src; 492362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Store; 493362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 494362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj UChar sz; /* 4|8 */ 495362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 496362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode *src; 497362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } LoadL; 498362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 499362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj UChar sz; /* 4|8 */ 5006ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj HReg old; 5016ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj HReg addr; 5026ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj HReg expd; 5036ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj HReg data; 5046ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj } Cas; 5056ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj struct { 5066ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj UChar sz; /* 4|8 */ 507362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode *dst; 508362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg src; 509362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } StoreC; 510362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Move from HI/LO register to GP register. */ 511362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 512362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 513362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } MfHL; 514362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 515362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Move to HI/LO register from GP register. */ 516362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 517362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg src; 518362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } MtHL; 519362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 520362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Read/Write Link Register */ 521362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 522362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool wrLR; 523362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg gpr; 524362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } RdWrLR; 525362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 526362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* MIPS Multiply and accumulate instructions. */ 527362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 528362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSMaccOp op; 529362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool syned; 530362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 531362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcL; 532362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcR; 533362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Macc; 534362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 535362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* MIPS Floating point */ 536362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 537362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSFpOp op; 538362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 539362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg src; 540362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } FpUnary; 541362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 542362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSFpOp op; 543362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 544362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcL; 545362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcR; 546362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } FpBinary; 547362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 548362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSFpOp op; 549362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 550b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg src1; 551b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg src2; 552b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg src3; 553b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj } FpTernary; 554b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj struct { 555b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPSFpOp op; 556b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg dst; 557362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcML; 558362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcMR; 559362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcAcc; 560362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } FpMulAcc; 561362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 562362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool isLoad; 563362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ 564362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg reg; 565362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode *addr; 566362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } FpLdSt; 567362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 568362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 569362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSFpOp op; 570362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 571362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg src; 572362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } FpConvert; 573362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 574362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSFpOp op; 575362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 576362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcL; 577362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcR; 578362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj UChar cond1; 579362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } FpCompare; 580362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Move from GP register to FCSR register. */ 581362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 582362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg src; 583362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } MtFCSR; 584362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* Move from FCSR register to GP register. */ 585362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 586362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg dst; 587362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } MfFCSR; 588362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 589362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode* amCounter; 590362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode* amFailAddr; 591362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } EvCheck; 592362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj struct { 593362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj /* No fields. The address of the counter to inc is 594362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj installed later, post-translation, by patching it in, 595362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj as it is not known at translation time. */ 596362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } ProfInc; 597362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 598b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj /* Move from/to fpr to/from gpr */ 599b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj struct { 600b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPSFpGpMoveOp op; 601b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg dst; 602b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg src; 603b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj } FpGpMove; 604b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj struct { 605b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPSMoveCondOp op; 606b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg dst; 607b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg src; 608b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg cond; 609b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj } MoveCond; 610b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 611362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj } Min; 612362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj} MIPSInstr; 613362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 614362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_LI(HReg, ULong); 615362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Alu(MIPSAluOp, HReg, HReg, MIPSRH *); 616362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Shft(MIPSShftOp, Bool sz32, HReg, HReg, MIPSRH *); 617362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Unary(MIPSUnaryOp op, HReg dst, HReg src); 618362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Cmp(Bool, Bool, HReg, HReg, HReg, MIPSCondCode); 619362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 620362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Mul(Bool syned, Bool hi32, Bool sz32, HReg, 621362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg, HReg); 622362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Div(Bool syned, Bool sz32, HReg, HReg); 623362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Madd(Bool, HReg, HReg); 624362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Msub(Bool, HReg, HReg); 625362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 626362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Load(UChar sz, HReg dst, MIPSAMode * src, 627362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool mode64); 628362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Store(UChar sz, MIPSAMode * dst, HReg src, 629362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool mode64); 630362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 631362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_LoadL(UChar sz, HReg dst, MIPSAMode * src, 632362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool mode64); 633362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src, 634362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool mode64); 6356ced72b3286a45a9fd05989a1e13c0ac5b911feedejanjextern MIPSInstr *MIPSInstr_Cas(UChar sz, HReg old, HReg addr, 6366ced72b3286a45a9fd05989a1e13c0ac5b911feedejanj HReg expd, HReg data, Bool mode64); 637362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 638b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjextern MIPSInstr *MIPSInstr_Call ( MIPSCondCode, Addr64, UInt, HReg, RetLoc ); 639b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjextern MIPSInstr *MIPSInstr_CallAlways ( MIPSCondCode, Addr64, UInt, RetLoc ); 640362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 641b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjextern MIPSInstr *MIPSInstr_XDirect ( Addr64 dstGA, MIPSAMode* amPC, 642b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj MIPSCondCode cond, Bool toFastEP ); 643362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_XIndir(HReg dstGA, MIPSAMode* amPC, 644362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSCondCode cond); 645362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_XAssisted(HReg dstGA, MIPSAMode* amPC, 646362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSCondCode cond, IRJumpKind jk); 647362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 648362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpUnary(MIPSFpOp op, HReg dst, HReg src); 649362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpBinary(MIPSFpOp op, HReg dst, HReg srcL, 650362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcR); 651b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjextern MIPSInstr *MIPSInstr_FpTernary ( MIPSFpOp op, HReg dst, HReg src1, 652b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg src2, HReg src3 ); 653362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpConvert(MIPSFpOp op, HReg dst, HReg src); 654362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL, 655f37c086134874a2ba372f6750a45466473a813b1dejanj HReg srcR); 656362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpMulAcc(MIPSFpOp op, HReg dst, HReg srcML, 657362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg srcMR, HReg srcAcc); 658362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpLdSt(Bool isLoad, UChar sz, HReg, MIPSAMode *); 659362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpSTFIW(HReg addr, HReg data); 660362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpRSP(HReg dst, HReg src); 661362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpCftI(Bool fromI, Bool int32, HReg dst, HReg src); 662362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpCMov(MIPSCondCode, HReg dst, HReg src); 663362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_MtFCSR(HReg src); 664362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_MfFCSR(HReg dst); 665362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_FpCmp(HReg dst, HReg srcL, HReg srcR); 666362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 667362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Mfhi(HReg dst); 668362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Mflo(HReg dst); 669362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Mthi(HReg src); 670362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_Mtlo(HReg src); 671362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 672362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_RdWrLR(Bool wrLR, HReg gpr); 673362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 674b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjextern MIPSInstr *MIPSInstr_MoveCond ( MIPSMoveCondOp op, HReg dst, 675b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj HReg src, HReg cond ); 676b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarj 677b92a95406aca7bba15ecc9b5828a16fdbbdc8778petarjextern MIPSInstr *MIPSInstr_FpGpMove ( MIPSFpGpMoveOp op, HReg dst, HReg src ); 678362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 679362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_EvCheck(MIPSAMode* amCounter, 680362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj MIPSAMode* amFailAddr ); 681362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern MIPSInstr *MIPSInstr_ProfInc( void ); 682362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 683d8c64e082224b2e688abdef9219cc76fd82b373bflorianextern void ppMIPSInstr(const MIPSInstr *, Bool mode64); 684362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 685362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* Some functions that insulate the register allocator from details 686362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj of the underlying instruction set. */ 687d8c64e082224b2e688abdef9219cc76fd82b373bflorianextern void getRegUsage_MIPSInstr (HRegUsage *, const MIPSInstr *, Bool); 688d8c64e082224b2e688abdef9219cc76fd82b373bflorianextern void mapRegs_MIPSInstr (HRegRemap *, MIPSInstr *, Bool mode64); 689d8c64e082224b2e688abdef9219cc76fd82b373bflorianextern Bool isMove_MIPSInstr (const MIPSInstr *, HReg *, HReg *); 6908462d113e3efeacceb304222dada8d85f748295aflorianextern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc, 691d8c64e082224b2e688abdef9219cc76fd82b373bflorian UChar* buf, Int nbuf, const MIPSInstr* i, 6928462d113e3efeacceb304222dada8d85f748295aflorian Bool mode64, 6938462d113e3efeacceb304222dada8d85f748295aflorian VexEndness endness_host, 6948462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_chain_me_to_slowEP, 6958462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_chain_me_to_fastEP, 6968462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_xindir, 6978462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_xassisted ); 698362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 699362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern void genSpill_MIPS ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, 700362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg rreg, Int offset, Bool); 701362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardjextern void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, 702362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj HReg rreg, Int offset, Bool); 703362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 704a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjextern const RRegUniverse* getRRegUniverse_MIPS ( Bool mode64 ); 705a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 706cacba8e675988fbf21b08feea1f317a9c896c053florianextern HInstrArray *iselSB_MIPS ( const IRSB*, 707362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj VexArch, 708d8c64e082224b2e688abdef9219cc76fd82b373bflorian const VexArchInfo*, 709d8c64e082224b2e688abdef9219cc76fd82b373bflorian const VexAbiInfo*, 710362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Int offs_Host_EvC_Counter, 711362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Int offs_Host_EvC_FailAddr, 712362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool chainingAllowed, 713362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool addProfInc, 714dcd6d236c9aef7d4c84369d4c51f6b92ac910127florian Addr max_ga ); 715362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 716362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* How big is an event check? This is kind of a kludge because it 717362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER, 718362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj and so assumes that they are both <= 128, and so can use the short 719362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj offset encoding. This is all checked with assertions, so in the 720362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj worst case we will merely assert at startup. */ 7217ce2cc883c5b36586babec833838951ecf9f2a76florianextern Int evCheckSzB_MIPS (void); 722362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 723362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* Perform a chaining and unchaining of an XDirect jump. */ 7249b76916dcc1628e133d57db001563429c6e3a590sewardjextern VexInvalRange chainXDirect_MIPS ( VexEndness endness_host, 7259b76916dcc1628e133d57db001563429c6e3a590sewardj void* place_to_chain, 7267d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* disp_cp_chain_me_EXPECTED, 7277d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* place_to_jump_to, 728362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool mode64 ); 729362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 7309b76916dcc1628e133d57db001563429c6e3a590sewardjextern VexInvalRange unchainXDirect_MIPS ( VexEndness endness_host, 7319b76916dcc1628e133d57db001563429c6e3a590sewardj void* place_to_unchain, 7327d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* place_to_jump_to_EXPECTED, 7337d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* disp_cp_chain_me, 734362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool mode64 ); 735362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 736362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/* Patch the counter location into an existing ProfInc point. */ 7379b76916dcc1628e133d57db001563429c6e3a590sewardjextern VexInvalRange patchProfInc_MIPS ( VexEndness endness_host, 7389b76916dcc1628e133d57db001563429c6e3a590sewardj void* place_to_patch, 7397d6f81de12e6d8deb3e119ab318f361d97a10a65florian const ULong* location_of_counter, 740362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj Bool mode64 ); 741362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 7429b76916dcc1628e133d57db001563429c6e3a590sewardj#endif /* ndef __VEX_HOST_MIPS_DEFS_H */ 743362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj 744362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/*---------------------------------------------------------------*/ 745362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/*--- end host-mips_defs.h ---*/ 746362cf841bd241b9eb32e63bcab8b1f0042caa6f0sewardj/*---------------------------------------------------------------*/ 747