1b78f13911bfe6eda303e91ef215c87a165aae8aeAlexandre Rames// Copyright 2014, VIXL authors 2ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// All rights reserved. 3ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 4ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Redistribution and use in source and binary forms, with or without 5ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// modification, are permitted provided that the following conditions are met: 6ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 7ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions of source code must retain the above copyright notice, 8ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer. 9ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions in binary form must reproduce the above copyright notice, 10ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer in the documentation 11ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// and/or other materials provided with the distribution. 12ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Neither the name of ARM Limited nor the names of its contributors may be 13ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// used to endorse or promote products derived from this software without 14ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// specific prior written permission. 15ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 16ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 27d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#ifndef VIXL_CPU_AARCH64_H 28d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#define VIXL_CPU_AARCH64_H 29ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "../globals-vixl.h" 31b68bacb75c1ab265fc539afa93964c7f51f35589Alexandre Rames 32b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "instructions-aarch64.h" 33ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 34ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlnamespace vixl { 3588c46b84df005638546de5e4e965bdcc31352f48Pierre Langloisnamespace aarch64 { 36ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 37ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlclass CPU { 38ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl public: 39ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Initialise CPU support. 40ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static void SetUp(); 41ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 42ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Ensures the data at a given address and with a given size is the same for 43ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // the I and D caches. I and D caches are not automatically coherent on ARM 44ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // so this operation is required before any dynamically generated code can 45ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // safely run. 46ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static void EnsureIAndDCacheCoherency(void *address, size_t length); 47ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 484a102baf640077d6794c0b33bb976f94b86c532barmvixl // Handle tagged pointers. 494a102baf640077d6794c0b33bb976f94b86c532barmvixl template <typename T> 504a102baf640077d6794c0b33bb976f94b86c532barmvixl static T SetPointerTag(T pointer, uint64_t tag) { 5188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(IsUintN(kAddressTagWidth, tag)); 524a102baf640077d6794c0b33bb976f94b86c532barmvixl 534a102baf640077d6794c0b33bb976f94b86c532barmvixl // Use C-style casts to get static_cast behaviour for integral types (T), 544a102baf640077d6794c0b33bb976f94b86c532barmvixl // and reinterpret_cast behaviour for other types. 554a102baf640077d6794c0b33bb976f94b86c532barmvixl 564a102baf640077d6794c0b33bb976f94b86c532barmvixl uint64_t raw = (uint64_t)pointer; 574a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw)); 584a102baf640077d6794c0b33bb976f94b86c532barmvixl 594a102baf640077d6794c0b33bb976f94b86c532barmvixl raw = (raw & ~kAddressTagMask) | (tag << kAddressTagOffset); 604a102baf640077d6794c0b33bb976f94b86c532barmvixl return (T)raw; 614a102baf640077d6794c0b33bb976f94b86c532barmvixl } 624a102baf640077d6794c0b33bb976f94b86c532barmvixl 634a102baf640077d6794c0b33bb976f94b86c532barmvixl template <typename T> 644a102baf640077d6794c0b33bb976f94b86c532barmvixl static uint64_t GetPointerTag(T pointer) { 654a102baf640077d6794c0b33bb976f94b86c532barmvixl // Use C-style casts to get static_cast behaviour for integral types (T), 664a102baf640077d6794c0b33bb976f94b86c532barmvixl // and reinterpret_cast behaviour for other types. 674a102baf640077d6794c0b33bb976f94b86c532barmvixl 684a102baf640077d6794c0b33bb976f94b86c532barmvixl uint64_t raw = (uint64_t)pointer; 694a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw)); 704a102baf640077d6794c0b33bb976f94b86c532barmvixl 714a102baf640077d6794c0b33bb976f94b86c532barmvixl return (raw & kAddressTagMask) >> kAddressTagOffset; 724a102baf640077d6794c0b33bb976f94b86c532barmvixl } 734a102baf640077d6794c0b33bb976f94b86c532barmvixl 74ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl private: 75ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Return the content of the cache type register. 76ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static uint32_t GetCacheType(); 77ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 78ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // I and D cache line size in bytes. 79ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static unsigned icache_line_size_; 80ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static unsigned dcache_line_size_; 81ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 82ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 8388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois} // namespace aarch64 84ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} // namespace vixl 85ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 86d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#endif // VIXL_CPU_AARCH64_H 87