1b78f13911bfe6eda303e91ef215c87a165aae8aeAlexandre Rames// Copyright 2015, VIXL authors 2ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// All rights reserved. 3ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 4ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// Redistribution and use in source and binary forms, with or without 5ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// modification, are permitted provided that the following conditions are met: 6ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 7ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions of source code must retain the above copyright notice, 8ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer. 9ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Redistributions in binary form must reproduce the above copyright notice, 10ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// this list of conditions and the following disclaimer in the documentation 11ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// and/or other materials provided with the distribution. 12ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// * Neither the name of ARM Limited nor the names of its contributors may be 13ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// used to endorse or promote products derived from this software without 14ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// specific prior written permission. 15ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// 16ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 27d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#ifndef VIXL_AARCH64_SIMULATOR_AARCH64_H_ 28d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#define VIXL_AARCH64_SIMULATOR_AARCH64_H_ 29ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "../globals-vixl.h" 31b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "../utils-vixl.h" 32b68bacb75c1ab265fc539afa93964c7f51f35589Alexandre Rames 33b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "abi-aarch64.h" 34b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "disasm-aarch64.h" 35b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "instructions-aarch64.h" 36b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "instrument-aarch64.h" 37b49bdb7996e603555eba4c8b56c7325e3e737ab6Alexandre Rames#include "simulator-constants-aarch64.h" 38ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 39a4055d25c688d1397fc369a40abf57fa4f1ab805Pierre Langlois#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64 40a4055d25c688d1397fc369a40abf57fa4f1ab805Pierre Langlois 41064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// These are only used for the ABI feature, and depend on checks performed for 42064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// it. 43ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#ifdef VIXL_HAS_ABI_SUPPORT 44064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#include <tuple> 45064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#if __cplusplus >= 201402L 46064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Required for `std::index_sequence` 47064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#include <utility> 48064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 49064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 50064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 51ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlnamespace vixl { 5288c46b84df005638546de5e4e965bdcc31352f48Pierre Langloisnamespace aarch64 { 53ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// Assemble the specified IEEE-754 components into the target type and apply 556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// appropriate rounding. 566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// sign: 0 = positive, 1 = negative 576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// exponent: Unbiased IEEE-754 exponent. 586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// mantissa: The mantissa of the input. The top bit (which is not encoded for 596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// normal IEEE-754 values) must not be omitted. This bit has the 606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// value 'pow(2, exponent)'. 616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// 626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// The input value is assumed to be a normalized value. That is, the input may 636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// not be infinity or NaN. If the source value is subnormal, it must be 646e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// normalized before calling this function such that the highest set bit in the 656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// mantissa has the value 'pow(2, exponent)'. 666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// 676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// Callers should use FPRoundToFloat or FPRoundToDouble directly, rather than 686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// calling a templated FPRound. 696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixltemplate <class T, int ebits, int mbits> 700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlT FPRound(int64_t sign, 710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t exponent, 720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t mantissa, 730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl FPRounding round_mode) { 746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT((sign == 0) || (sign == 1)); 756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Only FPTieEven and FPRoundOdd rounding modes are implemented. 776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); 786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Rounding can promote subnormals to normals, and normals to infinities. For 806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // example, a double with exponent 127 (FLT_MAX_EXP) would appear to be 816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // encodable as a float, but rounding based on the low-order mantissa bits 826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // could make it overflow. With ties-to-even rounding, this value would become 836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // an infinity. 846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // ---- Rounding Method ---- 866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 876e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The exponent is irrelevant in the rounding operation, so we treat the 886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // lowest-order bit that will fit into the result ('onebit') as having 896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the value '1'. Similarly, the highest-order bit that won't fit into 906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the result ('halfbit') has the value '0.5'. The 'point' sits between 916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 'onebit' and 'halfbit': 926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // These bits fit into the result. 946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // |---------------------| 956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa = 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // || 976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | 986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / halfbit 996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // onebit 1006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For subnormal outputs, the range of representable bits is smaller and 1026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the position of onebit and halfbit depends on the exponent of the 1036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // input, but the method is otherwise similar. 1046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // onebit(frac) 1066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | 1076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | halfbit(frac) halfbit(adjusted) 1086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | / / 1096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // | | | 1106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.0 (exact) -> 0b00.0 (exact) -> 0b00 1116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.0... -> 0b00.0... -> 0b00 1126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.1 (exact) -> 0b00.0111..111 -> 0b00 1136e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b00.1... -> 0b00.1... -> 0b01 1146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.0 (exact) -> 0b01.0 (exact) -> 0b01 1156e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.0... -> 0b01.0... -> 0b01 1166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.1 (exact) -> 0b01.1 (exact) -> 0b10 1176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b01.1... -> 0b01.1... -> 0b10 1186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.0 (exact) -> 0b10.0 (exact) -> 0b10 1196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.0... -> 0b10.0... -> 0b10 1206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.1 (exact) -> 0b10.0111..111 -> 0b10 1216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b10.1... -> 0b10.1... -> 0b11 1226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 0b11.0 (exact) -> 0b11.0 (exact) -> 0b11 1236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // ... / | / | 1246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | / | 1256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // / | 1266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // adjusted = frac - (halfbit(mantissa) & ~onebit(frac)); / | 1276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa = (mantissa >> shift) + halfbit(adjusted); 1296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int mantissa_offset = 0; 1316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int exponent_offset = mantissa_offset + mbits; 1326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int sign_offset = exponent_offset + ebits; 1336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(sign_offset == (sizeof(T) * 8 - 1)); 1346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Bail out early for zero inputs. 1366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (mantissa == 0) { 137db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>(sign << sign_offset); 1386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // If all bits in the exponent are set, the value is infinite or NaN. 1416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // This is true for all binary IEEE-754 formats. 1426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int infinite_exponent = (1 << ebits) - 1; 1436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static const int max_normal_exponent = infinite_exponent - 1; 1446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Apply the exponent bias to encode it for the result. Doing this early makes 1466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // it easy to detect values that will be infinite or subnormal. 1476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent += max_normal_exponent >> 1; 1486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (exponent > max_normal_exponent) { 1506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Overflow: the input is too large for the result type to represent. 1516e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 1526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // FPTieEven rounding mode handles overflows using infinities. 1536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = infinite_exponent; 1546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa = 0; 1556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 1566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 1576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // FPRoundOdd rounding mode handles overflows using the largest magnitude 1586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal number. 1596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = max_normal_exponent; 1606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa = (UINT64_C(1) << exponent_offset) - 1; 1616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 162db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 163db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 164db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (mantissa << mantissa_offset)); 1656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Calculate the shift required to move the top mantissa bit to the proper 1686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // place in the destination type. 1696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const int highest_significant_bit = 63 - CountLeadingZeros(mantissa); 1706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int shift = highest_significant_bit - mbits; 1716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (exponent <= 0) { 1736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The output will be subnormal (before rounding). 1746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For subnormal outputs, the shift must be adjusted by the exponent. The +1 1756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // is necessary because the exponent of a subnormal value (encoded as 0) is 1766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the same as the exponent of the smallest normal value (encoded as 1). 1776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl shift += -exponent + 1; 1786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Handle inputs that would produce a zero output. 1806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 1816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Shifts higher than highest_significant_bit+1 will always produce a zero 1826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // result. A shift of exactly highest_significant_bit+1 might produce a 1836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // non-zero result after rounding. 1846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (shift > (highest_significant_bit + 1)) { 1856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 1866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // The result will always be +/-0.0. 187db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>(sign << sign_offset); 1886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 1896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 1906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(mantissa != 0); 1916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // For FPRoundOdd, if the mantissa is too small to represent and 1926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // non-zero return the next "odd" value. 193db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 1); 1946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Properly encode the exponent for a subnormal output. 1986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = 0; 1996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 2006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Clear the topmost mantissa bit, since this is not encoded in IEEE-754 2016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal values. 2026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa &= ~(UINT64_C(1) << highest_significant_bit); 2036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (shift > 0) { 2066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (round_mode == FPTieEven) { 2076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // We have to shift the mantissa to the right. Some precision is lost, so 2086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // we need to apply rounding. 2096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t onebit_mantissa = (mantissa >> (shift)) & 1; 2100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t halfbit_mantissa = (mantissa >> (shift - 1)) & 1; 2116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t adjustment = (halfbit_mantissa & ~onebit_mantissa); 2126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t adjusted = mantissa - adjustment; 2130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T halfbit_adjusted = (adjusted >> (shift - 1)) & 1; 2146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T result = 2160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static_cast<T>((sign << sign_offset) | (exponent << exponent_offset) | 2170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ((mantissa >> shift) << mantissa_offset)); 2186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // A very large mantissa can overflow during rounding. If this happens, 2206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // the exponent should be incremented and the mantissa set to 1.0 2216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // (encoded as 0). Applying halfbit_adjusted after assembling the float 2226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // has the nice side-effect that this case is handled for free. 2236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 2246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // This also handles cases where a very large finite value overflows to 2256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // infinity, or where a very large subnormal value overflows to become 2266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // normal. 2276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return result + halfbit_adjusted; 2286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 2296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPRoundOdd); 2306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // If any bits at position halfbit or below are set, onebit (ie. the 2316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // bottom bit of the resulting mantissa) must be set. 2326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t fractional_bits = mantissa & ((UINT64_C(1) << shift) - 1); 2336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (fractional_bits != 0) { 2346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa |= UINT64_C(1) << shift; 2356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 237db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 238db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 239db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl ((mantissa >> shift) << mantissa_offset)); 2406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 2426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // We have to shift the mantissa to the left (or not at all). The input 2436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // mantissa is exactly representable in the output mantissa, so apply no 2446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // rounding correction. 245db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl return static_cast<T>((sign << sign_offset) | 246db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl (exponent << exponent_offset) | 247db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl ((mantissa << -shift) << mantissa_offset)); 2486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 2506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Representation of memory, with typed getters and setters for access. 2535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass Memory { 2545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 2555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 2565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static T AddressUntag(T address) { 2575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Cast the address using a C-style cast. A reinterpret_cast would be 2585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // appropriate, but it can't cast one integral type to another. 2595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t bits = (uint64_t)address; 2605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (T)(bits & ~kAddressTagMask); 2615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename A> 2645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static T Read(A address) { 2655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T value; 2665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl address = AddressUntag(address); 2675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || 2685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 4) || (sizeof(value) == 8) || 2695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 16)); 2700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl memcpy(&value, reinterpret_cast<const char*>(address), sizeof(value)); 2715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return value; 2725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename A> 2755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static void Write(A address, T value) { 2765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl address = AddressUntag(address); 2775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) || 2785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 4) || (sizeof(value) == 8) || 2795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == 16)); 2800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl memcpy(reinterpret_cast<char*>(address), &value, sizeof(value)); 2815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 2835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Represent a register (r0-r31, v0-v31). 2850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltemplate <int kSizeInBytes> 2865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass SimRegisterBase { 2875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 2885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimRegisterBase() : written_since_last_log_(false) {} 2895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Write the specified value. The value is zero-extended if necessary. 2910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 29288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void Write(T new_value) { 2935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(new_value) <= kSizeInBytes); 2945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(new_value) < kSizeInBytes) { 2955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // All AArch64 registers are zero-extending. 2965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memset(value_ + sizeof(new_value), 0, kSizeInBytes - sizeof(new_value)); 2975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 2985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(value_, &new_value, sizeof(new_value)); 2995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NotifyRegisterWrite(); 3005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 30188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 30288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("Write", void Set(T new_value)) { 30388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Write(new_value); 30488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 3055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Insert a typed value into a register, leaving the rest of the register 3075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // unchanged. The lane parameter indicates where in the register the value 3085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // should be inserted, in the range [ 0, sizeof(value_) / sizeof(T) ), where 3095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 0 represents the least significant bits. 3100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 3115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void Insert(int lane, T new_value) { 3125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(lane >= 0); 3130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT((sizeof(new_value) + (lane * sizeof(new_value))) <= 3140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl kSizeInBytes); 3155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(&value_[lane * sizeof(new_value)], &new_value, sizeof(new_value)); 3165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NotifyRegisterWrite(); 3175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Get the value as the specified type. The value is truncated if necessary. 32088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 32188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T Get() const { 32288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetLane<T>(0); 32388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 32488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 32588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Get the lane value as the specified type. The value is truncated if 32688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // necessary. 3270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 32888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T GetLane(int lane) const { 3295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result; 3305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(lane >= 0); 3315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sizeof(result) + (lane * sizeof(result))) <= kSizeInBytes); 3325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl memcpy(&result, &value_[lane * sizeof(result)], sizeof(result)); 3335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return result; 3345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 33588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 33688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetLane", T Get(int lane) const) { 33788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetLane(lane); 33888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 3395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: Make this return a map of updated bytes, so that we can highlight 3415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // updated lanes for load-and-insert. (That never happens for scalar code, but 3425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // NEON has some instructions that can update individual lanes.) 3430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool WrittenSinceLastLog() const { return written_since_last_log_; } 3445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void NotifyRegisterLogged() { written_since_last_log_ = false; } 3465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl protected: 3485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint8_t value_[kSizeInBytes]; 3495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Helpers to aid with register tracing. 3515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool written_since_last_log_; 3525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void NotifyRegisterWrite() { written_since_last_log_ = true; } 3545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 3550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltypedef SimRegisterBase<kXRegSizeInBytes> SimRegister; // r0-r31 3560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltypedef SimRegisterBase<kQRegSizeInBytes> SimVRegister; // v0-v31 3575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Representation of a vector register, with typed getters and setters for lanes 3595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// and additional information to represent lane state. 3605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlclass LogicVRegister { 3615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl public: 36260241a544be0ebf48347789bf0ec268414364627Vincent Belliard inline LogicVRegister( 36360241a544be0ebf48347789bf0ec268414364627Vincent Belliard SimVRegister& other) // NOLINT(runtime/references)(runtime/explicit) 3645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl : register_(other) { 3655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = 0; i < sizeof(saturated_) / sizeof(saturated_[0]); i++) { 3665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl saturated_[i] = kNotSaturated; 3675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = 0; i < sizeof(round_) / sizeof(round_[0]); i++) { 3695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl round_[i] = 0; 3705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t Int(VectorFormat vform, int index) const { 3745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t element; 3755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 3760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 37788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int8_t>(index); 3780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 38088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int16_t>(index); 3810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 38388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int32_t>(index); 3840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 38688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<int64_t>(index); 3870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 3880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 3890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 3900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return 0; 3915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return element; 3935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 3945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 3955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t Uint(VectorFormat vform, int index) const { 3965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t element; 3975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 3980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 39988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint8_t>(index); 4000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 40288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint16_t>(index); 4030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 40588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint32_t>(index); 4060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 40888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois element = register_.GetLane<uint64_t>(index); 4090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return 0; 4135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return element; 4155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t UintLeftJustified(VectorFormat vform, int index) const { 4185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); 4195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4215b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell int64_t IntLeftJustified(VectorFormat vform, int index) const { 4225b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell uint64_t value = UintLeftJustified(vform, index); 4235b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell int64_t result; 4245b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell memcpy(&result, &value, sizeof(result)); 4255b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell return result; 4265b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell } 4275b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell 4285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetInt(VectorFormat vform, int index, int64_t value) const { 4295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int8_t>(value)); 4320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int16_t>(value)); 4350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int32_t>(value)); 4380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<int64_t>(value)); 4410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 448b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell void SetIntArray(VectorFormat vform, const int64_t* src) const { 449b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell ClearForWrite(vform); 450b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell for (int i = 0; i < LaneCountFromFormat(vform); i++) { 451b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell SetInt(vform, i, src[i]); 452b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell } 453b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell } 454b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell 4555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetUint(VectorFormat vform, int index, uint64_t value) const { 4565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4570f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint8_t>(value)); 4590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint16_t>(value)); 4620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint32_t>(value)); 4650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, static_cast<uint64_t>(value)); 4680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 475b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell void SetUintArray(VectorFormat vform, const uint64_t* src) const { 476b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell ClearForWrite(vform); 477b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell for (int i = 0; i < LaneCountFromFormat(vform); i++) { 478b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell SetUint(vform, i, src[i]); 479b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell } 480b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell } 481b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell 4825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const { 4835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 4840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 4850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint8_t>(addr)); 4860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 4880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint16_t>(addr)); 4890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 4910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint32_t>(addr)); 4920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 4940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl register_.Insert(index, Memory::Read<uint64_t>(addr)); 4950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 4960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 4970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 4980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return; 4995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const { 503db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t value = Uint(vform, index); 5045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (LaneSizeInBitsFromFormat(vform)) { 5050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 8: 5060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint8_t>(value)); 5070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 16: 5090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint16_t>(value)); 5100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 32: 5120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, static_cast<uint32_t>(value)); 5130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 64: 5150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Memory::Write(addr, value); 5160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 5175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 5215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T Float(int index) const { 52288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return register_.GetLane<T>(index); 5235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 5265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetFloat(int index, T value) const { 5275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl register_.Insert(index, value); 5285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // When setting a result in a register of size less than Q, the top bits of 5315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // the Q register must be cleared. 5325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ClearForWrite(VectorFormat vform) const { 5335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned size = RegisterSizeInBytesFromFormat(vform); 5345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (unsigned i = size; i < kQRegSizeInBytes; i++) { 5355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(kFormat16B, i, 0); 5365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Saturation state for each lane of a vector. 5405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl enum Saturation { 5415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kNotSaturated = 0, 5425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatPositive = 1 << 0, 5435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatNegative = 1 << 1, 5445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatMask = kSignedSatPositive | kSignedSatNegative, 5455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kSignedSatUndefined = kSignedSatMask, 5465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatPositive = 1 << 2, 5475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatNegative = 1 << 3, 5485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatMask = kUnsignedSatPositive | kUnsignedSatNegative, 5495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kUnsignedSatUndefined = kUnsignedSatMask 5505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl }; 5515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Getters for saturation state. 5535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation GetSignedSaturation(int index) { 5545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<Saturation>(saturated_[index] & kSignedSatMask); 5555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation GetUnsignedSaturation(int index) { 5585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<Saturation>(saturated_[index] & kUnsignedSatMask); 5595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Setters for saturation state. 5620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ClearSat(int index) { saturated_[index] = kNotSaturated; } 5635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetSignedSat(int index, bool positive) { 5655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetSatFlag(index, positive ? kSignedSatPositive : kSignedSatNegative); 5665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetUnsignedSat(int index, bool positive) { 5695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetSatFlag(index, positive ? kUnsignedSatPositive : kUnsignedSatNegative); 5705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SetSatFlag(int index, Saturation sat) { 5735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl saturated_[index] = static_cast<Saturation>(saturated_[index] | sat); 5745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sat & kUnsignedSatMask) != kUnsignedSatUndefined); 5755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((sat & kSignedSatMask) != kSignedSatUndefined); 5765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Saturate lanes of a vector based on saturation state. 5795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& SignedSaturate(VectorFormat vform) { 5805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation sat = GetSignedSaturation(i); 5825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sat == kSignedSatPositive) { 5835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, MaxIntFromFormat(vform)); 5845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (sat == kSignedSatNegative) { 5855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, MinIntFromFormat(vform)); 5865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 5895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& UnsignedSaturate(VectorFormat vform) { 5925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation sat = GetUnsignedSaturation(i); 5945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sat == kUnsignedSatPositive) { 5955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(vform, i, MaxUintFromFormat(vform)); 5965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (sat == kUnsignedSatNegative) { 5975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetUint(vform, i, 0); 5985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Getter for rounding state. 6040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool GetRounding(int index) { return round_[index]; } 6055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Setter for rounding state. 6070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void SetRounding(int index, bool round) { round_[index] = round; } 6085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Round lanes of a vector based on rounding state. 6105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Round(VectorFormat vform) { 6115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6125b24fb388927a1f1801a15d460d4c9448f7aa733Martyn Capewell SetUint(vform, i, Uint(vform, i) + (GetRounding(i) ? 1 : 0)); 6135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Unsigned halve lanes of a vector, and use the saturation state to set the 6185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // top bit. 6195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Uhalve(VectorFormat vform) { 6205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t val = Uint(vform, i); 6225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetRounding(i, (val & 1) == 1); 6235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val >>= 1; 6245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (GetUnsignedSaturation(i) != kNotSaturated) { 6255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the operation causes unsigned saturation, the bit shifted into the 6265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // most significant bit must be set. 6275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val |= (MaxUintFromFormat(vform) >> 1) + 1; 6285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, val); 6305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Signed halve lanes of a vector, and use the carry state to set the top bit. 6355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister& Halve(VectorFormat vform) { 6365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t val = Int(vform, i); 6385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetRounding(i, (val & 1) == 1); 6395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val >>= 1; 6405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (GetSignedSaturation(i) != kNotSaturated) { 6415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the operation causes signed saturation, the sign bit must be 6425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // inverted. 6435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl val ^= (MaxUintFromFormat(vform) >> 1) + 1; 6445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SetInt(vform, i, val); 6465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return *this; 6485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl private: 6515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister& register_; 6525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Allocate one saturation state entry per lane; largest register is type Q, 6545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // and lanes can be a minimum of one byte wide. 6555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Saturation saturated_[kQRegSizeInBytes]; 6565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Allocate one rounding state entry per lane. 6585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool round_[kQRegSizeInBytes]; 6595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl}; 6605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 661578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// The proper way to initialize a simulated system register (such as NZCV) is as 662578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// follows: 663578645f14e122d2b87d907e298cda7e7d0babf1farmvixl// SimSystemRegister nzcv = SimSystemRegister::DefaultValueFor(NZCV); 664578645f14e122d2b87d907e298cda7e7d0babf1farmvixlclass SimSystemRegister { 665578645f14e122d2b87d907e298cda7e7d0babf1farmvixl public: 666578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // The default constructor represents a register which has no writable bits. 667578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // It is not possible to set its value to anything other than 0. 6680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl SimSystemRegister() : value_(0), write_ignore_mask_(0xffffffff) {} 669578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 67088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t GetRawValue() const { return value_; } 67188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetRawValue", uint32_t RawValue() const) { 67288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetRawValue(); 67388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 674578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 675330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void SetRawValue(uint32_t new_value) { 676578645f14e122d2b87d907e298cda7e7d0babf1farmvixl value_ = (value_ & write_ignore_mask_) | (new_value & ~write_ignore_mask_); 677578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 678578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 67988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t ExtractBits(int msb, int lsb) const { 68088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractUnsignedBitfield32(msb, lsb, value_); 68188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 68288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ExtractBits", uint32_t Bits(int msb, int lsb) const) { 68388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractBits(msb, lsb); 684578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 685578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 68688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t ExtractSignedBits(int msb, int lsb) const { 68788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractSignedBitfield32(msb, lsb, value_); 68888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 68988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ExtractSignedBits", 69088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t SignedBits(int msb, int lsb) const) { 69188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractSignedBits(msb, lsb); 692578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 693578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 694578645f14e122d2b87d907e298cda7e7d0babf1farmvixl void SetBits(int msb, int lsb, uint32_t bits); 695578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 696578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Default system register values. 697578645f14e122d2b87d907e298cda7e7d0babf1farmvixl static SimSystemRegister DefaultValueFor(SystemRegister id); 698578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 69988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois#define DEFINE_GETTER(Name, HighBit, LowBit, Func) \ 70088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t Get##Name() const { return this->Func(HighBit, LowBit); } \ 70188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("Get" #Name, uint32_t Name() const) { return Get##Name(); } \ 702330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void Set##Name(uint32_t bits) { SetBits(HighBit, LowBit, bits); } 7030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_WRITE_IGNORE_MASK(Name, Mask) \ 704578645f14e122d2b87d907e298cda7e7d0babf1farmvixl static const uint32_t Name##WriteIgnoreMask = ~static_cast<uint32_t>(Mask); 705578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 706578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SYSTEM_REGISTER_FIELDS_LIST(DEFINE_GETTER, DEFINE_WRITE_IGNORE_MASK) 707578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 708578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#undef DEFINE_ZERO_BITS 709578645f14e122d2b87d907e298cda7e7d0babf1farmvixl#undef DEFINE_GETTER 710578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 711578645f14e122d2b87d907e298cda7e7d0babf1farmvixl protected: 712578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Most system registers only implement a few of the bits in the word. Other 713578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // bits are "read-as-zero, write-ignored". The write_ignore_mask argument 714578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // describes the bits which are not modifiable. 715578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister(uint32_t value, uint32_t write_ignore_mask) 7160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl : value_(value), write_ignore_mask_(write_ignore_mask) {} 717578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 718578645f14e122d2b87d907e298cda7e7d0babf1farmvixl uint32_t value_; 719578645f14e122d2b87d907e298cda7e7d0babf1farmvixl uint32_t write_ignore_mask_; 720578645f14e122d2b87d907e298cda7e7d0babf1farmvixl}; 721578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 722578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 7234a102baf640077d6794c0b33bb976f94b86c532barmvixlclass SimExclusiveLocalMonitor { 7244a102baf640077d6794c0b33bb976f94b86c532barmvixl public: 7254a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveLocalMonitor() : kSkipClearProbability(8), seed_(0x87654321) { 7264a102baf640077d6794c0b33bb976f94b86c532barmvixl Clear(); 7274a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7284a102baf640077d6794c0b33bb976f94b86c532barmvixl 7294a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the exclusive monitor (like clrex). 7304a102baf640077d6794c0b33bb976f94b86c532barmvixl void Clear() { 7314a102baf640077d6794c0b33bb976f94b86c532barmvixl address_ = 0; 7324a102baf640077d6794c0b33bb976f94b86c532barmvixl size_ = 0; 7334a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7344a102baf640077d6794c0b33bb976f94b86c532barmvixl 7354a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the exclusive monitor most of the time. 7364a102baf640077d6794c0b33bb976f94b86c532barmvixl void MaybeClear() { 7374a102baf640077d6794c0b33bb976f94b86c532barmvixl if ((seed_ % kSkipClearProbability) != 0) { 7384a102baf640077d6794c0b33bb976f94b86c532barmvixl Clear(); 7394a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7404a102baf640077d6794c0b33bb976f94b86c532barmvixl 7414a102baf640077d6794c0b33bb976f94b86c532barmvixl // Advance seed_ using a simple linear congruential generator. 7424a102baf640077d6794c0b33bb976f94b86c532barmvixl seed_ = (seed_ * 48271) % 2147483647; 7434a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7444a102baf640077d6794c0b33bb976f94b86c532barmvixl 7454a102baf640077d6794c0b33bb976f94b86c532barmvixl // Mark the address range for exclusive access (like load-exclusive). 746330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void MarkExclusive(uint64_t address, size_t size) { 747330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl address_ = address; 7484a102baf640077d6794c0b33bb976f94b86c532barmvixl size_ = size; 7494a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7504a102baf640077d6794c0b33bb976f94b86c532barmvixl 7514a102baf640077d6794c0b33bb976f94b86c532barmvixl // Return true if the address range is marked (like store-exclusive). 7524a102baf640077d6794c0b33bb976f94b86c532barmvixl // This helper doesn't implicitly clear the monitor. 753330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool IsExclusive(uint64_t address, size_t size) { 7544a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_ASSERT(size > 0); 7554a102baf640077d6794c0b33bb976f94b86c532barmvixl // Be pedantic: Require both the address and the size to match. 756330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return (size == size_) && (address == address_); 7574a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7584a102baf640077d6794c0b33bb976f94b86c532barmvixl 7594a102baf640077d6794c0b33bb976f94b86c532barmvixl private: 760330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uint64_t address_; 7614a102baf640077d6794c0b33bb976f94b86c532barmvixl size_t size_; 7624a102baf640077d6794c0b33bb976f94b86c532barmvixl 7634a102baf640077d6794c0b33bb976f94b86c532barmvixl const int kSkipClearProbability; 7644a102baf640077d6794c0b33bb976f94b86c532barmvixl uint32_t seed_; 7654a102baf640077d6794c0b33bb976f94b86c532barmvixl}; 7664a102baf640077d6794c0b33bb976f94b86c532barmvixl 7674a102baf640077d6794c0b33bb976f94b86c532barmvixl 7684a102baf640077d6794c0b33bb976f94b86c532barmvixl// We can't accurate simulate the global monitor since it depends on external 7694a102baf640077d6794c0b33bb976f94b86c532barmvixl// influences. Instead, this implementation occasionally causes accesses to 7704a102baf640077d6794c0b33bb976f94b86c532barmvixl// fail, according to kPassProbability. 7714a102baf640077d6794c0b33bb976f94b86c532barmvixlclass SimExclusiveGlobalMonitor { 7724a102baf640077d6794c0b33bb976f94b86c532barmvixl public: 7734a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveGlobalMonitor() : kPassProbability(8), seed_(0x87654321) {} 7744a102baf640077d6794c0b33bb976f94b86c532barmvixl 775330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl bool IsExclusive(uint64_t address, size_t size) { 776db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl USE(address, size); 7774a102baf640077d6794c0b33bb976f94b86c532barmvixl 7784a102baf640077d6794c0b33bb976f94b86c532barmvixl bool pass = (seed_ % kPassProbability) != 0; 7794a102baf640077d6794c0b33bb976f94b86c532barmvixl // Advance seed_ using a simple linear congruential generator. 7804a102baf640077d6794c0b33bb976f94b86c532barmvixl seed_ = (seed_ * 48271) % 2147483647; 7814a102baf640077d6794c0b33bb976f94b86c532barmvixl return pass; 7824a102baf640077d6794c0b33bb976f94b86c532barmvixl } 7834a102baf640077d6794c0b33bb976f94b86c532barmvixl 7844a102baf640077d6794c0b33bb976f94b86c532barmvixl private: 7854a102baf640077d6794c0b33bb976f94b86c532barmvixl const int kPassProbability; 7864a102baf640077d6794c0b33bb976f94b86c532barmvixl uint32_t seed_; 7874a102baf640077d6794c0b33bb976f94b86c532barmvixl}; 7884a102baf640077d6794c0b33bb976f94b86c532barmvixl 7894a102baf640077d6794c0b33bb976f94b86c532barmvixl 790ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixlclass Simulator : public DecoderVisitor { 791ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl public: 792ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl explicit Simulator(Decoder* decoder, FILE* stream = stdout); 793ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl ~Simulator(); 794ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 795ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl void ResetState(); 796ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 797ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Run the simulator. 798ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl virtual void Run(); 799c68cb64496485710cdb5b8480f8fee287058c93farmvixl void RunFrom(const Instruction* first); 800ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 8010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // Execution ends when the PC hits this address. 8020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static const Instruction* kEndOfSimAddress; 8030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 804ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Simulation helpers. 80588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois const Instruction* ReadPc() const { return pc_; } 80688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadPc", const Instruction* pc() const) { return ReadPc(); } 80788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 808e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley enum BranchLogMode { LogBranches, NoBranchLog }; 809e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley 810e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley void WritePc(const Instruction* new_pc, 811e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley BranchLogMode log_mode = LogBranches) { 812e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley if (log_mode == LogBranches) LogTakenBranch(new_pc); 8135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl pc_ = Memory::AddressUntag(new_pc); 814ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl pc_modified_ = true; 815ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 81688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WritePc", void set_pc(const Instruction* new_pc)) { 81788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WritePc(new_pc); 81888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 819ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 82088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void IncrementPc() { 821ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if (!pc_modified_) { 82288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois pc_ = pc_->GetNextInstruction(); 823ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 824ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 82588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("IncrementPc", void increment_pc()) { IncrementPc(); } 826ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 827330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void ExecuteInstruction() { 828ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // The program counter should always be aligned. 829b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_ASSERT(IsWordAligned(pc_)); 8300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl pc_modified_ = false; 831ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl decoder_->Decode(pc_); 83288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois IncrementPc(); 8330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogAllWrittenRegisters(); 834ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 835ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 8360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl// Declare all Visitor functions. 8373fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois#define DECLARE(A) \ 8383fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois virtual void Visit##A(const Instruction* instr) VIXL_OVERRIDE; 839684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VISITOR_LIST_THAT_RETURN(DECLARE) 8400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE 841ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 8423fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois#define DECLARE(A) \ 8433fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois VIXL_DEBUG_NO_RETURN virtual void Visit##A(const Instruction* instr) \ 8443fac43c1a101f98f116e752b80abc122d32b83acPierre Langlois VIXL_OVERRIDE; 845684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VISITOR_LIST_THAT_DONT_RETURN(DECLARE) 8460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE 847684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 848684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 8494a102baf640077d6794c0b33bb976f94b86c532barmvixl // Integer register accessors. 850f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 8514a102baf640077d6794c0b33bb976f94b86c532barmvixl // Basic accessor: Read the register as the specified type. 8520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 85388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadRegister(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const { 854868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT( 855868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code < kNumberOfRegisters || 856868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode))); 857ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if ((code == 31) && (r31mode == Reg31IsZeroRegister)) { 858f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T result; 859f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl memset(&result, 0, sizeof(result)); 860f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return result; 861ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 862868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode)) { 863868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code = 31; 864868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 8654a102baf640077d6794c0b33bb976f94b86c532barmvixl return registers_[code].Get<T>(); 866f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 86788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 86888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 86988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) 87088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois const) { 87188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<T>(code, r31mode); 87288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 873f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 87488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Common specialized accessors for the ReadRegister() template. 87588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t ReadWRegister(unsigned code, 87688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 87788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int32_t>(code, r31mode); 87888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 87988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadWRegister", 88088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t wreg(unsigned code, 88188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 88288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadWRegister(code, r31mode); 883ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 884ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 88588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t ReadXRegister(unsigned code, 88688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 88788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int64_t>(code, r31mode); 88888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 88988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadXRegister", 89088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t xreg(unsigned code, 89188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 89288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadXRegister(code, r31mode); 893f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 894f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 8954a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and return type. The value is 8964a102baf640077d6794c0b33bb976f94b86c532barmvixl // either zero-extended or truncated to fit, as required. 8970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 89888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadRegister(unsigned size, 89988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 90088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 9014a102baf640077d6794c0b33bb976f94b86c532barmvixl uint64_t raw; 9024a102baf640077d6794c0b33bb976f94b86c532barmvixl switch (size) { 9030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kWRegSize: 90488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadRegister<uint32_t>(code, r31mode); 9050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 9060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kXRegSize: 90788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadRegister<uint64_t>(code, r31mode); 9080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 9094a102baf640077d6794c0b33bb976f94b86c532barmvixl default: 9104a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_UNREACHABLE(); 9114a102baf640077d6794c0b33bb976f94b86c532barmvixl return 0; 9124a102baf640077d6794c0b33bb976f94b86c532barmvixl } 9134a102baf640077d6794c0b33bb976f94b86c532barmvixl 9144a102baf640077d6794c0b33bb976f94b86c532barmvixl T result; 9154a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(result) <= sizeof(raw)); 9164a102baf640077d6794c0b33bb976f94b86c532barmvixl // Copy the result and truncate to fit. This assumes a little-endian host. 9174a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&result, &raw, sizeof(result)); 9184a102baf640077d6794c0b33bb976f94b86c532barmvixl return result; 9194a102baf640077d6794c0b33bb976f94b86c532barmvixl } 92088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 92188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 92288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T reg(unsigned size, 92388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 92488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 92588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<T>(size, code, r31mode); 92688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 9274a102baf640077d6794c0b33bb976f94b86c532barmvixl 9284a102baf640077d6794c0b33bb976f94b86c532barmvixl // Use int64_t by default if T is not specified. 92988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t ReadRegister(unsigned size, 93088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 93188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const { 93288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister<int64_t>(size, code, r31mode); 93388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 93488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRegister", 93588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t reg(unsigned size, 93688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 93788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) const) { 93888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadRegister(size, code, r31mode); 939f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 940f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 9410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl enum RegLogMode { LogRegWrites, NoRegLog }; 942330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 943330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Write 'value' into an integer register. The value is zero-extended. This 944330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // behaviour matches AArch64 register writes. 9450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 94688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteRegister(unsigned code, 94788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 94888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 94988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 9504a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT((sizeof(T) == kWRegSizeInBytes) || 9514a102baf640077d6794c0b33bb976f94b86c532barmvixl (sizeof(T) == kXRegSizeInBytes)); 952868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT( 953868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code < kNumberOfRegisters || 954868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode))); 955f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 956ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl if ((code == 31) && (r31mode == Reg31IsZeroRegister)) { 957f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl return; 958ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 959ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 960868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode)) { 961868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames code = 31; 962868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 963868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 96488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois registers_[code].Write(value); 965330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 966330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (log_mode == LogRegWrites) LogRegister(code, r31mode); 967ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 96888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 96988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteRegister", 97088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_reg(unsigned code, 97188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 97288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 97388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 97488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister<T>(code, value, log_mode, r31mode); 97588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 976ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 977f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl // Common specialized accessors for the set_reg() template. 97888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteWRegister(unsigned code, 97988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t value, 98088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 98188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 98288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, value, log_mode, r31mode); 98388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 98488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteWRegister", 98588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_wreg(unsigned code, 98688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t value, 98788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 98888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 98988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteWRegister(code, value, log_mode, r31mode); 990ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 991ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 99288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteXRegister(unsigned code, 99388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t value, 99488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 99588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 99688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, value, log_mode, r31mode); 99788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 99888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteXRegister", 99988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_xreg(unsigned code, 100088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t value, 100188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 100288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 100388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteXRegister(code, value, log_mode, r31mode); 10044a102baf640077d6794c0b33bb976f94b86c532barmvixl } 10054a102baf640077d6794c0b33bb976f94b86c532barmvixl 10064a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and type. The value is either 10074a102baf640077d6794c0b33bb976f94b86c532barmvixl // zero-extended or truncated to fit, as required. 10080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 100988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteRegister(unsigned size, 101088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 101188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 101288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 101388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister) { 10144a102baf640077d6794c0b33bb976f94b86c532barmvixl // Zero-extend the input. 10154a102baf640077d6794c0b33bb976f94b86c532barmvixl uint64_t raw = 0; 10164a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(value) <= sizeof(raw)); 10174a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&raw, &value, sizeof(value)); 10184a102baf640077d6794c0b33bb976f94b86c532barmvixl 10194a102baf640077d6794c0b33bb976f94b86c532barmvixl // Write (and possibly truncate) the value. 10204a102baf640077d6794c0b33bb976f94b86c532barmvixl switch (size) { 1021db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl case kWRegSize: 102288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, static_cast<uint32_t>(raw), log_mode, r31mode); 1023db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl break; 1024db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl case kXRegSize: 102588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(code, raw, log_mode, r31mode); 1026db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl break; 10274a102baf640077d6794c0b33bb976f94b86c532barmvixl default: 10284a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_UNREACHABLE(); 10294a102baf640077d6794c0b33bb976f94b86c532barmvixl return; 10304a102baf640077d6794c0b33bb976f94b86c532barmvixl } 1031ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 103288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 103388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteRegister", 103488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_reg(unsigned size, 103588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois unsigned code, 103688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 103788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites, 103888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois Reg31Mode r31mode = Reg31IsZeroRegister)) { 103988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(size, code, value, log_mode, r31mode); 104088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1041ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 10424a102baf640077d6794c0b33bb976f94b86c532barmvixl // Common specialized accessors for the set_reg() template. 10434a102baf640077d6794c0b33bb976f94b86c532barmvixl 1044f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl // Commonly-used special cases. 10450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 104688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteLr(T value) { 104788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(kLinkRegCode, value); 104888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 104988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 105088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteLr", void set_lr(T value)) { 105188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteLr(value); 1052ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1053ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 10540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 105588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSp(T value) { 105688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteRegister(31, value, LogRegWrites, Reg31IsStackPointer); 105788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 105888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 105988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSp", void set_sp(T value)) { 106088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSp(value); 1061f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl } 1062ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 10635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Vector register accessors. 10645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // These are equivalent to the integer register accessors, but for vector 10654a102baf640077d6794c0b33bb976f94b86c532barmvixl // registers. 1066f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 10675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // A structure for representing a 128-bit Q register. 10680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl struct qreg_t { 10690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint8_t val[kQRegSizeInBytes]; 10700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl }; 10715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Basic accessor: read the register as the specified type. 10730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 107488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadVRegister(unsigned code) const { 10750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_STATIC_ASSERT( 10760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kBRegSizeInBytes) || (sizeof(T) == kHRegSizeInBytes) || 10770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kSRegSizeInBytes) || (sizeof(T) == kDRegSizeInBytes) || 10780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sizeof(T) == kQRegSizeInBytes)); 10795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(code < kNumberOfVRegisters); 10805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return vregisters_[code].Get<T>(); 10825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 108388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 108488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", T vreg(unsigned code) const) { 108588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<T>(code); 108688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 10875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Common specialized accessors for the vreg() template. 108988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t ReadBRegister(unsigned code) const { 109088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<int8_t>(code); 109188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 109288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadBRegister", int8_t breg(unsigned code) const) { 109388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadBRegister(code); 109488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 10954a102baf640077d6794c0b33bb976f94b86c532barmvixl 109688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t ReadHRegister(unsigned code) const { 109788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<int16_t>(code); 109888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 109988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadHRegister", int16_t hreg(unsigned code) const) { 110088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadHRegister(code); 110188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1102ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 110388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float ReadSRegister(unsigned code) const { 110488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<float>(code); 110588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 110688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadSRegister", float sreg(unsigned code) const) { 110788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadSRegister(code); 110888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1109ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 111088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t ReadSRegisterBits(unsigned code) const { 111188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<uint32_t>(code); 111288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 111388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadSRegisterBits", 111488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t sreg_bits(unsigned code) const) { 111588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadSRegisterBits(code); 111688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1117ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 111888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double ReadDRegister(unsigned code) const { 111988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<double>(code); 112088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 112188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDRegister", double dreg(unsigned code) const) { 112288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDRegister(code); 112388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1124ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 112588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t ReadDRegisterBits(unsigned code) const { 112688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<uint64_t>(code); 112788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 112888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDRegisterBits", 112988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t dreg_bits(unsigned code) const) { 113088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDRegisterBits(code); 113188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 11325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 113388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t ReadQRegister(unsigned code) const { 113488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<qreg_t>(code); 113588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 113688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadQRegister", qreg_t qreg(unsigned code) const) { 113788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadQRegister(code); 113888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1139ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 11404a102baf640077d6794c0b33bb976f94b86c532barmvixl // As above, with parameterized size and return type. The value is 11414a102baf640077d6794c0b33bb976f94b86c532barmvixl // either zero-extended or truncated to fit, as required. 11420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 114388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T ReadVRegister(unsigned size, unsigned code) const { 11445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t raw = 0; 11455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result; 11465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1147ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (size) { 11480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kSRegSize: 114988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadVRegister<uint32_t>(code); 11500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 11510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kDRegSize: 115288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois raw = ReadVRegister<uint64_t>(code); 11530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 1154f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl default: 1155b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 11564a102baf640077d6794c0b33bb976f94b86c532barmvixl break; 1157ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 11584a102baf640077d6794c0b33bb976f94b86c532barmvixl 11594a102baf640077d6794c0b33bb976f94b86c532barmvixl VIXL_STATIC_ASSERT(sizeof(result) <= sizeof(raw)); 11604a102baf640077d6794c0b33bb976f94b86c532barmvixl // Copy the result and truncate to fit. This assumes a little-endian host. 11614a102baf640077d6794c0b33bb976f94b86c532barmvixl memcpy(&result, &raw, sizeof(result)); 11624a102baf640077d6794c0b33bb976f94b86c532barmvixl return result; 1163ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 116488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 116588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", T vreg(unsigned size, unsigned code) const) { 116688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister<T>(size, code); 116788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1168ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 116988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimVRegister& ReadVRegister(unsigned code) { return vregisters_[code]; } 117088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadVRegister", SimVRegister& vreg(unsigned code)) { 117188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadVRegister(code); 117288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 11735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11744a102baf640077d6794c0b33bb976f94b86c532barmvixl // Basic accessor: Write the specified value. 11750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 117688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteVRegister(unsigned code, 117788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 117888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 11795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT((sizeof(value) == kBRegSizeInBytes) || 11805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kHRegSizeInBytes) || 11815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kSRegSizeInBytes) || 11825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kDRegSizeInBytes) || 11835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (sizeof(value) == kQRegSizeInBytes)); 11845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(code < kNumberOfVRegisters); 118588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois vregisters_[code].Write(value); 1186330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1187330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl if (log_mode == LogRegWrites) { 11885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogVRegister(code, GetPrintRegisterFormat(value)); 1189330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1190ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 119188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois template <typename T> 119288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteVRegister", 119388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_vreg(unsigned code, 119488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois T value, 119588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 119688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 119788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1198ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 119988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Common specialized accessors for the WriteVRegister() template. 120088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteBRegister(unsigned code, 120188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t value, 120288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 120388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 120488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 120588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteBRegister", 120688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_breg(unsigned code, 120788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int8_t value, 120888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 120988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WriteBRegister(code, value, log_mode); 12105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 121288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteHRegister(unsigned code, 121388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t value, 121488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 121588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 121688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 121788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteHRegister", 121888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_hreg(unsigned code, 121988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int16_t value, 122088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 122188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return WriteHRegister(code, value, log_mode); 12225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 122488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSRegister(unsigned code, 122588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float value, 122688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 122788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 122888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 122988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSRegister", 123088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_sreg(unsigned code, 123188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois float value, 123288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 123388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSRegister(code, value, log_mode); 1234ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1235ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 123688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteSRegisterBits(unsigned code, 123788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t value, 123888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 123988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 124088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 124188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteSRegisterBits", 124288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_sreg_bits(unsigned code, 124388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t value, 124488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 124588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteSRegisterBits(code, value, log_mode); 1246ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1247ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 124888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteDRegister(unsigned code, 124988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double value, 125088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 125188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 125288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 125388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteDRegister", 125488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_dreg(unsigned code, 125588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double value, 125688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 125788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteDRegister(code, value, log_mode); 1258ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1259ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 126088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteDRegisterBits(unsigned code, 126188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t value, 126288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 126388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 126488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 126588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteDRegisterBits", 126688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_dreg_bits(unsigned code, 126788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t value, 126888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 126988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteDRegisterBits(code, value, log_mode); 12705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 127288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void WriteQRegister(unsigned code, 127388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t value, 127488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites) { 127588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteVRegister(code, value, log_mode); 1276ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 127788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("WriteQRegister", 127888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_qreg(unsigned code, 127988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois qreg_t value, 128088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois RegLogMode log_mode = LogRegWrites)) { 128188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois WriteQRegister(code, value, log_mode); 128288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 128388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 1284868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1285868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadRegister(Register reg) const { 1286868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadRegister<T>(reg.GetCode(), Reg31IsZeroRegister); 1287868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1288868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1289868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1290868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteRegister(Register reg, 1291868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1292868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1293868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteRegister<T>(reg.GetCode(), value, log_mode, Reg31IsZeroRegister); 1294868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1295868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1296868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1297868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadVRegister(VRegister vreg) const { 1298868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadVRegister<T>(vreg.GetCode()); 1299868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1300868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1301868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1302868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteVRegister(VRegister vreg, 1303868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1304868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1305868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteVRegister<T>(vreg.GetCode(), value, log_mode); 1306868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1307868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1308868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1309868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadCPURegister(CPURegister reg) const { 1310868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (reg.IsVRegister()) { 1311868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadVRegister<T>(VRegister(reg)); 1312868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1313868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadRegister<T>(Register(reg)); 1314868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1315868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1316868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1317868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1318868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteCPURegister(CPURegister reg, 1319868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1320868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1321868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (reg.IsVRegister()) { 1322868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteVRegister<T>(VRegister(reg), value, log_mode); 1323868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1324868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteRegister<T>(Register(reg), value, log_mode); 1325868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1326868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1327868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1328868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames uint64_t ComputeMemOperandAddress(const MemOperand& mem_op) const; 1329868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1330868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1331868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T ReadGenericOperand(GenericOperand operand) const { 1332868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (operand.IsCPURegister()) { 1333868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return ReadCPURegister<T>(operand.GetCPURegister()); 1334868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1335868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT(operand.IsMemOperand()); 1336868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames return Memory::Read<T>(ComputeMemOperandAddress(operand.GetMemOperand())); 1337868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1338868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1339868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 1340868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames template <typename T> 1341868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames void WriteGenericOperand(GenericOperand operand, 1342868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames T value, 1343868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames RegLogMode log_mode = LogRegWrites) { 1344868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames if (operand.IsCPURegister()) { 1345868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames WriteCPURegister<T>(operand.GetCPURegister(), value, log_mode); 1346868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } else { 1347868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames VIXL_ASSERT(operand.IsMemOperand()); 1348868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames Memory::Write(ComputeMemOperandAddress(operand.GetMemOperand()), value); 1349868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1350868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames } 1351868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames 135288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadN() const { return nzcv_.GetN() != 0; } 135388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadN", bool N() const) { return ReadN(); } 1354ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 135588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadZ() const { return nzcv_.GetZ() != 0; } 135688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadZ", bool Z() const) { return ReadZ(); } 135788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 135888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadC() const { return nzcv_.GetC() != 0; } 135988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadC", bool C() const) { return ReadC(); } 136088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 136188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadV() const { return nzcv_.GetV() != 0; } 136288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadV", bool V() const) { return ReadV(); } 136388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 136488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimSystemRegister& ReadNzcv() { return nzcv_; } 136588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadNzcv", SimSystemRegister& nzcv()) { return ReadNzcv(); } 1366578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 13675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO: Find a way to make the fpcr_ members return the proper types, so 13685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // these accessors are not necessary. 136988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois FPRounding ReadRMode() const { 137088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return static_cast<FPRounding>(fpcr_.GetRMode()); 137188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 137288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadRMode", FPRounding RMode()) { return ReadRMode(); } 137388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 137488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool ReadDN() const { return fpcr_.GetDN() != 0; } 137588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadDN", bool DN()) { return ReadDN(); } 137688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 137788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SimSystemRegister& ReadFpcr() { return fpcr_; } 137888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("ReadFpcr", SimSystemRegister& fpcr()) { return ReadFpcr(); } 1379ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 13805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Specify relevant register formats for Print(V)Register and related helpers. 13815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl enum PrintRegisterFormat { 13825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // The lane size. 13835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeB = 0 << 0, 13845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeH = 1 << 0, 13855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeS = 2 << 0, 13865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeW = kPrintRegLaneSizeS, 13875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeD = 3 << 0, 13885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeX = kPrintRegLaneSizeD, 13895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeQ = 4 << 0, 13905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeOffset = 0, 13925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegLaneSizeMask = 7 << 0, 13935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // The lane count. 13955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsScalar = 0, 13965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsDVector = 1 << 3, 13975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsQVector = 2 << 3, 13985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsVectorMask = 3 << 3, 14005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Indicate floating-point format lanes. (This flag is only supported for S- 14025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // and D-sized lanes.) 14035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintRegAsFP = 1 << 5, 14045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Supported combinations. 14065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintXReg = kPrintRegLaneSizeX | kPrintRegAsScalar, 14085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintWReg = kPrintRegLaneSizeW | kPrintRegAsScalar, 14095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintSReg = kPrintRegLaneSizeS | kPrintRegAsScalar | kPrintRegAsFP, 14105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintDReg = kPrintRegLaneSizeD | kPrintRegAsScalar | kPrintRegAsFP, 14115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1B = kPrintRegLaneSizeB | kPrintRegAsScalar, 14135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg8B = kPrintRegLaneSizeB | kPrintRegAsDVector, 14145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg16B = kPrintRegLaneSizeB | kPrintRegAsQVector, 14155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1H = kPrintRegLaneSizeH | kPrintRegAsScalar, 14165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4H = kPrintRegLaneSizeH | kPrintRegAsDVector, 14175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg8H = kPrintRegLaneSizeH | kPrintRegAsQVector, 14185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1S = kPrintRegLaneSizeS | kPrintRegAsScalar, 14195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2S = kPrintRegLaneSizeS | kPrintRegAsDVector, 14205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4S = kPrintRegLaneSizeS | kPrintRegAsQVector, 14215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1SFP = kPrintRegLaneSizeS | kPrintRegAsScalar | kPrintRegAsFP, 14225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2SFP = kPrintRegLaneSizeS | kPrintRegAsDVector | kPrintRegAsFP, 14235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg4SFP = kPrintRegLaneSizeS | kPrintRegAsQVector | kPrintRegAsFP, 14245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1D = kPrintRegLaneSizeD | kPrintRegAsScalar, 14255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2D = kPrintRegLaneSizeD | kPrintRegAsQVector, 14265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1DFP = kPrintRegLaneSizeD | kPrintRegAsScalar | kPrintRegAsFP, 14275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg2DFP = kPrintRegLaneSizeD | kPrintRegAsQVector | kPrintRegAsFP, 14285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl kPrintReg1Q = kPrintRegLaneSizeQ | kPrintRegAsScalar 14295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl }; 14305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneSizeInBytesLog2(PrintRegisterFormat format) { 14325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (format & kPrintRegLaneSizeMask) >> kPrintRegLaneSizeOffset; 14335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneSizeInBytes(PrintRegisterFormat format) { 14365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << GetPrintRegLaneSizeInBytesLog2(format); 14375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegSizeInBytesLog2(PrintRegisterFormat format) { 14405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (format & kPrintRegAsDVector) return kDRegSizeInBytesLog2; 14415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (format & kPrintRegAsQVector) return kQRegSizeInBytesLog2; 14425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Scalar types. 14445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegLaneSizeInBytesLog2(format); 14455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegSizeInBytes(PrintRegisterFormat format) { 14485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << GetPrintRegSizeInBytesLog2(format); 14495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned GetPrintRegLaneCount(PrintRegisterFormat format) { 14525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned reg_size_log2 = GetPrintRegSizeInBytesLog2(format); 14535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned lane_size_log2 = GetPrintRegLaneSizeInBytesLog2(format); 14545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(reg_size_log2 >= lane_size_log2); 14555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 1 << (reg_size_log2 - lane_size_log2); 14565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSize(unsigned reg_size, 14595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl unsigned lane_size); 14605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSize(unsigned size) { 14625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSize(size, size); 14635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatForSizeFP(unsigned size) { 14665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (size) { 14670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 14680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 14690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintDReg; 14700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kDRegSizeInBytes: 14710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintDReg; 14720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kSRegSizeInBytes: 14730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return kPrintSReg; 14745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormatTryFP(PrintRegisterFormat format) { 14785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((GetPrintRegLaneSizeInBytes(format) == kSRegSizeInBytes) || 14795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (GetPrintRegLaneSizeInBytes(format) == kDRegSizeInBytes)) { 14805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<PrintRegisterFormat>(format | kPrintRegAsFP); 14815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return format; 14835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> 14865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(T value) { 14875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSize(sizeof(value)); 14885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(double value) { 14915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(value) == kDRegSizeInBytes); 14925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSizeFP(sizeof(value)); 14935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(float value) { 14965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_STATIC_ASSERT(sizeof(value) == kSRegSizeInBytes); 14975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return GetPrintRegisterFormatForSizeFP(sizeof(value)); 14985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat GetPrintRegisterFormat(VectorFormat vform); 15010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat GetPrintRegisterFormatFP(VectorFormat vform); 15025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1503330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print all registers of the specified types. 1504330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintRegisters(); 15055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintVRegisters(); 1506330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintSystemRegisters(); 1507330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 15085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // As above, but only print the registers that have been updated. 15095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintWrittenRegisters(); 15105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintWrittenVRegisters(); 15115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // As above, but respect LOG_REG and LOG_VREG. 15135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogWrittenRegisters() { 151488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintWrittenRegisters(); 1515330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogWrittenVRegisters() { 151788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) PrintWrittenVRegisters(); 1518330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogAllWrittenRegisters() { 15205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogWrittenRegisters(); 15215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogWrittenVRegisters(); 1522330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1523330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1524330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print individual register values (after update). 1525330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer); 15265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void PrintVRegister(unsigned code, PrintRegisterFormat format); 1527330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void PrintSystemRegister(SystemRegister id); 1528e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley void PrintTakenBranch(const Instruction* target); 1529330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 153088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Like Print* (above), but respect GetTraceParameters(). 1531330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void LogRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer) { 153288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintRegister(code, r31mode); 1533330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void LogVRegister(unsigned code, PrintRegisterFormat format) { 153588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) PrintVRegister(code, format); 1536330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1537330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void LogSystemRegister(SystemRegister id) { 153888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_SYSREGS) PrintSystemRegister(id); 1539330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1540e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley void LogTakenBranch(const Instruction* target) { 1541e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley if (GetTraceParameters() & LOG_BRANCH) PrintTakenBranch(target); 1542e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley } 1543330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1544330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // Print memory accesses. 15450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintRead(uintptr_t address, 15460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format); 15480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintWrite(uintptr_t address, 15490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format); 15510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRead(uintptr_t address, 15520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 15540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane); 15550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVWrite(uintptr_t address, 15560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15570f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 15580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane); 1559330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 156088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Like Print* (above), but respect GetTraceParameters(). 15610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogRead(uintptr_t address, 15620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format) { 156488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_REGS) PrintRead(address, reg_code, format); 1565330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogWrite(uintptr_t address, 15670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintRegisterFormat format) { 156988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_WRITE) PrintWrite(address, reg_code, format); 1570330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogVRead(uintptr_t address, 15720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 15740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane = 0) { 157588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_VREGS) { 15765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintVRead(address, reg_code, format, lane); 15775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 1578330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 15790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void LogVWrite(uintptr_t address, 15800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned reg_code, 15810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PrintRegisterFormat format, 15820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane = 0) { 158388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (GetTraceParameters() & LOG_WRITE) { 15845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PrintVWrite(address, reg_code, format, lane); 15855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 1586330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl } 1587330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 15885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Helper functions for register tracing. 15890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintRegisterRawHelper(unsigned code, 15900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl Reg31Mode r31mode, 15915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int size_in_bytes = kXRegSizeInBytes); 15920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRegisterRawHelper(unsigned code, 15930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int bytes = kQRegSizeInBytes, 15945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lsb = 0); 15950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void PrintVRegisterFPHelper(unsigned code, 15960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl unsigned lane_size_in_bytes, 15970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int lane_count = 1, 15980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int rightmost_lane = 0); 15995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1600684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl VIXL_NO_RETURN void DoUnreachable(const Instruction* instr); 1601330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void DoTrace(const Instruction* instr); 1602330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void DoLog(const Instruction* instr); 1603ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1604ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* WRegNameForCode(unsigned code, 1605ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Reg31Mode mode = Reg31IsZeroRegister); 1606ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* XRegNameForCode(unsigned code, 1607ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Reg31Mode mode = Reg31IsZeroRegister); 1608ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* SRegNameForCode(unsigned code); 1609ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* DRegNameForCode(unsigned code); 1610ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* VRegNameForCode(unsigned code); 1611ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 161288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois bool IsColouredTrace() const { return coloured_trace_; } 161388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("IsColouredTrace", bool coloured_trace() const) { 161488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return IsColouredTrace(); 161588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1616ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 161788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetColouredTrace(bool value); 161888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetColouredTrace", void set_coloured_trace(bool value)) { 161988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetColouredTrace(value); 162088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1621330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 1622d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames // Values for traces parameters defined in simulator-constants-aarch64.h in 162388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // enum TraceParameters. 162488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int GetTraceParameters() const { return trace_parameters_; } 162588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("GetTraceParameters", int trace_parameters() const) { 162688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return GetTraceParameters(); 162788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 162888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 162988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetTraceParameters(int parameters); 163088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetTraceParameters", 163188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_trace_parameters(int parameters)) { 163288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetTraceParameters(parameters); 163388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 163488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois 163588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void SetInstructionStats(bool value); 163688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_DEPRECATED("SetInstructionStats", 163788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois void set_instruction_stats(bool value)) { 163888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois SetInstructionStats(value); 163988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois } 1640ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 16414a102baf640077d6794c0b33bb976f94b86c532barmvixl // Clear the simulated local monitor to force the next store-exclusive 16424a102baf640077d6794c0b33bb976f94b86c532barmvixl // instruction to fail. 16430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ClearLocalMonitor() { local_monitor_.Clear(); } 16444a102baf640077d6794c0b33bb976f94b86c532barmvixl 1645330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl void SilenceExclusiveAccessWarning() { 16464a102baf640077d6794c0b33bb976f94b86c532barmvixl print_exclusive_access_warning_ = false; 16474a102baf640077d6794c0b33bb976f94b86c532barmvixl } 16484a102baf640077d6794c0b33bb976f94b86c532barmvixl 1649064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Runtime call emulation support. 1650064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// It requires VIXL's ABI features, and C++11 or greater. 1651482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley// Also, the initialisation of the tuples in RuntimeCall(Non)Void is incorrect 1652482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley// in GCC before 4.9.1: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51253 1653482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley#if defined(VIXL_HAS_ABI_SUPPORT) && __cplusplus >= 201103L && \ 1654482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley (defined(__clang__) || GCC_VERSION_OR_NEWER(4, 9, 1)) 1655064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1656ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#define VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT 1657064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1658064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// The implementation of the runtime call helpers require the functionality 1659064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// provided by `std::index_sequence`. It is only available from C++14, but 1660064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// we want runtime call simulation to work from C++11, so we emulate if 1661064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// necessary. 1662064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#if __cplusplus >= 201402L 1663064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t... I> 1664064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using local_index_sequence = std::index_sequence<I...>; 1665064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1666064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using __local_index_sequence_for = std::index_sequence_for<P...>; 1667064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#else 1668064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Emulate the behaviour of `std::index_sequence` and 1669064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // `std::index_sequence_for`. 1670064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Naming follow the `std` names, prefixed with `emulated_`. 1671064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <size_t... I> 1672064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_index_sequence {}; 1673064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1674064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // A recursive template to create a sequence of indexes. 1675064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // The base case (for `N == 0`) is declared outside of the class scope, as 1676064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // required by C++. 1677064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t N, size_t... I> 1678064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_make_index_sequence_helper 1679064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : emulated_make_index_sequence_helper<N - 1, N - 1, I...> {}; 1680064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1681064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t N> 1682064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_make_index_sequence : emulated_make_index_sequence_helper<N> { 1683064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1684064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1685064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1686064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct emulated_index_sequence_for 1687064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : emulated_make_index_sequence<sizeof...(P)> {}; 1688064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1689064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <std::size_t... I> 1690064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using local_index_sequence = emulated_index_sequence<I...>; 1691064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1692064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames using __local_index_sequence_for = emulated_index_sequence_for<P...>; 1693064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 1694064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1695064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Expand the argument tuple and perform the call. 1696064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P, std::size_t... I> 1697064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R DoRuntimeCall(R (*function)(P...), 1698064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> arguments, 1699064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames local_index_sequence<I...>) { 1700064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames return function(std::get<I>(arguments)...); 1701064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1702064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1703064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1704064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void RuntimeCallNonVoid(R (*function)(P...)) { 1705064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ABI abi; 1706064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> argument_operands{ 1707064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ReadGenericOperand<P>(abi.GetNextParameterGenericOperand<P>())...}; 1708064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R return_value = DoRuntimeCall(function, 1709064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames argument_operands, 1710064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames __local_index_sequence_for<P...>{}); 1711064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames WriteGenericOperand(abi.GetReturnGenericOperand<R>(), return_value); 1712064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1713064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1714064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1715064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void RuntimeCallVoid(R (*function)(P...)) { 1716064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ABI abi; 1717064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames std::tuple<P...> argument_operands{ 1718064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames ReadGenericOperand<P>(abi.GetNextParameterGenericOperand<P>())...}; 1719064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames DoRuntimeCall(function, 1720064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames argument_operands, 1721064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames __local_index_sequence_for<P...>{}); 1722064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1723064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1724064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // We use `struct` for `void` return type specialisation. 1725064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename R, typename... P> 1726064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct RuntimeCallStructHelper { 1727482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley static void Wrapper(Simulator* simulator, uintptr_t function_pointer) { 1728064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames R (*function)(P...) = reinterpret_cast<R (*)(P...)>(function_pointer); 1729064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames simulator->RuntimeCallNonVoid(function); 1730064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1731064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1732064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1733064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames // Partial specialization when the return type is `void`. 1734064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames template <typename... P> 1735064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames struct RuntimeCallStructHelper<void, P...> { 1736482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley static void Wrapper(Simulator* simulator, uintptr_t function_pointer) { 1737064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void (*function)(P...) = 1738064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames reinterpret_cast<void (*)(P...)>(function_pointer); 1739064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames simulator->RuntimeCallVoid(function); 1740064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames } 1741064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames }; 1742064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 1743064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 1744ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl protected: 1745b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_normal; 1746b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_flag_name; 1747b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_flag_value; 1748b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_reg_name; 1749b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_reg_value; 17505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const char* clr_vreg_name; 17515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const char* clr_vreg_value; 1752b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_memory_address; 17534a102baf640077d6794c0b33bb976f94b86c532barmvixl const char* clr_warning; 17544a102baf640077d6794c0b33bb976f94b86c532barmvixl const char* clr_warning_message; 1755b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl const char* clr_printf; 1756e79723a010a6f42fe78e2515c7b0eb9308b93093Jacob Bramley const char* clr_branch_marker; 1757b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 1758ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Simulation helpers ------------------------------------ 1759ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool ConditionPassed(Condition cond) { 1760ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl switch (cond) { 1761ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case eq: 176288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadZ(); 1763ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ne: 176488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadZ(); 1765ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case hs: 176688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadC(); 1767ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case lo: 176888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadC(); 1769ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case mi: 177088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN(); 1771ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case pl: 177288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadN(); 1773ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case vs: 177488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadV(); 1775ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case vc: 177688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadV(); 1777ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case hi: 177888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadC() && !ReadZ(); 1779ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ls: 178088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !(ReadC() && !ReadZ()); 1781ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case ge: 178288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN() == ReadV(); 1783ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case lt: 178488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadN() != ReadV(); 1785ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case gt: 178688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !ReadZ() && (ReadN() == ReadV()); 1787ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case le: 178888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return !(!ReadZ() && (ReadN() == ReadV())); 17896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case nv: 17906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_FALLTHROUGH(); 1791ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl case al: 1792ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return true; 1793ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl default: 1794b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl VIXL_UNREACHABLE(); 1795ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl return false; 1796ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1797ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 1798ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 17994a102baf640077d6794c0b33bb976f94b86c532barmvixl bool ConditionPassed(Instr cond) { 18004a102baf640077d6794c0b33bb976f94b86c532barmvixl return ConditionPassed(static_cast<Condition>(cond)); 18014a102baf640077d6794c0b33bb976f94b86c532barmvixl } 18024a102baf640077d6794c0b33bb976f94b86c532barmvixl 18030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool ConditionFailed(Condition cond) { return !ConditionPassed(cond); } 1804ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1805c68cb64496485710cdb5b8480f8fee287058c93farmvixl void AddSubHelper(const Instruction* instr, int64_t op2); 1806684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t AddWithCarry(unsigned reg_size, 1807684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl bool set_flags, 1808684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t left, 1809684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl uint64_t right, 1810684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl int carry_in = 0); 1811c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LogicalHelper(const Instruction* instr, int64_t op2); 1812c68cb64496485710cdb5b8480f8fee287058c93farmvixl void ConditionalCompareHelper(const Instruction* instr, int64_t op2); 1813c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LoadStoreHelper(const Instruction* instr, 1814ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t offset, 1815ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl AddrMode addrmode); 1816c68cb64496485710cdb5b8480f8fee287058c93farmvixl void LoadStorePairHelper(const Instruction* instr, AddrMode addrmode); 1817330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uintptr_t AddressModeHelper(unsigned addr_reg, 1818330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl int64_t offset, 1819330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl AddrMode addrmode); 18205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void NEONLoadStoreMultiStructHelper(const Instruction* instr, 18215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl AddrMode addr_mode); 18225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void NEONLoadStoreSingleStructHelper(const Instruction* instr, 18235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl AddrMode addr_mode); 1824330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl 18250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t AddressUntag(uint64_t address) { return address & ~kAddressTagMask; } 1826ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 18274a102baf640077d6794c0b33bb976f94b86c532barmvixl template <typename T> 1828330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl T* AddressUntag(T* address) { 1829330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl uintptr_t address_raw = reinterpret_cast<uintptr_t>(address); 1830330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl return reinterpret_cast<T*>(AddressUntag(address_raw)); 18314a102baf640077d6794c0b33bb976f94b86c532barmvixl } 1832ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 1833ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t ShiftOperand(unsigned reg_size, 1834ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t value, 1835ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Shift shift_type, 1836868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames unsigned amount) const; 1837ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t ExtendValue(unsigned reg_width, 1838ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t value, 1839ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Extend extend_type, 1840868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames unsigned left_shift = 0) const; 1841868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Rames uint16_t PolynomialMult(uint8_t op1, uint8_t op2) const; 18425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr); 18440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr); 18450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr); 18465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2(VectorFormat vform, 18475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2(VectorFormat vform, 18515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld2r(VectorFormat vform, 18560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 18570f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 18580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 18595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3(VectorFormat vform, 18605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 18635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3(VectorFormat vform, 18655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 18685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld3r(VectorFormat vform, 18710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 18720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 18730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst3, 18740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 18755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4(VectorFormat vform, 18765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 18795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 18805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4(VectorFormat vform, 18825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 18835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 18845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 18855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 18865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 18875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 18885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void ld4r(VectorFormat vform, 18890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst1, 18900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst2, 18910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst3, 18920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst4, 18930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t addr); 18940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void st1(VectorFormat vform, LogicVRegister src, uint64_t addr); 18950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr); 18965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st2(VectorFormat vform, 18975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 18985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 18995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st2(VectorFormat vform, 19015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st3(VectorFormat vform, 19065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 19095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st3(VectorFormat vform, 19115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 19145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st4(VectorFormat vform, 19175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 19205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src4, 19215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void st4(VectorFormat vform, 19235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 19245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src2, 19255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src3, 19265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src4, 19275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 19285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr); 19295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmp(VectorFormat vform, 19305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 19345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmp(VectorFormat vform, 19355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int imm, 19385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 19395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cmptst(VectorFormat vform, 19405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister add(VectorFormat vform, 19445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addp(VectorFormat vform, 19485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mla(VectorFormat vform, 19525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mls(VectorFormat vform, 19565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mul(VectorFormat vform, 19605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mul(VectorFormat vform, 19645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mla(VectorFormat vform, 19695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister mls(VectorFormat vform, 19745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister pmul(VectorFormat vform, 19795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 19825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl typedef LogicVRegister (Simulator::*ByElementOp)(VectorFormat vform, 19845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmul(VectorFormat vform, 19895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 19945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 19975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 19985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 19995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmulx(VectorFormat vform, 20045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smull(VectorFormat vform, 20095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smull2(VectorFormat vform, 20145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umull(VectorFormat vform, 20195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umull2(VectorFormat vform, 20245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlal(VectorFormat vform, 20295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlal2(VectorFormat vform, 20345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlal(VectorFormat vform, 20395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlal2(VectorFormat vform, 20445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlsl(VectorFormat vform, 20495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smlsl2(VectorFormat vform, 20545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlsl(VectorFormat vform, 20595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umlsl2(VectorFormat vform, 20645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmull(VectorFormat vform, 20695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmull2(VectorFormat vform, 20745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlal(VectorFormat vform, 20795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlal2(VectorFormat vform, 20845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlsl(VectorFormat vform, 20895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmlsl2(VectorFormat vform, 20945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 20965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 20975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 20985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmulh(VectorFormat vform, 20995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrdmulh(VectorFormat vform, 21045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sub(VectorFormat vform, 21095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister and_(VectorFormat vform, 21135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orr(VectorFormat vform, 21175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orn(VectorFormat vform, 21215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister eor(VectorFormat vform, 21255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bic(VectorFormat vform, 21295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bic(VectorFormat vform, 21335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 21365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bif(VectorFormat vform, 21375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bit(VectorFormat vform, 21415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister bsl(VectorFormat vform, 21455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 21485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cls(VectorFormat vform, 21495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister clz(VectorFormat vform, 21525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister cnt(VectorFormat vform, 21555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister not_(VectorFormat vform, 21585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rbit(VectorFormat vform, 21615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev(VectorFormat vform, 21645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int revSize); 21675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev16(VectorFormat vform, 21685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev32(VectorFormat vform, 21715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rev64(VectorFormat vform, 21745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addlp(VectorFormat vform, 21775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 21795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool is_signed, 21805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool do_accumulate); 21815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddlp(VectorFormat vform, 21825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddlp(VectorFormat vform, 21855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sadalp(VectorFormat vform, 21885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uadalp(VectorFormat vform, 21915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 21935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ext(VectorFormat vform, 21945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index); 21985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ins_element(VectorFormat vform, 21995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 22015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int src_index); 22035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ins_immediate(VectorFormat vform, 22045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 22065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 22075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dup_element(VectorFormat vform, 22085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int src_index); 22115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dup_immediate(VectorFormat vform, 22125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 22140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister movi(VectorFormat vform, LogicVRegister dst, uint64_t imm); 22150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister mvni(VectorFormat vform, LogicVRegister dst, uint64_t imm); 22165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister orr(VectorFormat vform, 22175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm); 22205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshl(VectorFormat vform, 22215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushl(VectorFormat vform, 22255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmax(VectorFormat vform, 22295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 22325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 22335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smax(VectorFormat vform, 22340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 22350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 22360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 22375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smin(VectorFormat vform, 22380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 22390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 22400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 22415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmaxp(VectorFormat vform, 22425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 2243b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& src1, 2244b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& src2, 22455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 22465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smaxp(VectorFormat vform, 22475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminp(VectorFormat vform, 22515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 22545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addp(VectorFormat vform, 22555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister addv(VectorFormat vform, 22585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddlv(VectorFormat vform, 22615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddlv(VectorFormat vform, 22645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminmaxv(VectorFormat vform, 22675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 22705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister smaxv(VectorFormat vform, 22715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sminv(VectorFormat vform, 22745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uxtl(VectorFormat vform, 22775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uxtl2(VectorFormat vform, 22805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sxtl(VectorFormat vform, 22835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sxtl2(VectorFormat vform, 22865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 22885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 22895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 22935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 22955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 22965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 22975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 22985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 23025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbl(VectorFormat vform, 23045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 23085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab4, 23095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 2310b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell LogicVRegister Table(VectorFormat vform, 2311b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell LogicVRegister dst, 2312b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& ind, 2313b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell bool zero_out_of_bounds, 2314b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister* tab1, 2315b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister* tab2 = NULL, 2316b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister* tab3 = NULL, 2317b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister* tab4 = NULL); 23185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 23195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 23235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 23285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 23325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister tbx(VectorFormat vform, 23345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 23365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 23375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 23385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab4, 23395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind); 23405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddl(VectorFormat vform, 23415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddl2(VectorFormat vform, 23455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddw(VectorFormat vform, 23495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaddw2(VectorFormat vform, 23535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddl(VectorFormat vform, 23575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddl2(VectorFormat vform, 23615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddw(VectorFormat vform, 23655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saddw2(VectorFormat vform, 23695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubl(VectorFormat vform, 23730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 23740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 23750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 23765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubl2(VectorFormat vform, 23775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubw(VectorFormat vform, 23815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usubw2(VectorFormat vform, 23855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubl(VectorFormat vform, 23895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubl2(VectorFormat vform, 23935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 23965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubw(VectorFormat vform, 23975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssubw2(VectorFormat vform, 24015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmax(VectorFormat vform, 24055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 24085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 24095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umax(VectorFormat vform, 24100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 24110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 24120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 24135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umin(VectorFormat vform, 24140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 24150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 24160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 24175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmaxp(VectorFormat vform, 24185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 2419b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& src1, 2420b953ea8255b36e27834f17941429cd17af12f6f2Martyn Capewell const LogicVRegister& src2, 24215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 24225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umaxp(VectorFormat vform, 24235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminp(VectorFormat vform, 24275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminmaxv(VectorFormat vform, 24315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max); 24345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister umaxv(VectorFormat vform, 24355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uminv(VectorFormat vform, 24385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister trn1(VectorFormat vform, 24415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister trn2(VectorFormat vform, 24455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister zip1(VectorFormat vform, 24495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister zip2(VectorFormat vform, 24535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uzp1(VectorFormat vform, 24575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uzp2(VectorFormat vform, 24615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 24635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 24645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shl(VectorFormat vform, 24655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister scvtf(VectorFormat vform, 24695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits, 24725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode); 24735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ucvtf(VectorFormat vform, 24745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits, 24775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode); 24785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshll(VectorFormat vform, 24795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshll2(VectorFormat vform, 24835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shll(VectorFormat vform, 24875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shll2(VectorFormat vform, 24905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 24925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushll(VectorFormat vform, 24935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 24965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushll2(VectorFormat vform, 24975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sli(VectorFormat vform, 25015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sri(VectorFormat vform, 25055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sshr(VectorFormat vform, 25095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ushr(VectorFormat vform, 25135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ssra(VectorFormat vform, 25175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usra(VectorFormat vform, 25215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister srsra(VectorFormat vform, 25255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ursra(VectorFormat vform, 25295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister suqadd(VectorFormat vform, 25330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 25340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 25355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister usqadd(VectorFormat vform, 25360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 25370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 25385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshl(VectorFormat vform, 25395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshl(VectorFormat vform, 25435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshlu(VectorFormat vform, 25475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister abs(VectorFormat vform, 25515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister neg(VectorFormat vform, 25545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister extractnarrow(VectorFormat vform, 25575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool dstIsSigned, 25595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool srcIsSigned); 25615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister xtn(VectorFormat vform, 25625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqxtn(VectorFormat vform, 25655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqxtn(VectorFormat vform, 25685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqxtun(VectorFormat vform, 25715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 25735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister absdiff(VectorFormat vform, 25745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 25775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool issigned); 25785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister saba(VectorFormat vform, 25795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uaba(VectorFormat vform, 25835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 25855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 25865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shrn(VectorFormat vform, 25875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shrn2(VectorFormat vform, 25910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 25920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src, 25930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int shift); 25945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rshrn(VectorFormat vform, 25955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 25985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister rshrn2(VectorFormat vform, 25995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshrn(VectorFormat vform, 26035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqshrn2(VectorFormat vform, 26075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqrshrn(VectorFormat vform, 26115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister uqrshrn2(VectorFormat vform, 26155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrn(VectorFormat vform, 26195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrn2(VectorFormat vform, 26235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrn(VectorFormat vform, 26275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrn2(VectorFormat vform, 26315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrun(VectorFormat vform, 26355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqshrun2(VectorFormat vform, 26395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrun(VectorFormat vform, 26435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrshrun2(VectorFormat vform, 26475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 26495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift); 26505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqrdmulh(VectorFormat vform, 26515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 26535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 26545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool round = true); 26555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister sqdmulh(VectorFormat vform, 26565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 26585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 26590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_3VREG_LOGIC_LIST(V) \ 26600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(addhn) \ 26610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(addhn2) \ 26620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(raddhn) \ 26630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(raddhn2) \ 26640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(subhn) \ 26650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(subhn2) \ 26660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(rsubhn) \ 26670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(rsubhn2) \ 26680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(pmull) \ 26690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(pmull2) \ 26700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabal) \ 26710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabal2) \ 26720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabal) \ 26730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabal2) \ 26740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabdl) \ 26750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sabdl2) \ 26760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabdl) \ 26770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(uabdl2) \ 26780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smull) \ 26790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smull2) \ 26800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umull) \ 26810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umull2) \ 26820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlal) \ 26830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlal2) \ 26840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlal) \ 26850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlal2) \ 26860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlsl) \ 26870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(smlsl2) \ 26880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlsl) \ 26890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(umlsl2) \ 26900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlal) \ 26910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlal2) \ 26920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlsl) \ 26930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmlsl2) \ 26940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmull) \ 26950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(sqdmull2) 26960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 26970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_LOGIC_FUNC(FXN) \ 26980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FXN(VectorFormat vform, \ 26990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 27025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_3VREG_LOGIC_LIST(DEFINE_LOGIC_FUNC) 27030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DEFINE_LOGIC_FUNC 27040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_FP3SAME_LIST(V) \ 27060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fadd, FPAdd, false) \ 27070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fsub, FPSub, true) \ 27080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmul, FPMul, true) \ 27090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmulx, FPMulx, true) \ 27100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fdiv, FPDiv, true) \ 27110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmax, FPMax, false) \ 27120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmin, FPMin, false) \ 27130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxnm, FPMaxNM, false) \ 27140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminnm, FPMinNM, false) 27150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DECLARE_NEON_FP_VECTOR_OP(FN, OP, PROCNAN) \ 27170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> \ 27180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FN(VectorFormat vform, \ 27190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); \ 27220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FN(VectorFormat vform, \ 27230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); 27265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_FP3SAME_LIST(DECLARE_NEON_FP_VECTOR_OP) 27270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE_NEON_FP_VECTOR_OP 27280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define NEON_FPPAIRWISE_LIST(V) \ 27300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(faddp, fadd, FPAdd) \ 27310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxp, fmax, FPMax) \ 27320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fmaxnmp, fmaxnm, FPMaxNM) \ 27330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminp, fmin, FPMin) \ 27340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl V(fminnmp, fminnm, FPMinNM) 27350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl 27360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DECLARE_NEON_FP_PAIR_OP(FNP, FN, OP) \ 27370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FNP(VectorFormat vform, \ 27380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 27400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2); \ 27410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister FNP(VectorFormat vform, \ 27420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 27430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src); 27445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl NEON_FPPAIRWISE_LIST(DECLARE_NEON_FP_PAIR_OP) 27450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#undef DECLARE_NEON_FP_PAIR_OP 27465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecps(VectorFormat vform, 27495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecps(VectorFormat vform, 27535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrts(VectorFormat vform, 27585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrts(VectorFormat vform, 27625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 27675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmla(VectorFormat vform, 27715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 27765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmls(VectorFormat vform, 27805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fnmul(VectorFormat vform, 27845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 27875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 27895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp(VectorFormat vform, 27905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 27935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 27945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp(VectorFormat vform, 27955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 27975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 27985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 27995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabscmp(VectorFormat vform, 28005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 28035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 28045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcmp_zero(VectorFormat vform, 28055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond); 28085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fneg(VectorFormat vform, 28115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fneg(VectorFormat vform, 28145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpx(VectorFormat vform, 28185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpx(VectorFormat vform, 28215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 28245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabs_(VectorFormat vform, 28255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabs_(VectorFormat vform, 28285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fabd(VectorFormat vform, 28315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2); 28345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frint(VectorFormat vform, 28355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 28385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool inexact_exception = false); 28395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvts(VectorFormat vform, 28405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 28435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits = 0); 28445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtu(VectorFormat vform, 28455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 28485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits = 0); 28495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtl(VectorFormat vform, 28505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtl2(VectorFormat vform, 28535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtn(VectorFormat vform, 28565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtn2(VectorFormat vform, 28595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtxn(VectorFormat vform, 28625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fcvtxn2(VectorFormat vform, 28655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fsqrt(VectorFormat vform, 28685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frsqrte(VectorFormat vform, 28715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister frecpe(VectorFormat vform, 28745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding); 28775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister ursqrte(VectorFormat vform, 28785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister urecpe(VectorFormat vform, 28815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl typedef float (Simulator::*FPMinMaxOp)(float a, float b); 28855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminmaxv(VectorFormat vform, 28875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPMinMaxOp Op); 28905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminv(VectorFormat vform, 28925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmaxv(VectorFormat vform, 28955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 28975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fminnmv(VectorFormat vform, 28985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister fmaxnmv(VectorFormat vform, 29015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src); 29035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static const uint32_t CRC32_POLY = 0x04C11DB7; 29055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl static const uint32_t CRC32C_POLY = 0x1EDC6F41; 29065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Poly32Mod2(unsigned n, uint64_t data, uint32_t poly); 29075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 29085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Crc32Checksum(uint32_t acc, T val, uint32_t poly); 29095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t Crc32Checksum(uint32_t acc, uint64_t val, uint32_t poly); 29105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl void SysOp_W(int op, int64_t val); 2912ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2913b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 29145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipSqrtEstimate(T op); 29155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 29165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipEstimate(T op, FPRounding rounding); 29175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T, typename R> 29185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl R FPToFixed(T op, int fbits, bool is_signed, FPRounding rounding); 2919b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 29206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl void FPCompare(double val0, double val1, FPTrapFlags trap); 2921ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl double FPRoundInt(double value, FPRounding round_mode); 2922578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double FPToDouble(float value); 2923578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float FPToFloat(double value, FPRounding round_mode); 29245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float FPToFloat(float16 value); 29255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float16 FPToFloat16(float value, FPRounding round_mode); 29265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float16 FPToFloat16(double value, FPRounding round_mode); 29275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double recip_sqrt_estimate(double a); 29285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double recip_estimate(double a); 29295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double FPRecipSqrtEstimate(double a); 29305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double FPRecipEstimate(double a); 2931578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double FixedToDouble(int64_t src, int fbits, FPRounding round_mode); 2932578645f14e122d2b87d907e298cda7e7d0babf1farmvixl double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode); 2933578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float FixedToFloat(int64_t src, int fbits, FPRounding round_mode); 2934578645f14e122d2b87d907e298cda7e7d0babf1farmvixl float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode); 2935ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int32_t FPToInt32(double value, FPRounding rmode); 2936ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl int64_t FPToInt64(double value, FPRounding rmode); 2937ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl uint32_t FPToUInt32(double value, FPRounding rmode); 2938ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl uint64_t FPToUInt64(double value, FPRounding rmode); 2939f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2940f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2941b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPAdd(T op1, T op2); 2942f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2943f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2944b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPDiv(T op1, T op2); 2945b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2946b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2947b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMax(T a, T b); 2948f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2949f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2950f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T FPMaxNM(T a, T b); 2951f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl 2952f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl template <typename T> 2953b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMin(T a, T b); 2954b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2955b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2956f37fdc0b307fc66239b8b754b0465d36bc0f8aedarmvixl T FPMinNM(T a, T b); 2957ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2958b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2959b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMul(T op1, T op2); 2960b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2961b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 29625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPMulx(T op1, T op2); 29635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 2965b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPMulAdd(T a, T op1, T op2); 2966b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2967b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2968b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPSqrt(T op); 2969b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2970b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl template <typename T> 2971b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl T FPSub(T op1, T op2); 2972b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 29735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 29745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRecipStepFused(T op1, T op2); 29755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl template <typename T> 29775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T FPRSqrtStepFused(T op1, T op2); 29785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 2979b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // This doesn't do anything at the moment. We'll need it if we want support 2980b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl // for cumulative exception bits or floating-point exceptions. 29810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl void FPProcessException() {} 2982b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2983c68cb64496485710cdb5b8480f8fee287058c93farmvixl bool FPProcessNaNs(const Instruction* instr); 2984b0c8ae2a5f0abc58f67322052d39bfd47edb2892armvixl 2985ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Pseudo Printf instruction 2986c68cb64496485710cdb5b8480f8fee287058c93farmvixl void DoPrintf(const Instruction* instr); 2987ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 2988064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Simulate a runtime call. 2989ca73ba046c11d65b6dce59cfd26847d14aba06abAlexandre Rames#ifndef VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT 2990064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames VIXL_NO_RETURN_IN_DEBUG_MODE 2991064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 2992064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames void DoRuntimeCall(const Instruction* instr); 2993064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 2994ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Processor state --------------------------------------- 2995ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 29964a102baf640077d6794c0b33bb976f94b86c532barmvixl // Simulated monitors for exclusive access instructions. 29974a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveLocalMonitor local_monitor_; 29984a102baf640077d6794c0b33bb976f94b86c532barmvixl SimExclusiveGlobalMonitor global_monitor_; 29994a102baf640077d6794c0b33bb976f94b86c532barmvixl 3000ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Output stream. 3001ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl FILE* stream_; 3002ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl PrintDisassembler* print_disasm_; 3003ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3004578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Instruction statistics instrumentation. 3005578645f14e122d2b87d907e298cda7e7d0babf1farmvixl Instrument* instrumentation_; 3006578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3007ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // General purpose registers. Register 31 is the stack pointer. 3008ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl SimRegister registers_[kNumberOfRegisters]; 3009ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Vector registers 30115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister vregisters_[kNumberOfVRegisters]; 3012ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3013ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Program Status Register. 3014ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // bits[31, 27]: Condition flags N, Z, C, and V. 3015ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // (Negative, Zero, Carry, Overflow) 3016578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister nzcv_; 3017578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3018578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Floating-Point Control Register 3019578645f14e122d2b87d907e298cda7e7d0babf1farmvixl SimSystemRegister fpcr_; 3020578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3021578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Only a subset of FPCR features are supported by the simulator. This helper 3022578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // checks that the FPCR settings are supported. 3023578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // 3024578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // This is checked when floating-point instructions are executed, not when 3025578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // FPCR is set. This allows generated code to modify FPCR for external 3026578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // functions, or to save and restore it when entering and leaving generated 3027578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // code. 3028578645f14e122d2b87d907e298cda7e7d0babf1farmvixl void AssertSupportedFPCR() { 302988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // No flush-to-zero support. 303088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(ReadFpcr().GetFZ() == 0); 303188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // Ties-to-even rounding only. 303288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois VIXL_ASSERT(ReadFpcr().GetRMode() == FPTieEven); 3033578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 303488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // The simulator does not support half-precision operations so 303588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois // GetFpcr().AHP() is irrelevant, and is not checked here. 3036578645f14e122d2b87d907e298cda7e7d0babf1farmvixl } 3037ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3038330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl static int CalcNFlag(uint64_t result, unsigned reg_size) { 3039578645f14e122d2b87d907e298cda7e7d0babf1farmvixl return (result >> (reg_size - 1)) & 1; 3040ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl } 3041ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 30420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl static int CalcZFlag(uint64_t result) { return (result == 0) ? 1 : 0; } 3043ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3044ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const uint32_t kConditionFlagsMask = 0xf0000000; 3045ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3046ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Stack 3047ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl byte* stack_; 3048ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const int stack_protection_size_ = 256; 3049ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // 2 KB stack. 3050ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const int stack_size_ = 2 * 1024 + 2 * stack_protection_size_; 3051ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl byte* stack_limit_; 3052ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3053ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl Decoder* decoder_; 3054ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // Indicates if the pc has been modified by the instruction and should not be 3055ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl // automatically incremented. 3056ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool pc_modified_; 3057c68cb64496485710cdb5b8480f8fee287058c93farmvixl const Instruction* pc_; 3058ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3059ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* xreg_names[]; 3060ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* wreg_names[]; 3061ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* sreg_names[]; 3062ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* dreg_names[]; 3063ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl static const char* vreg_names[]; 3064ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3065ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl private: 30666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 30676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl static T FPDefaultNaN(); 30686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 30696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Standard NaN processing. 30706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 30716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaN(T op) { 30726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(std::isnan(op)); 30736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op)) { 30746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPProcessException(); 30756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 307688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ReadDN() ? FPDefaultNaN<T>() : ToQuietNaN(op); 30776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 30796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 30806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaNs(T op1, T op2) { 30816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op1)) { 30826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 30836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op2)) { 30846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 30856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op1)) { 30866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op1)); 30876e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 30886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op2)) { 30896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op2)); 30906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 30916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 30926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0.0; 30936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 30966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl template <typename T> 30976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl T FPProcessNaNs3(T op1, T op2, T op3) { 30986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(op1)) { 30996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 31006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op2)) { 31016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 31026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (IsSignallingNaN(op3)) { 31036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op3); 31046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op1)) { 31056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op1)); 31066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op1); 31076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op2)) { 31086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op2)); 31096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op2); 31106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(op3)) { 31116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(IsQuietNaN(op3)); 31126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPProcessNaN(op3); 31136e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 31146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0.0; 31156e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 31166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 31176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3118ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl bool coloured_trace_; 3119578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3120330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl // A set of TraceParameters flags. 3121330dc7153e671968beb67f09ed2cb7b5bda334dbarmvixl int trace_parameters_; 3122578645f14e122d2b87d907e298cda7e7d0babf1farmvixl 3123578645f14e122d2b87d907e298cda7e7d0babf1farmvixl // Indicates whether the instruction instrumentation is active. 3124578645f14e122d2b87d907e298cda7e7d0babf1farmvixl bool instruction_stats_; 31254a102baf640077d6794c0b33bb976f94b86c532barmvixl 31264a102baf640077d6794c0b33bb976f94b86c532barmvixl // Indicates whether the exclusive-access warning has been printed. 31274a102baf640077d6794c0b33bb976f94b86c532barmvixl bool print_exclusive_access_warning_; 31284a102baf640077d6794c0b33bb976f94b86c532barmvixl void PrintExclusiveAccessWarning(); 3129ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl}; 3130064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 3131482d4df29d1466ff87d94e74034f1a8659f1b354Jacob Bramley#if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) && __cplusplus < 201402L 3132064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// Base case of the recursive template used to emulate C++14 3133064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames// `std::index_sequence`. 3134064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Ramestemplate <size_t... I> 3135064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Ramesstruct Simulator::emulated_make_index_sequence_helper<0, I...> 3136064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames : Simulator::emulated_index_sequence<I...> {}; 3137064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames#endif 3138064e02d4e85938b2e2be4d4b37a2691b2e015ebbAlexandre Rames 313988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois} // namespace aarch64 3140ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl} // namespace vixl 3141ad96eda8944ab1c1ba55715c50d9d6f0a3ed1dcarmvixl 3142a4055d25c688d1397fc369a40abf57fa4f1ab805Pierre Langlois#endif // VIXL_INCLUDE_SIMULATOR_AARCH64 3143a4055d25c688d1397fc369a40abf57fa4f1ab805Pierre Langlois 3144d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#endif // VIXL_AARCH64_SIMULATOR_AARCH64_H_ 3145