test-simulator-cond-rd-operand-rn-ror-amount-a32.cc revision 6a049f97861bd71c69d81f643e42308d28c5de31
1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28// ----------------------------------------------------------------------------- 29// This file is auto generated from the 30// test/aarch32/config/template-simulator-aarch32.cc.in template file using 31// tools/generate_tests.py. 32// 33// PLEASE DO NOT EDIT. 34// ----------------------------------------------------------------------------- 35 36 37#include "test-runner.h" 38 39#include "test-utils.h" 40#include "test-utils-aarch32.h" 41 42#include "aarch32/assembler-aarch32.h" 43#include "aarch32/macro-assembler-aarch32.h" 44#include "aarch32/disasm-aarch32.h" 45 46#define __ masm. 47#define BUF_SIZE (4096) 48 49#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32 50// Run tests with the simulator. 51 52#define SETUP() MacroAssembler masm(BUF_SIZE) 53 54#define START() masm.GetBuffer()->Reset() 55 56#define END() \ 57 __ Hlt(0); \ 58 __ FinalizeCode(); 59 60// TODO: Run the tests in the simulator. 61#define RUN() 62 63#define TEARDOWN() 64 65#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32. 66 67#define SETUP() MacroAssembler masm(BUF_SIZE); 68 69#define START() \ 70 masm.GetBuffer()->Reset(); \ 71 __ Push(r4); \ 72 __ Push(r5); \ 73 __ Push(r6); \ 74 __ Push(r7); \ 75 __ Push(r8); \ 76 __ Push(r9); \ 77 __ Push(r10); \ 78 __ Push(r11); \ 79 __ Push(r12); \ 80 __ Push(lr) 81 82#define END() \ 83 __ Pop(lr); \ 84 __ Pop(r12); \ 85 __ Pop(r11); \ 86 __ Pop(r10); \ 87 __ Pop(r9); \ 88 __ Pop(r8); \ 89 __ Pop(r7); \ 90 __ Pop(r6); \ 91 __ Pop(r5); \ 92 __ Pop(r4); \ 93 __ Bx(lr); \ 94 __ FinalizeCode(); 95 96#define RUN() \ 97 { \ 98 int pcs_offset = masm.IsUsingT32() ? 1 : 0; \ 99 masm.GetBuffer()->SetExecutable(); \ 100 ExecuteMemory(masm.GetBuffer()->GetStartAddress<byte*>(), \ 101 masm.GetSizeOfCodeGenerated(), \ 102 pcs_offset); \ 103 masm.GetBuffer()->SetWritable(); \ 104 } 105 106#define TEARDOWN() 107 108#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32 109 110namespace vixl { 111namespace aarch32 { 112 113// List of instruction encodings: 114#define FOREACH_INSTRUCTION(M) \ 115 M(Sxtb) \ 116 M(Sxtb16) \ 117 M(Sxth) \ 118 M(Uxtb) \ 119 M(Uxtb16) \ 120 M(Uxth) 121 122 123// Values to be passed to the assembler to produce the instruction under test. 124struct Operands { 125 Condition cond; 126 Register rd; 127 Register rn; 128 ShiftType ror; 129 uint32_t amount; 130}; 131 132// Input data to feed to the instruction. 133struct Inputs { 134 uint32_t apsr; 135 uint32_t rd; 136 uint32_t rn; 137}; 138 139// This structure contains all input data needed to test one specific encoding. 140// It used to generate a loop over an instruction. 141struct TestLoopData { 142 // The `operands` fields represents the values to pass to the assembler to 143 // produce the instruction. 144 Operands operands; 145 // Description of the operands, used for error reporting. 146 const char* operands_description; 147 // Unique identifier, used for generating traces. 148 const char* identifier; 149 // Array of values to be fed to the instruction. 150 size_t input_size; 151 const Inputs* inputs; 152}; 153 154static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab}, 155 {ZFlag, 0xabababab, 0xabababab}, 156 {CFlag, 0xabababab, 0xabababab}, 157 {VFlag, 0xabababab, 0xabababab}, 158 {NZFlag, 0xabababab, 0xabababab}, 159 {NCFlag, 0xabababab, 0xabababab}, 160 {NVFlag, 0xabababab, 0xabababab}, 161 {ZCFlag, 0xabababab, 0xabababab}, 162 {ZVFlag, 0xabababab, 0xabababab}, 163 {CVFlag, 0xabababab, 0xabababab}, 164 {NZCFlag, 0xabababab, 0xabababab}, 165 {NZVFlag, 0xabababab, 0xabababab}, 166 {NCVFlag, 0xabababab, 0xabababab}, 167 {ZCVFlag, 0xabababab, 0xabababab}, 168 {NZCVFlag, 0xabababab, 0xabababab}}; 169 170static const Inputs kRdIsRn[] = {{NoFlag, 0x00000000, 0x00000000}, 171 {NoFlag, 0x00000001, 0x00000001}, 172 {NoFlag, 0x00000002, 0x00000002}, 173 {NoFlag, 0x00000020, 0x00000020}, 174 {NoFlag, 0x0000007d, 0x0000007d}, 175 {NoFlag, 0x0000007e, 0x0000007e}, 176 {NoFlag, 0x0000007f, 0x0000007f}, 177 {NoFlag, 0x00007ffd, 0x00007ffd}, 178 {NoFlag, 0x00007ffe, 0x00007ffe}, 179 {NoFlag, 0x00007fff, 0x00007fff}, 180 {NoFlag, 0x33333333, 0x33333333}, 181 {NoFlag, 0x55555555, 0x55555555}, 182 {NoFlag, 0x7ffffffd, 0x7ffffffd}, 183 {NoFlag, 0x7ffffffe, 0x7ffffffe}, 184 {NoFlag, 0x7fffffff, 0x7fffffff}, 185 {NoFlag, 0x80000000, 0x80000000}, 186 {NoFlag, 0x80000001, 0x80000001}, 187 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 188 {NoFlag, 0xcccccccc, 0xcccccccc}, 189 {NoFlag, 0xffff8000, 0xffff8000}, 190 {NoFlag, 0xffff8001, 0xffff8001}, 191 {NoFlag, 0xffff8002, 0xffff8002}, 192 {NoFlag, 0xffff8003, 0xffff8003}, 193 {NoFlag, 0xffffff80, 0xffffff80}, 194 {NoFlag, 0xffffff81, 0xffffff81}, 195 {NoFlag, 0xffffff82, 0xffffff82}, 196 {NoFlag, 0xffffff83, 0xffffff83}, 197 {NoFlag, 0xffffffe0, 0xffffffe0}, 198 {NoFlag, 0xfffffffd, 0xfffffffd}, 199 {NoFlag, 0xfffffffe, 0xfffffffe}, 200 {NoFlag, 0xffffffff, 0xffffffff}}; 201 202static const Inputs kRdIsNotRn[] = {{NoFlag, 0x00000002, 0xcccccccc}, 203 {NoFlag, 0x7ffffffd, 0x00007ffe}, 204 {NoFlag, 0xffffff80, 0x00000020}, 205 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 206 {NoFlag, 0x33333333, 0xffffff82}, 207 {NoFlag, 0xffff8001, 0x7ffffffe}, 208 {NoFlag, 0xfffffffd, 0x00007ffe}, 209 {NoFlag, 0xffffff80, 0x80000000}, 210 {NoFlag, 0x00000001, 0x33333333}, 211 {NoFlag, 0xcccccccc, 0x7ffffffe}, 212 {NoFlag, 0x00000000, 0xcccccccc}, 213 {NoFlag, 0x00000000, 0x55555555}, 214 {NoFlag, 0xffffffff, 0xffffffff}, 215 {NoFlag, 0x0000007e, 0xffff8002}, 216 {NoFlag, 0x80000000, 0x7ffffffd}, 217 {NoFlag, 0xffffff81, 0x0000007e}, 218 {NoFlag, 0x0000007f, 0xffff8001}, 219 {NoFlag, 0xffffffe0, 0x00007ffd}, 220 {NoFlag, 0xffff8003, 0x00000002}, 221 {NoFlag, 0xffffff83, 0x55555555}, 222 {NoFlag, 0xffffff83, 0xffffff80}, 223 {NoFlag, 0xffffff81, 0xffff8000}, 224 {NoFlag, 0x00000020, 0x7ffffffe}, 225 {NoFlag, 0xffffffe0, 0x00000000}, 226 {NoFlag, 0x7fffffff, 0x0000007e}, 227 {NoFlag, 0x80000001, 0xffffffff}, 228 {NoFlag, 0x00000001, 0x80000001}, 229 {NoFlag, 0x00000002, 0x0000007f}, 230 {NoFlag, 0x7fffffff, 0xcccccccc}, 231 {NoFlag, 0x80000001, 0x00007ffe}, 232 {NoFlag, 0xffff8002, 0x0000007e}, 233 {NoFlag, 0x00007ffe, 0xcccccccc}, 234 {NoFlag, 0x80000000, 0xffff8002}, 235 {NoFlag, 0xffffff83, 0x7ffffffe}, 236 {NoFlag, 0xffff8001, 0x00000001}, 237 {NoFlag, 0xffffff81, 0x00000020}, 238 {NoFlag, 0xfffffffe, 0xffff8001}, 239 {NoFlag, 0xffffffff, 0xfffffffe}, 240 {NoFlag, 0xcccccccc, 0x55555555}, 241 {NoFlag, 0x00000020, 0xffffff83}, 242 {NoFlag, 0xffffff83, 0xffff8001}, 243 {NoFlag, 0xffffff83, 0xffff8000}, 244 {NoFlag, 0x00007fff, 0x00000002}, 245 {NoFlag, 0x55555555, 0xffff8000}, 246 {NoFlag, 0x80000001, 0xffffff81}, 247 {NoFlag, 0x00000002, 0x00000000}, 248 {NoFlag, 0x33333333, 0xffffff81}, 249 {NoFlag, 0xffff8001, 0xffffff82}, 250 {NoFlag, 0xcccccccc, 0xffff8003}, 251 {NoFlag, 0xffff8003, 0x7ffffffd}, 252 {NoFlag, 0x0000007d, 0x00007ffe}, 253 {NoFlag, 0xffffff80, 0x0000007d}, 254 {NoFlag, 0xaaaaaaaa, 0x00007ffd}, 255 {NoFlag, 0x80000000, 0xffffff82}, 256 {NoFlag, 0x00000002, 0x7ffffffe}, 257 {NoFlag, 0x00000002, 0xffffff83}, 258 {NoFlag, 0x55555555, 0x00000002}, 259 {NoFlag, 0xffffffff, 0xffffff82}, 260 {NoFlag, 0xaaaaaaaa, 0x00000020}, 261 {NoFlag, 0x00000001, 0xffffff82}, 262 {NoFlag, 0x0000007f, 0xffffff82}, 263 {NoFlag, 0x7ffffffd, 0xaaaaaaaa}, 264 {NoFlag, 0x00007ffe, 0x00000001}, 265 {NoFlag, 0xfffffffd, 0xffffffe0}, 266 {NoFlag, 0xffffff81, 0xffffff83}, 267 {NoFlag, 0x0000007d, 0x00000000}, 268 {NoFlag, 0x0000007d, 0xffff8000}, 269 {NoFlag, 0xffffff81, 0x7fffffff}, 270 {NoFlag, 0xffffffff, 0x80000000}, 271 {NoFlag, 0x00000000, 0x00000001}, 272 {NoFlag, 0x55555555, 0xffffff82}, 273 {NoFlag, 0x00007ffe, 0x00007ffe}, 274 {NoFlag, 0x80000001, 0xfffffffd}, 275 {NoFlag, 0x00007fff, 0x33333333}, 276 {NoFlag, 0x00007fff, 0x80000000}, 277 {NoFlag, 0xcccccccc, 0x00007fff}, 278 {NoFlag, 0xfffffffe, 0xffffffe0}, 279 {NoFlag, 0x7ffffffe, 0x0000007f}, 280 {NoFlag, 0x00007ffd, 0xffff8001}, 281 {NoFlag, 0x00000002, 0x00000001}, 282 {NoFlag, 0x80000000, 0xffffffff}, 283 {NoFlag, 0xffffff83, 0xcccccccc}, 284 {NoFlag, 0xffff8002, 0x7ffffffe}, 285 {NoFlag, 0xaaaaaaaa, 0x00000000}, 286 {NoFlag, 0xffffff80, 0xcccccccc}, 287 {NoFlag, 0x33333333, 0xffffff83}, 288 {NoFlag, 0x0000007e, 0xffffffe0}, 289 {NoFlag, 0x0000007e, 0x00007fff}, 290 {NoFlag, 0x0000007f, 0x00000002}, 291 {NoFlag, 0x7ffffffe, 0xcccccccc}, 292 {NoFlag, 0x0000007d, 0xffffff80}, 293 {NoFlag, 0x00007fff, 0x00000020}, 294 {NoFlag, 0x7ffffffe, 0xfffffffe}, 295 {NoFlag, 0xfffffffe, 0xffffff81}, 296 {NoFlag, 0xffffffff, 0x0000007f}, 297 {NoFlag, 0xffff8002, 0x7ffffffd}, 298 {NoFlag, 0xffff8001, 0xfffffffe}, 299 {NoFlag, 0x33333333, 0xffff8002}, 300 {NoFlag, 0x00000000, 0xffffffff}, 301 {NoFlag, 0x33333333, 0xffffff80}, 302 {NoFlag, 0x0000007f, 0x00007fff}, 303 {NoFlag, 0xffffffff, 0xffff8001}, 304 {NoFlag, 0x7fffffff, 0xffff8002}, 305 {NoFlag, 0x7ffffffd, 0xffffff83}, 306 {NoFlag, 0x7fffffff, 0x0000007f}, 307 {NoFlag, 0xffffff83, 0xfffffffe}, 308 {NoFlag, 0x7ffffffe, 0xffff8003}, 309 {NoFlag, 0xffff8002, 0xffff8002}, 310 {NoFlag, 0x80000001, 0x0000007f}, 311 {NoFlag, 0x00000020, 0x00000002}, 312 {NoFlag, 0xffffff82, 0xffff8001}, 313 {NoFlag, 0xffffffff, 0x00000001}, 314 {NoFlag, 0xffffff80, 0xffff8002}, 315 {NoFlag, 0xffff8003, 0x7fffffff}, 316 {NoFlag, 0xffffffff, 0xffff8000}, 317 {NoFlag, 0xffff8002, 0x00007ffd}, 318 {NoFlag, 0x00000020, 0xffffff81}, 319 {NoFlag, 0x00000001, 0x55555555}, 320 {NoFlag, 0x7ffffffe, 0x00000020}, 321 {NoFlag, 0x80000000, 0x00000001}, 322 {NoFlag, 0x00007ffd, 0xffff8002}, 323 {NoFlag, 0x7fffffff, 0xfffffffe}, 324 {NoFlag, 0xcccccccc, 0x00007ffd}, 325 {NoFlag, 0x00000000, 0xfffffffd}, 326 {NoFlag, 0xffff8003, 0xffffff80}, 327 {NoFlag, 0x80000001, 0xffffff80}, 328 {NoFlag, 0xffffffff, 0xffff8002}, 329 {NoFlag, 0x00007ffe, 0xffff8002}, 330 {NoFlag, 0xffffff80, 0x00007ffe}, 331 {NoFlag, 0x80000001, 0xffff8001}, 332 {NoFlag, 0x0000007f, 0xffffff80}, 333 {NoFlag, 0xffffff81, 0x80000000}, 334 {NoFlag, 0x00007fff, 0x00007ffe}, 335 {NoFlag, 0x33333333, 0xffff8000}, 336 {NoFlag, 0x33333333, 0x00007fff}, 337 {NoFlag, 0x00000000, 0x0000007d}, 338 {NoFlag, 0x80000001, 0x00000000}, 339 {NoFlag, 0xffffffff, 0x55555555}, 340 {NoFlag, 0x80000001, 0x80000000}, 341 {NoFlag, 0xffffffff, 0xffffff80}, 342 {NoFlag, 0xffffff81, 0xffff8003}, 343 {NoFlag, 0x55555555, 0x80000001}, 344 {NoFlag, 0x7fffffff, 0xffff8001}, 345 {NoFlag, 0xffffff83, 0x00000002}, 346 {NoFlag, 0x0000007e, 0xffffff81}, 347 {NoFlag, 0x80000000, 0xffff8001}, 348 {NoFlag, 0xffffff80, 0xfffffffe}, 349 {NoFlag, 0x0000007e, 0xfffffffd}, 350 {NoFlag, 0xffffffe0, 0xffffffff}, 351 {NoFlag, 0x55555555, 0x80000000}, 352 {NoFlag, 0x0000007d, 0x80000001}, 353 {NoFlag, 0xffffffe0, 0x7ffffffd}, 354 {NoFlag, 0x00000000, 0x00000000}, 355 {NoFlag, 0x55555555, 0x00000001}, 356 {NoFlag, 0x00007ffd, 0x7fffffff}, 357 {NoFlag, 0x55555555, 0xffffffff}, 358 {NoFlag, 0xffff8003, 0x00007fff}, 359 {NoFlag, 0xffffff82, 0x00007fff}, 360 {NoFlag, 0x33333333, 0x55555555}, 361 {NoFlag, 0x00000020, 0x33333333}, 362 {NoFlag, 0x7ffffffe, 0xfffffffd}, 363 {NoFlag, 0x7ffffffe, 0x00000001}, 364 {NoFlag, 0xffffff83, 0xffffffe0}, 365 {NoFlag, 0xfffffffe, 0xaaaaaaaa}, 366 {NoFlag, 0xffff8002, 0x33333333}, 367 {NoFlag, 0xffff8002, 0xffff8003}, 368 {NoFlag, 0x33333333, 0x7fffffff}, 369 {NoFlag, 0xfffffffd, 0xffffff83}, 370 {NoFlag, 0x00000000, 0xffff8000}, 371 {NoFlag, 0xffffff82, 0x55555555}, 372 {NoFlag, 0xffffff82, 0xffffff81}, 373 {NoFlag, 0xcccccccc, 0xfffffffe}, 374 {NoFlag, 0xfffffffd, 0x7fffffff}, 375 {NoFlag, 0x00007fff, 0x7fffffff}, 376 {NoFlag, 0xffffff83, 0xffff8003}, 377 {NoFlag, 0xfffffffe, 0xffffffff}, 378 {NoFlag, 0x7ffffffd, 0x00007ffd}, 379 {NoFlag, 0x7ffffffd, 0x00007fff}, 380 {NoFlag, 0x00007ffd, 0xffffffff}, 381 {NoFlag, 0x00000001, 0xffff8003}, 382 {NoFlag, 0xffffff80, 0xfffffffd}, 383 {NoFlag, 0x33333333, 0x80000000}, 384 {NoFlag, 0xffff8001, 0x00000020}, 385 {NoFlag, 0xcccccccc, 0x00000002}, 386 {NoFlag, 0x00000000, 0x00000002}, 387 {NoFlag, 0x0000007d, 0x00007fff}, 388 {NoFlag, 0xcccccccc, 0x00000001}, 389 {NoFlag, 0xffffff83, 0x00007fff}, 390 {NoFlag, 0x80000001, 0x00000020}, 391 {NoFlag, 0xffff8003, 0xffffffe0}, 392 {NoFlag, 0x00007ffd, 0xaaaaaaaa}, 393 {NoFlag, 0x33333333, 0xffff8001}, 394 {NoFlag, 0xffffff83, 0x80000001}, 395 {NoFlag, 0xffff8000, 0xffff8000}, 396 {NoFlag, 0x00007ffe, 0xffff8001}, 397 {NoFlag, 0x7ffffffd, 0x00000000}, 398 {NoFlag, 0x00007ffe, 0x33333333}, 399 {NoFlag, 0xffff8001, 0xffffff80}, 400 {NoFlag, 0xfffffffe, 0x55555555}, 401 {NoFlag, 0xffffff82, 0xffffffff}}; 402 403static const Inputs kRotations[] = {{NoFlag, 0xabababab, 0x00000000}, 404 {NoFlag, 0xabababab, 0x00000001}, 405 {NoFlag, 0xabababab, 0x00000002}, 406 {NoFlag, 0xabababab, 0x00000020}, 407 {NoFlag, 0xabababab, 0x0000007d}, 408 {NoFlag, 0xabababab, 0x0000007e}, 409 {NoFlag, 0xabababab, 0x0000007f}, 410 {NoFlag, 0xabababab, 0x00007ffd}, 411 {NoFlag, 0xabababab, 0x00007ffe}, 412 {NoFlag, 0xabababab, 0x00007fff}, 413 {NoFlag, 0xabababab, 0x33333333}, 414 {NoFlag, 0xabababab, 0x55555555}, 415 {NoFlag, 0xabababab, 0x7ffffffd}, 416 {NoFlag, 0xabababab, 0x7ffffffe}, 417 {NoFlag, 0xabababab, 0x7fffffff}, 418 {NoFlag, 0xabababab, 0x80000000}, 419 {NoFlag, 0xabababab, 0x80000001}, 420 {NoFlag, 0xabababab, 0xaaaaaaaa}, 421 {NoFlag, 0xabababab, 0xcccccccc}, 422 {NoFlag, 0xabababab, 0xffff8000}, 423 {NoFlag, 0xabababab, 0xffff8001}, 424 {NoFlag, 0xabababab, 0xffff8002}, 425 {NoFlag, 0xabababab, 0xffff8003}, 426 {NoFlag, 0xabababab, 0xffffff80}, 427 {NoFlag, 0xabababab, 0xffffff81}, 428 {NoFlag, 0xabababab, 0xffffff82}, 429 {NoFlag, 0xabababab, 0xffffff83}, 430 {NoFlag, 0xabababab, 0xffffffe0}, 431 {NoFlag, 0xabababab, 0xfffffffd}, 432 {NoFlag, 0xabababab, 0xfffffffe}, 433 {NoFlag, 0xabababab, 0xffffffff}}; 434 435 436// A loop will be generated for each element of this array. 437static const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0}, 438 "eq r0 r0 ROR 0", 439 "Condition_eq_r0_r0_ROR_0", 440 ARRAY_SIZE(kCondition), 441 kCondition}, 442 {{ne, r0, r0, ROR, 0}, 443 "ne r0 r0 ROR 0", 444 "Condition_ne_r0_r0_ROR_0", 445 ARRAY_SIZE(kCondition), 446 kCondition}, 447 {{cs, r0, r0, ROR, 0}, 448 "cs r0 r0 ROR 0", 449 "Condition_cs_r0_r0_ROR_0", 450 ARRAY_SIZE(kCondition), 451 kCondition}, 452 {{cc, r0, r0, ROR, 0}, 453 "cc r0 r0 ROR 0", 454 "Condition_cc_r0_r0_ROR_0", 455 ARRAY_SIZE(kCondition), 456 kCondition}, 457 {{mi, r0, r0, ROR, 0}, 458 "mi r0 r0 ROR 0", 459 "Condition_mi_r0_r0_ROR_0", 460 ARRAY_SIZE(kCondition), 461 kCondition}, 462 {{pl, r0, r0, ROR, 0}, 463 "pl r0 r0 ROR 0", 464 "Condition_pl_r0_r0_ROR_0", 465 ARRAY_SIZE(kCondition), 466 kCondition}, 467 {{vs, r0, r0, ROR, 0}, 468 "vs r0 r0 ROR 0", 469 "Condition_vs_r0_r0_ROR_0", 470 ARRAY_SIZE(kCondition), 471 kCondition}, 472 {{vc, r0, r0, ROR, 0}, 473 "vc r0 r0 ROR 0", 474 "Condition_vc_r0_r0_ROR_0", 475 ARRAY_SIZE(kCondition), 476 kCondition}, 477 {{hi, r0, r0, ROR, 0}, 478 "hi r0 r0 ROR 0", 479 "Condition_hi_r0_r0_ROR_0", 480 ARRAY_SIZE(kCondition), 481 kCondition}, 482 {{ls, r0, r0, ROR, 0}, 483 "ls r0 r0 ROR 0", 484 "Condition_ls_r0_r0_ROR_0", 485 ARRAY_SIZE(kCondition), 486 kCondition}, 487 {{ge, r0, r0, ROR, 0}, 488 "ge r0 r0 ROR 0", 489 "Condition_ge_r0_r0_ROR_0", 490 ARRAY_SIZE(kCondition), 491 kCondition}, 492 {{lt, r0, r0, ROR, 0}, 493 "lt r0 r0 ROR 0", 494 "Condition_lt_r0_r0_ROR_0", 495 ARRAY_SIZE(kCondition), 496 kCondition}, 497 {{gt, r0, r0, ROR, 0}, 498 "gt r0 r0 ROR 0", 499 "Condition_gt_r0_r0_ROR_0", 500 ARRAY_SIZE(kCondition), 501 kCondition}, 502 {{le, r0, r0, ROR, 0}, 503 "le r0 r0 ROR 0", 504 "Condition_le_r0_r0_ROR_0", 505 ARRAY_SIZE(kCondition), 506 kCondition}, 507 {{al, r0, r0, ROR, 0}, 508 "al r0 r0 ROR 0", 509 "Condition_al_r0_r0_ROR_0", 510 ARRAY_SIZE(kCondition), 511 kCondition}, 512 {{al, r0, r0, ROR, 0}, 513 "al r0 r0 ROR 0", 514 "RdIsRn_al_r0_r0_ROR_0", 515 ARRAY_SIZE(kRdIsRn), 516 kRdIsRn}, 517 {{al, r1, r1, ROR, 0}, 518 "al r1 r1 ROR 0", 519 "RdIsRn_al_r1_r1_ROR_0", 520 ARRAY_SIZE(kRdIsRn), 521 kRdIsRn}, 522 {{al, r2, r2, ROR, 0}, 523 "al r2 r2 ROR 0", 524 "RdIsRn_al_r2_r2_ROR_0", 525 ARRAY_SIZE(kRdIsRn), 526 kRdIsRn}, 527 {{al, r3, r3, ROR, 0}, 528 "al r3 r3 ROR 0", 529 "RdIsRn_al_r3_r3_ROR_0", 530 ARRAY_SIZE(kRdIsRn), 531 kRdIsRn}, 532 {{al, r4, r4, ROR, 0}, 533 "al r4 r4 ROR 0", 534 "RdIsRn_al_r4_r4_ROR_0", 535 ARRAY_SIZE(kRdIsRn), 536 kRdIsRn}, 537 {{al, r5, r5, ROR, 0}, 538 "al r5 r5 ROR 0", 539 "RdIsRn_al_r5_r5_ROR_0", 540 ARRAY_SIZE(kRdIsRn), 541 kRdIsRn}, 542 {{al, r6, r6, ROR, 0}, 543 "al r6 r6 ROR 0", 544 "RdIsRn_al_r6_r6_ROR_0", 545 ARRAY_SIZE(kRdIsRn), 546 kRdIsRn}, 547 {{al, r7, r7, ROR, 0}, 548 "al r7 r7 ROR 0", 549 "RdIsRn_al_r7_r7_ROR_0", 550 ARRAY_SIZE(kRdIsRn), 551 kRdIsRn}, 552 {{al, r8, r8, ROR, 0}, 553 "al r8 r8 ROR 0", 554 "RdIsRn_al_r8_r8_ROR_0", 555 ARRAY_SIZE(kRdIsRn), 556 kRdIsRn}, 557 {{al, r9, r9, ROR, 0}, 558 "al r9 r9 ROR 0", 559 "RdIsRn_al_r9_r9_ROR_0", 560 ARRAY_SIZE(kRdIsRn), 561 kRdIsRn}, 562 {{al, r10, r10, ROR, 0}, 563 "al r10 r10 ROR 0", 564 "RdIsRn_al_r10_r10_ROR_0", 565 ARRAY_SIZE(kRdIsRn), 566 kRdIsRn}, 567 {{al, r11, r11, ROR, 0}, 568 "al r11 r11 ROR 0", 569 "RdIsRn_al_r11_r11_ROR_0", 570 ARRAY_SIZE(kRdIsRn), 571 kRdIsRn}, 572 {{al, r12, r12, ROR, 0}, 573 "al r12 r12 ROR 0", 574 "RdIsRn_al_r12_r12_ROR_0", 575 ARRAY_SIZE(kRdIsRn), 576 kRdIsRn}, 577 {{al, r14, r14, ROR, 0}, 578 "al r14 r14 ROR 0", 579 "RdIsRn_al_r14_r14_ROR_0", 580 ARRAY_SIZE(kRdIsRn), 581 kRdIsRn}, 582 {{al, r1, r8, ROR, 0}, 583 "al r1 r8 ROR 0", 584 "RdIsNotRn_al_r1_r8_ROR_0", 585 ARRAY_SIZE(kRdIsNotRn), 586 kRdIsNotRn}, 587 {{al, r7, r4, ROR, 0}, 588 "al r7 r4 ROR 0", 589 "RdIsNotRn_al_r7_r4_ROR_0", 590 ARRAY_SIZE(kRdIsNotRn), 591 kRdIsNotRn}, 592 {{al, r14, r10, ROR, 0}, 593 "al r14 r10 ROR 0", 594 "RdIsNotRn_al_r14_r10_ROR_0", 595 ARRAY_SIZE(kRdIsNotRn), 596 kRdIsNotRn}, 597 {{al, r10, r6, ROR, 0}, 598 "al r10 r6 ROR 0", 599 "RdIsNotRn_al_r10_r6_ROR_0", 600 ARRAY_SIZE(kRdIsNotRn), 601 kRdIsNotRn}, 602 {{al, r6, r5, ROR, 0}, 603 "al r6 r5 ROR 0", 604 "RdIsNotRn_al_r6_r5_ROR_0", 605 ARRAY_SIZE(kRdIsNotRn), 606 kRdIsNotRn}, 607 {{al, r12, r2, ROR, 0}, 608 "al r12 r2 ROR 0", 609 "RdIsNotRn_al_r12_r2_ROR_0", 610 ARRAY_SIZE(kRdIsNotRn), 611 kRdIsNotRn}, 612 {{al, r0, r11, ROR, 0}, 613 "al r0 r11 ROR 0", 614 "RdIsNotRn_al_r0_r11_ROR_0", 615 ARRAY_SIZE(kRdIsNotRn), 616 kRdIsNotRn}, 617 {{al, r10, r14, ROR, 0}, 618 "al r10 r14 ROR 0", 619 "RdIsNotRn_al_r10_r14_ROR_0", 620 ARRAY_SIZE(kRdIsNotRn), 621 kRdIsNotRn}, 622 {{al, r0, r5, ROR, 0}, 623 "al r0 r5 ROR 0", 624 "RdIsNotRn_al_r0_r5_ROR_0", 625 ARRAY_SIZE(kRdIsNotRn), 626 kRdIsNotRn}, 627 {{al, r0, r3, ROR, 0}, 628 "al r0 r3 ROR 0", 629 "RdIsNotRn_al_r0_r3_ROR_0", 630 ARRAY_SIZE(kRdIsNotRn), 631 kRdIsNotRn}, 632 {{al, r0, r1, ROR, 0}, 633 "al r0 r1 ROR 0", 634 "Rotations_al_r0_r1_ROR_0", 635 ARRAY_SIZE(kRotations), 636 kRotations}, 637 {{al, r0, r1, ROR, 8}, 638 "al r0 r1 ROR 8", 639 "Rotations_al_r0_r1_ROR_8", 640 ARRAY_SIZE(kRotations), 641 kRotations}, 642 {{al, r0, r1, ROR, 16}, 643 "al r0 r1 ROR 16", 644 "Rotations_al_r0_r1_ROR_16", 645 ARRAY_SIZE(kRotations), 646 kRotations}, 647 {{al, r0, r1, ROR, 24}, 648 "al r0 r1 ROR 24", 649 "Rotations_al_r0_r1_ROR_24", 650 ARRAY_SIZE(kRotations), 651 kRotations}}; 652 653// We record all inputs to the instructions as outputs. This way, we also check 654// that what shouldn't change didn't change. 655struct TestResult { 656 size_t output_size; 657 const Inputs* outputs; 658}; 659 660// These headers each contain an array of `TestResult` with the reference output 661// values. The reference arrays are names `kReference{mnemonic}`. 662#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h" 663#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h" 664#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h" 665#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h" 666#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h" 667#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h" 668 669 670// The maximum number of errors to report in detail for each test. 671static const unsigned kErrorReportLimit = 8; 672 673typedef void (MacroAssembler::*Fn)(Condition cond, 674 Register rd, 675 const Operand& op); 676 677static void TestHelper(Fn instruction, 678 const char* mnemonic, 679 const TestResult reference[]) { 680 SETUP(); 681 masm.UseA32(); 682 START(); 683 684 // Data to compare to `reference`. 685 TestResult* results[ARRAY_SIZE(kTests)]; 686 687 // Test cases for memory bound instructions may allocate a buffer and save its 688 // address in this array. 689 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)]; 690 691 // Generate a loop for each element in `kTests`. Each loop tests one specific 692 // instruction. 693 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 694 // Allocate results on the heap for this test. 695 results[i] = new TestResult; 696 results[i]->outputs = new Inputs[kTests[i].input_size]; 697 results[i]->output_size = kTests[i].input_size; 698 699 size_t input_stride = sizeof(kTests[i].inputs[0]) * kTests[i].input_size; 700 VIXL_ASSERT(IsUint32(input_stride)); 701 702 scratch_memory_buffers[i] = NULL; 703 704 Label loop; 705 UseScratchRegisterScope scratch_registers(&masm); 706 // Include all registers from r0 ro r12. 707 scratch_registers.Include(RegisterList(0x1fff)); 708 709 // Values to pass to the macro-assembler. 710 Condition cond = kTests[i].operands.cond; 711 Register rd = kTests[i].operands.rd; 712 Register rn = kTests[i].operands.rn; 713 ShiftType ror = kTests[i].operands.ror; 714 uint32_t amount = kTests[i].operands.amount; 715 Operand op(rn, ror, amount); 716 scratch_registers.Exclude(rd); 717 scratch_registers.Exclude(rn); 718 719 // Allocate reserved registers for our own use. 720 Register input_ptr = scratch_registers.Acquire(); 721 Register input_end = scratch_registers.Acquire(); 722 Register result_ptr = scratch_registers.Acquire(); 723 724 // Initialize `input_ptr` to the first element and `input_end` the address 725 // after the array. 726 __ Mov(input_ptr, Operand::From(kTests[i].inputs)); 727 __ Add(input_end, input_ptr, static_cast<uint32_t>(input_stride)); 728 __ Mov(result_ptr, Operand::From(results[i]->outputs)); 729 __ Bind(&loop); 730 731 { 732 UseScratchRegisterScope temp_registers(&masm); 733 Register nzcv_bits = temp_registers.Acquire(); 734 Register saved_q_bit = temp_registers.Acquire(); 735 // Save the `Q` bit flag. 736 __ Mrs(saved_q_bit, APSR); 737 __ And(saved_q_bit, saved_q_bit, QFlag); 738 // Set the `NZCV` and `Q` flags together. 739 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr))); 740 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); 741 __ Msr(APSR_nzcvq, nzcv_bits); 742 } 743 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd))); 744 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn))); 745 746 (masm.*instruction)(cond, rd, op); 747 748 { 749 UseScratchRegisterScope temp_registers(&masm); 750 Register nzcv_bits = temp_registers.Acquire(); 751 __ Mrs(nzcv_bits, APSR); 752 // Only record the NZCV bits. 753 __ And(nzcv_bits, nzcv_bits, NZCVFlag); 754 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr))); 755 } 756 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd))); 757 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn))); 758 759 // Advance the result pointer. 760 __ Add(result_ptr, result_ptr, Operand::From(sizeof(kTests[i].inputs[0]))); 761 // Loop back until `input_ptr` is lower than `input_base`. 762 __ Add(input_ptr, input_ptr, Operand::From(sizeof(kTests[i].inputs[0]))); 763 __ Cmp(input_ptr, input_end); 764 __ B(ne, &loop); 765 } 766 767 END(); 768 769 RUN(); 770 771 if (Test::generate_test_trace()) { 772 // Print the results. 773 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 774 printf("static const Inputs kOutputs_%s_%s[] = {\n", 775 mnemonic, 776 kTests[i].identifier); 777 for (size_t j = 0; j < results[i]->output_size; j++) { 778 printf(" { "); 779 printf("0x%08" PRIx32, results[i]->outputs[j].apsr); 780 printf(", "); 781 printf("0x%08" PRIx32, results[i]->outputs[j].rd); 782 printf(", "); 783 printf("0x%08" PRIx32, results[i]->outputs[j].rn); 784 printf(" },\n"); 785 } 786 printf("};\n"); 787 } 788 printf("static const TestResult kReference%s[] = {\n", mnemonic); 789 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 790 printf(" {\n"); 791 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n", 792 mnemonic, 793 kTests[i].identifier); 794 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier); 795 printf(" },\n"); 796 } 797 printf("};\n"); 798 } else if (kCheckSimulatorTestResults) { 799 // Check the results. 800 unsigned total_error_count = 0; 801 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 802 bool instruction_has_errors = false; 803 for (size_t j = 0; j < kTests[i].input_size; j++) { 804 uint32_t apsr = results[i]->outputs[j].apsr; 805 uint32_t rd = results[i]->outputs[j].rd; 806 uint32_t rn = results[i]->outputs[j].rn; 807 uint32_t apsr_input = kTests[i].inputs[j].apsr; 808 uint32_t rd_input = kTests[i].inputs[j].rd; 809 uint32_t rn_input = kTests[i].inputs[j].rn; 810 uint32_t apsr_ref = reference[i].outputs[j].apsr; 811 uint32_t rd_ref = reference[i].outputs[j].rd; 812 uint32_t rn_ref = reference[i].outputs[j].rn; 813 814 if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) && 815 (++total_error_count <= kErrorReportLimit)) { 816 // Print the instruction once even if it triggered multiple failures. 817 if (!instruction_has_errors) { 818 printf("Error(s) when testing \"%s %s\":\n", 819 mnemonic, 820 kTests[i].operands_description); 821 instruction_has_errors = true; 822 } 823 // Print subsequent errors. 824 printf(" Input: "); 825 printf("0x%08" PRIx32, apsr_input); 826 printf(", "); 827 printf("0x%08" PRIx32, rd_input); 828 printf(", "); 829 printf("0x%08" PRIx32, rn_input); 830 printf("\n"); 831 printf(" Expected: "); 832 printf("0x%08" PRIx32, apsr_ref); 833 printf(", "); 834 printf("0x%08" PRIx32, rd_ref); 835 printf(", "); 836 printf("0x%08" PRIx32, rn_ref); 837 printf("\n"); 838 printf(" Found: "); 839 printf("0x%08" PRIx32, apsr); 840 printf(", "); 841 printf("0x%08" PRIx32, rd); 842 printf(", "); 843 printf("0x%08" PRIx32, rn); 844 printf("\n\n"); 845 } 846 } 847 } 848 849 if (total_error_count > kErrorReportLimit) { 850 printf("%u other errors follow.\n", 851 total_error_count - kErrorReportLimit); 852 } 853 VIXL_CHECK(total_error_count == 0); 854 } else { 855 VIXL_WARNING("Assembled the code, but did not run anything.\n"); 856 } 857 858 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 859 delete[] results[i]->outputs; 860 delete results[i]; 861 delete[] scratch_memory_buffers[i]; 862 } 863 864 TEARDOWN(); 865} 866 867// Instantiate tests for each instruction in the list. 868#define TEST(mnemonic) \ 869 static void Test_##mnemonic() { \ 870 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \ 871 } \ 872 static Test test_##mnemonic( \ 873 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_ROR_AMOUNT_A32_" #mnemonic, \ 874 &Test_##mnemonic); 875FOREACH_INSTRUCTION(TEST) 876#undef TEST 877 878} // aarch32 879} // vixl 880