test-simulator-cond-rd-operand-rn-ror-amount-a32.cc revision d3832965c62a8ad461b9ea9eb0994ca6b0a3da2c
1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27// ----------------------------------------------------------------------------- 28// This file is auto generated from the 29// test/aarch32/config/template-simulator-aarch32.cc.in template file using 30// tools/generate_tests.py. 31// 32// PLEASE DO NOT EDIT. 33// ----------------------------------------------------------------------------- 34 35#include "test-runner.h" 36 37#include "test-utils.h" 38#include "test-utils-aarch32.h" 39 40#include "aarch32/assembler-aarch32.h" 41#include "aarch32/macro-assembler-aarch32.h" 42#include "aarch32/disasm-aarch32.h" 43 44#define __ masm. 45#define BUF_SIZE (4096) 46 47#ifdef VIXL_INCLUDE_SIMULATOR 48// Run tests with the simulator. 49 50#define SETUP() MacroAssembler masm(BUF_SIZE) 51 52#define START() masm.GetBuffer().Reset() 53 54#define END() \ 55 __ Hlt(0); \ 56 __ FinalizeCode(); 57 58// TODO: Run the tests in the simulator. 59#define RUN() 60 61#define TEARDOWN() 62 63#else // ifdef VIXL_INCLUDE_SIMULATOR. 64 65#define SETUP() MacroAssembler masm(BUF_SIZE); 66 67#define START() \ 68 masm.GetBuffer().Reset(); \ 69 __ Push(r4); \ 70 __ Push(r5); \ 71 __ Push(r6); \ 72 __ Push(r7); \ 73 __ Push(r8); \ 74 __ Push(r9); \ 75 __ Push(r10); \ 76 __ Push(r11); \ 77 __ Push(r12); \ 78 __ Push(lr) 79 80#define END() \ 81 __ Pop(lr); \ 82 __ Pop(r12); \ 83 __ Pop(r11); \ 84 __ Pop(r10); \ 85 __ Pop(r9); \ 86 __ Pop(r8); \ 87 __ Pop(r7); \ 88 __ Pop(r6); \ 89 __ Pop(r5); \ 90 __ Pop(r4); \ 91 __ Bx(lr); \ 92 __ FinalizeCode(); 93 94// Copy the generated code into a memory area garanteed to be executable before 95// executing it. 96#define RUN() \ 97 { \ 98 ExecutableMemory code(masm.GetBuffer().GetCursorOffset()); \ 99 code.Write(masm.GetBuffer().GetOffsetAddress<byte*>(0), \ 100 masm.GetBuffer().GetCursorOffset()); \ 101 int pcs_offset = masm.IsT32() ? 1 : 0; \ 102 code.Execute(pcs_offset); \ 103 } 104 105#define TEARDOWN() 106 107#endif // ifdef VIXL_INCLUDE_SIMULATOR 108 109namespace vixl { 110namespace aarch32 { 111 112// List of instruction encodings: 113#define FOREACH_INSTRUCTION(M) \ 114 M(Sxtb) \ 115 M(Sxtb16) \ 116 M(Sxth) \ 117 M(Uxtb) \ 118 M(Uxtb16) \ 119 M(Uxth) 120 121// Values to be passed to the assembler to produce the instruction under test. 122struct Operands { 123 Condition cond; 124 Register rd; 125 Register rn; 126 ShiftType ror; 127 uint32_t amount; 128}; 129 130// Input data to feed to the instruction. 131struct Inputs { 132 uint32_t apsr; 133 uint32_t rd; 134 uint32_t rn; 135}; 136 137// This structure contains all input data needed to test one specific encoding. 138// It used to generate a loop over an instruction. 139struct TestLoopData { 140 // The `operands` fields represents the values to pass to the assembler to 141 // produce the instruction. 142 Operands operands; 143 // Description of the operands, used for error reporting. 144 const char* operands_description; 145 // Unique identifier, used for generating traces. 146 const char* identifier; 147 // Array of values to be fed to the instruction. 148 size_t input_size; 149 const Inputs* inputs; 150}; 151 152static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab}, 153 {ZFlag, 0xabababab, 0xabababab}, 154 {CFlag, 0xabababab, 0xabababab}, 155 {VFlag, 0xabababab, 0xabababab}, 156 {NZFlag, 0xabababab, 0xabababab}, 157 {NCFlag, 0xabababab, 0xabababab}, 158 {NVFlag, 0xabababab, 0xabababab}, 159 {ZCFlag, 0xabababab, 0xabababab}, 160 {ZVFlag, 0xabababab, 0xabababab}, 161 {CVFlag, 0xabababab, 0xabababab}, 162 {NZCFlag, 0xabababab, 0xabababab}, 163 {NZVFlag, 0xabababab, 0xabababab}, 164 {NCVFlag, 0xabababab, 0xabababab}, 165 {ZCVFlag, 0xabababab, 0xabababab}, 166 {NZCVFlag, 0xabababab, 0xabababab}}; 167 168static const Inputs kRdIsRn[] = {{NoFlag, 0x00000000, 0x00000000}, 169 {NoFlag, 0x00000001, 0x00000001}, 170 {NoFlag, 0x00000002, 0x00000002}, 171 {NoFlag, 0x00000020, 0x00000020}, 172 {NoFlag, 0x0000007d, 0x0000007d}, 173 {NoFlag, 0x0000007e, 0x0000007e}, 174 {NoFlag, 0x0000007f, 0x0000007f}, 175 {NoFlag, 0x00007ffd, 0x00007ffd}, 176 {NoFlag, 0x00007ffe, 0x00007ffe}, 177 {NoFlag, 0x00007fff, 0x00007fff}, 178 {NoFlag, 0x33333333, 0x33333333}, 179 {NoFlag, 0x55555555, 0x55555555}, 180 {NoFlag, 0x7ffffffd, 0x7ffffffd}, 181 {NoFlag, 0x7ffffffe, 0x7ffffffe}, 182 {NoFlag, 0x7fffffff, 0x7fffffff}, 183 {NoFlag, 0x80000000, 0x80000000}, 184 {NoFlag, 0x80000001, 0x80000001}, 185 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 186 {NoFlag, 0xcccccccc, 0xcccccccc}, 187 {NoFlag, 0xffff8000, 0xffff8000}, 188 {NoFlag, 0xffff8001, 0xffff8001}, 189 {NoFlag, 0xffff8002, 0xffff8002}, 190 {NoFlag, 0xffff8003, 0xffff8003}, 191 {NoFlag, 0xffffff80, 0xffffff80}, 192 {NoFlag, 0xffffff81, 0xffffff81}, 193 {NoFlag, 0xffffff82, 0xffffff82}, 194 {NoFlag, 0xffffff83, 0xffffff83}, 195 {NoFlag, 0xffffffe0, 0xffffffe0}, 196 {NoFlag, 0xfffffffd, 0xfffffffd}, 197 {NoFlag, 0xfffffffe, 0xfffffffe}, 198 {NoFlag, 0xffffffff, 0xffffffff}}; 199 200static const Inputs kRdIsNotRn[] = {{NoFlag, 0x00000002, 0xcccccccc}, 201 {NoFlag, 0x7ffffffd, 0x00007ffe}, 202 {NoFlag, 0xffffff80, 0x00000020}, 203 {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 204 {NoFlag, 0x33333333, 0xffffff82}, 205 {NoFlag, 0xffff8001, 0x7ffffffe}, 206 {NoFlag, 0xfffffffd, 0x00007ffe}, 207 {NoFlag, 0xffffff80, 0x80000000}, 208 {NoFlag, 0x00000001, 0x33333333}, 209 {NoFlag, 0xcccccccc, 0x7ffffffe}, 210 {NoFlag, 0x00000000, 0xcccccccc}, 211 {NoFlag, 0x00000000, 0x55555555}, 212 {NoFlag, 0xffffffff, 0xffffffff}, 213 {NoFlag, 0x0000007e, 0xffff8002}, 214 {NoFlag, 0x80000000, 0x7ffffffd}, 215 {NoFlag, 0xffffff81, 0x0000007e}, 216 {NoFlag, 0x0000007f, 0xffff8001}, 217 {NoFlag, 0xffffffe0, 0x00007ffd}, 218 {NoFlag, 0xffff8003, 0x00000002}, 219 {NoFlag, 0xffffff83, 0x55555555}, 220 {NoFlag, 0xffffff83, 0xffffff80}, 221 {NoFlag, 0xffffff81, 0xffff8000}, 222 {NoFlag, 0x00000020, 0x7ffffffe}, 223 {NoFlag, 0xffffffe0, 0x00000000}, 224 {NoFlag, 0x7fffffff, 0x0000007e}, 225 {NoFlag, 0x80000001, 0xffffffff}, 226 {NoFlag, 0x00000001, 0x80000001}, 227 {NoFlag, 0x00000002, 0x0000007f}, 228 {NoFlag, 0x7fffffff, 0xcccccccc}, 229 {NoFlag, 0x80000001, 0x00007ffe}, 230 {NoFlag, 0xffff8002, 0x0000007e}, 231 {NoFlag, 0x00007ffe, 0xcccccccc}, 232 {NoFlag, 0x80000000, 0xffff8002}, 233 {NoFlag, 0xffffff83, 0x7ffffffe}, 234 {NoFlag, 0xffff8001, 0x00000001}, 235 {NoFlag, 0xffffff81, 0x00000020}, 236 {NoFlag, 0xfffffffe, 0xffff8001}, 237 {NoFlag, 0xffffffff, 0xfffffffe}, 238 {NoFlag, 0xcccccccc, 0x55555555}, 239 {NoFlag, 0x00000020, 0xffffff83}, 240 {NoFlag, 0xffffff83, 0xffff8001}, 241 {NoFlag, 0xffffff83, 0xffff8000}, 242 {NoFlag, 0x00007fff, 0x00000002}, 243 {NoFlag, 0x55555555, 0xffff8000}, 244 {NoFlag, 0x80000001, 0xffffff81}, 245 {NoFlag, 0x00000002, 0x00000000}, 246 {NoFlag, 0x33333333, 0xffffff81}, 247 {NoFlag, 0xffff8001, 0xffffff82}, 248 {NoFlag, 0xcccccccc, 0xffff8003}, 249 {NoFlag, 0xffff8003, 0x7ffffffd}, 250 {NoFlag, 0x0000007d, 0x00007ffe}, 251 {NoFlag, 0xffffff80, 0x0000007d}, 252 {NoFlag, 0xaaaaaaaa, 0x00007ffd}, 253 {NoFlag, 0x80000000, 0xffffff82}, 254 {NoFlag, 0x00000002, 0x7ffffffe}, 255 {NoFlag, 0x00000002, 0xffffff83}, 256 {NoFlag, 0x55555555, 0x00000002}, 257 {NoFlag, 0xffffffff, 0xffffff82}, 258 {NoFlag, 0xaaaaaaaa, 0x00000020}, 259 {NoFlag, 0x00000001, 0xffffff82}, 260 {NoFlag, 0x0000007f, 0xffffff82}, 261 {NoFlag, 0x7ffffffd, 0xaaaaaaaa}, 262 {NoFlag, 0x00007ffe, 0x00000001}, 263 {NoFlag, 0xfffffffd, 0xffffffe0}, 264 {NoFlag, 0xffffff81, 0xffffff83}, 265 {NoFlag, 0x0000007d, 0x00000000}, 266 {NoFlag, 0x0000007d, 0xffff8000}, 267 {NoFlag, 0xffffff81, 0x7fffffff}, 268 {NoFlag, 0xffffffff, 0x80000000}, 269 {NoFlag, 0x00000000, 0x00000001}, 270 {NoFlag, 0x55555555, 0xffffff82}, 271 {NoFlag, 0x00007ffe, 0x00007ffe}, 272 {NoFlag, 0x80000001, 0xfffffffd}, 273 {NoFlag, 0x00007fff, 0x33333333}, 274 {NoFlag, 0x00007fff, 0x80000000}, 275 {NoFlag, 0xcccccccc, 0x00007fff}, 276 {NoFlag, 0xfffffffe, 0xffffffe0}, 277 {NoFlag, 0x7ffffffe, 0x0000007f}, 278 {NoFlag, 0x00007ffd, 0xffff8001}, 279 {NoFlag, 0x00000002, 0x00000001}, 280 {NoFlag, 0x80000000, 0xffffffff}, 281 {NoFlag, 0xffffff83, 0xcccccccc}, 282 {NoFlag, 0xffff8002, 0x7ffffffe}, 283 {NoFlag, 0xaaaaaaaa, 0x00000000}, 284 {NoFlag, 0xffffff80, 0xcccccccc}, 285 {NoFlag, 0x33333333, 0xffffff83}, 286 {NoFlag, 0x0000007e, 0xffffffe0}, 287 {NoFlag, 0x0000007e, 0x00007fff}, 288 {NoFlag, 0x0000007f, 0x00000002}, 289 {NoFlag, 0x7ffffffe, 0xcccccccc}, 290 {NoFlag, 0x0000007d, 0xffffff80}, 291 {NoFlag, 0x00007fff, 0x00000020}, 292 {NoFlag, 0x7ffffffe, 0xfffffffe}, 293 {NoFlag, 0xfffffffe, 0xffffff81}, 294 {NoFlag, 0xffffffff, 0x0000007f}, 295 {NoFlag, 0xffff8002, 0x7ffffffd}, 296 {NoFlag, 0xffff8001, 0xfffffffe}, 297 {NoFlag, 0x33333333, 0xffff8002}, 298 {NoFlag, 0x00000000, 0xffffffff}, 299 {NoFlag, 0x33333333, 0xffffff80}, 300 {NoFlag, 0x0000007f, 0x00007fff}, 301 {NoFlag, 0xffffffff, 0xffff8001}, 302 {NoFlag, 0x7fffffff, 0xffff8002}, 303 {NoFlag, 0x7ffffffd, 0xffffff83}, 304 {NoFlag, 0x7fffffff, 0x0000007f}, 305 {NoFlag, 0xffffff83, 0xfffffffe}, 306 {NoFlag, 0x7ffffffe, 0xffff8003}, 307 {NoFlag, 0xffff8002, 0xffff8002}, 308 {NoFlag, 0x80000001, 0x0000007f}, 309 {NoFlag, 0x00000020, 0x00000002}, 310 {NoFlag, 0xffffff82, 0xffff8001}, 311 {NoFlag, 0xffffffff, 0x00000001}, 312 {NoFlag, 0xffffff80, 0xffff8002}, 313 {NoFlag, 0xffff8003, 0x7fffffff}, 314 {NoFlag, 0xffffffff, 0xffff8000}, 315 {NoFlag, 0xffff8002, 0x00007ffd}, 316 {NoFlag, 0x00000020, 0xffffff81}, 317 {NoFlag, 0x00000001, 0x55555555}, 318 {NoFlag, 0x7ffffffe, 0x00000020}, 319 {NoFlag, 0x80000000, 0x00000001}, 320 {NoFlag, 0x00007ffd, 0xffff8002}, 321 {NoFlag, 0x7fffffff, 0xfffffffe}, 322 {NoFlag, 0xcccccccc, 0x00007ffd}, 323 {NoFlag, 0x00000000, 0xfffffffd}, 324 {NoFlag, 0xffff8003, 0xffffff80}, 325 {NoFlag, 0x80000001, 0xffffff80}, 326 {NoFlag, 0xffffffff, 0xffff8002}, 327 {NoFlag, 0x00007ffe, 0xffff8002}, 328 {NoFlag, 0xffffff80, 0x00007ffe}, 329 {NoFlag, 0x80000001, 0xffff8001}, 330 {NoFlag, 0x0000007f, 0xffffff80}, 331 {NoFlag, 0xffffff81, 0x80000000}, 332 {NoFlag, 0x00007fff, 0x00007ffe}, 333 {NoFlag, 0x33333333, 0xffff8000}, 334 {NoFlag, 0x33333333, 0x00007fff}, 335 {NoFlag, 0x00000000, 0x0000007d}, 336 {NoFlag, 0x80000001, 0x00000000}, 337 {NoFlag, 0xffffffff, 0x55555555}, 338 {NoFlag, 0x80000001, 0x80000000}, 339 {NoFlag, 0xffffffff, 0xffffff80}, 340 {NoFlag, 0xffffff81, 0xffff8003}, 341 {NoFlag, 0x55555555, 0x80000001}, 342 {NoFlag, 0x7fffffff, 0xffff8001}, 343 {NoFlag, 0xffffff83, 0x00000002}, 344 {NoFlag, 0x0000007e, 0xffffff81}, 345 {NoFlag, 0x80000000, 0xffff8001}, 346 {NoFlag, 0xffffff80, 0xfffffffe}, 347 {NoFlag, 0x0000007e, 0xfffffffd}, 348 {NoFlag, 0xffffffe0, 0xffffffff}, 349 {NoFlag, 0x55555555, 0x80000000}, 350 {NoFlag, 0x0000007d, 0x80000001}, 351 {NoFlag, 0xffffffe0, 0x7ffffffd}, 352 {NoFlag, 0x00000000, 0x00000000}, 353 {NoFlag, 0x55555555, 0x00000001}, 354 {NoFlag, 0x00007ffd, 0x7fffffff}, 355 {NoFlag, 0x55555555, 0xffffffff}, 356 {NoFlag, 0xffff8003, 0x00007fff}, 357 {NoFlag, 0xffffff82, 0x00007fff}, 358 {NoFlag, 0x33333333, 0x55555555}, 359 {NoFlag, 0x00000020, 0x33333333}, 360 {NoFlag, 0x7ffffffe, 0xfffffffd}, 361 {NoFlag, 0x7ffffffe, 0x00000001}, 362 {NoFlag, 0xffffff83, 0xffffffe0}, 363 {NoFlag, 0xfffffffe, 0xaaaaaaaa}, 364 {NoFlag, 0xffff8002, 0x33333333}, 365 {NoFlag, 0xffff8002, 0xffff8003}, 366 {NoFlag, 0x33333333, 0x7fffffff}, 367 {NoFlag, 0xfffffffd, 0xffffff83}, 368 {NoFlag, 0x00000000, 0xffff8000}, 369 {NoFlag, 0xffffff82, 0x55555555}, 370 {NoFlag, 0xffffff82, 0xffffff81}, 371 {NoFlag, 0xcccccccc, 0xfffffffe}, 372 {NoFlag, 0xfffffffd, 0x7fffffff}, 373 {NoFlag, 0x00007fff, 0x7fffffff}, 374 {NoFlag, 0xffffff83, 0xffff8003}, 375 {NoFlag, 0xfffffffe, 0xffffffff}, 376 {NoFlag, 0x7ffffffd, 0x00007ffd}, 377 {NoFlag, 0x7ffffffd, 0x00007fff}, 378 {NoFlag, 0x00007ffd, 0xffffffff}, 379 {NoFlag, 0x00000001, 0xffff8003}, 380 {NoFlag, 0xffffff80, 0xfffffffd}, 381 {NoFlag, 0x33333333, 0x80000000}, 382 {NoFlag, 0xffff8001, 0x00000020}, 383 {NoFlag, 0xcccccccc, 0x00000002}, 384 {NoFlag, 0x00000000, 0x00000002}, 385 {NoFlag, 0x0000007d, 0x00007fff}, 386 {NoFlag, 0xcccccccc, 0x00000001}, 387 {NoFlag, 0xffffff83, 0x00007fff}, 388 {NoFlag, 0x80000001, 0x00000020}, 389 {NoFlag, 0xffff8003, 0xffffffe0}, 390 {NoFlag, 0x00007ffd, 0xaaaaaaaa}, 391 {NoFlag, 0x33333333, 0xffff8001}, 392 {NoFlag, 0xffffff83, 0x80000001}, 393 {NoFlag, 0xffff8000, 0xffff8000}, 394 {NoFlag, 0x00007ffe, 0xffff8001}, 395 {NoFlag, 0x7ffffffd, 0x00000000}, 396 {NoFlag, 0x00007ffe, 0x33333333}, 397 {NoFlag, 0xffff8001, 0xffffff80}, 398 {NoFlag, 0xfffffffe, 0x55555555}, 399 {NoFlag, 0xffffff82, 0xffffffff}}; 400 401static const Inputs kRotations[] = {{NoFlag, 0xabababab, 0x00000000}, 402 {NoFlag, 0xabababab, 0x00000001}, 403 {NoFlag, 0xabababab, 0x00000002}, 404 {NoFlag, 0xabababab, 0x00000020}, 405 {NoFlag, 0xabababab, 0x0000007d}, 406 {NoFlag, 0xabababab, 0x0000007e}, 407 {NoFlag, 0xabababab, 0x0000007f}, 408 {NoFlag, 0xabababab, 0x00007ffd}, 409 {NoFlag, 0xabababab, 0x00007ffe}, 410 {NoFlag, 0xabababab, 0x00007fff}, 411 {NoFlag, 0xabababab, 0x33333333}, 412 {NoFlag, 0xabababab, 0x55555555}, 413 {NoFlag, 0xabababab, 0x7ffffffd}, 414 {NoFlag, 0xabababab, 0x7ffffffe}, 415 {NoFlag, 0xabababab, 0x7fffffff}, 416 {NoFlag, 0xabababab, 0x80000000}, 417 {NoFlag, 0xabababab, 0x80000001}, 418 {NoFlag, 0xabababab, 0xaaaaaaaa}, 419 {NoFlag, 0xabababab, 0xcccccccc}, 420 {NoFlag, 0xabababab, 0xffff8000}, 421 {NoFlag, 0xabababab, 0xffff8001}, 422 {NoFlag, 0xabababab, 0xffff8002}, 423 {NoFlag, 0xabababab, 0xffff8003}, 424 {NoFlag, 0xabababab, 0xffffff80}, 425 {NoFlag, 0xabababab, 0xffffff81}, 426 {NoFlag, 0xabababab, 0xffffff82}, 427 {NoFlag, 0xabababab, 0xffffff83}, 428 {NoFlag, 0xabababab, 0xffffffe0}, 429 {NoFlag, 0xabababab, 0xfffffffd}, 430 {NoFlag, 0xabababab, 0xfffffffe}, 431 {NoFlag, 0xabababab, 0xffffffff}}; 432 433// A loop will be generated for each element of this array. 434static const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0}, 435 "eq r0 r0 ROR 0", 436 "Condition_eq_r0_r0_ROR_0", 437 ARRAY_SIZE(kCondition), 438 kCondition}, 439 {{ne, r0, r0, ROR, 0}, 440 "ne r0 r0 ROR 0", 441 "Condition_ne_r0_r0_ROR_0", 442 ARRAY_SIZE(kCondition), 443 kCondition}, 444 {{cs, r0, r0, ROR, 0}, 445 "cs r0 r0 ROR 0", 446 "Condition_cs_r0_r0_ROR_0", 447 ARRAY_SIZE(kCondition), 448 kCondition}, 449 {{cc, r0, r0, ROR, 0}, 450 "cc r0 r0 ROR 0", 451 "Condition_cc_r0_r0_ROR_0", 452 ARRAY_SIZE(kCondition), 453 kCondition}, 454 {{mi, r0, r0, ROR, 0}, 455 "mi r0 r0 ROR 0", 456 "Condition_mi_r0_r0_ROR_0", 457 ARRAY_SIZE(kCondition), 458 kCondition}, 459 {{pl, r0, r0, ROR, 0}, 460 "pl r0 r0 ROR 0", 461 "Condition_pl_r0_r0_ROR_0", 462 ARRAY_SIZE(kCondition), 463 kCondition}, 464 {{vs, r0, r0, ROR, 0}, 465 "vs r0 r0 ROR 0", 466 "Condition_vs_r0_r0_ROR_0", 467 ARRAY_SIZE(kCondition), 468 kCondition}, 469 {{vc, r0, r0, ROR, 0}, 470 "vc r0 r0 ROR 0", 471 "Condition_vc_r0_r0_ROR_0", 472 ARRAY_SIZE(kCondition), 473 kCondition}, 474 {{hi, r0, r0, ROR, 0}, 475 "hi r0 r0 ROR 0", 476 "Condition_hi_r0_r0_ROR_0", 477 ARRAY_SIZE(kCondition), 478 kCondition}, 479 {{ls, r0, r0, ROR, 0}, 480 "ls r0 r0 ROR 0", 481 "Condition_ls_r0_r0_ROR_0", 482 ARRAY_SIZE(kCondition), 483 kCondition}, 484 {{ge, r0, r0, ROR, 0}, 485 "ge r0 r0 ROR 0", 486 "Condition_ge_r0_r0_ROR_0", 487 ARRAY_SIZE(kCondition), 488 kCondition}, 489 {{lt, r0, r0, ROR, 0}, 490 "lt r0 r0 ROR 0", 491 "Condition_lt_r0_r0_ROR_0", 492 ARRAY_SIZE(kCondition), 493 kCondition}, 494 {{gt, r0, r0, ROR, 0}, 495 "gt r0 r0 ROR 0", 496 "Condition_gt_r0_r0_ROR_0", 497 ARRAY_SIZE(kCondition), 498 kCondition}, 499 {{le, r0, r0, ROR, 0}, 500 "le r0 r0 ROR 0", 501 "Condition_le_r0_r0_ROR_0", 502 ARRAY_SIZE(kCondition), 503 kCondition}, 504 {{al, r0, r0, ROR, 0}, 505 "al r0 r0 ROR 0", 506 "Condition_al_r0_r0_ROR_0", 507 ARRAY_SIZE(kCondition), 508 kCondition}, 509 {{al, r0, r0, ROR, 0}, 510 "al r0 r0 ROR 0", 511 "RdIsRn_al_r0_r0_ROR_0", 512 ARRAY_SIZE(kRdIsRn), 513 kRdIsRn}, 514 {{al, r1, r1, ROR, 0}, 515 "al r1 r1 ROR 0", 516 "RdIsRn_al_r1_r1_ROR_0", 517 ARRAY_SIZE(kRdIsRn), 518 kRdIsRn}, 519 {{al, r2, r2, ROR, 0}, 520 "al r2 r2 ROR 0", 521 "RdIsRn_al_r2_r2_ROR_0", 522 ARRAY_SIZE(kRdIsRn), 523 kRdIsRn}, 524 {{al, r3, r3, ROR, 0}, 525 "al r3 r3 ROR 0", 526 "RdIsRn_al_r3_r3_ROR_0", 527 ARRAY_SIZE(kRdIsRn), 528 kRdIsRn}, 529 {{al, r4, r4, ROR, 0}, 530 "al r4 r4 ROR 0", 531 "RdIsRn_al_r4_r4_ROR_0", 532 ARRAY_SIZE(kRdIsRn), 533 kRdIsRn}, 534 {{al, r5, r5, ROR, 0}, 535 "al r5 r5 ROR 0", 536 "RdIsRn_al_r5_r5_ROR_0", 537 ARRAY_SIZE(kRdIsRn), 538 kRdIsRn}, 539 {{al, r6, r6, ROR, 0}, 540 "al r6 r6 ROR 0", 541 "RdIsRn_al_r6_r6_ROR_0", 542 ARRAY_SIZE(kRdIsRn), 543 kRdIsRn}, 544 {{al, r7, r7, ROR, 0}, 545 "al r7 r7 ROR 0", 546 "RdIsRn_al_r7_r7_ROR_0", 547 ARRAY_SIZE(kRdIsRn), 548 kRdIsRn}, 549 {{al, r8, r8, ROR, 0}, 550 "al r8 r8 ROR 0", 551 "RdIsRn_al_r8_r8_ROR_0", 552 ARRAY_SIZE(kRdIsRn), 553 kRdIsRn}, 554 {{al, r9, r9, ROR, 0}, 555 "al r9 r9 ROR 0", 556 "RdIsRn_al_r9_r9_ROR_0", 557 ARRAY_SIZE(kRdIsRn), 558 kRdIsRn}, 559 {{al, r10, r10, ROR, 0}, 560 "al r10 r10 ROR 0", 561 "RdIsRn_al_r10_r10_ROR_0", 562 ARRAY_SIZE(kRdIsRn), 563 kRdIsRn}, 564 {{al, r11, r11, ROR, 0}, 565 "al r11 r11 ROR 0", 566 "RdIsRn_al_r11_r11_ROR_0", 567 ARRAY_SIZE(kRdIsRn), 568 kRdIsRn}, 569 {{al, r12, r12, ROR, 0}, 570 "al r12 r12 ROR 0", 571 "RdIsRn_al_r12_r12_ROR_0", 572 ARRAY_SIZE(kRdIsRn), 573 kRdIsRn}, 574 {{al, r14, r14, ROR, 0}, 575 "al r14 r14 ROR 0", 576 "RdIsRn_al_r14_r14_ROR_0", 577 ARRAY_SIZE(kRdIsRn), 578 kRdIsRn}, 579 {{al, r1, r8, ROR, 0}, 580 "al r1 r8 ROR 0", 581 "RdIsNotRn_al_r1_r8_ROR_0", 582 ARRAY_SIZE(kRdIsNotRn), 583 kRdIsNotRn}, 584 {{al, r7, r4, ROR, 0}, 585 "al r7 r4 ROR 0", 586 "RdIsNotRn_al_r7_r4_ROR_0", 587 ARRAY_SIZE(kRdIsNotRn), 588 kRdIsNotRn}, 589 {{al, r14, r10, ROR, 0}, 590 "al r14 r10 ROR 0", 591 "RdIsNotRn_al_r14_r10_ROR_0", 592 ARRAY_SIZE(kRdIsNotRn), 593 kRdIsNotRn}, 594 {{al, r10, r6, ROR, 0}, 595 "al r10 r6 ROR 0", 596 "RdIsNotRn_al_r10_r6_ROR_0", 597 ARRAY_SIZE(kRdIsNotRn), 598 kRdIsNotRn}, 599 {{al, r6, r5, ROR, 0}, 600 "al r6 r5 ROR 0", 601 "RdIsNotRn_al_r6_r5_ROR_0", 602 ARRAY_SIZE(kRdIsNotRn), 603 kRdIsNotRn}, 604 {{al, r12, r2, ROR, 0}, 605 "al r12 r2 ROR 0", 606 "RdIsNotRn_al_r12_r2_ROR_0", 607 ARRAY_SIZE(kRdIsNotRn), 608 kRdIsNotRn}, 609 {{al, r0, r11, ROR, 0}, 610 "al r0 r11 ROR 0", 611 "RdIsNotRn_al_r0_r11_ROR_0", 612 ARRAY_SIZE(kRdIsNotRn), 613 kRdIsNotRn}, 614 {{al, r10, r14, ROR, 0}, 615 "al r10 r14 ROR 0", 616 "RdIsNotRn_al_r10_r14_ROR_0", 617 ARRAY_SIZE(kRdIsNotRn), 618 kRdIsNotRn}, 619 {{al, r0, r5, ROR, 0}, 620 "al r0 r5 ROR 0", 621 "RdIsNotRn_al_r0_r5_ROR_0", 622 ARRAY_SIZE(kRdIsNotRn), 623 kRdIsNotRn}, 624 {{al, r0, r3, ROR, 0}, 625 "al r0 r3 ROR 0", 626 "RdIsNotRn_al_r0_r3_ROR_0", 627 ARRAY_SIZE(kRdIsNotRn), 628 kRdIsNotRn}, 629 {{al, r0, r1, ROR, 0}, 630 "al r0 r1 ROR 0", 631 "Rotations_al_r0_r1_ROR_0", 632 ARRAY_SIZE(kRotations), 633 kRotations}, 634 {{al, r0, r1, ROR, 8}, 635 "al r0 r1 ROR 8", 636 "Rotations_al_r0_r1_ROR_8", 637 ARRAY_SIZE(kRotations), 638 kRotations}, 639 {{al, r0, r1, ROR, 16}, 640 "al r0 r1 ROR 16", 641 "Rotations_al_r0_r1_ROR_16", 642 ARRAY_SIZE(kRotations), 643 kRotations}, 644 {{al, r0, r1, ROR, 24}, 645 "al r0 r1 ROR 24", 646 "Rotations_al_r0_r1_ROR_24", 647 ARRAY_SIZE(kRotations), 648 kRotations}}; 649 650// We record all inputs to the instructions as outputs. This way, we also check 651// that what shouldn't change didn't change. 652struct TestResult { 653 size_t output_size; 654 const Inputs* outputs; 655}; 656 657// These headers each contain an array of `TestResult` with the reference output 658// values. The reference arrays are names `kReference{mnemonic}`. 659#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb.h" 660#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxtb16.h" 661#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-sxth.h" 662#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb.h" 663#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxtb16.h" 664#include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-a32-uxth.h" 665 666// The maximum number of errors to report in detail for each test. 667static const unsigned kErrorReportLimit = 8; 668 669typedef void (MacroAssembler::*Fn)(Condition cond, Register rd, 670 const Operand& op); 671 672static void TestHelper(Fn instruction, const char* mnemonic, 673 const TestResult reference[]) { 674 SETUP(); 675 masm.SetT32(false); 676 START(); 677 678 // Data to compare to `reference`. 679 TestResult* results[ARRAY_SIZE(kTests)]; 680 681 // Test cases for memory bound instructions may allocate a buffer and save its 682 // address in this array. 683 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)]; 684 685 // Generate a loop for each element in `kTests`. Each loop tests one specific 686 // instruction. 687 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 688 // Allocate results on the heap for this test. 689 results[i] = new TestResult; 690 results[i]->outputs = new Inputs[kTests[i].input_size]; 691 results[i]->output_size = kTests[i].input_size; 692 693 uintptr_t input_address = reinterpret_cast<uintptr_t>(kTests[i].inputs); 694 uintptr_t result_address = reinterpret_cast<uintptr_t>(results[i]->outputs); 695 696 scratch_memory_buffers[i] = NULL; 697 698 Label loop; 699 UseScratchRegisterScope scratch_registers(&masm); 700 // Include all registers from r0 ro r12. 701 scratch_registers.Include(RegisterList(0x1fff)); 702 703 // Values to pass to the macro-assembler. 704 Condition cond = kTests[i].operands.cond; 705 Register rd = kTests[i].operands.rd; 706 Register rn = kTests[i].operands.rn; 707 ShiftType ror = kTests[i].operands.ror; 708 uint32_t amount = kTests[i].operands.amount; 709 Operand op(rn, ror, amount); 710 scratch_registers.Exclude(rd); 711 scratch_registers.Exclude(rn); 712 713 // Allocate reserved registers for our own use. 714 Register input_ptr = scratch_registers.Acquire(); 715 Register input_end = scratch_registers.Acquire(); 716 Register result_ptr = scratch_registers.Acquire(); 717 718 // Initialize `input_ptr` to the first element and `input_end` the address 719 // after the array. 720 __ Mov(input_ptr, input_address); 721 __ Add(input_end, input_ptr, 722 sizeof(kTests[i].inputs[0]) * kTests[i].input_size); 723 __ Mov(result_ptr, result_address); 724 __ Bind(&loop); 725 726 { 727 UseScratchRegisterScope temp_registers(&masm); 728 Register nzcv_bits = temp_registers.Acquire(); 729 Register saved_q_bit = temp_registers.Acquire(); 730 // Save the `Q` bit flag. 731 __ Mrs(saved_q_bit, APSR); 732 __ And(saved_q_bit, saved_q_bit, QFlag); 733 // Set the `NZCV` and `Q` flags together. 734 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr))); 735 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); 736 __ Msr(APSR_nzcvq, nzcv_bits); 737 } 738 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd))); 739 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn))); 740 741 (masm.*instruction)(cond, rd, op); 742 743 { 744 UseScratchRegisterScope temp_registers(&masm); 745 Register nzcv_bits = temp_registers.Acquire(); 746 __ Mrs(nzcv_bits, APSR); 747 // Only record the NZCV bits. 748 __ And(nzcv_bits, nzcv_bits, NZCVFlag); 749 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr))); 750 } 751 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd))); 752 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn))); 753 754 // Advance the result pointer. 755 __ Add(result_ptr, result_ptr, sizeof(kTests[i].inputs[0])); 756 // Loop back until `input_ptr` is lower than `input_base`. 757 __ Add(input_ptr, input_ptr, sizeof(kTests[i].inputs[0])); 758 __ Cmp(input_ptr, input_end); 759 __ B(ne, &loop); 760 } 761 762 END(); 763 764 RUN(); 765 766 if (Test::generate_test_trace()) { 767 // Print the results. 768 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 769 printf("static const Inputs kOutputs_%s_%s[] = {\n", mnemonic, 770 kTests[i].identifier); 771 for (size_t j = 0; j < results[i]->output_size; j++) { 772 printf(" { "); 773 printf("0x%08" PRIx32, results[i]->outputs[j].apsr); 774 printf(", "); 775 printf("0x%08" PRIx32, results[i]->outputs[j].rd); 776 printf(", "); 777 printf("0x%08" PRIx32, results[i]->outputs[j].rn); 778 printf(" },\n"); 779 } 780 printf("};\n"); 781 } 782 printf("static const TestResult kReference%s[] = {\n", mnemonic); 783 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 784 printf(" {\n"); 785 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n", mnemonic, 786 kTests[i].identifier); 787 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier); 788 printf(" },\n"); 789 } 790 printf("};\n"); 791 } else { 792 // Check the results. 793 unsigned total_error_count = 0; 794 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 795 bool instruction_has_errors = false; 796 for (size_t j = 0; j < kTests[i].input_size; j++) { 797 uint32_t apsr = results[i]->outputs[j].apsr; 798 uint32_t rd = results[i]->outputs[j].rd; 799 uint32_t rn = results[i]->outputs[j].rn; 800 uint32_t apsr_input = kTests[i].inputs[j].apsr; 801 uint32_t rd_input = kTests[i].inputs[j].rd; 802 uint32_t rn_input = kTests[i].inputs[j].rn; 803 uint32_t apsr_ref = reference[i].outputs[j].apsr; 804 uint32_t rd_ref = reference[i].outputs[j].rd; 805 uint32_t rn_ref = reference[i].outputs[j].rn; 806 807 if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) && 808 (++total_error_count <= kErrorReportLimit)) { 809 // Print the instruction once even if it triggered multiple failures. 810 if (!instruction_has_errors) { 811 printf("Error(s) when testing \"%s %s\":\n", mnemonic, 812 kTests[i].operands_description); 813 instruction_has_errors = true; 814 } 815 // Print subsequent errors. 816 printf(" Input: "); 817 printf("0x%08" PRIx32, apsr_input); 818 printf(", "); 819 printf("0x%08" PRIx32, rd_input); 820 printf(", "); 821 printf("0x%08" PRIx32, rn_input); 822 printf("\n"); 823 printf(" Expected: "); 824 printf("0x%08" PRIx32, apsr_ref); 825 printf(", "); 826 printf("0x%08" PRIx32, rd_ref); 827 printf(", "); 828 printf("0x%08" PRIx32, rn_ref); 829 printf("\n"); 830 printf(" Found: "); 831 printf("0x%08" PRIx32, apsr); 832 printf(", "); 833 printf("0x%08" PRIx32, rd); 834 printf(", "); 835 printf("0x%08" PRIx32, rn); 836 printf("\n\n"); 837 } 838 } 839 } 840 841 if (total_error_count > kErrorReportLimit) { 842 printf("%u other errors follow.\n", 843 total_error_count - kErrorReportLimit); 844 } 845// TODO: Do this check for the simulator too when it is ready. 846#ifndef VIXL_INCLUDE_SIMULATOR 847 VIXL_CHECK(total_error_count == 0); 848#endif 849 } 850 851 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 852 delete[] results[i]->outputs; 853 delete results[i]; 854 delete scratch_memory_buffers[i]; 855 } 856 857 TEARDOWN(); 858} 859 860// Instantiate tests for each instruction in the list. 861#define TEST(mnemonic) \ 862 static void Test_##mnemonic() { \ 863 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \ 864 } \ 865 static Test test_##mnemonic( \ 866 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_ROR_AMOUNT_A32_" #mnemonic, \ 867 &Test_##mnemonic); 868FOREACH_INSTRUCTION(TEST) 869#undef TEST 870 871} // aarch32 872} // vixl 873