armVCM4P10_Average_4x_Align_unsafe_s.S revision 7ea582e1dbdd9a88b2105fbe29ed0ec92cbf70c6 
1/*
2 * Copyright (C) 2007-2008 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *
16 */
17/*
18 *
19 */
20
21    .eabi_attribute 24, 1
22    .eabi_attribute 25, 1
23
24    .arm
25    .fpu neon
26    .text
27
28    .global armVCM4P10_Average_4x4_Align0_unsafe
29armVCM4P10_Average_4x4_Align0_unsafe:
30    PUSH     {r4-r6,lr}
31    LDR      r7, =0x80808080
32    LDR      r12,[r2,#0]
33    LDR      r10,[r0],r1
34    LDR      lr,[r2,r3]
35    LDR      r11,[r0],r1
36    MVN      r12,r12
37    MVN      lr,lr
38    UHSUB8   r5,r10,r12
39    UHSUB8   r4,r11,lr
40    EOR      r5,r5,r7
41    STR      r5,[r2],r3
42    EOR      r4,r4,r7
43    STR      r4,[r2],r3
44    LDR      r10,[r0],r1
45    LDR      r12,[r2,#0]
46    LDR      r11,[r0],r1
47    LDR      lr,[r2,r3]
48    MVN      r12,r12
49    UHSUB8   r5,r10,r12
50    MVN      lr,lr
51    UHSUB8   r4,r11,lr
52    EOR      r5,r5,r7
53    STR      r5,[r2],r3
54    EOR      r4,r4,r7
55    STR      r4,[r2],r3
56    POP      {r4-r6,pc}
57
58    .global armVCM4P10_Average_4x4_Align2_unsafe
59armVCM4P10_Average_4x4_Align2_unsafe:
60    PUSH     {r4-r6,lr}
61    LDR      r7, =0x80808080
62    LDR      r4,[r0,#4]
63    LDR      r10,[r0],r1
64    LDR      r12,[r2,#0]
65    LDR      lr,[r2,r3]
66    LDR      r5,[r0,#4]
67    LDR      r11,[r0],r1
68    MVN      r12,r12
69    MVN      lr,lr
70    LSR      r10,r10,#16
71    ORR      r10,r10,r4,LSL #16
72    LSR      r11,r11,#16
73    ORR      r11,r11,r5,LSL #16
74    UHSUB8   r5,r10,r12
75    UHSUB8   r4,r11,lr
76    EOR      r5,r5,r7
77    STR      r5,[r2],r3
78    EOR      r4,r4,r7
79    STR      r4,[r2],r3
80    LDR      r4,[r0,#4]
81    LDR      r10,[r0],r1
82    LDR      r12,[r2,#0]
83    LDR      lr,[r2,r3]
84    LDR      r5,[r0,#4]
85    LDR      r11,[r0],r1
86    MVN      r12,r12
87    MVN      lr,lr
88    LSR      r10,r10,#16
89    ORR      r10,r10,r4,LSL #16
90    LSR      r11,r11,#16
91    ORR      r11,r11,r5,LSL #16
92    UHSUB8   r5,r10,r12
93    UHSUB8   r4,r11,lr
94    EOR      r5,r5,r7
95    STR      r5,[r2],r3
96    EOR      r4,r4,r7
97    STR      r4,[r2],r3
98    POP      {r4-r6,pc}
99
100    .global armVCM4P10_Average_4x4_Align3_unsafe
101armVCM4P10_Average_4x4_Align3_unsafe:
102    PUSH     {r4-r6,lr}
103    LDR      r7, =0x80808080
104    LDR      r4,[r0,#4]
105    LDR      r10,[r0],r1
106    LDR      r12,[r2,#0]
107    LDR      lr,[r2,r3]
108    LDR      r5,[r0,#4]
109    LDR      r11,[r0],r1
110    MVN      r12,r12
111    MVN      lr,lr
112    LSR      r10,r10,#24
113    ORR      r10,r10,r4,LSL #8
114    LSR      r11,r11,#24
115    ORR      r11,r11,r5,LSL #8
116    UHSUB8   r5,r10,r12
117    UHSUB8   r4,r11,lr
118    EOR      r5,r5,r7
119    STR      r5,[r2],r3
120    EOR      r4,r4,r7
121    STR      r4,[r2],r3
122    LDR      r4,[r0,#4]
123    LDR      r10,[r0],r1
124    LDR      r12,[r2,#0]
125    LDR      lr,[r2,r3]
126    LDR      r5,[r0,#4]
127    LDR      r11,[r0],r1
128    MVN      r12,r12
129    MVN      lr,lr
130    LSR      r10,r10,#24
131    ORR      r10,r10,r4,LSL #8
132    LSR      r11,r11,#24
133    ORR      r11,r11,r5,LSL #8
134    UHSUB8   r5,r10,r12
135    UHSUB8   r4,r11,lr
136    EOR      r5,r5,r7
137    STR      r5,[r2],r3
138    EOR      r4,r4,r7
139    STR      r4,[r2],r3
140    POP      {r4-r6,pc}
141
142    .end
143
144