1/*
2 * Copyright (C) 2007-2008 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *
16 */
17/*
18 *
19 */
20
21    .eabi_attribute 24, 1
22    .eabi_attribute 25, 1
23
24    .arm
25    .fpu neon
26    .text
27
28    .extern   armVCM4P10_CAVLCCoeffTokenTables
29    .extern   armVCM4P10_SuffixToLevel
30    .extern   armVCM4P10_CAVLCTotalZeros2x2Tables
31    .extern   armVCM4P10_CAVLCTotalZeroTables
32    .extern   armVCM4P10_CAVLCRunBeforeTables
33    .extern   armVCM4P10_ZigZag_2x2
34    .extern   armVCM4P10_ZigZag_4x4
35
36    .hidden   armVCM4P10_CAVLCCoeffTokenTables
37    .hidden   armVCM4P10_SuffixToLevel
38    .hidden   armVCM4P10_CAVLCTotalZeros2x2Tables
39    .hidden   armVCM4P10_CAVLCTotalZeroTables
40    .hidden   armVCM4P10_CAVLCRunBeforeTables
41    .hidden   armVCM4P10_ZigZag_2x2
42    .hidden   armVCM4P10_ZigZag_4x4
43
44    .global armVCM4P10_DecodeCoeffsToPair
45armVCM4P10_DecodeCoeffsToPair:
46    PUSH     {r4-r12,lr}
47    SUB      sp,sp,#0x40
48    LDR      r10,[r0,#0]
49    LDR      r12,[r1,#0]
50    LDR      r6, .LarmVCM4P10_CAVLCCoeffTokenTables
51P0: ADD      r6, pc
52    LDR      r4,[sp,#0x68]
53    LDRB     r9,[r10,#2]
54    LDRB     r8,[r10,#1]
55    LDRB     r11,[r10],#3
56    ADD      r12,r12,#8
57    LDR      r6,[r6,r4,LSL #2]
58    ORR      r9,r9,r8,LSL #8
59    ORR      r11,r9,r11,LSL #16
60    LSLS     r8,r11,r12
61    MOVS     r7,#0x1e
62    AND      r7,r7,r8,LSR #27
63    SUBS     r12,r12,#8
64L0x44:
65    BCC      L1
66    LDRB     r8,[r10],#1
67L1:
68    LDRH     r7,[r6,r7]
69    ADDCC    r12,r12,#8
70    ADD      r12,r12,#4
71    ORRCS    r11,r8,r11,LSL #8
72    LSRS     r8,r7,#1
73    BCS      L0x74
74    LSLS     r8,r11,r12
75    SUBS     r12,r12,#0xa
76    ADD      r7,r7,r8,LSR #29
77    BIC      r7,r7,#1
78    B        L0x44
79L0x74:
80    SUB      r12,r12,r7,LSR #13
81    BIC      r7,r8,#0xf000
82    LSRS     r5,r7,#2
83    STRB     r5,[r2,#0]
84    BEQ      L0x344
85    CMP      r7,#0x44
86    BGE      L0x33c
87    STR      r0,[sp,#0]
88    STR      r1,[sp,#4]
89    STR      r3,[sp,#8]
90    ANDS     r1,r7,#3
91    ADD      r2,sp,#0xc
92    BEQ      L0xd8
93    MOV      r0,r1
94L0xac:
95    LSLS     r7,r11,r12
96    SUBS     r12,r12,#7
97    BCC      L2
98    LDRB     r8,[r10],#1
99L2:
100    ADDCC    r12,r12,#8
101    LSR      r7,r7,#31
102    ORRCS    r11,r8,r11,LSL #8
103    SUBS     r0,r0,#1
104    MOV      r8,#1
105    SUB      r8,r8,r7,LSL #1
106    STRH     r8,[r2],#2
107    BGT      L0xac
108L0xd8:
109    SUBS     r0,r5,r1
110    BEQ      L0x1b8
111    MOV      r4,#1
112    CMP      r5,#0xa
113    MOVLE    r4,#0
114    CMP      r1,#3
115    MOVLT    r1,#4
116    MOVGE    r1,#2
117    MOVGE    r4,#0
118L0xfc:
119    LSLS     r7,r11,r12
120    CLZ      r7,r7
121    ADD      r12,r12,r7
122    SUBS     r12,r12,#7
123    BCC      L3
124    LDRB     r8,[r10],#1
125    ORR      r11,r8,r11,LSL #8
126    SUBS     r12,r12,#8
127    BCC      L3
128    LDRB     r8,[r10],#1
129L3:
130    ADDCC    r12,r12,#8
131    ORRCS    r11,r8,r11,LSL #8
132    CMP      r7,#0x10
133    BGE      L0x33c
134    MOVS     lr,r4
135    TEQEQ    r7,#0xe
136    MOVEQ    lr,#4
137    TEQ      r7,#0xf
138    MOVEQ    lr,#0xc
139    TEQEQ    r4,#0
140    ADDEQ    r7,r7,#0xf
141    TEQ      lr,#0
142    BEQ      L0x184
143    LSL      r3,r11,r12
144    ADD      r12,r12,lr
145    SUBS     r12,r12,#8
146    RSB      r9,lr,#0x20
147    BCC      L4
148    LDRB     r8,[r10],#1
149    ORR      r11,r8,r11,LSL #8
150    SUBS     r12,r12,#8
151    BCC      L4
152    LDRB     r8,[r10],#1
153L4:
154    ADDCC    r12,r12,#8
155    LSR      r3,r3,r9
156    ORRCS    r11,r8,r11,LSL #8
157    LSL      r7,r7,r4
158    ADD      r7,r3,r7
159L0x184:
160    ADD      r7,r7,r1
161    MOV      r1,#2
162    LSRS     r8,r7,#1
163    RSBCS    r8,r8,#0
164    STRH     r8,[r2],#2
165    LDR      r9, .LarmVCM4P10_SuffixToLevel
166P1: ADD      r9, pc
167    LDRSB    r8,[r9,r4]
168    TEQ      r4,#0
169    MOVEQ    r4,#1
170    CMP      r7,r8
171    ADDCS    r4,r4,#1
172    SUBS     r0,r0,#1
173    BGT      L0xfc
174L0x1b8:
175    LDR      r8,[sp,#0x6c]
176    SUB      r0,r5,#1
177    SUBS     r1,r8,r5
178    ADD      r4,sp,#0x2c
179    MOV      lr,r5
180    SUB      lr,lr,#1
181    BEQ      L0x2b0
182    TEQ      r8,#4
183    LDREQ    r6, .LarmVCM4P10_CAVLCTotalZeros2x2Tables
184    LDRNE    r6, .LarmVCM4P10_CAVLCTotalZeroTables
185P2: ADD      r6, pc
186    LDR      r6,[r6,r5,LSL #2]
187    LSLS     r8,r11,r12
188    MOVS     r7,#0x1e
189    AND      r7,r7,r8,LSR #27
190    SUBS     r12,r12,#8
191L0x1f4:
192    BCC      L5
193    LDRB     r8,[r10],#1
194L5:
195    LDRH     r7,[r6,r7]
196    ADDCC    r12,r12,#8
197    ADD      r12,r12,#4
198    ORRCS    r11,r8,r11,LSL #8
199    LSRS     r8,r7,#1
200    BCS      L0x224
201    LSLS     r8,r11,r12
202    SUBS     r12,r12,#0xa
203    ADD      r7,r7,r8,LSR #29
204    BIC      r7,r7,#1
205    B        L0x1f4
206L0x224:
207    SUB      r12,r12,r7,LSR #13
208    BIC      r7,r8,#0xf000
209    CMP      r7,#0x10
210    BGE      L0x33c
211    LDR      r3, .LarmVCM4P10_CAVLCRunBeforeTables
212P3: ADD      r3, pc
213    ADD      r4,sp,#0x2c
214    MOVS     r1,r7
215    ADD      lr,lr,r1
216    BEQ      L0x2b0
217L0x248:
218    SUBS     r0,r0,#1
219    LDR      r6,[r3,r1,LSL #2]
220    BLT      L0x2bc
221    LSLS     r8,r11,r12
222    MOVS     r7,#0xe
223    AND      r7,r7,r8,LSR #28
224    SUBS     r12,r12,#8
225L0x264:
226    BCC      L6
227    LDRB     r8,[r10],#1
228L6:
229    LDRH     r7,[r6,r7]
230    ADDCC    r12,r12,#8
231    ADD      r12,r12,#3
232    ORRCS    r11,r8,r11,LSL #8
233    LSRS     r8,r7,#1
234    BCS      L0x294
235    LSLS     r8,r11,r12
236    SUBS     r12,r12,#9
237    ADD      r7,r7,r8,LSR #29
238    BIC      r7,r7,#1
239    B        L0x264
240L0x294:
241    SUB      r12,r12,r7,LSR #13
242    BIC      r7,r8,#0xf000
243    CMP      r7,#0xf
244    BGE      L0x33c
245    SUBS     r1,r1,r7
246    STRB     r7,[r4],#1
247    BGT      L0x248
248L0x2b0:
249    SUBS     r0,r0,#1
250    BLT      L7
251    STRB     r1,[r4],#1
252L7:
253    BGT      L0x2b0
254L0x2bc:
255    STRB     r1,[r4],#1
256    LDR      r8,[sp,#0x6c]
257    TEQ      r8,#0xf
258    ADDEQ    lr,lr,#1
259    SUB      r4,r4,r5
260    SUB      r2,r2,r5
261    SUB      r2,r2,r5
262    LDR      r3,[sp,#8]
263    LDR      r0,[r3,#0]
264    TEQ      r8,#4
265    LDREQ    r6, .LarmVCM4P10_ZigZag_2x2
266    LDRNE    r6, .LarmVCM4P10_ZigZag_4x4
267P4: ADD      r6, pc
268L0x2ec:
269    LDRB     r9,[r4],#1
270    LDRB     r8,[r6,lr]
271    SUB      lr,lr,#1
272    SUB      lr,lr,r9
273    LDRSH    r9,[r2],#2
274    SUBS     r5,r5,#1
275    ORREQ    r8,r8,#0x20
276    ADD      r1,r9,#0x80
277    CMP      r1,#0x100
278    ORRCS    r8,r8,#0x10
279    TEQ      r5,#0
280    STRB     r8,[r0],#1
281    STRB     r9,[r0],#1
282    LSR      r9,r9,#8
283    BCC      L8
284    STRB     r9,[r0],#1
285L8:
286    BNE      L0x2ec
287    STR      r0,[r3,#0]
288    LDR      r0,[sp,#0]
289    LDR      r1,[sp,#4]
290    B        L0x344
291L0x33c:
292    MVN      r0,#1
293    B        L0x35c
294L0x344:
295    ADD      r10,r10,r12,LSR #3
296    AND      r12,r12,#7
297    SUB      r10,r10,#4
298    STR      r12,[r1,#0]
299    STR      r10,[r0,#0]
300    MOV      r0,#0
301L0x35c:
302    ADD      sp,sp,#0x40
303    POP      {r4-r12,pc}
304
305.LarmVCM4P10_CAVLCCoeffTokenTables:
306    .word   armVCM4P10_CAVLCCoeffTokenTables-(P0+8)
307.LarmVCM4P10_SuffixToLevel:
308    .word   armVCM4P10_SuffixToLevel-(P1+8)
309.LarmVCM4P10_CAVLCTotalZeros2x2Tables:
310    .word   (armVCM4P10_CAVLCTotalZeros2x2Tables - 4)-(P2+8)
311.LarmVCM4P10_CAVLCTotalZeroTables:
312    .word   (armVCM4P10_CAVLCTotalZeroTables - 4)-(P2+8)
313.LarmVCM4P10_CAVLCRunBeforeTables:
314    .word   (armVCM4P10_CAVLCRunBeforeTables - 4)-(P3+8)
315.LarmVCM4P10_ZigZag_2x2:
316    .word   armVCM4P10_ZigZag_2x2-(P4+8)
317.LarmVCM4P10_ZigZag_4x4:
318    .word   armVCM4P10_ZigZag_4x4-(P4+8)
319
320    .end
321