1/*
2 * Copyright (C) 2007-2008 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *
16 */
17/*
18 *
19 */
20
21    .eabi_attribute 24, 1
22    .eabi_attribute 25, 1
23
24    .arm
25    .fpu neon
26    .text
27
28    .global omxVCM4P10_DequantTransformResidualFromPairAndAdd
29omxVCM4P10_DequantTransformResidualFromPairAndAdd:
30    PUSH     {r4-r12,lr}
31    VPUSH    {d8-d9}
32    SUB      sp,sp,#0x20
33    ADD      r4,sp,#0
34    LDR      r5,[sp,#0x64]
35    MOV      r7,r1
36    MOV      r8,r2
37    MOV      r9,r3
38    CMP      r5,#0
39    BEQ      L0x114
40    MOV      r1,r4
41    BL       armVCM4P10_UnpackBlock4x4  ;//
42    LDR      r1,[sp,#0x60]
43    LDR      r11, .LarmVCM4P10_QPModuloTable
44P0: ADD      r11, pc
45    LDR      r10, .LarmVCM4P10_QPDivTable
46P1: ADD      r10, pc
47    LDR      r2, .LarmVCM4P10_VMatrixU16
48P2: ADD      r2, pc
49    LDRSB    r12,[r11,r1]
50    LDRSB    lr,[r10,r1]
51    LDR      r10, =0x3020504
52    LDR      r1, =0x5040100
53    ADD      r2,r2,r12
54    VDUP.32  d7,r1
55    VDUP.32  d9,r10
56    VDUP.16  d5,lr
57    VLD1.8   {d6},[r2]
58    VTBL.8   d8,{d6},d7
59    VTBL.8   d4,{d6},d9
60    CMP      r8,#0
61    VLD1.16  {d0,d1,d2,d3},[r4]
62    VSHL.U16 d8,d8,d5
63    VSHL.U16 d4,d4,d5
64    BEQ      L1
65    LDRSH    r10,[r8,#0]
66L1:
67    VMUL.I16 d0,d0,d8
68    VMUL.I16 d1,d1,d4
69    VMUL.I16 d2,d2,d8
70    VMUL.I16 d3,d3,d4
71    VMOVNE.16 d0[0],r10
72    VTRN.16  d0,d1
73    VTRN.16  d2,d3
74    VTRN.32  q0,q1
75    VMOV.I16 d4,#0
76    VADD.I16 d5,d0,d2
77    VSUB.I16 d6,d0,d2
78    VHADD.S16 d7,d1,d4
79    VHADD.S16 d8,d3,d4
80    VSUB.I16 d7,d7,d3
81    VADD.I16 d8,d1,d8
82    VADD.I16 d0,d5,d8
83    VADD.I16 d1,d6,d7
84    VSUB.I16 d2,d6,d7
85    VSUB.I16 d3,d5,d8
86    VTRN.16  d0,d1
87    VTRN.16  d2,d3
88    VTRN.32  q0,q1
89    VADD.I16 d5,d0,d2
90    VSUB.I16 d6,d0,d2
91    VHADD.S16 d7,d1,d4
92    VHADD.S16 d8,d3,d4
93    VSUB.I16 d7,d7,d3
94    VADD.I16 d8,d1,d8
95    VADD.I16 d0,d5,d8
96    VADD.I16 d1,d6,d7
97    VSUB.I16 d2,d6,d7
98    VSUB.I16 d3,d5,d8
99    VRSHR.S16 d0,d0,#6
100    VRSHR.S16 d1,d1,#6
101    VRSHR.S16 d2,d2,#6
102    VRSHR.S16 d3,d3,#6
103    B        L0x130
104L0x114:
105    LDRSH    r10,[r8,#0]
106    ADD      r10,r10,#0x20
107    ASR      r10,r10,#6
108    VDUP.16  d0,r10
109    VDUP.16  d1,r10
110    VDUP.16  d2,r10
111    VDUP.16  d3,r10
112L0x130:
113    LDR      r1,[sp,#0x58]
114    LDR      r10,[sp,#0x5c]
115    LDR      r3,[r7],r1
116    LDR      r5,[r7],r1
117    VMOV     d4,r3,r5
118    LDR      r3,[r7],r1
119    LDR      r5,[r7,#0]
120    VMOV     d5,r3,r5
121    VADDW.U8 q3,q0,d4
122    VADDW.U8 q4,q1,d5
123    VQMOVUN.S16 d0,q3
124    VQMOVUN.S16 d1,q4
125    VST1.32  {d0[0]},[r9],r10
126    VST1.32  {d0[1]},[r9],r10
127    VST1.32  {d1[0]},[r9],r10
128    VST1.32  {d1[1]},[r9]
129    MOV      r0,#0
130    ADD      sp,sp,#0x20
131    VPOP     {d8-d9}
132    POP      {r4-r12,pc}
133
134.LarmVCM4P10_QPModuloTable:
135    .word   armVCM4P10_QPModuloTable-(P0+8)
136.LarmVCM4P10_QPDivTable:
137    .word   armVCM4P10_QPDivTable-(P1+8)
138.LarmVCM4P10_VMatrixU16:
139    .word   armVCM4P10_VMatrixU16-(P2+8)
140
141    .end
142
143