1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10 * GNU General Public License for more details.
11 */
12#ifndef __MSMB_ISP__
13#define __MSMB_ISP__
14
15#include <linux/videodev2.h>
16
17#define MAX_PLANES_PER_STREAM 3
18#define MAX_NUM_STREAM 7
19
20#define ISP_VERSION_47        47
21#define ISP_VERSION_46        46
22#define ISP_VERSION_44        44
23#define ISP_VERSION_40        40
24#define ISP_VERSION_32        32
25#define ISP_NATIVE_BUF_BIT    (0x10000 << 0)
26#define ISP0_BIT              (0x10000 << 1)
27#define ISP1_BIT              (0x10000 << 2)
28#define ISP_META_CHANNEL_BIT  (0x10000 << 3)
29#define ISP_SCRATCH_BUF_BIT   (0x10000 << 4)
30#define ISP_STATS_STREAM_BIT  0x80000000
31
32struct msm_vfe_cfg_cmd_list;
33
34enum ISP_START_PIXEL_PATTERN {
35	ISP_BAYER_RGRGRG,
36	ISP_BAYER_GRGRGR,
37	ISP_BAYER_BGBGBG,
38	ISP_BAYER_GBGBGB,
39	ISP_YUV_YCbYCr,
40	ISP_YUV_YCrYCb,
41	ISP_YUV_CbYCrY,
42	ISP_YUV_CrYCbY,
43	ISP_PIX_PATTERN_MAX
44};
45
46enum msm_vfe_plane_fmt {
47	Y_PLANE,
48	CB_PLANE,
49	CR_PLANE,
50	CRCB_PLANE,
51	CBCR_PLANE,
52	VFE_PLANE_FMT_MAX
53};
54
55enum msm_vfe_input_src {
56	VFE_PIX_0,
57	VFE_RAW_0,
58	VFE_RAW_1,
59	VFE_RAW_2,
60	VFE_SRC_MAX,
61};
62
63enum msm_vfe_axi_stream_src {
64	PIX_ENCODER,
65	PIX_VIEWFINDER,
66	PIX_VIDEO,
67	CAMIF_RAW,
68	IDEAL_RAW,
69	RDI_INTF_0,
70	RDI_INTF_1,
71	RDI_INTF_2,
72	VFE_AXI_SRC_MAX
73};
74
75enum msm_vfe_frame_skip_pattern {
76	NO_SKIP,
77	EVERY_2FRAME,
78	EVERY_3FRAME,
79	EVERY_4FRAME,
80	EVERY_5FRAME,
81	EVERY_6FRAME,
82	EVERY_7FRAME,
83	EVERY_8FRAME,
84	EVERY_16FRAME,
85	EVERY_32FRAME,
86	SKIP_ALL,
87	SKIP_RANGE,
88	MAX_SKIP,
89};
90
91enum msm_isp_stats_type {
92	MSM_ISP_STATS_AEC,   /* legacy based AEC */
93	MSM_ISP_STATS_AF,    /* legacy based AF */
94	MSM_ISP_STATS_AWB,   /* legacy based AWB */
95	MSM_ISP_STATS_RS,    /* legacy based RS */
96	MSM_ISP_STATS_CS,    /* legacy based CS */
97	MSM_ISP_STATS_IHIST, /* legacy based HIST */
98	MSM_ISP_STATS_SKIN,  /* legacy based SKIN */
99	MSM_ISP_STATS_BG,    /* Bayer Grids */
100	MSM_ISP_STATS_BF,    /* Bayer Focus */
101	MSM_ISP_STATS_BE,    /* Bayer Exposure*/
102	MSM_ISP_STATS_BHIST, /* Bayer Hist */
103	MSM_ISP_STATS_BF_SCALE,  /* Bayer Focus scale */
104	MSM_ISP_STATS_HDR_BE,    /* HDR Bayer Exposure */
105	MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */
106	MSM_ISP_STATS_AEC_BG,   /* AEC BG */
107	MSM_ISP_STATS_MAX    /* MAX */
108};
109
110/*
111 * @stats_type_mask: Stats type mask (enum msm_isp_stats_type).
112 * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src)
113 * @skip_mode: skip pattern, if skip mode is range only then min/max is used
114 * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE)
115 * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE)
116*/
117struct msm_isp_sw_framskip {
118	uint32_t stats_type_mask;
119	uint32_t stream_src_mask;
120	enum msm_vfe_frame_skip_pattern skip_mode;
121	uint32_t min_frame_id;
122	uint32_t max_frame_id;
123};
124
125enum msm_vfe_testgen_color_pattern {
126	COLOR_BAR_8_COLOR,
127	UNICOLOR_WHITE,
128	UNICOLOR_YELLOW,
129	UNICOLOR_CYAN,
130	UNICOLOR_GREEN,
131	UNICOLOR_MAGENTA,
132	UNICOLOR_RED,
133	UNICOLOR_BLUE,
134	UNICOLOR_BLACK,
135	MAX_COLOR,
136};
137
138enum msm_vfe_camif_input {
139	CAMIF_DISABLED,
140	CAMIF_PAD_REG_INPUT,
141	CAMIF_MIDDI_INPUT,
142	CAMIF_MIPI_INPUT,
143};
144
145struct msm_vfe_fetch_engine_cfg {
146	uint32_t input_format;
147	uint32_t buf_width;
148	uint32_t buf_height;
149	uint32_t fetch_width;
150	uint32_t fetch_height;
151	uint32_t x_offset;
152	uint32_t y_offset;
153	uint32_t buf_stride;
154};
155
156/*
157 * Camif output general configuration
158 */
159struct msm_vfe_camif_subsample_cfg {
160	uint32_t irq_subsample_period;
161	uint32_t irq_subsample_pattern;
162	uint32_t sof_counter_step;
163	uint32_t pixel_skip;
164	uint32_t line_skip;
165};
166
167/*
168 * Camif frame and window configuration
169 */
170struct msm_vfe_camif_cfg {
171	uint32_t lines_per_frame;
172	uint32_t pixels_per_line;
173	uint32_t first_pixel;
174	uint32_t last_pixel;
175	uint32_t first_line;
176	uint32_t last_line;
177	uint32_t epoch_line0;
178	uint32_t epoch_line1;
179	uint32_t hbi_cnt;
180	enum msm_vfe_camif_input camif_input;
181	struct msm_vfe_camif_subsample_cfg subsample_cfg;
182};
183
184struct msm_vfe_testgen_cfg {
185	uint32_t lines_per_frame;
186	uint32_t pixels_per_line;
187	uint32_t v_blank;
188	uint32_t h_blank;
189	enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
190	uint32_t rotate_period;
191	enum msm_vfe_testgen_color_pattern color_bar_pattern;
192	uint32_t burst_num_frame;
193};
194
195enum msm_vfe_inputmux {
196	CAMIF,
197	TESTGEN,
198	EXTERNAL_READ,
199};
200
201enum msm_vfe_stats_composite_group {
202	STATS_COMPOSITE_GRP_NONE,
203	STATS_COMPOSITE_GRP_1,
204	STATS_COMPOSITE_GRP_2,
205	STATS_COMPOSITE_GRP_MAX,
206};
207
208struct msm_vfe_pix_cfg {
209	struct msm_vfe_camif_cfg camif_cfg;
210	struct msm_vfe_testgen_cfg testgen_cfg;
211	struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
212	enum msm_vfe_inputmux input_mux;
213	enum ISP_START_PIXEL_PATTERN pixel_pattern;
214	uint32_t input_format;
215	uint32_t is_split;
216};
217
218struct msm_vfe_rdi_cfg {
219	uint8_t cid;
220	uint8_t frame_based;
221};
222
223struct msm_vfe_input_cfg {
224	union {
225		struct msm_vfe_pix_cfg pix_cfg;
226		struct msm_vfe_rdi_cfg rdi_cfg;
227	} d;
228	enum msm_vfe_input_src input_src;
229	uint32_t input_pix_clk;
230};
231
232struct msm_vfe_fetch_eng_start {
233	uint32_t session_id;
234	uint32_t stream_id;
235	uint32_t buf_idx;
236	uint32_t buf_addr;
237};
238
239struct msm_vfe_axi_plane_cfg {
240	uint32_t output_width; /*Include padding*/
241	uint32_t output_height;
242	uint32_t output_stride;
243	uint32_t output_scan_lines;
244	uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
245	uint32_t plane_addr_offset;
246	uint8_t csid_src; /*RDI 0-2*/
247	uint8_t rdi_cid;/*CID 1-16*/
248};
249
250enum msm_stream_memory_input_t {
251	MEMORY_INPUT_DISABLED,
252	MEMORY_INPUT_ENABLED
253};
254
255struct msm_vfe_axi_stream_request_cmd {
256	uint32_t session_id;
257	uint32_t stream_id;
258	uint32_t vt_enable;
259	uint32_t output_format;/*Planar/RAW/Misc*/
260	enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
261	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
262
263	uint32_t burst_count;
264	uint32_t hfr_mode;
265	uint8_t frame_base;
266
267	uint32_t init_frame_drop; /*MAX 31 Frames*/
268	enum msm_vfe_frame_skip_pattern frame_skip_pattern;
269	uint8_t buf_divert; /* if TRUE no vb2 buf done. */
270	/*Return values*/
271	uint32_t axi_stream_handle;
272	uint32_t controllable_output;
273	uint32_t burst_len;
274	/* Flag indicating memory input stream */
275	enum msm_stream_memory_input_t memory_input;
276};
277
278struct msm_vfe_axi_stream_release_cmd {
279	uint32_t stream_handle;
280};
281
282enum msm_vfe_axi_stream_cmd {
283	STOP_STREAM,
284	START_STREAM,
285	STOP_IMMEDIATELY,
286};
287
288struct msm_vfe_axi_stream_cfg_cmd {
289	uint8_t num_streams;
290	uint32_t stream_handle[MAX_NUM_STREAM];
291	enum msm_vfe_axi_stream_cmd cmd;
292};
293
294enum msm_vfe_axi_stream_update_type {
295	ENABLE_STREAM_BUF_DIVERT,
296	DISABLE_STREAM_BUF_DIVERT,
297	UPDATE_STREAM_FRAMEDROP_PATTERN,
298	UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
299	UPDATE_STREAM_AXI_CONFIG,
300	UPDATE_STREAM_REQUEST_FRAMES,
301	UPDATE_STREAM_ADD_BUFQ,
302	UPDATE_STREAM_REMOVE_BUFQ,
303	UPDATE_STREAM_SW_FRAME_DROP,
304};
305
306enum msm_vfe_iommu_type {
307	IOMMU_ATTACH,
308	IOMMU_DETACH,
309};
310
311enum msm_vfe_buff_queue_id {
312	VFE_BUF_QUEUE_DEFAULT,
313	VFE_BUF_QUEUE_SHARED,
314	VFE_BUF_QUEUE_MAX,
315};
316
317struct msm_vfe_axi_stream_cfg_update_info {
318	uint32_t stream_handle;
319	uint32_t output_format;
320	uint32_t user_stream_id;
321	uint32_t frame_id;
322	enum msm_vfe_frame_skip_pattern skip_pattern;
323	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
324	struct msm_isp_sw_framskip sw_skip_info;
325};
326
327struct msm_vfe_axi_halt_cmd {
328	uint32_t stop_camif;
329	uint32_t overflow_detected;
330	uint32_t blocking_halt;
331};
332
333struct msm_vfe_axi_reset_cmd {
334	uint32_t blocking;
335	uint32_t frame_id;
336};
337
338struct msm_vfe_axi_restart_cmd {
339	uint32_t enable_camif;
340};
341
342struct msm_vfe_axi_stream_update_cmd {
343	uint32_t num_streams;
344	enum msm_vfe_axi_stream_update_type update_type;
345	struct msm_vfe_axi_stream_cfg_update_info
346					update_info[MSM_ISP_STATS_MAX];
347};
348
349struct msm_vfe_smmu_attach_cmd {
350	uint32_t security_mode;
351	uint32_t iommu_attach_mode;
352};
353
354struct msm_vfe_stats_stream_request_cmd {
355	uint32_t session_id;
356	uint32_t stream_id;
357	enum msm_isp_stats_type stats_type;
358	uint32_t composite_flag;
359	uint32_t framedrop_pattern;
360	uint32_t init_frame_drop; /*MAX 31 Frames*/
361	uint32_t irq_subsample_pattern;
362	uint32_t buffer_offset;
363	uint32_t stream_handle;
364};
365
366struct msm_vfe_stats_stream_release_cmd {
367	uint32_t stream_handle;
368};
369struct msm_vfe_stats_stream_cfg_cmd {
370	uint8_t num_streams;
371	uint32_t stream_handle[MSM_ISP_STATS_MAX];
372	uint8_t enable;
373	uint32_t stats_burst_len;
374};
375
376enum msm_vfe_reg_cfg_type {
377	VFE_WRITE,
378	VFE_WRITE_MB,
379	VFE_READ,
380	VFE_CFG_MASK,
381	VFE_WRITE_DMI_16BIT,
382	VFE_WRITE_DMI_32BIT,
383	VFE_WRITE_DMI_64BIT,
384	VFE_READ_DMI_16BIT,
385	VFE_READ_DMI_32BIT,
386	VFE_READ_DMI_64BIT,
387	GET_MAX_CLK_RATE,
388	GET_CLK_RATES,
389	GET_ISP_ID,
390	VFE_HW_UPDATE_LOCK,
391	VFE_HW_UPDATE_UNLOCK,
392	SET_WM_UB_SIZE,
393	SET_UB_POLICY,
394};
395
396struct msm_vfe_cfg_cmd2 {
397	uint16_t num_cfg;
398	uint16_t cmd_len;
399	void __user *cfg_data;
400	void __user *cfg_cmd;
401};
402
403struct msm_vfe_cfg_cmd_list {
404	struct msm_vfe_cfg_cmd2      cfg_cmd;
405	struct msm_vfe_cfg_cmd_list *next;
406	uint32_t                     next_size;
407};
408
409struct msm_vfe_reg_rw_info {
410	uint32_t reg_offset;
411	uint32_t cmd_data_offset;
412	uint32_t len;
413};
414
415struct msm_vfe_reg_mask_info {
416	uint32_t reg_offset;
417	uint32_t mask;
418	uint32_t val;
419};
420
421struct msm_vfe_reg_dmi_info {
422	uint32_t hi_tbl_offset; /*Optional*/
423	uint32_t lo_tbl_offset; /*Required*/
424	uint32_t len;
425};
426
427struct msm_vfe_reg_cfg_cmd {
428	union {
429		struct msm_vfe_reg_rw_info rw_info;
430		struct msm_vfe_reg_mask_info mask_info;
431		struct msm_vfe_reg_dmi_info dmi_info;
432	} u;
433
434	enum msm_vfe_reg_cfg_type cmd_type;
435};
436
437enum msm_isp_buf_type {
438	ISP_PRIVATE_BUF,
439	ISP_SHARE_BUF,
440	MAX_ISP_BUF_TYPE,
441};
442
443struct msm_isp_buf_request {
444	uint32_t session_id;
445	uint32_t stream_id;
446	uint8_t num_buf;
447	uint32_t handle;
448	enum msm_isp_buf_type buf_type;
449};
450
451struct msm_isp_qbuf_plane {
452	uint32_t addr;
453	uint32_t offset;
454	uint32_t length;
455};
456
457struct msm_isp_qbuf_buffer {
458	struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
459	uint32_t num_planes;
460};
461
462struct msm_isp_qbuf_info {
463	uint32_t handle;
464	int32_t buf_idx;
465	/*Only used for prepare buffer*/
466	struct msm_isp_qbuf_buffer buffer;
467	/*Only used for diverted buffer*/
468	uint32_t dirty_buf;
469};
470
471struct msm_isp_clk_rates {
472	uint32_t nominal_rate;
473	uint32_t high_rate;
474};
475
476struct msm_vfe_axi_src_state {
477	enum msm_vfe_input_src input_src;
478	uint32_t src_active;
479	uint32_t src_frame_id;
480};
481
482enum msm_isp_event_mask_index {
483	ISP_EVENT_MASK_INDEX_STATS_NOTIFY		= 0,
484	ISP_EVENT_MASK_INDEX_ERROR			= 1,
485	ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT		= 2,
486	ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE		= 3,
487	ISP_EVENT_MASK_INDEX_REG_UPDATE			= 4,
488	ISP_EVENT_MASK_INDEX_SOF			= 5,
489	ISP_EVENT_MASK_INDEX_BUF_DIVERT			= 6,
490	ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY		= 7,
491	ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE		= 8
492};
493
494
495#define ISP_EVENT_SUBS_MASK_NONE			0
496
497#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \
498			(1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
499
500#define ISP_EVENT_SUBS_MASK_ERROR \
501			(1 << ISP_EVENT_MASK_INDEX_ERROR)
502
503#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \
504			(1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
505
506#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \
507			(1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
508
509#define ISP_EVENT_SUBS_MASK_REG_UPDATE \
510			(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
511
512#define ISP_EVENT_SUBS_MASK_SOF \
513			(1 << ISP_EVENT_MASK_INDEX_SOF)
514
515#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \
516			(1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
517
518#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \
519			(1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
520
521#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \
522			(1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
523
524enum msm_isp_event_idx {
525	ISP_REG_UPDATE        = 0,
526	ISP_EPOCH_0           = 1,
527	ISP_EPOCH_1           = 2,
528	ISP_START_ACK         = 3,
529	ISP_STOP_ACK          = 4,
530	ISP_IRQ_VIOLATION     = 5,
531	ISP_STATS_OVERFLOW    = 6,
532	ISP_BUF_DONE          = 7,
533	ISP_FE_RD_DONE        = 8,
534	ISP_IOMMU_P_FAULT     = 9,
535	ISP_ERROR             = 10,
536	ISP_PING_PONG_MISMATCH = 11,
537	ISP_REG_UPDATE_MISSING = 12,
538	ISP_EVENT_MAX         = 13
539};
540
541#define ISP_EVENT_OFFSET          8
542#define ISP_EVENT_BASE            (V4L2_EVENT_PRIVATE_START)
543#define ISP_BUF_EVENT_BASE        (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
544#define ISP_STATS_EVENT_BASE      (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
545#define ISP_CAMIF_EVENT_BASE      (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
546#define ISP_STREAM_EVENT_BASE     (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
547#define ISP_EVENT_REG_UPDATE      (ISP_EVENT_BASE + ISP_REG_UPDATE)
548#define ISP_EVENT_EPOCH_0         (ISP_EVENT_BASE + ISP_EPOCH_0)
549#define ISP_EVENT_EPOCH_1         (ISP_EVENT_BASE + ISP_EPOCH_1)
550#define ISP_EVENT_START_ACK       (ISP_EVENT_BASE + ISP_START_ACK)
551#define ISP_EVENT_STOP_ACK        (ISP_EVENT_BASE + ISP_STOP_ACK)
552#define ISP_EVENT_IRQ_VIOLATION   (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
553#define ISP_EVENT_STATS_OVERFLOW  (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
554#define ISP_EVENT_ERROR           (ISP_EVENT_BASE + ISP_ERROR)
555#define ISP_EVENT_SOF             (ISP_CAMIF_EVENT_BASE)
556#define ISP_EVENT_EOF             (ISP_CAMIF_EVENT_BASE + 1)
557#define ISP_EVENT_BUF_DONE        (ISP_EVENT_BASE + ISP_BUF_DONE)
558#define ISP_EVENT_BUF_DIVERT      (ISP_BUF_EVENT_BASE)
559#define ISP_EVENT_STATS_NOTIFY    (ISP_STATS_EVENT_BASE)
560#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
561#define ISP_EVENT_FE_READ_DONE    (ISP_EVENT_BASE + ISP_FE_RD_DONE)
562#define ISP_EVENT_IOMMU_P_FAULT   (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
563#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
564#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
565#define ISP_EVENT_STREAM_UPDATE_DONE   (ISP_STREAM_EVENT_BASE)
566
567/* The msm_v4l2_event_data structure should match the
568 * v4l2_event.u.data field.
569 * should not exceed 64 bytes */
570
571struct msm_isp_buf_event {
572	uint32_t session_id;
573	uint32_t stream_id;
574	uint32_t handle;
575	uint32_t output_format;
576	int8_t buf_idx;
577};
578struct msm_isp_stats_event {
579	uint32_t stats_mask;                        /* 4 bytes */
580	uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX];  /* 11 bytes */
581};
582
583struct msm_isp_stream_ack {
584	uint32_t session_id;
585	uint32_t stream_id;
586	uint32_t handle;
587};
588
589enum msm_vfe_error_type {
590	ISP_ERROR_NONE,
591	ISP_ERROR_CAMIF,
592	ISP_ERROR_BUS_OVERFLOW,
593	ISP_ERROR_RETURN_EMPTY_BUFFER,
594	ISP_ERROR_FRAME_ID_MISMATCH,
595	ISP_ERROR_MAX,
596};
597
598struct msm_isp_error_info {
599	enum msm_vfe_error_type err_type;
600	uint32_t session_id;
601	uint32_t stream_id;
602};
603
604struct msm_isp_output_info {
605	uint32_t regs_not_updated;
606	uint32_t output_err_mask;
607	uint16_t stream_framedrop_mask;
608	uint32_t stats_framedrop_mask;
609	uint32_t axi_updating_mask;
610};
611
612struct msm_isp_event_data {
613	/*Wall clock except for buffer divert events
614	 *which use monotonic clock
615	 */
616	struct timeval timestamp;
617	/* Monotonic timestamp since bootup */
618	struct timeval mono_timestamp;
619	uint32_t frame_id;
620	union {
621		struct msm_isp_stats_event stats;
622		struct msm_isp_buf_event buf_done;
623		struct msm_isp_error_info error_info;
624		struct msm_isp_output_info output_info;
625	} u; /* union can have max 52 bytes */
626};
627
628#ifdef CONFIG_COMPAT
629struct msm_isp_event_data32 {
630	struct compat_timeval timestamp;
631	struct compat_timeval mono_timestamp;
632	uint32_t frame_id;
633	union {
634		struct msm_isp_stats_event stats;
635		struct msm_isp_buf_event buf_done;
636		struct msm_isp_error_info error_info;
637		struct msm_isp_output_info output_info;
638	} u;
639};
640#endif
641
642#define V4L2_PIX_FMT_QBGGR8  v4l2_fourcc('Q', 'B', 'G', '8')
643#define V4L2_PIX_FMT_QGBRG8  v4l2_fourcc('Q', 'G', 'B', '8')
644#define V4L2_PIX_FMT_QGRBG8  v4l2_fourcc('Q', 'G', 'R', '8')
645#define V4L2_PIX_FMT_QRGGB8  v4l2_fourcc('Q', 'R', 'G', '8')
646#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
647#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
648#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
649#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
650#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
651#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
652#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
653#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
654#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
655#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
656#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
657#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
658#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
659#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
660#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
661#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
662#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
663#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
664#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
665#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/
666#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/
667#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/
668#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/
669
670#define VIDIOC_MSM_VFE_REG_CFG \
671	_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2)
672
673#define VIDIOC_MSM_ISP_REQUEST_BUF \
674	_IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request)
675
676#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
677	_IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info)
678
679#define VIDIOC_MSM_ISP_RELEASE_BUF \
680	_IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request)
681
682#define VIDIOC_MSM_ISP_REQUEST_STREAM \
683	_IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd)
684
685#define VIDIOC_MSM_ISP_CFG_STREAM \
686	_IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd)
687
688#define VIDIOC_MSM_ISP_RELEASE_STREAM \
689	_IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd)
690
691#define VIDIOC_MSM_ISP_INPUT_CFG \
692	_IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg)
693
694#define VIDIOC_MSM_ISP_SET_SRC_STATE \
695	_IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state)
696
697#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
698	_IOWR('V', BASE_VIDIOC_PRIVATE+9, \
699	struct msm_vfe_stats_stream_request_cmd)
700
701#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
702	_IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd)
703
704#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
705	_IOWR('V', BASE_VIDIOC_PRIVATE+11, \
706	struct msm_vfe_stats_stream_release_cmd)
707
708#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \
709	_IOWR('V', BASE_VIDIOC_PRIVATE+12, enum msm_vfe_input_src)
710
711#define VIDIOC_MSM_ISP_UPDATE_STREAM \
712	_IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd)
713
714#define VIDIOC_MSM_VFE_REG_LIST_CFG \
715	_IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list)
716
717#define VIDIOC_MSM_ISP_SMMU_ATTACH \
718	_IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd)
719
720#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \
721	_IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd)
722
723#define VIDIOC_MSM_ISP_AXI_HALT \
724	_IOWR('V', BASE_VIDIOC_PRIVATE+17, struct msm_vfe_axi_halt_cmd)
725
726#define VIDIOC_MSM_ISP_AXI_RESET \
727	_IOWR('V', BASE_VIDIOC_PRIVATE+18, struct msm_vfe_axi_reset_cmd)
728
729#define VIDIOC_MSM_ISP_AXI_RESTART \
730	_IOWR('V', BASE_VIDIOC_PRIVATE+19, struct msm_vfe_axi_restart_cmd)
731
732#define VIDIOC_MSM_ISP_FETCH_ENG_START \
733	_IOWR('V', BASE_VIDIOC_PRIVATE+20, struct msm_vfe_fetch_eng_start)
734
735#define VIDIOC_MSM_ISP_DEQUEUE_BUF \
736	_IOWR('V', BASE_VIDIOC_PRIVATE+21, struct msm_isp_qbuf_info)
737
738#endif /* __MSMB_ISP__ */
739