| b0cc55f29831638069407a4c1a5c809b26902ab6 |
|
02-Dec-2016 |
Ben Widawsky <ben@bwidawsk.net> |
i965: Fix SURFACE_STATE to handle non-zero aux offsets
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Stone <daniels@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 99c019e1d41eb72c5ca9e0ae4b263acd6e6c214f |
|
05-Jan-2017 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix textureGather with RG32I/UI on Gen7.
According to the "Gather4 R32G32_FLOAT Bug" internal documentation
page, the R32G32_UINT and R32G32_SINT formats are affected by the
same bug as R32G32_FLOAT. Applying the same workarounds should be
viable - apparently the R32G32_FLOAT_LD format shouldn't corrupt
integer data which is NaN or other sketchy floating point values.
One irritating caveat is that, because it's a FLOAT format, the
alpha channel or any set to SCS_ONE return 0x3f8 (1.0) rather than
integer 1. So we need shader code to whack those channels to 1.
Fixes GL45-CTS.texture_gather.plain-gather-int-cube-rg on Haswell.
v2: Fix swizzle component zeroing (caught by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c46a630000a2539e38a448f24a456397ce201a2e |
|
03-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
mesa: make _CurrentFragmentProgram a gl_program struct pointer
Making this point to a gl_program struct rather than a gl_shader_program
struct will allow use to later also make the CurrentProgram array hold
gl_program structs which in turn will allow for code simpilifcation.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d3b2ee6b4975bbb8eb960b20329461136a3e1a3f |
|
05-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: pass gl_program to brw_upload_ubo_surfaces()
There is no need to pass gl_linked_shader anymore.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f5bc127b2f140213a8ceb58c4ed2d9b9a4c0449c |
|
05-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/glsl/i965: move ShaderStorageBlocks to gl_program
Having it here rather than in gl_linked_shader allows us to simplify
the code.
Also it is error prone to depend on the gl_linked_shader for programs
in current use because a failed linking attempt will free infomation
about the current program. In i965 we could be trying to recompile
a shader variant but may have lost some required fields.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f62eb6c7eb22cd97c691ebdb5f25eb5fe8e9ed11 |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/glsl/i965: set num_ssbos directly in shader_info
Here we also remove the duplicate field in gl_linked_shader and always
get the value from shader_info instead.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0e7eec1ab5f27ced1aa4b2d77c2c63512d299694 |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/glsl/i965: move per stage UniformBlocks to gl_program
This will help allow us to store pointers to gl_program structs in the
CurrentProgram array resulting in a bunch of code simplifications.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b792c3897927c1d89968bc0040faef02ec976184 |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/glsl/i965: set num_ubos directly in shader_info
This also removes the duplicate field in gl_linked_shader, and
gets num_ubos from shader_info instead.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a1da57c19c27505b9eab4792355f2f1b5c774a0a |
|
04-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/glsl/i965: move ImageUnits and ImageAccess fields to gl_program
Having it here rather than in gl_linked_shader allows us to simplify
the code.
Also it is error prone to depend on the gl_linked_shader for programs
in current use because a failed linking attempt will free infomation
about the current program. In i965 we could be trying to recompile
a shader variant but may have lost some required fields.
We drop the memset on ImageUnits because gl_program is already
created using rzalloc().
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ea2c4196004980a513aee10b606bc1aa74d003c5 |
|
09-Jun-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Add plumbing for fast clear layer/level details
Until now fast clear has been supported only for non-layered and
non-mipmapped buffers. However, from gen8 onwards there is hardware
support also for layered/mipmapped. Once this is enabled, fast clear
operations target specific layer/level and call for the state to be
tracked in the same granularity. This is the first step providing
the details from callers to the state tracking.
Patch introduces new interface for reading and writing the state
hiding the upcoming bookkeeping changes in the call sites. There is
bunch of sanity checks added that will be relaxed per hardware
generation later on when the actual functionality is enabled.
v2: Rebased on top current master setting the state in
blorp_surf_for_miptree().
v3: Replace open-coded resolved check in surface state emission
with intel_miptree_has_color_unresolved().
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 71d48d6f42c3ae03b797c25d58f2f1f4dcd8fc29 |
|
05-Jul-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Refactor lossless compression state tracking
Essentially this moves fast clear state update away from surface
state setup into brw_postdraw_set_buffers_need_resolve() that gets
called just after draw submission.
Calling intel_miptree_used_for_rendering() can be drop for gen6
and earlier as it is no-op.
v2: Rebased on top current master setting the state in
blorp_surf_for_miptree().
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c20564ae3ec2b5ac6bee23751d53a92b2dc09067 |
|
11-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
glsl/i965: move per stage AtomicBuffers list to gl_program
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 67b9c263425b748a292606dee079c46d87c48c3b |
|
27-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get num_abos from shader_info rather than gl_linked_shader
This is a step towards freeing gl_linked_shader after linking.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ba40c8b03cb5250af771c50ff785bd5ec293e3c1 |
|
27-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get num_images from shader_info rather than gl_linked_shader
This is a step towards freeing gl_linked_shader after linking.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0272f76741e6311aa12a79fa24c3ace323236941 |
|
16-Nov-2016 |
Ben Widawsky <ben@bwidawsk.net> |
Partial revert "i965: "Fix" aux offsets"
This partially reverts commit 0d241085f723402120b4b47e939fe77020a16d80.
HiZ buffer cannot do this properly now, and it's not required, so remove
it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0d241085f723402120b4b47e939fe77020a16d80 |
|
16-Nov-2016 |
Ben Widawsky <ben@bwidawsk.net> |
i965: "Fix" aux offsets
When 1 BO is used for aux data, it needs to point to the correct offset,
which will not be the BOs offset but instead an offset from the BOs
offset. Since today there are always multiple BOs for aux, this doesn't
actually change anything.
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b3bc8068550d2efc98c49d7d82a6aa40154f76fe |
|
20-Sep-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel/isl: Add some basic info about RENDER_SURFACE_STATE to isl_device
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3b0c2bc41755db2f2cef487f367e697aa57dcd78 |
|
21-Oct-2016 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965/gen9: Add HiZ auxiliary buffer support
The original functionality this patch introduces was authored by a patch from
Ken (the commit subject was the same). Since I ended up changing so many patches
in the code before this one, I had some non-trivial decisions to make, and I
didn't feel it was appropriate to keeps Ken's name as author (mostly because he
might not like what I've done). Ken's original patch was like 2 LOC :-)
In either case, some credit needs to go to Ken, and to Jordan for a few small
other changes in that original patch.
v2: Back to a smaller diff now that ISL handles most of the actual
programming (Lionel)
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> (v1)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v2)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 36d1c555edef238648cf18f3a3adb4ea3805f1b9 |
|
21-Oct-2016 |
Ben Widawsky <benjamin.widawsky@intel.com> |
i965: Drop the aux mt when not used
This patch will preserve the BO & offset, and not the miptree for the
aux_mcs buffer. Eventually it might make sense to pull put the sizing
function in miptree creation, but for now this should be sufficient
and not too hideous.
v2: Save BO's offset too (Lionel)
v3: Squash previous patch storing the size of the allocated aux buffer
(Lionel)
Fix memory leak with mcs_buf->bo (Lionel)
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> (v1)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v2)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0041169cacb300a882b4dc38cd341f98bf2a7c38 |
|
21-Oct-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Wrap MCS miptree in intel_miptree_aux_buffer
This will allow us to treat HiZ and MCS the same when using as an
auxiliary surface buffer.
v2: (Ben) Minor rebase conflict resolution.
Rename mcs_buf to aux_buf to address upcoming change for hiz specific buffers.
That second thing is essentially a squash of:
i965/gen8: Use intel_miptree_aux_buffer for auxiliary buffer - which didn't need
to be separate in my opinion.
v3: rebase on master (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>a (v2)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v3)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 13d0cf57bf069644e4a1d8b2ddc3c5810e84cc67 |
|
18-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: replace brw_fragment_program with brw_program
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3423488d55b9c483fcdb3996eb89b424c1031d24 |
|
19-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
st/mesa/r200/i915/i965: eliminate gl_fragment_program
Here we move OriginUpperLeft and PixelCenterInteger into gl_program
all other fields have been replace by shader_info.
V2: Don't use anonymous union/structs to hold vertex/fragment fields
suggested by Ian.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 17e28a1571b6141368fefc84cc8b0a3b4e52f8ee |
|
19-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965/mesa/st/swrast: set fs shader_info directly and switch to using it
Note we access shader_info from the program struct rather than the
nir_shader pointer because shader cache won't create a nir_shader.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e1af20f18a86f52a9640faf2d4ff8a71b0a4fa9b |
|
13-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
nir/i965/anv/radv/gallium: make shader info a pointer
When restoring something from shader cache we won't have and don't
want to create a nir_shader this change detaches the two.
There are other advantages such as being able to reuse the
shader info populated by GLSL IR.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d11a63d6e69298f34bb08334f637c100f6989ca7 |
|
08-Oct-2016 |
Xu,Randy <randy.xu@intel.com> |
i965: solve cubemap negative x/y/z faces buffer offset issue in dEQP.
Add the miptree level/slice x/y_offset when count the surface offset
in brw_emit_surface_state. The surface offset has two parts, one is
from mt->offset, which should be 32 aligned in width/height for tiled
buffer; another is from mt->level[current_level].slice[current_slice].
x/y_offset.
This fix will solve 12 deqp failure
dEQP-EGL.functional.image.create.gles2_cubemap_negative_*_texture
Signed-off-by: Xu,Randy <randy.xu@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b526a9b708b48c3d1c394783cba99f11eb17d0b9 |
|
05-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get outputs read from nir info
This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.
This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ee829cba8ed7941631e214ae8557c5af9fa667b4 |
|
05-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: get uses texture gather from nir info
This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.
This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a85a8ecd32202b22e560bdf714b5715a168cc76e |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->cs.prog_data pointer.
Just say no to:
- brw->cs.base.prog_data = &brw->cs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_cs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 16d5536e55aed2aad0596e9385f1962b4ca5db2b |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->wm.prog_data pointer.
Just say no to:
- brw->wm.base.prog_data = &brw->wm.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_wm_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| bab1c056344854ca2e147bafd313723eb3a32ecb |
|
22-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing BRW_CS_PROG_DATA to CS work group surface atom.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f2b9b0c730e345bcffa9eadabb25af3ab02642f2 |
|
22-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing BRW_NEW_FS_PROG_DATA to render target reads.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| bc24590f0c579a2528fd94eb8d40dd4ce12eba29 |
|
22-Sep-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
intel/i965: make gen_device_info mutable
Make gen_device_info a mutable structure so we can update the fields that
can be refined by querying the kernel (like subslices and EU numbers).
This patch does not make any functional change, it just makes
gen_get_device_info() fill a structure rather than returning a const
pointer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9694b23f66f4c41407289fb7d3ff25321042ef49 |
|
01-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename intelScreen to screen.
"intelScreen" is wordy and also doesn't fit our style guidelines.
"screen" is shorter, which is nice, because we use it fairly often.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7ddb21708c800dfbe3cea2df6aaaf7aed852761b |
|
28-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel/isl: Add an isl_swizzle structure and use it for isl_view swizzles
This should be more compact than the enum isl_channel_select[4] that we
were using before. It's also very convenient because we already had such a
structure in the Vulkan driver we just needed to pull it over.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6939532593efb5f6dc0ddb79081989f31d0a6851 |
|
07-Sep-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Add sanity check for non-compressible texture views
v2: Fix missing inline declaration
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1b6fcc08df677725cf5ee4e913ebfbd2bff27e22 |
|
31-Aug-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/rbc: Consult rb settings for texture surface setup
Once mcs buffer gets allocated without delay for lossless
compression (same as we do for msaa), one gets regression in:
GL45-CTS.texture_barrier_ARB.same-texel-rw
Setting the auxiliary surface for both sampling engine and data
port seems to fix this. I haven't found any hardware documentation
backing this though.
v2 (Jason): Prepare also for the case where surface is sampled with
non-compressible format forcing also rendering without
compression.
v3: Split asserts and decision making.
v4: Detailed comment provided by Jason explaining the need for using
auxiliary buffer for texturing when the same surface is also
used as render target.
Added check for existence of renderbuffer before considering if
underlying miptree matches.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 22d9a4824baf0bf89bb8e39025ad01fecb213888 |
|
04-Sep-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Track non-compressible sampling of renderbuffers
v3:
- Actually set the flags when needed instead of falsely
overwriting them (Jason).
- Use more generic name for flag (dropped RENDERBUFFER)
- Consult also shader images
v4:
- Consult only lossless compressd shader images
v5:
- Check the existence of renderbuffer before considering
if it matches the given miptree
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1f51217d99e7eb70a62b2611cd1b70f9b5a40fcf |
|
05-Sep-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Replace boolean rb surface state setup argument with flags
And add plumbing to provide it all the way to surface state emitter.
This is not used yet but will be in subsequent patches to carry
additional constraints.
v2 (Jason): Use uint32_t instead of int as the type
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 527f37199929932300acc1688d8160e1f3b1d753 |
|
23-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel: s/brw_device_info/gen_device_info/
Generated by:
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 751682434ecb0489df3945f88e565079ecbe9f31 |
|
12-Jun-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/gen7: Use R8_UINT stencil copy when sampling the stencil texture
v2:
* Check gen <= 7, rather than gen == 7. (Ian)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 40241d40d0a481f9f1cd112d2d48dadf1ec6ad0f |
|
28-Jun-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable hardware blending if advanced blending is in use.
We'll do blending in the shader in this case, so just disable the
hardware blending.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 786108e7b27e4728353d69ff60aa046987859d8e |
|
01-Jul-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Upload surface state for non-coherent framebuffer fetch.
This iterates over the list of attached render buffers and binds
appropriate surface state structures to the binding table block
allocated for shader framebuffer read.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| dc96968dbf7b359a24a991def16e382379f4b11a |
|
22-Jul-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Implement support for overriding the texture target in brw_emit_surface_state.
This allows the caller to bind a miptree using a texture target other
than the one it it was created with. The code should work even if the
memory layouts of the specified and original targets don't match, as
long as the caller only intends to access a single slice of the
miptree structure.
This will be exploited by the next commit in order to support
non-coherent framebuffer fetch of a single layer of a 3D texture
(since some generations lack the minimum array element control for 3D
textures bound to the sampler unit), and multiple layers of a 1D array
texture (since binding it as an actual 1D array texture would require
state-dependent recompiles because the same shader couldn't
simultaneously work for 1D and 2D array textures due to the different
texel fetch coordinate ordering).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 49ea2bd17500cbe3cc5f39b59162eaae1278167d |
|
19-Aug-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Massage argument list of brw_emit_surface_state().
This commit does three different things in a single pass in order to
keep the amount of churn low: Remove the for_gather boolean argument
which was unused, pass the isl_view argument by value rather than by
reference since I'll have to modify it from within the function, and
add a target argument to allow callers to bind textures using a target
other than the original. The prototype of the function now looks
like:
void brw_emit_surface_state(struct brw_context *brw,
struct intel_mipmap_tree *mt,
GLenum target, struct isl_view view,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains);
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 96ea753d9eb802c95544c79035e89df38daf15f7 |
|
27-May-2016 |
Dave Airlie <airlied@redhat.com> |
i965: report bound buffer size not underlying buffer size for image size (v2)
This seems to make sense, the image is bound to a subset of the buffer
so the image size should be from the bound size not the underlying
object.
This fixes:
GL44-CTS.shader_image_size.advanced-nonMS-fs-int
v2: get mininum of the two values, same as we write to the hw.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4adad99cfbefc66ddfc65c2143c2bf402fc3426c |
|
07-Jun-2016 |
Dave Airlie <airlied@redhat.com> |
i965: use new subroutine index uploader.
This plugs the subroutine index updates into the i965 backend,
where it loads constants.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Acked-by: Andres Gomez <agomez@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d81435336510ee00b59d5fb538ca5fb065abd579 |
|
28-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/blorp: Use the generic surface state path for gen8 textures
Now that the generic blorp path uses base level/layer, there's no need to
make gen8 special.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 027cbf00f248bda325521db8f56a3718898da46b |
|
02-Aug-2016 |
Mathias Fröhlich <mathias.froehlich@web.de> |
util: Move _mesa_fsl/util_last_bit into util/bitscan.h
As requested with the initial creation of util/bitscan.h
now move other bitscan related functions into util.
v2: Split into two patches.
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 96dfed49e47eac7afc100e5b8d3b316dd6652fb6 |
|
19-Jul-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Stop muging cube array lengths by 6
From the Sky Lake PRM:
"For SURFTYPE_CUBE: For Sampling Engine Surfaces and Typed Data Port
Surfaces, the range of this field is [0,340], indicating the number of
cube array elements (equal to the number of underlying 2D array elements
divided by 6). For other surfaces, this field must be zero."
In other words, the depth field for cube maps is in number of cubes not
number of 2-D slices so we need to divide by 6. ISL will do this correctly
for us assuming that we provide it with the correct array bounds which it
expects to be in 2-D slices. It appears as if we've been doing this wrong
ever since we first added cube map arrays for Sandy Bridge and the change
to ISL made things slightly worse. While we're at it, we now need to remoe
the shader hacks we've always done since they were only needed because we
were setting the depth field six times too large.
v2: Fix the vec4 backend as well (not sure how I missed this).
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 89873c9b0860067ce01ec92b11b4f4242ef450c4 |
|
19-Jul-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use tex_mocs instead of rb_mocs for GL images.
Fixes a 10-20% performance regression in OglCSDof caused by commit
5a8c89038abab0184ea72664ab390ec6ca58b4d6, which made images (in the
image load/store sense) use BDW_MOCS_PTE instead of BDW_MOCS_WB.
This seems sketchy, as the default PTE value is supposed to be
WB LLC eLLC, which is the same as our MOCS WB setting. It's only
supposed to change when using a surface for display, which won't
ever happen for images. Something may be wrong in the kernel...
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 905d7dc4d164b7ccc287b390a5b2492da3e0fd8b |
|
18-Jul-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Skip update_texture_surface when the plane doesn't exist
Thanks to rebase fail, recent surface state changes (commits 7e951cd56,
8521ce1a7, and 69c0dc5c53) effectively reverted 727a9b24933 and 367cf3a2e3e
which was unintentional. This should bring it back.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 745f5778f3f0faa1fc2eae22edc489811673d70f |
|
11-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/context: Remove some unnecessary vfuncs
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 305044c5b14b635676d1585b6a1822d11fdcf0a6 |
|
10-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Get rid of gen6_surface_state.c
The only useful thing left was gen6_init_vtable_surface_functions which we
can easily put in brw_wm_surface_state.c.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 16fb285946c94b0b1edb295ca45fa4985f7a240a |
|
10-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Use ISL for emitting buffer surface states
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ee229d1b9c9530a2a973c304490e7c17f7305340 |
|
10-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/state: Account for the element size in emit_buffer_surface_state
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 69c0dc5c53e565c7c0a95501e5626e01083ca855 |
|
09-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/gen4-6: Use the generic ISL-based path for texture surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 09b5a71517fadd6c20b72e7ad9ea1f7539c93a42 |
|
10-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/state: Add generic surface update functions based on ISL
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1abb37baa072d16d25dd6165f5c30b1f189fd490 |
|
07-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/surface_state: Rename brw_update to gen4_update
We're about to add generic versions which work across gens and those should
have the brw name.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5a8c89038abab0184ea72664ab390ec6ca58b4d6 |
|
09-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/state: Use ISL for emitting image surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5cf665afa1250d50856130f889570f7227f20eb0 |
|
07-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/state: Add a helper for emitting a surface state using isl
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1fb8c6df884c2a17cf980c4ea32db4c214903b55 |
|
30-Jun-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
glsl/mesa: split gl_shader in two
There are two distinctly different uses of this struct. The first
is to store GL shader objects. The second is to store information
about a shader stage thats been linked.
The two uses actually share few fields and there is clearly confusion
about their use. For example the linked shaders map one to one with
a program so can simply be destroyed along with the program. However
previously we were calling reference counting on the linked shaders.
We were also creating linked shaders with a name even though it
is always 0 and called the driver version of the _mesa_new_shader()
function unnecessarily for GL shader objects.
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 367cf3a2e3e51466429a6446ef14ed398a5fb948 |
|
12-Jun-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Use miptree to decide format on multi-plane images for gen < 7
This wasn't handled correctly for multi-plane images on gen < 7 in
727a9b24933d384f5440ed4318fb720ed11d6dd1.
Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96674
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 727a9b24933d384f5440ed4318fb720ed11d6dd1 |
|
12-Jun-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Skip update_texture_surface when the plane doesn't exist
Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96607
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2a1cc94d27c80929d91e38b4843333a5408d563e |
|
11-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/gen4: Subtract 1 from buffer sizes
The PRM states that the values put in Width, Height, and Depth should be
various bits from the value size - 1. We seem to have done this wrong
more-or-less from the start.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e8580b8f981a48dd481c62292c7d618a4860dfad |
|
10-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Remove fake W-tiled render target support
This hasn't been used since 1cfb4bc890b8 where we deleted the meta stencil
blit path.
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0f9cd74aab021da81a7e5a2f0fbf66213471628f |
|
22-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/gen4-6: Handle gl_texture_object::BaseLevel and MinLayer correctly
This is basically a direct translation of what we do for gen7.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ee39d3ba918de9d52d79bdee6db2c120bcf0f28e |
|
22-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/gen4: Pull texture formats from the texture object not the miptree
This makes texture views sort-of work. It doesn't add full texture view
support for gen4-5 but it is enough to fix the GL_ARB_copy_image formats
piglit test on Iron Lake.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 037ce5d7343829a69ec9c7361a0964bc1366b019 |
|
09-Jun-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Emit surface states for extra planes prior to gen8
When Kristian implemented GL_TEXTURE_EXTERNAL_OES, he hooked it up for gen8
but not for gen7 or earlier. It all works, we just need to emit the states
for the extra planes.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 44997fc0c1cc7f24216e3b1c5d954919df946ee5 |
|
02-May-2016 |
Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com> |
i965: Support textures with multiple planes
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6d5ce1b0433f4cbc5cd88b4bfeaf4cdcba6beda8 |
|
22-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make all atoms to track BRW_NEW_BLORP by default
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 541e6c05000b87cee02d5f8e1adc7973c2a2deea |
|
16-Apr-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/surface_state: Use libisl functions for image format lowering
This lets us delete some redundant code and keep all of the
image_load_store format lowering logic in one place: libisl.
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8b2332e3d11dc047e11bc84a4f8da45ccfb6013b |
|
07-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Allow texture surface state setup to be used by blorp
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9e30d66b7c9e7428ad15b6274694a7a1ceee68ae |
|
12-Feb-2016 |
Francisco Jerez <currojerez@riseup.net> |
i965: Reupload push and pull constants when we get new shader image unit state.
Fixes several of the
"dEQP-GLES31.functional.image_load_store*load_store*single_layer" dEQP
tests that use image formats we implement using untyped surface
messages.
Cc: mesa-stable@lists.freedesktop.org
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f275c61c30cbd389f9dac5223cc3904b3fe11e3e |
|
10-Feb-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split brw_upload_texture_surfaces into compute/render atoms.
When uploading state for the compute pipeline, we don't want to
look at VS/TCS/TES/GS/FS programs, as they might be stale, and
aren't relevant anyway. Likewise, the render pipeline shouldn't
look at CS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 14f21f53d50ecd6e2803b2326a90e93aceacfe24 |
|
05-Jan-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
i965/wm: use binding size for ubo/ssbo when automatic size is unset
This fixes the same tests that commit 8cf2e892f was attempting to fix:
ES31-CTS.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-std430-vec-bindrangeOffset
ES31-CTS.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-std430-vec-bindrangeSize
as confirmed by Samuel.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a1d664a0b7dbd8bbab0ff7a179e8960c25a52c0b |
|
05-Jan-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
Revert "i965/wm: use proper API buffer size for the surfaces."
This reverts commit 8cf2e892fca20c4776b4a07c39918343cb2d4e0e. It's
entirely bogus to attempt to store anything about the binding in the
buffer object itself, which might be bound any number of times.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8cf2e892fca20c4776b4a07c39918343cb2d4e0e |
|
15-Dec-2015 |
Samuel Iglesias Gonsálvez <siglesias@igalia.com> |
i965/wm: use proper API buffer size for the surfaces.
Commit 5bb5eeea fixes a bug indicating that the surfaces should have the
API buffer size. Hovewer it picked the wrong value.
This patch adds a new variable, which takes into account
glBindBufferRange() values. This patch fixes the following CTS
regressions:
ES31-CTS.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-std430-vec-bindrangeOffset
ES31-CTS.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-std430-vec-bindrangeSize
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f46dbfaed914e0e3463f3a28fc877695cd7e7834 |
|
18-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Consolidate BRW_NEW_TESS_{CTRL,EVAL}_PROGRAM flags.
For several reasons, I don't think it's particularly useful to have
separate flags:
1. Most of the time, tessellation shaders are paired, so both will be
replaced at the same time.
2. The data layout is tightly coupled. Both need to agree on the number
of per-patch slots in the VUE map. Even adding extra TCS outputs
that aren't read by the TES will trigger the need for recompiles.
3. The TCS is optional from an API perspective, but required by the
hardware whenever tessellation is enabled. So, atoms that deal with
the TCS must check brw->tess_eval_program (BRW_NEW_TESS_EVAL_PROGRAM?)
rather than brw->tess_ctrl_program to tell whether tessellation is
enabled.
So, not only is it unlikely to be useful, it's a bit confusing to get
right. Simply using one flag for both simplifies this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f34c04fda69c6fc91e60633d41108e488af1f88a |
|
01-Oct-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add tessellation shader surface support.
This is brw_gs_surface_state.c copy and pasted twice with search and
replace.
brw_binding_table.c code is similarly copy and pasted.
v2: Drop dword_pitch related fields.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| abb569ca18db159ae3e4c4b51d01e5a8b3215e04 |
|
05-Dec-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/state: Get rid of dword_pitch arguments to buffer functions
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 05bdc21f84edc200a0b0a695b79d12f25cc00645 |
|
02-Nov-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/vec4: Use a stride of 1 and byte offsets for UBOs
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92909
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 13ad8d03f201a4d09bf7ab9078b00807d61dfada |
|
01-Nov-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965/fs: Use a stride of 1 and byte offsets for UBOs
Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 231db5869c2c0f32608f39100bffff569da21bea |
|
02-Dec-2015 |
Tapani Pälli <tapani.palli@intel.com> |
i965: use _Shader to get fragment program when updating surface state
Atomic counters and Images were using ctx::Shader that does not take in
to account program pipeline changes, ctx::_Shader must be used for SSO to
work. Commit c0347705 already changed ubo's to use this.
Fixes failures seen with following Piglit test:
arb_separate_shader_object-atomic-counter
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2bba2152e4ea10d4ae9b15795dc42e75bdc71bc2 |
|
24-Nov-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: remove trailing spaces in various files
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f36993b46962eab4446bc1964eb47149751aee26 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Clean up #includes in the compiler.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a3d0359aff7a9be90149c416844f330b4f9a15ed |
|
26-Oct-2015 |
Timothy Arceri <timothy.arceri@collabora.com> |
glsl: keep track of intra-stage indices for atomics
This is more optimal as it means we no longer have to upload the same set
of ABO surfaces to all stages in the program.
This also fixes a bug where since commit c0cd5b var->data.binding was
being used as a replacement for atomic buffer index, but they don't have
to be the same value they just happened to end up the same when binding is 0.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Alejandro Piñeiro <apinheiro@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90175
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 55403665b6bff3778ba335e9fd7821fc9a11ad2b |
|
16-Oct-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Do not use NumBufferInterfaceBlocks
This is the only place in the driver where we use this. Since we now work
with separate index spaces, always use NumUniformBlocks and
NumShaderStorageBlocks instead of NumBufferInterfaceBlocks to be more
consistent with the rest of the code.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d3f45888045c84b2bc382a34d169a0ede4774a24 |
|
09-Oct-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Adapt SSBOs to work with their own separate index space
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 27dccf097d053b085c498a7bcab47197a5e83525 |
|
01-Oct-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
mesa: Rename {Num}UniformBlocks to {Num}BufferInterfaceBlocks
Currently, these arrays in gl_shader and gl_shader_program hold both
UBOs and SSBOs, so this looks like a better name. We were already
using NumBufferInterfaceBlocks in gl_shader_program, so this makes
things more consistent as well.
In a later patch we will add {Num}UniformBlocks and
{Num}ShaderStorageBlocks which will contain only references to
UBOs and SSBOs respectively that will provide backends with
a separate index space for both types of objects.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2d97a78b37ddf325d90e056f5eefee0548092530 |
|
29-Aug-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Use _mesa_is_image_unit_valid() instead of gl_image_unit::_Valid.
gl_image_unit::_Valid will be removed in a future commit.
Tested-by: Ye Tian <yex.tian@intel.com>
CC: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f7fe9fb0f19196f74864e0b0f57ac61c066c9d10 |
|
25-Sep-2015 |
Chad Versace <chad.versace@intel.com> |
i965/miptree: Rename align_w,align_h -> halign,valign
The values of intel_mipmap_tree::align_w and ::align_h correspond to the
hardware enums HALIGN_* and VALIGN_*.
See the confusion?
align_h != HALIGN
align_h == VALIGN
Reduce the confusion by renaming the variables to match the hardware
enum names:
git ls-files |
xargs sed -i -e 's/align_w/halign/g' \
-e 's/align_h/valign/g'
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7b391142e9da6186221a9eb39977e487f079ef72 |
|
30-Sep-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Upload UBO/SSBO surfaces
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 63d7b33f516815ce3f9b3bb1b26a39f1545a4446 |
|
24-Sep-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Setup surface binding for gl_NumWorkGroups
This will only be setup when the prog_data uses_num_work_groups
boolean is set.
At this point nothing will set uses_num_work_groups, but soon code
will set it when emitting code for the intrinsic that loads
gl_NumWorkGroups.
We can't emit this surface information earlier at the start of the
DispatchCompute* call because we may not have generated the program
yet. Until we generate the program, we don't know if the
gl_NumWorkGroups variable is accessed.
We also can't emit the surface as part of the brw_cs_state atom,
because we might not need the surface if gl_NumWorkGroups is not used
by the program.
Lastly, we cannot emit the surface later (after state upload) in the
DispatchCompute* call, because it needs to be run before the
brw_cs_state atom is emitted, since it changes the surface state.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5bb5eeea008a01f5bc44570915ea4b7ac432cef9 |
|
24-Apr-2015 |
Samuel Iglesias Gonsalvez <siglesias@igalia.com> |
i965/wm: surfaces should have the API buffer size, not the drm buffer size
The returned drm buffer object has a size multiple of 4096 but that should not
be exposed to the API user, which is working with a different size.
As far as I can see this problem is only visible in the calculation of the
length of unsized arrays used in SSBOs, as the implementation of this needs
to query the underlying buffer size via a message.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| eaa6f01c8d0c49d8ae637d8104163da9c45526ca |
|
16-Apr-2015 |
Samuel Iglesias Gonsalvez <siglesias@igalia.com> |
i965/wm: emit null buffer surfaces when null buffers are attached
Otherwise we can expect odd things to happen if, for example, we ask
for the size of the attached buffer from shader code, since that
might query this value from the surface we uploaded and get random
results.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 37da6a2acd549d145b1691bb1f6bab87b65c92a6 |
|
23-Mar-2015 |
Iago Toral Quiroga <itoral@igalia.com> |
i965: Upload Shader Storage Buffer Object surfaces
Since these are a special kind of UBOs we emit them together reusing the
same infrastructure, however, we use a RAW surface so we can reuse
existing untyped read/write/atomic messages which include a pixel mask
header that we need to set to obtain correct behavior with helper
invocations of the fragment shader.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2b9c35945a74c6e2b559bb52eb612231465e86a1 |
|
04-Oct-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Support CS in update_stage_texture_surfaces
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b97d8c95a91773dc002e3ba42bd02e84a00eada3 |
|
17-Aug-2015 |
Francisco Jerez <currojerez@riseup.net> |
mesa: Don't lose track of the shader image layer originally specified by the user.
The spec requires that all layers of the image starting from the 0-th
are bound to the image unit regardless of the Layer parameter when
Layered is true, so I was setting gl_image_unit::Layer to zero in that
case for the convenience of the driver back-end. However the
ES31-CTS.shader_image_load_store.basic-api-bind conformance test
checks that the layer value returned by glGetInteger is the same that
was originally specified, regardless of the value of layered. Rename
Layer to _Layer as is usual for other derived state and keep track of
the original layer value as gl_image_unit::Layer.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 30694b3f42d0da4fb106561fc898279babb498ad |
|
06-Aug-2015 |
Rhys Kidd <rhyskidd@gmail.com> |
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c: In function 'brw_upload_abo_surfaces':
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c:961:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < prog->NumAtomicBuffers; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5fb58012be6f783d735ded79582aa46a2c71e0fd |
|
06-Aug-2015 |
Rhys Kidd <rhyskidd@gmail.com> |
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c: In function 'brw_upload_ubo_surfaces':
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c:901:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < shader->NumUniformBlocks; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 47f9b07e4cf79a8249c6f9f09148a6a0b4fabacc |
|
20-Jul-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Hook up image state upload.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 87a3e02d9bec689e110f820bba7b125b3e801fdd |
|
21-Jan-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Define and initialize image parameter structure.
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass. size will be used for bounds checking with some image
formats and will be useful for ARB_shader_image_size too. surface_idx
is always used.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
v3: Improve documentation.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3144844f5ca89cd5743bc9b0ac142ccf862af557 |
|
02-May-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Implement surface state set-up for shader images.
v2: Add SKL support.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 41b6db225f42a5d81beec1b4455ec7b504e2416d |
|
17-Jun-2015 |
Kevin Rogovin <kevin.rogovin@intel.com> |
i965: Use _mesa_geometric_ functions appropriately
Change references to gl_framebuffer::Width, Height, MaxNumLayers
and Visual::samples to use the _mesa_geometry_ convenience functions
for those places where the geometry of the gl_framebuffer is needed
(in contrast to the geometry of the intersection of the attachments
of the gl_framebuffer).
This patch is to pave the way to enable GL_ARB_framebuffer_no_attachments
on Gen7 and higher in i965.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| eeee212e53feac673ea4ac0345fe493418b187df |
|
27-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: Upload atomic buffer state for compute shaders
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c15e20d8f6f6d632ad55d444149c2a12d0dcc515 |
|
19-Mar-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Expose and refactor brw_update_renderbuffer_surfaces()
Note that brw_update_renderbuffer_surfaces() already had a helper
variable which was used in parallel to direct access of the current
draw buffer of the context.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea |
|
17-Mar-2015 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965: Refactor rb surface setup to allow caller to store offsets
Notice that in gen7_wm_surface_state.c there is also indentation
change in the surrounding code removing tabs.
v2 (Matt): Fixed whitespace: tabs -> spaces
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 28d9e90428282a5e0a6aa31ad858a5cf514d1264 |
|
07-Apr-2015 |
Marius Predut <marius.predut@intel.com> |
i965: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
No functional changes.
Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Marius Predut <marius.predut@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4e56a9ad46ff7fe85308ce12e21719ff2b476516 |
|
20-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Don't use brw->state.dirty.brw
Now, we only use ctx->NewDriverState.
I used this bash & sed command in the i965 directory:
for file in *.[ch] *.[ch]pp; do
sed -i -e 's/state\.dirty\.brw/ctx.NewDriverState/g' $file
done
Followed by manual changes to brw_state_upload.c.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7bfbaf4a5ab580a8661ea99059cb48c64a016ab6 |
|
10-Feb-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Remove the create_raw_surface vtbl hook.
It's a wrapper around emit_buffer_surface_state with format=RAW, pitch=1,
rw=true and the remaining arguments ordered differently. There's no point in
having a separate vtbl pointer for that.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 53295bebc883c5b90b4b3a2612d7cacabc94fd1b |
|
26-Feb-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix I/L/LA SNORM formats.
_mesa_choose_tex_format (texformat.c) tries I8_SNORM, L8_SNORM, and
either L8A8_SNORM or A8L8_SNORM, none of which are supported by our
driver. Failing that, it falls back to RGBX for luminance, and RGBA
intensity and luminance alpha. So, we need to use swizzle overrrides
to obtain the correct values.
Fixes Piglit's EXT_texture_snorm/fbo-blending-formats and
fbo-clear-formats.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 46b03d5400794736e04eee5d373673309ba286ad |
|
10-Feb-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Generalize the update_null_renderbuffer_surface vtbl hook to non-renderbuffers.
Null surfaces are going to be useful to have something to point
unbound image units to, as the ARB_shader_image_load_store extension
requires us to behave deterministically in cases where some shader
tries to access an unbound image unit: Invalid stores and atomics are
supposed to be discarded and invalid loads are supposed to return
zero, which is precisely what the null surface does.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8cb18760cccf2c89d94c50ff14b330ec2d5c4a3c |
|
06-Feb-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Override swizzles for integer luminance formats.
The hardware's integer luminance formats are completely unusable;
currently we fall back to RGBA. This means we need to override
the texture swizzle to obtain the XXX1 values expected for luminance
formats.
Fixes spec/EXT_texture_integer/texwrap formats bordercolor [swizzled]
on Broadwell - 100% of border color tests now pass on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 11f5d8a5d4fbb861ec161f68593e429cbd65d1cd |
|
16-Dec-2014 |
Francisco Jerez <currojerez@riseup.net> |
i965: Enable L3 caching of buffer surfaces.
And remove the mocs argument of the emit_buffer_surface_state vtbl hook. Its
semantics vary greatly from one generation to another, so it kind of
encourages the caller to pass 0 which is the only valid setting across
generations. After this commit the hardware-specific code decides what the
best cacheability settings are for buffer surfaces, just like we do for
textures.
This together with some additional changes coming is expected to improve
performance of pull constants, buffer textures, atomic counters and image
objects on Gen7 and up.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 117a1d69de84c6cb7d895ce7e157f434facde7c9 |
|
13-Jan-2015 |
Jason Ekstrand <jason.ekstrand@intel.com> |
i965: Apply the miptree offset to surface state for renderbuffers
Previously, we were completely ignoring the mt->offset field for
renderbuffers. While it does have some alignment constraints, it is valid
to use it. This patch adds the code to each of the 4 surface state setup
functions to handle it.
Reviewed-by: Neil Roberts <neil@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4616b2ef850cb2b3e33005809ed77a697afc4186 |
|
23-Dec-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing BRW_NEW_*_PROG_DATA to texture/renderbuffer atoms.
This was probably missed when moving from a fixed binding table layout
to a dynamic one that changes based on the shader.
Fixes newly proposed Piglit test fbo-mrt-new-bind.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87619
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Mike Stroyan <mike@LunarG.com>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c5b3878714a75dab40439622050b2ce6f60337c0 |
|
21-Oct-2014 |
Kristian Høgsberg <krh@bitplanet.net> |
i965: Add new SIMD8 VS prog data flag
This flag signals that we have a SIMD8 VS shader so we can set up the
corresponding state accordingly. This boils down to setting
the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull
constant buffers use dword pitch.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5f34a18f96e58aff1aca2d2971fca1c91dc6931d |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete brw_state_flags::cache and related code.
It's been merged into brw_state_flags::brw for simplicity and
efficiency.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4f24c168c87e9938f35f5ec135062408148be373 |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).
I put the BRW_NEW_*_PROG_DATA flags at the beginning so that
brw_state_cache.c can still continue using 1 << brw_cache_id.
I also added a comment explaining the difference between
BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM, as it took me a long time
to remember it.
Non-mechanical changes:
- brw_state_cache.c and brw_ff_gs.c now signal .brw, not .cache.
- brw_state_upload.c - INTEL_DEBUG=state changes.
- brw_context.h - bit definition merging.
v2: Correct the explanation of BRW_NEW_*_PROG_DATA to mention
state-based recompiles, and nix the "proper subset" claim,
as it's false. (Caught by Kristian Høgsberg).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ce44b2061cf59264b4f22271e8d70cdc826af6de |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.
Now that we've moved a bunch of CACHE_NEW_* bits to BRW_NEW_*, the only
ones that are left are legitimately related to the program cache. Yet,
it seems a bit wasteful to have an entire bitfield for only 7 bits.
State upload is one of the hottest paths in the driver. For each atom
in the list, we call check_state() to see if it needs to be emitted.
Currently, this involves comparing three separate bitfields (mesa, brw,
and cache). Consolidating the brw and cache bitfields would save a
small amount of CPU overhead per atom. Broadwell, for example, has
57 state atoms, so this small savings can add up.
CACHE_NEW_*_PROG covers the brw_*_prog_data structures, as well as the
offset into the program cache BO (prog_offset). Since most uses refer
to brw_*_prog_data, I decided to use BRW_NEW_*_PROG_DATA as the name.
Removing "cache" completely is a bit painful, so I decided to do it in
several patches for easier review, and to separate mechanical changes
from manual ones. This one simply renames things, and was made via:
$ for file in *.[ch]; do
sed -i -e 's/CACHE_NEW_\([A-Z_\*]*\)_PROG/BRW_NEW_\1_PROG_DATA/g' \
-e 's/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/g' $file
done
Note that BRW_NEW_*_PROG_DATA is still in .cache, not .brw!
The next patch will remedy this flaw. It will also fix the
alphabetization issues.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| bea9b8e306e8424ffacbdfc99ca2fc91f1c9912b |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Alphabetize brw_tracked_state flags and use a consistent style.
Most of the dirty flags were listed in some arbitrary order. Some used
bonus parenthesis. Some put multiple flags on one line, others put one
per line. Some used tabs instead of spaces...but only on some lines.
This patch settles on one flag per line, in alphabetical order, using
spaces instead of tabs, and sheds the unnecessary parentheses.
Sorting was mostly done with vim's visual block feature and !sort,
although I alphabetized short lists by hand; it was pretty manual.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0dc56600aa0fae509b60da09f57d1f649125be04 |
|
23-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Correctly use ABO count to trigger flagging of new surfaces.
This would have *almost never* actually been an issue, since other state
tends to get flagged at the same time as new ABOs -- but still bogus.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 25189c72ce49a4af81a270e11f3a987669727406 |
|
01-Oct-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: No longer reemit textures on BRW_NEW_UNIFORM_BUFFER
This didn't make any sense, but papered over the missing TexBO flagging
we've just fixed, in a bunch of cases.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| be5df289416f7b4b24811722cea8da9a3fe75ee3 |
|
01-Oct-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add new dirty flag for new TexBOs.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e4e3b0fc0dfbd57e13359ffdd9660128711aaa72 |
|
23-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Fix typo in comment
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 864c463485aafaa2802b18a7427f8b75dc96e3ef |
|
03-Sep-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404
Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
c5bdf9be1eca190417998d548fd140c1eca37a54
Conflicts:
src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
6f56e1424d923fd80c84090fbf4506c9eaaffea1
Conflicts:
src/mesa/drivers/dri/i965/brw_blorp.cpp
src/mesa/drivers/dri/i965/brw_state_cache.c
src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
88e3d404dad009d8cff5124cf8acee7daeaceb64
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 88e3d404dad009d8cff5124cf8acee7daeaceb64 |
|
10-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Create a macro for setting a dirty bit.
This will make it easier to extend dirty bit handling to support
compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 848fc7f7103b36b013e16910f6e72941df156c55 |
|
06-Jul-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Fix warnings introduced in commit e24ef5ab.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e874274d0847733b2ae6c2efb911145d2da6e6b6 |
|
21-May-2014 |
Eric Anholt <eric@anholt.net> |
i965: Add a comment about null renderbuffer surfaces and why they exist.
I noticed this when trying to find comments about pull constant buffers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e24ef5ab189a962722bff7c6bc2ee574296e0953 |
|
21-May-2014 |
Eric Anholt <eric@anholt.net> |
i965: Merge VS/GS and WM pull constant buffer upload paths.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3d826729dabab53896cdbb1f453c76fab1c7e696 |
|
29-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use unreachable() instead of unconditional assert().
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f6a99d1167b14a3ada7c1d6f41a5cc6f13290e0d |
|
29-May-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't emit SURFACE_STATEs for gather workarounds on Broadwell.
As far as I can tell, Broadwell doesn't need any of the SURFACE_STATE
workarounds for textureGather() bugs, so there's no need to emit
a second set of identical copies.
To keep things simple, just point the gather surface index base to the
same place as the texture surface index base.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6aefaa4eb23dec764a59f9e28bbe4a7d5036fdbf |
|
07-May-2014 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/wm: Surface state overrides for configuring w-tiled as y-tiled
v2: Use intel_mipmap_tree::total_width in order to get correct alignment
automatically. Also use "mt->total_height / mt->physical_depth0" as
surface height allowing hardware to offset to correct slice.
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e16c5c906316c58c0633e9bba02339ef981e5ef3 |
|
25-Apr-2014 |
Eric Anholt <eric@anholt.net> |
i965: Drop use of intel_region from miptrees.
Note: region->width/height used to reflect the total_width/height padding
of separate stencil, though mt->total_width didn't. region->width/height
was being used in EGL images, where the padded value would have been the
wrong one, so I converted them to use rb->Width/Height.
v2: Drop debug printf that slipped in (caught by Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ff9c3e8e5a22597c83505479e918981377f8fdf4 |
|
24-Apr-2014 |
Eric Anholt <eric@anholt.net> |
mesa: Replace use of _ReallyEnabled as a boolean with use of _Current.
I'm probably not the only person that has tried to kill _ReallyEnabled.
This does the mechanical part of the work, and cleans _ReallyEnabled from
i965.
I think that using _Current makes texture management clearer: You can't
have multiple targets in use in the same texture image unit at the same
time, because there's just that one pointer.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b02bcea7157020b01d5f4fdcb5da69c10013a818 |
|
01-Nov-2013 |
Eric Anholt <eric@anholt.net> |
i965: Use intel_upload_space() for pull constant uploads.
This also happens to fix a leak of the current GS pull constant BO on
context destroy, by just not holding on to the pull const bos after the
surface state is generated.
No statistically significant performance difference on GLB2.7 on HSW at
1024x768 (n=40) or 320x240 (n=44), or on BYT at 320x240 (n=47).
v2: Rebase on intel_upload simplification.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c03477050a6f51e601f75cb3c061a3e16a5b7171 |
|
03-May-2013 |
Gregory Hainaut <gregory.hainaut@gmail.com> |
mesa/sso: rename Shader to the pointer _Shader
Basically a sed but shaderapi.c and get.c.
get.c => GL_CURRENT_PROGAM always refer to the "old" UseProgram behavior
shaderapi.c => the old api stil update the Shader object directly
V2: formatting improvement
V3 (idr):
* Rebase fixes after a block of code was moved from ir_to_mesa.cpp to
shaderapi.c.
* Trivial reformatting.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| afed5354aa7860483113722d2a810cccfa175474 |
|
12-Feb-2014 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/wm: Use resolved miptree consistently in surface setup
Most of the logic refers to the local variable 'mt' directly but
a few cases use 'intelObj->mt' instead. These are the same for
now but will be different once stencil miptree gets used.
v2 (Ian): fixed also indentation in surrounding lines
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ae8b066da5862b4cfc510b3a9a0e1273f9f6edd4 |
|
19-Feb-2014 |
Francisco Jerez <currojerez@riseup.net> |
i965: Move up duplicated fields from stage-specific prog_data to brw_stage_prog_data.
There doesn't seem to be any reason for nr_params, nr_pull_params,
param, and pull_param to be duplicated in the stage-specific
subclasses of brw_stage_prog_data. Moving their definition to the
common base class will allow some code sharing in a future commit, the
removal of brw_vec4_prog_data_compare and brw_*_prog_data_free, and
the simplification of the stage-specific brw_*_prog_data_compare.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c2d51aaa11c2593edb9f4b9279745d39c79ff23c |
|
03-Feb-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add surface format overrides for Gen6 gather
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 71fe9437169cfdafda8814aa814bb85429fb6cfc |
|
04-Jan-2014 |
Mark Mueller <MarkKMueller@gmail.com> |
mesa: change gl_format to mesa_format
s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 67ebcb4711d7c6d35df03298f065806613a62798 |
|
13-Jan-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use the new drm_intel_bo offset64 field.
libdrm 2.4.52 introduces a new 'uint64_t offset64' field, intended to
replace the old 'unsigned long offset' field. To preserve ABI, libdrm
continues to store the presumed offset in both locations.
On Broadwell, a 64-bit kernel may place BOs at "high" (> 4G) addresses.
However, with a 32-bit userspace, the 'unsigned long offset' field will
only be 32-bit, which is not large enough to hold this value. We need
to use a proper uint64_t (like the kernel does).
Technically, a lot of this code doesn't affect Broadwell, so we could
leave it using the old field. But it makes sense to just switch to the
new, properly typed field.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 877128505431adaf817dc8069172ebe4a1cdf5d8 |
|
17-Jan-2014 |
José Fonseca <jfonseca@vmware.com> |
s/Tungsten Graphics/VMware/
Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.
This was the sed script I used:
$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#
# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g
# Rename emails
s/alanh@tungstengraphics.com/alanh@vmware.com/
s/jens@tungstengraphics.com/jowen@vmware.com/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g
s/keithw\?@tungstengraphics.com/keithw@vmware.com/g
s/michel@tungstengraphics.com/daenzer@vmware.com/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/zack@tungstengraphics.com/zackr@vmware.com/
# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g
# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 532b1fecd93fd30d3b1b101b55fd2c6e074088ad |
|
07-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix clears of layered framebuffers with mismatched layer counts.
Previously, Mesa enforced the following rule (from
ARB_geometry_shader4's list of criteria for framebuffer completeness):
* If any framebuffer attachment is layered, all attachments must have
the same layer count. For three-dimensional textures, the layer count
is the depth of the attached volume. For cube map textures, the layer
count is always six. For one- and two-dimensional array textures, the
layer count is simply the number of layers in the array texture.
{ FRAMEBUFFER_INCOMPLETE_LAYER_COUNT_ARB }
However, when ARB_geometry_shader4 was adopted into GL 3.2, this rule
was dropped; GL 3.2 permits different attachments to have different
layer counts. This patch brings Mesa in line with GL 3.2.
In order to ensure that layered clears properly clear all layers, we
now have to keep track of the maximum number of layers in a layered
framebuffer.
Fixes the following piglit tests in spec/!OpenGL 3.2/layered-rendering:
- clear-color-all-types 1d_array mipmapped
- clear-color-all-types 1d_array single_level
- clear-color-mismatched-layer-count
- framebuffer-layer-count-mismatch
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e3b86f07da4ba9a4db6b8aae4072af6f1638b7cc |
|
07-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
mesa: Use gl_shader::Stage instead of gl_shader::Type where possible.
This reduces confusion since gl_shader::Type is sometimes
GL_SHADER_PROGRAM_MESA but is more frequently
GL_SHADER_{VERTEX,GEOMETRY,FRAGMENT}. It also has the advantage that
when switching on gl_shader::Stage, the compiler will alert if one of
the possible enum types is unhandled. Finally, many functions in
src/glsl (especially those dealing with linking) already use
gl_shader_stage to represent pipeline stages; using gl_shader::Stage
in those functions avoids the need for a conversion.
Note: in the process I changed _mesa_write_shader_to_file() so that if
it encounters an unexpected shader stage, it will use a file suffix of
"????" rather than "geom".
Reviewed-by: Brian Paul <brianp@vmware.com>
v2: Split from patch "mesa: Store gl_shader_stage enum in gl_shader objects."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| da031f83f741b2d0182d3b05970093e9a73fbf58 |
|
27-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove unused depth_mode parameter from translate_tex_format().
According to git blame, this hasn't been used in over two years:
commit d2235b0f4681f75d562131d655a6d7b7033d2d8b
Author: Eric Anholt <eric@anholt.net>
Date: Thu Nov 17 17:01:58 2011 -0800
i965: Always handle GL_DEPTH_TEXTURE_MODE through the shader.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a7bdd4cba8ddcab8dff59ecaaa7efbd436c6c307 |
|
26-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Drop trailing whitespace from the rest of the driver.
Performed via:
$ for file in *; do sed -i 's/ *//g'; done
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 95140740ad1c6cd8a34002c307556f5c49a34589 |
|
20-Nov-2013 |
Paul Berry <stereotype441@gmail.com> |
mesa: Track number of layers in layered framebuffers.
In order to properly clear layered framebuffers, we need to know how
many layers they have. The easiest way to do this is to record it in
the gl_framebuffer struct when we check framebuffer completeness.
This patch replaces the gl_framebuffer::Layered boolean with a
gl_framebuffer::NumLayers integer, which is 0 if the framebuffer is
not layered, and equal to the number of layers otherwise.
v2: Remove gl_framebuffer::Layered and make gl_framebuffer::NumLayers
always have a defined value. Fix factor of 6 error in the number of
layers in a cube map array.
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9b3e1592c26a183580342282e509d906d78bb6f6 |
|
06-Nov-2013 |
Eric Anholt <eric@anholt.net> |
i965: Fix undefined value usage in ABO setup.
Fixes a compiler warning.
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 39ebb72e52779b2975bfea3f08b91b7409f4a95c |
|
02-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine {brw,gen7}_update_texture_buffer_surface() functions.
Now that brw_update_texture_buffer_surface() uses the virtual
emit_buffer_surface_state() function, it works for Gen7+ too.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7a974a645e8b5c6a9aca3cc935a5a95cd9f33af8 |
|
02-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Unvirtualize brw_create_constant_surface; delete Gen7+ variant.
Now that brw_create_constant_surface uses a virtual function internally,
it doesn't need to be virtual itself. We can delete the Gen7+ variant
and simplify things.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ee23dd139a7b76188c9245650e9f73d8b239e9c8 |
|
02-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use the new emit_buffer_surface_state() vtable entry.
This will allow us to combine the Gen4-6 and Gen7 variants of these
functions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ba836e02a3f09cdc2188c45b6e409a936a840bea |
|
25-Oct-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Virtualize emit_buffer_surface_state().
This entails adding "mocs" and "rw" parameters to the Gen4-5 version.
I made it actually pay attention to the rw flag (even though it is
always false), but mocs is always ignored.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5809512b17d3216045b612d359f97759644945f1 |
|
20-Oct-2013 |
Francisco Jerez <currojerez@riseup.net> |
i965: Implement ABO surface state emission.
The maximum number of atomic buffer objects is somewhat arbitrary, we
can change it in the future easily if it turns out it's not enough...
v2: Add comments with the relevant mesa dirty bits. Fix usage of
BRW_NEW_UNIFORM_BUFFER in the GS ABO state atom.
v3: Update binding table layout diagrams.
v4: Resolve conflicts with the recent dynamic surface index assignment changes.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c298f5ff5681dd7c3cf0bf7c37a6f22430deeb91 |
|
04-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Try to avoid stalls on the GPU when doing glBufferSubData().
On DOTA2, framerate on dota2-de1.dem in windowed mode on my laptop
improves by 7.69854% +/- 0.909163% (n=3). In a microbenchmark hitting
this code path (wall time of piglit vbo-subdata-many), runtime decreases
from 0.8 to 0.05 seconds.
v2: Use out of range start/end instead of separate bool for the active
flag (suggestion by Jordan), fix double-upload in the stalling path.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a5e2e7f9a4bc813ce85f4a10bcd6086f21aa8a32 |
|
05-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_ARB_texture_buffer_range.
Supporting this extension turns out to simplify our code a bit over not
supporting this extension, once the glBufferSubData() synchronization code
lands.
v2: Use 16 byte alignment like we do for uniform buffers, due to unaligned
access penalties.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c0a9436d191d24d9aea18fcca7a79674af3a782e |
|
05-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Fix texture buffer rendering after a whole buffer replacement.
If glBufferData(), glBufferSubData(0, obj->Size), or similar happens, we
get a new drm_intel_bo for the buffer object, and thus need to re-upload
texture buffer state so we point at the new data.
Fixes the new piglit GL_ARB_texture_buffer_object/data-sync
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3c9dc2d31b80fc73bffa1f40a91443a53229c8e2 |
|
02-Oct-2013 |
Eric Anholt <eric@anholt.net> |
i965: Make a brw_stage_prog_data for storing the SURF_INDEX information.
It would be nice to be able to pack our binding table so that programs
that use 1 render target don't upload an extra BRW_MAX_DRAW_BUFFERS - 1
binding table entries. To do that, we need the compiled program to have
information on where its surfaces go.
v2: Rename size to size_bytes to be more explicit.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c08f2083ee0c5d71351fe8eb9f41218a6fed7b10 |
|
15-Sep-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Emit a second set of SURFACE_STATE for gather4 from textures.
This allows us to use a different surface format for gather4, which is
required for R32G32_FLOAT to work on Gen7.
V4: - Only emit alternate surface state for shaders which will actually
use it.
- Pass a simple 'for_gather' flag rather than a function pointer.
The callee can decide what w/a to apply.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7de88ac38004e68b5a0a94c881cc1da1ee4371d7 |
|
18-Sep-2013 |
Eric Anholt <eric@anholt.net> |
i965: Totally switch around how we handle nonzero baselevel-first_level.
This has no effect currently, because intel_finalize_mipmap_tree() always
makes mt->first_level == tObj->BaseLevel.
The change I made before to handle it
(b1080cfbdb0a084122fcd662cd27b4748c5598fd) got very close to working, but
after fixing some unrelated bugs in the series, it still left
tex-miplevel-selection producing errors when testing textureLod(). The
problem is that for explicit LODs, the sampler's LOD clamping is ignored,
and only the surface's MIP clamping is respected. So we need to use
surface mip clamping, which applies on top of the sampler's mip clamping,
so the sampler change gets backed out.
Now actually tested with a non-regressing series producing a non-zero
computed baselevel.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9c116d5eacf286cd8548d64ba8ce6528edb889c9 |
|
18-Sep-2013 |
Eric Anholt <eric@anholt.net> |
i965: Always look up from the object's mt when setting up texturing state.
We know that the object's mt is equal to the firstimage's mt because it's
gone through intel_finalize_mipmap_tree(). Saves a lookup of firstimage
on pre-gen7.
v2: Merge in the warning fix that appeared later in the series (noted by
Chad)
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b6b549ccfc6f71f94ba58892b0506ca5cd7b4a7c |
|
14-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Refactor Gen4-6 SURFACE_STATE setup for buffer surfaces.
This was an embarassingly large amount of copy and pasted code,
and it wasn't particularly simple code either. By factoring it out
into a helper function, we consolidate the complexity.
v2: Properly NULL-check bo. Caught by Eric Anholt.
v3: Do the subtraction by 1 in gen7_emit_buffer_surface_state, rather
than making callers do it. This makes the buffer_size parameter
the actual size of the buffer. Suggested by Paul Berry.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 35a54ad02f977a11b119d1ed13a3ce4d78a1599b |
|
17-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix off by one errors in texture buffer size calculations.
The value that's split into width/height/depth needs to be the size of
the buffer minus one. This makes it consistent with the constant buffer
and shader time SURFACE_STATE setup code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| feaad189b45cafe860b5f23bf534618ff30b5bd2 |
|
14-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move binding table code to a new file, brw_binding_tables.c.
The code to upload the binding tables for each stage was scattered
across brw_{vs,gs,wm}_surface_state.c and brw_misc_state.c, which also
contain a lot of code to populate individual SURFACE_STATE structures.
This patch brings all the binding table upload code together, and splits
it out from the code which fills in SURFACE_STATE entries.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 113a75ff2d5013583bc41f5bd71e24d7897cd459 |
|
14-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use brw_upload_binding_table() for the pixel shader as well.
This is not quite the same: brw_upload_binding_table() also has code to
early-return if there are no entries, while the existing code did not.
The PS binding table is unlikely to be empty since it will have at least
one color buffer. If it ever is empty, early returning seems wise.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b8244b00569828f62137693f251297bc83dee67c |
|
14-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove MIPLAYOUT_BELOW from Gen4-6 constant buffer surface state.
Specifying a miptree layout makes no sense for constant buffers.
This has no functional change since BRW_SURFACE_MIPMAPLAYOUT_BELOW is
just a #define for 0.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4b3c0a797f89830fd5ba0943b061abf4fc38337e |
|
02-Sep-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use brw_stage_state for WM data as well.
This gets the VS, GS, and PS all using the same data structure.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 89563489ff3c61c0e40ce3540dd542b118436647 |
|
25-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: add geometry shader support to brw_texture_surfaces.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 08d8ff0965af7e2dd7beb074efa08ec062b6a04a |
|
21-Jun-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: generalize brw_texture_surfaces in preparation for gs.
There is a slight functionality change. Previously we would compute a
common value for num_samplers for all stages, and populate that many
entries in each stage's surf_offset table regardless of how many
samplers each stage used. Now we only populate the number of entries
in the surf_offset table corresponding to the number of samplers
actually used by the stage.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5a8033f142e86ed51511c695138cacaf4532e6cf |
|
25-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Modify signature to update_texture_surface functions.
Previously these functions would accept a pointer to the binding table
and an index indicating which entry in the binding table should be
updated. Now they merely take a pointer to the binding table entry to
be updated.
This will make it easier to generalize brw_texture_surfaces to support
geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ec94e3c3d02857e26ba66e7e6a4b54044c820a0a |
|
24-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Move data from brw->vs into a base class if gs will also need it.
This paves the way for sharing the code that will set up the vertex
and geometry shader pipeline state.
v2: Rename the base class to brw_stage_state.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| cdf03b69282d12f9d27daf2edb3abb351f5de7f6 |
|
25-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: Update defines related to GS surface organization.
Defines that previously referred to VS now refer to VEC4, since they
will be shared by the user-programmable vertex shader and geometry
shader stages.
Defines that previously referred to the Gen6 geometry shader stage
(which is only used for transform feedback) are now renamed to
explicitly refer to Gen6, to avoid confusion with the Gen7
user-programmable geometry shader stage.
Based on work by Eric Anholt <eric@anholt.net>.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b1080cfbdb0a084122fcd662cd27b4748c5598fd |
|
28-Aug-2013 |
Eric Anholt <eric@anholt.net> |
i965: Switch gen4-6 to using the sampler's base level for GL BASE_LEVEL.
Thanks to Ken for trawling through my neglected public branches and
finding the bug in this change (inside a megacommit) that made me abandon
this work.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 60689c05d1f69610b3daac1c9f407c75ebecc81b |
|
15-Aug-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Make the FS binding table as small as possible.
Computing the minimum size was easy, and done at compile-time for no
extra overhead here. Making the binding table smaller wastes less batch
space.
Adding the CACHE_NEW_WM_PROG dirty bit isn't strictly necessary, since
other atoms depend on it and flag BRW_NEW_SURFACES. However, it's best
to add it for clarity and safety. It shouldn't add any new overhead.
v2: Use binding_table_size, rather than max_surface_index.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7c717690b5594c768a18cc2a00364e5ec7bc20ab |
|
15-Aug-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use SURF_INDEX_DRAW() for drawbuffer binding table indices.
SURF_INDEX_DRAW() has been the identity function since the dawn of time,
and both the shader code and binding table upload code relied on that,
simply using X rather than SURF_INDEX_DRAW(X).
Even if that continues to be true, using the macro clarifies the code.
The comment about draw buffers needing to be first in order for
headerless render target writes to work turned out to be wrong; with
this change, SURF_INDEX_DRAW can be changed to arbitrary indices and
everything continues working.
The confusion was over the "Render Target Index" field in the FB write
message header. If it were a binding table index, then RT 0 would have
to be at index 0 for headerless FB writes to work. However, it's
actually an index into the blend state table, so there's no problem.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3f64cfabfc0bae7f5dba9d541680edcc6b745cea |
|
10-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Cite the 965 PRM for "the data cache is the sampler cache".
Presumably, this comment exists to justify the usage of
I915_GEM_DOMAIN_SAMPLER for this relocation. At one point, this was
necessary to ensure that the right flushing was done to keep caches
coherent. These days, the kernel just flushes everything, so I don't
think it matters.
Still, the comment is interesting, so leave it in place.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8c9a54e7bcfc80295ad77097910d35958dfd3644 |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete intel_context entirely.
This makes brw_context inherit directly from gl_context; that was the
only thing left in intel_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 329779a0b45b63be17627f026533c80b2c8f7991 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::batch to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| eeb75b41f1d7be609861d3e98b64b6fffd13bb4f |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::bufmgr to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e43043c316a8274f5f07a8cf818960ef1387a788 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::vtbl to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 745f6c692cda4ae74d0de3b4128cc39d2ffc2054 |
|
26-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split surface format code into a new file (brw_surface_formats.c).
brw_wm_surface_state.c has gotten rather large and unwieldy. At this
point, it consists of two separate portions:
1. Surface format code
This includes the giant table of surface formats and what features
they support on each generation, as well as the code to translate
between Mesa formats and hardware formats.
This is used across all generations.
2. Binding table (SURFACE_STATE) related code.
This is the code to generate SURFACE_STATE entries for renderbuffers,
textures, transform feedback buffers, constant buffers, and so on, as
well as the code to assemble them into binding tables.
This is only used on Gen4-6; gen7_surface_state.c has Gen7+ code.
Since the two are logically separate, and one is reused on every
generation while the other is not, it makes a lot of sense to split
them out. It should also make finding code easier.
No code is changed by this patch. I simply copied the file then deleted
portions of both.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 88514d922e4e392ec82ea8ab2ecb5bf0d2317c4f |
|
19-Jun-2013 |
Eric Anholt <eric@anholt.net> |
i965: Stop recomputing the miptree's size from the texture image.
We've already computed what the dimensions of the miptree are, and stored
it in the miptree.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 820325b258b6531377ec34840193c64bfa10fc36 |
|
19-Jun-2013 |
Eric Anholt <eric@anholt.net> |
i965: Drop unused argument to translate_tex_format().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958 |
|
07-May-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7+: Create an enum for keeping track of fast color clear state.
This patch includes code to update the fast color clear state
appropriately when rendering occurs. The state will also need to be
updated when a fast clear or a resolve operation is performed; those
state updates will be added when the fast clear and resolve operations
are added.
v2: Create a new function, intel_miptree_used_for_rendering() to
handle updating the fast color clear state when rendering occurs.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6a5469cff9eb8167a9cf977b42bdcf423e400bb7 |
|
19-Apr-2013 |
Jordan Justen <jordan.l.justen@intel.com> |
intel: add layered parameter to update_renderbuffer_surface
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0ae294bf7c885aa587c7bde54fd4f9bf70af02d4 |
|
04-Feb-2013 |
Eric Anholt <eric@anholt.net> |
intel: Rename intel_renderbuffer_tile_offsets.
This makes it more consistent with intel_miptree_get_tile_offsets().
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5c85e1cf554803e61bfb30f2a8683422a3ead0e4 |
|
04-Feb-2013 |
Eric Anholt <eric@anholt.net> |
intel: Make intel_miptree_get_tile_offsets return a page offset.
Right now, the callers in i965 don't expect a nonzero page offset to
actually occur (since that's being handled elsewhere), but it seems
like a trap to leave it this way.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e98c39c109f9b38d6bb97e3890382fdf66c25176 |
|
10-May-2013 |
Eric Anholt <eric@anholt.net> |
mesa: Track the TexImage being rendered to in the gl_renderbuffer.
We keep having to pass the attachments around with our gl_renderbuffers
because that's the only way to find what the gl_renderbuffer actually
refers to. This is a step toward removing that (though drivers still need
the Zoffset as well).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 61506257f68c18cc927a44f25344ee0584fdbd0e |
|
17-Apr-2013 |
Eric Anholt <eric@anholt.net> |
i965: Fill in brw_format_for_mesa_format for some non-rendering formats.
This should have no change on driver operation, but it means that when you
wonder why some format isn't supported natively, you can just look at the
table above, instead of wondering if maybe there's an appropriate entry in
the surface formats table that is already supported.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9db9bc3aa19983f1bd0f1c0f3fe9c6317484892d |
|
17-Apr-2013 |
Eric Anholt <eric@anholt.net> |
i965: Use native RGB_FLOAT16 support when available.
Previously we would expand it to RGBA_FLOAT16. This format now comes out
as framebuffer incomplete, but it seems worth the memory savings if that's
what people are asking for (and GL3 does list it under "texture-only"
color formats)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 028c11e8e3a8bc24938b665264fddcb566f59d18 |
|
17-Apr-2013 |
Eric Anholt <eric@anholt.net> |
i965: Use the Mesa surface formats for float RGB surfaces.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2e057076a8bdc53d976fe7515fdb2ab2fbfcd5ba |
|
17-Apr-2013 |
Eric Anholt <eric@anholt.net> |
i965: Use the new XRGB UNORM formats.
This is a step on the way to removing some of our code for forcing alpha
to 1, but I want easy bisecting so I'll add groups of formats separately.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 77d8fbcfd4b79fa022c021ed52bda157d72e1ca9 |
|
26-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: add & use a new driver flag for UBO updates instead of _NEW_BUFFER_OBJECT
v2: move the flagging from intel_bufferobj_data to intel_bufferobj_alloc_buffer
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0b0d6f97cfac75524470c895be686b69d67f050f |
|
21-Mar-2013 |
Eric Anholt <eric@anholt.net> |
i965: Sync brw_format_for_mesa_format() table with new Mesa formats.
I'm not filling them all in, to prevent any breakage in this commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2755946427392344b79d39f8e2fc144e9fa333aa |
|
21-Mar-2013 |
Eric Anholt <eric@anholt.net> |
i965: Update the surface formats table from the current specs.
Unfortunately the surface formats table is now splattered across multiple
chapters. All surface format enums from brw_defines.h are present, but
only support for them that is mentioned in the public specs is included
here.
v2 (from Ken): Mark R32G32B32A32_SFIXED as unsupported on Ivybridge.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e34c857639380303a43146a50cdd724774f59a2f |
|
18-Apr-2013 |
Eric Anholt <eric@anholt.net> |
mesa: Make a Mesa core function for sRGB render encoding handling.
v2: const-qualify ctx, and add a comment about the function (recommended
by Brian and Kenneth).
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 73bc6061f5c3b6a3bb7a8114bb2e1ab77d23cfdb |
|
25-Apr-2013 |
Eric Anholt <eric@anholt.net> |
i965: Disable Z16 on contexts that don't require it.
It appears that Z16 on Intel hardware is in fact slower than Z24, so
people are getting surprisingly hurt when trying to use Z16 as a
performance-versus-precision tradeoff, or when they're targeting GLES2 and
that's all you get.
GL 3.0+ have Z16 on the list of required exact format sizes, but GLES
doesn't, so choose the better-performing layout in that case. Improves
GLB 2.7 trex performance at 1920x1080 by 10.7% +/- 1.1% (n=3) on my IVB
system.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 740350c982bd2735b9eb9063c2b91856b6f1ad31 |
|
14-Mar-2013 |
Eric Anholt <eric@anholt.net> |
i965: Make the fragment shader pull constants index by dwords, not vec4s.
We want to load vec4s, since loading a vec4 instead of a dword is
basically no increased latency. But for variable indexed access, the
previous requirement of aligned vec4s for a sampler LD was hard to
implement.
Note that this change only affects those messages that use the surface
format, like sampler LDs, but not to the untyped data cache loads we've
used in other cases.
No significant performance difference on my GLSL demo with uniforms forced
to take the varying pull constants path (n=4).
NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2f41a601455e6e0366e28b6b84871842cb4bd341 |
|
20-Mar-2013 |
Eric Anholt <eric@anholt.net> |
i965: Make the constant surface interface take a normal byte size.
This puts the rounding-up logic into the function itself instead of all
the callers having to manage it. Also drop an "unused" comment in gen4,
as the stride *is* used for texbos (and will be for uniforms soon).
NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d86efc075ed84a8c45bfb71cee56dcd18858f727 |
|
15-Mar-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't use texture swizzling to force alpha to 1.0 if unnecessary.
Commit 33599433c7 began setting the texture swizzle mode to XYZ1 for
RED, RG, and RGB textures in order to force alpha to 1.0 in case we
actually stored the texture as RGBA.
This had a unforseen performance implication: the shader precompile
assumes that the texture swizzle mode will be XYZW for non-shadow
sampler types. By setting it to XYZ1, this means every shader used with
a RED, RG, or RGB texture has to be recompiled. This is a very common
case.
Unfortunately, there's no way to improve the precompile, since RGBA
textures still need XYZW, and there's no way to know by looking at
the shader source what texture formats might be used.
However, we only need to smash alpha to 1.0 if the texture's memory
format actually has alpha bits. If not, the sampler already returns 1.0
for us without any special swizzling. XRGB8888, for example, is a very
common case where this occurs.
This partially fixes a performance regression since commit 33599433c7.
More work is required to fully fix it in all cases. This at least helps
Warsow.
NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Carl Worth <cworth@cworth.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0af56c9d53a454477645f4537b8086120a638d3e |
|
08-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Avoid unnecessary copy when depthstencil workaround invoked by clear.
Since apps typically begin rendering with a call to glClear(), it is
likely that when brw_workaround_depthstencil_alignment() moves a
miplevel to a temporary buffer, it can avoid doing a blit, since the
contents of the miplevel are about to be erased.
This patch adds the necessary plumbing to determine when
brw_workaround_depthstencil_alignment() is being called as a
consequence of glClear(), and avoids the unnecessary blit when it is
safe to do so.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
v2: Eliminate unnecessary call to _mesa_is_depthstencil_format(). Fix
handling of depth buffer in depth/stencil format.
v3: Use correct bitfields for clear_mask. Fix handling of depth
buffer in depth/stencil format when hardware uses separate stencil.
When invalidating, make sure we still reassociate the image to the new
miptree.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 125b34cffbd377a3b27967b37767692796542250 |
|
07-Feb-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Specialize SURFACE_STATE creation for shader time.
This is basically a copy and paste of gen7_create_constant_surface, but
with the parameters filled in to offer a simpler interface.
It will diverge shortly.
I didn't bother adding it to the vtable for now since shader time is only
exposed on Gen7+.
v2: Replace tabs in the new code (by anholt)
Add back dropped memset() and add a comment about HSW channel selects.
NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 807eedf70fe6a01eb0298b9d2e7a26687f7c6d82 |
|
22-Feb-2013 |
Eric Anholt <eric@anholt.net> |
intel: Hook up the WARN_ONCE macro to GL_ARB_debug_output.
This doesn't provide detailed error type information, but it's important
to get these relatively severe but rare error messages out to the
developer through whatever mechanism they are using.
v2: Rebase on new WARN_ONCE additions.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8cc26ae9937685438d1554463e0ba69972ec26cf |
|
22-Dec-2012 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Support multisampling in surface_state for textures
The surface_state setup for renderbuffers already worked; only the
texturing side needed work. BLORP does something similar, but does its
own surface_state setup.
On Gen6, we just need to set the correct sample count.
On Gen7: - set the correct sample count
- set the correct layout mode
- set GEN7_SURFACE_ARYSPC_LOD0 if it's set in the miptree.
V2: - Clarify commit message
- Rebased onto Paul's physical/logical dims cleanup
- Added Gen7 support
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e62b6a10bcebae9fe6cb8fe81e95941ac06f13cd |
|
16-Dec-2012 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: add support for multisample textures
V2: - Fix for state moving from texobj to image
- Rebased onto Paul's logical/physical cleanup
- Fixed missing quantization of sample count
- Fold in IMS renderbuffer wrapper fixes from later in the series
- Use correct physical slice offset for UMS/CMS surfaces on Gen7
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ddc2b453d02f2a9460efcc6c6198f56ba89e87fe |
|
06-Feb-2013 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Work around missing sRGB RGB DXT1 support.
The hardware just doesn't support it. I suspect this was a regression from
the move to fixed MESA_FORMATs for compressed textures and that previously we
were storing uncompressed for this or something.
Fixes GPU hangs in piglit "texwrap GL_EXT_texture_sRGB-s3tc bordercolor
swizzled" on my GM965.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ebe86b80825404cec057fb7e7519864754e9481c |
|
24-Jan-2013 |
Marek Olšák <maraeo@gmail.com> |
mesa: fixup inconsistent naming of RG16 formats
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5751d0cb2dd6d1682d2a954e3f008be61b4ab7e2 |
|
04-Feb-2013 |
Eric Anholt <eric@anholt.net> |
i965: Fix segfaults from 45a28a927ab7f29ff325b9326d386a39ba538c18
If you look up a level that isn't in the miptree, you crash.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 45a28a927ab7f29ff325b9326d386a39ba538c18 |
|
27-Nov-2012 |
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> |
i965: Account for offsets when updating SURFACE_STATE.
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9db2098d18dd28cbb4f9f98ec9e8f9d579608c38 |
|
24-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use GL_RED for DEPTH_TEXTURE_MODE in ES 3.0 for unsized formats.
Khronos has apparently decided that depth textures with sized formats
(allowed with ARB_internalformat_query or ES 3.0) should be treated as
GL_RED, while unsized formats (an existing feature) should be treated
as GL_INTENSITY for compatibility with ES 2.0.
Ian is proposing changes to ARB_internalformat_query which will make
this actually legal and consistent.
A similar problem exists with GL 4.2, but we're going to ignore that
for the time being.
Tested on Ivybridge: no Piglit regressions; fixes 4 es3conform tests:
- depth_texture_fbo
- depth_texture_fbo_clear
- depth_texture_teximage
- depth_texture_texsubimage
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8059c2ea9011110df3632e28a4311de9373b9b4e |
|
22-Jan-2013 |
Carl Worth <cworth@cworth.org> |
i965: Use swizzles to force R, G, and B to 0.0 for ALPHA textures.
Similar to the previous commit, we may be using a texture with actual RGBA
storage for the GL_ALPHA format, so force the color values to 0.0.
This commit fixes the following piglit (sub) tests:
EXT_texture_snorm/fbo-blending-formats
GL_ALPHA16_SNORM
GL_ALPHA8_SNORM
GL_ALPHA_SNORM
Note: Haswell bypasses this swizzle code, so may require an independent fix
for this bug.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 33599433c75c0ab433615d08ed7e4002146ba462 |
|
22-Jan-2013 |
Carl Worth <cworth@cworth.org> |
i965: Use swizzles to force alpha to 1.0 for RED, RG, or RGB textures.
We may be using a texture with actual RGBA storage for these formats, so force
the alpha value read to 1.0.
This commit fixes the following piglit (sub) tests:
ARB_texture_float/fb-blending-formats
GL_RGB16F_ARB
EXT_framebuffer_object/fbo-blending-formats
GL_RGB10
GL_RGB12
GL_RGB16
EXT_texture_snorm/fbo-blending-formats
GL_RGB16_SNORM
GL_RGB8_SNORM
GL_RGB_SNORM
These test improvements depend on the previous commit as well. That commit
smashes alpha to 1.0 for the case of ReadPixels (so fixes "FBO testing" as
reported by this test), while this commit smashes alpha to 1.0 for the case of
texturing (fixed the "window testing" as reported by this test).
Note: Haswell bypasses this swizzle code, so may require an independent fix
for this bug.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 582b06c2c689ecf23dca8abd81412ce193a04d10 |
|
11-Jan-2013 |
Eric Anholt <eric@anholt.net> |
i965: Add support for MESA_FORMAT_RGB_FLOAT32 surfaces.
This is for GL_ARB_texture_buffer_object_rgb32 support, but it also
causes the format to get used for float32 rgb textures as well on
Ironlake and later. Since that came with some surprises, separate
the change from the enable commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 60894edeef973e86a73067276f658b72f84271b6 |
|
11-Jan-2013 |
Eric Anholt <eric@anholt.net> |
intel: Make intel_region's pitch be bytes instead of pixels.
We almost never want a stride in pixels -- if you're doing anything with
a stride, you're specifying an offset or incrementing a pointer, and in
both cases you had to multiply by cpp to get the bytes value you wanted.
But worse, on the way to creating a region from a new tiled BO, we
divided by cpp to get pitch in pixels, and for an RGB32 buffer (an
upcoming change) the pitch wouldn't divide exactly, and we'd end up with
a wrong stride in our region.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7e28d6c1ab101894c3a3c90bef929c34e9da6148 |
|
21-Nov-2012 |
Eric Anholt <eric@anholt.net> |
i965: Consistently use nr_pull_params instead of NumParameters.
NumParameters used to be an upper bound on the number of vec4s to be
uploaded, which was basically safe (unless your buffer was bound near
the top of address space *and* you array indexed outside the buffer, in
which case I think you might GPU hang). As I migrate the driver away
from ParameterValues[], this is no longer true.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0cda3382a6a150d42877711f14964b44fe8c6db5 |
|
22-Nov-2012 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Add various plumbing for cubemap arrays
V4: Fixed style nits
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4e9d19717c77d24844ff4443efb4a8bdc1736534 |
|
17-Sep-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
intel: Enable ETC2 support on intel hardware
This patch enables support for ETC2 compressed textures on
all intel hardware. At present, ETC2 texture decoding is not
available on intel hardware. So, compressed ETC2 texture data
is decoded in software and stored in a suitable uncompressed
MESA_FORMAT at the time of glCompressedTexImage2D. Currently,
ETC2 formats are only exposed in OpenGL ES 3.0.
V2: Use single etc_wraps variable for both etc1 and etc2.
V3: Remove redundant code and use just one intel_miptree_map_etc()
and intel_miptree_unmap_etc() function.
Choose MESA_FORMAT_SIGNED_{R16, GR1616} for ETC2 signed-{r11, rg11}
formats
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 71f06344a0d72a6bd27750ceca571fc016b8de85 |
|
27-Nov-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add a debug flag for counting cycles spent in each compiled shader.
This can be used for two purposes: Using hand-coded shaders to determine
per-instruction timings, or figuring out which shader to optimize in a
whole application.
Note that this doesn't cover the instructions that set up the message to
the URB/FB write -- we'd need to convert the MRF usage in these
instructions to GRFs so that our offsets/times don't overwrite our
shader outputs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
v2: Check the timestamp reset flag in the VS, which is apparently
getting set fairly regularly in the range we watch, resulting in
negative numbers getting added to our 32-bit counter, and thus large
values added to our uint64_t.
v3: Rebase on reladdr changes, removing a new safety check that proved
impossible to satisfy. Add a comment to the AOP defs from Ken's
review, and put them in a slightly more sensible spot.
v4: Check timestamp reset in the FS as well.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| df3cecab7d04f73eb3b010a511a048c3b87694a5 |
|
12-Nov-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add comments for each of the surface state table's columns.
I can never remember what "AB" means, and having to constantly consult
the docs is annoying. Just add comments to the top which explain each
of the abbreviations.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ddfa346e4a685269c576714eb0b14fd23d748217 |
|
08-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Make a helper function for the renderbuffer temporary mt workaround.
We now have a case of wanting to do that on gen6+ as well, so make this logic
usable elsewhere.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b5a042a657fed45264406cbd0d67fa6217a410a1 |
|
07-Sep-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Refactor texture swizzle generation into a helper.
It's going to be reused in a second place soon.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 28f4be9eb91b12a2c6b1db6660cca71a98c486ec |
|
12-Sep-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix out-of-order sampler unit usage in ARB fragment programs.
ARB fragment programs use texture unit numbers directly, unlike GLSL
which has an extra indirection. If a fragment program only uses one
texture assigned to GL_TEXTURE1, SamplersUsed will only contain a single
bit, which would make us only upload a single surface/sampler state
entry. However, it needs to be the second entry.
Using _mesa_fls() instead of _mesa_bitcount() solves this. For ARB
programs, this makes num_samplers the ID of the highest texture unit
used. Since GLSL uses consecutive integers assigned by the linker,
_mesa_fls() should give the same result as _mesa_bitcount()..
Fixes a regression since 85e8e9e000732908b259a7e2cbc1724a1be2d447,
which caused GPU hangs in ETQW (and probably others), as well as
breaking piglit test fp-fragment-position.
v2: Add a comment, as suggested by Matt.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54098
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54179
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: meng <mengmeng.meng@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 85e8e9e000732908b259a7e2cbc1724a1be2d447 |
|
24-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use linker-assigned sampler IDs in instruction encoding.
When assigning uniform locations, the linker assigns each sampler
uniform a sequential numerical ID. gl_shader_program::SamplerUnits maps
these sampler variable IDs to the actual texture units they reference
(specified via glUniform1i).
Previously, we encoded this mapping in the SEND instruction encoding:
the "sampler" was the texture unit number, and the binding table index
was SURF_INDEX_TEXTURE(the texture unit number). This unfortunately
meant that whenever the application changed the value of a sampler
uniform, we had to recompile the shader to change the SEND instructions.
This was horrible for the game Cogs, which repeatedly switches between
using texture unit 0 and 1. It also made fragment shader precompiles
useless: we'd do the precompile at glLinkShader() time, before the
application called glUniform1i to set the sampler values. As soon as
it did that, we'd have to recompile, wasting time and space in the
program cache.
This patch encodes the SamplerUnits indirection in the binding table,
sampler state, and sampler default color tables. Instead of baking the
texture unit number into the shader, we bake in the sampler variable ID
assigned by the linker. Since those never change, we don't need to
recompile programs on uniform changes.
This does mean that the tables now depend on the linked shader program
being used for rendering, rather than simply representing all available
texture units. This could cause an increase in state emission.
Another plus is that the sampler state and sampler default color tables
are now compact: we only emit as many entries as there are sampler
uniforms, with no holes in the table since the new sampler IDs are
sequential. Previously we had to emit a full 16 entries every time,
since the tables tracked the state of all active texture units.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 28fab4295e9631ca91c5ebdf26d1bee23011d57e |
|
15-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Un-hardcode WM binding table from update_texture_surface.
Currently, we mirror the VS and WM binding tables' texture entries.
That may not continue to be true, so in preparation, pass in the binding
table and surface index as arguments.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b3900ed5ad9bd5df112490dd2b5d2c17d6124067 |
|
09-Jun-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: add ARB_texture_rgb10_a2ui support
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 25d2bf3845e9a6faaef8d808c1255ec57dc71dba |
|
20-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965: Bind UBOs as surfaces like we do for pull constants.
v2: Comment fix, drop extraneous parens (review by Kenneth)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5bffbd7ba2ba2ff21469b2a69a0ed67f0802fec7 |
|
20-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add an offset argument to constant buffer setup.
We'll use this for UBO surfaces.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c37efbfe4c415b6fd2d4f968220d7c9b62f11ecf |
|
12-Jun-2012 |
Pauli Nieminen <pauli.nieminen@linux.intel.com> |
mesa: Move DepthMode to texture object
GL_DEPTH_TEXTURE_MODE isn't meant to be part of sampler state based on
compatibility profile specifications.
OpenGL specification 4.1 compatibility 20100725 3.9.2:
"... The values accepted in the pname parameter
are TEXTURE_WRAP_S, TEXTURE_WRAP_T, TEXTURE_WRAP_R, TEXTURE_MIN_-
FILTER, TEXTURE_MAG_FILTER, TEXTURE_BORDER_COLOR, TEXTURE_MIN_-
LOD, TEXTURE_MAX_LOD, TEXTURE_LOD_BIAS, TEXTURE_COMPARE_MODE, and
TEXTURE_COMPARE_FUNC. Texture state listed in table 6.25 but not listed here and
in the sampler state in table 6.26 is not part of the sampler state, and remains in the
texture object."
The list of states is in Table 6.24 "Textures (state per texture
object)" instead of 6.25 mentioned in the specification text.
Same can be found from 3.3 compatibility specification.
Signed-off-by: Pauli Nieminen <pauli.nieminen@linux.intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 97fc89c6cbaa3b5ef7f678d2dc2c7d5bbba05315 |
|
27-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Treat GL_SAMPLES=1 as equivalent to GL_SAMPLES=0.
EXT_framebuffer_multisample is a required subpart of
ARB_framebuffer_object, which means that we must support it even on
platforms that don't support MSAA. Fortunately
EXT_framebuffer_multisample allows for this by allowing GL_MAX_SAMPLES
to be set to 1.
This leads to a tricky quirk in the GL spec: since
GlRenderbufferStorageMultisamples() accepts any value for its
"samples" parameter up to and including GL_MAX_SAMPLES, that means
that on platforms that don't support MSAA, GL_SAMPLES is allowed to be
set to either 0 or 1. On platforms that do support MSAA, GL_SAMPLES=1
is not used; 0 means no MSAA, and 2 or higher means MSAA.
In other words, GL_SAMPLES needs to be interpreted as follows:
=0 no MSAA (possible on all platforms)
=1 no MSAA (only possible on platforms where MSAA unsupported)
>1 MSAA (only possible on platforms where MSAA supported)
This patch modifies all MSAA-related code to choose between
multisampling and single-sampling based on the condition (GL_SAMPLES >
1) instead of (GL_SAMPLES > 0) so that GL_SAMPLES=1 will be treated as
"no MSAA".
Note that since GL_SAMPLES=1 implies GL_SAMPLE_BUFFERS=1, we can no
longer use GL_SAMPLE_BUFFERS to distinguish between MSAA and non-MSAA
rendering.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 19bd5936af7278c0cce0728e8d6dec1a951eaf58 |
|
30-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_SKIP_DECODE_EXT on other SRGB formats.
Fixes some failures in getteximage-formats.
v2: Remove stray include, and drop extra test for encoding == GL_SRGB --
_mesa_get_srgb_format_linear() returns the same format if it wasn't SRGB.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48120
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f56dfc32134d65599159f53215713bf372c51a13 |
|
09-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Support MESA_FORMAT_SIGNED_RGBA_16.
The hardware supports this format with no known quirks, so we may as
well enable it.
Alpha blending is not supported until Sandybridge, but as far as I can
tell, OpenGL doesn't require alpha blending on SNORM formats. Plus, we
already expose R8G8B8A8_SNORM which has a similar restriction.
Fixes 6 piglit texwrap-2D-*SNORM* cases,
gl-3.1/required-sized-texture-formats, and 10 oglconform snorm-textures
subcases
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| cc44aa77490e1360b099eb0b887266f434298b4f |
|
21-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Remove unused param conversion code.
Ever since ctx->NativeIntegers was set, the conversion flag has been
PARAM_NO_CONVERT.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| bac43b8bb7ace5401a2cc0d92f416340344df1bd |
|
10-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Work around problems with null render targets on Gen6.
On Gen6, multisampled null render targets don't seem to work
properly--they cause the GPU to hang. So, as a workaround, we render
into a dummy color buffer.
Fortunately this situation (multisampled rendering without a color
buffer) is rare, and we don't have to waste too much memory, because
we can give the workaround buffer a very small pitch.
Fixes piglit test "EXT_framebuffer_multisample/no-color {2,4}
depth-computed *" on Gen6.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0aeb87023e64807734aee323e76f81796d525a36 |
|
13-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Set width, height, and tiling properly for null render targets.
The HW docs say that the width and height of null render targets need
to match the width and height of the corresponding depth and/or
stencil buffers, and that they need to be marked as Y-tiled. Although
leaving these values at 0 doesn't seem to cause any ill effects, it
seems wise to follow the documented requirements.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a5a34b153d494ad4374e7b2c8ea13b1073a887e2 |
|
19-Jun-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Enable GL_OES_compressed_ETC1_RGB8_texture
Enable it for all hardware.
No current hardware supports ETC1, so this patch implements it by
translating the ETC1 data to RGBX data during the call to
glCompressedTexImage2D(). For details, see the doxygen for
intel_mipmap_tree::wraps_etc1.
Passes the Piglit test spec/OES_compressed_ETC1_RGB8_texture/miptree and
the ETC1 test in the GLES2 conformance suite.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1bd4d456cdecf7bea55f4e3dac574af54efad994 |
|
04-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add an enum to describe MSAA layout.
From the Ivy Bridge PRM, Vol 1 Part 1, p112:
There are three types of multisampled surface layouts designated
as follows:
- IMS Interleaved Multisampled Surface
- CMS Compressed Mulitsampled Surface
- UMS Uncompressed Multisampled Surface
Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved. To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}. It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM. CMS layout is not yet used.
The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 02ebad900db4ef1ac42cbfb41b433919a4c857a2 |
|
05-Jul-2012 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Add offset field to miptree
This lets us specify an offset into the bo where the miptree starts,
which will let us set up a texture for a single plane in a planar buffer.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 14311ef3f2031307fb660328db14eb535da9a4fa |
|
09-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Re-enable rendering to SNORM formats.
Commit d73f6375f50b fixed the cause of the Piglit failure with
ARB_color_buffer_float fragment clamp modes. Now that it's fixed,
there's no reason to leave snorm format rendering disabled.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3b0279a69392a8fcc81ad462ca5623ec2a73f890 |
|
15-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Disable unsupported formats.
Due to hardware limitations, MSAA is unsupported on Gen6 for formats
containing >64 bits of data per pixel. From the Sandy Bridge PRM,
vol4 part1, p72 ("Surface Format"):
If Number of Multisamples is set to a value other than
MULTISAMPLECOUNT_1, this field cannot be set to the following
formats:
- any format with greater than 64 bits per element
- any compressed texture format (BC*)
- any YCRCB* format
Gen7 has a similar, but less stringent limitation: formats with >64
bits of data per pixel only support 4x MSAA.
This patch causes the unsupported formats to report
GL_FRAMEBUFFER_UNSUPPORTED.
Fixes piglit "multisample-formats" tests on Gen6.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| adbfc4a09a21a3a9c707833e21a712a1d3fff7bd |
|
01-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement texture buffer objects on Gen6.
Commit a07cf3397e332388d3599c83e50ac45511972890 added support for TBOs
on Gen7, but missed Gen6.
Passes piglit -t texture_buffer and oglconform's buffermapping
basic.read.texture tests.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 455ac562722f60ac9fb0c3d3c697fa339fa011ad |
|
08-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Properly handle sliced layout for Gen7.
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface. This is the only layout
available in Gen6. On Gen7 it is used for depth and stencil
surfaces only.
- Sliced, in which the surface is stored as a 2D array, with array
slice n containing all pixel data for sample n. On Gen7 this layout
is used for color surfaces.
The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.
This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode. It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 36e34134184e72532f2e6a2b9438f72284ac3057 |
|
27-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Expose surface setup internals for use by blits.
This patch exposes the functions brw_get_surface_tiling_bits and
gen7_set_surface_tiling, so that they can be re-used when setting up
surface states in gen6_blorp.cpp and gen7_blorp.cpp.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| fcd57280ae687d6b7c11cb8ac8fb8cc4f01a646d |
|
23-Apr-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add a comment about the state flag for sRGBEnabled.
I thought this might be _NEW_COLOR, but it isn't.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| fd0082c47ecf1028bbb9e1e0dbc20173a3174772 |
|
24-Apr-2012 |
Sean V Kelley <sean.v.kelley@linux.intel.com> |
i965: Support Android RGBX8888 format for EGL generated images
Enabled MESA_FORMAT_RGBX8888_REV for RGBX. Android software
requires RGBX8888 format to be supported for software rendering.
That requires EGL to be capable of generating images from this
format.
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4f96e9830fa316fd1dacd6068c1f0e79a56ba038 |
|
19-Apr-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename BRW_MAX_SURFACES to BRW_MAX_WM_SURFACES.
Now that we use separate binding tables for WM, VS, and GS, and have
BRW_MAX_VS_SURFACES and BRW_MAX_GS_SURFACES macros, we really shouldn't
have an unqualified BRW_MAX_SURFACES macro. It's confusing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| dd32df3829317105adbfacc7fe7b1d2a2dc96a58 |
|
01-Apr-2012 |
Dylan Noblesmith <nobled@dreamwidth.org> |
i965: fix typo
Noticed by clang:
brw_wm_surface_state.c:330:30: warning: initializer overrides prior
initialization of this subobject [-Winitializer-overrides]
[MESA_FORMAT_Z24_S8] = 0,
^
brw_wm_surface_state.c:326:30: note: previous initialization is here
[MESA_FORMAT_Z24_S8] = 0,
^
No functionality change, since the array is declared static so
it was zero-initialized by default.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0b3729c987065883c6ff65a5c5288e852dd5b26a |
|
28-Mar-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add real support for texturing/rendering with MESA_FORMAT_RGBA8888_REV.
This was hacked in in one place for EGL image stuff, but the right
thing to do was just to provide the mapping from the mesa format to
the native hardware format, which includes render target support.
This turns out to be required for GL_ARB_texture_buffer_object, which
sees data in this layout.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5a7942c2f1e3af4daedd92c1ddf21fa6a0e4e752 |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Rename the original binding table to mention that it's the WM now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 07e00b3040d6da381595c65db5afe597f20d99fc |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Split the VS binding table to a separate table.
This is a step toward making the samplers/binding tables reflect
sampler uniform mappings instead of embedding those in the programs.
No significant performance difference on the microbenchmark (n=10).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e2dce7f7ee3e7da9cbb0bb33307ecd79e824426d |
|
10-Feb-2012 |
Eric Anholt <eric@anholt.net> |
intel: Fix rendering from textures after RenderTexture().
There's a serious trap for drivers: RenderTexture() does not indicate
that the texture is currently bound to the draw buffer, despite
FinishRenderTexture() signaling that the texture is just now being
unbound from the draw buffer.
We were acting as if RenderTexture() *was* the start of rendering and
that we could make texturing incoherent with the current contents of
the renderbuffer. This caused intel oglconform sRGB
Mipmap.1D_textures to fail, because we got a call to TexImage() and
thus RenderTexture() on a texture bound to a framebuffer that wasn't
the draw buffer, so we skipped validating the new image into the
texture object used for rendering.
We can't (easily) make RenderTexture() indicate the start of drawing,
because both our driver and gallium are using it as the moment to set
up the renderbuffer wrapper used for things like MapRenderbuffer().
Instead, postpone the setup of the workaround render target miptree
until update_renderbuffer time, so that we no longer need to skip
validation of miptrees used as render targets. As a bonus, this
should make GL_NV_texture_barrier possible.
(This also fixes a regression in the gen4 small-mipmap rendering since
3b38b33c1648b07e75dc4d8340758171e109c598, which switched
set_draw_offset from image->mt to irb->mt but didn't move the irb->mt
replacement up before set_draw_offset).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44961
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3a8cf3357abb50d4ee11cfb801f965e3df7592fb |
|
25-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965: Don't allow rendering to non-GL_RED/RG/RGBA integer textures.
Fixes piglit EXT_texture_integer/fbo-blending.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 796f44d77906342e5912e7da6bdba1ba86bab9f0 |
|
20-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Pass the gl_renderbuffer to render_target_supported() vtable method.
I'm going to want to go looking at it for an integer texture fix.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6bc08ee56991ac3ca0fa0728c3907835282332b8 |
|
24-Jan-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Fix segfault in transform feedback to DYNAMIC_DRAW buffers.
When storing data in a buffer of type DYNAMIC_DRAW, we don't create a
drm_intel_bo for it; instead we store the data in system memory and
defer allocation of the GPU buffer until it is needed. Therefore, in
brw_update_sol_surface(), we can't just consult the "buffer" field of
the intel_buffer_object structure; we need to call
intel_bufferobj_buffer() to ensure that the deferred allocation
occurs.
This parallels a similar fix for gen7 (see commit ba6f4c9).
Fixes piglit test EXT_transform_feedback/buffer-usage on gen6.
This is a candidate for the 8.0 release branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 924de7dc96f4607cb3d833637b5f69f4b9e2a6d0 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: use intel_rb_format() to get renderbuffer format
This will make future changes cleaner and less invasive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2f868f1ddd636bc8d4cbcd5beeef1246cec80c65 |
|
18-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for Z16 depth formats.
v2: Don't flag the format as being HiZ ready (there's DRI2 handshake
pain to go through).
Fixes piglit gl-3.0-required-sized-texture-formats
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| fcd5af4a916b4ba7860ba27eb47404934bde0d08 |
|
10-Jan-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Set pitch of pull constant buffers to 16.
We always access pull constant buffers using the message types "OWord
Block Read" or "OWord Dual Block Read". According to the Sandy Bridge
PRM, Vol 4 Part 1, pages 214 and 218, when using these messages:
"the surface pitch is ignored, the surface is treated as a
1-dimensional surface. An element size (pitch) of 16 bytes is
used to determine the size of the buffer for out-of-bounds
checking if using the surface state model."
Previously we were setting the pitch for pull constant buffers to the
size of the whole constant buffer--this made no sense and would have
led to incorrect behavior if it were not for the fact that the pitch
is ignored.
For clarity, this patch sets the pitch for pull constant buffers to 16
bytes, consistent with the hardware's behavior.
v2: Clarify the meaning of the ignored values by writing them as (16 - 1).
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f6f43bd5a276990c58c021bc047e60f9763df479 |
|
09-Jan-2012 |
Paul Berry <stereotype441@gmail.com> |
i965 gen4-6: Fix off-by-one errors brw_create_constant_surface()
Commit 9bdc44a52804a64219a0ca1a061b18596863e524 (i965: Replace struct
with bit shifting for WM pull constant surfaces) accidentally
introduced off-by-one errors into the calculation of the surface
width, height, and depth. This patch restores the correct
computation.
The reason this wasn't noticed by Piglit tests is that the size of our
constant surfaces is always less than 2^20, therefore the off-by-one
error was causing the "depth" field of the surface to be set to all
1's. The hardware interpreted this as an extremely large surface, so
overflow checking was effectively disabled.
No Piglit regressions on Sandy Bridge.
NOTE: This is a candidate for the 7.11 and 8.0 branches.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7420c9dab4aaf87e6b840410226c296c4668a48f |
|
22-Dec-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Create mock implementation of GL_OES_EGL_image_external
In Android IceCreamSandwich, SurfaceFlinger requires GL_OES_image_external
for basic compositing tasks. Without the extension, SurfaceFlinger fails
to start.
Despite the incompleteness of the extension's implementation introduced by
this patch, it is good enough to enable SurfaceFlinger and to unblock the
people who need to begin testing Mesa on IceCreamSandwich.
To enable the extension, set the environment variable
MESA_EXTENSION_OVERRIDE="+GL_OES_EGL_image_external". Ideally, Android
should set this in init.rc.
WARNING: This implementation of GL_OES_EGL_image_external is not complete.
Some of it is even incorrect. When we begin to really implement
GL_OES_EGL_image_external, much of the patch will need reverting.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9cfa8a74ce484d5305b6581608b66b1cc53bc88b |
|
22-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Rename BRW_NEW_WM_SURFACES to BRW_NEW_SURFACES.
The surface states tracked by BRW_NEW_WM_SURFACES are no longer used
for just WM. They are also used for vertex texturing and transform
feedback. To avoid confusion, this patch renames BRW_NEW_WM_SURFACES
to BRW_NEW_SURFACES.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9308f298300beaa757194a0db8ed50924754c011 |
|
28-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Initial implementation of transform feedback.
This patch adds basic transform feedback capability for Gen6 hardware.
This consists of several related pieces of functionality:
(1) In gen6_sol.c, we set up binding table entries for use by
transform feedback. We use one binding table entry per transform
feedback varying (this allows us to avoid doing pointer arithmetic in
the shader, since we can set up the binding table entries with the
appropriate offsets and surface pitches to place each varying at the
correct address).
(2) In brw_context.c, we advertise the hardware capabilities, which
are as follows:
MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64
MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4
MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16
OpenGL 3.0 requires these values to be at least 64, 4, and 4,
respectively. The reason we advertise a larger value than required
for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already
set aside 64 binding table entries, so we might as well make them all
available in both separate attribs and interleaved modes.
(3) We set aside a single SVBI ("streamed vertex buffer index") for
use by transform feedback. The hardware supports four independent
SVBI's, but we only need one, since vertices are added to all
transform feedback buffers at the same rate. Note: at the moment this
index is reset to 0 only when the driver is initialized. It needs to
be reset to 0 whenever BeginTransformFeedback() is called, and
otherwise preserved.
(4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader
program to output transform feedback data as a side effect.
(5) In gen6_gs_state.c, we configure the geometry shader stage to
handle the SVBI pointer correctly.
Note: ordering of vertices is not yet correct for triangle strips
(alternate triangles are improperly oriented). This will be addressed
in a future patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 507e71e45a2e46c6e01423ab00948a72f435396c |
|
18-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_ARB_depth_buffer_float under 3.0 override.
This is not exposed generally yet because some of the swrast paths hit
in piglit (drawpixels, copypixels, blit) aren't yet converted to
MapRenderbuffer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e71fc6a8200cd78037a9788230ec0cc9f451a4b1 |
|
13-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use the miptree format for texture surface format choice.
With separate stencil GL_DEPTH32F_STENCIL8, the miptree will have a
really different format (MESA_FORMAT_Z32_FLOAT) from the teximage
(MESA_FORMAT_Z32_FLOAT_X24S8).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b4aecc4e1861e60e40e14868719219084967e46d |
|
01-Dec-2011 |
Brian Paul <brianp@vmware.com> |
mesa: rename MESA_FORMAT_RG88_REV to MESA_FORMAT_RG88
R is in the high byte, G in the low byte.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0a3c895f341ae458b09dcdc9cbd674600366a925 |
|
01-Dec-2011 |
Brian Paul <brianp@vmware.com> |
mesa: rename MESA_FORMAT_RG88 to MESA_FORMAT_GR88
To better reflect the component ordering and be consistent with other
format names.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d2235b0f4681f75d562131d655a6d7b7033d2d8b |
|
18-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Always handle GL_DEPTH_TEXTURE_MODE through the shader.
We were already doing it through the shader (layered underneath
GL_EXT_texture_swizzle) in the shadow compare case. This avoids
having per-format logic for switching out the surface format dependent
on the depth mode.
v2: Also do the swizzling for DEPTH_STENCIL. oops.
Reviewed-by: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f8b13ba1374bd4369ad85f7f2becec375f0b66ad |
|
16-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for ARGB2101010 rendering.
GL 3.0 specifies GL_RGB10_A2 as a required sized format for rendering
and texturing.
This introduces two piglit regressions: one due to fbo-mipmap-copypix
hitting swrast GetRow (we want to convert swrast to MapRenderbuffer),
and one due to fbo-blending-formats being too picky while leaving
dithering on.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b0a0f4bf14fbaa7df02db1d2057b287bfbea3347 |
|
16-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for RGBA_16 unorm rendering.
GL 3.0 specifies GL_RGBA16 as a required sized format for rendering
and texturing.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1e42568bf304e9b3bae9fef8ad8febd25e1ac29f |
|
16-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for half-float formats.
Now that all the rest of the driver is driven off of the surface
formats table, all we really need to do is add the mapping from
MESA_FORMAT to BRW_SURFACEFORMAT. However, we also add format
override for I16/L16 render targets at the same time, so that existing
users of I16 that were getting promoted to I32 and then getting the
I32->R32 override still get FBO support.
Fixes failures in piglit gl-3.0-required-sized-texture-formats, and
will prevent regressions in ARB_texture_float on gen4 when moving to
fully table-driven texture format setup.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2d159e6b365f039d9322b59e1538f3d42e8d8d8d |
|
16-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Reorganize MESA_FORMAT -> BRW_SURFACEFORMAT table.
This should be a no-op change. The initializers are reordered to
match the ordering of the enum, since there isn't a clearly sensible
ordering, but "the order they were added to the driver, sort of" is
definitely not one.
Also, the unsupported formats are explicitly initialized to 0, so it's
more obvious what we aren't claiming to support.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1b4910b3050729eabac15936ef701ef3acd4e70f |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Mark texture formats as supported using the surface formats table.
This is currently duplicated with intel_context.c's setup of the
formats table, and sets true for exactly the same set of formats on
gen6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ca10b2d4494798405a5fd654201291944645af5d |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use the surface format table to determine render target supportedness.
This moves any chipset-dependent logic we want for render target
format choices to init time as well. There is still logic left at
state update for SRGB handling, where format choices change based on
GL state.
The brw_render_target_supported() function should now return correct
results, instead of relying on the limited results from
intel_span_supports_format() to avoid lying about FBO completeness.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6661b7596f3b26a773ccde79f018179713b6b6e0 |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add the context to the render_target_supported() vtbl method.
We're going to want to provide different answers per chipset
generation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e589ebdf23342111587b9ebd0f0dcb2580a2dac2 |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a table of the surface format information from the PRM.
This will be used to drive chosing formats and determining framebuffer
completeness, instead of the bunch of ad-hoc checks we have had until
now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| dd0e46c4102976b7d317104ecd1bb565ac34613a |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965/gen6: Set vertical alignment in SURFACE_STATE batch
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| da2816a45e6e3a33246a341fee72e6f893f315d9 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_renderbuffer::region with a miptree [v3]
Essentially, this patch just globally substitutes `irb->region` with
`irb->mt->region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
v2:
- Return early in intel_process_dri2_buffer_*() if region allocation
fails.
- Fix double semicolon.
- Fix miptree reference leaks in the following functions:
intel_process_dri2_buffer_with_separate_stencil()
intel_image_target_renderbuffer_storage()
v3:
- [anholt] Fix check for hiz allocation failure. Replace
``if (!irb->mt)` with ``if(!irb->mt->hiz_region)``.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9ae10e9cbdfce6404a3d86188f2897d8f5d0dcb2 |
|
10-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make Gen6+ renderbuffer surface updates not depend on NEW_COLOR.
NEW_COLOR is only needed on Gen4-5 as brw_update_renderbuffer_surfaces
only uses ctx->Color when intel->gen < 6.
This should reduce unnecessary state updates.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e7c29c5de82f6de3d30ed1143d9672dd2e25f0e7 |
|
31-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use a single binding table for all pipeline stages.
Although the hardware supports separate binding tables for each pipeline
stage, we don't see much advantage over a single shared table.
Consider the contents of the binding table:
- Textures (16)
- Draw buffers (8)
- Pull constant buffers (1 for VS, 1 for WM)
OpenGL's texture bindings are global: the same set of textures is
available to all shader targets. So our binding table entries for
textures would be exactly the same in every table.
There are only two pull constant buffers (not many), and although draw
buffers aren't interesting to the VS, it shouldn't hurt to have them in
the table. The hardware supports up to 254 binding table entries, and
we currently only use 26.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4a42bd3931d6298ab9a84b76957ce5d83d289f69 |
|
02-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split brw_wm_surfaces state into renderbuffer and texture atoms.
First, the texturing setup code is relevant for all pipeline stages,
while renderbuffer surfaces are only used by the WM.
Secondly, renderbuffer and texture setup depends on a different set of
dirty bits. There's no reason to walk the array of textures when
changing draw buffers, or vice-versa.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a7d0fa209b444e3c7ad9358f1d31e3f638c20e40 |
|
02-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine the two WM pull constant tracked state atoms.
These were only split for historical reasons: brw_wm_constants used to
be the "prepare" step, while brw_wm_constant_surface was "emit". Now
that both happen at emit time, it makes sense to combine them.
Call the newly combined state atom "brw_wm_pull_constants" to indicate
help distinguish it from the Gen6+ atoms that handle push constants.
Finally, remove the BRW_NEW_WM_CONSTBUF dirty bit entirely now that it's
never flagged nor used.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e4b1c9b4bebd8f1fe851617e9ad350e45435e130 |
|
02-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove nr_surfaces computation from brw_update_wm_surfaces.
This code is fairly fragile, as it depends on the ordering of the
entries in the binding table, which will change soon.
Also, stop listening on the BRW_NEW_WM_CONSTBUF dirty bit as it's no
longer required.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6ba9090ea05e817bd38c1fcc63c53168b16593c7 |
|
01-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use 0 for the number of binding table entries in 3DSTATE_(VS|WM).
These fields control how many entries the hardware prefetches into the
state cache, so they only impact performance, not correctness. However,
it's not clear how to use this in a way that's beneficial.
According to the documentation, kernels "using a large number" of
entries may wish to program this to zero to avoid thrashing the cache;
it's unclear how many is too many. Also, Ironlake's WM was missing this
feature entirely---the count had to be zero.
The dirty bit tracking to handle this complicates the surface state
and binding table setup; removing it should simplify things and make
future refactoring easier. So just set 0 for the number of entries
rather than trying to compute and track it.
Appears to have no impact on Nexuiz and OpenArena on Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7c057f2360106488365e07af8055b4c696d855a3 |
|
08-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing CACHE_NEW_WM_PROG dirty bit to WM pull constants.
Comparing brw_upload_vs_pull_constants and brw_upload_wm_pull_constants,
it became evident that something was amiss: the VS code had both
CACHE_NEW_VS_PROG and BRW_NEW_VERTEX_PROGRAM, while the WM code was
missing the CACHE_NEW_WM_PROG flag.
Not observed to fix anything, but likely necessary.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c3e3903a9089043b280c461a72dab5158dc25d32 |
|
01-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use new vtable entries for surface state updating functions.
Now that we have vtable entries in place, we should use them. This
allows us to drop the cut and pasted Gen7 brw_tracked_state atoms as
they now do exactly the same thing as their brw_wm_surface_state
counterparts.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5d448b42b7143a1a38911b23d94b5c5d5bfa79f0 |
|
01-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add new vtable entries for surface state updating functions.
Gen7+ SURFACE_STATE is different from Gen4-6, so we need separate
per-generation functions for creating and updating it. However, the
usage is the same, and callers just want to utilize the appropriate
functions with minimal pain. So, put them in the vtable.
Since these take a brw_context pointer and are only used on Gen4, just
add a forward declaration. This is the simplest (if not cleanest)
solution. It would be nicer to have a i965-specific vtable, but that's
a refactor for another day.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 42c5552b0eef9c06898d29bb3f5c985f31316250 |
|
02-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Claim to support rendering to integer FBOs.
We're missing support for the software paths still, but basic
rendering is working.
v2: Override RGB_INT32/UINT32 to not be renderable, since the hardware
can't do it but we do allow texturing from it now. Drop the
DataType override, since the _mesa_problem() isn't in that path
any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 35be4ae77eb813bf6184699c038e82ad32bd267d |
|
05-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add mapping from MESA_FORMAT to BRW_SURFACEFORMAT for integer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e56aecf2492e3ca63ea70332a346f3f8414cba6c |
|
08-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for 16-bit unorm L, A, and I textures.
While not required by any particular spec version, mplayer was asking
for L16 and hoping for actual L16 without checking. The 8 bits
allocated led to 10-bit planar video data stored in the lower 10 bits
giving only 2 bits of precision in video. While it was an amusing
effect, give them what they actually wanted instead.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41461
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2b730c1f19ac1e15fa1b70c6cb3a3bd158e18ea1 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move WM pull constant setup to emit() time.
It's needed by the WM surface state setup, which is now emit().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 93cabff7d69a29b75e8f3143099edebf6e46bee7 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Fold WM surface state prepare()/emit() together.
These produce BRW_NEW_SURFACES (used by binding table emit()) and
BRW_NEW_NR_WM_SURFACES (used by WM unit emit()). Fixes a bug where
with no texturing and no color buffer, we wouldn't consider the null
renderbuffer in nr_surfaces. This was harmless because nr_surfaces is
only used for the prefetch info in the unit state.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| eaf4d3e6e2493a6e0b20d1205a5fb33ce500c9c2 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove the validated BO list, now that it's unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d646d069296982cfee14803fa882fdc4ff1b5abc |
|
04-Oct-2011 |
Brian Paul <brianp@vmware.com> |
i965: remove unneeded includes of texstore.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 669f1822d2a60865514faf37f9fde21e4567b3d2 |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_EXT_texture_array and GL_MESA_texture_array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| fd99cd0e10849205749aad580fea8c970fb46a31 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a helper function for getting miptree size from a texture image.
With 1D array textures, we no longer agree between the GL information
about width/height/depth of a texture and how we lay out a miptree.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8004a1cb95b8a195f3f4bbaa8d39d2f3297167de |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Rename region->buffer to region->bo, and remove accessor function.
We call all the other drm_intel_bo pointers in intel/*.h "bo", so this
one was rather out of place.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 03e623a27b95ef228fb4fca71c6d7c7a21630033 |
|
21-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_EXT_packed_float.
This doesn't cover support for this format as a renderbuffer yet. The
spec allows implementations to not support it, though it is something
we do want to support.
Only one failure in piglit on gen6, which is texwrap with bordercolor
(as usual).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2fd8c4e3edf989c6f7dd1261a67b01f06979feab |
|
21-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_EXT_texture_shared_exponent.
Only one failure in piglit on gen6, which is texwrap with bordercolor
(as usual).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2836aab2031d5b6926923fbc70f867ec638301bd |
|
09-Sep-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Use ColorLogicOpEnabled instead of _LogicOpEnabled
Since GL_EXT_blend_logic_op is removed, _LogicOpEnabled and
ColorLogicOpEnabled always have the same value.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9fe197c62611815ebe74248033271ad9fd07ae06 |
|
21-Aug-2011 |
Chia-I Wu <olv@lunarg.com> |
intel: add support for __DRI_IMAGE_FORMAT_ABGR8888
It maps to MESA_FORMAT_RGBA8888_REV. Surfaces of the format can only be
sampled from but not render to.
Only i915 is tested.
Reviewed-by: Eric Anholt <eric@anholt.net>
[olv: add a check in intel_image_target_renderbuffer_storage]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a070d5f363e99b0f846d555e9ca3a74ec807fdc0 |
|
04-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Start adding support for uniforms
There's no clever packing here, no pull constants, and no array support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d375df220fae47f38944c4832bcbd5f5d568884c |
|
23-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a type argument to brw_state_batch().
I want to make brw_state_dump.c handle more than just the last
statechange, so I want to keep track of what's in the batch state. By
using AUB file numbering for most of these packets, this may be
reusable for aub dumping.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0c27dcb75cf43bd58d32c3d5d580f0d3145e27d8 |
|
22-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Make the brw_format_for_mesa_format table static const.
Once again, assuming the compiler is clever works out so poorly. The
generated code initialized the structure on the stack, then did a
lookup into it. This was a performance regression from
70c6cd39bd9396b0d3f9e84df41fd8bef1f26cc4.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b17aab5753a6d14c9e757bedb186963b2dae8823 |
|
31-May-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move the draw_x/draw_y to the renderbuffer where it belongs.
It was originally located in the region because the tracking of
depth/color buffers was on the regions, and getting back to the irb
would have been tricky. Now, we're keying off of the renderbuffer in
more places, which means we can move these fields where they belong.
This could fix potential rendering failure with a single texture
having multiple images attached to different renderbuffers across
shareCtx (as far as I can tell, this was the only failure we could
cause, since anything else should trigger intel_render_texture in
between, for example a BindFramebuffer).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2abc8cae87b4cd037ebde68b4b9a1d02254657df |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
i965/brw: Emit state for hiz and separate stencil buffers
When emitting 3DSTATE_DEPTH_BUFFER, also emit 3DSTATE_HIER_DEPTH_BUFFER if
there is a hiz buffer. Ditto for 3DSTATE_STENCIL_BUFFER and a separate
stencil buffer.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e764f10ea557c9d819ad25bf1e700b1b3bd83277 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Replace struct with bit shifting for WM null surfaces.
Reduces compiled size of brw_wm_surface_state.o another 1.9%.
Overall, this brw_wm_surface_state reduction series cuts
firefox-talos-gfx runtime by 0.68% +/- 0.42% (n=6).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9bdc44a52804a64219a0ca1a061b18596863e524 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Replace struct with bit shifting for WM pull constant surfaces.
This reduces compiled size (4.7% of brw_wm_surface_state.o).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ac11c01ddeccf34230f363c0723783a1e2fce555 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Replace struct with bit shifting for WM render target surfaces.
This massively reduces compiled size (6.7% of brw_wm_surface_state.o).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ae5c1fceba383d13ab66f1c8db652bd98dfa4a26 |
|
28-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Replace structs with bitfield shifting for WM texture surfaces.
This massively reduces compiled size (4.9% of brw_wm_surface_state.o).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| bcbb1a536f7b6f00bbb164bd14d9f63102b9a8af |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop a gratuitous "if" that the compiler didn't eliminate at -O2.
Oddly, this increases compiled code size. (marking the 'if' as likely
also increases code size, but not as much).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d1946f53482a5a490a1da86d9bf9a3e2e866c0c4 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move prepare_wm_surfaces texobj declarations inside of _ReallyEnabled.
Interestingly, the compiler wasn't doing this for us at -O2, so we
were doing the computation for every non-_ReallyEnabled unit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3e43adef95ee24dd218279d2de56939b90edcb4c |
|
13-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for rendering to depthbuffer mipmap levels > 0.
Fixes
GL_ARB_depth_texture/fbo-clear-formats
GL_EXT_packed_depth_stencil/fbo-clear-formats
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4e98318fc1722171a07d867a99ab7608ecf758cd |
|
13-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Instead of fallback on missing region, just bind a null renderbuffer.
The change for GPU hanging in 13bab58f04c1ec6d0d52760eab490a0997d9abe2
fell back even when rb == NULL, which is wrong for GLES2 and caused
segfaulting in GLES2 conformance. For the GPU hang case (where the
broken 2D driver failed to allocate a BO for the window system
renderbuffer), it also would assertion fail/segfault immediately after
the fallback setup when the renderbuffer map failed.
Fixes GLES2 conformance packed_depth_stencil.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c12a93d5c452da16ff0c8955e55770b8eda28036 |
|
28-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Mark a few more brw_wm_surface_state functions as non-static.
I need to reuse them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 70c6cd39bd9396b0d3f9e84df41fd8bef1f26cc4 |
|
28-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Change brw_format_for_mesa_format to a non-static function.
This will make it easier to share between files.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e0e2c045965f7bd4becae3dce8394f8455184e0d |
|
22-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split BRW_NEW_BINDING_TABLE dirty bit into one per stage.
Ivybridge can update each stage's binding table pointer independently,
so we want separate dirty bits. Previous generations can simply
subscribe to all three dirty bits and emit as usual.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 530de3a2f5f6c1f1a6ec7a5f781d90f7229cab2a |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Give the push constants and pull constants unique function names.
This helps clarify profiling results.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1f32c665c8af0622e2bbf451edb999ffbcd7d0fe |
|
20-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_sampler_objects.
This extension support consists of replacing
"gl_texture_obj->Sampler." with "_mesa_get_samplerobj(ctx, unit)->".
One instance of referencing the texture's base sampler remains in the
initial miptree allocation, where I'm not sure we have a clear
association with any texture unit.
Tested with piglit ARB_sampler_objects/sampler-objects.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4093fdce6d7b8370bfe3ff5119dc0ef0acb32054 |
|
18-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for ARB_texture_compression_rgtc.
Tested with rgtc-teximage-0[12].
EXT_texture_compression_rgtc/fbo-generatemipmap-formats fails in NPOT
just like S3TC does.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 87478cd6e3e6349abc2688b390f8845d1e21af3d |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_texture_float.
For 1 and 2-channel formats the hardware only supports rendering to R
and RG. To do I and L render targets we just call them R and
everything works out. For A, we would need to rewrite the CC to do
the alpha channel's blending on color instead, and send the fragment
alpha down the red channel. For LA, there doesn't seem to be any
hope, because we can't do independent color/alpha blending while
treating the LA surface as RG.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ecfaab88b2577bd0395bc05d75a036126806a9c4 |
|
10-Apr-2011 |
Brian Paul <brianp@vmware.com> |
mesa: move sampler state into new gl_sampler_object type
gl_texture_object contains an instance of this type for the regular
texture object sampling state. glGenSamplers() generates new instances
of gl_sampler_object which can override that state with glBindSampler().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ad3fbac00bb4430aa26f4dbd3a795715b0fc7fef |
|
03-Apr-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Add the missing supportable EXT_texture_snorm formats
This class of hardware can natively sample all of the snorm surface
formats that DX10 requires, but it can't do some of the legacy GL
formats. In particular, all of the alpha, luminance, and intensity
formats are unsupported.
This partially fixes the breakage in glean's pixelFormats test since
GL_EXT_texture_snorm support was added to Mesa.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3f55683927278e57f3ef8a151d15f4cffdc060dc |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: drop state_bo references to batch_bo
As we use state relocations and we know that all the state belongs to
the same bo, we can drop the multiple references to the same bo.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1be3764dbe8d8ab2259c206a2158fe8f3c62c962 |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: directly write wm state to batch
As we write directly into the batch in system memory, we do not need to
write first to the stack (as was to avoid read back through the GTT)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 13bab58f04c1ec6d0d52760eab490a0997d9abe2 |
|
18-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Fallback on encountering a NULL render buffer
Following a GPU hang, or other error, the render target is not likely to
have an allocated BO and so we must fallback to avoid using it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32534
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 88ffa9ce5b8e5fe2b93238f8b9a7a888be28324e |
|
28-Jan-2011 |
Dave Airlie <airlied@gmail.com> |
mesa/965: add support for GL_EXT_framebuffer_sRGB (v2)
This adds i965 support for GL_EXT_framebuffer_sRGB, it introduces a new
constant to say that the driver can support sRGB enabled FBOs since enabling
the extension doesn't mean the driver can actually support sRGB.
Also adds the suggested state flush in the core code suggested by Brian.
fix the ARB_fbo color encoding.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9b1a15e1cb42247703422d1d25c7150214778f84 |
|
13-Jan-2011 |
Dave Airlie <airlied@gmail.com> |
i965: add support for EXT_texture_sRGB_decode
We just choose the texture format depending on the srgb decode bit
for the sRGB formats.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 483de8ef2eb9d4861c746dee750379529ea0ce0c |
|
13-Jan-2011 |
Dave Airlie <airlied@gmail.com> |
i965: fix fbo-srgb on i965.
Until we get the EXT_framebuffer_sRGB extension we should bind the sRGB
formats for FBO as linear.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5b3eb7538cd9ceb967b6e9e765896183e7c2c4d4 |
|
10-Jan-2011 |
Eric Anholt <eric@anholt.net> |
Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."
This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663.
This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa.
I was wrong about which generations supported baselevel adjustment --
it's just gen4, nothing earlier. This meant that i915 would have
never used the mag filter when baselevel != 0. Not a severe bug, but
not an intentional regression. I think we can fix the performance
issue another way.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a7bf7230564ac282cc957207224d16f322fa73d8 |
|
08-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a vtbl hook for determining if a format is renderable.
By relying on just intel_span_supports_format, some formats that
aren't supported pre-gen4 were not reporting FBO incomplete. And we
also complained in stderr when it happened on i915 because draw_region
gets called before framebuffer completeness validation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7ce6517f3ac41bf770ab39aba4509d4f535ef663 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Always allocate miptrees from level 0, not tObj->BaseLevel.
BaseLevel/MaxLevel are mostly used for two things: clamping texture
access for FBO rendering, and limiting the used mipmap levels when
incrementally loading textures. By restricting our mipmap trees to
just the current BaseLevel/MaxLevel, we caused reallocation thrashing
in the common case, for a theoretical win if someone really did want
just levels 2..4 or whatever of their texture object.
Bug #30366
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1b18b45d79e065e4e05a1e89e9d756d96258ded5 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Clarify first_level/last_level vs baselevel/maxlevel by deletion.
This has always been ugly about our texture code -- object base/max
level vs intel object first/last level vs image level vs miptree
first/last level. We now get rid of intelObj->first_level which is
just tObj->BaseLevel, and make intelObj->_MaxLevel clearly based off
of tObj->_MaxLevel instead of duplicating its code (incorrectly, as
image->MaxLog2 only considers width/height and not depth!)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 332a90e1015f0e1be4fb441e2d34e91f6bba812f |
|
05-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Simplify the renderbuffer setup code.
It was quite a mess by trying to do NULL renderbuffers and real
renderbuffers in the same function. This clarifies the common case of
real renderbuffers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 06cb1a6a5bdba5654408e3568584e1ab168266b7 |
|
05-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for SRGB DXT1 formats.
This makes
fbo-generatemipmap-formats GL_EXT_texture_sRGB-s3tc
match
fbo-generatemipmap-formats GL_EXT_texture_compression_s3tc
and swrast in bad DXT1_RGBA alpha=0 handling, but it means we won't
unpack and repack someone's textures into uncompressed SARGB8 format.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 783e7caadf945f176cb297b8791769e2855fc9ef |
|
10-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Put common info on converting MESA_FORMAT to BRW_FORMAT in a table.
There are exceptions to the table for depth texturing or rendering to
not-quite-supported formats thanks to the non-orthogonal component
selection for surface formats, but it's still a lot simpler.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3fb18d67753fec8a21461266246ff6949fc0fe81 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
intel: Set the swizzling for depth textures using the GL_RED depth mode.
Fixes depth-tex-modes-rg.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| cfcc2ef587fad91ad1dff1abbd42886dbe9cc095 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set render_cache_read_write surface state bit on gen6 constant surfs.
This is said to be required in the spec, even when you aren't doing writes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9e3641bd0d739a87a6998300ca29580cb557f380 |
|
25-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Make FS uniforms be the actual type of the uniform at upload time.
This fixes some insanity that would otherwise be required for GLSL
1.30 bit ops or gen6 integer uniform operations in general, at the
cost of upload-time pain. Given that we only have that pain because
mesa's mangling our integer uniforms to be floats, this something that
should be fixed outside of the shader codegen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 07cd8f46acc34b04308f81de2faf05ba33da264b |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for pull constants to the new FS backend.
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c77cd9ec10f7c6ad2927740e15900591d1ff388a |
|
20-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Enable GL_ARB_texture_rg
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1946b81e700fbb266294b8c1cb0d29ced84bf647 |
|
25-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for rendering to SARGB8 FBOs.
Tested with fbo-generatemipmap-formats GL_EXT_texture_srgb. The test
still fails on SLA8, though.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ca12aefdacd22fb42e3f1d3852db4c12de886554 |
|
24-Jun-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'shader-file-reorg'
1. Move all GL entrypoint functions and files into src/mesa/main/
This includes the ARB vp/vp, NV vp/fp, ATI fragshader and GLSL bits
that were in src/mesa/shader/
2. Move src/mesa/shader/slang/ to src/mesa/slang/ to reduce the tree depth
3. Rename src/mesa/shader/ to src/mesa/program/ since all the
remaining files are concerned with GPU programs.
4. Misc code refactoring. In particular, I got rid of most of the
GLSL-related ctx->Driver hook functions. None of the drivers used
them.
Conflicts:
src/mesa/drivers/dri/i965/brw_context.c
|
| 108264e859b4f435e9608472dc2e388aa200183c |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove the surface key used to generate constant surfaces.
We had to fill out all that junk when using the cache, but no more.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 34c82804edb1e9b11cf31be2246a9086694d35d6 |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Warning fixes from the i965-streaming merge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 27bc2de5461c1d66c8e005b35de77e7b9e214754 |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the state base address to avoid relocations.
This makes the binding table code simpler, and is required for gen6,
which requires binding table addresses to be under 64k offset from the
surface state base addr.
No significant change in performance on firefox-talos-gfx.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 178414eba402f9087ea505e7ef19f1becdd7a36d |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove caching of surface state objects.
It turns out that computing a 56 byte key to look up a 20-byte object
out of a hash table was some sort of a bad idea. Whoops.
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
after:
[ 0] gl firefox-talos-gfx 34.761 34.784 0.17% 5/6
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 73de09f265cb1c66d70fd9eb92021882bfbbbef6 |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Convert the binding table to streamed indirect state.
This slightly reduces reduces cairo-gl firefox-talos-gfx runtime on my
Ironlake:
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 38.236 38.383 0.43% 5/6
after:
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
It turns out the cost of caching these objects and looking them up in
the cache again is greater than the cost of just computing the object
again, particularly when the overhead of having a separate BO to pin
is removed.
(Those that are paying close attention will note that this is a
reversal of the path I was moving the driver in a couple of years ago.
The major thing that has changed is that back then all state was
recomputed when we wrapped the streaming state buffer, including
recompiling our precious programs. Now, we're uncaching just the
objects that are cheap to compute, and retaining caching of expensive
objects)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 118a47623a11a374df371d52ed0294224e6a62dc |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Split constant buffer setup from its surface state/binding state.
This was bothering me when redoing the binding tables.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 638342858894293246400d95a90d153c7f66719a |
|
25-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_ALPHA framebuffer objects.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| df3c1a563f3d76b07ab82c7b230b0030452f36ff |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.
The new API makes so much more sense, I'd like to forget how the old
one worked.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 890b3c61e3b81d4c5623e452317e8faccea91de4 |
|
02-Jun-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Remove a leftover DRI1/DRI2 conditional
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b2e52e727849bd78f8600931261ae69c1b29d6a6 |
|
23-Apr-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix assertion for surface tile offset usage on Ironlake.
Fixes assertion failure in fbo-generatemipmap-npot.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 362c1bf75eb74de5b4655c481b74f79718ed4a34 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Replace mt->pitch with mt->region->pitch.
The pitch is not really an inherent part of the miptree, since it's
not part of any of the layout calculations, and it's dictated by the
libdrm-allocated region pitch now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a232cc59e3f8ac8462c23b1a83e0ba60b451e681 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove support for the DRI1 TFP extension.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 20952f0378247f69849b6e37a7374bc9c94437a0 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove the paths for making a const surface object for a NULL BO.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0b9932ffde3f7228288717302b43aa01df0b5fa0 |
|
03-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Update WM surface state setup for sandybridge's new BLEND_STATE.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ab53f710151d920286d0c92f93262fb468008051 |
|
26-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for EXT_draw_buffers2.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache.
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5a7c2a99a65399a59f54c6a0756c106c1ae048ff |
|
05-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix build after blind merge of mesa 7.7 by Brian.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5ac16495a2772886100789f04e1a7d65068e9a40 |
|
05-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
docs/relnotes.html
src/gallium/drivers/llvmpipe/lp_tex_sample_c.c
src/gallium/drivers/r300/r300_cs.h
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
src/mesa/main/enums.c
|
| 63610fae4f46361f2500577a83bf5ac6f9e8b0ac |
|
04-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the surface offset calculation for tiled buffers.
If we ever had a non-tile-aligned tiled renderbuffer, the math was all
off. Use the existing x,y coordinates instead of trying to
reconstruct them from an incorrectly-calculated offset value.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| fd5511d27fc44096117c47ab503fb5b47f993061 |
|
30-Dec-2009 |
Brian Paul <brianp@vmware.com> |
mesa: implement per-buffer color masking
This is part of the GL_EXT_draw_buffers2 extension and part of GL 3.0.
The ctx->Color.ColorMask field is now a 2-D array. Until drivers are
modified to support per-buffer color masking, they can just look at
the 0th color mask.
The new _mesa_ColorMaskIndexed() function will be called by
glColorMaskIndexedEXT() or glColorMaski().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0b87f143c466f7e5bd730895ee29f1cd20a68f9b |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_G4X() across the driver with context structure usage.
Saves ~2KB of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b90f7f3ad324b1e4c39e334cdeb9556c3eb808ab |
|
15-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Use current draw buffer instead of drawable visual to get alpha bits
Use the currently bound draw buffer instead of the visual from the
drawable used to create the context. This cause problems generating
mipmaps for an RGBA texture in an RGB context.
This fixes the failure in piglit's glsl-lod-bias test reported in bug #25614.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e624b77eb2d594cde053c73a530836e05227126a |
|
09-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Remove ARGB internal_format == GL_RGB hacks
Now that XRGB is supported, we don't need to hack around cases of an RGBA
format buffer with an internal format of GL_RGB.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| eadd9b8e16e3b1ad35fec54f780a0f94ac43988f |
|
09-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Fix handling of drawing to MESA_FORMAT_XRGB8888
It turns out that 965 and friends cannot actually render to an xRGB
surfaces. Instead, the surface has to be RGBA with writes to alpha
disabled and the blend function modified to always use 1.0 for
destination alpha.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3078bd136d6ee1d9ad16b4c834cad23b005304a4 |
|
08-Dec-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Axe intel_renderbuffer::texformat
Since the texformat branch merge, the value of intel_renderbuffer::texformat
is just a copy of gl_renderbuffer::Format.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| fdfbae3381553fc93202560abe3b41b4d543f0bf |
|
17-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Use MESA_FORMAT_AL1616 when appropriate
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| eb6a1f8a00596156cd7164838ef9e9a5b39e7254 |
|
10-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add a note explaining the data cache domain.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4a253431abf43a0638afb43605b44a8742b72a60 |
|
30-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: update intel_create_renderbuffer(format), add XRGB support
Pass a gl_format to intel_create_renderbuffer() instead of GLenum.
Add cases for MESA_FORMAT_XRGB8888 textures and renderbuffers.
However, we don't yet create any renderbuffers or textures with that
format. It seems the default alpha value is zero instead of one.
Need to investigate that first.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 198ec96d364dabd82952a451eeda7937db383f0d |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: define, use BRW_MAX_DRAW_BUFFERS
i965 might support more than 4 color draw buffers. But if not, this protects
from breakage if the Mesa limit is raised.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1f196b786d6bd0c6a5dbdc638574ff716cc3d4de |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'texformat-rework'
Conflicts:
src/mesa/drivers/dri/radeon/radeon_fbo.c
src/mesa/drivers/dri/s3v/s3v_tex.c
src/mesa/drivers/dri/s3v/s3v_xmesa.c
src/mesa/drivers/dri/trident/trident_context.c
src/mesa/main/debug.c
src/mesa/main/mipmap.c
src/mesa/main/texformat.c
src/mesa/main/texgetimage.c
|
| bfd51dc34d45ba584683c70b1f854a513d9104d3 |
|
08-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i965: Annotate _NEW_COLOR dependency for brw_update_renderbuffer_surface().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4bd70b5cff13039a4b0e0c554156fec06e3c3906 |
|
22-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: change parameter type to gl_format
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 15d2ef602461ca75e7160af46a2b5040742a91c9 |
|
13-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: remove unused var
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3e34a2a2b97e7c93955deedb7c12b73bccd6662d |
|
06-Oct-2009 |
Brian Paul <brianp@vmware.com> |
drivers: don't include texformat.h
And remove other unneeded #includes while we're at it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4182b58169c1c37833c590d00d0a6a52b2b55326 |
|
02-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use a little stack space to avoid a malloc in wm_get_binding_table.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1f7c914ad0beea8a29c1a171c7cd1a12f2efe0fa |
|
01-Oct-2009 |
Brian Paul <brianp@vmware.com> |
mesa: replace gl_texture_format with gl_format
Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum.
ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x.
gl_texture_format will go away next.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8b23755ce978247a92c00e390de2e459c0a9d5ad |
|
22-Sep-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove some dead metaops code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 5604b27b9326ac542069a49ed9650c4b0d3e939a |
|
09-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix relocation delta for WM surfaces.
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245.
Bug #23688
Bug #23254
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 15c0cc5cf4b75d60fa9a8469df34b487a8c0e376 |
|
07-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set NULL WM surfaces as tiled according to requirement by specs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ea6dab2537998d6910c04cd7bb68a79bee8fda68 |
|
05-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use the renderbuffer surface size instead of region size for WM surfaces.
For drawing to lower mipmap levels, the region size makes the renderbuffer
be the size of the lowest level, instead of the current level. On DRI1,
Brian previously found that the RB size was incorrect, so leave this broken
there.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0f328c90dbc893e15005f2ab441d309c1c176245 |
|
06-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fall back or appropriately adjust offsets of drawing to tiled regions.
3D rendering to tiled textures was being done with non-tile-aligned offsets.
The G4X hardware has fields to let us support it easily and correctly, while
the pre-G4X hardware requires a path full of suffering, so we just fall back.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f831d2d41b5551abcf61f19880bc96779c5efd51 |
|
06-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove the forced lack of caching for renderbuffer surface state.
This snuck in with the multi-draw-buffers commit, and is a major penalty
to performance. It doesn't appear to be required, as the only dependency
the surface BO has is on the state key (and if there's some other dependency,
it should just be in the key).
This brings openarena performance up to almost 2% faster than Mesa 7.4.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4cb87840ff7c99654a89f45c6a5a2a026a587a2f |
|
06-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove _NEW_PROGRAM from brw_wm_surfaces setup dependencies.
This was a leftover from the brw_wm_constant_buffer change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 71fb9d62ece0177183efd5bb955d1f3292cb4376 |
|
06-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Split WM constant buffer update from other WM surfaces.
This can avoid re-uploading constant data when it isn't necessary, and is
a step towards not updating other surfaces just because constants change.
It also brings the upload of the constant buffer next to the creation.
This brings openarena performance up another 4%, to 91% of the Mesa 7.4 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9490d86808300e5819941a40784e272c290e05ee |
|
05-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Disentangle VS constant surface state from WM surface state.
Also, only create VS surface state if there's a VS constant buffer to be
uploaded, and set the contents of the buffer at the same time as creation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d277547dc69c9004097afdc2ca56a7aed85c6f54 |
|
05-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Don't create constant buffers if they won't be used.
Really, the creation and upload of constants should be in the same place,
since they should only happen together, and a state flag should be
triggered by them so that we don't thrash state around so much for just
updating constants. But this still recovers openarena performance by
another 19%, leaving us 16% behind Mesa 7.4 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b9196c1fa39dd566c5d7ab340e353b77714edb5f |
|
01-May-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'const-buffer-changes'
Conflicts:
src/mesa/drivers/dri/i965/brw_curbe.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/i965/brw_wm_glsl.c
|
| 8374379572d1c541a804990bc926108360f67c02 |
|
23-Apr-2009 |
Eric Anholt <eric@anholt.net> |
i965: Support drawing to FBO cube faces other than positive X.
Also fixes drawing to 3D texture depth levels.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4843e54fc69daf379dea9899673b3df92b44049c |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: actually use the new, second surface state cache
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1dbab84e21cad81e971265db3dbc8dc6c344b340 |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: use _NEW_PROGRAM_CONSTANTS and always create new const buffers
When program constants change we create a new VS constant buffer
instead of re-using the old one. This allows us to have several
const buffers in flight with vertex rendering.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 927dc39de0aa3840b6e054128f49a6882771ab19 |
|
18-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: use region width, height in brw_update_renderbuffer_surface()
Fixes a regression from commit 2c30fd84dfa052949a117c78d932b58c1f88b446
seen with DRI1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2c30fd84dfa052949a117c78d932b58c1f88b446 |
|
10-Apr-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.
Also enable them all regardless of screen bpp, as 32 bpp what I've been
testing against, and haven't been able to detect any screen bpp-specific
troubles with them.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| cafea7528052624c8d3e4cd1c5b26a61bf04d1d0 |
|
14-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: checkpoint commit: VS constant buffers
Hook up a constant buffer, binding table, etc for the VS unit.
This will allow using large constant buffers with vertex shaders.
The new code is disabled at this time (use_const_buffer=FALSE).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 60ad4b0bf0919c9dfd23aaa54271a8f1e47ab843 |
|
10-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: clean-up in prepare_wm_surfaces()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 20f3497e4b6756e330f7b3f54e8acaa1d6c92052 |
|
10-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: re-org of some of the new constant buffer code
Plus, begin the new code for vertex shader const buffers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2078e6cf55e3068454df9d843618b412b6abb811 |
|
10-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: new SURF_INDEX_ macros
Used to map drawables, textures and constant buffers to surface binding
table indexes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 597cd5b94e4818679af1134d053541f3d2cfb80e |
|
01-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: check-point commit of new constant buffer support
Currently, shader constants are stored in the GRF (loaded from the CURBE
prior to shader execution). This severly limits the number of constants
and temps that we can support.
This new code will support (practically) unlimited size constant buffers
and free up registers in the GRF. We allocate a new buffer object for the
constants and read them with "Read" messages/instructions. When only a
small number of constants are used, we can still use the old method.
The code works for fragment shaders only (and is actually disabled) for now.
Need to do the same thing for vertex shaders and need to add the necessary
code-gen to fetch the constants which are referenced by the shader
instructions.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d5346a925c569d959eb9ebedda95fdddb9d5350c |
|
24-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: comments, clean-up in prepare_wm_surfaces()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a693a2998c996f063edec8a83a4f6a175f39c471 |
|
28-Mar-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: srgb texture fixes
i965 can either do SRGBA8_REV format or SARGB8 format, but not SRGBA8.
Could add SRGBA8_REV support to mesa, but simply use SARGB8 for now.
While here, also add true srgb luminance / luminance_alpha support -
unfortunately the published docs fail to mention which asics support
this, tested on g43 so assume this works on any g4x.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 79e2df63af4d231a1223887e79a819b3baac9a6c |
|
27-Mar-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: add support for signed rgba texture format
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 66175aac7609ad314f25fbdff0d3958af310dc24 |
|
18-Mar-2009 |
Eric Anholt <eric@anholt.net> |
Fix DRI2 accelerated EXT_texture_from_pixmap with GL_RGB format.
This requires upgrading the interface so that the argument to
glXBindTexImageEXT isn't just dropped on the floor. Note that this only
fixes the accelerated path on Intel, as Mesa's texture format support is
missing x8r8g8b8 support (right now, GL_RGB textures get uploaded as a8r8gb8,
but in this case we're not doing the upload so we can't really work around it
that way).
Fixes bugs with compositors trying to use shaders that use alpha channels, on
windows without a valid alpha channel. Bug #19910 and likely others as well.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3327cc64e7fdc13d3843ccb17763f68dd381185f |
|
12-Mar-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: add support for ATI_envmap_bumpmap
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| cdc63901df6af3b370935bd4997e3c9c4eb4b933 |
|
26-Feb-2009 |
root <root@i965.localnet.net> |
i965: rename draw_regions -> color_regions
Be a little more specific about what these are.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 078e8a61b2aa547c6794f586a5c8bfaa575bb066 |
|
19-Feb-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix render target read domains.
We were asking for something illegal (write_domain != 0 && read_domains !=
write_domain) because at the time of writing the region surfaces were used
for texturing occasionally as well, and we weren't really clear on the model
GEM was going to use.
This reliably triggered a kernel bug with domain handling, resulting in
oglconform mustpass.c failure. Of course, it only became visible after
01bc4d441fd6821ad9fc20d5e9544e4e587e4ff0 cleaned up some gratuitous flushing.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 773e9d47651149158e58916616235b26904c3665 |
|
20-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: check depth_mode in translate_tex_format() for MESA_FORMAT_S8_Z24
Note that I24X8 vs. A24X8 vs. L24X8 doesn't seem to make any difference
for texture/shadow compare, however.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1b3e3e6b841535b78ff4fa1d3861e9d8cdeff972 |
|
14-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: indentation fixes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e476acb1051ae1a7e5e2be35a89488a8e5b07ff4 |
|
28-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Add a new state flag BRW_NEW_NR_SURFACES instead of CACHE_NEW_SURFACE
The CACHE_NEW_SURFACE bit always gets spammed since we get many different
surface BOs per state emit, but the only consumer of it wanted to just know
how many surfaces were enabled.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| df6ae3f0a39f95cb1199ac16c98be2bf9a3bc96f |
|
01-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix overwriting of depth override for SetTexOffset.
Fixes black borders around windows in compiz. Bug #17233.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 0adfd1021035e90995a25ec5f20b736e55075d92 |
|
04-Sep-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: Fix depth_stencil texture.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9cc13eba3e58d5cbb905c51828b6b2743dc61290 |
|
25-Jul-2008 |
Dave Airlie <airlied@linux.ie> |
i965: fixup format for TFP zero copy
(cherry picked from commit 9bc9e0ecb0fb2069b2c123e665eb2118e358098f which
was lost in a merge)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ce61660ab90d2f80370e423e4cd40a51ff4c4902 |
|
25-Jul-2008 |
Dave Airlie <airlied@linux.ie> |
i965: make tex offset override work..
should fix fd.o 14441
(cherry-picked from commit d4244683a61f66cfb78408a37cf2587587847f96 which was
lost in a merge)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2e841880cfc1006a2818d4a8bfefd21136dc39a9 |
|
11-Jul-2008 |
Eric Anholt <eric@anholt.net> |
drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
|
11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| ab50ddaa9173ae108833db0edb209045788efc41 |
|
07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6e620162a1b235ade227368b87fa993e844d7077 |
|
22-Apr-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fix DEPTH_TEXTURE_MODE (bug #14220)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 7183ccaa9df1b5591e7aca926ce4ea5aab4ffc86 |
|
20-Mar-2008 |
Eric Anholt <eric@anholt.net> |
[965] Initialize region surface key structure padding.
Fixes valgrind warnings, and potential performance loss from cache misses.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| f94d317d7aea8043b179a0ba64308606375500d7 |
|
14-Mar-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: fix abort issue with shadowtex demo when use
DEPTH_STENCIL texture. (bug#14952).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| fcb7cb9e72ecac7c165a3a6ed7a033e2e6793a26 |
|
13-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] multiple rendering target support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| b39f15b88f4ef585f260db689294c12b1aee41f2 |
|
29-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Fix conditional sequencing to allow the frame_buffer_texobj case.
Previously the frame_buffer_texobj case would have been bound as a normal
texture, at best resulting in no surface data being associated with it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a04b632350e5d0e9994fc667afc59407a39da0ba |
|
10-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Add more cliprect modes to cover other meanings for batch emits.
The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:
- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
(copybuffers, clears).
All callers should now be fixed to use one of these states for any batchbuffer
emits. Thanks to Keith Whitwell for pointing out the failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 8abffada70fcd62e3c2dcbcdc6d00d258805326b |
|
03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert relocations to not be cleared out on buffer submit.
We have two consumers of relocations. One is static state buffers, which
want the same relocation every time. The other is the batchbuffer, which gets
thrown out immediately after submit. This lets us reduce repeated computation
for static state buffers, and clean up the code by moving relocations nearer
to where the state buffer is computed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| a95b48d55bdeed85df8b4fdd6699ef9f0d3c7a45 |
|
02-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert surface state to use a cache key instead of brw_cache_data.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 146030aad2c41eb8303935a13333c93fdc7c4a58 |
|
18-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Allow draw or depth regions to be NULL.
With FBOs, we end up wanting to do 3D metaops against one or the other without
having to find the other one to fill in if we're not going to draw to it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| d859a60dc3b8aa7d8405c5839a21850c0838f07f |
|
17-Dec-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: check NULL pointer
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 1daf5b3ad6460f33870b9f016a6615c5f1f8aa5e |
|
16-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Fully initialize the texture surface key data (padding around GLboolean)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| c0b4257aa9ba783674ccf7162799385734dff211 |
|
16-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Move to using shared texture management code.
This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support. It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3ecdae82d751f9f404d10332f030e3280949ce4e |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Remove dead code in upload_wm_surfaces.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| e34a183d870e393187b2c26e37ea1e900c2ab1f7 |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Move brw_surface_state stack allocation into the function using it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| db928291dcbda2a820dbb1668c43d2fb4266be7c |
|
10-Aug-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: roland's DXTn format texture patch(bug10347)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 6bf81a5edfa287a396f30188b107ff1761039f3f |
|
02-Aug-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
EXT_texture_sRGB support on i965
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 69337ed098bdf0def6820ccdb121b08c0e139085 |
|
31-Jul-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Use I16_UNORM instead of L16_UNORM (bug 11742)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 3cd06cf8c5ef6a27e36c584e12ba79ed8dacbf28 |
|
29-Nov-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add accelerated CopyPixels for non-overlapping, 1:1 blits.
Submitted by Gary Wong <gtw@gnu.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| afd244d4e8dc36895676c1b3bdbdba59f03a6962 |
|
21-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
use the requested internal texture format where possible
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 133f14168009393c5f396d218521625cb79b653f |
|
07-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Make sure bmBufferOffset is called for all active buffers every time
we render. Currenly requires that some state be re-examined after
every LOCK_HARDWARE().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|