Cross Reference: /art/compiler/optimizing/intrinsics

Lines Matching defs:in
5  * you may not use this file except in compliance with the License.
10  * Unless required by applicable law or agreed to in writing, software
84 // intrinsic) in an intrinsified call. This will copy the arguments
87 // Note: The actual parameters are required to be in the locations
116       DCHECK(out.IsRegister());  // TODO: Replace this when we support output in memory.
152   FpuRegister in  = locations->InAt(0).AsFpuRegister<FpuRegister>();
156     __ Dmfc1(out, in);
158     __ Mfc1(out, in);
188   GpuRegister in  = locations->InAt(0).AsRegister<GpuRegister>();
192     __ Dmtc1(in, out);
194     __ Mtc1(in, out);
226   GpuRegister in  = locations->InAt(0).AsRegister<GpuRegister>();
231       __ Dsbh(out, in);
235       __ Rotr(out, in, 16);
239       __ Dsbh(out, in);
278   GpuRegister in  = locations->InAt(0).AsRegister<GpuRegister>();
282     __ Dclz(out, in);
284     __ Clz(out, in);
309   Location in = locations->InAt(0);
313     __ Dsbh(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>());
318     __ Rotr(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>(), 16);
348   GpuRegister in  = locations->InAt(0).AsRegister<GpuRegister>();
352     __ Rotr(out, in, 16);
356     __ Dsbh(out, in);
391   GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
407   // machine instructions each for the values being used in this algorithm).
410   // For a 64-bit operand this can be performed in 24 instructions compared
413   // There are algorithms which are faster in the cases where very few
419     __ Srl(TMP, in, 1);
422     __ Subu(TMP, in, TMP);
436     __ Dsrl(TMP, in, 1);
439     __ Dsubu(TMP, in, TMP);
474   FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
478     __ AbsD(out, in);
480     __ AbsS(out, in);
510   GpuRegister in  = locations->InAt(0).AsRegister<GpuRegister>();
514     __ Dsra32(AT, in, 31);
515     __ Xor(out, in, AT);
518     __ Sra(AT, in, 31);
519     __ Xor(out, in, AT);
682     // first input register is needed to make sure that value in the
684     // computing the output value. The logic in the corresponding else
686     // register isn't clobbered in the event that it's the same register
765   FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
768   __ SqrtD(out, in);
788   FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
791   __ RintD(out, in);
814   FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
817   DCHECK_NE(in, out);
821   // double floor/ceil(double in) {
822   //     if in.isNaN || in.isInfinite || in.isZero {
823   //         return in;
825   __ ClassD(out, in);
828   __ MovD(out, in);
831   //     Long outLong = floor/ceil(in);
836   //         // be returned in these cases.
837   //         // There is also a small probability that floor(in)/ceil(in)
841   //         return in;
844     __ FloorLD(out, in);
846     __ CeilLD(out, in);
849   __ MovD(out, in);
881   FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
889   // out = floor(in);
892   //   TMP = ((in - out) >= 0.5) ? 1 : 0;
897   // out = floor(in);
899     __ FloorLD(FTMP, in);
902     __ FloorWS(FTMP, in);
927   // TMP = (0.5 <= (in - out)) ? -1 : 0;
931     __ SubD(FTMP, in, FTMP);
938     __ SubS(FTMP, in, FTMP);
1130     // path in InstructionCodeGeneratorMIPS64::GenerateReferenceLoadWithBakerReadBarrier.
1464   // Temporary register used in CAS by (Baker) read barrier.
1499       // Need to make sure the reference stored in the field is a to-space
1550                         // in the case that the store fails.  Whether the
1643     // No support for this odd case (String class is moveable, not in the boot image).
1727   // Assertions that must hold in order to compare strings 8 bytes at a time.
1751   // If loop does not result in returning false, we return true.
1926   FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
1930     __ ClassD(FTMP, in);
1932     __ ClassS(FTMP, in);
1976   // Check assumption that sizeof(Char) is 2 (used in scaling below).
1994   // Location of data in char array buffer.
2114   // Where is the length in the Array?
2189     // We have already checked in the LocationsBuilder for the constant case.
2205   // Check assumption that sizeof(Char) is 2 (used in scaling below).
2247   GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
2251     __ Dclz(TMP, in);
2255     __ Clz(TMP, in);
2259   // For either value of "type", when "in" is zero, "out" should also
2260   // be zero. Without this extra "and" operation, when "in" is zero,
2265   __ And(out, AT, in);
2291   GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
2295     __ Dsubu(TMP, ZERO, in);
2297     __ Subu(TMP, ZERO, in);
2299   __ And(out, TMP, in);
2343   FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
2344   DCHECK_EQ(in, F12);
2549       // Just embed the j.l.Integer in the code.
2557       // TODO: If we JIT, we could allocate the j.l.Integer now, and store it in the
2570     GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
2574     // Is (info.low <= in) && (in <= info.high)?
2575     __ Addiu32(out, in, -info.low);
2579     // This means that "in" is outside of the range [info.low, info.high].
2597     __ StoreToOffset(kStoreWord, in, out, info.value_offset);