Lines Matching refs:size
30 "Unexpected Mips pointer size.");
31 static_assert(kMipsPointerSize == PointerSize::k32, "Unexpected Mips pointer size.");
67 // generator to CodePosition() to record the buffer size.
68 // Instructions after which the buffer size is recorded cannot
139 size_t size = buffer_.Size();
146 if (ds_fsm_target_pcs_.size() != 0 && ds_fsm_target_pcs_.back() + sizeof(uint32_t) == size) {
149 return size;
199 size_t size = advances.size();
200 DCHECK_NE(size, 0u);
205 while (adjust_pos != number_of_delayed_adjust_pcs || late_emit_pos != size) {
209 size_t late_emit_pc = (late_emit_pos != size)
221 size_t end_pos = (entry + 1u == size) ? old_stream.size() : advances[entry + 1u].stream_pos;
231 for (size_t cnt = ds_fsm_target_pcs_.size(), i = 0; i < cnt; i++) {
237 for (size_t id = 0; id < branches_.size(); id++) {
678 void MipsAssembler::Ext(Register rd, Register rt, int pos, int size) {
680 CHECK(0 < size && size <= 32) << size;
681 CHECK(0 < pos + size && pos + size <= 32) << pos << " + " << size;
682 DsFsmInstr(EmitR(0x1f, rt, rd, static_cast<Register>(size - 1), pos, 0x00))
686 void MipsAssembler::Ins(Register rd, Register rt, int pos, int size) {
688 CHECK(0 < size && size <= 32) << size;
689 CHECK(0 < pos + size && pos + size <= 32) << pos << " + " << size;
690 DsFsmInstr(EmitR(0x1f, rt, rd, static_cast<Register>(pos + size - 1), pos, 0x04))
953 size_t size = buffer_.Size();
954 CHECK_GE(size, 2 * sizeof(uint32_t));
955 size_t pos1 = size - 2 * sizeof(uint32_t);
956 size_t pos2 = size - sizeof(uint32_t);
3308 // bump up the distance by a value larger than the max byte size of a composite branch.
3418 // Promote the short branch to long if the offset size is too small
3485 CHECK_LT(branch_id, branches_.size());
3490 CHECK_LT(branch_id, branches_.size());
3530 BindRelativeToPrecedingBranch(label, branches_.size(), bound_pc);
3555 while (last_branch_id_ != branches_.size()) {
3589 uint32_t branch_id = branches_.size() - 1;
3722 size_t size = buffer_.Size();
3723 CHECK_GE(size, sizeof(uint32_t));
3724 size -= sizeof(uint32_t);
3725 CHECK_EQ(buffer_.Load<uint32_t>(size), delay_slot_.instruction_);
3726 buffer_.Resize(size);
3779 Literal* MipsAssembler::NewLiteral(size_t size, const uint8_t* data) {
3780 DCHECK(size == 4u || size == 8u) << size;
3781 literals_.emplace_back(size, data);
3816 for (size_t i = 0, size = literal.GetSize(); i != size; ++i) {
3842 for (size_t cnt = table.GetData().size(), i = 0; i < cnt; i++) {
3886 // If this branch has been promoted and needs to expand in size,
3887 // relocate all branches by the expansion size.
3900 size_t branch_count = branches_.size();
3912 uint32_t size = end - branch.GetOldEndLocation();
3913 buffer_.Move(branch.GetEndLocation(), branch.GetOldEndLocation(), size);
4335 size_t size = buffer_.Size();
4336 CHECK_GE(size, 2 * sizeof(uint32_t));
4337 size_t pos1 = size - 2 * sizeof(uint32_t);
4338 size_t pos2 = size - sizeof(uint32_t);
4503 // operands that are machine word in size or smaller. For doubleword-sized
4596 // offset is dependant on the size of the data format df (10-bit offsets for ld.b,
4628 // Max int16_t that's a multiple of element size.
4630 // Max ld.df/st.df offset that's a multiple of element size.
4710 size_t size) {
4713 CHECK_EQ(0u, size) << dst;
4715 CHECK_EQ(kMipsWordSize, size) << dst;
4718 CHECK_EQ(kMipsDoublewordSize, size) << dst;
4721 if (size == kMipsWordSize) {
4724 CHECK_EQ(kMipsDoublewordSize, size) << dst;
4728 CHECK_EQ(kMipsDoublewordSize, size) << dst;
4765 // Increase frame to required size.
4772 for (int i = callee_save_regs.size() - 1; i >= 0; --i) {
4784 for (size_t i = 0; i < entry_spills.size(); ++i) {
4810 int stack_offset = frame_size - (callee_save_regs.size() * kFramePointerSize) - kFramePointerSize;
4811 for (size_t i = 0; i < callee_save_regs.size(); ++i) {
4826 // Decrease frame to required size.
4829 // Decrease frame to required size.
4860 void MipsAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) {
4863 CHECK_EQ(0u, size);
4865 CHECK_EQ(kMipsWordSize, size);
4868 CHECK_EQ(kMipsDoublewordSize, size);
4873 if (size == kMipsWordSize) {
4876 CHECK_EQ(kMipsDoublewordSize, size);
4880 CHECK_EQ(kMipsDoublewordSize, size);
4928 void MipsAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
4929 return EmitLoad(mdest, SP, src.Int32Value(), size);
4932 void MipsAssembler::LoadFromThread(ManagedRegister mdest, ThreadOffset32 src, size_t size) {
4933 return EmitLoad(mdest, S1, src.Int32Value(), size);
4966 void MipsAssembler::SignExtend(ManagedRegister /*mreg*/, size_t /*size*/) {
4970 void MipsAssembler::ZeroExtend(ManagedRegister /*mreg*/, size_t /*size*/) {
4974 void MipsAssembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) {
4983 if (size == kMipsWordSize) {
4986 CHECK_EQ(kMipsDoublewordSize, size);
5036 void MipsAssembler::Copy(FrameOffset dest, FrameOffset src, ManagedRegister mscratch, size_t size) {
5039 CHECK(size == kMipsWordSize || size == kMipsDoublewordSize) << size;
5040 if (size == kMipsWordSize) {
5043 } else if (size == kMipsDoublewordSize) {
5052 ManagedRegister mscratch, size_t size) {
5054 CHECK_EQ(size, kMipsWordSize);
5060 ManagedRegister mscratch, size_t size) {
5062 CHECK_EQ(size, kMipsWordSize);
5071 size_t size ATTRIBUTE_UNUSED) {
5077 ManagedRegister mscratch, size_t size) {
5078 CHECK_EQ(size, kMipsWordSize);
5089 size_t size ATTRIBUTE_UNUSED) {