Cross Reference: /art/compiler/utils/mips64/assembler

Lines Matching refs:fs
164 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd,
167   CHECK_NE(fs, kNoFpuRegister);
172                       static_cast<uint32_t>(fs) << kFsShift |
977 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
978   EmitFR(0x11, 0x10, ft, fs, fd, 0x0);
981 void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
982   EmitFR(0x11, 0x10, ft, fs, fd, 0x1);
985 void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
986   EmitFR(0x11, 0x10, ft, fs, fd, 0x2);
989 void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
990   EmitFR(0x11, 0x10, ft, fs, fd, 0x3);
993 void Mips64Assembler::AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
994   EmitFR(0x11, 0x11, ft, fs, fd, 0x0);
997 void Mips64Assembler::SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
998   EmitFR(0x11, 0x11, ft, fs, fd, 0x1);
1001 void Mips64Assembler::MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1002   EmitFR(0x11, 0x11, ft, fs, fd, 0x2);
1005 void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1006   EmitFR(0x11, 0x11, ft, fs, fd, 0x3);
1009 void Mips64Assembler::SqrtS(FpuRegister fd, FpuRegister fs) {
1010   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x4);
1013 void Mips64Assembler::SqrtD(FpuRegister fd, FpuRegister fs) {
1014   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x4);
1017 void Mips64Assembler::AbsS(FpuRegister fd, FpuRegister fs) {
1018   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x5);
1021 void Mips64Assembler::AbsD(FpuRegister fd, FpuRegister fs) {
1022   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x5);
1025 void Mips64Assembler::MovS(FpuRegister fd, FpuRegister fs) {
1026   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6);
1029 void Mips64Assembler::MovD(FpuRegister fd, FpuRegister fs) {
1030   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x6);
1033 void Mips64Assembler::NegS(FpuRegister fd, FpuRegister fs) {
1034   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x7);
1037 void Mips64Assembler::NegD(FpuRegister fd, FpuRegister fs) {
1038   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x7);
1041 void Mips64Assembler::RoundLS(FpuRegister fd, FpuRegister fs) {
1042   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x8);
1045 void Mips64Assembler::RoundLD(FpuRegister fd, FpuRegister fs) {
1046   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x8);
1049 void Mips64Assembler::RoundWS(FpuRegister fd, FpuRegister fs) {
1050   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xc);
1053 void Mips64Assembler::RoundWD(FpuRegister fd, FpuRegister fs) {
1054   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xc);
1057 void Mips64Assembler::TruncLS(FpuRegister fd, FpuRegister fs) {
1058   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x9);
1061 void Mips64Assembler::TruncLD(FpuRegister fd, FpuRegister fs) {
1062   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x9);
1065 void Mips64Assembler::TruncWS(FpuRegister fd, FpuRegister fs) {
1066   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xd);
1069 void Mips64Assembler::TruncWD(FpuRegister fd, FpuRegister fs) {
1070   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xd);
1073 void Mips64Assembler::CeilLS(FpuRegister fd, FpuRegister fs) {
1074   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xa);
1077 void Mips64Assembler::CeilLD(FpuRegister fd, FpuRegister fs) {
1078   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xa);
1081 void Mips64Assembler::CeilWS(FpuRegister fd, FpuRegister fs) {
1082   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xe);
1085 void Mips64Assembler::CeilWD(FpuRegister fd, FpuRegister fs) {
1086   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xe);
1089 void Mips64Assembler::FloorLS(FpuRegister fd, FpuRegister fs) {
1090   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xb);
1093 void Mips64Assembler::FloorLD(FpuRegister fd, FpuRegister fs) {
1094   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xb);
1097 void Mips64Assembler::FloorWS(FpuRegister fd, FpuRegister fs) {
1098   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0xf);
1101 void Mips64Assembler::FloorWD(FpuRegister fd, FpuRegister fs) {
1102   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0xf);
1105 void Mips64Assembler::SelS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1106   EmitFR(0x11, 0x10, ft, fs, fd, 0x10);
1109 void Mips64Assembler::SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1110   EmitFR(0x11, 0x11, ft, fs, fd, 0x10);
1113 void Mips64Assembler::SeleqzS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1114   EmitFR(0x11, 0x10, ft, fs, fd, 0x14);
1117 void Mips64Assembler::SeleqzD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1118   EmitFR(0x11, 0x11, ft, fs, fd, 0x14);
1121 void Mips64Assembler::SelnezS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1122   EmitFR(0x11, 0x10, ft, fs, fd, 0x17);
1125 void Mips64Assembler::SelnezD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1126   EmitFR(0x11, 0x11, ft, fs, fd, 0x17);
1129 void Mips64Assembler::RintS(FpuRegister fd, FpuRegister fs) {
1130   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1a);
1133 void Mips64Assembler::RintD(FpuRegister fd, FpuRegister fs) {
1134   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1a);
1137 void Mips64Assembler::ClassS(FpuRegister fd, FpuRegister fs) {
1138   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1b);
1141 void Mips64Assembler::ClassD(FpuRegister fd, FpuRegister fs) {
1142   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x1b);
1145 void Mips64Assembler::MinS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1146   EmitFR(0x11, 0x10, ft, fs, fd, 0x1c);
1149 void Mips64Assembler::MinD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1150   EmitFR(0x11, 0x11, ft, fs, fd, 0x1c);
1153 void Mips64Assembler::MaxS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1154   EmitFR(0x11, 0x10, ft, fs, fd, 0x1e);
1157 void Mips64Assembler::MaxD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1158   EmitFR(0x11, 0x11, ft, fs, fd, 0x1e);
1161 void Mips64Assembler::CmpUnS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1162   EmitFR(0x11, 0x14, ft, fs, fd, 0x01);
1165 void Mips64Assembler::CmpEqS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1166   EmitFR(0x11, 0x14, ft, fs, fd, 0x02);
1169 void Mips64Assembler::CmpUeqS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1170   EmitFR(0x11, 0x14, ft, fs, fd, 0x03);
1173 void Mips64Assembler::CmpLtS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1174   EmitFR(0x11, 0x14, ft, fs, fd, 0x04);
1177 void Mips64Assembler::CmpUltS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1178   EmitFR(0x11, 0x14, ft, fs, fd, 0x05);
1181 void Mips64Assembler::CmpLeS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1182   EmitFR(0x11, 0x14, ft, fs, fd, 0x06);
1185 void Mips64Assembler::CmpUleS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1186   EmitFR(0x11, 0x14, ft, fs, fd, 0x07);
1189 void Mips64Assembler::CmpOrS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1190   EmitFR(0x11, 0x14, ft, fs, fd, 0x11);
1193 void Mips64Assembler::CmpUneS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1194   EmitFR(0x11, 0x14, ft, fs, fd, 0x12);
1197 void Mips64Assembler::CmpNeS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1198   EmitFR(0x11, 0x14, ft, fs, fd, 0x13);
1201 void Mips64Assembler::CmpUnD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1202   EmitFR(0x11, 0x15, ft, fs, fd, 0x01);
1205 void Mips64Assembler::CmpEqD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1206   EmitFR(0x11, 0x15, ft, fs, fd, 0x02);
1209 void Mips64Assembler::CmpUeqD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1210   EmitFR(0x11, 0x15, ft, fs, fd, 0x03);
1213 void Mips64Assembler::CmpLtD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1214   EmitFR(0x11, 0x15, ft, fs, fd, 0x04);
1217 void Mips64Assembler::CmpUltD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1218   EmitFR(0x11, 0x15, ft, fs, fd, 0x05);
1221 void Mips64Assembler::CmpLeD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1222   EmitFR(0x11, 0x15, ft, fs, fd, 0x06);
1225 void Mips64Assembler::CmpUleD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1226   EmitFR(0x11, 0x15, ft, fs, fd, 0x07);
1229 void Mips64Assembler::CmpOrD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1230   EmitFR(0x11, 0x15, ft, fs, fd, 0x11);
1233 void Mips64Assembler::CmpUneD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1234   EmitFR(0x11, 0x15, ft, fs, fd, 0x12);
1237 void Mips64Assembler::CmpNeD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
1238   EmitFR(0x11, 0x15, ft, fs, fd, 0x13);
1241 void Mips64Assembler::Cvtsw(FpuRegister fd, FpuRegister fs) {
1242   EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x20);
1245 void Mips64Assembler::Cvtdw(FpuRegister fd, FpuRegister fs) {
1246   EmitFR(0x11, 0x14, static_cast<FpuRegister>(0), fs, fd, 0x21);
1249 void Mips64Assembler::Cvtsd(FpuRegister fd, FpuRegister fs) {
1250   EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), fs, fd, 0x20);
1253 void Mips64Assembler::Cvtds(FpuRegister fd, FpuRegister fs) {
1254   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x21);
1257 void Mips64Assembler::Cvtsl(FpuRegister fd, FpuRegister fs) {
1258   EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x20);
1261 void Mips64Assembler::Cvtdl(FpuRegister fd, FpuRegister fs) {
1262   EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x21);
1265 void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) {
1266   EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
1269 void Mips64Assembler::Mfhc1(GpuRegister rt, FpuRegister fs) {
1270   EmitFR(0x11, 0x03, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
1273 void Mips64Assembler::Mtc1(GpuRegister rt, FpuRegister fs) {
1274   EmitFR(0x11, 0x04, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
1277 void Mips64Assembler::Mthc1(GpuRegister rt, FpuRegister fs) {
1278   EmitFR(0x11, 0x07, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
1281 void Mips64Assembler::Dmfc1(GpuRegister rt, FpuRegister fs) {
1282   EmitFR(0x11, 0x01, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);
1285 void Mips64Assembler::Dmtc1(GpuRegister rt, FpuRegister fs) {
1286   EmitFR(0x11, 0x05, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0);