Lines Matching refs:s0
60 v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit).
3426 * "instr" line that specifies an instruction that performs "s0 = op w0".
3436 scvtf s0, w0 // d0<- op
3438 SET_VREG s0, w4 // vA<- d0
3492 * "instr" line that specifies an instruction that performs "s0 = op x0".
3501 scvtf s0, x0 // d0<- op
3503 SET_VREG s0, w4 // vA<- d0
3536 * "instr" line that specifies an instruction that performs "w0 = op s0".
3544 GET_VREG s0, w3
3546 fcvtzs w0, s0 // d0<- op
3559 * "instr" line that specifies an instruction that performs "x0 = op s0".
3566 GET_VREG s0, w3
3568 fcvtzs x0, s0 // d0<- op
3581 * "instr" line that specifies an instruction that performs "d0 = op s0".
3588 GET_VREG s0, w3
3590 fcvt d0, s0 // d0<- op
3647 * "instr" line that specifies an instruction that performs "s0 = op d0".
3656 fcvt s0, d0 // d0<- op
3658 SET_VREG s0, w4 // vA<- d0
4539 * form: <op> s0, s0, s1
4546 GET_VREG s0, w0
4547 fadd s0, s0, s1 // s0<- op
4551 SET_VREG s0, w1
4564 * form: <op> s0, s0, s1
4571 GET_VREG s0, w0
4572 fsub s0, s0, s1 // s0<- op
4576 SET_VREG s0, w1
4589 * form: <op> s0, s0, s1
4596 GET_VREG s0, w0
4597 fmul s0, s0, s1 // s0<- op
4601 SET_VREG s0, w1
4614 * form: <op> s0, s0, s1
4621 GET_VREG s0, w0
4622 fdiv s0, s0, s1 // s0<- op
4626 SET_VREG s0, w1
4640 * form: <op> s0, s0, s1
4647 GET_VREG s0, w0
4648 bl fmodf // s0<- op
4652 SET_VREG s0, w1
5566 * "s2 = s0 op s1".
5574 GET_VREG s0, w9
5575 fadd s2, s0, s1 // s2<- op
5590 * "s2 = s0 op s1".
5598 GET_VREG s0, w9
5599 fsub s2, s0, s1 // s2<- op
5614 * "s2 = s0 op s1".
5622 GET_VREG s0, w9
5623 fmul s2, s0, s1 // s2<- op
5638 * "s2 = s0 op s1".
5646 GET_VREG s0, w9
5647 fdiv s2, s0, s1 // s2<- op
5662 GET_VREG s0, w9
5667 SET_VREG s0, w9