Lines Matching defs:KillSrc

1872     unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode,
1892 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
1899 unsigned SrcReg, bool KillSrc) const {
1920 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1923 .addReg(SrcReg, getKillRegState(KillSrc))
1944 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1949 .addReg(SrcReg, getKillRegState(KillSrc));
1960 .addReg(SrcReg, getKillRegState(KillSrc))
1970 .addReg(SrcReg, getKillRegState(KillSrc));
1980 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1990 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1999 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
2009 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
2019 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
2028 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
2038 .addReg(SrcReg, getKillRegState(KillSrc));
2042 .addReg(SrcReg, getKillRegState(KillSrc))
2063 .addReg(SrcReg, getKillRegState(KillSrc));
2066 .addReg(SrcReg, getKillRegState(KillSrc));
2080 .addReg(SrcReg, getKillRegState(KillSrc));
2083 .addReg(SrcReg, getKillRegState(KillSrc));
2097 .addReg(SrcReg, getKillRegState(KillSrc));
2104 .addReg(SrcReg, getKillRegState(KillSrc));
2118 .addReg(SrcReg, getKillRegState(KillSrc));
2125 .addReg(SrcReg, getKillRegState(KillSrc));
2134 .addReg(SrcReg, getKillRegState(KillSrc));
2140 .addReg(SrcReg, getKillRegState(KillSrc));
2147 .addReg(SrcReg, getKillRegState(KillSrc));
2153 .addReg(SrcReg, getKillRegState(KillSrc));
2161 .addReg(SrcReg, getKillRegState(KillSrc))
2170 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));