Lines Matching defs:Br
318 bool fixupImmediateBr(ImmBranch &Br);
319 bool fixupConditionalBr(ImmBranch &Br);
320 bool fixupUnconditionalBr(ImmBranch &Br);
1675 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {
1676 MachineInstr *MI = Br.MI;
1680 if (isBBInRange(MI, DestBB, Br.MaxDisp))
1683 if (!Br.isCond)
1684 return fixupUnconditionalBr(Br);
1685 return fixupConditionalBr(Br);
1693 ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
1694 MachineInstr *MI = Br.MI;
1700 Br.MaxDisp = (1 << 21) * 2;
1716 ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
1717 MachineInstr *MI = Br.MI;
1741 BMI->getOpcode() == Br.UncondBr) {
1750 if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
1780 Br.MI = &MBB->back();
1783 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
1786 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1788 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1789 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1901 ImmBranch &Br = ImmBranches[i-1];
1902 unsigned Opcode = Br.MI->getOpcode();
1922 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1923 if (isBBInRange(Br.MI, DestBB, MaxOffs)) {
1924 DEBUG(dbgs() << "Shrink branch: " << *Br.MI);
1925 Br.MI->setDesc(TII->get(NewOpc));
1926 MachineBasicBlock *MBB = Br.MI->getParent();
1934 Opcode = Br.MI->getOpcode();
1940 if (!Br.MI->killsRegister(ARM::CPSR))
1945 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg);
1952 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1955 unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2;
1958 MachineBasicBlock::iterator CmpMI = Br.MI;
1959 if (CmpMI != Br.MI->getParent()->begin()) {
1967 MachineBasicBlock *MBB = Br.MI->getParent();
1968 DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI);
1970 BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
1971 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
1973 Br.MI->eraseFromParent();
1974 Br.MI = NewBR;