Lines Matching refs:RR
167 static bool getSubregMask(const BitTracker::RegisterRef &RR,
182 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI);
363 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
365 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
367 assert(RR.Sub == 0);
373 if (RR.Sub == 0) {
378 assert(RR.Sub == Hexagon::subreg_loreg || RR.Sub == Hexagon::subreg_hireg);
380 Begin = (RR.Sub == Hexagon::subreg_loreg ? 0 : 32);
850 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
851 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
853 auto *RC = MRI.getRegClass(RR.Reg);
854 if (RR.Sub == 0)
863 VerifySR(RR.Sub);
866 VerifySR(RR.Sub);
869 VerifySR(RR.Sub);
1207 BitTracker::RegisterRef RR = MI.getOperand(OpN);
1208 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI);
2090 BitTracker::RegisterRef RR(V.RefI.Reg, 0);
2093 RR.Sub = Hexagon::subreg_loreg;
2096 RR.Sub = Hexagon::subreg_hireg;
2104 .addReg(RR.Reg, 0, RR.Sub)