Lines Matching refs:v2i32
242 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
409 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
1268 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1269 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1309 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1310 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1311 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1746 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1925 promoteLdStType(MVT::v2i32, MVT::i64);
1977 MVT::v2i32, MVT::v1i64}) {
2372 } else if (VT.getSimpleVT() == MVT::v2i32) {
2420 // Try to generate COMBINE to build v2i32 vectors.
2421 if (VT.getSimpleVT() == MVT::v2i32) {
2625 else if (SVT == MVT::v2i32 && X == 1)