Lines Matching refs:ADDR_ASSERT
163 ADDR_ASSERT(!"Invalid pipe config");
734 ADDR_ASSERT(pTileInfo != NULL);
1251 ADDR_ASSERT(pIn->width == expPitch);
1261 ADDR_ASSERT(IsPow2(expPitch));
1383 ADDR_ASSERT(numSamples == 1);
1435 ADDR_ASSERT(!"This should be a Fusion");
1533 ADDR_ASSERT(bpp != 128);
1540 ADDR_ASSERT(numSamples == 4);
1849 ADDR_ASSERT(m_logicalBanks <= 16);
2020 ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1);
2023 ADDR_ASSERT(yBitToCheck <= 3);
2154 ADDR_ASSERT(pTileInfo->macroAspectRatio > 1)
2203 ADDR_ASSERT(!pIn->flags.pow2Pad || ((pIn->basePitch != 0) && IsPow2(pIn->basePitch)));
2235 ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
2256 ADDR_ASSERT(pOut->height != 0);
2351 ADDR_ASSERT(index < m_noOfEntries);
2424 ADDR_ASSERT(index < static_cast<INT_32>(m_noOfEntries));
2571 ADDR_ASSERT(noOfEntries <= TileTableSize);
2599 ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED);
2685 ADDR_ASSERT(numFrags <= 8);
2696 ADDR_ASSERT(numSamples >= 4);
2703 ADDR_ASSERT(numSamples >= 4);
2710 ADDR_ASSERT(numSamples == 16);
2725 ADDR_ASSERT(numSamples >= 4);
2732 ADDR_ASSERT(numSamples >= 4);
2739 ADDR_ASSERT(numSamples >= 16);
2813 ADDR_ASSERT(pIn->flags.prt == TRUE);