Lines Matching refs:inst
36 check_uniforms(const struct etna_inst *inst)
43 const struct etna_inst_src *src = &inst->src[i];
62 etna_assemble(uint32_t *out, const struct etna_inst *inst)
65 if (inst->imm && inst->src[2].use)
68 if (!check_uniforms(inst))
71 out[0] = VIV_ISA_WORD_0_OPCODE(inst->opcode) |
72 VIV_ISA_WORD_0_COND(inst->cond) |
73 COND(inst->sat, VIV_ISA_WORD_0_SAT) |
74 COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) |
75 VIV_ISA_WORD_0_DST_AMODE(inst->dst.amode) |
76 VIV_ISA_WORD_0_DST_REG(inst->dst.reg) |
77 VIV_ISA_WORD_0_DST_COMPS(inst->dst.comps) |
78 VIV_ISA_WORD_0_TEX_ID(inst->tex.id);
79 out[1] = VIV_ISA_WORD_1_TEX_AMODE(inst->tex.amode) |
80 VIV_ISA_WORD_1_TEX_SWIZ(inst->tex.swiz) |
81 COND(inst->src[0].use, VIV_ISA_WORD_1_SRC0_USE) |
82 VIV_ISA_WORD_1_SRC0_REG(inst->src[0].reg) |
83 COND(inst->type & 0x4, VIV_ISA_WORD_1_TYPE_BIT2) |
84 VIV_ISA_WORD_1_SRC0_SWIZ(inst->src[0].swiz) |
85 COND(inst->src[0].neg, VIV_ISA_WORD_1_SRC0_NEG) |
86 COND(inst->src[0].abs, VIV_ISA_WORD_1_SRC0_ABS);
87 out[2] = VIV_ISA_WORD_2_SRC0_AMODE(inst->src[0].amode) |
88 VIV_ISA_WORD_2_SRC0_RGROUP(inst->src[0].rgroup) |
89 COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) |
90 VIV_ISA_WORD_2_SRC1_REG(inst->src[1].reg) |
91 VIV_ISA_WORD_2_SRC1_SWIZ(inst->src[1].swiz) |
92 COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG) |
93 COND(inst->src[1].abs, VIV_ISA_WORD_2_SRC1_ABS) |
94 VIV_ISA_WORD_2_SRC1_AMODE(inst->src[1].amode) |
95 VIV_ISA_WORD_2_TYPE_BIT01(inst->type & 0x3);
96 out[3] = VIV_ISA_WORD_3_SRC1_RGROUP(inst->src[1].rgroup) |
97 COND(inst->src[2].use, VIV_ISA_WORD_3_SRC2_USE) |
98 VIV_ISA_WORD_3_SRC2_REG(inst->src[2].reg) |
99 VIV_ISA_WORD_3_SRC2_SWIZ(inst->src[2].swiz) |
100 COND(inst->src[2].neg, VIV_ISA_WORD_3_SRC2_NEG) |
101 COND(inst->src[2].abs, VIV_ISA_WORD_3_SRC2_ABS) |
102 VIV_ISA_WORD_3_SRC2_AMODE(inst->src[2].amode) |
103 VIV_ISA_WORD_3_SRC2_RGROUP(inst->src[2].rgroup);
104 out[3] |= VIV_ISA_WORD_3_SRC2_IMM(inst->imm);