Cross Reference: /external/valgrind/VEX/priv/guest_arm64

Lines Matching defs:iop
3401       IROp   iop  = Iop_INVALID;
3408             case BITS2(0,0): iop = mkSHL(ty); break;
3409             case BITS2(0,1): iop = mkSHR(ty); break;
3410             case BITS2(1,0): iop = mkSAR(ty); break;
3413          assign(res, binop(iop, mkexpr(srcL),
10438       IROp   iop = isU ? (isD ? Iop_I64UtoF64 : Iop_I32UtoF32)
10441       putQRegLO(dd, binop(iop, mkexpr(rm), getQRegLO(nn, tyI)));
12213       IROp   iop = isH ? Iop_Reverse16sIn32_x4 : Iop_Reverse8sIn32_x4;
12214       assign(res, unop(iop, getQReg128(nn)));
12786          IROp   iop = isU ? (isF64 ? Iop_I64UtoF64 : Iop_I32UtoF32)
12793                         binop(iop, mkexpr(rm), getQRegLane(nn, i, tyI)));
13812       IROp   iop = Iop_INVALID;
13815          case BITS4(0,0,0,0): nm = "fmul"; iop = mkMULF(ity); break;
13816          case BITS4(0,0,0,1): nm = "fdiv"; iop = mkDIVF(ity); break;
13817          case BITS4(0,0,1,0): nm = "fadd"; iop = mkADDF(ity); break;
13818          case BITS4(0,0,1,1): nm = "fsub"; iop = mkSUBF(ity); break;
13819          case BITS4(0,1,0,0): nm = "fmax"; iop = mkVecMAXF(ty+2); break;
13820          case BITS4(0,1,0,1): nm = "fmin"; iop = mkVecMINF(ty+2); break;
13821          case BITS4(0,1,1,0): nm = "fmaxnm"; iop = mkVecMAXF(ty+2); break; //!!
13822          case BITS4(0,1,1,1): nm = "fminnm"; iop = mkVecMINF(ty+2); break; //!!
13828          assign(res, triop(iop, mkexpr(mk_get_IR_rounding_mode()),
13834                              binop(iop, getQReg128(nn), getQReg128(mm))));
13844       IROp   iop  = mkMULF(ity);
13848                           triop(iop, mkexpr(mk_get_IR_rounding_mode()),
14176       IROp iop = iops[ix];
14179              (iop == Iop_F32toI32S && irrm == Irrm_ZERO)   /* FCVTZS Wd,Sn */
14180           || (iop == Iop_F32toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Sn */
14181           || (iop == Iop_F32toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Sn */
14182           || (iop == Iop_F32toI32S && irrm == Irrm_NEAREST)/* FCVT{A,N}S W,S */
14184           || (iop == Iop_F32toI32U && irrm == Irrm_ZERO)   /* FCVTZU Wd,Sn */
14185           || (iop == Iop_F32toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Sn */
14186           || (iop == Iop_F32toI32U && irrm == Irrm_PosINF) /* FCVTPU Wd,Sn */
14187           || (iop == Iop_F32toI32U && irrm == Irrm_NEAREST)/* FCVT{A,N}U W,S */
14189           || (iop == Iop_F32toI64S && irrm == Irrm_ZERO)   /* FCVTZS Xd,Sn */
14190           || (iop == Iop_F32toI64S && irrm == Irrm_NegINF) /* FCVTMS Xd,Sn */
14191           || (iop == Iop_F32toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Sn */
14192           || (iop == Iop_F32toI64S && irrm == Irrm_NEAREST)/* FCVT{A,N}S X,S */
14194           || (iop == Iop_F32toI64U && irrm == Irrm_ZERO)   /* FCVTZU Xd,Sn */
14195           || (iop == Iop_F32toI64U && irrm == Irrm_NegINF) /* FCVTMU Xd,Sn */
14196           || (iop == Iop_F32toI64U && irrm == Irrm_PosINF) /* FCVTPU Xd,Sn */
14197           || (iop == Iop_F32toI64U && irrm == Irrm_NEAREST)/* FCVT{A,N}U X,S */
14199           || (iop == Iop_F64toI32S && irrm == Irrm_ZERO)   /* FCVTZS Wd,Dn */
14200           || (iop == Iop_F64toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Dn */
14201           || (iop == Iop_F64toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Dn */
14202           || (iop == Iop_F64toI32S && irrm == Irrm_NEAREST)/* FCVT{A,N}S W,D */
14204           || (iop == Iop_F64toI32U && irrm == Irrm_ZERO)   /* FCVTZU Wd,Dn */
14205           || (iop == Iop_F64toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Dn */
14206           || (iop == Iop_F64toI32U && irrm == Irrm_PosINF) /* FCVTPU Wd,Dn */
14207           || (iop == Iop_F64toI32U && irrm == Irrm_NEAREST)/* FCVT{A,N}U W,D */
14209           || (iop == Iop_F64toI64S && irrm == Irrm_ZERO)   /* FCVTZS Xd,Dn */
14210           || (iop == Iop_F64toI64S && irrm == Irrm_NegINF) /* FCVTMS Xd,Dn */
14211           || (iop == Iop_F64toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Dn */
14212           || (iop == Iop_F64toI64S && irrm == Irrm_NEAREST)/* FCVT{A,N}S X,D */
14214           || (iop == Iop_F64toI64U && irrm == Irrm_ZERO)   /* FCVTZU Xd,Dn */
14215           || (iop == Iop_F64toI64U && irrm == Irrm_NegINF) /* FCVTMU Xd,Dn */
14216           || (iop == Iop_F64toI64U && irrm == Irrm_PosINF) /* FCVTPU Xd,Dn */
14217           || (iop == Iop_F64toI64U && irrm == Irrm_NEAREST)/* FCVT{A,N}U X,D */
14228       assign(dst, binop(iop, mkU32(irrm), mkexpr(src)));