Cross Reference: /external/valgrind/VEX/priv/guest_s390

Lines Matching refs:archreg
432 get_fpr_pair(UInt archreg)
434    IRExpr *high = get_fpr_dw0(archreg);
435    IRExpr *low  = get_fpr_dw0(archreg + 2);
442 put_fpr_pair(UInt archreg, IRExpr *expr)
447    put_fpr_dw0(archreg,     high);
448    put_fpr_dw0(archreg + 2, low);
455 get_dpr_pair(UInt archreg)
457    IRExpr *high = get_dpr_dw0(archreg);
458    IRExpr *low  = get_dpr_dw0(archreg + 2);
465 put_dpr_pair(UInt archreg, IRExpr *expr)
470    put_dpr_dw0(archreg,     high);
471    put_dpr_dw0(archreg + 2, low);
867 ar_offset(UInt archreg)
888    vassert(archreg < 16);
890    return offset[archreg];
896 ar_w0_offset(UInt archreg)
898    return ar_offset(archreg) + 0;
903 put_ar_w0(UInt archreg, IRExpr *expr)
907    stmt(IRStmt_Put(ar_w0_offset(archreg), expr));
912 get_ar_w0(UInt archreg)
914    return IRExpr_Get(ar_w0_offset(archreg), Ity_I32);
924 fpr_offset(UInt archreg)
945    vassert(archreg < 16);
947    return offset[archreg];
953 fpr_w0_offset(UInt archreg)
955    return fpr_offset(archreg) + 0;
960 put_fpr_w0(UInt archreg, IRExpr *expr)
964    stmt(IRStmt_Put(fpr_w0_offset(archreg), expr));
969 get_fpr_w0(UInt archreg)
971    return IRExpr_Get(fpr_w0_offset(archreg), Ity_F32);
976 fpr_dw0_offset(UInt archreg)
978    return fpr_offset(archreg) + 0;
983 put_fpr_dw0(UInt archreg, IRExpr *expr)
987    stmt(IRStmt_Put(fpr_dw0_offset(archreg), expr));
992 get_fpr_dw0(UInt archreg)
994    return IRExpr_Get(fpr_dw0_offset(archreg), Ity_F64);
999 put_dpr_w0(UInt archreg, IRExpr *expr)
1003    stmt(IRStmt_Put(fpr_w0_offset(archreg), expr));
1008 get_dpr_w0(UInt archreg)
1010    return IRExpr_Get(fpr_w0_offset(archreg), Ity_D32);
1015 put_dpr_dw0(UInt archreg, IRExpr *expr)
1019    stmt(IRStmt_Put(fpr_dw0_offset(archreg), expr));
1024 get_dpr_dw0(UInt archreg)
1026    return IRExpr_Get(fpr_dw0_offset(archreg), Ity_D64);
1035 gpr_offset(UInt archreg)
1056    vassert(archreg < 16);
1058    return offset[archreg];
1064 gpr_w0_offset(UInt archreg)
1066    return gpr_offset(archreg) + 0;
1071 put_gpr_w0(UInt archreg, IRExpr *expr)
1075    stmt(IRStmt_Put(gpr_w0_offset(archreg), expr));
1080 get_gpr_w0(UInt archreg)
1082    return IRExpr_Get(gpr_w0_offset(archreg), Ity_I32);
1087 gpr_dw0_offset(UInt archreg)
1089    return gpr_offset(archreg) + 0;
1094 put_gpr_dw0(UInt archreg, IRExpr *expr)
1098    stmt(IRStmt_Put(gpr_dw0_offset(archreg), expr));
1103 get_gpr_dw0(UInt archreg)
1105    return IRExpr_Get(gpr_dw0_offset(archreg), Ity_I64);
1110 gpr_hw1_offset(UInt archreg)
1112    return gpr_offset(archreg) + 2;
1117 put_gpr_hw1(UInt archreg, IRExpr *expr)
1121    stmt(IRStmt_Put(gpr_hw1_offset(archreg), expr));
1126 get_gpr_hw1(UInt archreg)
1128    return IRExpr_Get(gpr_hw1_offset(archreg), Ity_I16);
1133 gpr_b6_offset(UInt archreg)
1135    return gpr_offset(archreg) + 6;
1140 put_gpr_b6(UInt archreg, IRExpr *expr)
1144    stmt(IRStmt_Put(gpr_b6_offset(archreg), expr));
1149 get_gpr_b6(UInt archreg)
1151    return IRExpr_Get(gpr_b6_offset(archreg), Ity_I8);
1156 gpr_b3_offset(UInt archreg)
1158    return gpr_offset(archreg) + 3;
1163 put_gpr_b3(UInt archreg, IRExpr *expr)
1167    stmt(IRStmt_Put(gpr_b3_offset(archreg), expr));
1172 get_gpr_b3(UInt archreg)
1174    return IRExpr_Get(gpr_b3_offset(archreg), Ity_I8);
1179 gpr_b0_offset(UInt archreg)
1181    return gpr_offset(archreg) + 0;
1186 put_gpr_b0(UInt archreg, IRExpr *expr)
1190    stmt(IRStmt_Put(gpr_b0_offset(archreg), expr));
1195 get_gpr_b0(UInt archreg)
1197    return IRExpr_Get(gpr_b0_offset(archreg), Ity_I8);
1202 gpr_w1_offset(UInt archreg)
1204    return gpr_offset(archreg) + 4;
1209 put_gpr_w1(UInt archreg, IRExpr *expr)
1213    stmt(IRStmt_Put(gpr_w1_offset(archreg), expr));
1218 get_gpr_w1(UInt archreg)
1220    return IRExpr_Get(gpr_w1_offset(archreg), Ity_I32);
1225 gpr_hw3_offset(UInt archreg)
1227    return gpr_offset(archreg) + 6;
1232 put_gpr_hw3(UInt archreg, IRExpr *expr)
1236    stmt(IRStmt_Put(gpr_hw3_offset(archreg), expr));
1241 get_gpr_hw3(UInt archreg)
1243    return IRExpr_Get(gpr_hw3_offset(archreg), Ity_I16);
1248 gpr_b7_offset(UInt archreg)
1250    return gpr_offset(archreg) + 7;
1255 put_gpr_b7(UInt archreg, IRExpr *expr)
1259    stmt(IRStmt_Put(gpr_b7_offset(archreg), expr));
1264 get_gpr_b7(UInt archreg)
1266    return IRExpr_Get(gpr_b7_offset(archreg), Ity_I8);
1271 gpr_hw0_offset(UInt archreg)
1273    return gpr_offset(archreg) + 0;
1278 put_gpr_hw0(UInt archreg, IRExpr *expr)
1282    stmt(IRStmt_Put(gpr_hw0_offset(archreg), expr));
1287 get_gpr_hw0(UInt archreg)
1289    return IRExpr_Get(gpr_hw0_offset(archreg), Ity_I16);
1294 gpr_b4_offset(UInt archreg)
1296    return gpr_offset(archreg) + 4;
1301 put_gpr_b4(UInt archreg, IRExpr *expr)
1305    stmt(IRStmt_Put(gpr_b4_offset(archreg), expr));
1310 get_gpr_b4(UInt archreg)
1312    return IRExpr_Get(gpr_b4_offset(archreg), Ity_I8);
1317 gpr_b1_offset(UInt archreg)
1319    return gpr_offset(archreg) + 1;
1324 put_gpr_b1(UInt archreg, IRExpr *expr)
1328    stmt(IRStmt_Put(gpr_b1_offset(archreg), expr));
1333 get_gpr_b1(UInt archreg)
1335    return IRExpr_Get(gpr_b1_offset(archreg), Ity_I8);
1340 gpr_hw2_offset(UInt archreg)
1342    return gpr_offset(archreg) + 4;
1347 put_gpr_hw2(UInt archreg, IRExpr *expr)
1351    stmt(IRStmt_Put(gpr_hw2_offset(archreg), expr));
1356 get_gpr_hw2(UInt archreg)
1358    return IRExpr_Get(gpr_hw2_offset(archreg), Ity_I16);
1363 gpr_b5_offset(UInt archreg)
1365    return gpr_offset(archreg) + 5;
1370 put_gpr_b5(UInt archreg, IRExpr *expr)
1374    stmt(IRStmt_Put(gpr_b5_offset(archreg), expr));
1379 get_gpr_b5(UInt archreg)
1381    return IRExpr_Get(gpr_b5_offset(archreg), Ity_I8);
1386 gpr_b2_offset(UInt archreg)
1388    return gpr_offset(archreg) + 2;
1393 put_gpr_b2(UInt archreg, IRExpr *expr)
1397    stmt(IRStmt_Put(gpr_b2_offset(archreg), expr));
1402 get_gpr_b2(UInt archreg)
1404    return IRExpr_Get(gpr_b2_offset(archreg), Ity_I8);