Lines Matching refs:UInt
44 UInt arm_hwcaps = 0;
213 ARMAMode1* ARMAMode1_RRS ( HReg base, HReg index, UInt shift ) {
415 static UInt ROR32 ( UInt x, UInt sh ) {
480 ARMRI5* ARMRI5_I5 ( UInt imm5 ) {
533 ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 ) {
646 ARMNRS* mkARMNRS(ARMNRS_tag tag, HReg reg, UInt index)
1012 static const HChar* showARMNeonDataSize_wrk ( UInt size )
1051 UInt size;
1129 ARMInstr* ARMInstr_Imm32 ( HReg dst, UInt imm32 ) {
1426 UInt size, Bool Q ) {
1438 UInt size, Bool Q ) {
1450 UInt size, Bool Q ) {
1463 UInt size, Bool Q ) {
1495 UInt size, Bool Q ) {
1507 ARMInstr* ARMInstr_NShl64 ( HReg dst, HReg src, UInt amt )
1519 static Bool fitsIn8x4 ( UInt* u8, UInt* u4, UInt u )
1521 UInt i;
1534 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) {
1535 UInt u8, u4;
1672 (UInt)(i->ARMin.XDirect.dstGA & 0xFFFF));
1674 (UInt)((i->ARMin.XDirect.dstGA >> 16) & 0xFFFF));
1969 UInt size;
2780 static inline UInt iregEnc ( HReg r )
2782 UInt n;
2790 static inline UInt dregEnc ( HReg r )
2792 UInt n;
2800 static inline UInt fregEnc ( HReg r )
2802 UInt n;
2810 static inline UInt qregEnc ( HReg r )
2812 UInt n;
2840 (((((UInt)(zzx7)) & 0xF) << 28) | \
2846 (((((UInt)(zzx7)) & 0xF) << 28) | \
2852 (((((UInt)(zzx7)) & 0xF) << 28) | \
2858 (((((UInt)(zzx7)) & 0xF) << 28) | \
2864 (((((UInt)(zzx7)) & 0xF) << 28) | \
2871 (((((UInt)(zzx7)) & 0xF) << 28) | (((zzx6) & 0xF) << 24))
2877 static UInt skeletal_RI84 ( ARMRI84* ri )
2879 UInt instr;
2895 static UInt skeletal_RI5 ( ARMRI5* ri )
2897 UInt instr;
2899 UInt imm5 = ri->ARMri5.I5.imm5;
2913 static UInt* imm32_to_ireg ( UInt* p, Int rD, UInt imm32 )
2915 UInt instr;
2938 UInt lo16 = imm32 & 0xFFFF;
2939 UInt hi16 = (imm32 >> 16) & 0xFFFF;
2951 UInt imm, rot;
2952 UInt op = X1010;
2953 UInt rN = 0;
2995 static UInt* imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
2999 UInt lo16 = imm32 & 0xFFFF;
3000 UInt hi16 = (imm32 >> 16) & 0xFFFF;
3001 UInt instr;
3018 static Bool is_imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
3022 UInt lo16 = imm32 & 0xFFFF;
3023 UInt hi16 = (imm32 >> 16) & 0xFFFF;
3024 UInt i0, i1;
3038 static UInt* do_load_or_store32 ( UInt* p,
3039 Bool isLoad, UInt rD, ARMAMode1* am )
3043 UInt bB = 0;
3044 UInt bL = isLoad ? 1 : 0;
3046 UInt instr, bP;
3078 UInt* p = (UInt*)buf;
3085 UInt instr, subopc;
3086 UInt rD = iregEnc(i->ARMin.Alu.dst);
3087 UInt rN = iregEnc(i->ARMin.Alu.argL);
3113 UInt instr, subopc;
3114 UInt rD = iregEnc(i->ARMin.Shift.dst);
3115 UInt rM = iregEnc(i->ARMin.Shift.argL);
3130 UInt instr;
3131 UInt rDst = iregEnc(i->ARMin.Unary.dst);
3132 UInt rSrc = iregEnc(i->ARMin.Unary.src);
3144 UInt subopc = X1111; /* MVN */
3157 UInt instr = skeletal_RI84(i->ARMin.CmpOrTst.argR);
3158 UInt subopc = i->ARMin.CmpOrTst.isCmp ? X1010 : X1000;
3159 UInt SBZ = 0;
3167 UInt instr = skeletal_RI84(i->ARMin.Mov.src);
3168 UInt subopc = X1101; /* MOV */
3169 UInt SBZ = 0;
3177 p = imm32_to_ireg( (UInt*)p, iregEnc(i->ARMin.Imm32.dst),
3183 UInt bL, bB;
3203 UInt instr, bP;
3225 UInt bS = i->ARMin.LdSt16.signedLoad ? 1 : 0;
3226 UInt bL = i->ARMin.LdSt16.isLoad ? 1 : 0;
3233 UInt bP, imm8hi, imm8lo, instr;
3280 UInt bP, imm8hi, imm8lo, instr;
3312 UInt* ptmp = NULL;
3343 (UInt)(Addr)disp_cp_chain_me);
3352 UInt notCond = 1 ^ (UInt)i->ARMin.XDirect.cond;
3370 UInt* ptmp = NULL;
3390 p = imm32_to_ireg(p, /*r*/12, (UInt)(Addr)disp_cp_xindir);
3398 UInt notCond = 1 ^ (UInt)i->ARMin.XIndir.cond;
3408 UInt* ptmp = NULL;
3426 UInt trcval = 0;
3454 p = imm32_to_ireg(p, /*r*/12, (UInt)(Addr)disp_cp_xassisted);
3462 UInt notCond = 1 ^ (UInt)i->ARMin.XAssisted.cond;
3471 UInt instr = skeletal_RI84(i->ARMin.CMov.src);
3472 UInt subopc = X1101; /* MOV */
3473 UInt SBZ = 0;
3482 UInt instr;
3500 p = imm32_to_ireg( (UInt*)p,
3501 scratchNo, (UInt)i->ARMin.Call.target );
3523 UInt* pBefore = p;
3529 p = imm32_to_ireg( (UInt*)p,
3530 scratchNo, (UInt)i->ARMin.Call.target );
3539 UInt* pPreElse = p;
3618 UInt dD = dregEnc(i->ARMin.VLdStD.dD);
3619 UInt rN = iregEnc(i->ARMin.VLdStD.amode->reg);
3621 UInt off8 = simm11 >= 0 ? simm11 : ((UInt)(-simm11));
3622 UInt bU = simm11 >= 0 ? 1 : 0;
3623 UInt bL = i->ARMin.VLdStD.isLoad ? 1 : 0;
3624 UInt insn;
3634 UInt fD = fregEnc(i->ARMin.VLdStS.fD);
3635 UInt rN = iregEnc(i->ARMin.VLdStS.amode->reg);
3637 UInt off8 = simm11 >= 0 ? simm11 : ((UInt)(-simm11));
3638 UInt bU = simm11 >= 0 ? 1 : 0;
3639 UInt bL = i->ARMin.VLdStS.isLoad ? 1 : 0;
3640 UInt bD = fD & 1;
3641 UInt insn;
3651 UInt dN = dregEnc(i->ARMin.VAluD.argL);
3652 UInt dD = dregEnc(i->ARMin.VAluD.dst);
3653 UInt dM = dregEnc(i->ARMin.VAluD.argR);
3654 UInt pqrs = X1111; /* undefined */
3663 UInt bP = (pqrs >> 3) & 1;
3664 UInt bQ = (pqrs >> 2) & 1;
3665 UInt bR = (pqrs >> 1) & 1;
3666 UInt bS = (pqrs >> 0) & 1;
3667 UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,0,bQ,bR), dN, dD,
3673 UInt dN = fregEnc(i->ARMin.VAluS.argL);
3674 UInt dD = fregEnc(i->ARMin.VAluS.dst);
3675 UInt dM = fregEnc(i->ARMin.VAluS.argR);
3676 UInt bN = dN & 1;
3677 UInt bD = dD & 1;
3678 UInt bM = dM & 1;
3679 UInt pqrs = X1111; /* undefined */
3688 UInt bP = (pqrs >> 3) & 1;
3689 UInt bQ = (pqrs >> 2) & 1;
3690 UInt bR = (pqrs >> 1) & 1;
3691 UInt bS = (pqrs >> 0) & 1;
3692 UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,bD,bQ,bR),
3699 UInt dD = dregEnc(i->ARMin.VUnaryD.dst);
3700 UInt dM = dregEnc(i->ARMin.VUnaryD.src);
3701 UInt insn = 0;
3722 UInt fD = fregEnc(i->ARMin.VUnaryS.dst);
3723 UInt fM = fregEnc(i->ARMin.VUnaryS.src);
3724 UInt insn = 0;
3753 UInt dD = dregEnc(i->ARMin.VCmpD.argL);
3754 UInt dM = dregEnc(i->ARMin.VCmpD.argR);
3755 UInt insn = XXXXXXXX(0xE, X1110, X1011, X0100, dD, X1011, X0100, dM);
3761 UInt cc = (UInt)i->ARMin.VCMovD.cond;
3762 UInt dD = dregEnc(i->ARMin.VCMovD.dst);
3763 UInt dM = dregEnc(i->ARMin.VCMovD.src);
3765 UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM);
3770 UInt cc = (UInt)i->ARMin.VCMovS.cond;
3771 UInt fD = fregEnc(i->ARMin.VCMovS.dst);
3772 UInt fM = fregEnc(i->ARMin.VCMovS.src);
3774 UInt insn = XXXXXXXX(cc, X1110, BITS4(1,(fD & 1),1,1),
3782 UInt dD = dregEnc(i->ARMin.VCvtSD.dst);
3783 UInt fM = fregEnc(i->ARMin.VCvtSD.src);
3784 UInt insn = XXXXXXXX(0xE, X1110, X1011, X0111, dD, X1010,
3790 UInt fD = fregEnc(i->ARMin.VCvtSD.dst);
3791 UInt dM = dregEnc(i->ARMin.VCvtSD.src);
3792 UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1),
3800 UInt insn;
3801 UInt qD = qregEnc(i->ARMin.VXferQ.qD);
3802 UInt dHi = dregEnc(i->ARMin.VXferQ.dHi);
3803 UInt dLo = dregEnc(i->ARMin.VXferQ.dLo);
3816 UInt qDlo = 2 * qD + 0;
3817 UInt qDhi = 2 * qD + 1;
3840 UInt dD = dregEnc(i->ARMin.VXferD.dD);
3841 UInt rHi = iregEnc(i->ARMin.VXferD.rHi);
3842 UInt rLo = iregEnc(i->ARMin.VXferD.rLo);
3848 UInt insn
3856 UInt fD = fregEnc(i->ARMin.VXferS.fD);
3857 UInt rLo = iregEnc(i->ARMin.VXferS.rLo);
3863 UInt insn
3875 UInt regF = fregEnc(i->ARMin.VCvtID.src);
3876 UInt regD = dregEnc(i->ARMin.VCvtID.dst);
3877 UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD,
3885 UInt regF = fregEnc(i->ARMin.VCvtID.src);
3886 UInt regD = dregEnc(i->ARMin.VCvtID.dst);
3887 UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD,
3895 UInt regD = dregEnc(i->ARMin.VCvtID.src);
3896 UInt regF = fregEnc(i->ARMin.VCvtID.dst);
3897 UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1),
3905 UInt regD = dregEnc(i->ARMin.VCvtID.src);
3906 UInt regF = fregEnc(i->ARMin.VCvtID.dst);
3907 UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1),
3918 UInt rDst = (isF64 ? dregEnc : fregEnc)(i->ARMin.VRIntR.dst);
3919 UInt rSrc = (isF64 ? dregEnc : fregEnc)(i->ARMin.VRIntR.src);
3922 UInt D, Vd, M, Vm;
3942 UInt rDst = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.dst);
3943 UInt rSrcL = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.srcL);
3944 UInt rSrcR = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.srcR);
3947 UInt D, Vd, N, Vn, M, Vm;
3973 UInt iReg = iregEnc(i->ARMin.FPSCR.iReg);
3999 UInt regD = qregEnc(i->ARMin.NLdStQ.dQ) << 1;
4000 UInt regN, regM;
4001 UInt D = regD >> 4;
4002 UInt bL = i->ARMin.NLdStQ.isLoad ? 1 : 0;
4003 UInt insn;
4019 UInt regD = dregEnc(i->ARMin.NLdStD.dD);
4020 UInt regN, regM;
4021 UInt D = regD >> 4;
4022 UInt bL = i->ARMin.NLdStD.isLoad ? 1 : 0;
4023 UInt insn;
4039 UInt Q = i->ARMin.NUnaryS.Q ? 1 : 0;
4040 UInt regD, D;
4041 UInt regM, M;
4042 UInt size = i->ARMin.NUnaryS.size;
4043 UInt insn;
4044 UInt opc, opc1, opc2;
4198 UInt Q = i->ARMin.NUnary.Q ? 1 : 0;
4199 UInt regD = (hregClass(i->ARMin.NUnary.dst) == HRcVec128)
4202 UInt regM, M;
4203 UInt D = regD >> 4;
4204 UInt sz1 = i->ARMin.NUnary.size >> 1;
4205 UInt sz2 = i->ARMin.NUnary.size & 1;
4206 UInt sz = i->ARMin.NUnary.size;
4207 UInt insn;
4208 UInt F = 0; /* TODO: floating point EQZ ??? */
4414 UInt Q = i->ARMin.NDual.Q ? 1 : 0;
4415 UInt regD = (hregClass(i->ARMin.NDual.arg1) == HRcVec128)
4418 UInt regM = (hregClass(i->ARMin.NDual.arg2) == HRcVec128)
4421 UInt D = regD >> 4;
4422 UInt M = regM >> 4;
4423 UInt sz1 = i->ARMin.NDual.size >> 1;
4424 UInt sz2 = i->ARMin.NDual.size & 1;
4425 UInt insn;
4448 UInt Q = i->ARMin.NBinary.Q ? 1 : 0;
4449 UInt regD = (hregClass(i->ARMin.NBinary.dst) == HRcVec128)
4452 UInt regN = (hregClass(i->ARMin.NBinary.argL) == HRcVec128)
4455 UInt regM = (hregClass(i->ARMin.NBinary.argR) == HRcVec128)
4458 UInt sz1 = i->ARMin.NBinary.size >> 1;
4459 UInt sz2 = i->ARMin.NBinary.size & 1;
4460 UInt D = regD >> 4;
4461 UInt N = regN >> 4;
4462 UInt M = regM >> 4;
4463 UInt insn;
4674 UInt Q = i->ARMin.NShift.Q ? 1 : 0;
4675 UInt regD = (hregClass(i->ARMin.NShift.dst) == HRcVec128)
4678 UInt regM = (hregClass(i->ARMin.NShift.argL) == HRcVec128)
4681 UInt regN = (hregClass(i->ARMin.NShift.argR) == HRcVec128)
4684 UInt sz1 = i->ARMin.NShift.size >> 1;
4685 UInt sz2 = i->ARMin.NShift.size & 1;
4686 UInt D = regD >> 4;
4687 UInt N = regN >> 4;
4688 UInt M = regM >> 4;
4689 UInt insn;
4719 UInt amt = i->ARMin.NShl64.amt;
4723 UInt regD = dregEnc(regDreg);
4724 UInt regM = dregEnc(regMreg);
4725 UInt D = (regD >> 4) & 1;
4726 UInt Vd = regD & 0xF;
4727 UInt L = 1;
4728 UInt Q = 0; /* always 64-bit */
4729 UInt M = (regM >> 4) & 1;
4730 UInt Vm = regM & 0xF;
4731 UInt insn = XXXXXXXX(X1111,X0010, BITS4(1,D,(amt>>5)&1,(amt>>4)&1),
4737 UInt Q = (hregClass(i->ARMin.NeonImm.dst) == HRcVec128) ? 1 : 0;
4738 UInt regD = Q ? (qregEnc(i->ARMin.NeonImm.dst) << 1) :
4740 UInt D = regD >> 4;
4741 UInt imm = i->ARMin.NeonImm.imm->imm8;
4742 UInt tp = i->ARMin.NeonImm.imm->type;
4743 UInt j = imm >> 7;
4744 UInt imm3 = (imm >> 4) & 0x7;
4745 UInt imm4 = imm & 0xF;
4746 UInt cmode, op;
4747 UInt insn;
4785 UInt cc = (UInt)i->ARMin.NCMovQ.cond;
4786 UInt qM = qregEnc(i->ARMin.NCMovQ.src) << 1;
4787 UInt qD = qregEnc(i->ARMin.NCMovQ.dst) << 1;
4788 UInt vM = qM & 0xF;
4789 UInt vD = qD & 0xF;
4790 UInt M = (qM >> 4) & 1;
4791 UInt D = (qD >> 4) & 1;
4794 UInt insn = XXXXXXXX(cc ^ 1, 0xA, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0);
4803 UInt regD = iregEnc(i->ARMin.Add32.rD);
4804 UInt regN = iregEnc(i->ARMin.Add32.rN);
4805 UInt imm32 = i->ARMin.Add32.imm32;
4808 p = imm32_to_ireg((UInt *)p, regD, imm32);
4810 UInt insn = XXXXXXXX(0xE, 0, X1000, regN, regD, 0, 0, regD);
4825 UInt* p0 = p;
4912 UInt* p = (UInt*)place_to_chain;
4915 p, /*r*/12, (UInt)(Addr)disp_cp_chain_me_EXPECTED));
4949 static UInt shortCTR = 0; /* DO NOT MAKE NON-STATIC */
4962 UInt uimm24 = (UInt)(delta >> 2);
4963 UInt uimm24_shl8 = uimm24 << 8;
4972 p, /*r*/12, (UInt)(Addr)place_to_jump_to);
5006 UInt* p = (UInt*)place_to_unchain;
5011 p, /*r*/12, (UInt)(Addr)place_to_jump_to_EXPECTED)
5038 p, /*r*/12, (UInt)(Addr)disp_cp_chain_me);
5053 UInt* p = (UInt*)place_to_patch;
5062 imm32_to_ireg_EXACTLY2(p, /*r*/12, (UInt)(Addr)location_of_counter);