Cross Reference: /external/valgrind/none/tests/mips64/shift

Lines Matching refs:s0
27                TEST2("drotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
31                TEST2("drotr $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
40                TEST2("drotr32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
44                TEST2("drotr32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
52                TEST1("drotrv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
53                                              s0, s1, s2);
60                TEST2("dsll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
64                TEST2("dsll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
71                TEST2("dsll32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
75                TEST2("dsll32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
81                TEST1("dsllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
82                                             s0, s1, s2);
89                TEST2("dsra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
93                TEST2("dsra $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
100                TEST2("dsra32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
104                TEST2("dsra32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
110                TEST1("dsrav $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
111                                             s0, s1, s2);
118                TEST2("dsrl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
122                TEST2("dsrl $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
129                TEST2("dsrl32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
133                TEST2("dsrl32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
139                TEST1("dsrlv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
140                                             s0, s1, s2);
149                TEST2("rotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
163                TEST2("sll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
167                TEST2("sll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
173                TEST1("sllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
174                                            s0, s1, s2);
181                TEST2("sra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
193                TEST2("srl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);