Cross Reference: /external/vixl/src/aarch64/assembler-aarch64.cc

Lines Matching defs:operand
402                     const Operand& operand) {
403   AddSub(rd, rn, operand, LeaveFlags, ADD);
409                      const Operand& operand) {
410   AddSub(rd, rn, operand, SetFlags, ADD);
414 void Assembler::cmn(const Register& rn, const Operand& operand) {
416   adds(zr, rn, operand);
422                     const Operand& operand) {
423   AddSub(rd, rn, operand, LeaveFlags, SUB);
429                      const Operand& operand) {
430   AddSub(rd, rn, operand, SetFlags, SUB);
434 void Assembler::cmp(const Register& rn, const Operand& operand) {
436   subs(zr, rn, operand);
440 void Assembler::neg(const Register& rd, const Operand& operand) {
442   sub(rd, zr, operand);
446 void Assembler::negs(const Register& rd, const Operand& operand) {
448   subs(rd, zr, operand);
454                     const Operand& operand) {
455   AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
461                      const Operand& operand) {
462   AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
468                     const Operand& operand) {
469   AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
475                      const Operand& operand) {
476   AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
480 void Assembler::ngc(const Register& rd, const Operand& operand) {
482   sbc(rd, zr, operand);
486 void Assembler::ngcs(const Register& rd, const Operand& operand) {
488   sbcs(rd, zr, operand);
495                      const Operand& operand) {
496   Logical(rd, rn, operand, AND);
502                      const Operand& operand) {
503   Logical(rd, rn, operand, ANDS);
507 void Assembler::tst(const Register& rn, const Operand& operand) {
508   ands(AppropriateZeroRegFor(rn), rn, operand);
514                     const Operand& operand) {
515   Logical(rd, rn, operand, BIC);
521                      const Operand& operand) {
522   Logical(rd, rn, operand, BICS);
528                     const Operand& operand) {
529   Logical(rd, rn, operand, ORR);
535                     const Operand& operand) {
536   Logical(rd, rn, operand, ORN);
542                     const Operand& operand) {
543   Logical(rd, rn, operand, EOR);
549                     const Operand& operand) {
550   Logical(rd, rn, operand, EON);
712                      const Operand& operand,
715   ConditionalCompare(rn, operand, nzcv, cond, CCMN);
720                      const Operand& operand,
723   ConditionalCompare(rn, operand, nzcv, cond, CCMP);
2034   // second operand of zero. Otherwise, orr with first operand zr is
2044 void Assembler::mvn(const Register& rd, const Operand& operand) {
2045   orn(rd, AppropriateZeroRegFor(rd), operand);
3941                        const Operand& operand,
3945   if (operand.IsImmediate()) {
3946     int64_t immediate = operand.GetImmediate();
3951   } else if (operand.IsShiftedRegister()) {
3952     VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits());
3953     VIXL_ASSERT(operand.GetShift() != ROR);
3960     // or their 64-bit register equivalents, convert the operand from shifted to
3966                                operand.ToExtendedRegister(),
3970       DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
3973     VIXL_ASSERT(operand.IsExtendedRegister());
3974     DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
3981                                 const Operand& operand,
3985   VIXL_ASSERT(rd.GetSizeInBits() == operand.GetRegister().GetSizeInBits());
3986   VIXL_ASSERT(operand.IsShiftedRegister() && (operand.GetShiftAmount() == 0));
3987   Emit(SF(rd) | op | Flags(S) | Rm(operand.GetRegister()) | Rn(rn) | Rd(rd));
4010                         const Operand operand,
4013   if (operand.IsImmediate()) {
4014     int64_t immediate = operand.GetImmediate();
4036     VIXL_ASSERT(operand.IsShiftedRegister());
4037     VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits());
4039     DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
4059                                    const Operand& operand,
4064   if (operand.IsImmediate()) {
4065     int64_t immediate = operand.GetImmediate();
4070     VIXL_ASSERT(operand.IsShiftedRegister() && (operand.GetShiftAmount() == 0));
4071     ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.GetRegister());
4221                                         const Operand& operand,
4224   VIXL_ASSERT(operand.IsShiftedRegister());
4226               (rn.Is32Bits() && IsUint5(operand.GetShiftAmount())));
4227   Emit(SF(rd) | op | Flags(S) | ShiftDP(operand.GetShift()) |
4228        ImmDPShift(operand.GetShiftAmount()) | Rm(operand.GetRegister()) |
4235                                          const Operand& operand,
4239   Emit(SF(rd) | op | Flags(S) | Rm(operand.GetRegister()) |
4240        ExtendMode(operand.GetExtend()) |
4241        ImmExtendShift(operand.GetShiftAmount()) | dest_reg | RnSP(rn));